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drm/i915/selftests: Ignore autoincrementing timestamp on verfifying whitelists
[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / handlers.c
CommitLineData
12d14cc4
ZW		 1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39#include "i915_drv.h"
feddf6e8
ZW		 40#include "gvt.h"
41#include "i915_pvinfo.h"
12d14cc4 42
e39c5add
ZW		 43/* XXX FIXME i915 has changed PP_XXX definition */
44#define PCH_PP_STATUS _MMIO(0xc7200)
45#define PCH_PP_CONTROL _MMIO(0xc7204)
46#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48#define PCH_PP_DIVISOR _MMIO(0xc7210)
49
12d14cc4
ZW		 50unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51{
a61ac1e7
CW		 52 struct drm_i915_private *i915 = gvt->gt->i915;
53
54 if (IS_BROADWELL(i915))
12d14cc4 55 return D_BDW;
a61ac1e7 56 else if (IS_SKYLAKE(i915))
12d14cc4 57 return D_SKL;
a61ac1e7 58 else if (IS_KABYLAKE(i915))
e3476c00 59 return D_KBL;
a61ac1e7 60 else if (IS_BROXTON(i915))
2939db9e 61 return D_BXT;
a61ac1e7 62 else if (IS_COFFEELAKE(i915))
36520ed0 63 return D_CFL;
12d14cc4
ZW		 64
65 return 0;
66}
67
68bool intel_gvt_match_device(struct intel_gvt *gvt,
69 unsigned long device)
70{
71 return intel_gvt_get_device_type(gvt) & device;
72}
73
e39c5add
ZW		 74static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
75 void *p_data, unsigned int bytes)
76{
77 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
78}
79
80static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
81 void *p_data, unsigned int bytes)
82{
83 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
84}
85
65f9f6fe
CD		 86static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
87 unsigned int offset)
88{
89 struct intel_gvt_mmio_info *e;
90
91 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
92 if (e->offset == offset)
93 return e;
94 }
95 return NULL;
96}
97
12d14cc4 98static int new_mmio_info(struct intel_gvt *gvt,
56a78de5 99 u32 offset, u8 flags, u32 size,
12d14cc4 100 u32 addr_mask, u32 ro_mask, u32 device,
65f9f6fe 101 gvt_mmio_func read, gvt_mmio_func write)
12d14cc4
ZW		 102{
103 struct intel_gvt_mmio_info *info, *p;
104 u32 start, end, i;
105
106 if (!intel_gvt_match_device(gvt, device))
107 return 0;
108
109 if (WARN_ON(!IS_ALIGNED(offset, 4)))
110 return -EINVAL;
111
112 start = offset;
113 end = offset + size;
114
115 for (i = start; i < end; i += 4) {
116 info = kzalloc(sizeof(*info), GFP_KERNEL);
117 if (!info)
118 return -ENOMEM;
119
120 info->offset = i;
65f9f6fe 121 p = find_mmio_info(gvt, info->offset);
36ed7e97
JJC		 122 if (p) {
123 WARN(1, "dup mmio definition offset %x\n",
12d14cc4 124 info->offset);
36ed7e97
JJC		 125 kfree(info);
126
127 /* We return -EEXIST here to make GVT-g load fail.
128 * So duplicated MMIO can be found as soon as
129 * possible.
130 */
131 return -EEXIST;
132 }
d8d94ba3 133
4ec3dd89 134 info->ro_mask = ro_mask;
12d14cc4 135 info->device = device;
e39c5add
ZW		 136 info->read = read ? read : intel_vgpu_default_mmio_read;
137 info->write = write ? write : intel_vgpu_default_mmio_write;
12d14cc4
ZW		 138 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
139 INIT_HLIST_NODE(&info->node);
140 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
fbfd76c3 141 gvt->mmio.num_tracked_mmio++;
12d14cc4
ZW		 142 }
143 return 0;
144}
145
62a6a537 146/**
8fde4107 147 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
62a6a537
ZW		 148 * @gvt: a GVT device
149 * @offset: register offset
150 *
151 * Returns:
8fde4107 152 * The engine containing the offset within its mmio page.
62a6a537 153 */
8fde4107
CW		 154const struct intel_engine_cs *
155intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
28c4c6ca 156{
0fac21e7 157 struct intel_engine_cs *engine;
a61ac1e7 158 enum intel_engine_id id;
28c4c6ca 159
62a6a537 160 offset &= ~GENMASK(11, 0);
a61ac1e7 161 for_each_engine(engine, gvt->gt, id)
62a6a537 162 if (engine->mmio_base == offset)
8fde4107
CW		 163 return engine;
164
165 return NULL;
28c4c6ca
ZW		 166}
167
e39c5add
ZW		 168#define offset_to_fence_num(offset) \
169 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
170
171#define fence_num_to_offset(num) \
172 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
173
fd64be63 174
e011c6ce 175void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
fd64be63
MH		 176{
177 switch (reason) {
178 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
179 pr_err("Detected your guest driver doesn't support GVT-g.\n");
180 break;
a33fc7a0
MH		 181 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
182 pr_err("Graphics resource is not enough for the guest\n");
f745e9cc 183 break;
e011c6ce 184 case GVT_FAILSAFE_GUEST_ERR:
185 pr_err("GVT Internal error for the guest\n");
f745e9cc 186 break;
fd64be63
MH		 187 default:
188 break;
189 }
190 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
191 vgpu->failsafe = true;
192}
193
e39c5add
ZW		 194static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
195 unsigned int fence_num, void *p_data, unsigned int bytes)
196{
c39bca4e
ZW		 197 unsigned int max_fence = vgpu_fence_sz(vgpu);
198
199 if (fence_num >= max_fence) {
b99f514f
CD		 200 gvt_vgpu_err("access oob fence reg %d/%d\n",
201 fence_num, max_fence);
fd64be63
MH		 202
203 /* When guest access oob fence regs without access
204 * pv_info first, we treat guest not supporting GVT,
205 * and we will let vgpu enter failsafe mode.
206 */
d1be371d 207 if (!vgpu->pv_notified)
fd64be63
MH		 208 enter_failsafe_mode(vgpu,
209 GVT_FAILSAFE_UNSUPPORTED_GUEST);
d1be371d 210
e39c5add 211 memset(p_data, 0, bytes);
d1be371d 212 return -EINVAL;
e39c5add
ZW		 213 }
214 return 0;
215}
216
52ca14e6
CD		 217static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
218 unsigned int offset, void *p_data, unsigned int bytes)
219{
220 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
221
a61ac1e7 222 if (INTEL_GEN(vgpu->gvt->gt->i915) <= 10) {
52ca14e6
CD		 223 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
224 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
225 else if (!ips)
226 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
227 else {
228 /* All engines must be enabled together for vGPU,
229 * since we don't know which engine the ppgtt will
230 * bind to when shadowing.
231 */
232 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
233 ips);
234 return -EINVAL;
235 }
236 }
237
238 write_vreg(vgpu, offset, p_data, bytes);
239 return 0;
240}
241
e39c5add
ZW		 242static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
243 void *p_data, unsigned int bytes)
244{
245 int ret;
246
247 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
248 p_data, bytes);
249 if (ret)
250 return ret;
251 read_vreg(vgpu, off, p_data, bytes);
252 return 0;
253}
254
255static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
256 void *p_data, unsigned int bytes)
257{
a61ac1e7 258 struct intel_gvt *gvt = vgpu->gvt;
e39c5add
ZW		 259 unsigned int fence_num = offset_to_fence_num(off);
260 int ret;
261
262 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
263 if (ret)
264 return ret;
265 write_vreg(vgpu, off, p_data, bytes);
266
a61ac1e7 267 mmio_hw_access_pre(gvt->gt);
e39c5add
ZW		 268 intel_vgpu_write_fence(vgpu, fence_num,
269 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
a61ac1e7 270 mmio_hw_access_post(gvt->gt);
e39c5add
ZW		 271 return 0;
272}
273
274#define CALC_MODE_MASK_REG(old, new) \
275 (((new) & GENMASK(31, 16)) \
276 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
277 | ((new) & ((new) >> 16))))
278
279static int mul_force_wake_write(struct intel_vgpu *vgpu,
280 unsigned int offset, void *p_data, unsigned int bytes)
281{
282 u32 old, new;
2e679d48 283 u32 ack_reg_offset;
e39c5add
ZW		 284
285 old = vgpu_vreg(vgpu, offset);
286 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
287
a61ac1e7 288 if (INTEL_GEN(vgpu->gvt->gt->i915) >= 9) {
e39c5add
ZW		 289 switch (offset) {
290 case FORCEWAKE_RENDER_GEN9_REG:
291 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
292 break;
293 case FORCEWAKE_BLITTER_GEN9_REG:
294 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
295 break;
296 case FORCEWAKE_MEDIA_GEN9_REG:
297 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
298 break;
299 default:
300 /*should not hit here*/
695fbc08 301 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
39762ad4 302 return -EINVAL;
e39c5add
ZW		 303 }
304 } else {
305 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
306 }
307
308 vgpu_vreg(vgpu, offset) = new;
309 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
310 return 0;
311}
312
313static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
c34eaa8d 314 void *p_data, unsigned int bytes)
e39c5add 315{
3a891a62 316 intel_engine_mask_t engine_mask = 0;
e39c5add 317 u32 data;
e39c5add 318
40d2428b 319 write_vreg(vgpu, offset, p_data, bytes);
e39c5add
ZW		 320 data = vgpu_vreg(vgpu, offset);
321
322 if (data & GEN6_GRDOM_FULL) {
323 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
c34eaa8d
CD		 324 engine_mask = ALL_ENGINES;
325 } else {
326 if (data & GEN6_GRDOM_RENDER) {
327 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
8a68d464 328 engine_mask |= BIT(RCS0);
c34eaa8d
CD		 329 }
330 if (data & GEN6_GRDOM_MEDIA) {
331 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
8a68d464 332 engine_mask |= BIT(VCS0);
c34eaa8d
CD		 333 }
334 if (data & GEN6_GRDOM_BLT) {
335 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
8a68d464 336 engine_mask |= BIT(BCS0);
c34eaa8d
CD		 337 }
338 if (data & GEN6_GRDOM_VECS) {
339 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
8a68d464 340 engine_mask |= BIT(VECS0);
c34eaa8d
CD		 341 }
342 if (data & GEN8_GRDOM_MEDIA2) {
343 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
8a68d464 344 engine_mask |= BIT(VCS1);
c34eaa8d 345 }
5e822e44
GF		 346 if (data & GEN9_GRDOM_GUC) {
347 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
348 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
349 }
a61ac1e7 350 engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask;
e39c5add 351 }
c34eaa8d 352
f25a49ab 353 /* vgpu_lock already hold by emulate mmio r/w */
c34eaa8d
CD		 354 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
355
0811fa66 356 /* sw will wait for the device to ack the reset request */
253fe56e 357 vgpu_vreg(vgpu, offset) = 0;
0811fa66 358
c34eaa8d 359 return 0;
e39c5add
ZW		 360}
361
04d348ae
ZW		 362static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
363 void *p_data, unsigned int bytes)
364{
365 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
366}
367
368static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
369 void *p_data, unsigned int bytes)
370{
371 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
372}
373
374static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
375 unsigned int offset, void *p_data, unsigned int bytes)
376{
377 write_vreg(vgpu, offset, p_data, bytes);
378
379 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
90551a12
ZW		 380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
382 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
383 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
04d348ae
ZW		 384
385 } else
90551a12 386 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
04d348ae
ZW		 387 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
388 | PP_CYCLE_DELAY_ACTIVE);
389 return 0;
390}
391
392static int transconf_mmio_write(struct intel_vgpu *vgpu,
393 unsigned int offset, void *p_data, unsigned int bytes)
394{
395 write_vreg(vgpu, offset, p_data, bytes);
396
397 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
398 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
399 else
400 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
401 return 0;
402}
403
404static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
405 void *p_data, unsigned int bytes)
406{
407 write_vreg(vgpu, offset, p_data, bytes);
408
409 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
410 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
411 else
412 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
413
414 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
415 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
416 else
417 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
418
419 return 0;
420}
421
422static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
423 void *p_data, unsigned int bytes)
424{
5cd82b75
CD		 425 switch (offset) {
426 case 0xe651c:
427 case 0xe661c:
428 case 0xe671c:
429 case 0xe681c:
430 vgpu_vreg(vgpu, offset) = 1 << 17;
431 break;
432 case 0xe6c04:
433 vgpu_vreg(vgpu, offset) = 0x3;
434 break;
435 case 0xe6e1c:
436 vgpu_vreg(vgpu, offset) = 0x2f << 16;
437 break;
438 default:
439 return -EINVAL;
440 }
04d348ae 441
5cd82b75 442 read_vreg(vgpu, offset, p_data, bytes);
04d348ae
ZW		 443 return 0;
444}
445
446static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
447 void *p_data, unsigned int bytes)
448{
449 u32 data;
450
451 write_vreg(vgpu, offset, p_data, bytes);
452 data = vgpu_vreg(vgpu, offset);
453
454 if (data & PIPECONF_ENABLE)
455 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
456 else
457 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
f25a49ab
CX		 458 /* vgpu_lock already hold by emulate mmio r/w */
459 mutex_unlock(&vgpu->vgpu_lock);
04d348ae 460 intel_gvt_check_vblank_emulation(vgpu->gvt);
f25a49ab 461 mutex_lock(&vgpu->vgpu_lock);
04d348ae
ZW		 462 return 0;
463}
464
3faae981 465/* sorted in ascending order */
e6cedfea 466static i915_reg_t force_nonpriv_white_list[] = {
3faae981 467 _MMIO(0xd80),
e6cedfea
ZY		 468 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
469 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
3faae981
TZ		 470 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
471 PS_INVOCATION_COUNT, //_MMIO(0x2348)
472 PS_DEPTH_COUNT, //_MMIO(0x2350)
e6cedfea
ZY		 473 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
474 _MMIO(0x2690),
475 _MMIO(0x2694),
476 _MMIO(0x2698),
1fd45b09
CX		 477 _MMIO(0x2754),
478 _MMIO(0x28a0),
e6cedfea
ZY		 479 _MMIO(0x4de0),
480 _MMIO(0x4de4),
481 _MMIO(0x4dfc),
482 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
483 _MMIO(0x7014),
484 HDC_CHICKEN0,//_MMIO(0x7300)
485 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
486 _MMIO(0x7700),
487 _MMIO(0x7704),
488 _MMIO(0x7708),
489 _MMIO(0x770c),
cba5ad62 490 _MMIO(0x83a8),
e6cedfea
ZY		 491 _MMIO(0xb110),
492 GEN8_L3SQCREG4,//_MMIO(0xb118)
493 _MMIO(0xe100),
494 _MMIO(0xe18c),
495 _MMIO(0xe48c),
496 _MMIO(0xe5f4),
3faae981 497 _MMIO(0x64844),
e6cedfea
ZY		 498};
499
500/* a simple bsearch */
8fde4107 501static inline bool in_whitelist(u32 reg)
e6cedfea
ZY		 502{
503 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
504 i915_reg_t *array = force_nonpriv_white_list;
505
506 while (left < right) {
507 int mid = (left + right)/2;
508
509 if (reg > array[mid].reg)
510 left = mid + 1;
511 else if (reg < array[mid].reg)
512 right = mid;
513 else
514 return true;
515 }
516 return false;
517}
518
519static int force_nonpriv_write(struct intel_vgpu *vgpu,
520 unsigned int offset, void *p_data, unsigned int bytes)
521{
aeab9eda 522 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
8fde4107
CW		 523 const struct intel_engine_cs *engine =
524 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
e6cedfea 525
8fde4107
CW		 526 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {
527 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
528 vgpu->id, offset, bytes);
529 return -EINVAL;
e6cedfea
ZY		 530 }
531
8fde4107
CW		 532 if (!in_whitelist(reg_nonpriv) &&
533 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {
3d8b9e25 534 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
8fde4107
CW		 535 vgpu->id, reg_nonpriv, offset);
536 } else
537 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
3d8b9e25 538
0438a105 539 return 0;
e6cedfea
ZY		 540}
541
04d348ae
ZW		 542static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
543 void *p_data, unsigned int bytes)
544{
545 write_vreg(vgpu, offset, p_data, bytes);
546
547 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
548 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
549 } else {
550 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
551 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
90551a12 552 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
04d348ae
ZW		 553 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
554 }
555 return 0;
556}
557
558static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
559 unsigned int offset, void *p_data, unsigned int bytes)
560{
561 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
562 return 0;
563}
564
565#define FDI_LINK_TRAIN_PATTERN1 0
566#define FDI_LINK_TRAIN_PATTERN2 1
567
568static int fdi_auto_training_started(struct intel_vgpu *vgpu)
569{
90551a12 570 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
04d348ae 571 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
90551a12 572 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
04d348ae
ZW		 573
574 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
575 (rx_ctl & FDI_RX_ENABLE) &&
576 (rx_ctl & FDI_AUTO_TRAINING) &&
577 (tx_ctl & DP_TP_CTL_ENABLE) &&
578 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
579 return 1;
580 else
581 return 0;
582}
583
584static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
585 enum pipe pipe, unsigned int train_pattern)
586{
587 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
588 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
589 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
590 unsigned int fdi_iir_check_bits;
591
592 fdi_rx_imr = FDI_RX_IMR(pipe);
593 fdi_tx_ctl = FDI_TX_CTL(pipe);
594 fdi_rx_ctl = FDI_RX_CTL(pipe);
595
596 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
597 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
598 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
599 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
600 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
601 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
602 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
603 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
604 } else {
695fbc08 605 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
04d348ae
ZW		 606 return -EINVAL;
607 }
608
609 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
610 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
611
612 /* If imr bit has been masked */
90551a12 613 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
04d348ae
ZW		 614 return 0;
615
90551a12 616 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
04d348ae 617 == fdi_tx_check_bits)
90551a12 618 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
04d348ae
ZW		 619 == fdi_rx_check_bits))
620 return 1;
621 else
622 return 0;
623}
624
625#define INVALID_INDEX (~0U)
626
627static unsigned int calc_index(unsigned int offset, unsigned int start,
628 unsigned int next, unsigned int end, i915_reg_t i915_end)
629{
630 unsigned int range = next - start;
631
632 if (!end)
633 end = i915_mmio_reg_offset(i915_end);
634 if (offset < start || offset > end)
635 return INVALID_INDEX;
636 offset -= start;
637 return offset / range;
638}
639
640#define FDI_RX_CTL_TO_PIPE(offset) \
641 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
642
643#define FDI_TX_CTL_TO_PIPE(offset) \
644 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
645
646#define FDI_RX_IMR_TO_PIPE(offset) \
647 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
648
649static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
650 unsigned int offset, void *p_data, unsigned int bytes)
651{
652 i915_reg_t fdi_rx_iir;
653 unsigned int index;
654 int ret;
655
656 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
657 index = FDI_RX_CTL_TO_PIPE(offset);
658 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
659 index = FDI_TX_CTL_TO_PIPE(offset);
660 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
661 index = FDI_RX_IMR_TO_PIPE(offset);
662 else {
695fbc08 663 gvt_vgpu_err("Unsupport registers %x\n", offset);
04d348ae
ZW		 664 return -EINVAL;
665 }
666
667 write_vreg(vgpu, offset, p_data, bytes);
668
669 fdi_rx_iir = FDI_RX_IIR(index);
670
671 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
672 if (ret < 0)
673 return ret;
674 if (ret)
90551a12 675 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
04d348ae
ZW		 676
677 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
678 if (ret < 0)
679 return ret;
680 if (ret)
90551a12 681 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
04d348ae
ZW		 682
683 if (offset == _FDI_RXA_CTL)
684 if (fdi_auto_training_started(vgpu))
90551a12 685 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
04d348ae
ZW		 686 DP_TP_STATUS_AUTOTRAIN_DONE;
687 return 0;
688}
689
690#define DP_TP_CTL_TO_PORT(offset) \
691 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
692
693static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
694 void *p_data, unsigned int bytes)
695{
696 i915_reg_t status_reg;
697 unsigned int index;
698 u32 data;
699
700 write_vreg(vgpu, offset, p_data, bytes);
701
702 index = DP_TP_CTL_TO_PORT(offset);
703 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
704 if (data == 0x2) {
705 status_reg = DP_TP_STATUS(index);
90551a12 706 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
04d348ae
ZW		 707 }
708 return 0;
709}
710
711static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
712 unsigned int offset, void *p_data, unsigned int bytes)
713{
714 u32 reg_val;
715 u32 sticky_mask;
716
717 reg_val = *((u32 *)p_data);
718 sticky_mask = GENMASK(27, 26) | (1 << 24);
719
720 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
721 (vgpu_vreg(vgpu, offset) & sticky_mask);
722 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
723 return 0;
724}
725
726static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
727 unsigned int offset, void *p_data, unsigned int bytes)
728{
729 u32 data;
730
731 write_vreg(vgpu, offset, p_data, bytes);
732 data = vgpu_vreg(vgpu, offset);
733
734 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
735 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
736 return 0;
737}
738
739static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
740 unsigned int offset, void *p_data, unsigned int bytes)
741{
742 u32 data;
743
744 write_vreg(vgpu, offset, p_data, bytes);
745 data = vgpu_vreg(vgpu, offset);
746
747 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
748 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
749 else
750 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
751 return 0;
752}
753
754#define DSPSURF_TO_PIPE(offset) \
755 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
756
757static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
758 void *p_data, unsigned int bytes)
759{
a61ac1e7 760 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
d57b39e3
CX		 761 u32 pipe = DSPSURF_TO_PIPE(offset);
762 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
04d348ae
ZW		 763
764 write_vreg(vgpu, offset, p_data, bytes);
d57b39e3
CX		 765 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
766
767 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
768
769 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
770 intel_vgpu_trigger_virtual_event(vgpu, event);
771 else
772 set_bit(event, vgpu->irq.flip_done_event[pipe]);
04d348ae 773
04d348ae
ZW		 774 return 0;
775}
776
777#define SPRSURF_TO_PIPE(offset) \
778 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
779
780static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
781 void *p_data, unsigned int bytes)
782{
d57b39e3
CX		 783 u32 pipe = SPRSURF_TO_PIPE(offset);
784 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
04d348ae
ZW		 785
786 write_vreg(vgpu, offset, p_data, bytes);
d57b39e3
CX		 787 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
788
789 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
790 intel_vgpu_trigger_virtual_event(vgpu, event);
791 else
792 set_bit(event, vgpu->irq.flip_done_event[pipe]);
793
794 return 0;
795}
796
797static int reg50080_mmio_write(struct intel_vgpu *vgpu,
798 unsigned int offset, void *p_data,
799 unsigned int bytes)
800{
a61ac1e7 801 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
d57b39e3
CX		 802 enum pipe pipe = REG_50080_TO_PIPE(offset);
803 enum plane_id plane = REG_50080_TO_PLANE(offset);
804 int event = SKL_FLIP_EVENT(pipe, plane);
805
806 write_vreg(vgpu, offset, p_data, bytes);
807 if (plane == PLANE_PRIMARY) {
808 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
809 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
810 } else {
811 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
812 }
813
814 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
815 intel_vgpu_trigger_virtual_event(vgpu, event);
816 else
817 set_bit(event, vgpu->irq.flip_done_event[pipe]);
04d348ae 818
04d348ae
ZW		 819 return 0;
820}
821
822static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
823 unsigned int reg)
824{
a61ac1e7 825 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
04d348ae
ZW		 826 enum intel_gvt_event_type event;
827
47c41af7 828 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
04d348ae 829 event = AUX_CHANNEL_A;
47c41af7
MR		 830 else if (reg == _PCH_DPB_AUX_CH_CTL ||
831 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
04d348ae 832 event = AUX_CHANNEL_B;
47c41af7
MR		 833 else if (reg == _PCH_DPC_AUX_CH_CTL ||
834 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
04d348ae 835 event = AUX_CHANNEL_C;
47c41af7
MR		 836 else if (reg == _PCH_DPD_AUX_CH_CTL ||
837 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
04d348ae
ZW		 838 event = AUX_CHANNEL_D;
839 else {
db19c724 840 drm_WARN_ON(&dev_priv->drm, true);
04d348ae
ZW		 841 return -EINVAL;
842 }
843
844 intel_vgpu_trigger_virtual_event(vgpu, event);
845 return 0;
846}
847
848static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
849 unsigned int reg, int len, bool data_valid)
850{
851 /* mark transaction done */
852 value |= DP_AUX_CH_CTL_DONE;
853 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
854 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
855
856 if (data_valid)
857 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
858 else
859 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
860
861 /* message size */
862 value &= ~(0xf << 20);
863 value |= (len << 20);
864 vgpu_vreg(vgpu, reg) = value;
865
866 if (value & DP_AUX_CH_CTL_INTERRUPT)
867 return trigger_aux_channel_interrupt(vgpu, reg);
868 return 0;
869}
870
871static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
2e679d48 872 u8 t)
04d348ae
ZW		 873{
874 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
875 /* training pattern 1 for CR */
876 /* set LANE0_CR_DONE, LANE1_CR_DONE */
877 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
878 /* set LANE2_CR_DONE, LANE3_CR_DONE */
879 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
880 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
881 DPCD_TRAINING_PATTERN_2) {
882 /* training pattern 2 for EQ */
883 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
884 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
885 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
886 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
887 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
888 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
889 /* set INTERLANE_ALIGN_DONE */
890 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
891 DPCD_INTERLANE_ALIGN_DONE;
892 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
893 DPCD_LINK_TRAINING_DISABLED) {
894 /* finish link training */
895 /* set sink status as synchronized */
896 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
897 }
898}
899
900#define _REG_HSW_DP_AUX_CH_CTL(dp) \
901 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
902
903#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
904
905#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
906
907#define dpy_is_valid_port(port) \
908 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
909
910static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
911 unsigned int offset, void *p_data, unsigned int bytes)
912{
913 struct intel_vgpu_display *display = &vgpu->display;
914 int msg, addr, ctrl, op, len;
915 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
916 struct intel_vgpu_dpcd_data *dpcd = NULL;
917 struct intel_vgpu_port *port = NULL;
918 u32 data;
919
920 if (!dpy_is_valid_port(port_index)) {
695fbc08 921 gvt_vgpu_err("Unsupported DP port access!\n");
04d348ae
ZW		 922 return 0;
923 }
924
925 write_vreg(vgpu, offset, p_data, bytes);
926 data = vgpu_vreg(vgpu, offset);
927
a61ac1e7 928 if ((INTEL_GEN(vgpu->gvt->gt->i915) >= 9)
e3476c00 929 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
04d348ae
ZW		 930 /* SKL DPB/C/D aux ctl register changed */
931 return 0;
a61ac1e7 932 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) &&
04d348ae
ZW		 933 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
934 /* write to the data registers */
935 return 0;
936 }
937
938 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
939 /* just want to clear the sticky bits */
940 vgpu_vreg(vgpu, offset) = 0;
941 return 0;
942 }
943
944 port = &display->ports[port_index];
945 dpcd = port->dpcd;
946
947 /* read out message from DATA1 register */
948 msg = vgpu_vreg(vgpu, offset + 4);
949 addr = (msg >> 8) & 0xffff;
950 ctrl = (msg >> 24) & 0xff;
951 len = msg & 0xff;
952 op = ctrl >> 4;
953
954 if (op == GVT_AUX_NATIVE_WRITE) {
955 int t;
2e679d48 956 u8 buf[16];
04d348ae
ZW		 957
958 if ((addr + len + 1) >= DPCD_SIZE) {
959 /*
960 * Write request exceeds what we supported,
961 * DCPD spec: When a Source Device is writing a DPCD
962 * address not supported by the Sink Device, the Sink
963 * Device shall reply with AUX NACK and “M” equal to
964 * zero.
965 */
966
967 /* NAK the write */
968 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
969 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
970 return 0;
971 }
972
973 /*
2f24636b
CD		 974 * Write request format: Headr (command + address + size) occupies
975 * 4 bytes, followed by (len + 1) bytes of data. See details at
976 * intel_dp_aux_transfer().
04d348ae 977 */
2f24636b
CD		 978 if ((len + 1 + 4) > AUX_BURST_SIZE) {
979 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
04d348ae 980 return -EINVAL;
2f24636b 981 }
04d348ae
ZW		 982
983 /* unpack data from vreg to buf */
984 for (t = 0; t < 4; t++) {
985 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
986
987 buf[t * 4] = (r >> 24) & 0xff;
988 buf[t * 4 + 1] = (r >> 16) & 0xff;
989 buf[t * 4 + 2] = (r >> 8) & 0xff;
990 buf[t * 4 + 3] = r & 0xff;
991 }
992
993 /* write to virtual DPCD */
994 if (dpcd && dpcd->data_valid) {
995 for (t = 0; t <= len; t++) {
996 int p = addr + t;
997
998 dpcd->data[p] = buf[t];
999 /* check for link training */
1000 if (p == DPCD_TRAINING_PATTERN_SET)
1001 dp_aux_ch_ctl_link_training(dpcd,
1002 buf[t]);
1003 }
1004 }
1005
1006 /* ACK the write */
1007 vgpu_vreg(vgpu, offset + 4) = 0;
1008 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1009 dpcd && dpcd->data_valid);
1010 return 0;
1011 }
1012
1013 if (op == GVT_AUX_NATIVE_READ) {
1014 int idx, i, ret = 0;
1015
1016 if ((addr + len + 1) >= DPCD_SIZE) {
1017 /*
1018 * read request exceeds what we supported
1019 * DPCD spec: A Sink Device receiving a Native AUX CH
1020 * read request for an unsupported DPCD address must
1021 * reply with an AUX ACK and read data set equal to
1022 * zero instead of replying with AUX NACK.
1023 */
1024
1025 /* ACK the READ*/
1026 vgpu_vreg(vgpu, offset + 4) = 0;
1027 vgpu_vreg(vgpu, offset + 8) = 0;
1028 vgpu_vreg(vgpu, offset + 12) = 0;
1029 vgpu_vreg(vgpu, offset + 16) = 0;
1030 vgpu_vreg(vgpu, offset + 20) = 0;
1031
1032 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1033 true);
1034 return 0;
1035 }
1036
1037 for (idx = 1; idx <= 5; idx++) {
1038 /* clear the data registers */
1039 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1040 }
1041
1042 /*
1043 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1044 */
2f24636b
CD		 1045 if ((len + 2) > AUX_BURST_SIZE) {
1046 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
04d348ae 1047 return -EINVAL;
2f24636b 1048 }
04d348ae
ZW		 1049
1050 /* read from virtual DPCD to vreg */
1051 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1052 if (dpcd && dpcd->data_valid) {
1053 for (i = 1; i <= (len + 1); i++) {
1054 int t;
1055
1056 t = dpcd->data[addr + i - 1];
1057 t <<= (24 - 8 * (i % 4));
1058 ret |= t;
1059
1060 if ((i % 4 == 3) || (i == (len + 1))) {
1061 vgpu_vreg(vgpu, offset +
1062 (i / 4 + 1) * 4) = ret;
1063 ret = 0;
1064 }
1065 }
1066 }
1067 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1068 dpcd && dpcd->data_valid);
1069 return 0;
1070 }
1071
1072 /* i2c transaction starts */
1073 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1074
1075 if (data & DP_AUX_CH_CTL_INTERRUPT)
1076 trigger_aux_channel_interrupt(vgpu, offset);
1077 return 0;
1078}
1079
975629c3
PZ		 1080static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1081 void *p_data, unsigned int bytes)
1082{
1083 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1084 write_vreg(vgpu, offset, p_data, bytes);
1085 return 0;
1086}
1087
04d348ae
ZW		 1088static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1089 void *p_data, unsigned int bytes)
1090{
1091 bool vga_disable;
1092
1093 write_vreg(vgpu, offset, p_data, bytes);
1094 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1095
1096 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1097 vga_disable ? "Disable" : "Enable");
1098 return 0;
1099}
1100
1101static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1102 unsigned int sbi_offset)
1103{
1104 struct intel_vgpu_display *display = &vgpu->display;
1105 int num = display->sbi.number;
1106 int i;
1107
1108 for (i = 0; i < num; ++i)
1109 if (display->sbi.registers[i].offset == sbi_offset)
1110 break;
1111
1112 if (i == num)
1113 return 0;
1114
1115 return display->sbi.registers[i].value;
1116}
1117
1118static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1119 unsigned int offset, u32 value)
1120{
1121 struct intel_vgpu_display *display = &vgpu->display;
1122 int num = display->sbi.number;
1123 int i;
1124
1125 for (i = 0; i < num; ++i) {
1126 if (display->sbi.registers[i].offset == offset)
1127 break;
1128 }
1129
1130 if (i == num) {
1131 if (num == SBI_REG_MAX) {
695fbc08 1132 gvt_vgpu_err("SBI caching meets maximum limits\n");
04d348ae
ZW		 1133 return;
1134 }
1135 display->sbi.number++;
1136 }
1137
1138 display->sbi.registers[i].offset = offset;
1139 display->sbi.registers[i].value = value;
1140}
1141
1142static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1143 void *p_data, unsigned int bytes)
1144{
90551a12 1145 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
04d348ae 1146 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
90551a12 1147 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
04d348ae
ZW		 1148 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1149 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1150 sbi_offset);
1151 }
1152 read_vreg(vgpu, offset, p_data, bytes);
1153 return 0;
1154}
1155
3e70c5d6 1156static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
04d348ae
ZW		 1157 void *p_data, unsigned int bytes)
1158{
1159 u32 data;
1160
1161 write_vreg(vgpu, offset, p_data, bytes);
1162 data = vgpu_vreg(vgpu, offset);
1163
1164 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1165 data |= SBI_READY;
1166
1167 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1168 data |= SBI_RESPONSE_SUCCESS;
1169
1170 vgpu_vreg(vgpu, offset) = data;
1171
90551a12 1172 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
04d348ae 1173 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
90551a12 1174 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
04d348ae
ZW		 1175 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1176
1177 write_virtual_sbi_register(vgpu, sbi_offset,
90551a12 1178 vgpu_vreg_t(vgpu, SBI_DATA));
04d348ae
ZW		 1179 }
1180 return 0;
1181}
1182
e39c5add
ZW		 1183#define _vgtif_reg(x) \
1184 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1185
1186static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1187 void *p_data, unsigned int bytes)
1188{
1189 bool invalid_read = false;
1190
1191 read_vreg(vgpu, offset, p_data, bytes);
1192
1193 switch (offset) {
1194 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1195 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1196 invalid_read = true;
1197 break;
1198 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1199 _vgtif_reg(avail_rs.fence_num):
1200 if (offset + bytes >
1201 _vgtif_reg(avail_rs.fence_num) + 4)
1202 invalid_read = true;
1203 break;
1204 case 0x78010: /* vgt_caps */
1205 case 0x7881c:
1206 break;
1207 default:
1208 invalid_read = true;
1209 break;
1210 }
1211 if (invalid_read)
695fbc08 1212 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
e39c5add 1213 offset, bytes, *(u32 *)p_data);
fd64be63 1214 vgpu->pv_notified = true;
e39c5add
ZW		 1215 return 0;
1216}
1217
1218static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1219{
0cf8f58d 1220 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
e6e9c46f 1221 struct intel_vgpu_mm *mm;
ede9d0cf 1222 u64 *pdps;
e39c5add 1223
ede9d0cf
CD		 1224 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1225
e39c5add
ZW		 1226 switch (notification) {
1227 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
e6e9c46f 1228 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
3eda0d22 1229 /* fall through */
e39c5add 1230 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
e6e9c46f
CD		 1231 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1232 return PTR_ERR_OR_ZERO(mm);
1233 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
e39c5add 1234 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
e6e9c46f 1235 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
e39c5add
ZW		 1236 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1237 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1238 case 1: /* Remove this in guest driver. */
1239 break;
1240 default:
695fbc08 1241 gvt_vgpu_err("Invalid PV notification %d\n", notification);
e39c5add 1242 }
e6e9c46f 1243 return 0;
e39c5add
ZW		 1244}
1245
04d348ae
ZW		 1246static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1247{
a61ac1e7 1248 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj;
04d348ae
ZW		 1249 char *env[3] = {NULL, NULL, NULL};
1250 char vmid_str[20];
1251 char display_ready_str[20];
1252
d8e9b2b9 1253 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
04d348ae
ZW		 1254 env[0] = display_ready_str;
1255
1256 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1257 env[1] = vmid_str;
1258
1259 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1260}
1261
e39c5add
ZW		 1262static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1263 void *p_data, unsigned int bytes)
1264{
971afec3
WL		 1265 u32 data = *(u32 *)p_data;
1266 bool invalid_write = false;
e39c5add
ZW		 1267
1268 switch (offset) {
1269 case _vgtif_reg(display_ready):
04d348ae
ZW		 1270 send_display_ready_uevent(vgpu, data ? 1 : 0);
1271 break;
e39c5add 1272 case _vgtif_reg(g2v_notify):
971afec3 1273 handle_g2v_notification(vgpu, data);
e39c5add
ZW		 1274 break;
1275 /* add xhot and yhot to handled list to avoid error log */
1c6ccad8
TZ		 1276 case _vgtif_reg(cursor_x_hot):
1277 case _vgtif_reg(cursor_y_hot):
e39c5add
ZW		 1278 case _vgtif_reg(pdp[0].lo):
1279 case _vgtif_reg(pdp[0].hi):
1280 case _vgtif_reg(pdp[1].lo):
1281 case _vgtif_reg(pdp[1].hi):
1282 case _vgtif_reg(pdp[2].lo):
1283 case _vgtif_reg(pdp[2].hi):
1284 case _vgtif_reg(pdp[3].lo):
1285 case _vgtif_reg(pdp[3].hi):
1286 case _vgtif_reg(execlist_context_descriptor_lo):
1287 case _vgtif_reg(execlist_context_descriptor_hi):
1288 break;
a33fc7a0 1289 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
971afec3 1290 invalid_write = true;
a33fc7a0
MH		 1291 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1292 break;
e39c5add 1293 default:
971afec3 1294 invalid_write = true;
695fbc08 1295 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
e39c5add
ZW		 1296 offset, bytes, data);
1297 break;
1298 }
971afec3
WL		 1299
1300 if (!invalid_write)
1301 write_vreg(vgpu, offset, p_data, bytes);
1302
e39c5add
ZW		 1303 return 0;
1304}
1305
04d348ae
ZW		 1306static int pf_write(struct intel_vgpu *vgpu,
1307 unsigned int offset, void *p_data, unsigned int bytes)
1308{
a61ac1e7 1309 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
04d348ae
ZW		 1310 u32 val = *(u32 *)p_data;
1311
1312 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1313 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1314 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
12d58619
PB		 1315 drm_WARN_ONCE(&i915->drm, true,
1316 "VM(%d): guest is trying to scaling a plane\n",
1317 vgpu->id);
04d348ae
ZW		 1318 return 0;
1319 }
1320
1321 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1322}
1323
1324static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1325 unsigned int offset, void *p_data, unsigned int bytes)
1326{
1327 write_vreg(vgpu, offset, p_data, bytes);
1328
75e39688
ID		 1329 if (vgpu_vreg(vgpu, offset) &
1330 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1af474fe 1331 vgpu_vreg(vgpu, offset) |=
75e39688 1332 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
04d348ae 1333 else
1af474fe 1334 vgpu_vreg(vgpu, offset) &=
75e39688 1335 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
04d348ae
ZW		 1336 return 0;
1337}
1338
9174c1d6
XZ		 1339static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1340 unsigned int offset, void *p_data, unsigned int bytes)
1341{
1342 write_vreg(vgpu, offset, p_data, bytes);
1343
1344 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1345 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1346 else
1347 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1348
1349 return 0;
1350}
1351
e39c5add
ZW		 1352static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1353 unsigned int offset, void *p_data, unsigned int bytes)
1354{
1355 write_vreg(vgpu, offset, p_data, bytes);
1356
1357 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1358 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1359 return 0;
1360}
1361
1362static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1363 void *p_data, unsigned int bytes)
1364{
a61ac1e7 1365 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
5f399f11
PG		 1366 u32 mode;
1367
1368 write_vreg(vgpu, offset, p_data, bytes);
1369 mode = vgpu_vreg(vgpu, offset);
e39c5add
ZW		 1370
1371 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
12d58619
PB		 1372 drm_WARN_ONCE(&i915->drm, 1,
1373 "VM(%d): iGVT-g doesn't support GuC\n",
e39c5add
ZW		 1374 vgpu->id);
1375 return 0;
1376 }
1377
1378 return 0;
1379}
1380
1381static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1382 void *p_data, unsigned int bytes)
1383{
a61ac1e7 1384 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
e39c5add
ZW		 1385 u32 trtte = *(u32 *)p_data;
1386
1387 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
12d58619
PB		 1388 drm_WARN(&i915->drm, 1,
1389 "VM(%d): Use physical address for TRTT!\n",
e39c5add
ZW		 1390 vgpu->id);
1391 return -EINVAL;
1392 }
1393 write_vreg(vgpu, offset, p_data, bytes);
e39c5add
ZW		 1394
1395 return 0;
1396}
1397
1398static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1399 void *p_data, unsigned int bytes)
1400{
e39c5add
ZW		 1401 write_vreg(vgpu, offset, p_data, bytes);
1402 return 0;
1403}
1404
04d348ae
ZW		 1405static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1406 void *p_data, unsigned int bytes)
1407{
1408 u32 v = 0;
1409
1410 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1411 v |= (1 << 0);
1412
1413 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1414 v |= (1 << 8);
1415
1416 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1417 v |= (1 << 16);
1418
1419 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1420 v |= (1 << 24);
1421
1422 vgpu_vreg(vgpu, offset) = v;
1423
1424 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1425}
1426
1427static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1428 void *p_data, unsigned int bytes)
1429{
1430 u32 value = *(u32 *)p_data;
1431 u32 cmd = value & 0xff;
90551a12 1432 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
04d348ae
ZW		 1433
1434 switch (cmd) {
8bcd7c18 1435 case GEN9_PCODE_READ_MEM_LATENCY:
a61ac1e7
CW		 1436 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1437 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1438 IS_COFFEELAKE(vgpu->gvt->gt->i915)) {
8bcd7c18
WL		 1439 /**
1440 * "Read memory latency" command on gen9.
1441 * Below memory latency values are read
1442 * from skylake platform.
1443 */
1444 if (!*data0)
1445 *data0 = 0x1e1a1100;
1446 else
1447 *data0 = 0x61514b3d;
a61ac1e7 1448 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) {
d71cb712
CX		 1449 /**
1450 * "Read memory latency" command on gen9.
1451 * Below memory latency values are read
1452 * from Broxton MRB.
1453 */
1454 if (!*data0)
1455 *data0 = 0x16080707;
1456 else
1457 *data0 = 0x16161616;
8bcd7c18 1458 }
04d348ae 1459 break;
d8a355be 1460 case SKL_PCODE_CDCLK_CONTROL:
a61ac1e7
CW		 1461 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1462 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1463 IS_COFFEELAKE(vgpu->gvt->gt->i915))
8bcd7c18 1464 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
d8a355be 1465 break;
8bcd7c18 1466 case GEN6_PCODE_READ_RC6VIDS:
04d348ae
ZW		 1467 *data0 |= 0x1;
1468 break;
1469 }
1470
1471 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1472 vgpu->id, value, *data0);
d8a355be
WL		 1473 /**
1474 * PCODE_READY clear means ready for pcode read/write,
1475 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1476 * always emulate as pcode read/write success and ready for access
1477 * anytime, since we don't touch real physical registers here.
1478 */
1479 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
04d348ae
ZW		 1480 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1481}
1482
a2ae95af
WL		 1483static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1484 void *p_data, unsigned int bytes)
1485{
1486 u32 value = *(u32 *)p_data;
8fde4107
CW		 1487 const struct intel_engine_cs *engine =
1488 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
a2ae95af
WL		 1489
1490 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
b52646fd
ZW		 1491 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1492 offset, value);
a2ae95af
WL		 1493 return -EINVAL;
1494 }
a61ac1e7 1495
a2ae95af
WL		 1496 /*
1497 * Need to emulate all the HWSP register write to ensure host can
1498 * update the VM CSB status correctly. Here listed registers can
1499 * support BDW, SKL or other platforms with same HWSP registers.
1500 */
8fde4107 1501 if (unlikely(!engine)) {
b52646fd
ZW		 1502 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1503 offset);
a2ae95af
WL		 1504 return -EINVAL;
1505 }
8fde4107 1506 vgpu->hws_pga[engine->id] = value;
a2ae95af
WL		 1507 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1508 vgpu->id, value, offset);
1509
1510 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1511}
1512
04d348ae
ZW		 1513static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1514 unsigned int offset, void *p_data, unsigned int bytes)
1515{
1516 u32 v = *(u32 *)p_data;
1517
a61ac1e7 1518 if (IS_BROXTON(vgpu->gvt->gt->i915))
d71cb712
CX		 1519 v &= (1 << 31) | (1 << 29);
1520 else
1521 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1522 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
04d348ae
ZW		 1523 v |= (v >> 1);
1524
1525 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1526}
1527
04d348ae
ZW		 1528static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1529 void *p_data, unsigned int bytes)
1530{
1531 u32 v = *(u32 *)p_data;
1532
1533 /* other bits are MBZ. */
1534 v &= (1 << 31) | (1 << 30);
1535 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1536
1537 vgpu_vreg(vgpu, offset) = v;
1538
1539 return 0;
1540}
1541
d71cb712
CX		 1542static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1543 unsigned int offset, void *p_data, unsigned int bytes)
1544{
1545 u32 v = *(u32 *)p_data;
1546
1547 if (v & BXT_DE_PLL_PLL_ENABLE)
1548 v |= BXT_DE_PLL_LOCK;
1549
1550 vgpu_vreg(vgpu, offset) = v;
1551
1552 return 0;
1553}
1554
1555static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1556 unsigned int offset, void *p_data, unsigned int bytes)
1557{
1558 u32 v = *(u32 *)p_data;
1559
1560 if (v & PORT_PLL_ENABLE)
1561 v |= PORT_PLL_LOCK;
1562
1563 vgpu_vreg(vgpu, offset) = v;
1564
1565 return 0;
1566}
1567
1568static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1569 unsigned int offset, void *p_data, unsigned int bytes)
1570{
1571 u32 v = *(u32 *)p_data;
1572 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1573
c8ab5ac3
CX		 1574 switch (offset) {
1575 case _PHY_CTL_FAMILY_EDP:
1576 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1577 break;
1578 case _PHY_CTL_FAMILY_DDI:
1579 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1580 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1581 break;
1582 }
d71cb712
CX		 1583
1584 vgpu_vreg(vgpu, offset) = v;
1585
1586 return 0;
1587}
1588
1589static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1590 unsigned int offset, void *p_data, unsigned int bytes)
1591{
1592 u32 v = vgpu_vreg(vgpu, offset);
1593
1594 v &= ~UNIQUE_TRANGE_EN_METHOD;
1595
1596 vgpu_vreg(vgpu, offset) = v;
1597
1598 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1599}
1600
1601static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1602 unsigned int offset, void *p_data, unsigned int bytes)
1603{
1604 u32 v = *(u32 *)p_data;
1605
1606 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1607 vgpu_vreg(vgpu, offset - 0x600) = v;
1608 vgpu_vreg(vgpu, offset - 0x800) = v;
1609 } else {
1610 vgpu_vreg(vgpu, offset - 0x400) = v;
1611 vgpu_vreg(vgpu, offset - 0x600) = v;
1612 }
1613
1614 vgpu_vreg(vgpu, offset) = v;
1615
1616 return 0;
1617}
1618
1619static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1620 unsigned int offset, void *p_data, unsigned int bytes)
1621{
1622 u32 v = *(u32 *)p_data;
1623
1624 if (v & BIT(0)) {
1625 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1626 ~PHY_RESERVED;
1627 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1628 PHY_POWER_GOOD;
1629 }
1630
1631 if (v & BIT(1)) {
1632 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1633 ~PHY_RESERVED;
1634 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1635 PHY_POWER_GOOD;
1636 }
1637
1638
1639 vgpu_vreg(vgpu, offset) = v;
1640
1641 return 0;
1642}
1643
5e7154ff 1644static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
93d68b25
CX		 1645 unsigned int offset, void *p_data, unsigned int bytes)
1646{
1647 vgpu_vreg(vgpu, offset) = 0;
1648 return 0;
1649}
1650
5e822e44
GF		 1651static int guc_status_read(struct intel_vgpu *vgpu,
1652 unsigned int offset, void *p_data,
1653 unsigned int bytes)
1654{
1655 /* keep MIA_IN_RESET before clearing */
1656 read_vreg(vgpu, offset, p_data, bytes);
1657 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1658 return 0;
1659}
1660
20a2bcde 1661static int mmio_read_from_hw(struct intel_vgpu *vgpu,
23ce0592
WL		 1662 unsigned int offset, void *p_data, unsigned int bytes)
1663{
295764cd 1664 struct intel_gvt *gvt = vgpu->gvt;
8fde4107
CW		 1665 const struct intel_engine_cs *engine =
1666 intel_gvt_render_mmio_to_engine(gvt, offset);
295764cd 1667
295764cd
XZ		 1668 /**
1669 * Read HW reg in following case
1670 * a. the offset isn't a ring mmio
1671 * b. the offset's ring is running on hw.
1672 * c. the offset is ring time stamp mmio
1673 */
295764cd 1674
8fde4107
CW		 1675 if (!engine ||
1676 vgpu == gvt->scheduler.engine_owner[engine->id] ||
1677 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||
1678 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {
a61ac1e7
CW		 1679 mmio_hw_access_pre(gvt->gt);
1680 vgpu_vreg(vgpu, offset) =
1681 intel_uncore_read(gvt->gt->uncore, _MMIO(offset));
1682 mmio_hw_access_post(gvt->gt);
295764cd 1683 }
23ce0592 1684
04d348ae
ZW		 1685 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1686}
1687
28c4c6ca
ZW		 1688static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1689 void *p_data, unsigned int bytes)
1690{
a61ac1e7 1691 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
8fde4107 1692 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
28c4c6ca
ZW		 1693 struct intel_vgpu_execlist *execlist;
1694 u32 data = *(u32 *)p_data;
6fb5082a 1695 int ret = 0;
28c4c6ca 1696
8fde4107 1697 if (drm_WARN_ON(&i915->drm, !engine))
28c4c6ca
ZW		 1698 return -EINVAL;
1699
8fde4107 1700 execlist = &vgpu->submission.execlist[engine->id];
28c4c6ca 1701
54cff647 1702 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
6fb5082a 1703 if (execlist->elsp_dwords.index == 3) {
8fde4107 1704 ret = intel_vgpu_submit_execlist(vgpu, engine);
6fb5082a 1705 if(ret)
8fde4107
CW		 1706 gvt_vgpu_err("fail submit workload on ring %s\n",
1707 engine->name);
6fb5082a 1708 }
28c4c6ca
ZW		 1709
1710 ++execlist->elsp_dwords.index;
1711 execlist->elsp_dwords.index &= 0x3;
6fb5082a 1712 return ret;
28c4c6ca
ZW		 1713}
1714
4b63960e
ZW		 1715static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1716 void *p_data, unsigned int bytes)
1717{
1718 u32 data = *(u32 *)p_data;
8fde4107
CW		 1719 const struct intel_engine_cs *engine =
1720 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
4b63960e 1721 bool enable_execlist;
ad1d3636 1722 int ret;
4b63960e 1723
888c0094 1724 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
a61ac1e7 1725 if (IS_COFFEELAKE(vgpu->gvt->gt->i915))
888c0094 1726 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
4b63960e 1727 write_vreg(vgpu, offset, p_data, bytes);
fd64be63 1728
888c0094
CX		 1729 if (data & _MASKED_BIT_ENABLE(1)) {
1730 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1731 return 0;
1732 }
1733
a61ac1e7 1734 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) &&
888c0094
CX		 1735 data & _MASKED_BIT_ENABLE(2)) {
1736 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1737 return 0;
1738 }
1739
fd64be63
MH		 1740 /* when PPGTT mode enabled, we will check if guest has called
1741 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1742 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1743 */
1744 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1745 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1746 && !vgpu->pv_notified) {
1747 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1748 return 0;
1749 }
4b63960e
ZW		 1750 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1751 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1752 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1753
8fde4107
CW		 1754 gvt_dbg_core("EXECLIST %s on ring %s\n",
1755 (enable_execlist ? "enabling" : "disabling"),
1756 engine->name);
4b63960e 1757
ad1d3636
ZW		 1758 if (!enable_execlist)
1759 return 0;
1760
ad1d3636 1761 ret = intel_vgpu_select_submission_ops(vgpu,
8fde4107
CW		 1762 engine->mask,
1763 INTEL_VGPU_EXECLIST_SUBMISSION);
ad1d3636
ZW		 1764 if (ret)
1765 return ret;
1766
1767 intel_vgpu_start_schedule(vgpu);
4b63960e
ZW		 1768 }
1769 return 0;
1770}
1771
17865713
ZW		 1772static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1773 unsigned int offset, void *p_data, unsigned int bytes)
1774{
17865713
ZW		 1775 unsigned int id = 0;
1776
f24940e0 1777 write_vreg(vgpu, offset, p_data, bytes);
4f3f1aed 1778 vgpu_vreg(vgpu, offset) = 0;
f24940e0 1779
17865713
ZW		 1780 switch (offset) {
1781 case 0x4260:
8a68d464 1782 id = RCS0;
17865713
ZW		 1783 break;
1784 case 0x4264:
8a68d464 1785 id = VCS0;
17865713
ZW		 1786 break;
1787 case 0x4268:
8a68d464 1788 id = VCS1;
17865713
ZW		 1789 break;
1790 case 0x426c:
8a68d464 1791 id = BCS0;
17865713
ZW		 1792 break;
1793 case 0x4270:
8a68d464 1794 id = VECS0;
17865713
ZW		 1795 break;
1796 default:
a1201053 1797 return -EINVAL;
17865713 1798 }
91d5d854 1799 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
17865713 1800
a1201053 1801 return 0;
17865713
ZW		 1802}
1803
2fb39fad
DC		 1804static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1805 unsigned int offset, void *p_data, unsigned int bytes)
1806{
1807 u32 data;
1808
1809 write_vreg(vgpu, offset, p_data, bytes);
1810 data = vgpu_vreg(vgpu, offset);
1811
1812 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1813 data |= RESET_CTL_READY_TO_RESET;
1814 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1815 data &= ~RESET_CTL_READY_TO_RESET;
1816
1817 vgpu_vreg(vgpu, offset) = data;
1818 return 0;
1819}
1820
cb2808da
CX		 1821static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
1822 unsigned int offset, void *p_data,
1823 unsigned int bytes)
1824{
1825 u32 data = *(u32 *)p_data;
1826
1827 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
1828 write_vreg(vgpu, offset, p_data, bytes);
1829
1830 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
1831 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1832
1833 return 0;
1834}
1835
12d14cc4 1836#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
c20164db 1837 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
12d14cc4
ZW		 1838 f, s, am, rm, d, r, w); \
1839 if (ret) \
1840 return ret; \
1841} while (0)
1842
1843#define MMIO_D(reg, d) \
1844 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1845
1846#define MMIO_DH(reg, d, r, w) \
1847 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1848
1849#define MMIO_DFH(reg, d, f, r, w) \
1850 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1851
1852#define MMIO_GM(reg, d, r, w) \
1853 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1854
0aa5277c
ZY		 1855#define MMIO_GM_RDR(reg, d, r, w) \
1856 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1857
12d14cc4
ZW		 1858#define MMIO_RO(reg, d, f, rm, r, w) \
1859 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1860
1861#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1862 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1863 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1864 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1865 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
8a68d464 1866 if (HAS_ENGINE(dev_priv, VCS1)) \
edee7ecd 1867 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
12d14cc4
ZW		 1868} while (0)
1869
1870#define MMIO_RING_D(prefix, d) \
1871 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1872
1873#define MMIO_RING_DFH(prefix, d, f, r, w) \
1874 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1875
1876#define MMIO_RING_GM(prefix, d, r, w) \
1877 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1878
0aa5277c
ZY		 1879#define MMIO_RING_GM_RDR(prefix, d, r, w) \
1880 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1881
12d14cc4
ZW		 1882#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1883 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1884
1885static int init_generic_mmio_info(struct intel_gvt *gvt)
1886{
a61ac1e7 1887 struct drm_i915_private *dev_priv = gvt->gt->i915;
12d14cc4
ZW		 1888 int ret;
1889
0aa5277c
ZY		 1890 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1891 intel_vgpu_reg_imr_handler);
e39c5add
ZW		 1892
1893 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1894 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1895 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1896 MMIO_D(SDEISR, D_ALL);
1897
0aa5277c 1898 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add 1899
52ca14e6
CD		 1900 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
1901 gamw_echo_dev_rw_ia_write);
1902
0aa5277c
ZY		 1903 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1904 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1905 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
e39c5add 1906
c20164db 1907#define RING_REG(base) _MMIO((base) + 0x28)
0aa5277c 1908 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1909#undef RING_REG
1910
c20164db 1911#define RING_REG(base) _MMIO((base) + 0x134)
0aa5277c 1912 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1913#undef RING_REG
1914
c20164db 1915#define RING_REG(base) _MMIO((base) + 0x6c)
20a2bcde 1916 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
23ce0592 1917#undef RING_REG
20a2bcde 1918 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
23ce0592 1919
c20164db 1920 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
baba6e57 1921 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
c20164db 1922 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
e39c5add
ZW		 1923 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1924
0aa5277c
ZY		 1925 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1926 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1927 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
894e287b 1928 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
0aa5277c 1929 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
e39c5add
ZW		 1930
1931 /* RING MODE */
c20164db 1932#define RING_REG(base) _MMIO((base) + 0x29c)
0aa5277c
ZY		 1933 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1934 ring_mode_mmio_write);
e39c5add
ZW		 1935#undef RING_REG
1936
0aa5277c
ZY		 1937 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1938 NULL, NULL);
41bfab35
PZ		 1939 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1940 NULL, NULL);
04d348ae 1941 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
20a2bcde 1942 mmio_read_from_hw, NULL);
04d348ae 1943 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
20a2bcde 1944 mmio_read_from_hw, NULL);
e39c5add 1945
0aa5277c
ZY		 1946 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1947 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1948 NULL, NULL);
a045fba4 1949 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 1950 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db 1951 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 1952
c20164db 1953 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 1954 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db 1955 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
3fcb01f8
WL		 1956 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
1957 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db 1958 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 1959 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1960 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1961 NULL, NULL);
bf3a26b3
WL		 1962 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1963 NULL, NULL);
c20164db
ZW		 1964 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1965 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1966 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1967 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1968 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1969 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1970 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1971 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
a045fba4 1972 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
187447a1 1973 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1974
1975 /* display */
c20164db
ZW		 1976 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1977 MMIO_D(_MMIO(0x602a0), D_ALL);
e39c5add 1978
c20164db
ZW		 1979 MMIO_D(_MMIO(0x65050), D_ALL);
1980 MMIO_D(_MMIO(0x650b4), D_ALL);
e39c5add 1981
c20164db 1982 MMIO_D(_MMIO(0xc4040), D_ALL);
e39c5add
ZW		 1983 MMIO_D(DERRMR, D_ALL);
1984
1985 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1986 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1987 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1988 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1989
04d348ae
ZW		 1990 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1991 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1992 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1993 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
e39c5add
ZW		 1994
1995 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1996 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1997 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1998 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1999
2000 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
2001 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
2002 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
2003 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
2004
2005 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
2006 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
2007 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
2008 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
2009
2010 MMIO_D(CURCNTR(PIPE_A), D_ALL);
2011 MMIO_D(CURCNTR(PIPE_B), D_ALL);
2012 MMIO_D(CURCNTR(PIPE_C), D_ALL);
2013
2014 MMIO_D(CURPOS(PIPE_A), D_ALL);
2015 MMIO_D(CURPOS(PIPE_B), D_ALL);
2016 MMIO_D(CURPOS(PIPE_C), D_ALL);
2017
2018 MMIO_D(CURBASE(PIPE_A), D_ALL);
2019 MMIO_D(CURBASE(PIPE_B), D_ALL);
2020 MMIO_D(CURBASE(PIPE_C), D_ALL);
2021
b2744f86
CX		 2022 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
2023 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
2024 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
2025
c20164db
ZW		 2026 MMIO_D(_MMIO(0x700ac), D_ALL);
2027 MMIO_D(_MMIO(0x710ac), D_ALL);
2028 MMIO_D(_MMIO(0x720ac), D_ALL);
e39c5add 2029
c20164db
ZW		 2030 MMIO_D(_MMIO(0x70090), D_ALL);
2031 MMIO_D(_MMIO(0x70094), D_ALL);
2032 MMIO_D(_MMIO(0x70098), D_ALL);
2033 MMIO_D(_MMIO(0x7009c), D_ALL);
e39c5add
ZW		 2034
2035 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
2036 MMIO_D(DSPADDR(PIPE_A), D_ALL);
2037 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
2038 MMIO_D(DSPPOS(PIPE_A), D_ALL);
2039 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
04d348ae 2040 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 2041 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
2042 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
d57b39e3
CX		 2043 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2044 reg50080_mmio_write);
e39c5add
ZW		 2045
2046 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
2047 MMIO_D(DSPADDR(PIPE_B), D_ALL);
2048 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
2049 MMIO_D(DSPPOS(PIPE_B), D_ALL);
2050 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
04d348ae 2051 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 2052 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
2053 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
d57b39e3
CX		 2054 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2055 reg50080_mmio_write);
e39c5add
ZW		 2056
2057 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
2058 MMIO_D(DSPADDR(PIPE_C), D_ALL);
2059 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
2060 MMIO_D(DSPPOS(PIPE_C), D_ALL);
2061 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
04d348ae 2062 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 2063 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
2064 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
d57b39e3
CX		 2065 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2066 reg50080_mmio_write);
e39c5add
ZW		 2067
2068 MMIO_D(SPRCTL(PIPE_A), D_ALL);
2069 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
2070 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
2071 MMIO_D(SPRPOS(PIPE_A), D_ALL);
2072 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
2073 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
2074 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
04d348ae 2075 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 2076 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
2077 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
2078 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
2079 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
d57b39e3
CX		 2080 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2081 reg50080_mmio_write);
e39c5add
ZW		 2082
2083 MMIO_D(SPRCTL(PIPE_B), D_ALL);
2084 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
2085 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
2086 MMIO_D(SPRPOS(PIPE_B), D_ALL);
2087 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
2088 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
2089 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
04d348ae 2090 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 2091 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
2092 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
2093 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
2094 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
d57b39e3
CX		 2095 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2096 reg50080_mmio_write);
e39c5add
ZW		 2097
2098 MMIO_D(SPRCTL(PIPE_C), D_ALL);
2099 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
2100 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
2101 MMIO_D(SPRPOS(PIPE_C), D_ALL);
2102 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
2103 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
2104 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
04d348ae 2105 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 2106 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
2107 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
2108 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
2109 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
d57b39e3
CX		 2110 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2111 reg50080_mmio_write);
e39c5add 2112
e39c5add
ZW		 2113 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
2114 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
2115 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2116 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
2117 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2118 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
2119 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
2120 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
2121 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
2122
2123 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
2124 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
2125 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2126 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
2127 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2128 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
2129 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
2130 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
2131 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
2132
2133 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
2134 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
2135 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2136 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
2137 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2138 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
2139 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
2140 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
2141 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
2142
2143 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
2144 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
2145 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
2146 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
2147 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
2148 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
2149 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
2150 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
2151
2152 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
2153 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
2154 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
2155 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
2156 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
2157 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
2158 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
2159 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
2160
2161 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
2162 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
2163 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
2164 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
2165 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
2166 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
2167 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
2168 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
2169
2170 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
2171 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
2172 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
2173 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
2174 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
2175 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
2176 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
2177 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
2178
2179 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
2180 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
2181 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
2182 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
2183 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
2184 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
2185 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
2186 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
2187
2188 MMIO_D(PF_CTL(PIPE_A), D_ALL);
2189 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
2190 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
2191 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
2192 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
2193
2194 MMIO_D(PF_CTL(PIPE_B), D_ALL);
2195 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
2196 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
2197 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
2198 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
2199
2200 MMIO_D(PF_CTL(PIPE_C), D_ALL);
2201 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
2202 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
2203 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
2204 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
2205
2206 MMIO_D(WM0_PIPEA_ILK, D_ALL);
2207 MMIO_D(WM0_PIPEB_ILK, D_ALL);
2208 MMIO_D(WM0_PIPEC_IVB, D_ALL);
2209 MMIO_D(WM1_LP_ILK, D_ALL);
2210 MMIO_D(WM2_LP_ILK, D_ALL);
2211 MMIO_D(WM3_LP_ILK, D_ALL);
2212 MMIO_D(WM1S_LP_ILK, D_ALL);
2213 MMIO_D(WM2S_LP_IVB, D_ALL);
2214 MMIO_D(WM3S_LP_IVB, D_ALL);
2215
2216 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
2217 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
2218 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
2219 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
2220
c20164db 2221 MMIO_D(_MMIO(0x48268), D_ALL);
e39c5add 2222
04d348ae
ZW		 2223 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2224 gmbus_mmio_write);
336662e5 2225 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
c20164db 2226 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add 2227
c20164db 2228 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
04d348ae 2229 dp_aux_ch_ctl_mmio_write);
c20164db 2230 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
04d348ae 2231 dp_aux_ch_ctl_mmio_write);
c20164db 2232 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
04d348ae 2233 dp_aux_ch_ctl_mmio_write);
e39c5add 2234
75e64ff2 2235 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
e39c5add 2236
c20164db
ZW		 2237 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2238 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
e39c5add 2239
04d348ae
ZW		 2240 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2241 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2242 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2243 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2244 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2245 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2246 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2247 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2248 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
e39c5add 2249
c20164db
ZW		 2250 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
2251 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
2252 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
2253 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
2254 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
2255 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
2256 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
2257
2258 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
2259 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2260 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2261 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2262 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2263 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2264 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2265
2266 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2267 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2268 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2269 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2270 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2271 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2272 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2273 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
e39c5add
ZW		 2274
2275 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2276 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2277 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2278
2279 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2280 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2281 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2282
2283 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2284 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2285 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2286
2287 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2288 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2289 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2290
c20164db
ZW		 2291 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2292 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2293 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2294 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2295 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2296 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
e39c5add 2297
04d348ae 2298 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
e39c5add
ZW		 2299 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2300 MMIO_D(PCH_PP_STATUS, D_ALL);
2301 MMIO_D(PCH_LVDS, D_ALL);
c20164db
ZW		 2302 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2303 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2304 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2305 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2306 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2307 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
e39c5add
ZW		 2308 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2309 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2310 MMIO_D(PCH_DPLL_SEL, D_ALL);
2311
c20164db
ZW		 2312 MMIO_D(_MMIO(0x61208), D_ALL);
2313 MMIO_D(_MMIO(0x6120c), D_ALL);
e39c5add
ZW		 2314 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2315 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2316
c20164db
ZW		 2317 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2318 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2319 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2320 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2321 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2322 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
e39c5add
ZW		 2323
2324 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2325 PORTA_HOTPLUG_STATUS_MASK
2326 | PORTB_HOTPLUG_STATUS_MASK
2327 | PORTC_HOTPLUG_STATUS_MASK
2328 | PORTD_HOTPLUG_STATUS_MASK,
2329 NULL, NULL);
2330
04d348ae 2331 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
e39c5add
ZW		 2332 MMIO_D(FUSE_STRAP, D_ALL);
2333 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2334
2335 MMIO_D(DISP_ARB_CTL, D_ALL);
2336 MMIO_D(DISP_ARB_CTL2, D_ALL);
2337
2338 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2339 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2340 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2341
2342 MMIO_D(SOUTH_CHICKEN1, D_ALL);
04d348ae 2343 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
c20164db
ZW		 2344 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2345 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
e39c5add 2346 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
c20164db
ZW		 2347 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2348 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
e39c5add
ZW		 2349
2350 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2351 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2352 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2353 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2354 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2355 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2356 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2357
2358 MMIO_D(IPS_CTL, D_ALL);
2359
2360 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2361 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2362 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2363 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2364 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2365 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2366 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2367 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2368 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2369 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2370 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2371 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2372 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2373
2374 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2375 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2376 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2377 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2378 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2379 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2380 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2381 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2382 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2383 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2384 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2385 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2386 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2387
2388 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2389 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2390 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2391 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2392 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2393 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2394 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2395 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2396 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2397 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2398 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2399 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2400 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2401
04d348ae
ZW		 2402 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2403 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2404 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2405
2406 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2407 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2408 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2409
2410 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2411 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2412 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2413
c20164db
ZW		 2414 MMIO_D(_MMIO(0x60110), D_ALL);
2415 MMIO_D(_MMIO(0x61110), D_ALL);
2416 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2417 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2418 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2419 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2420 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2421 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2422 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2423 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2424 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
e39c5add 2425
0560b0c6
VS		 2426 MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
2427 MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
2428 MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
e39c5add 2429 MMIO_D(SPLL_CTL, D_ALL);
c20164db
ZW		 2430 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2431 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
e39c5add
ZW		 2432 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2433 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2434 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2435 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2436 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2437 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2438 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2439 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2440
2441 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
c20164db 2442 MMIO_D(_MMIO(0x46508), D_ALL);
e39c5add 2443
c20164db
ZW		 2444 MMIO_D(_MMIO(0x49080), D_ALL);
2445 MMIO_D(_MMIO(0x49180), D_ALL);
2446 MMIO_D(_MMIO(0x49280), D_ALL);
e39c5add 2447
c20164db
ZW		 2448 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2449 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2450 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 2451
2452 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2453 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2454 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2455
e39c5add
ZW		 2456 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2457 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2458 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2459
2460 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2461 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2462 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2463
2464 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2465 MMIO_D(SBI_ADDR, D_ALL);
04d348ae
ZW		 2466 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2467 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
e39c5add
ZW		 2468 MMIO_D(PIXCLK_GATE, D_ALL);
2469
c20164db 2470 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
04d348ae
ZW		 2471 dp_aux_ch_ctl_mmio_write);
2472
2473 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2474 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2475 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2476 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2477 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2478
2479 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2480 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2481 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2482 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2483 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2484
2485 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2486 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2487 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2488 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2489 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
e39c5add 2490
c20164db
ZW		 2491 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2492 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2493 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2494 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2495 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 2496
2497 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2498 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
b2744f86 2499 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
e39c5add 2500
c20164db
ZW		 2501 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2502 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2503 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2504 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
e39c5add 2505
c20164db
ZW		 2506 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2507 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2508 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2509 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
e39c5add
ZW		 2510
2511 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2512 MMIO_D(FORCEWAKE_ACK, D_ALL);
2513 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2514 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
0aa5277c
ZY		 2515 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2516 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add 2517 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
a1dcba90 2518 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
e39c5add
ZW		 2519 MMIO_D(ECOBUS, D_ALL);
2520 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2521 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2522 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2523 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2524 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2525 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2526 MMIO_D(GEN6_RPSTAT1, D_ALL);
2527 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2528 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2529 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2530 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2531 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2532 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2533 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2534 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2535 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2536 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2537 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2538 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2539 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2540 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2541 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2542 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2543 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2544 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2545 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2546 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2547 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2548 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2549 MMIO_D(GEN6_PMINTRMSK, D_ALL);
75e39688
ID		 2550 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2551 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2552 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2553 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
a1dcba90 2554 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2555 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
e39c5add
ZW		 2556
2557 MMIO_D(RSTDBYCTL, D_ALL);
2558
2559 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2560 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
04d348ae 2561 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
e39c5add 2562
e39c5add
ZW		 2563 MMIO_D(TILECTL, D_ALL);
2564
2565 MMIO_D(GEN6_UCGCTL1, D_ALL);
2566 MMIO_D(GEN6_UCGCTL2, D_ALL);
2567
c20164db 2568 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add 2569
e39c5add 2570 MMIO_D(GEN6_PCODE_DATA, D_ALL);
c20164db 2571 MMIO_D(_MMIO(0x13812c), D_ALL);
e39c5add
ZW		 2572 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2573 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2574 MMIO_D(HSW_IDICR, D_ALL);
2575 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2576
c20164db
ZW		 2577 MMIO_D(_MMIO(0x3c), D_ALL);
2578 MMIO_D(_MMIO(0x860), D_ALL);
e39c5add 2579 MMIO_D(ECOSKPD, D_ALL);
c20164db 2580 MMIO_D(_MMIO(0x121d0), D_ALL);
e39c5add 2581 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
c20164db 2582 MMIO_D(_MMIO(0x41d0), D_ALL);
e39c5add 2583 MMIO_D(GAC_ECO_BITS, D_ALL);
c20164db
ZW		 2584 MMIO_D(_MMIO(0x6200), D_ALL);
2585 MMIO_D(_MMIO(0x6204), D_ALL);
2586 MMIO_D(_MMIO(0x6208), D_ALL);
2587 MMIO_D(_MMIO(0x7118), D_ALL);
2588 MMIO_D(_MMIO(0x7180), D_ALL);
2589 MMIO_D(_MMIO(0x7408), D_ALL);
2590 MMIO_D(_MMIO(0x7c00), D_ALL);
975629c3 2591 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
c20164db
ZW		 2592 MMIO_D(_MMIO(0x911c), D_ALL);
2593 MMIO_D(_MMIO(0x9120), D_ALL);
a045fba4 2594 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2595
2596 MMIO_D(GAB_CTL, D_ALL);
c20164db
ZW		 2597 MMIO_D(_MMIO(0x48800), D_ALL);
2598 MMIO_D(_MMIO(0xce044), D_ALL);
2599 MMIO_D(_MMIO(0xe6500), D_ALL);
2600 MMIO_D(_MMIO(0xe6504), D_ALL);
2601 MMIO_D(_MMIO(0xe6600), D_ALL);
2602 MMIO_D(_MMIO(0xe6604), D_ALL);
2603 MMIO_D(_MMIO(0xe6700), D_ALL);
2604 MMIO_D(_MMIO(0xe6704), D_ALL);
2605 MMIO_D(_MMIO(0xe6800), D_ALL);
2606 MMIO_D(_MMIO(0xe6804), D_ALL);
e39c5add
ZW		 2607 MMIO_D(PCH_GMBUS4, D_ALL);
2608 MMIO_D(PCH_GMBUS5, D_ALL);
2609
c20164db
ZW		 2610 MMIO_D(_MMIO(0x902c), D_ALL);
2611 MMIO_D(_MMIO(0xec008), D_ALL);
2612 MMIO_D(_MMIO(0xec00c), D_ALL);
2613 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2614 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2615 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2616 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2617 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2618 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2619 MMIO_D(_MMIO(0xec408), D_ALL);
2620 MMIO_D(_MMIO(0xec40c), D_ALL);
2621 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2622 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2623 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2624 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2625 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2626 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2627 MMIO_D(_MMIO(0xfc810), D_ALL);
2628 MMIO_D(_MMIO(0xfc81c), D_ALL);
2629 MMIO_D(_MMIO(0xfc828), D_ALL);
2630 MMIO_D(_MMIO(0xfc834), D_ALL);
2631 MMIO_D(_MMIO(0xfcc00), D_ALL);
2632 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2633 MMIO_D(_MMIO(0xfcc18), D_ALL);
2634 MMIO_D(_MMIO(0xfcc24), D_ALL);
2635 MMIO_D(_MMIO(0xfd000), D_ALL);
2636 MMIO_D(_MMIO(0xfd00c), D_ALL);
2637 MMIO_D(_MMIO(0xfd018), D_ALL);
2638 MMIO_D(_MMIO(0xfd024), D_ALL);
2639 MMIO_D(_MMIO(0xfd034), D_ALL);
e39c5add
ZW		 2640
2641 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
c20164db
ZW		 2642 MMIO_D(_MMIO(0x2054), D_ALL);
2643 MMIO_D(_MMIO(0x12054), D_ALL);
2644 MMIO_D(_MMIO(0x22054), D_ALL);
2645 MMIO_D(_MMIO(0x1a054), D_ALL);
2646
2647 MMIO_D(_MMIO(0x44070), D_ALL);
2648 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2649 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2650 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2651 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2652 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2653
2654 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2655 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2656 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2657 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2658 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2659 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2660
2661 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2662 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 2663 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2664
2665 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2666 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2667 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2668 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2669 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2670 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2671 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2672 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2673 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2674 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2675 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
c20164db
ZW		 2676 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2677 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2678 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2679 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2680 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2681 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add 2682
9112caaf
ZY		 2683 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2684 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
c20164db
ZW		 2685 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2686 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2687 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
9112caaf
ZY		 2688 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2689 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
c20164db
ZW		 2690 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2691 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2692 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2693 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
5e7154ff
LZ		 2694
2695 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2696 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
5e822e44
GF		 2697 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2698
12d14cc4
ZW		 2699 return 0;
2700}
2701
72588ffd 2702static int init_bdw_mmio_info(struct intel_gvt *gvt)
12d14cc4 2703{
a61ac1e7 2704 struct drm_i915_private *dev_priv = gvt->gt->i915;
12d14cc4
ZW		 2705 int ret;
2706
e39c5add
ZW		 2707 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2708 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2709 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2710 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2711
2712 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2713 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2714 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2715 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2716
2717 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2718 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2719 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2720 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2721
2722 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2723 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2724 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2725 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2726
2727 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2728 intel_vgpu_reg_imr_handler);
2729 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2730 intel_vgpu_reg_ier_handler);
2731 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2732 intel_vgpu_reg_iir_handler);
2733 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2734
2735 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2736 intel_vgpu_reg_imr_handler);
2737 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2738 intel_vgpu_reg_ier_handler);
2739 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2740 intel_vgpu_reg_iir_handler);
2741 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2742
2743 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2744 intel_vgpu_reg_imr_handler);
2745 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2746 intel_vgpu_reg_ier_handler);
2747 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2748 intel_vgpu_reg_iir_handler);
2749 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2750
2751 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2752 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2753 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2754 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2755
2756 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2757 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2758 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2759 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2760
2761 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2762 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2763 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2764 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2765
2766 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2767 intel_vgpu_reg_master_irq_handler);
2768
894e287b
XZ		 2769 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2770 mmio_read_from_hw, NULL);
e39c5add 2771
c20164db 2772#define RING_REG(base) _MMIO((base) + 0xd0)
2fb39fad
DC		 2773 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2774 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2775 ring_reset_ctl_write);
2fb39fad
DC		 2776#undef RING_REG
2777
c20164db 2778#define RING_REG(base) _MMIO((base) + 0x230)
28c4c6ca 2779 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
e39c5add
ZW		 2780#undef RING_REG
2781
c20164db 2782#define RING_REG(base) _MMIO((base) + 0x234)
0aa5277c
ZY		 2783 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2784 NULL, NULL);
e39c5add
ZW		 2785#undef RING_REG
2786
c20164db 2787#define RING_REG(base) _MMIO((base) + 0x244)
0aa5277c 2788 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2789#undef RING_REG
2790
c20164db 2791#define RING_REG(base) _MMIO((base) + 0x370)
e39c5add 2792 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2793#undef RING_REG
2794
c20164db 2795#define RING_REG(base) _MMIO((base) + 0x3a0)
e39c5add 2796 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
e39c5add
ZW		 2797#undef RING_REG
2798
2799 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2800 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2801 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
c20164db 2802 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
e39c5add
ZW		 2803 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2804 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
c20164db 2805 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
e39c5add 2806
8bcd7c18
WL		 2807 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2808
e39c5add
ZW		 2809 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2810 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2811
2812 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2813
c20164db 2814#define RING_REG(base) _MMIO((base) + 0x270)
bec3df93 2815 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2816#undef RING_REG
2817
a2ae95af 2818 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
e39c5add 2819
a045fba4 2820 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add 2821
593e59b4
ZY		 2822 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2823 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2824 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
e39c5add
ZW		 2825
2826 MMIO_D(WM_MISC, D_BDW);
4ab4fa10 2827 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
e39c5add 2828
b2744f86 2829 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
c20164db
ZW		 2830 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2831 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
e39c5add
ZW		 2832
2833 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2834
2835 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2836 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2837 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2838
c20164db 2839 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
0aa5277c
ZY		 2840 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2841 NULL, NULL);
2842 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2843 NULL, NULL);
2844 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add 2845
c20164db
ZW		 2846 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2847 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2848 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
c20164db
ZW		 2849 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2850 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2851 MMIO_D(_MMIO(0xb110), D_BDW);
e39c5add 2852
c20164db 2853 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
e6cedfea 2854 NULL, force_nonpriv_write);
e39c5add 2855
c20164db
ZW		 2856 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2857 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
593e59b4 2858
c20164db 2859 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2860 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2861
c20164db 2862 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2863
c20164db 2864 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
e39c5add 2865
c20164db 2866 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
e39c5add 2867
c20164db
ZW		 2868 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2869 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
e39c5add 2870
c20164db
ZW		 2871 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2872 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
a045fba4 2873 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db
ZW		 2874 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2875
2876 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2877
2878 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2879 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2880 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2881 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2882 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2883 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2884 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2885 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2886 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
ba0a64bc 2887 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
12d14cc4
ZW		 2888 return 0;
2889}
2890
e39c5add
ZW		 2891static int init_skl_mmio_info(struct intel_gvt *gvt)
2892{
a61ac1e7 2893 struct drm_i915_private *dev_priv = gvt->gt->i915;
e39c5add
ZW		 2894 int ret;
2895
2896 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2897 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2898 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2899 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2900 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2901 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2902
47c41af7 2903 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
5cf5fe8f 2904 dp_aux_ch_ctl_mmio_write);
47c41af7 2905 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
5cf5fe8f 2906 dp_aux_ch_ctl_mmio_write);
47c41af7 2907 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
5cf5fe8f
XH		 2908 dp_aux_ch_ctl_mmio_write);
2909
75e39688
ID		 2910 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2911 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
e39c5add 2912
2570b7e3 2913 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
9174c1d6 2914
43226e6f 2915 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
e39c5add
ZW		 2916 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2917 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
a045fba4 2918 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
43226e6f
XZ		 2919 MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
2920 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2921 MMIO_D(DC_STATE_EN, D_SKL_PLUS);
2922 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
2923 MMIO_D(CDCLK_CTL, D_SKL_PLUS);
2924 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2925 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2926 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
2927 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
2928 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
2929 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
2930 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
2931 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
2932 MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
2933 MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
2934 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
5cf5fe8f
XH		 2935
2936 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2937 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2938 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2939 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2940 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2941 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2942
2943 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2944 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2945 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2946 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2947 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2948 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2949
2950 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2951 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2952 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2953 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2954 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2955 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2956
2957 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2958 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2959 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2960 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2961
2962 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2963 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2964 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2965 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2966
2967 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2968 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2969 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2970 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2971
2972 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2973 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2974 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2975
2976 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2977 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2978 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2979
2980 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2981 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2982 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2983
2984 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2985 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2986 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2987
2988 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2989 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2990 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2991
2992 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2993 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2994 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2995
2996 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2997 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2998 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2999
3000 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3001 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3002 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3003
3004 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
3005 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
3006 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
3007
3008 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
3009 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
3010 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
3011 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
3012
3013 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
3014 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
3015 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
3016 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
3017
3018 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3019 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3020 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3021 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
3022
c20164db
ZW		 3023 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3024 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3025 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3026 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3027
c20164db
ZW		 3028 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3029 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3030 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3031 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3032
c20164db
ZW		 3033 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3034 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3035 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3036 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3037
c20164db
ZW		 3038 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3039 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3040 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3041 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3042
c20164db
ZW		 3043 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3044 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3045 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3046 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3047
c20164db
ZW		 3048 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3049 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3050 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3051 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3052
43226e6f
XZ		 3053 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
3054 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
c20164db 3055 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
b2744f86 3056 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
43226e6f 3057 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
5cf5fe8f 3058
43226e6f
XZ		 3059 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
3060 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
3061 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
5cf5fe8f 3062
3fcb01f8 3063 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
5cf5fe8f 3064
43226e6f
XZ		 3065 MMIO_D(SKL_DFSM, D_SKL_PLUS);
3066 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
5cf5fe8f 3067
43226e6f 3068 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
d71cb712 3069 NULL, NULL);
43226e6f 3070 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
d71cb712 3071 NULL, NULL);
5cf5fe8f 3072
b2744f86 3073 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
c20164db 3074 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
b2744f86 3075 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
3fcb01f8
WL		 3076 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
3077 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
43226e6f 3078 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
d71cb712 3079 NULL, NULL);
e39c5add
ZW		 3080
3081 /* TRTT */
43226e6f
XZ		 3082 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3083 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3084 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3085 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3086 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3087 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
d71cb712
CX		 3088 NULL, gen9_trtte_write);
3089 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
e39c5add 3090
d71cb712 3091 MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
e39c5add 3092
d71cb712 3093 MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
e39c5add 3094
d71cb712 3095 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3fcb01f8 3096 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 3097 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3098
c20164db 3099 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
43226e6f 3100 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
d71cb712
CX		 3101 MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
3102 MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
3103 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
3104 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
3105 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
3106 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
3107 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
3108 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
c20164db
ZW		 3109
3110 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
3111 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
3112 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
3113
3114 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
3115 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
3116 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
03fa9350
PZ		 3117 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
3118 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
3119 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
c20164db
ZW		 3120 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
3121 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
3122 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
3123
3124 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
cb2808da
CX		 3125#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
3126 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3127 NULL, csfe_chicken1_mmio_write);
3128#undef CSFE_CHICKEN1_REG
d71cb712 3129 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
b9b824a5
CX		 3130 NULL, NULL);
3131 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3132 NULL, NULL);
5cf5fe8f 3133
43226e6f
XZ		 3134 MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
3135 MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
d71cb712
CX		 3136
3137 return 0;
3138}
3139
3140static int init_bxt_mmio_info(struct intel_gvt *gvt)
3141{
a61ac1e7 3142 struct drm_i915_private *dev_priv = gvt->gt->i915;
d71cb712
CX		 3143 int ret;
3144
3145 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
3146
3147 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
3148 MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
3149 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
3150 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
3151 MMIO_D(ERROR_GEN6, D_BXT);
3152 MMIO_D(DONE_REG, D_BXT);
3153 MMIO_D(EIR, D_BXT);
3154 MMIO_D(PGTBL_ER, D_BXT);
3155 MMIO_D(_MMIO(0x4194), D_BXT);
3156 MMIO_D(_MMIO(0x4294), D_BXT);
3157 MMIO_D(_MMIO(0x4494), D_BXT);
3158
3159 MMIO_RING_D(RING_PSMI_CTL, D_BXT);
3160 MMIO_RING_D(RING_DMA_FADD, D_BXT);
3161 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
3162 MMIO_RING_D(RING_IPEHR, D_BXT);
3163 MMIO_RING_D(RING_INSTPS, D_BXT);
3164 MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
3165 MMIO_RING_D(RING_BBSTATE, D_BXT);
3166 MMIO_RING_D(RING_IPEIR, D_BXT);
3167
3168 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
3169
3170 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
3171 MMIO_D(BXT_RP_STATE_CAP, D_BXT);
3172 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
3173 NULL, bxt_phy_ctl_family_write);
3174 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
3175 NULL, bxt_phy_ctl_family_write);
3176 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
3177 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
3178 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
3179 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
3180 NULL, bxt_port_pll_enable_write);
3181 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
3182 NULL, bxt_port_pll_enable_write);
3183 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
3184 bxt_port_pll_enable_write);
3185
3186 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
3187 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
3188 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
3189 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
3190 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
3191 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
3192 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
3193 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
3194 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
3195
3196 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
3197 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
3198 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
3199 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
3200 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
3201 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
3202 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
3203 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
3204 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
3205
3206 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
3207 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
3208 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3209 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3210 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3211 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
3212 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
3213 NULL, bxt_pcs_dw12_grp_write);
3214 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3215 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3216 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
3217 bxt_port_tx_dw3_read, NULL);
3218 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3219 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3220 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3221 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3222 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3223 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3224 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3225 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3226 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3227 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3228 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3229 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
3230 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
3231 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
3232 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
3233
3234 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
3235 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
3236 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3237 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3238 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3239 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
3240 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
3241 NULL, bxt_pcs_dw12_grp_write);
3242 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3243 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3244 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
3245 bxt_port_tx_dw3_read, NULL);
3246 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3247 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3248 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3249 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3250 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3251 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3252 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3253 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3254 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3255 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3256 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3257 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
3258 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
3259 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
3260 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
3261
3262 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
3263 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
3264 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3265 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3266 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3267 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
3268 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
3269 NULL, bxt_pcs_dw12_grp_write);
3270 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3271 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3272 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
3273 bxt_port_tx_dw3_read, NULL);
3274 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3275 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3276 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3277 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3278 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3279 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3280 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3281 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3282 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3283 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3284 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3285 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
3286 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
3287 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
3288 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
3289
3290 MMIO_D(BXT_DE_PLL_CTL, D_BXT);
3291 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
3292 MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
3293 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3294
3295 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
d817de3b 3296 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
d71cb712
CX		 3297
3298 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3299 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3300 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3301
3302 MMIO_D(RC6_CTX_BASE, D_BXT);
3303
3304 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
3305 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3306 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3307 MMIO_D(GEN6_GFXPAUSE, D_BXT);
3fcb01f8 3308 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
d71cb712
CX		 3309
3310 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
5cf5fe8f 3311
e39c5add
ZW		 3312 return 0;
3313}
04d348ae 3314
65f9f6fe
CD		 3315static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3316 unsigned int offset)
3317{
3318 unsigned long device = intel_gvt_get_device_type(gvt);
02b6ed44
TZ		 3319 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3320 int num = gvt->mmio.num_mmio_block;
65f9f6fe 3321 int i;
12d14cc4 3322
02b6ed44 3323 for (i = 0; i < num; i++, block++) {
65f9f6fe
CD		 3324 if (!(device & block->device))
3325 continue;
c20164db
ZW		 3326 if (offset >= i915_mmio_reg_offset(block->offset) &&
3327 offset < i915_mmio_reg_offset(block->offset) + block->size)
65f9f6fe 3328 return block;
12d14cc4
ZW		 3329 }
3330 return NULL;
3331}
3332
3333/**
3334 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
3335 * @gvt: GVT device
3336 *
3337 * This function is called at the driver unloading stage, to clean up the MMIO
3338 * information table of GVT device
3339 *
3340 */
3341void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
3342{
3343 struct hlist_node *tmp;
3344 struct intel_gvt_mmio_info *e;
3345 int i;
3346
3347 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
3348 kfree(e);
3349
3350 vfree(gvt->mmio.mmio_attribute);
3351 gvt->mmio.mmio_attribute = NULL;
3352}
3353
02b6ed44
TZ		 3354/* Special MMIO blocks. */
3355static struct gvt_mmio_block mmio_blocks[] = {
3356 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
8631fef7 3357 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
02b6ed44
TZ		 3358 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
3359 pvinfo_mmio_read, pvinfo_mmio_write},
3360 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3361 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3362 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3363};
3364
12d14cc4
ZW		 3365/**
3366 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
3367 * @gvt: GVT device
3368 *
3369 * This function is called at the initialization stage, to setup the MMIO
3370 * information table for GVT device
3371 *
3372 * Returns:
3373 * zero on success, negative if failed.
3374 */
3375int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
3376{
3377 struct intel_gvt_device_info *info = &gvt->device_info;
a61ac1e7 3378 struct drm_i915_private *i915 = gvt->gt->i915;
56a78de5 3379 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
12d14cc4
ZW		 3380 int ret;
3381
56a78de5 3382 gvt->mmio.mmio_attribute = vzalloc(size);
12d14cc4
ZW		 3383 if (!gvt->mmio.mmio_attribute)
3384 return -ENOMEM;
3385
3386 ret = init_generic_mmio_info(gvt);
3387 if (ret)
3388 goto err;
3389
a61ac1e7 3390 if (IS_BROADWELL(i915)) {
72588ffd 3391 ret = init_bdw_mmio_info(gvt);
12d14cc4
ZW		 3392 if (ret)
3393 goto err;
a61ac1e7
CW		 3394 } else if (IS_SKYLAKE(i915) ||
3395 IS_KABYLAKE(i915) ||
3396 IS_COFFEELAKE(i915)) {
72588ffd 3397 ret = init_bdw_mmio_info(gvt);
e39c5add
ZW		 3398 if (ret)
3399 goto err;
3400 ret = init_skl_mmio_info(gvt);
3401 if (ret)
3402 goto err;
a61ac1e7 3403 } else if (IS_BROXTON(i915)) {
72588ffd 3404 ret = init_bdw_mmio_info(gvt);
d71cb712
CX		 3405 if (ret)
3406 goto err;
3407 ret = init_skl_mmio_info(gvt);
3408 if (ret)
3409 goto err;
3410 ret = init_bxt_mmio_info(gvt);
3411 if (ret)
3412 goto err;
12d14cc4 3413 }
fbfd76c3 3414
02b6ed44
TZ		 3415 gvt->mmio.mmio_block = mmio_blocks;
3416 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
3417
12d14cc4
ZW		 3418 return 0;
3419err:
3420 intel_gvt_clean_mmio_info(gvt);
3421 return ret;
3422}
e39c5add 3423
7cb16018
CD		 3424/**
3425 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3426 * @gvt: a GVT device
3427 * @handler: the handler
3428 * @data: private data given to handler
3429 *
3430 * Returns:
3431 * Zero on success, negative error code if failed.
3432 */
3433int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3434 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3435 void *data)
3436{
3437 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3438 struct intel_gvt_mmio_info *e;
3439 int i, j, ret;
3440
3441 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3442 ret = handler(gvt, e->offset, data);
3443 if (ret)
3444 return ret;
3445 }
3446
3447 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
83faaf07
TZ		 3448 /* pvinfo data doesn't come from hw mmio */
3449 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3450 continue;
3451
7cb16018
CD		 3452 for (j = 0; j < block->size; j += 4) {
3453 ret = handler(gvt,
c20164db
ZW		 3454 i915_mmio_reg_offset(block->offset) + j,
3455 data);
7cb16018
CD		 3456 if (ret)
3457 return ret;
3458 }
3459 }
3460 return 0;
3461}
e39c5add
ZW		 3462
3463/**
3464 * intel_vgpu_default_mmio_read - default MMIO read handler
3465 * @vgpu: a vGPU
3466 * @offset: access offset
3467 * @p_data: data return buffer
3468 * @bytes: access data length
3469 *
3470 * Returns:
3471 * Zero on success, negative error code if failed.
3472 */
3473int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3474 void *p_data, unsigned int bytes)
3475{
3476 read_vreg(vgpu, offset, p_data, bytes);
3477 return 0;
3478}
3479
3480/**
3481 * intel_t_default_mmio_write - default MMIO write handler
3482 * @vgpu: a vGPU
3483 * @offset: access offset
3484 * @p_data: write data buffer
3485 * @bytes: access data length
3486 *
3487 * Returns:
3488 * Zero on success, negative error code if failed.
3489 */
3490int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3491 void *p_data, unsigned int bytes)
3492{
3493 write_vreg(vgpu, offset, p_data, bytes);
3494 return 0;
3495}
4938ca90 3496
6cef21a1
HY		 3497/**
3498 * intel_vgpu_mask_mmio_write - write mask register
3499 * @vgpu: a vGPU
3500 * @offset: access offset
3501 * @p_data: write data buffer
3502 * @bytes: access data length
3503 *
3504 * Returns:
3505 * Zero on success, negative error code if failed.
3506 */
3507int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3508 void *p_data, unsigned int bytes)
3509{
3510 u32 mask, old_vreg;
3511
3512 old_vreg = vgpu_vreg(vgpu, offset);
3513 write_vreg(vgpu, offset, p_data, bytes);
3514 mask = vgpu_vreg(vgpu, offset) >> 16;
3515 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3516 (vgpu_vreg(vgpu, offset) & mask);
3517
3518 return 0;
3519}
3520
4938ca90
ZY		 3521/**
3522 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3523 * force-nopriv register
3524 *
3525 * @gvt: a GVT device
3526 * @offset: register offset
3527 *
3528 * Returns:
3529 * True if the register is in force-nonpriv whitelist;
3530 * False if outside;
3531 */
3532bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3533 unsigned int offset)
3534{
3535 return in_whitelist(offset);
3536}
65f9f6fe
CD		 3537
3538/**
3539 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3540 * @vgpu: a vGPU
3541 * @offset: register offset
3542 * @pdata: data buffer
3543 * @bytes: data length
a752b070 3544 * @is_read: read or write
65f9f6fe
CD		 3545 *
3546 * Returns:
3547 * Zero on success, negative error code if failed.
3548 */
3549int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3550 void *pdata, unsigned int bytes, bool is_read)
3551{
a61ac1e7 3552 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
65f9f6fe
CD		 3553 struct intel_gvt *gvt = vgpu->gvt;
3554 struct intel_gvt_mmio_info *mmio_info;
3555 struct gvt_mmio_block *mmio_block;
3556 gvt_mmio_func func;
3557 int ret;
3558
12d58619 3559 if (drm_WARN_ON(&i915->drm, bytes > 8))
65f9f6fe
CD		 3560 return -EINVAL;
3561
3562 /*
3563 * Handle special MMIO blocks.
3564 */
3565 mmio_block = find_mmio_block(gvt, offset);
3566 if (mmio_block) {
3567 func = is_read ? mmio_block->read : mmio_block->write;
3568 if (func)
3569 return func(vgpu, offset, pdata, bytes);
3570 goto default_rw;
3571 }
3572
3573 /*
3574 * Normal tracked MMIOs.
3575 */
3576 mmio_info = find_mmio_info(gvt, offset);
3577 if (!mmio_info) {
b99f514f 3578 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
65f9f6fe
CD		 3579 goto default_rw;
3580 }
3581
65f9f6fe
CD		 3582 if (is_read)
3583 return mmio_info->read(vgpu, offset, pdata, bytes);
3584 else {
3585 u64 ro_mask = mmio_info->ro_mask;
9c1c8416 3586 u32 old_vreg = 0;
65f9f6fe
CD		 3587 u64 data = 0;
3588
3589 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3590 old_vreg = vgpu_vreg(vgpu, offset);
65f9f6fe
CD		 3591 }
3592
3593 if (likely(!ro_mask))
3594 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3595 else if (!~ro_mask) {
3596 gvt_vgpu_err("try to write RO reg %x\n", offset);
3597 return 0;
3598 } else {
3599 /* keep the RO bits in the virtual register */
3600 memcpy(&data, pdata, bytes);
3601 data &= ~ro_mask;
3602 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3603 ret = mmio_info->write(vgpu, offset, &data, bytes);
3604 }
3605
3606 /* higher 16bits of mode ctl regs are mask bits for change */
3607 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3608 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3609
3610 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3611 | (vgpu_vreg(vgpu, offset) & mask);
65f9f6fe
CD		 3612 }
3613 }
3614
3615 return ret;
3616
3617default_rw:
3618 return is_read ?
3619 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3620 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3621}
Linux 6.x block layer and io_uring tree(s)