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drm/i915/gvt: Wean gvt off dev_priv->engine[]
[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / handlers.c
CommitLineData
12d14cc4
ZW		 1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39#include "i915_drv.h"
feddf6e8
ZW		 40#include "gvt.h"
41#include "i915_pvinfo.h"
12d14cc4 42
e39c5add
ZW		 43/* XXX FIXME i915 has changed PP_XXX definition */
44#define PCH_PP_STATUS _MMIO(0xc7200)
45#define PCH_PP_CONTROL _MMIO(0xc7204)
46#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48#define PCH_PP_DIVISOR _MMIO(0xc7210)
49
12d14cc4
ZW		 50unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
51{
52 if (IS_BROADWELL(gvt->dev_priv))
53 return D_BDW;
54 else if (IS_SKYLAKE(gvt->dev_priv))
55 return D_SKL;
e3476c00
XH		 56 else if (IS_KABYLAKE(gvt->dev_priv))
57 return D_KBL;
2939db9e
CX		 58 else if (IS_BROXTON(gvt->dev_priv))
59 return D_BXT;
36520ed0 60 else if (IS_COFFEELAKE(gvt->dev_priv))
61 return D_CFL;
12d14cc4
ZW		 62
63 return 0;
64}
65
66bool intel_gvt_match_device(struct intel_gvt *gvt,
67 unsigned long device)
68{
69 return intel_gvt_get_device_type(gvt) & device;
70}
71
e39c5add
ZW		 72static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
73 void *p_data, unsigned int bytes)
74{
75 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
76}
77
78static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
79 void *p_data, unsigned int bytes)
80{
81 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
82}
83
65f9f6fe
CD		 84static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt,
85 unsigned int offset)
86{
87 struct intel_gvt_mmio_info *e;
88
89 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
90 if (e->offset == offset)
91 return e;
92 }
93 return NULL;
94}
95
12d14cc4 96static int new_mmio_info(struct intel_gvt *gvt,
56a78de5 97 u32 offset, u8 flags, u32 size,
12d14cc4 98 u32 addr_mask, u32 ro_mask, u32 device,
65f9f6fe 99 gvt_mmio_func read, gvt_mmio_func write)
12d14cc4
ZW		 100{
101 struct intel_gvt_mmio_info *info, *p;
102 u32 start, end, i;
103
104 if (!intel_gvt_match_device(gvt, device))
105 return 0;
106
107 if (WARN_ON(!IS_ALIGNED(offset, 4)))
108 return -EINVAL;
109
110 start = offset;
111 end = offset + size;
112
113 for (i = start; i < end; i += 4) {
114 info = kzalloc(sizeof(*info), GFP_KERNEL);
115 if (!info)
116 return -ENOMEM;
117
118 info->offset = i;
65f9f6fe 119 p = find_mmio_info(gvt, info->offset);
36ed7e97
JJC		 120 if (p) {
121 WARN(1, "dup mmio definition offset %x\n",
12d14cc4 122 info->offset);
36ed7e97
JJC		 123 kfree(info);
124
125 /* We return -EEXIST here to make GVT-g load fail.
126 * So duplicated MMIO can be found as soon as
127 * possible.
128 */
129 return -EEXIST;
130 }
d8d94ba3 131
4ec3dd89 132 info->ro_mask = ro_mask;
12d14cc4 133 info->device = device;
e39c5add
ZW		 134 info->read = read ? read : intel_vgpu_default_mmio_read;
135 info->write = write ? write : intel_vgpu_default_mmio_write;
12d14cc4
ZW		 136 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
137 INIT_HLIST_NODE(&info->node);
138 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
fbfd76c3 139 gvt->mmio.num_tracked_mmio++;
12d14cc4
ZW		 140 }
141 return 0;
142}
143
62a6a537 144/**
8fde4107 145 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
62a6a537
ZW		 146 * @gvt: a GVT device
147 * @offset: register offset
148 *
149 * Returns:
8fde4107 150 * The engine containing the offset within its mmio page.
62a6a537 151 */
8fde4107
CW		 152const struct intel_engine_cs *
153intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
28c4c6ca 154{
0fac21e7
ZW		 155 enum intel_engine_id id;
156 struct intel_engine_cs *engine;
28c4c6ca 157
62a6a537 158 offset &= ~GENMASK(11, 0);
8fde4107 159 for_each_engine(engine, gvt->dev_priv, id)
62a6a537 160 if (engine->mmio_base == offset)
8fde4107
CW		 161 return engine;
162
163 return NULL;
28c4c6ca
ZW		 164}
165
e39c5add
ZW		 166#define offset_to_fence_num(offset) \
167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
168
169#define fence_num_to_offset(num) \
170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
171
fd64be63 172
e011c6ce 173void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
fd64be63
MH		 174{
175 switch (reason) {
176 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
177 pr_err("Detected your guest driver doesn't support GVT-g.\n");
178 break;
a33fc7a0
MH		 179 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
180 pr_err("Graphics resource is not enough for the guest\n");
f745e9cc 181 break;
e011c6ce 182 case GVT_FAILSAFE_GUEST_ERR:
183 pr_err("GVT Internal error for the guest\n");
f745e9cc 184 break;
fd64be63
MH		 185 default:
186 break;
187 }
188 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
189 vgpu->failsafe = true;
190}
191
e39c5add
ZW		 192static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
193 unsigned int fence_num, void *p_data, unsigned int bytes)
194{
c39bca4e
ZW		 195 unsigned int max_fence = vgpu_fence_sz(vgpu);
196
197 if (fence_num >= max_fence) {
b99f514f
CD		 198 gvt_vgpu_err("access oob fence reg %d/%d\n",
199 fence_num, max_fence);
fd64be63
MH		 200
201 /* When guest access oob fence regs without access
202 * pv_info first, we treat guest not supporting GVT,
203 * and we will let vgpu enter failsafe mode.
204 */
d1be371d 205 if (!vgpu->pv_notified)
fd64be63
MH		 206 enter_failsafe_mode(vgpu,
207 GVT_FAILSAFE_UNSUPPORTED_GUEST);
d1be371d 208
e39c5add 209 memset(p_data, 0, bytes);
d1be371d 210 return -EINVAL;
e39c5add
ZW		 211 }
212 return 0;
213}
214
52ca14e6
CD		 215static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
216 unsigned int offset, void *p_data, unsigned int bytes)
217{
218 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
219
220 if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) {
221 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
222 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
223 else if (!ips)
224 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
225 else {
226 /* All engines must be enabled together for vGPU,
227 * since we don't know which engine the ppgtt will
228 * bind to when shadowing.
229 */
230 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
231 ips);
232 return -EINVAL;
233 }
234 }
235
236 write_vreg(vgpu, offset, p_data, bytes);
237 return 0;
238}
239
e39c5add
ZW		 240static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
241 void *p_data, unsigned int bytes)
242{
243 int ret;
244
245 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
246 p_data, bytes);
247 if (ret)
248 return ret;
249 read_vreg(vgpu, off, p_data, bytes);
250 return 0;
251}
252
253static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
254 void *p_data, unsigned int bytes)
255{
9b7bd65e 256 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
e39c5add
ZW		 257 unsigned int fence_num = offset_to_fence_num(off);
258 int ret;
259
260 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
261 if (ret)
262 return ret;
263 write_vreg(vgpu, off, p_data, bytes);
264
9b7bd65e 265 mmio_hw_access_pre(dev_priv);
e39c5add
ZW		 266 intel_vgpu_write_fence(vgpu, fence_num,
267 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
9b7bd65e 268 mmio_hw_access_post(dev_priv);
e39c5add
ZW		 269 return 0;
270}
271
272#define CALC_MODE_MASK_REG(old, new) \
273 (((new) & GENMASK(31, 16)) \
274 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
275 | ((new) & ((new) >> 16))))
276
277static int mul_force_wake_write(struct intel_vgpu *vgpu,
278 unsigned int offset, void *p_data, unsigned int bytes)
279{
280 u32 old, new;
2e679d48 281 u32 ack_reg_offset;
e39c5add
ZW		 282
283 old = vgpu_vreg(vgpu, offset);
284 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
285
c3b5a843 286 if (INTEL_GEN(vgpu->gvt->dev_priv) >= 9) {
e39c5add
ZW		 287 switch (offset) {
288 case FORCEWAKE_RENDER_GEN9_REG:
289 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
290 break;
291 case FORCEWAKE_BLITTER_GEN9_REG:
292 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
293 break;
294 case FORCEWAKE_MEDIA_GEN9_REG:
295 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
296 break;
297 default:
298 /*should not hit here*/
695fbc08 299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
39762ad4 300 return -EINVAL;
e39c5add
ZW		 301 }
302 } else {
303 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
304 }
305
306 vgpu_vreg(vgpu, offset) = new;
307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
308 return 0;
309}
310
311static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
c34eaa8d 312 void *p_data, unsigned int bytes)
e39c5add 313{
3a891a62 314 intel_engine_mask_t engine_mask = 0;
e39c5add 315 u32 data;
e39c5add 316
40d2428b 317 write_vreg(vgpu, offset, p_data, bytes);
e39c5add
ZW		 318 data = vgpu_vreg(vgpu, offset);
319
320 if (data & GEN6_GRDOM_FULL) {
321 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
c34eaa8d
CD		 322 engine_mask = ALL_ENGINES;
323 } else {
324 if (data & GEN6_GRDOM_RENDER) {
325 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
8a68d464 326 engine_mask |= BIT(RCS0);
c34eaa8d
CD		 327 }
328 if (data & GEN6_GRDOM_MEDIA) {
329 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
8a68d464 330 engine_mask |= BIT(VCS0);
c34eaa8d
CD		 331 }
332 if (data & GEN6_GRDOM_BLT) {
333 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
8a68d464 334 engine_mask |= BIT(BCS0);
c34eaa8d
CD		 335 }
336 if (data & GEN6_GRDOM_VECS) {
337 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
8a68d464 338 engine_mask |= BIT(VECS0);
c34eaa8d
CD		 339 }
340 if (data & GEN8_GRDOM_MEDIA2) {
341 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
8a68d464 342 engine_mask |= BIT(VCS1);
c34eaa8d 343 }
5e822e44
GF		 344 if (data & GEN9_GRDOM_GUC) {
345 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
346 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
347 }
8a68d464 348 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask;
e39c5add 349 }
c34eaa8d 350
f25a49ab 351 /* vgpu_lock already hold by emulate mmio r/w */
c34eaa8d
CD		 352 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
353
0811fa66 354 /* sw will wait for the device to ack the reset request */
253fe56e 355 vgpu_vreg(vgpu, offset) = 0;
0811fa66 356
c34eaa8d 357 return 0;
e39c5add
ZW		 358}
359
04d348ae
ZW		 360static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
361 void *p_data, unsigned int bytes)
362{
363 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
364}
365
366static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
367 void *p_data, unsigned int bytes)
368{
369 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
370}
371
372static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
373 unsigned int offset, void *p_data, unsigned int bytes)
374{
375 write_vreg(vgpu, offset, p_data, bytes);
376
377 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
90551a12
ZW		 378 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
379 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
380 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
381 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
04d348ae
ZW		 382
383 } else
90551a12 384 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
04d348ae
ZW		 385 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
386 | PP_CYCLE_DELAY_ACTIVE);
387 return 0;
388}
389
390static int transconf_mmio_write(struct intel_vgpu *vgpu,
391 unsigned int offset, void *p_data, unsigned int bytes)
392{
393 write_vreg(vgpu, offset, p_data, bytes);
394
395 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
396 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
397 else
398 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
399 return 0;
400}
401
402static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
403 void *p_data, unsigned int bytes)
404{
405 write_vreg(vgpu, offset, p_data, bytes);
406
407 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
408 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
409 else
410 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
411
412 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
413 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
414 else
415 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
416
417 return 0;
418}
419
420static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
421 void *p_data, unsigned int bytes)
422{
5cd82b75
CD		 423 switch (offset) {
424 case 0xe651c:
425 case 0xe661c:
426 case 0xe671c:
427 case 0xe681c:
428 vgpu_vreg(vgpu, offset) = 1 << 17;
429 break;
430 case 0xe6c04:
431 vgpu_vreg(vgpu, offset) = 0x3;
432 break;
433 case 0xe6e1c:
434 vgpu_vreg(vgpu, offset) = 0x2f << 16;
435 break;
436 default:
437 return -EINVAL;
438 }
04d348ae 439
5cd82b75 440 read_vreg(vgpu, offset, p_data, bytes);
04d348ae
ZW		 441 return 0;
442}
443
444static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
445 void *p_data, unsigned int bytes)
446{
447 u32 data;
448
449 write_vreg(vgpu, offset, p_data, bytes);
450 data = vgpu_vreg(vgpu, offset);
451
452 if (data & PIPECONF_ENABLE)
453 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
454 else
455 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
f25a49ab
CX		 456 /* vgpu_lock already hold by emulate mmio r/w */
457 mutex_unlock(&vgpu->vgpu_lock);
04d348ae 458 intel_gvt_check_vblank_emulation(vgpu->gvt);
f25a49ab 459 mutex_lock(&vgpu->vgpu_lock);
04d348ae
ZW		 460 return 0;
461}
462
e6cedfea
ZY		 463/* ascendingly sorted */
464static i915_reg_t force_nonpriv_white_list[] = {
465 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
466 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
68421940 467 PS_INVOCATION_COUNT,//_MMIO(0x2348)
e6cedfea
ZY		 468 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
469 _MMIO(0x2690),
470 _MMIO(0x2694),
471 _MMIO(0x2698),
1fd45b09
CX		 472 _MMIO(0x2754),
473 _MMIO(0x28a0),
e6cedfea
ZY		 474 _MMIO(0x4de0),
475 _MMIO(0x4de4),
476 _MMIO(0x4dfc),
477 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
478 _MMIO(0x7014),
479 HDC_CHICKEN0,//_MMIO(0x7300)
480 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
481 _MMIO(0x7700),
482 _MMIO(0x7704),
483 _MMIO(0x7708),
484 _MMIO(0x770c),
cba5ad62 485 _MMIO(0x83a8),
e6cedfea
ZY		 486 _MMIO(0xb110),
487 GEN8_L3SQCREG4,//_MMIO(0xb118)
488 _MMIO(0xe100),
489 _MMIO(0xe18c),
490 _MMIO(0xe48c),
491 _MMIO(0xe5f4),
492};
493
494/* a simple bsearch */
8fde4107 495static inline bool in_whitelist(u32 reg)
e6cedfea
ZY		 496{
497 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
498 i915_reg_t *array = force_nonpriv_white_list;
499
500 while (left < right) {
501 int mid = (left + right)/2;
502
503 if (reg > array[mid].reg)
504 left = mid + 1;
505 else if (reg < array[mid].reg)
506 right = mid;
507 else
508 return true;
509 }
510 return false;
511}
512
513static int force_nonpriv_write(struct intel_vgpu *vgpu,
514 unsigned int offset, void *p_data, unsigned int bytes)
515{
aeab9eda 516 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
8fde4107
CW		 517 const struct intel_engine_cs *engine =
518 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
e6cedfea 519
8fde4107
CW		 520 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {
521 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
522 vgpu->id, offset, bytes);
523 return -EINVAL;
e6cedfea
ZY		 524 }
525
8fde4107
CW		 526 if (!in_whitelist(reg_nonpriv) &&
527 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {
3d8b9e25 528 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
8fde4107
CW		 529 vgpu->id, reg_nonpriv, offset);
530 } else
531 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
3d8b9e25 532
0438a105 533 return 0;
e6cedfea
ZY		 534}
535
04d348ae
ZW		 536static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
537 void *p_data, unsigned int bytes)
538{
539 write_vreg(vgpu, offset, p_data, bytes);
540
541 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
542 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
543 } else {
544 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
545 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
90551a12 546 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
04d348ae
ZW		 547 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
548 }
549 return 0;
550}
551
552static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
553 unsigned int offset, void *p_data, unsigned int bytes)
554{
555 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
556 return 0;
557}
558
559#define FDI_LINK_TRAIN_PATTERN1 0
560#define FDI_LINK_TRAIN_PATTERN2 1
561
562static int fdi_auto_training_started(struct intel_vgpu *vgpu)
563{
90551a12 564 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
04d348ae 565 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
90551a12 566 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
04d348ae
ZW		 567
568 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
569 (rx_ctl & FDI_RX_ENABLE) &&
570 (rx_ctl & FDI_AUTO_TRAINING) &&
571 (tx_ctl & DP_TP_CTL_ENABLE) &&
572 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
573 return 1;
574 else
575 return 0;
576}
577
578static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
579 enum pipe pipe, unsigned int train_pattern)
580{
581 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
582 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
583 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
584 unsigned int fdi_iir_check_bits;
585
586 fdi_rx_imr = FDI_RX_IMR(pipe);
587 fdi_tx_ctl = FDI_TX_CTL(pipe);
588 fdi_rx_ctl = FDI_RX_CTL(pipe);
589
590 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
591 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
592 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
593 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
594 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
595 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
596 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
597 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
598 } else {
695fbc08 599 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
04d348ae
ZW		 600 return -EINVAL;
601 }
602
603 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
604 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
605
606 /* If imr bit has been masked */
90551a12 607 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
04d348ae
ZW		 608 return 0;
609
90551a12 610 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
04d348ae 611 == fdi_tx_check_bits)
90551a12 612 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
04d348ae
ZW		 613 == fdi_rx_check_bits))
614 return 1;
615 else
616 return 0;
617}
618
619#define INVALID_INDEX (~0U)
620
621static unsigned int calc_index(unsigned int offset, unsigned int start,
622 unsigned int next, unsigned int end, i915_reg_t i915_end)
623{
624 unsigned int range = next - start;
625
626 if (!end)
627 end = i915_mmio_reg_offset(i915_end);
628 if (offset < start || offset > end)
629 return INVALID_INDEX;
630 offset -= start;
631 return offset / range;
632}
633
634#define FDI_RX_CTL_TO_PIPE(offset) \
635 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
636
637#define FDI_TX_CTL_TO_PIPE(offset) \
638 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
639
640#define FDI_RX_IMR_TO_PIPE(offset) \
641 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
642
643static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
644 unsigned int offset, void *p_data, unsigned int bytes)
645{
646 i915_reg_t fdi_rx_iir;
647 unsigned int index;
648 int ret;
649
650 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
651 index = FDI_RX_CTL_TO_PIPE(offset);
652 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
653 index = FDI_TX_CTL_TO_PIPE(offset);
654 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
655 index = FDI_RX_IMR_TO_PIPE(offset);
656 else {
695fbc08 657 gvt_vgpu_err("Unsupport registers %x\n", offset);
04d348ae
ZW		 658 return -EINVAL;
659 }
660
661 write_vreg(vgpu, offset, p_data, bytes);
662
663 fdi_rx_iir = FDI_RX_IIR(index);
664
665 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
666 if (ret < 0)
667 return ret;
668 if (ret)
90551a12 669 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
04d348ae
ZW		 670
671 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
672 if (ret < 0)
673 return ret;
674 if (ret)
90551a12 675 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
04d348ae
ZW		 676
677 if (offset == _FDI_RXA_CTL)
678 if (fdi_auto_training_started(vgpu))
90551a12 679 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
04d348ae
ZW		 680 DP_TP_STATUS_AUTOTRAIN_DONE;
681 return 0;
682}
683
684#define DP_TP_CTL_TO_PORT(offset) \
685 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
686
687static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
688 void *p_data, unsigned int bytes)
689{
690 i915_reg_t status_reg;
691 unsigned int index;
692 u32 data;
693
694 write_vreg(vgpu, offset, p_data, bytes);
695
696 index = DP_TP_CTL_TO_PORT(offset);
697 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
698 if (data == 0x2) {
699 status_reg = DP_TP_STATUS(index);
90551a12 700 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
04d348ae
ZW		 701 }
702 return 0;
703}
704
705static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
706 unsigned int offset, void *p_data, unsigned int bytes)
707{
708 u32 reg_val;
709 u32 sticky_mask;
710
711 reg_val = *((u32 *)p_data);
712 sticky_mask = GENMASK(27, 26) | (1 << 24);
713
714 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
715 (vgpu_vreg(vgpu, offset) & sticky_mask);
716 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
717 return 0;
718}
719
720static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
721 unsigned int offset, void *p_data, unsigned int bytes)
722{
723 u32 data;
724
725 write_vreg(vgpu, offset, p_data, bytes);
726 data = vgpu_vreg(vgpu, offset);
727
728 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
729 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
730 return 0;
731}
732
733static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
734 unsigned int offset, void *p_data, unsigned int bytes)
735{
736 u32 data;
737
738 write_vreg(vgpu, offset, p_data, bytes);
739 data = vgpu_vreg(vgpu, offset);
740
741 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
742 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
743 else
744 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
745 return 0;
746}
747
748#define DSPSURF_TO_PIPE(offset) \
749 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
750
751static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
752 void *p_data, unsigned int bytes)
753{
754 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
d57b39e3
CX		 755 u32 pipe = DSPSURF_TO_PIPE(offset);
756 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
04d348ae
ZW		 757
758 write_vreg(vgpu, offset, p_data, bytes);
d57b39e3
CX		 759 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
760
761 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
762
763 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
764 intel_vgpu_trigger_virtual_event(vgpu, event);
765 else
766 set_bit(event, vgpu->irq.flip_done_event[pipe]);
04d348ae 767
04d348ae
ZW		 768 return 0;
769}
770
771#define SPRSURF_TO_PIPE(offset) \
772 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
773
774static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
775 void *p_data, unsigned int bytes)
776{
d57b39e3
CX		 777 u32 pipe = SPRSURF_TO_PIPE(offset);
778 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
04d348ae
ZW		 779
780 write_vreg(vgpu, offset, p_data, bytes);
d57b39e3
CX		 781 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
782
783 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
784 intel_vgpu_trigger_virtual_event(vgpu, event);
785 else
786 set_bit(event, vgpu->irq.flip_done_event[pipe]);
787
788 return 0;
789}
790
791static int reg50080_mmio_write(struct intel_vgpu *vgpu,
792 unsigned int offset, void *p_data,
793 unsigned int bytes)
794{
795 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
796 enum pipe pipe = REG_50080_TO_PIPE(offset);
797 enum plane_id plane = REG_50080_TO_PLANE(offset);
798 int event = SKL_FLIP_EVENT(pipe, plane);
799
800 write_vreg(vgpu, offset, p_data, bytes);
801 if (plane == PLANE_PRIMARY) {
802 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
803 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
804 } else {
805 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
806 }
807
808 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
809 intel_vgpu_trigger_virtual_event(vgpu, event);
810 else
811 set_bit(event, vgpu->irq.flip_done_event[pipe]);
04d348ae 812
04d348ae
ZW		 813 return 0;
814}
815
816static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
817 unsigned int reg)
818{
819 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
820 enum intel_gvt_event_type event;
821
47c41af7 822 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
04d348ae 823 event = AUX_CHANNEL_A;
47c41af7
MR		 824 else if (reg == _PCH_DPB_AUX_CH_CTL ||
825 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
04d348ae 826 event = AUX_CHANNEL_B;
47c41af7
MR		 827 else if (reg == _PCH_DPC_AUX_CH_CTL ||
828 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
04d348ae 829 event = AUX_CHANNEL_C;
47c41af7
MR		 830 else if (reg == _PCH_DPD_AUX_CH_CTL ||
831 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
04d348ae
ZW		 832 event = AUX_CHANNEL_D;
833 else {
db19c724 834 drm_WARN_ON(&dev_priv->drm, true);
04d348ae
ZW		 835 return -EINVAL;
836 }
837
838 intel_vgpu_trigger_virtual_event(vgpu, event);
839 return 0;
840}
841
842static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
843 unsigned int reg, int len, bool data_valid)
844{
845 /* mark transaction done */
846 value |= DP_AUX_CH_CTL_DONE;
847 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
848 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
849
850 if (data_valid)
851 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
852 else
853 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
854
855 /* message size */
856 value &= ~(0xf << 20);
857 value |= (len << 20);
858 vgpu_vreg(vgpu, reg) = value;
859
860 if (value & DP_AUX_CH_CTL_INTERRUPT)
861 return trigger_aux_channel_interrupt(vgpu, reg);
862 return 0;
863}
864
865static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
2e679d48 866 u8 t)
04d348ae
ZW		 867{
868 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
869 /* training pattern 1 for CR */
870 /* set LANE0_CR_DONE, LANE1_CR_DONE */
871 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
872 /* set LANE2_CR_DONE, LANE3_CR_DONE */
873 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
874 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
875 DPCD_TRAINING_PATTERN_2) {
876 /* training pattern 2 for EQ */
877 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
878 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
879 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
880 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
881 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
882 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
883 /* set INTERLANE_ALIGN_DONE */
884 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
885 DPCD_INTERLANE_ALIGN_DONE;
886 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
887 DPCD_LINK_TRAINING_DISABLED) {
888 /* finish link training */
889 /* set sink status as synchronized */
890 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
891 }
892}
893
894#define _REG_HSW_DP_AUX_CH_CTL(dp) \
895 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
896
897#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
898
899#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
900
901#define dpy_is_valid_port(port) \
902 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
903
904static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
905 unsigned int offset, void *p_data, unsigned int bytes)
906{
907 struct intel_vgpu_display *display = &vgpu->display;
908 int msg, addr, ctrl, op, len;
909 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
910 struct intel_vgpu_dpcd_data *dpcd = NULL;
911 struct intel_vgpu_port *port = NULL;
912 u32 data;
913
914 if (!dpy_is_valid_port(port_index)) {
695fbc08 915 gvt_vgpu_err("Unsupported DP port access!\n");
04d348ae
ZW		 916 return 0;
917 }
918
919 write_vreg(vgpu, offset, p_data, bytes);
920 data = vgpu_vreg(vgpu, offset);
921
c3b5a843 922 if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9)
e3476c00 923 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
04d348ae
ZW		 924 /* SKL DPB/C/D aux ctl register changed */
925 return 0;
926 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
927 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
928 /* write to the data registers */
929 return 0;
930 }
931
932 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
933 /* just want to clear the sticky bits */
934 vgpu_vreg(vgpu, offset) = 0;
935 return 0;
936 }
937
938 port = &display->ports[port_index];
939 dpcd = port->dpcd;
940
941 /* read out message from DATA1 register */
942 msg = vgpu_vreg(vgpu, offset + 4);
943 addr = (msg >> 8) & 0xffff;
944 ctrl = (msg >> 24) & 0xff;
945 len = msg & 0xff;
946 op = ctrl >> 4;
947
948 if (op == GVT_AUX_NATIVE_WRITE) {
949 int t;
2e679d48 950 u8 buf[16];
04d348ae
ZW		 951
952 if ((addr + len + 1) >= DPCD_SIZE) {
953 /*
954 * Write request exceeds what we supported,
955 * DCPD spec: When a Source Device is writing a DPCD
956 * address not supported by the Sink Device, the Sink
957 * Device shall reply with AUX NACK and “M” equal to
958 * zero.
959 */
960
961 /* NAK the write */
962 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
963 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
964 return 0;
965 }
966
967 /*
2f24636b
CD		 968 * Write request format: Headr (command + address + size) occupies
969 * 4 bytes, followed by (len + 1) bytes of data. See details at
970 * intel_dp_aux_transfer().
04d348ae 971 */
2f24636b
CD		 972 if ((len + 1 + 4) > AUX_BURST_SIZE) {
973 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
04d348ae 974 return -EINVAL;
2f24636b 975 }
04d348ae
ZW		 976
977 /* unpack data from vreg to buf */
978 for (t = 0; t < 4; t++) {
979 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
980
981 buf[t * 4] = (r >> 24) & 0xff;
982 buf[t * 4 + 1] = (r >> 16) & 0xff;
983 buf[t * 4 + 2] = (r >> 8) & 0xff;
984 buf[t * 4 + 3] = r & 0xff;
985 }
986
987 /* write to virtual DPCD */
988 if (dpcd && dpcd->data_valid) {
989 for (t = 0; t <= len; t++) {
990 int p = addr + t;
991
992 dpcd->data[p] = buf[t];
993 /* check for link training */
994 if (p == DPCD_TRAINING_PATTERN_SET)
995 dp_aux_ch_ctl_link_training(dpcd,
996 buf[t]);
997 }
998 }
999
1000 /* ACK the write */
1001 vgpu_vreg(vgpu, offset + 4) = 0;
1002 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1003 dpcd && dpcd->data_valid);
1004 return 0;
1005 }
1006
1007 if (op == GVT_AUX_NATIVE_READ) {
1008 int idx, i, ret = 0;
1009
1010 if ((addr + len + 1) >= DPCD_SIZE) {
1011 /*
1012 * read request exceeds what we supported
1013 * DPCD spec: A Sink Device receiving a Native AUX CH
1014 * read request for an unsupported DPCD address must
1015 * reply with an AUX ACK and read data set equal to
1016 * zero instead of replying with AUX NACK.
1017 */
1018
1019 /* ACK the READ*/
1020 vgpu_vreg(vgpu, offset + 4) = 0;
1021 vgpu_vreg(vgpu, offset + 8) = 0;
1022 vgpu_vreg(vgpu, offset + 12) = 0;
1023 vgpu_vreg(vgpu, offset + 16) = 0;
1024 vgpu_vreg(vgpu, offset + 20) = 0;
1025
1026 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1027 true);
1028 return 0;
1029 }
1030
1031 for (idx = 1; idx <= 5; idx++) {
1032 /* clear the data registers */
1033 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1034 }
1035
1036 /*
1037 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1038 */
2f24636b
CD		 1039 if ((len + 2) > AUX_BURST_SIZE) {
1040 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
04d348ae 1041 return -EINVAL;
2f24636b 1042 }
04d348ae
ZW		 1043
1044 /* read from virtual DPCD to vreg */
1045 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1046 if (dpcd && dpcd->data_valid) {
1047 for (i = 1; i <= (len + 1); i++) {
1048 int t;
1049
1050 t = dpcd->data[addr + i - 1];
1051 t <<= (24 - 8 * (i % 4));
1052 ret |= t;
1053
1054 if ((i % 4 == 3) || (i == (len + 1))) {
1055 vgpu_vreg(vgpu, offset +
1056 (i / 4 + 1) * 4) = ret;
1057 ret = 0;
1058 }
1059 }
1060 }
1061 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1062 dpcd && dpcd->data_valid);
1063 return 0;
1064 }
1065
1066 /* i2c transaction starts */
1067 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1068
1069 if (data & DP_AUX_CH_CTL_INTERRUPT)
1070 trigger_aux_channel_interrupt(vgpu, offset);
1071 return 0;
1072}
1073
975629c3
PZ		 1074static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1075 void *p_data, unsigned int bytes)
1076{
1077 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1078 write_vreg(vgpu, offset, p_data, bytes);
1079 return 0;
1080}
1081
04d348ae
ZW		 1082static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1083 void *p_data, unsigned int bytes)
1084{
1085 bool vga_disable;
1086
1087 write_vreg(vgpu, offset, p_data, bytes);
1088 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1089
1090 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1091 vga_disable ? "Disable" : "Enable");
1092 return 0;
1093}
1094
1095static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1096 unsigned int sbi_offset)
1097{
1098 struct intel_vgpu_display *display = &vgpu->display;
1099 int num = display->sbi.number;
1100 int i;
1101
1102 for (i = 0; i < num; ++i)
1103 if (display->sbi.registers[i].offset == sbi_offset)
1104 break;
1105
1106 if (i == num)
1107 return 0;
1108
1109 return display->sbi.registers[i].value;
1110}
1111
1112static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1113 unsigned int offset, u32 value)
1114{
1115 struct intel_vgpu_display *display = &vgpu->display;
1116 int num = display->sbi.number;
1117 int i;
1118
1119 for (i = 0; i < num; ++i) {
1120 if (display->sbi.registers[i].offset == offset)
1121 break;
1122 }
1123
1124 if (i == num) {
1125 if (num == SBI_REG_MAX) {
695fbc08 1126 gvt_vgpu_err("SBI caching meets maximum limits\n");
04d348ae
ZW		 1127 return;
1128 }
1129 display->sbi.number++;
1130 }
1131
1132 display->sbi.registers[i].offset = offset;
1133 display->sbi.registers[i].value = value;
1134}
1135
1136static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1137 void *p_data, unsigned int bytes)
1138{
90551a12 1139 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
04d348ae 1140 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
90551a12 1141 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
04d348ae
ZW		 1142 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1143 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1144 sbi_offset);
1145 }
1146 read_vreg(vgpu, offset, p_data, bytes);
1147 return 0;
1148}
1149
3e70c5d6 1150static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
04d348ae
ZW		 1151 void *p_data, unsigned int bytes)
1152{
1153 u32 data;
1154
1155 write_vreg(vgpu, offset, p_data, bytes);
1156 data = vgpu_vreg(vgpu, offset);
1157
1158 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1159 data |= SBI_READY;
1160
1161 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1162 data |= SBI_RESPONSE_SUCCESS;
1163
1164 vgpu_vreg(vgpu, offset) = data;
1165
90551a12 1166 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
04d348ae 1167 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
90551a12 1168 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
04d348ae
ZW		 1169 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1170
1171 write_virtual_sbi_register(vgpu, sbi_offset,
90551a12 1172 vgpu_vreg_t(vgpu, SBI_DATA));
04d348ae
ZW		 1173 }
1174 return 0;
1175}
1176
e39c5add
ZW		 1177#define _vgtif_reg(x) \
1178 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1179
1180static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1181 void *p_data, unsigned int bytes)
1182{
1183 bool invalid_read = false;
1184
1185 read_vreg(vgpu, offset, p_data, bytes);
1186
1187 switch (offset) {
1188 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1189 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1190 invalid_read = true;
1191 break;
1192 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1193 _vgtif_reg(avail_rs.fence_num):
1194 if (offset + bytes >
1195 _vgtif_reg(avail_rs.fence_num) + 4)
1196 invalid_read = true;
1197 break;
1198 case 0x78010: /* vgt_caps */
1199 case 0x7881c:
1200 break;
1201 default:
1202 invalid_read = true;
1203 break;
1204 }
1205 if (invalid_read)
695fbc08 1206 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
e39c5add 1207 offset, bytes, *(u32 *)p_data);
fd64be63 1208 vgpu->pv_notified = true;
e39c5add
ZW		 1209 return 0;
1210}
1211
1212static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1213{
0cf8f58d 1214 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
e6e9c46f 1215 struct intel_vgpu_mm *mm;
ede9d0cf 1216 u64 *pdps;
e39c5add 1217
ede9d0cf
CD		 1218 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1219
e39c5add
ZW		 1220 switch (notification) {
1221 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
e6e9c46f 1222 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
3eda0d22 1223 /* fall through */
e39c5add 1224 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
e6e9c46f
CD		 1225 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1226 return PTR_ERR_OR_ZERO(mm);
1227 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
e39c5add 1228 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
e6e9c46f 1229 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
e39c5add
ZW		 1230 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1231 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1232 case 1: /* Remove this in guest driver. */
1233 break;
1234 default:
695fbc08 1235 gvt_vgpu_err("Invalid PV notification %d\n", notification);
e39c5add 1236 }
e6e9c46f 1237 return 0;
e39c5add
ZW		 1238}
1239
04d348ae
ZW		 1240static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1241{
1242 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1243 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1244 char *env[3] = {NULL, NULL, NULL};
1245 char vmid_str[20];
1246 char display_ready_str[20];
1247
d8e9b2b9 1248 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
04d348ae
ZW		 1249 env[0] = display_ready_str;
1250
1251 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1252 env[1] = vmid_str;
1253
1254 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1255}
1256
e39c5add
ZW		 1257static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1258 void *p_data, unsigned int bytes)
1259{
971afec3
WL		 1260 u32 data = *(u32 *)p_data;
1261 bool invalid_write = false;
e39c5add
ZW		 1262
1263 switch (offset) {
1264 case _vgtif_reg(display_ready):
04d348ae
ZW		 1265 send_display_ready_uevent(vgpu, data ? 1 : 0);
1266 break;
e39c5add 1267 case _vgtif_reg(g2v_notify):
971afec3 1268 handle_g2v_notification(vgpu, data);
e39c5add
ZW		 1269 break;
1270 /* add xhot and yhot to handled list to avoid error log */
1c6ccad8
TZ		 1271 case _vgtif_reg(cursor_x_hot):
1272 case _vgtif_reg(cursor_y_hot):
e39c5add
ZW		 1273 case _vgtif_reg(pdp[0].lo):
1274 case _vgtif_reg(pdp[0].hi):
1275 case _vgtif_reg(pdp[1].lo):
1276 case _vgtif_reg(pdp[1].hi):
1277 case _vgtif_reg(pdp[2].lo):
1278 case _vgtif_reg(pdp[2].hi):
1279 case _vgtif_reg(pdp[3].lo):
1280 case _vgtif_reg(pdp[3].hi):
1281 case _vgtif_reg(execlist_context_descriptor_lo):
1282 case _vgtif_reg(execlist_context_descriptor_hi):
1283 break;
a33fc7a0 1284 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
971afec3 1285 invalid_write = true;
a33fc7a0
MH		 1286 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1287 break;
e39c5add 1288 default:
971afec3 1289 invalid_write = true;
695fbc08 1290 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
e39c5add
ZW		 1291 offset, bytes, data);
1292 break;
1293 }
971afec3
WL		 1294
1295 if (!invalid_write)
1296 write_vreg(vgpu, offset, p_data, bytes);
1297
e39c5add
ZW		 1298 return 0;
1299}
1300
04d348ae
ZW		 1301static int pf_write(struct intel_vgpu *vgpu,
1302 unsigned int offset, void *p_data, unsigned int bytes)
1303{
12d58619 1304 struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
04d348ae
ZW		 1305 u32 val = *(u32 *)p_data;
1306
1307 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1308 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1309 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
12d58619
PB		 1310 drm_WARN_ONCE(&i915->drm, true,
1311 "VM(%d): guest is trying to scaling a plane\n",
1312 vgpu->id);
04d348ae
ZW		 1313 return 0;
1314 }
1315
1316 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1317}
1318
1319static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1320 unsigned int offset, void *p_data, unsigned int bytes)
1321{
1322 write_vreg(vgpu, offset, p_data, bytes);
1323
75e39688
ID		 1324 if (vgpu_vreg(vgpu, offset) &
1325 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1af474fe 1326 vgpu_vreg(vgpu, offset) |=
75e39688 1327 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
04d348ae 1328 else
1af474fe 1329 vgpu_vreg(vgpu, offset) &=
75e39688 1330 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
04d348ae
ZW		 1331 return 0;
1332}
1333
9174c1d6
XZ		 1334static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1335 unsigned int offset, void *p_data, unsigned int bytes)
1336{
1337 write_vreg(vgpu, offset, p_data, bytes);
1338
1339 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1340 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1341 else
1342 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1343
1344 return 0;
1345}
1346
e39c5add
ZW		 1347static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1348 unsigned int offset, void *p_data, unsigned int bytes)
1349{
1350 write_vreg(vgpu, offset, p_data, bytes);
1351
1352 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1353 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1354 return 0;
1355}
1356
1357static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1358 void *p_data, unsigned int bytes)
1359{
12d58619 1360 struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
5f399f11
PG		 1361 u32 mode;
1362
1363 write_vreg(vgpu, offset, p_data, bytes);
1364 mode = vgpu_vreg(vgpu, offset);
e39c5add
ZW		 1365
1366 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
12d58619
PB		 1367 drm_WARN_ONCE(&i915->drm, 1,
1368 "VM(%d): iGVT-g doesn't support GuC\n",
e39c5add
ZW		 1369 vgpu->id);
1370 return 0;
1371 }
1372
1373 return 0;
1374}
1375
1376static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1377 void *p_data, unsigned int bytes)
1378{
12d58619 1379 struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
e39c5add
ZW		 1380 u32 trtte = *(u32 *)p_data;
1381
1382 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
12d58619
PB		 1383 drm_WARN(&i915->drm, 1,
1384 "VM(%d): Use physical address for TRTT!\n",
e39c5add
ZW		 1385 vgpu->id);
1386 return -EINVAL;
1387 }
1388 write_vreg(vgpu, offset, p_data, bytes);
e39c5add
ZW		 1389
1390 return 0;
1391}
1392
1393static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1394 void *p_data, unsigned int bytes)
1395{
e39c5add
ZW		 1396 write_vreg(vgpu, offset, p_data, bytes);
1397 return 0;
1398}
1399
04d348ae
ZW		 1400static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1401 void *p_data, unsigned int bytes)
1402{
1403 u32 v = 0;
1404
1405 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1406 v |= (1 << 0);
1407
1408 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1409 v |= (1 << 8);
1410
1411 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1412 v |= (1 << 16);
1413
1414 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1415 v |= (1 << 24);
1416
1417 vgpu_vreg(vgpu, offset) = v;
1418
1419 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1420}
1421
1422static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1423 void *p_data, unsigned int bytes)
1424{
1425 u32 value = *(u32 *)p_data;
1426 u32 cmd = value & 0xff;
90551a12 1427 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
04d348ae
ZW		 1428
1429 switch (cmd) {
8bcd7c18 1430 case GEN9_PCODE_READ_MEM_LATENCY:
e3476c00 1431 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
c3b5a843 1432 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1433 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) {
8bcd7c18
WL		 1434 /**
1435 * "Read memory latency" command on gen9.
1436 * Below memory latency values are read
1437 * from skylake platform.
1438 */
1439 if (!*data0)
1440 *data0 = 0x1e1a1100;
1441 else
1442 *data0 = 0x61514b3d;
d71cb712
CX		 1443 } else if (IS_BROXTON(vgpu->gvt->dev_priv)) {
1444 /**
1445 * "Read memory latency" command on gen9.
1446 * Below memory latency values are read
1447 * from Broxton MRB.
1448 */
1449 if (!*data0)
1450 *data0 = 0x16080707;
1451 else
1452 *data0 = 0x16161616;
8bcd7c18 1453 }
04d348ae 1454 break;
d8a355be 1455 case SKL_PCODE_CDCLK_CONTROL:
e3476c00 1456 if (IS_SKYLAKE(vgpu->gvt->dev_priv)
c3b5a843 1457 || IS_KABYLAKE(vgpu->gvt->dev_priv)
1458 || IS_COFFEELAKE(vgpu->gvt->dev_priv))
8bcd7c18 1459 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
d8a355be 1460 break;
8bcd7c18 1461 case GEN6_PCODE_READ_RC6VIDS:
04d348ae
ZW		 1462 *data0 |= 0x1;
1463 break;
1464 }
1465
1466 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1467 vgpu->id, value, *data0);
d8a355be
WL		 1468 /**
1469 * PCODE_READY clear means ready for pcode read/write,
1470 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1471 * always emulate as pcode read/write success and ready for access
1472 * anytime, since we don't touch real physical registers here.
1473 */
1474 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
04d348ae
ZW		 1475 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1476}
1477
a2ae95af
WL		 1478static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1479 void *p_data, unsigned int bytes)
1480{
1481 u32 value = *(u32 *)p_data;
8fde4107
CW		 1482 const struct intel_engine_cs *engine =
1483 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
a2ae95af
WL		 1484
1485 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
b52646fd
ZW		 1486 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1487 offset, value);
a2ae95af
WL		 1488 return -EINVAL;
1489 }
1490 /*
1491 * Need to emulate all the HWSP register write to ensure host can
1492 * update the VM CSB status correctly. Here listed registers can
1493 * support BDW, SKL or other platforms with same HWSP registers.
1494 */
8fde4107 1495 if (unlikely(!engine)) {
b52646fd
ZW		 1496 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1497 offset);
a2ae95af
WL		 1498 return -EINVAL;
1499 }
8fde4107 1500 vgpu->hws_pga[engine->id] = value;
a2ae95af
WL		 1501 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1502 vgpu->id, value, offset);
1503
1504 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1505}
1506
04d348ae
ZW		 1507static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1508 unsigned int offset, void *p_data, unsigned int bytes)
1509{
1510 u32 v = *(u32 *)p_data;
1511
d71cb712
CX		 1512 if (IS_BROXTON(vgpu->gvt->dev_priv))
1513 v &= (1 << 31) | (1 << 29);
1514 else
1515 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1516 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
04d348ae
ZW		 1517 v |= (v >> 1);
1518
1519 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1520}
1521
04d348ae
ZW		 1522static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1523 void *p_data, unsigned int bytes)
1524{
1525 u32 v = *(u32 *)p_data;
1526
1527 /* other bits are MBZ. */
1528 v &= (1 << 31) | (1 << 30);
1529 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1530
1531 vgpu_vreg(vgpu, offset) = v;
1532
1533 return 0;
1534}
1535
d71cb712
CX		 1536static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1537 unsigned int offset, void *p_data, unsigned int bytes)
1538{
1539 u32 v = *(u32 *)p_data;
1540
1541 if (v & BXT_DE_PLL_PLL_ENABLE)
1542 v |= BXT_DE_PLL_LOCK;
1543
1544 vgpu_vreg(vgpu, offset) = v;
1545
1546 return 0;
1547}
1548
1549static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1550 unsigned int offset, void *p_data, unsigned int bytes)
1551{
1552 u32 v = *(u32 *)p_data;
1553
1554 if (v & PORT_PLL_ENABLE)
1555 v |= PORT_PLL_LOCK;
1556
1557 vgpu_vreg(vgpu, offset) = v;
1558
1559 return 0;
1560}
1561
1562static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1563 unsigned int offset, void *p_data, unsigned int bytes)
1564{
1565 u32 v = *(u32 *)p_data;
1566 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1567
c8ab5ac3
CX		 1568 switch (offset) {
1569 case _PHY_CTL_FAMILY_EDP:
1570 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1571 break;
1572 case _PHY_CTL_FAMILY_DDI:
1573 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1574 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1575 break;
1576 }
d71cb712
CX		 1577
1578 vgpu_vreg(vgpu, offset) = v;
1579
1580 return 0;
1581}
1582
1583static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1584 unsigned int offset, void *p_data, unsigned int bytes)
1585{
1586 u32 v = vgpu_vreg(vgpu, offset);
1587
1588 v &= ~UNIQUE_TRANGE_EN_METHOD;
1589
1590 vgpu_vreg(vgpu, offset) = v;
1591
1592 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1593}
1594
1595static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1596 unsigned int offset, void *p_data, unsigned int bytes)
1597{
1598 u32 v = *(u32 *)p_data;
1599
1600 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1601 vgpu_vreg(vgpu, offset - 0x600) = v;
1602 vgpu_vreg(vgpu, offset - 0x800) = v;
1603 } else {
1604 vgpu_vreg(vgpu, offset - 0x400) = v;
1605 vgpu_vreg(vgpu, offset - 0x600) = v;
1606 }
1607
1608 vgpu_vreg(vgpu, offset) = v;
1609
1610 return 0;
1611}
1612
1613static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1614 unsigned int offset, void *p_data, unsigned int bytes)
1615{
1616 u32 v = *(u32 *)p_data;
1617
1618 if (v & BIT(0)) {
1619 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1620 ~PHY_RESERVED;
1621 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1622 PHY_POWER_GOOD;
1623 }
1624
1625 if (v & BIT(1)) {
1626 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1627 ~PHY_RESERVED;
1628 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1629 PHY_POWER_GOOD;
1630 }
1631
1632
1633 vgpu_vreg(vgpu, offset) = v;
1634
1635 return 0;
1636}
1637
5e7154ff 1638static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
93d68b25
CX		 1639 unsigned int offset, void *p_data, unsigned int bytes)
1640{
1641 vgpu_vreg(vgpu, offset) = 0;
1642 return 0;
1643}
1644
5e822e44
GF		 1645static int guc_status_read(struct intel_vgpu *vgpu,
1646 unsigned int offset, void *p_data,
1647 unsigned int bytes)
1648{
1649 /* keep MIA_IN_RESET before clearing */
1650 read_vreg(vgpu, offset, p_data, bytes);
1651 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1652 return 0;
1653}
1654
20a2bcde 1655static int mmio_read_from_hw(struct intel_vgpu *vgpu,
23ce0592
WL		 1656 unsigned int offset, void *p_data, unsigned int bytes)
1657{
295764cd
XZ		 1658 struct intel_gvt *gvt = vgpu->gvt;
1659 struct drm_i915_private *dev_priv = gvt->dev_priv;
8fde4107
CW		 1660 const struct intel_engine_cs *engine =
1661 intel_gvt_render_mmio_to_engine(gvt, offset);
295764cd 1662
295764cd
XZ		 1663 /**
1664 * Read HW reg in following case
1665 * a. the offset isn't a ring mmio
1666 * b. the offset's ring is running on hw.
1667 * c. the offset is ring time stamp mmio
1668 */
295764cd 1669
8fde4107
CW		 1670 if (!engine ||
1671 vgpu == gvt->scheduler.engine_owner[engine->id] ||
1672 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||
1673 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {
295764cd
XZ		 1674 mmio_hw_access_pre(dev_priv);
1675 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1676 mmio_hw_access_post(dev_priv);
1677 }
23ce0592 1678
04d348ae
ZW		 1679 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1680}
1681
28c4c6ca
ZW		 1682static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1683 void *p_data, unsigned int bytes)
1684{
12d58619 1685 struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
8fde4107 1686 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
28c4c6ca
ZW		 1687 struct intel_vgpu_execlist *execlist;
1688 u32 data = *(u32 *)p_data;
6fb5082a 1689 int ret = 0;
28c4c6ca 1690
8fde4107 1691 if (drm_WARN_ON(&i915->drm, !engine))
28c4c6ca
ZW		 1692 return -EINVAL;
1693
8fde4107 1694 execlist = &vgpu->submission.execlist[engine->id];
28c4c6ca 1695
54cff647 1696 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
6fb5082a 1697 if (execlist->elsp_dwords.index == 3) {
8fde4107 1698 ret = intel_vgpu_submit_execlist(vgpu, engine);
6fb5082a 1699 if(ret)
8fde4107
CW		 1700 gvt_vgpu_err("fail submit workload on ring %s\n",
1701 engine->name);
6fb5082a 1702 }
28c4c6ca
ZW		 1703
1704 ++execlist->elsp_dwords.index;
1705 execlist->elsp_dwords.index &= 0x3;
6fb5082a 1706 return ret;
28c4c6ca
ZW		 1707}
1708
4b63960e
ZW		 1709static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1710 void *p_data, unsigned int bytes)
1711{
1712 u32 data = *(u32 *)p_data;
8fde4107
CW		 1713 const struct intel_engine_cs *engine =
1714 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
4b63960e 1715 bool enable_execlist;
ad1d3636 1716 int ret;
4b63960e 1717
888c0094
CX		 1718 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
1719 if (IS_COFFEELAKE(vgpu->gvt->dev_priv))
1720 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
4b63960e 1721 write_vreg(vgpu, offset, p_data, bytes);
fd64be63 1722
888c0094
CX		 1723 if (data & _MASKED_BIT_ENABLE(1)) {
1724 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1725 return 0;
1726 }
1727
1728 if (IS_COFFEELAKE(vgpu->gvt->dev_priv) &&
1729 data & _MASKED_BIT_ENABLE(2)) {
1730 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1731 return 0;
1732 }
1733
fd64be63
MH		 1734 /* when PPGTT mode enabled, we will check if guest has called
1735 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1736 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1737 */
1738 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1739 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1740 && !vgpu->pv_notified) {
1741 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1742 return 0;
1743 }
4b63960e
ZW		 1744 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1745 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1746 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1747
8fde4107
CW		 1748 gvt_dbg_core("EXECLIST %s on ring %s\n",
1749 (enable_execlist ? "enabling" : "disabling"),
1750 engine->name);
4b63960e 1751
ad1d3636
ZW		 1752 if (!enable_execlist)
1753 return 0;
1754
ad1d3636 1755 ret = intel_vgpu_select_submission_ops(vgpu,
8fde4107
CW		 1756 engine->mask,
1757 INTEL_VGPU_EXECLIST_SUBMISSION);
ad1d3636
ZW		 1758 if (ret)
1759 return ret;
1760
1761 intel_vgpu_start_schedule(vgpu);
4b63960e
ZW		 1762 }
1763 return 0;
1764}
1765
17865713
ZW		 1766static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1767 unsigned int offset, void *p_data, unsigned int bytes)
1768{
17865713
ZW		 1769 unsigned int id = 0;
1770
f24940e0 1771 write_vreg(vgpu, offset, p_data, bytes);
4f3f1aed 1772 vgpu_vreg(vgpu, offset) = 0;
f24940e0 1773
17865713
ZW		 1774 switch (offset) {
1775 case 0x4260:
8a68d464 1776 id = RCS0;
17865713
ZW		 1777 break;
1778 case 0x4264:
8a68d464 1779 id = VCS0;
17865713
ZW		 1780 break;
1781 case 0x4268:
8a68d464 1782 id = VCS1;
17865713
ZW		 1783 break;
1784 case 0x426c:
8a68d464 1785 id = BCS0;
17865713
ZW		 1786 break;
1787 case 0x4270:
8a68d464 1788 id = VECS0;
17865713
ZW		 1789 break;
1790 default:
a1201053 1791 return -EINVAL;
17865713 1792 }
91d5d854 1793 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
17865713 1794
a1201053 1795 return 0;
17865713
ZW		 1796}
1797
2fb39fad
DC		 1798static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1799 unsigned int offset, void *p_data, unsigned int bytes)
1800{
1801 u32 data;
1802
1803 write_vreg(vgpu, offset, p_data, bytes);
1804 data = vgpu_vreg(vgpu, offset);
1805
1806 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1807 data |= RESET_CTL_READY_TO_RESET;
1808 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1809 data &= ~RESET_CTL_READY_TO_RESET;
1810
1811 vgpu_vreg(vgpu, offset) = data;
1812 return 0;
1813}
1814
cb2808da
CX		 1815static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
1816 unsigned int offset, void *p_data,
1817 unsigned int bytes)
1818{
1819 u32 data = *(u32 *)p_data;
1820
1821 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
1822 write_vreg(vgpu, offset, p_data, bytes);
1823
1824 if (data & _MASKED_BIT_ENABLE(0x10) || data & _MASKED_BIT_ENABLE(0x8))
1825 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1826
1827 return 0;
1828}
1829
12d14cc4 1830#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
c20164db 1831 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
12d14cc4
ZW		 1832 f, s, am, rm, d, r, w); \
1833 if (ret) \
1834 return ret; \
1835} while (0)
1836
1837#define MMIO_D(reg, d) \
1838 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1839
1840#define MMIO_DH(reg, d, r, w) \
1841 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1842
1843#define MMIO_DFH(reg, d, f, r, w) \
1844 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1845
1846#define MMIO_GM(reg, d, r, w) \
1847 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1848
0aa5277c
ZY		 1849#define MMIO_GM_RDR(reg, d, r, w) \
1850 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1851
12d14cc4
ZW		 1852#define MMIO_RO(reg, d, f, rm, r, w) \
1853 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1854
1855#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1856 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1857 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1858 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1859 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
8a68d464 1860 if (HAS_ENGINE(dev_priv, VCS1)) \
edee7ecd 1861 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
12d14cc4
ZW		 1862} while (0)
1863
1864#define MMIO_RING_D(prefix, d) \
1865 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1866
1867#define MMIO_RING_DFH(prefix, d, f, r, w) \
1868 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1869
1870#define MMIO_RING_GM(prefix, d, r, w) \
1871 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1872
0aa5277c
ZY		 1873#define MMIO_RING_GM_RDR(prefix, d, r, w) \
1874 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1875
12d14cc4
ZW		 1876#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1877 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1878
1879static int init_generic_mmio_info(struct intel_gvt *gvt)
1880{
e39c5add 1881 struct drm_i915_private *dev_priv = gvt->dev_priv;
12d14cc4
ZW		 1882 int ret;
1883
0aa5277c
ZY		 1884 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1885 intel_vgpu_reg_imr_handler);
e39c5add
ZW		 1886
1887 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1888 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1889 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1890 MMIO_D(SDEISR, D_ALL);
1891
0aa5277c 1892 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add 1893
52ca14e6
CD		 1894 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
1895 gamw_echo_dev_rw_ia_write);
1896
0aa5277c
ZY		 1897 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1898 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1899 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
e39c5add 1900
c20164db 1901#define RING_REG(base) _MMIO((base) + 0x28)
0aa5277c 1902 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1903#undef RING_REG
1904
c20164db 1905#define RING_REG(base) _MMIO((base) + 0x134)
0aa5277c 1906 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1907#undef RING_REG
1908
c20164db 1909#define RING_REG(base) _MMIO((base) + 0x6c)
20a2bcde 1910 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
23ce0592 1911#undef RING_REG
20a2bcde 1912 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
23ce0592 1913
c20164db 1914 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
baba6e57 1915 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
c20164db 1916 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
e39c5add
ZW		 1917 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1918
0aa5277c
ZY		 1919 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1920 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1921 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
894e287b 1922 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);
0aa5277c 1923 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
e39c5add
ZW		 1924
1925 /* RING MODE */
c20164db 1926#define RING_REG(base) _MMIO((base) + 0x29c)
0aa5277c
ZY		 1927 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1928 ring_mode_mmio_write);
e39c5add
ZW		 1929#undef RING_REG
1930
0aa5277c
ZY		 1931 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1932 NULL, NULL);
41bfab35
PZ		 1933 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1934 NULL, NULL);
04d348ae 1935 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
20a2bcde 1936 mmio_read_from_hw, NULL);
04d348ae 1937 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
20a2bcde 1938 mmio_read_from_hw, NULL);
e39c5add 1939
0aa5277c
ZY		 1940 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1941 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1942 NULL, NULL);
a045fba4 1943 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 1944 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db 1945 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 1946
c20164db 1947 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c 1948 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db 1949 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
3fcb01f8
WL		 1950 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
1951 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db 1952 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 1953 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1954 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1955 NULL, NULL);
bf3a26b3
WL		 1956 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1957 NULL, NULL);
c20164db
ZW		 1958 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
1959 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
1960 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
1961 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
1962 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
1963 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
1964 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
1965 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
a045fba4 1966 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
187447a1 1967 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 1968
1969 /* display */
c20164db
ZW		 1970 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1971 MMIO_D(_MMIO(0x602a0), D_ALL);
e39c5add 1972
c20164db
ZW		 1973 MMIO_D(_MMIO(0x65050), D_ALL);
1974 MMIO_D(_MMIO(0x650b4), D_ALL);
e39c5add 1975
c20164db 1976 MMIO_D(_MMIO(0xc4040), D_ALL);
e39c5add
ZW		 1977 MMIO_D(DERRMR, D_ALL);
1978
1979 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1980 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1981 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1982 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1983
04d348ae
ZW		 1984 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1985 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1986 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1987 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
e39c5add
ZW		 1988
1989 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1990 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1991 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1992 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1993
1994 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1995 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1996 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1997 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1998
1999 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
2000 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
2001 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
2002 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
2003
2004 MMIO_D(CURCNTR(PIPE_A), D_ALL);
2005 MMIO_D(CURCNTR(PIPE_B), D_ALL);
2006 MMIO_D(CURCNTR(PIPE_C), D_ALL);
2007
2008 MMIO_D(CURPOS(PIPE_A), D_ALL);
2009 MMIO_D(CURPOS(PIPE_B), D_ALL);
2010 MMIO_D(CURPOS(PIPE_C), D_ALL);
2011
2012 MMIO_D(CURBASE(PIPE_A), D_ALL);
2013 MMIO_D(CURBASE(PIPE_B), D_ALL);
2014 MMIO_D(CURBASE(PIPE_C), D_ALL);
2015
b2744f86
CX		 2016 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
2017 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
2018 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL);
2019
c20164db
ZW		 2020 MMIO_D(_MMIO(0x700ac), D_ALL);
2021 MMIO_D(_MMIO(0x710ac), D_ALL);
2022 MMIO_D(_MMIO(0x720ac), D_ALL);
e39c5add 2023
c20164db
ZW		 2024 MMIO_D(_MMIO(0x70090), D_ALL);
2025 MMIO_D(_MMIO(0x70094), D_ALL);
2026 MMIO_D(_MMIO(0x70098), D_ALL);
2027 MMIO_D(_MMIO(0x7009c), D_ALL);
e39c5add
ZW		 2028
2029 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
2030 MMIO_D(DSPADDR(PIPE_A), D_ALL);
2031 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
2032 MMIO_D(DSPPOS(PIPE_A), D_ALL);
2033 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
04d348ae 2034 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 2035 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
2036 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
d57b39e3
CX		 2037 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2038 reg50080_mmio_write);
e39c5add
ZW		 2039
2040 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
2041 MMIO_D(DSPADDR(PIPE_B), D_ALL);
2042 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
2043 MMIO_D(DSPPOS(PIPE_B), D_ALL);
2044 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
04d348ae 2045 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 2046 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
2047 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
d57b39e3
CX		 2048 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2049 reg50080_mmio_write);
e39c5add
ZW		 2050
2051 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
2052 MMIO_D(DSPADDR(PIPE_C), D_ALL);
2053 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
2054 MMIO_D(DSPPOS(PIPE_C), D_ALL);
2055 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
04d348ae 2056 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
e39c5add
ZW		 2057 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
2058 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
d57b39e3
CX		 2059 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2060 reg50080_mmio_write);
e39c5add
ZW		 2061
2062 MMIO_D(SPRCTL(PIPE_A), D_ALL);
2063 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
2064 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
2065 MMIO_D(SPRPOS(PIPE_A), D_ALL);
2066 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
2067 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
2068 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
04d348ae 2069 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 2070 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
2071 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
2072 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
2073 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
d57b39e3
CX		 2074 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2075 reg50080_mmio_write);
e39c5add
ZW		 2076
2077 MMIO_D(SPRCTL(PIPE_B), D_ALL);
2078 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
2079 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
2080 MMIO_D(SPRPOS(PIPE_B), D_ALL);
2081 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
2082 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
2083 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
04d348ae 2084 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 2085 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
2086 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
2087 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
2088 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
d57b39e3
CX		 2089 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2090 reg50080_mmio_write);
e39c5add
ZW		 2091
2092 MMIO_D(SPRCTL(PIPE_C), D_ALL);
2093 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
2094 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
2095 MMIO_D(SPRPOS(PIPE_C), D_ALL);
2096 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
2097 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
2098 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
04d348ae 2099 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
e39c5add
ZW		 2100 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
2101 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
2102 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
2103 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
d57b39e3
CX		 2104 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2105 reg50080_mmio_write);
e39c5add 2106
e39c5add
ZW		 2107 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
2108 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
2109 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
2110 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
2111 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
2112 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
2113 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
2114 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
2115 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
2116
2117 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
2118 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
2119 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
2120 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
2121 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
2122 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
2123 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
2124 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
2125 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
2126
2127 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
2128 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
2129 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
2130 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
2131 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
2132 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
2133 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
2134 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
2135 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
2136
2137 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
2138 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
2139 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
2140 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
2141 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
2142 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
2143 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
2144 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
2145
2146 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
2147 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
2148 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
2149 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
2150 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
2151 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
2152 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
2153 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
2154
2155 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
2156 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
2157 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
2158 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
2159 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
2160 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
2161 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
2162 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
2163
2164 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
2165 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
2166 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
2167 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
2168 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
2169 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
2170 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
2171 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
2172
2173 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
2174 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
2175 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
2176 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
2177 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
2178 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
2179 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
2180 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
2181
2182 MMIO_D(PF_CTL(PIPE_A), D_ALL);
2183 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
2184 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
2185 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
2186 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
2187
2188 MMIO_D(PF_CTL(PIPE_B), D_ALL);
2189 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
2190 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
2191 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
2192 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
2193
2194 MMIO_D(PF_CTL(PIPE_C), D_ALL);
2195 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
2196 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
2197 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
2198 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
2199
2200 MMIO_D(WM0_PIPEA_ILK, D_ALL);
2201 MMIO_D(WM0_PIPEB_ILK, D_ALL);
2202 MMIO_D(WM0_PIPEC_IVB, D_ALL);
2203 MMIO_D(WM1_LP_ILK, D_ALL);
2204 MMIO_D(WM2_LP_ILK, D_ALL);
2205 MMIO_D(WM3_LP_ILK, D_ALL);
2206 MMIO_D(WM1S_LP_ILK, D_ALL);
2207 MMIO_D(WM2S_LP_IVB, D_ALL);
2208 MMIO_D(WM3S_LP_IVB, D_ALL);
2209
2210 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
2211 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
2212 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
2213 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
2214
c20164db 2215 MMIO_D(_MMIO(0x48268), D_ALL);
e39c5add 2216
04d348ae
ZW		 2217 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2218 gmbus_mmio_write);
336662e5 2219 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
c20164db 2220 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add 2221
c20164db 2222 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
04d348ae 2223 dp_aux_ch_ctl_mmio_write);
c20164db 2224 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
04d348ae 2225 dp_aux_ch_ctl_mmio_write);
c20164db 2226 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
04d348ae 2227 dp_aux_ch_ctl_mmio_write);
e39c5add 2228
75e64ff2 2229 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
e39c5add 2230
c20164db
ZW		 2231 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2232 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
e39c5add 2233
04d348ae
ZW		 2234 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2235 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2236 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2237 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2238 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2239 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2240 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2241 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2242 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
e39c5add 2243
c20164db
ZW		 2244 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL);
2245 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL);
2246 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL);
2247 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL);
2248 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL);
2249 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL);
2250 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL);
2251
2252 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL);
2253 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL);
2254 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL);
2255 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL);
2256 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL);
2257 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL);
2258 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL);
2259
2260 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL);
2261 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL);
2262 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL);
2263 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL);
2264 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL);
2265 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL);
2266 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL);
2267 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL);
e39c5add
ZW		 2268
2269 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
2270 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
2271 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
2272
2273 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
2274 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
2275 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
2276
2277 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
2278 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
2279 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
2280
2281 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
2282 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
2283 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
2284
c20164db
ZW		 2285 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL);
2286 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL);
2287 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL);
2288 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL);
2289 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL);
2290 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL);
e39c5add 2291
04d348ae 2292 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
e39c5add
ZW		 2293 MMIO_D(PCH_PP_DIVISOR, D_ALL);
2294 MMIO_D(PCH_PP_STATUS, D_ALL);
2295 MMIO_D(PCH_LVDS, D_ALL);
c20164db
ZW		 2296 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL);
2297 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL);
2298 MMIO_D(_MMIO(_PCH_FPA0), D_ALL);
2299 MMIO_D(_MMIO(_PCH_FPA1), D_ALL);
2300 MMIO_D(_MMIO(_PCH_FPB0), D_ALL);
2301 MMIO_D(_MMIO(_PCH_FPB1), D_ALL);
e39c5add
ZW		 2302 MMIO_D(PCH_DREF_CONTROL, D_ALL);
2303 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
2304 MMIO_D(PCH_DPLL_SEL, D_ALL);
2305
c20164db
ZW		 2306 MMIO_D(_MMIO(0x61208), D_ALL);
2307 MMIO_D(_MMIO(0x6120c), D_ALL);
e39c5add
ZW		 2308 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
2309 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
2310
c20164db
ZW		 2311 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2312 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2313 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2314 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2315 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2316 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
e39c5add
ZW		 2317
2318 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2319 PORTA_HOTPLUG_STATUS_MASK
2320 | PORTB_HOTPLUG_STATUS_MASK
2321 | PORTC_HOTPLUG_STATUS_MASK
2322 | PORTD_HOTPLUG_STATUS_MASK,
2323 NULL, NULL);
2324
04d348ae 2325 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
e39c5add
ZW		 2326 MMIO_D(FUSE_STRAP, D_ALL);
2327 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
2328
2329 MMIO_D(DISP_ARB_CTL, D_ALL);
2330 MMIO_D(DISP_ARB_CTL2, D_ALL);
2331
2332 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
2333 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
2334 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
2335
2336 MMIO_D(SOUTH_CHICKEN1, D_ALL);
04d348ae 2337 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
c20164db
ZW		 2338 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL);
2339 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL);
e39c5add 2340 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
c20164db
ZW		 2341 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL);
2342 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL);
e39c5add
ZW		 2343
2344 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
2345 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2346 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2347 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2348 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2349 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2350 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2351
2352 MMIO_D(IPS_CTL, D_ALL);
2353
2354 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2355 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2356 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2357 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2358 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2359 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2360 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2361 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2362 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2363 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2364 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2365 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2366 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2367
2368 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2369 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2370 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2371 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2372 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2373 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2374 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2375 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2376 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2377 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2378 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2379 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2380 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2381
2382 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2383 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2384 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2385 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2386 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2387 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2388 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2389 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2390 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2391 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2392 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2393 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2394 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2395
04d348ae
ZW		 2396 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2397 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2398 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2399
2400 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2401 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2402 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2403
2404 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2405 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2406 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2407
c20164db
ZW		 2408 MMIO_D(_MMIO(0x60110), D_ALL);
2409 MMIO_D(_MMIO(0x61110), D_ALL);
2410 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2411 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2412 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2413 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2414 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2415 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2416 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2417 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2418 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
e39c5add 2419
0560b0c6
VS		 2420 MMIO_D(WM_LINETIME(PIPE_A), D_ALL);
2421 MMIO_D(WM_LINETIME(PIPE_B), D_ALL);
2422 MMIO_D(WM_LINETIME(PIPE_C), D_ALL);
e39c5add 2423 MMIO_D(SPLL_CTL, D_ALL);
c20164db
ZW		 2424 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL);
2425 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL);
e39c5add
ZW		 2426 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2427 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2428 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2429 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2430 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2431 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2432 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2433 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2434
2435 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
c20164db 2436 MMIO_D(_MMIO(0x46508), D_ALL);
e39c5add 2437
c20164db
ZW		 2438 MMIO_D(_MMIO(0x49080), D_ALL);
2439 MMIO_D(_MMIO(0x49180), D_ALL);
2440 MMIO_D(_MMIO(0x49280), D_ALL);
e39c5add 2441
c20164db
ZW		 2442 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2443 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2444 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 2445
2446 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2447 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2448 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2449
e39c5add
ZW		 2450 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2451 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2452 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2453
2454 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2455 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2456 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2457
2458 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2459 MMIO_D(SBI_ADDR, D_ALL);
04d348ae
ZW		 2460 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2461 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
e39c5add
ZW		 2462 MMIO_D(PIXCLK_GATE, D_ALL);
2463
c20164db 2464 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
04d348ae
ZW		 2465 dp_aux_ch_ctl_mmio_write);
2466
2467 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2468 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2469 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2470 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2471 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2472
2473 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2474 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2475 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2476 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2477 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2478
2479 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2480 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2481 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2482 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2483 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
e39c5add 2484
c20164db
ZW		 2485 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2486 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2487 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2488 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2489 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add
ZW		 2490
2491 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2492 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
b2744f86 2493 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL);
e39c5add 2494
c20164db
ZW		 2495 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2496 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2497 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2498 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
e39c5add 2499
c20164db
ZW		 2500 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL);
2501 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL);
2502 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL);
2503 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL);
e39c5add
ZW		 2504
2505 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2506 MMIO_D(FORCEWAKE_ACK, D_ALL);
2507 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2508 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
0aa5277c
ZY		 2509 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2510 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add 2511 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
a1dcba90 2512 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
e39c5add
ZW		 2513 MMIO_D(ECOBUS, D_ALL);
2514 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2515 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2516 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2517 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2518 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2519 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2520 MMIO_D(GEN6_RPSTAT1, D_ALL);
2521 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2522 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2523 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2524 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2525 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2526 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2527 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2528 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2529 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2530 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2531 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2532 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2533 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2534 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2535 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2536 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2537 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2538 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2539 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2540 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2541 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2542 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2543 MMIO_D(GEN6_PMINTRMSK, D_ALL);
75e39688
ID		 2544 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2545 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2546 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2547 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
a1dcba90 2548 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2549 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
e39c5add
ZW		 2550
2551 MMIO_D(RSTDBYCTL, D_ALL);
2552
2553 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2554 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
04d348ae 2555 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
e39c5add 2556
e39c5add
ZW		 2557 MMIO_D(TILECTL, D_ALL);
2558
2559 MMIO_D(GEN6_UCGCTL1, D_ALL);
2560 MMIO_D(GEN6_UCGCTL2, D_ALL);
2561
c20164db 2562 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL);
e39c5add 2563
e39c5add 2564 MMIO_D(GEN6_PCODE_DATA, D_ALL);
c20164db 2565 MMIO_D(_MMIO(0x13812c), D_ALL);
e39c5add
ZW		 2566 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2567 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2568 MMIO_D(HSW_IDICR, D_ALL);
2569 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2570
c20164db
ZW		 2571 MMIO_D(_MMIO(0x3c), D_ALL);
2572 MMIO_D(_MMIO(0x860), D_ALL);
e39c5add 2573 MMIO_D(ECOSKPD, D_ALL);
c20164db 2574 MMIO_D(_MMIO(0x121d0), D_ALL);
e39c5add 2575 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
c20164db 2576 MMIO_D(_MMIO(0x41d0), D_ALL);
e39c5add 2577 MMIO_D(GAC_ECO_BITS, D_ALL);
c20164db
ZW		 2578 MMIO_D(_MMIO(0x6200), D_ALL);
2579 MMIO_D(_MMIO(0x6204), D_ALL);
2580 MMIO_D(_MMIO(0x6208), D_ALL);
2581 MMIO_D(_MMIO(0x7118), D_ALL);
2582 MMIO_D(_MMIO(0x7180), D_ALL);
2583 MMIO_D(_MMIO(0x7408), D_ALL);
2584 MMIO_D(_MMIO(0x7c00), D_ALL);
975629c3 2585 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
c20164db
ZW		 2586 MMIO_D(_MMIO(0x911c), D_ALL);
2587 MMIO_D(_MMIO(0x9120), D_ALL);
a045fba4 2588 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2589
2590 MMIO_D(GAB_CTL, D_ALL);
c20164db
ZW		 2591 MMIO_D(_MMIO(0x48800), D_ALL);
2592 MMIO_D(_MMIO(0xce044), D_ALL);
2593 MMIO_D(_MMIO(0xe6500), D_ALL);
2594 MMIO_D(_MMIO(0xe6504), D_ALL);
2595 MMIO_D(_MMIO(0xe6600), D_ALL);
2596 MMIO_D(_MMIO(0xe6604), D_ALL);
2597 MMIO_D(_MMIO(0xe6700), D_ALL);
2598 MMIO_D(_MMIO(0xe6704), D_ALL);
2599 MMIO_D(_MMIO(0xe6800), D_ALL);
2600 MMIO_D(_MMIO(0xe6804), D_ALL);
e39c5add
ZW		 2601 MMIO_D(PCH_GMBUS4, D_ALL);
2602 MMIO_D(PCH_GMBUS5, D_ALL);
2603
c20164db
ZW		 2604 MMIO_D(_MMIO(0x902c), D_ALL);
2605 MMIO_D(_MMIO(0xec008), D_ALL);
2606 MMIO_D(_MMIO(0xec00c), D_ALL);
2607 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL);
2608 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL);
2609 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL);
2610 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL);
2611 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL);
2612 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL);
2613 MMIO_D(_MMIO(0xec408), D_ALL);
2614 MMIO_D(_MMIO(0xec40c), D_ALL);
2615 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL);
2616 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL);
2617 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL);
2618 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL);
2619 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL);
2620 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL);
2621 MMIO_D(_MMIO(0xfc810), D_ALL);
2622 MMIO_D(_MMIO(0xfc81c), D_ALL);
2623 MMIO_D(_MMIO(0xfc828), D_ALL);
2624 MMIO_D(_MMIO(0xfc834), D_ALL);
2625 MMIO_D(_MMIO(0xfcc00), D_ALL);
2626 MMIO_D(_MMIO(0xfcc0c), D_ALL);
2627 MMIO_D(_MMIO(0xfcc18), D_ALL);
2628 MMIO_D(_MMIO(0xfcc24), D_ALL);
2629 MMIO_D(_MMIO(0xfd000), D_ALL);
2630 MMIO_D(_MMIO(0xfd00c), D_ALL);
2631 MMIO_D(_MMIO(0xfd018), D_ALL);
2632 MMIO_D(_MMIO(0xfd024), D_ALL);
2633 MMIO_D(_MMIO(0xfd034), D_ALL);
e39c5add
ZW		 2634
2635 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
c20164db
ZW		 2636 MMIO_D(_MMIO(0x2054), D_ALL);
2637 MMIO_D(_MMIO(0x12054), D_ALL);
2638 MMIO_D(_MMIO(0x22054), D_ALL);
2639 MMIO_D(_MMIO(0x1a054), D_ALL);
2640
2641 MMIO_D(_MMIO(0x44070), D_ALL);
2642 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2643 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2644 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2645 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2646 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2647
2648 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2649 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS);
2650 MMIO_D(_MMIO(0x2360), D_BDW_PLUS);
2651 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2652 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2653 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2654
2655 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2656 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
0aa5277c
ZY		 2657 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2658
2659 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2660 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2661 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2662 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2663 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2664 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2665 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2666 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2667 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2668 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2669 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
c20164db
ZW		 2670 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2671 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2672 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2673 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2674 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2675 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add 2676
9112caaf
ZY		 2677 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2678 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
c20164db
ZW		 2679 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2680 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2681 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
9112caaf
ZY		 2682 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2683 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
c20164db
ZW		 2684 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2685 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2686 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2687 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
5e7154ff
LZ		 2688
2689 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2690 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
5e822e44
GF		 2691 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2692
12d14cc4
ZW		 2693 return 0;
2694}
2695
72588ffd 2696static int init_bdw_mmio_info(struct intel_gvt *gvt)
12d14cc4 2697{
e39c5add 2698 struct drm_i915_private *dev_priv = gvt->dev_priv;
12d14cc4
ZW		 2699 int ret;
2700
e39c5add
ZW		 2701 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2702 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2703 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2704 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2705
2706 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2707 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2708 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2709 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2710
2711 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2712 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2713 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2714 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2715
2716 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2717 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2718 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2719 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2720
2721 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2722 intel_vgpu_reg_imr_handler);
2723 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2724 intel_vgpu_reg_ier_handler);
2725 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2726 intel_vgpu_reg_iir_handler);
2727 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2728
2729 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2730 intel_vgpu_reg_imr_handler);
2731 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2732 intel_vgpu_reg_ier_handler);
2733 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2734 intel_vgpu_reg_iir_handler);
2735 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2736
2737 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2738 intel_vgpu_reg_imr_handler);
2739 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2740 intel_vgpu_reg_ier_handler);
2741 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2742 intel_vgpu_reg_iir_handler);
2743 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2744
2745 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2746 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2747 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2748 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2749
2750 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2751 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2752 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2753 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2754
2755 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2756 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2757 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2758 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2759
2760 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2761 intel_vgpu_reg_master_irq_handler);
2762
894e287b
XZ		 2763 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,
2764 mmio_read_from_hw, NULL);
e39c5add 2765
c20164db 2766#define RING_REG(base) _MMIO((base) + 0xd0)
2fb39fad
DC		 2767 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2768 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2769 ring_reset_ctl_write);
2fb39fad
DC		 2770#undef RING_REG
2771
c20164db 2772#define RING_REG(base) _MMIO((base) + 0x230)
28c4c6ca 2773 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
e39c5add
ZW		 2774#undef RING_REG
2775
c20164db 2776#define RING_REG(base) _MMIO((base) + 0x234)
0aa5277c
ZY		 2777 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2778 NULL, NULL);
e39c5add
ZW		 2779#undef RING_REG
2780
c20164db 2781#define RING_REG(base) _MMIO((base) + 0x244)
0aa5277c 2782 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2783#undef RING_REG
2784
c20164db 2785#define RING_REG(base) _MMIO((base) + 0x370)
e39c5add 2786 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2787#undef RING_REG
2788
c20164db 2789#define RING_REG(base) _MMIO((base) + 0x3a0)
e39c5add 2790 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
e39c5add
ZW		 2791#undef RING_REG
2792
2793 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2794 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2795 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
c20164db 2796 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS);
e39c5add
ZW		 2797 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2798 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
c20164db 2799 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS);
e39c5add 2800
8bcd7c18
WL		 2801 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2802
e39c5add
ZW		 2803 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2804 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2805
2806 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2807
c20164db 2808#define RING_REG(base) _MMIO((base) + 0x270)
e39c5add 2809 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
e39c5add
ZW		 2810#undef RING_REG
2811
a2ae95af 2812 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
e39c5add 2813
a045fba4 2814 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
e39c5add 2815
593e59b4
ZY		 2816 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2817 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2818 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
e39c5add
ZW		 2819
2820 MMIO_D(WM_MISC, D_BDW);
4ab4fa10 2821 MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
e39c5add 2822
b2744f86 2823 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
c20164db
ZW		 2824 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
2825 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS);
e39c5add
ZW		 2826
2827 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2828
2829 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2830 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2831 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2832
c20164db 2833 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS);
0aa5277c
ZY		 2834 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2835 NULL, NULL);
2836 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2837 NULL, NULL);
2838 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add 2839
c20164db
ZW		 2840 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2841 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2842 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
c20164db
ZW		 2843 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2844 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2845 MMIO_D(_MMIO(0xb110), D_BDW);
e39c5add 2846
c20164db 2847 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
e6cedfea 2848 NULL, force_nonpriv_write);
e39c5add 2849
c20164db
ZW		 2850 MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
2851 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
593e59b4 2852
c20164db 2853 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 2854 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2855
c20164db 2856 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
e39c5add 2857
c20164db 2858 MMIO_D(_MMIO(0x110000), D_BDW_PLUS);
e39c5add 2859
c20164db 2860 MMIO_D(_MMIO(0x48400), D_BDW_PLUS);
e39c5add 2861
c20164db
ZW		 2862 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS);
2863 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS);
e39c5add 2864
c20164db
ZW		 2865 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2866 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
a045fba4 2867 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
c20164db
ZW		 2868 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2869
2870 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2871
2872 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2873 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2874 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2875 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2876 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2877 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2878 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2879 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2880 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
ba0a64bc 2881 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
12d14cc4
ZW		 2882 return 0;
2883}
2884
e39c5add
ZW		 2885static int init_skl_mmio_info(struct intel_gvt *gvt)
2886{
2887 struct drm_i915_private *dev_priv = gvt->dev_priv;
2888 int ret;
2889
2890 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2891 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2892 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2893 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2894 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2895 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2896
47c41af7 2897 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
5cf5fe8f 2898 dp_aux_ch_ctl_mmio_write);
47c41af7 2899 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
5cf5fe8f 2900 dp_aux_ch_ctl_mmio_write);
47c41af7 2901 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
5cf5fe8f
XH		 2902 dp_aux_ch_ctl_mmio_write);
2903
75e39688
ID		 2904 MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2905 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
e39c5add 2906
2570b7e3 2907 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
9174c1d6 2908
43226e6f 2909 MMIO_D(GEN9_PG_ENABLE, D_SKL_PLUS);
e39c5add
ZW		 2910 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2911 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
a045fba4 2912 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
43226e6f
XZ		 2913 MMIO_DH(MMCD_MISC_CTRL, D_SKL_PLUS, NULL, NULL);
2914 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2915 MMIO_D(DC_STATE_EN, D_SKL_PLUS);
2916 MMIO_D(DC_STATE_DEBUG, D_SKL_PLUS);
2917 MMIO_D(CDCLK_CTL, D_SKL_PLUS);
2918 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2919 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2920 MMIO_D(_MMIO(_DPLL1_CFGCR1), D_SKL_PLUS);
2921 MMIO_D(_MMIO(_DPLL2_CFGCR1), D_SKL_PLUS);
2922 MMIO_D(_MMIO(_DPLL3_CFGCR1), D_SKL_PLUS);
2923 MMIO_D(_MMIO(_DPLL1_CFGCR2), D_SKL_PLUS);
2924 MMIO_D(_MMIO(_DPLL2_CFGCR2), D_SKL_PLUS);
2925 MMIO_D(_MMIO(_DPLL3_CFGCR2), D_SKL_PLUS);
2926 MMIO_D(DPLL_CTRL1, D_SKL_PLUS);
2927 MMIO_D(DPLL_CTRL2, D_SKL_PLUS);
2928 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
5cf5fe8f
XH		 2929
2930 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2931 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2932 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2933 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2934 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2935 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2936
2937 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2938 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2939 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2940 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2941 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2942 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2943
2944 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2945 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2946 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2947 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2948 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2949 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2950
2951 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2952 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2953 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2954 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2955
2956 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2957 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2958 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2959 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2960
2961 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2962 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2963 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2964 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2965
2966 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2967 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2968 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2969
2970 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2971 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2972 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2973
2974 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2975 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2976 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2977
2978 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2979 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2980 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2981
2982 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2983 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2984 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL);
2985
2986 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2987 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2988 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2989
2990 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2991 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2992 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2993
2994 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2995 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2996 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2997
2998 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2999 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
3000 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
3001
3002 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
3003 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
3004 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
3005 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
3006
3007 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
3008 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
3009 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
3010 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
3011
3012 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
3013 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
3014 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
3015 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
3016
c20164db
ZW		 3017 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3018 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3019 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3020 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3021
c20164db
ZW		 3022 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3023 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3024 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3025 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3026
c20164db
ZW		 3027 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3028 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3029 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3030 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3031
c20164db
ZW		 3032 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
3033 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
3034 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
3035 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3036
c20164db
ZW		 3037 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
3038 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
3039 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
3040 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3041
c20164db
ZW		 3042 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
3043 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
3044 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
3045 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
5cf5fe8f 3046
43226e6f
XZ		 3047 MMIO_D(_MMIO(_PLANE_CTL_3_A), D_SKL_PLUS);
3048 MMIO_D(_MMIO(_PLANE_CTL_3_B), D_SKL_PLUS);
c20164db 3049 MMIO_D(_MMIO(0x72380), D_SKL_PLUS);
b2744f86 3050 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
43226e6f 3051 MMIO_D(_MMIO(_PLANE_SURF_3_A), D_SKL_PLUS);
5cf5fe8f 3052
43226e6f
XZ		 3053 MMIO_D(CSR_SSP_BASE, D_SKL_PLUS);
3054 MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
3055 MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
5cf5fe8f 3056
3fcb01f8 3057 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
5cf5fe8f 3058
43226e6f
XZ		 3059 MMIO_D(SKL_DFSM, D_SKL_PLUS);
3060 MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
5cf5fe8f 3061
43226e6f 3062 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
d71cb712 3063 NULL, NULL);
43226e6f 3064 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
d71cb712 3065 NULL, NULL);
5cf5fe8f 3066
b2744f86 3067 MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
c20164db 3068 MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
b2744f86 3069 MMIO_D(RC6_LOCATION, D_SKL_PLUS);
3fcb01f8
WL		 3070 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
3071 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
43226e6f 3072 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
d71cb712 3073 NULL, NULL);
e39c5add
ZW		 3074
3075 /* TRTT */
43226e6f
XZ		 3076 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3077 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3078 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3079 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3080 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
3081 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS,
d71cb712
CX		 3082 NULL, gen9_trtte_write);
3083 MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
e39c5add 3084
d71cb712 3085 MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
e39c5add 3086
d71cb712 3087 MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
e39c5add 3088
d71cb712 3089 MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
3fcb01f8 3090 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
e39c5add
ZW		 3091 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
3092
c20164db 3093 MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
43226e6f 3094 MMIO_D(GEN6_STOLEN_RESERVED, D_SKL_PLUS);
d71cb712
CX		 3095 MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
3096 MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
3097 MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
3098 MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
3099 MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
3100 MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
3101 MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
3102 MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
c20164db
ZW		 3103
3104 MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
3105 MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
3106 MMIO_D(_MMIO(0x72034), D_SKL_PLUS);
3107
3108 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS);
3109 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS);
3110 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS);
03fa9350
PZ		 3111 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS);
3112 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS);
3113 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS);
c20164db
ZW		 3114 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS);
3115 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS);
3116 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS);
3117
3118 MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
cb2808da
CX		 3119#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
3120 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3121 NULL, csfe_chicken1_mmio_write);
3122#undef CSFE_CHICKEN1_REG
d71cb712 3123 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
b9b824a5
CX		 3124 NULL, NULL);
3125 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
3126 NULL, NULL);
5cf5fe8f 3127
43226e6f
XZ		 3128 MMIO_D(GAMT_CHKN_BIT_REG, D_KBL);
3129 MMIO_D(GEN9_CTX_PREEMPT_REG, D_KBL | D_SKL);
d71cb712
CX		 3130
3131 return 0;
3132}
3133
3134static int init_bxt_mmio_info(struct intel_gvt *gvt)
3135{
3136 struct drm_i915_private *dev_priv = gvt->dev_priv;
3137 int ret;
3138
3139 MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
3140
3141 MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
3142 MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
3143 MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
3144 MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
3145 MMIO_D(ERROR_GEN6, D_BXT);
3146 MMIO_D(DONE_REG, D_BXT);
3147 MMIO_D(EIR, D_BXT);
3148 MMIO_D(PGTBL_ER, D_BXT);
3149 MMIO_D(_MMIO(0x4194), D_BXT);
3150 MMIO_D(_MMIO(0x4294), D_BXT);
3151 MMIO_D(_MMIO(0x4494), D_BXT);
3152
3153 MMIO_RING_D(RING_PSMI_CTL, D_BXT);
3154 MMIO_RING_D(RING_DMA_FADD, D_BXT);
3155 MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
3156 MMIO_RING_D(RING_IPEHR, D_BXT);
3157 MMIO_RING_D(RING_INSTPS, D_BXT);
3158 MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
3159 MMIO_RING_D(RING_BBSTATE, D_BXT);
3160 MMIO_RING_D(RING_IPEIR, D_BXT);
3161
3162 MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
3163
3164 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
3165 MMIO_D(BXT_RP_STATE_CAP, D_BXT);
3166 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
3167 NULL, bxt_phy_ctl_family_write);
3168 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
3169 NULL, bxt_phy_ctl_family_write);
3170 MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
3171 MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
3172 MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
3173 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
3174 NULL, bxt_port_pll_enable_write);
3175 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
3176 NULL, bxt_port_pll_enable_write);
3177 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
3178 bxt_port_pll_enable_write);
3179
3180 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
3181 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
3182 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
3183 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
3184 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
3185 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
3186 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
3187 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
3188 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
3189
3190 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
3191 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
3192 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
3193 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
3194 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
3195 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
3196 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
3197 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
3198 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
3199
3200 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
3201 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
3202 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3203 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3204 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
3205 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
3206 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
3207 NULL, bxt_pcs_dw12_grp_write);
3208 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3209 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3210 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
3211 bxt_port_tx_dw3_read, NULL);
3212 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3213 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
3214 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
3215 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3216 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3217 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3218 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3219 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
3220 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
3221 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
3222 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
3223 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
3224 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
3225 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
3226 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
3227
3228 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
3229 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
3230 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3231 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3232 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
3233 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
3234 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
3235 NULL, bxt_pcs_dw12_grp_write);
3236 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3237 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3238 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
3239 bxt_port_tx_dw3_read, NULL);
3240 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3241 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
3242 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
3243 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3244 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3245 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3246 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3247 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
3248 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
3249 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
3250 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
3251 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
3252 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
3253 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
3254 MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
3255
3256 MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
3257 MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
3258 MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3259 MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3260 MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
3261 MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
3262 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
3263 NULL, bxt_pcs_dw12_grp_write);
3264 MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3265 MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3266 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
3267 bxt_port_tx_dw3_read, NULL);
3268 MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3269 MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
3270 MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
3271 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3272 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3273 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3274 MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3275 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
3276 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
3277 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
3278 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
3279 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
3280 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
3281 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
3282 MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
3283
3284 MMIO_D(BXT_DE_PLL_CTL, D_BXT);
3285 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
3286 MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
3287 MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
3288
3289 MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
d817de3b 3290 MMIO_D(GEN9_CLKGATE_DIS_4, D_BXT);
d71cb712
CX		 3291
3292 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3293 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3294 MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3295
3296 MMIO_D(RC6_CTX_BASE, D_BXT);
3297
3298 MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
3299 MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
3300 MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
3301 MMIO_D(GEN6_GFXPAUSE, D_BXT);
3fcb01f8 3302 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
d71cb712
CX		 3303
3304 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
5cf5fe8f 3305
e39c5add
ZW		 3306 return 0;
3307}
04d348ae 3308
65f9f6fe
CD		 3309static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
3310 unsigned int offset)
3311{
3312 unsigned long device = intel_gvt_get_device_type(gvt);
02b6ed44
TZ		 3313 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3314 int num = gvt->mmio.num_mmio_block;
65f9f6fe 3315 int i;
12d14cc4 3316
02b6ed44 3317 for (i = 0; i < num; i++, block++) {
65f9f6fe
CD		 3318 if (!(device & block->device))
3319 continue;
c20164db
ZW		 3320 if (offset >= i915_mmio_reg_offset(block->offset) &&
3321 offset < i915_mmio_reg_offset(block->offset) + block->size)
65f9f6fe 3322 return block;
12d14cc4
ZW		 3323 }
3324 return NULL;
3325}
3326
3327/**
3328 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
3329 * @gvt: GVT device
3330 *
3331 * This function is called at the driver unloading stage, to clean up the MMIO
3332 * information table of GVT device
3333 *
3334 */
3335void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
3336{
3337 struct hlist_node *tmp;
3338 struct intel_gvt_mmio_info *e;
3339 int i;
3340
3341 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
3342 kfree(e);
3343
3344 vfree(gvt->mmio.mmio_attribute);
3345 gvt->mmio.mmio_attribute = NULL;
3346}
3347
02b6ed44
TZ		 3348/* Special MMIO blocks. */
3349static struct gvt_mmio_block mmio_blocks[] = {
3350 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL},
8631fef7 3351 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
02b6ed44
TZ		 3352 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
3353 pvinfo_mmio_read, pvinfo_mmio_write},
3354 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL},
3355 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL},
3356 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL},
3357};
3358
12d14cc4
ZW		 3359/**
3360 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
3361 * @gvt: GVT device
3362 *
3363 * This function is called at the initialization stage, to setup the MMIO
3364 * information table for GVT device
3365 *
3366 * Returns:
3367 * zero on success, negative if failed.
3368 */
3369int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
3370{
3371 struct intel_gvt_device_info *info = &gvt->device_info;
3372 struct drm_i915_private *dev_priv = gvt->dev_priv;
56a78de5 3373 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
12d14cc4
ZW		 3374 int ret;
3375
56a78de5 3376 gvt->mmio.mmio_attribute = vzalloc(size);
12d14cc4
ZW		 3377 if (!gvt->mmio.mmio_attribute)
3378 return -ENOMEM;
3379
3380 ret = init_generic_mmio_info(gvt);
3381 if (ret)
3382 goto err;
3383
3384 if (IS_BROADWELL(dev_priv)) {
72588ffd 3385 ret = init_bdw_mmio_info(gvt);
12d14cc4
ZW		 3386 if (ret)
3387 goto err;
e3476c00 3388 } else if (IS_SKYLAKE(dev_priv)
c3b5a843 3389 || IS_KABYLAKE(dev_priv)
3390 || IS_COFFEELAKE(dev_priv)) {
72588ffd 3391 ret = init_bdw_mmio_info(gvt);
e39c5add
ZW		 3392 if (ret)
3393 goto err;
3394 ret = init_skl_mmio_info(gvt);
3395 if (ret)
3396 goto err;
d71cb712 3397 } else if (IS_BROXTON(dev_priv)) {
72588ffd 3398 ret = init_bdw_mmio_info(gvt);
d71cb712
CX		 3399 if (ret)
3400 goto err;
3401 ret = init_skl_mmio_info(gvt);
3402 if (ret)
3403 goto err;
3404 ret = init_bxt_mmio_info(gvt);
3405 if (ret)
3406 goto err;
12d14cc4 3407 }
fbfd76c3 3408
02b6ed44
TZ		 3409 gvt->mmio.mmio_block = mmio_blocks;
3410 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks);
3411
12d14cc4
ZW		 3412 return 0;
3413err:
3414 intel_gvt_clean_mmio_info(gvt);
3415 return ret;
3416}
e39c5add 3417
7cb16018
CD		 3418/**
3419 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3420 * @gvt: a GVT device
3421 * @handler: the handler
3422 * @data: private data given to handler
3423 *
3424 * Returns:
3425 * Zero on success, negative error code if failed.
3426 */
3427int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3428 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3429 void *data)
3430{
3431 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3432 struct intel_gvt_mmio_info *e;
3433 int i, j, ret;
3434
3435 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3436 ret = handler(gvt, e->offset, data);
3437 if (ret)
3438 return ret;
3439 }
3440
3441 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
83faaf07
TZ		 3442 /* pvinfo data doesn't come from hw mmio */
3443 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3444 continue;
3445
7cb16018
CD		 3446 for (j = 0; j < block->size; j += 4) {
3447 ret = handler(gvt,
c20164db
ZW		 3448 i915_mmio_reg_offset(block->offset) + j,
3449 data);
7cb16018
CD		 3450 if (ret)
3451 return ret;
3452 }
3453 }
3454 return 0;
3455}
e39c5add
ZW		 3456
3457/**
3458 * intel_vgpu_default_mmio_read - default MMIO read handler
3459 * @vgpu: a vGPU
3460 * @offset: access offset
3461 * @p_data: data return buffer
3462 * @bytes: access data length
3463 *
3464 * Returns:
3465 * Zero on success, negative error code if failed.
3466 */
3467int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3468 void *p_data, unsigned int bytes)
3469{
3470 read_vreg(vgpu, offset, p_data, bytes);
3471 return 0;
3472}
3473
3474/**
3475 * intel_t_default_mmio_write - default MMIO write handler
3476 * @vgpu: a vGPU
3477 * @offset: access offset
3478 * @p_data: write data buffer
3479 * @bytes: access data length
3480 *
3481 * Returns:
3482 * Zero on success, negative error code if failed.
3483 */
3484int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3485 void *p_data, unsigned int bytes)
3486{
3487 write_vreg(vgpu, offset, p_data, bytes);
3488 return 0;
3489}
4938ca90 3490
6cef21a1
HY		 3491/**
3492 * intel_vgpu_mask_mmio_write - write mask register
3493 * @vgpu: a vGPU
3494 * @offset: access offset
3495 * @p_data: write data buffer
3496 * @bytes: access data length
3497 *
3498 * Returns:
3499 * Zero on success, negative error code if failed.
3500 */
3501int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3502 void *p_data, unsigned int bytes)
3503{
3504 u32 mask, old_vreg;
3505
3506 old_vreg = vgpu_vreg(vgpu, offset);
3507 write_vreg(vgpu, offset, p_data, bytes);
3508 mask = vgpu_vreg(vgpu, offset) >> 16;
3509 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3510 (vgpu_vreg(vgpu, offset) & mask);
3511
3512 return 0;
3513}
3514
4938ca90
ZY		 3515/**
3516 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3517 * force-nopriv register
3518 *
3519 * @gvt: a GVT device
3520 * @offset: register offset
3521 *
3522 * Returns:
3523 * True if the register is in force-nonpriv whitelist;
3524 * False if outside;
3525 */
3526bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3527 unsigned int offset)
3528{
3529 return in_whitelist(offset);
3530}
65f9f6fe
CD		 3531
3532/**
3533 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3534 * @vgpu: a vGPU
3535 * @offset: register offset
3536 * @pdata: data buffer
3537 * @bytes: data length
a752b070 3538 * @is_read: read or write
65f9f6fe
CD		 3539 *
3540 * Returns:
3541 * Zero on success, negative error code if failed.
3542 */
3543int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3544 void *pdata, unsigned int bytes, bool is_read)
3545{
12d58619 3546 struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
65f9f6fe
CD		 3547 struct intel_gvt *gvt = vgpu->gvt;
3548 struct intel_gvt_mmio_info *mmio_info;
3549 struct gvt_mmio_block *mmio_block;
3550 gvt_mmio_func func;
3551 int ret;
3552
12d58619 3553 if (drm_WARN_ON(&i915->drm, bytes > 8))
65f9f6fe
CD		 3554 return -EINVAL;
3555
3556 /*
3557 * Handle special MMIO blocks.
3558 */
3559 mmio_block = find_mmio_block(gvt, offset);
3560 if (mmio_block) {
3561 func = is_read ? mmio_block->read : mmio_block->write;
3562 if (func)
3563 return func(vgpu, offset, pdata, bytes);
3564 goto default_rw;
3565 }
3566
3567 /*
3568 * Normal tracked MMIOs.
3569 */
3570 mmio_info = find_mmio_info(gvt, offset);
3571 if (!mmio_info) {
b99f514f 3572 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
65f9f6fe
CD		 3573 goto default_rw;
3574 }
3575
65f9f6fe
CD		 3576 if (is_read)
3577 return mmio_info->read(vgpu, offset, pdata, bytes);
3578 else {
3579 u64 ro_mask = mmio_info->ro_mask;
9c1c8416 3580 u32 old_vreg = 0;
65f9f6fe
CD		 3581 u64 data = 0;
3582
3583 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3584 old_vreg = vgpu_vreg(vgpu, offset);
65f9f6fe
CD		 3585 }
3586
3587 if (likely(!ro_mask))
3588 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3589 else if (!~ro_mask) {
3590 gvt_vgpu_err("try to write RO reg %x\n", offset);
3591 return 0;
3592 } else {
3593 /* keep the RO bits in the virtual register */
3594 memcpy(&data, pdata, bytes);
3595 data &= ~ro_mask;
3596 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3597 ret = mmio_info->write(vgpu, offset, &data, bytes);
3598 }
3599
3600 /* higher 16bits of mode ctl regs are mask bits for change */
3601 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3602 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3603
3604 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3605 | (vgpu_vreg(vgpu, offset) & mask);
65f9f6fe
CD		 3606 }
3607 }
3608
3609 return ret;
3610
3611default_rw:
3612 return is_read ?
3613 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3614 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3615}
Linux 6.x block layer and io_uring tree(s)