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12d14cc4 ZW |
1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Kevin Tian <kevin.tian@intel.com> | |
25 | * Eddie Dong <eddie.dong@intel.com> | |
26 | * Zhiyuan Lv <zhiyuan.lv@intel.com> | |
27 | * | |
28 | * Contributors: | |
29 | * Min He <min.he@intel.com> | |
30 | * Tina Zhang <tina.zhang@intel.com> | |
31 | * Pei Zhang <pei.zhang@intel.com> | |
32 | * Niu Bing <bing.niu@intel.com> | |
33 | * Ping Gao <ping.a.gao@intel.com> | |
34 | * Zhi Wang <zhi.a.wang@intel.com> | |
35 | * | |
36 | ||
37 | */ | |
38 | ||
39 | #include "i915_drv.h" | |
feddf6e8 ZW |
40 | #include "gvt.h" |
41 | #include "i915_pvinfo.h" | |
12d14cc4 | 42 | |
e39c5add ZW |
43 | /* XXX FIXME i915 has changed PP_XXX definition */ |
44 | #define PCH_PP_STATUS _MMIO(0xc7200) | |
45 | #define PCH_PP_CONTROL _MMIO(0xc7204) | |
46 | #define PCH_PP_ON_DELAYS _MMIO(0xc7208) | |
47 | #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) | |
48 | #define PCH_PP_DIVISOR _MMIO(0xc7210) | |
49 | ||
12d14cc4 ZW |
50 | /* Register contains RO bits */ |
51 | #define F_RO (1 << 0) | |
52 | /* Register contains graphics address */ | |
53 | #define F_GMADR (1 << 1) | |
54 | /* Mode mask registers with high 16 bits as the mask bits */ | |
55 | #define F_MODE_MASK (1 << 2) | |
56 | /* This reg can be accessed by GPU commands */ | |
57 | #define F_CMD_ACCESS (1 << 3) | |
58 | /* This reg has been accessed by a VM */ | |
59 | #define F_ACCESSED (1 << 4) | |
60 | /* This reg has been accessed through GPU commands */ | |
61 | #define F_CMD_ACCESSED (1 << 5) | |
62 | /* This reg could be accessed by unaligned address */ | |
63 | #define F_UNALIGN (1 << 6) | |
64 | ||
65 | unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) | |
66 | { | |
67 | if (IS_BROADWELL(gvt->dev_priv)) | |
68 | return D_BDW; | |
69 | else if (IS_SKYLAKE(gvt->dev_priv)) | |
70 | return D_SKL; | |
e3476c00 XH |
71 | else if (IS_KABYLAKE(gvt->dev_priv)) |
72 | return D_KBL; | |
12d14cc4 ZW |
73 | |
74 | return 0; | |
75 | } | |
76 | ||
77 | bool intel_gvt_match_device(struct intel_gvt *gvt, | |
78 | unsigned long device) | |
79 | { | |
80 | return intel_gvt_get_device_type(gvt) & device; | |
81 | } | |
82 | ||
e39c5add ZW |
83 | static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, |
84 | void *p_data, unsigned int bytes) | |
85 | { | |
86 | memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); | |
87 | } | |
88 | ||
89 | static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, | |
90 | void *p_data, unsigned int bytes) | |
91 | { | |
92 | memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); | |
93 | } | |
94 | ||
12d14cc4 ZW |
95 | static int new_mmio_info(struct intel_gvt *gvt, |
96 | u32 offset, u32 flags, u32 size, | |
97 | u32 addr_mask, u32 ro_mask, u32 device, | |
3e70c5d6 NI |
98 | int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned int), |
99 | int (*write)(struct intel_vgpu *, unsigned int, void *, unsigned int)) | |
12d14cc4 ZW |
100 | { |
101 | struct intel_gvt_mmio_info *info, *p; | |
102 | u32 start, end, i; | |
103 | ||
104 | if (!intel_gvt_match_device(gvt, device)) | |
105 | return 0; | |
106 | ||
107 | if (WARN_ON(!IS_ALIGNED(offset, 4))) | |
108 | return -EINVAL; | |
109 | ||
110 | start = offset; | |
111 | end = offset + size; | |
112 | ||
113 | for (i = start; i < end; i += 4) { | |
114 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
115 | if (!info) | |
116 | return -ENOMEM; | |
117 | ||
118 | info->offset = i; | |
119 | p = intel_gvt_find_mmio_info(gvt, info->offset); | |
120 | if (p) | |
121 | gvt_err("dup mmio definition offset %x\n", | |
122 | info->offset); | |
123 | info->size = size; | |
124 | info->length = (i + 4) < end ? 4 : (end - i); | |
125 | info->addr_mask = addr_mask; | |
4ec3dd89 | 126 | info->ro_mask = ro_mask; |
12d14cc4 | 127 | info->device = device; |
e39c5add ZW |
128 | info->read = read ? read : intel_vgpu_default_mmio_read; |
129 | info->write = write ? write : intel_vgpu_default_mmio_write; | |
12d14cc4 ZW |
130 | gvt->mmio.mmio_attribute[info->offset / 4] = flags; |
131 | INIT_HLIST_NODE(&info->node); | |
132 | hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); | |
133 | } | |
134 | return 0; | |
135 | } | |
136 | ||
28c4c6ca ZW |
137 | static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg) |
138 | { | |
0fac21e7 ZW |
139 | enum intel_engine_id id; |
140 | struct intel_engine_cs *engine; | |
28c4c6ca ZW |
141 | |
142 | reg &= ~GENMASK(11, 0); | |
0fac21e7 ZW |
143 | for_each_engine(engine, gvt->dev_priv, id) { |
144 | if (engine->mmio_base == reg) | |
145 | return id; | |
28c4c6ca ZW |
146 | } |
147 | return -1; | |
148 | } | |
149 | ||
e39c5add ZW |
150 | #define offset_to_fence_num(offset) \ |
151 | ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) | |
152 | ||
153 | #define fence_num_to_offset(num) \ | |
154 | (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) | |
155 | ||
fd64be63 MH |
156 | |
157 | static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) | |
158 | { | |
159 | switch (reason) { | |
160 | case GVT_FAILSAFE_UNSUPPORTED_GUEST: | |
161 | pr_err("Detected your guest driver doesn't support GVT-g.\n"); | |
162 | break; | |
a33fc7a0 MH |
163 | case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: |
164 | pr_err("Graphics resource is not enough for the guest\n"); | |
fd64be63 MH |
165 | default: |
166 | break; | |
167 | } | |
168 | pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); | |
169 | vgpu->failsafe = true; | |
170 | } | |
171 | ||
e39c5add ZW |
172 | static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, |
173 | unsigned int fence_num, void *p_data, unsigned int bytes) | |
174 | { | |
175 | if (fence_num >= vgpu_fence_sz(vgpu)) { | |
fd64be63 MH |
176 | |
177 | /* When guest access oob fence regs without access | |
178 | * pv_info first, we treat guest not supporting GVT, | |
179 | * and we will let vgpu enter failsafe mode. | |
180 | */ | |
d1be371d | 181 | if (!vgpu->pv_notified) |
fd64be63 MH |
182 | enter_failsafe_mode(vgpu, |
183 | GVT_FAILSAFE_UNSUPPORTED_GUEST); | |
d1be371d ZX |
184 | |
185 | if (!vgpu->mmio.disable_warn_untrack) { | |
695fbc08 TZ |
186 | gvt_vgpu_err("found oob fence register access\n"); |
187 | gvt_vgpu_err("total fence %d, access fence %d\n", | |
188 | vgpu_fence_sz(vgpu), fence_num); | |
fd64be63 | 189 | } |
e39c5add | 190 | memset(p_data, 0, bytes); |
d1be371d | 191 | return -EINVAL; |
e39c5add ZW |
192 | } |
193 | return 0; | |
194 | } | |
195 | ||
196 | static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, | |
197 | void *p_data, unsigned int bytes) | |
198 | { | |
199 | int ret; | |
200 | ||
201 | ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), | |
202 | p_data, bytes); | |
203 | if (ret) | |
204 | return ret; | |
205 | read_vreg(vgpu, off, p_data, bytes); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, | |
210 | void *p_data, unsigned int bytes) | |
211 | { | |
212 | unsigned int fence_num = offset_to_fence_num(off); | |
213 | int ret; | |
214 | ||
215 | ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); | |
216 | if (ret) | |
217 | return ret; | |
218 | write_vreg(vgpu, off, p_data, bytes); | |
219 | ||
220 | intel_vgpu_write_fence(vgpu, fence_num, | |
221 | vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); | |
222 | return 0; | |
223 | } | |
224 | ||
225 | #define CALC_MODE_MASK_REG(old, new) \ | |
226 | (((new) & GENMASK(31, 16)) \ | |
227 | | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ | |
228 | | ((new) & ((new) >> 16)))) | |
229 | ||
230 | static int mul_force_wake_write(struct intel_vgpu *vgpu, | |
231 | unsigned int offset, void *p_data, unsigned int bytes) | |
232 | { | |
233 | u32 old, new; | |
234 | uint32_t ack_reg_offset; | |
235 | ||
236 | old = vgpu_vreg(vgpu, offset); | |
237 | new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); | |
238 | ||
e3476c00 XH |
239 | if (IS_SKYLAKE(vgpu->gvt->dev_priv) |
240 | || IS_KABYLAKE(vgpu->gvt->dev_priv)) { | |
e39c5add ZW |
241 | switch (offset) { |
242 | case FORCEWAKE_RENDER_GEN9_REG: | |
243 | ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; | |
244 | break; | |
245 | case FORCEWAKE_BLITTER_GEN9_REG: | |
246 | ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; | |
247 | break; | |
248 | case FORCEWAKE_MEDIA_GEN9_REG: | |
249 | ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; | |
250 | break; | |
251 | default: | |
252 | /*should not hit here*/ | |
695fbc08 | 253 | gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); |
39762ad4 | 254 | return -EINVAL; |
e39c5add ZW |
255 | } |
256 | } else { | |
257 | ack_reg_offset = FORCEWAKE_ACK_HSW_REG; | |
258 | } | |
259 | ||
260 | vgpu_vreg(vgpu, offset) = new; | |
261 | vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); | |
262 | return 0; | |
263 | } | |
264 | ||
265 | static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
c34eaa8d | 266 | void *p_data, unsigned int bytes) |
e39c5add | 267 | { |
c34eaa8d | 268 | unsigned int engine_mask = 0; |
e39c5add | 269 | u32 data; |
e39c5add | 270 | |
40d2428b | 271 | write_vreg(vgpu, offset, p_data, bytes); |
e39c5add ZW |
272 | data = vgpu_vreg(vgpu, offset); |
273 | ||
274 | if (data & GEN6_GRDOM_FULL) { | |
275 | gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); | |
c34eaa8d CD |
276 | engine_mask = ALL_ENGINES; |
277 | } else { | |
278 | if (data & GEN6_GRDOM_RENDER) { | |
279 | gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); | |
280 | engine_mask |= (1 << RCS); | |
281 | } | |
282 | if (data & GEN6_GRDOM_MEDIA) { | |
283 | gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); | |
284 | engine_mask |= (1 << VCS); | |
285 | } | |
286 | if (data & GEN6_GRDOM_BLT) { | |
287 | gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); | |
288 | engine_mask |= (1 << BCS); | |
289 | } | |
290 | if (data & GEN6_GRDOM_VECS) { | |
291 | gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); | |
292 | engine_mask |= (1 << VECS); | |
293 | } | |
294 | if (data & GEN8_GRDOM_MEDIA2) { | |
295 | gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); | |
296 | if (HAS_BSD2(vgpu->gvt->dev_priv)) | |
297 | engine_mask |= (1 << VCS2); | |
298 | } | |
e39c5add | 299 | } |
c34eaa8d CD |
300 | |
301 | intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); | |
302 | ||
303 | return 0; | |
e39c5add ZW |
304 | } |
305 | ||
04d348ae ZW |
306 | static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, |
307 | void *p_data, unsigned int bytes) | |
308 | { | |
309 | return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); | |
310 | } | |
311 | ||
312 | static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
313 | void *p_data, unsigned int bytes) | |
314 | { | |
315 | return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); | |
316 | } | |
317 | ||
318 | static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, | |
319 | unsigned int offset, void *p_data, unsigned int bytes) | |
320 | { | |
321 | write_vreg(vgpu, offset, p_data, bytes); | |
322 | ||
323 | if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { | |
324 | vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; | |
325 | vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; | |
326 | vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; | |
327 | vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; | |
328 | ||
329 | } else | |
330 | vgpu_vreg(vgpu, PCH_PP_STATUS) &= | |
331 | ~(PP_ON | PP_SEQUENCE_POWER_DOWN | |
332 | | PP_CYCLE_DELAY_ACTIVE); | |
333 | return 0; | |
334 | } | |
335 | ||
336 | static int transconf_mmio_write(struct intel_vgpu *vgpu, | |
337 | unsigned int offset, void *p_data, unsigned int bytes) | |
338 | { | |
339 | write_vreg(vgpu, offset, p_data, bytes); | |
340 | ||
341 | if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) | |
342 | vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; | |
343 | else | |
344 | vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; | |
345 | return 0; | |
346 | } | |
347 | ||
348 | static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
349 | void *p_data, unsigned int bytes) | |
350 | { | |
351 | write_vreg(vgpu, offset, p_data, bytes); | |
352 | ||
353 | if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) | |
354 | vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; | |
355 | else | |
356 | vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; | |
357 | ||
358 | if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) | |
359 | vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; | |
360 | else | |
361 | vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, | |
367 | void *p_data, unsigned int bytes) | |
368 | { | |
369 | *(u32 *)p_data = (1 << 17); | |
370 | return 0; | |
371 | } | |
372 | ||
373 | static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset, | |
374 | void *p_data, unsigned int bytes) | |
375 | { | |
376 | *(u32 *)p_data = 3; | |
377 | return 0; | |
378 | } | |
379 | ||
380 | static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset, | |
381 | void *p_data, unsigned int bytes) | |
382 | { | |
383 | *(u32 *)p_data = (0x2f << 16); | |
384 | return 0; | |
385 | } | |
386 | ||
387 | static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
388 | void *p_data, unsigned int bytes) | |
389 | { | |
390 | u32 data; | |
391 | ||
392 | write_vreg(vgpu, offset, p_data, bytes); | |
393 | data = vgpu_vreg(vgpu, offset); | |
394 | ||
395 | if (data & PIPECONF_ENABLE) | |
396 | vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; | |
397 | else | |
398 | vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; | |
399 | intel_gvt_check_vblank_emulation(vgpu->gvt); | |
400 | return 0; | |
401 | } | |
402 | ||
e6cedfea ZY |
403 | /* ascendingly sorted */ |
404 | static i915_reg_t force_nonpriv_white_list[] = { | |
405 | GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) | |
406 | GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) | |
407 | GEN8_CS_CHICKEN1,//_MMIO(0x2580) | |
408 | _MMIO(0x2690), | |
409 | _MMIO(0x2694), | |
410 | _MMIO(0x2698), | |
411 | _MMIO(0x4de0), | |
412 | _MMIO(0x4de4), | |
413 | _MMIO(0x4dfc), | |
414 | GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) | |
415 | _MMIO(0x7014), | |
416 | HDC_CHICKEN0,//_MMIO(0x7300) | |
417 | GEN8_HDC_CHICKEN1,//_MMIO(0x7304) | |
418 | _MMIO(0x7700), | |
419 | _MMIO(0x7704), | |
420 | _MMIO(0x7708), | |
421 | _MMIO(0x770c), | |
422 | _MMIO(0xb110), | |
423 | GEN8_L3SQCREG4,//_MMIO(0xb118) | |
424 | _MMIO(0xe100), | |
425 | _MMIO(0xe18c), | |
426 | _MMIO(0xe48c), | |
427 | _MMIO(0xe5f4), | |
428 | }; | |
429 | ||
430 | /* a simple bsearch */ | |
431 | static inline bool in_whitelist(unsigned int reg) | |
432 | { | |
433 | int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); | |
434 | i915_reg_t *array = force_nonpriv_white_list; | |
435 | ||
436 | while (left < right) { | |
437 | int mid = (left + right)/2; | |
438 | ||
439 | if (reg > array[mid].reg) | |
440 | left = mid + 1; | |
441 | else if (reg < array[mid].reg) | |
442 | right = mid; | |
443 | else | |
444 | return true; | |
445 | } | |
446 | return false; | |
447 | } | |
448 | ||
449 | static int force_nonpriv_write(struct intel_vgpu *vgpu, | |
450 | unsigned int offset, void *p_data, unsigned int bytes) | |
451 | { | |
452 | u32 reg_nonpriv = *(u32 *)p_data; | |
453 | int ret = -EINVAL; | |
454 | ||
455 | if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) { | |
456 | gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", | |
457 | vgpu->id, offset, bytes); | |
458 | return ret; | |
459 | } | |
460 | ||
461 | if (in_whitelist(reg_nonpriv)) { | |
462 | ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, | |
463 | bytes); | |
464 | } else { | |
465 | gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n", | |
466 | vgpu->id, reg_nonpriv); | |
467 | } | |
468 | return ret; | |
469 | } | |
470 | ||
04d348ae ZW |
471 | static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
472 | void *p_data, unsigned int bytes) | |
473 | { | |
474 | write_vreg(vgpu, offset, p_data, bytes); | |
475 | ||
476 | if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { | |
477 | vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; | |
478 | } else { | |
479 | vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; | |
480 | if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) | |
481 | vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) | |
482 | &= ~DP_TP_STATUS_AUTOTRAIN_DONE; | |
483 | } | |
484 | return 0; | |
485 | } | |
486 | ||
487 | static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, | |
488 | unsigned int offset, void *p_data, unsigned int bytes) | |
489 | { | |
490 | vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; | |
491 | return 0; | |
492 | } | |
493 | ||
494 | #define FDI_LINK_TRAIN_PATTERN1 0 | |
495 | #define FDI_LINK_TRAIN_PATTERN2 1 | |
496 | ||
497 | static int fdi_auto_training_started(struct intel_vgpu *vgpu) | |
498 | { | |
499 | u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); | |
500 | u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); | |
501 | u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); | |
502 | ||
503 | if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && | |
504 | (rx_ctl & FDI_RX_ENABLE) && | |
505 | (rx_ctl & FDI_AUTO_TRAINING) && | |
506 | (tx_ctl & DP_TP_CTL_ENABLE) && | |
507 | (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) | |
508 | return 1; | |
509 | else | |
510 | return 0; | |
511 | } | |
512 | ||
513 | static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, | |
514 | enum pipe pipe, unsigned int train_pattern) | |
515 | { | |
516 | i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; | |
517 | unsigned int fdi_rx_check_bits, fdi_tx_check_bits; | |
518 | unsigned int fdi_rx_train_bits, fdi_tx_train_bits; | |
519 | unsigned int fdi_iir_check_bits; | |
520 | ||
521 | fdi_rx_imr = FDI_RX_IMR(pipe); | |
522 | fdi_tx_ctl = FDI_TX_CTL(pipe); | |
523 | fdi_rx_ctl = FDI_RX_CTL(pipe); | |
524 | ||
525 | if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { | |
526 | fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; | |
527 | fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; | |
528 | fdi_iir_check_bits = FDI_RX_BIT_LOCK; | |
529 | } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { | |
530 | fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; | |
531 | fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; | |
532 | fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; | |
533 | } else { | |
695fbc08 | 534 | gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); |
04d348ae ZW |
535 | return -EINVAL; |
536 | } | |
537 | ||
538 | fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; | |
539 | fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; | |
540 | ||
541 | /* If imr bit has been masked */ | |
542 | if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) | |
543 | return 0; | |
544 | ||
545 | if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) | |
546 | == fdi_tx_check_bits) | |
547 | && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) | |
548 | == fdi_rx_check_bits)) | |
549 | return 1; | |
550 | else | |
551 | return 0; | |
552 | } | |
553 | ||
554 | #define INVALID_INDEX (~0U) | |
555 | ||
556 | static unsigned int calc_index(unsigned int offset, unsigned int start, | |
557 | unsigned int next, unsigned int end, i915_reg_t i915_end) | |
558 | { | |
559 | unsigned int range = next - start; | |
560 | ||
561 | if (!end) | |
562 | end = i915_mmio_reg_offset(i915_end); | |
563 | if (offset < start || offset > end) | |
564 | return INVALID_INDEX; | |
565 | offset -= start; | |
566 | return offset / range; | |
567 | } | |
568 | ||
569 | #define FDI_RX_CTL_TO_PIPE(offset) \ | |
570 | calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) | |
571 | ||
572 | #define FDI_TX_CTL_TO_PIPE(offset) \ | |
573 | calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) | |
574 | ||
575 | #define FDI_RX_IMR_TO_PIPE(offset) \ | |
576 | calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) | |
577 | ||
578 | static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, | |
579 | unsigned int offset, void *p_data, unsigned int bytes) | |
580 | { | |
581 | i915_reg_t fdi_rx_iir; | |
582 | unsigned int index; | |
583 | int ret; | |
584 | ||
585 | if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) | |
586 | index = FDI_RX_CTL_TO_PIPE(offset); | |
587 | else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) | |
588 | index = FDI_TX_CTL_TO_PIPE(offset); | |
589 | else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) | |
590 | index = FDI_RX_IMR_TO_PIPE(offset); | |
591 | else { | |
695fbc08 | 592 | gvt_vgpu_err("Unsupport registers %x\n", offset); |
04d348ae ZW |
593 | return -EINVAL; |
594 | } | |
595 | ||
596 | write_vreg(vgpu, offset, p_data, bytes); | |
597 | ||
598 | fdi_rx_iir = FDI_RX_IIR(index); | |
599 | ||
600 | ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); | |
601 | if (ret < 0) | |
602 | return ret; | |
603 | if (ret) | |
604 | vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; | |
605 | ||
606 | ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); | |
607 | if (ret < 0) | |
608 | return ret; | |
609 | if (ret) | |
610 | vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; | |
611 | ||
612 | if (offset == _FDI_RXA_CTL) | |
613 | if (fdi_auto_training_started(vgpu)) | |
614 | vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= | |
615 | DP_TP_STATUS_AUTOTRAIN_DONE; | |
616 | return 0; | |
617 | } | |
618 | ||
619 | #define DP_TP_CTL_TO_PORT(offset) \ | |
620 | calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) | |
621 | ||
622 | static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
623 | void *p_data, unsigned int bytes) | |
624 | { | |
625 | i915_reg_t status_reg; | |
626 | unsigned int index; | |
627 | u32 data; | |
628 | ||
629 | write_vreg(vgpu, offset, p_data, bytes); | |
630 | ||
631 | index = DP_TP_CTL_TO_PORT(offset); | |
632 | data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; | |
633 | if (data == 0x2) { | |
634 | status_reg = DP_TP_STATUS(index); | |
635 | vgpu_vreg(vgpu, status_reg) |= (1 << 25); | |
636 | } | |
637 | return 0; | |
638 | } | |
639 | ||
640 | static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, | |
641 | unsigned int offset, void *p_data, unsigned int bytes) | |
642 | { | |
643 | u32 reg_val; | |
644 | u32 sticky_mask; | |
645 | ||
646 | reg_val = *((u32 *)p_data); | |
647 | sticky_mask = GENMASK(27, 26) | (1 << 24); | |
648 | ||
649 | vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | | |
650 | (vgpu_vreg(vgpu, offset) & sticky_mask); | |
651 | vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); | |
652 | return 0; | |
653 | } | |
654 | ||
655 | static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, | |
656 | unsigned int offset, void *p_data, unsigned int bytes) | |
657 | { | |
658 | u32 data; | |
659 | ||
660 | write_vreg(vgpu, offset, p_data, bytes); | |
661 | data = vgpu_vreg(vgpu, offset); | |
662 | ||
663 | if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) | |
664 | vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
665 | return 0; | |
666 | } | |
667 | ||
668 | static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, | |
669 | unsigned int offset, void *p_data, unsigned int bytes) | |
670 | { | |
671 | u32 data; | |
672 | ||
673 | write_vreg(vgpu, offset, p_data, bytes); | |
674 | data = vgpu_vreg(vgpu, offset); | |
675 | ||
676 | if (data & FDI_MPHY_IOSFSB_RESET_CTL) | |
677 | vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; | |
678 | else | |
679 | vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; | |
680 | return 0; | |
681 | } | |
682 | ||
683 | #define DSPSURF_TO_PIPE(offset) \ | |
684 | calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) | |
685 | ||
686 | static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
687 | void *p_data, unsigned int bytes) | |
688 | { | |
689 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
690 | unsigned int index = DSPSURF_TO_PIPE(offset); | |
691 | i915_reg_t surflive_reg = DSPSURFLIVE(index); | |
692 | int flip_event[] = { | |
693 | [PIPE_A] = PRIMARY_A_FLIP_DONE, | |
694 | [PIPE_B] = PRIMARY_B_FLIP_DONE, | |
695 | [PIPE_C] = PRIMARY_C_FLIP_DONE, | |
696 | }; | |
697 | ||
698 | write_vreg(vgpu, offset, p_data, bytes); | |
699 | vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); | |
700 | ||
701 | set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); | |
702 | return 0; | |
703 | } | |
704 | ||
705 | #define SPRSURF_TO_PIPE(offset) \ | |
706 | calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) | |
707 | ||
708 | static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
709 | void *p_data, unsigned int bytes) | |
710 | { | |
711 | unsigned int index = SPRSURF_TO_PIPE(offset); | |
712 | i915_reg_t surflive_reg = SPRSURFLIVE(index); | |
713 | int flip_event[] = { | |
714 | [PIPE_A] = SPRITE_A_FLIP_DONE, | |
715 | [PIPE_B] = SPRITE_B_FLIP_DONE, | |
716 | [PIPE_C] = SPRITE_C_FLIP_DONE, | |
717 | }; | |
718 | ||
719 | write_vreg(vgpu, offset, p_data, bytes); | |
720 | vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); | |
721 | ||
722 | set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); | |
723 | return 0; | |
724 | } | |
725 | ||
726 | static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, | |
727 | unsigned int reg) | |
728 | { | |
729 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
730 | enum intel_gvt_event_type event; | |
731 | ||
732 | if (reg == _DPA_AUX_CH_CTL) | |
733 | event = AUX_CHANNEL_A; | |
734 | else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) | |
735 | event = AUX_CHANNEL_B; | |
736 | else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) | |
737 | event = AUX_CHANNEL_C; | |
738 | else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) | |
739 | event = AUX_CHANNEL_D; | |
740 | else { | |
741 | WARN_ON(true); | |
742 | return -EINVAL; | |
743 | } | |
744 | ||
745 | intel_vgpu_trigger_virtual_event(vgpu, event); | |
746 | return 0; | |
747 | } | |
748 | ||
749 | static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, | |
750 | unsigned int reg, int len, bool data_valid) | |
751 | { | |
752 | /* mark transaction done */ | |
753 | value |= DP_AUX_CH_CTL_DONE; | |
754 | value &= ~DP_AUX_CH_CTL_SEND_BUSY; | |
755 | value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; | |
756 | ||
757 | if (data_valid) | |
758 | value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; | |
759 | else | |
760 | value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; | |
761 | ||
762 | /* message size */ | |
763 | value &= ~(0xf << 20); | |
764 | value |= (len << 20); | |
765 | vgpu_vreg(vgpu, reg) = value; | |
766 | ||
767 | if (value & DP_AUX_CH_CTL_INTERRUPT) | |
768 | return trigger_aux_channel_interrupt(vgpu, reg); | |
769 | return 0; | |
770 | } | |
771 | ||
772 | static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, | |
773 | uint8_t t) | |
774 | { | |
775 | if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { | |
776 | /* training pattern 1 for CR */ | |
777 | /* set LANE0_CR_DONE, LANE1_CR_DONE */ | |
778 | dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; | |
779 | /* set LANE2_CR_DONE, LANE3_CR_DONE */ | |
780 | dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; | |
781 | } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == | |
782 | DPCD_TRAINING_PATTERN_2) { | |
783 | /* training pattern 2 for EQ */ | |
784 | /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ | |
785 | dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; | |
786 | dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; | |
787 | /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ | |
788 | dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; | |
789 | dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; | |
790 | /* set INTERLANE_ALIGN_DONE */ | |
791 | dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= | |
792 | DPCD_INTERLANE_ALIGN_DONE; | |
793 | } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == | |
794 | DPCD_LINK_TRAINING_DISABLED) { | |
795 | /* finish link training */ | |
796 | /* set sink status as synchronized */ | |
797 | dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; | |
798 | } | |
799 | } | |
800 | ||
801 | #define _REG_HSW_DP_AUX_CH_CTL(dp) \ | |
802 | ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) | |
803 | ||
804 | #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) | |
805 | ||
806 | #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) | |
807 | ||
808 | #define dpy_is_valid_port(port) \ | |
809 | (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) | |
810 | ||
811 | static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, | |
812 | unsigned int offset, void *p_data, unsigned int bytes) | |
813 | { | |
814 | struct intel_vgpu_display *display = &vgpu->display; | |
815 | int msg, addr, ctrl, op, len; | |
816 | int port_index = OFFSET_TO_DP_AUX_PORT(offset); | |
817 | struct intel_vgpu_dpcd_data *dpcd = NULL; | |
818 | struct intel_vgpu_port *port = NULL; | |
819 | u32 data; | |
820 | ||
821 | if (!dpy_is_valid_port(port_index)) { | |
695fbc08 | 822 | gvt_vgpu_err("Unsupported DP port access!\n"); |
04d348ae ZW |
823 | return 0; |
824 | } | |
825 | ||
826 | write_vreg(vgpu, offset, p_data, bytes); | |
827 | data = vgpu_vreg(vgpu, offset); | |
828 | ||
e3476c00 XH |
829 | if ((IS_SKYLAKE(vgpu->gvt->dev_priv) |
830 | || IS_KABYLAKE(vgpu->gvt->dev_priv)) | |
831 | && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { | |
04d348ae ZW |
832 | /* SKL DPB/C/D aux ctl register changed */ |
833 | return 0; | |
834 | } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && | |
835 | offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { | |
836 | /* write to the data registers */ | |
837 | return 0; | |
838 | } | |
839 | ||
840 | if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { | |
841 | /* just want to clear the sticky bits */ | |
842 | vgpu_vreg(vgpu, offset) = 0; | |
843 | return 0; | |
844 | } | |
845 | ||
846 | port = &display->ports[port_index]; | |
847 | dpcd = port->dpcd; | |
848 | ||
849 | /* read out message from DATA1 register */ | |
850 | msg = vgpu_vreg(vgpu, offset + 4); | |
851 | addr = (msg >> 8) & 0xffff; | |
852 | ctrl = (msg >> 24) & 0xff; | |
853 | len = msg & 0xff; | |
854 | op = ctrl >> 4; | |
855 | ||
856 | if (op == GVT_AUX_NATIVE_WRITE) { | |
857 | int t; | |
858 | uint8_t buf[16]; | |
859 | ||
860 | if ((addr + len + 1) >= DPCD_SIZE) { | |
861 | /* | |
862 | * Write request exceeds what we supported, | |
863 | * DCPD spec: When a Source Device is writing a DPCD | |
864 | * address not supported by the Sink Device, the Sink | |
865 | * Device shall reply with AUX NACK and “M” equal to | |
866 | * zero. | |
867 | */ | |
868 | ||
869 | /* NAK the write */ | |
870 | vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; | |
871 | dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); | |
872 | return 0; | |
873 | } | |
874 | ||
875 | /* | |
876 | * Write request format: (command + address) occupies | |
877 | * 3 bytes, followed by (len + 1) bytes of data. | |
878 | */ | |
879 | if (WARN_ON((len + 4) > AUX_BURST_SIZE)) | |
880 | return -EINVAL; | |
881 | ||
882 | /* unpack data from vreg to buf */ | |
883 | for (t = 0; t < 4; t++) { | |
884 | u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); | |
885 | ||
886 | buf[t * 4] = (r >> 24) & 0xff; | |
887 | buf[t * 4 + 1] = (r >> 16) & 0xff; | |
888 | buf[t * 4 + 2] = (r >> 8) & 0xff; | |
889 | buf[t * 4 + 3] = r & 0xff; | |
890 | } | |
891 | ||
892 | /* write to virtual DPCD */ | |
893 | if (dpcd && dpcd->data_valid) { | |
894 | for (t = 0; t <= len; t++) { | |
895 | int p = addr + t; | |
896 | ||
897 | dpcd->data[p] = buf[t]; | |
898 | /* check for link training */ | |
899 | if (p == DPCD_TRAINING_PATTERN_SET) | |
900 | dp_aux_ch_ctl_link_training(dpcd, | |
901 | buf[t]); | |
902 | } | |
903 | } | |
904 | ||
905 | /* ACK the write */ | |
906 | vgpu_vreg(vgpu, offset + 4) = 0; | |
907 | dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, | |
908 | dpcd && dpcd->data_valid); | |
909 | return 0; | |
910 | } | |
911 | ||
912 | if (op == GVT_AUX_NATIVE_READ) { | |
913 | int idx, i, ret = 0; | |
914 | ||
915 | if ((addr + len + 1) >= DPCD_SIZE) { | |
916 | /* | |
917 | * read request exceeds what we supported | |
918 | * DPCD spec: A Sink Device receiving a Native AUX CH | |
919 | * read request for an unsupported DPCD address must | |
920 | * reply with an AUX ACK and read data set equal to | |
921 | * zero instead of replying with AUX NACK. | |
922 | */ | |
923 | ||
924 | /* ACK the READ*/ | |
925 | vgpu_vreg(vgpu, offset + 4) = 0; | |
926 | vgpu_vreg(vgpu, offset + 8) = 0; | |
927 | vgpu_vreg(vgpu, offset + 12) = 0; | |
928 | vgpu_vreg(vgpu, offset + 16) = 0; | |
929 | vgpu_vreg(vgpu, offset + 20) = 0; | |
930 | ||
931 | dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, | |
932 | true); | |
933 | return 0; | |
934 | } | |
935 | ||
936 | for (idx = 1; idx <= 5; idx++) { | |
937 | /* clear the data registers */ | |
938 | vgpu_vreg(vgpu, offset + 4 * idx) = 0; | |
939 | } | |
940 | ||
941 | /* | |
942 | * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. | |
943 | */ | |
944 | if (WARN_ON((len + 2) > AUX_BURST_SIZE)) | |
945 | return -EINVAL; | |
946 | ||
947 | /* read from virtual DPCD to vreg */ | |
948 | /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ | |
949 | if (dpcd && dpcd->data_valid) { | |
950 | for (i = 1; i <= (len + 1); i++) { | |
951 | int t; | |
952 | ||
953 | t = dpcd->data[addr + i - 1]; | |
954 | t <<= (24 - 8 * (i % 4)); | |
955 | ret |= t; | |
956 | ||
957 | if ((i % 4 == 3) || (i == (len + 1))) { | |
958 | vgpu_vreg(vgpu, offset + | |
959 | (i / 4 + 1) * 4) = ret; | |
960 | ret = 0; | |
961 | } | |
962 | } | |
963 | } | |
964 | dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, | |
965 | dpcd && dpcd->data_valid); | |
966 | return 0; | |
967 | } | |
968 | ||
969 | /* i2c transaction starts */ | |
970 | intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); | |
971 | ||
972 | if (data & DP_AUX_CH_CTL_INTERRUPT) | |
973 | trigger_aux_channel_interrupt(vgpu, offset); | |
974 | return 0; | |
975 | } | |
976 | ||
975629c3 PZ |
977 | static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, |
978 | void *p_data, unsigned int bytes) | |
979 | { | |
980 | *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); | |
981 | write_vreg(vgpu, offset, p_data, bytes); | |
982 | return 0; | |
983 | } | |
984 | ||
04d348ae ZW |
985 | static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
986 | void *p_data, unsigned int bytes) | |
987 | { | |
988 | bool vga_disable; | |
989 | ||
990 | write_vreg(vgpu, offset, p_data, bytes); | |
991 | vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; | |
992 | ||
993 | gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, | |
994 | vga_disable ? "Disable" : "Enable"); | |
995 | return 0; | |
996 | } | |
997 | ||
998 | static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, | |
999 | unsigned int sbi_offset) | |
1000 | { | |
1001 | struct intel_vgpu_display *display = &vgpu->display; | |
1002 | int num = display->sbi.number; | |
1003 | int i; | |
1004 | ||
1005 | for (i = 0; i < num; ++i) | |
1006 | if (display->sbi.registers[i].offset == sbi_offset) | |
1007 | break; | |
1008 | ||
1009 | if (i == num) | |
1010 | return 0; | |
1011 | ||
1012 | return display->sbi.registers[i].value; | |
1013 | } | |
1014 | ||
1015 | static void write_virtual_sbi_register(struct intel_vgpu *vgpu, | |
1016 | unsigned int offset, u32 value) | |
1017 | { | |
1018 | struct intel_vgpu_display *display = &vgpu->display; | |
1019 | int num = display->sbi.number; | |
1020 | int i; | |
1021 | ||
1022 | for (i = 0; i < num; ++i) { | |
1023 | if (display->sbi.registers[i].offset == offset) | |
1024 | break; | |
1025 | } | |
1026 | ||
1027 | if (i == num) { | |
1028 | if (num == SBI_REG_MAX) { | |
695fbc08 | 1029 | gvt_vgpu_err("SBI caching meets maximum limits\n"); |
04d348ae ZW |
1030 | return; |
1031 | } | |
1032 | display->sbi.number++; | |
1033 | } | |
1034 | ||
1035 | display->sbi.registers[i].offset = offset; | |
1036 | display->sbi.registers[i].value = value; | |
1037 | } | |
1038 | ||
1039 | static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, | |
1040 | void *p_data, unsigned int bytes) | |
1041 | { | |
1042 | if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> | |
1043 | SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { | |
1044 | unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & | |
1045 | SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; | |
1046 | vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, | |
1047 | sbi_offset); | |
1048 | } | |
1049 | read_vreg(vgpu, offset, p_data, bytes); | |
1050 | return 0; | |
1051 | } | |
1052 | ||
3e70c5d6 | 1053 | static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
04d348ae ZW |
1054 | void *p_data, unsigned int bytes) |
1055 | { | |
1056 | u32 data; | |
1057 | ||
1058 | write_vreg(vgpu, offset, p_data, bytes); | |
1059 | data = vgpu_vreg(vgpu, offset); | |
1060 | ||
1061 | data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); | |
1062 | data |= SBI_READY; | |
1063 | ||
1064 | data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); | |
1065 | data |= SBI_RESPONSE_SUCCESS; | |
1066 | ||
1067 | vgpu_vreg(vgpu, offset) = data; | |
1068 | ||
1069 | if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> | |
1070 | SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { | |
1071 | unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & | |
1072 | SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; | |
1073 | ||
1074 | write_virtual_sbi_register(vgpu, sbi_offset, | |
1075 | vgpu_vreg(vgpu, SBI_DATA)); | |
1076 | } | |
1077 | return 0; | |
1078 | } | |
1079 | ||
e39c5add ZW |
1080 | #define _vgtif_reg(x) \ |
1081 | (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) | |
1082 | ||
1083 | static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, | |
1084 | void *p_data, unsigned int bytes) | |
1085 | { | |
1086 | bool invalid_read = false; | |
1087 | ||
1088 | read_vreg(vgpu, offset, p_data, bytes); | |
1089 | ||
1090 | switch (offset) { | |
1091 | case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): | |
1092 | if (offset + bytes > _vgtif_reg(vgt_id) + 4) | |
1093 | invalid_read = true; | |
1094 | break; | |
1095 | case _vgtif_reg(avail_rs.mappable_gmadr.base) ... | |
1096 | _vgtif_reg(avail_rs.fence_num): | |
1097 | if (offset + bytes > | |
1098 | _vgtif_reg(avail_rs.fence_num) + 4) | |
1099 | invalid_read = true; | |
1100 | break; | |
1101 | case 0x78010: /* vgt_caps */ | |
1102 | case 0x7881c: | |
1103 | break; | |
1104 | default: | |
1105 | invalid_read = true; | |
1106 | break; | |
1107 | } | |
1108 | if (invalid_read) | |
695fbc08 | 1109 | gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", |
e39c5add | 1110 | offset, bytes, *(u32 *)p_data); |
fd64be63 | 1111 | vgpu->pv_notified = true; |
e39c5add ZW |
1112 | return 0; |
1113 | } | |
1114 | ||
1115 | static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) | |
1116 | { | |
1117 | int ret = 0; | |
1118 | ||
1119 | switch (notification) { | |
1120 | case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: | |
1121 | ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); | |
1122 | break; | |
1123 | case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: | |
1124 | ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); | |
1125 | break; | |
1126 | case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: | |
1127 | ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); | |
1128 | break; | |
1129 | case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: | |
1130 | ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); | |
1131 | break; | |
1132 | case VGT_G2V_EXECLIST_CONTEXT_CREATE: | |
1133 | case VGT_G2V_EXECLIST_CONTEXT_DESTROY: | |
1134 | case 1: /* Remove this in guest driver. */ | |
1135 | break; | |
1136 | default: | |
695fbc08 | 1137 | gvt_vgpu_err("Invalid PV notification %d\n", notification); |
e39c5add ZW |
1138 | } |
1139 | return ret; | |
1140 | } | |
1141 | ||
04d348ae ZW |
1142 | static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) |
1143 | { | |
1144 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
1145 | struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; | |
1146 | char *env[3] = {NULL, NULL, NULL}; | |
1147 | char vmid_str[20]; | |
1148 | char display_ready_str[20]; | |
1149 | ||
d8e9b2b9 | 1150 | snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); |
04d348ae ZW |
1151 | env[0] = display_ready_str; |
1152 | ||
1153 | snprintf(vmid_str, 20, "VMID=%d", vgpu->id); | |
1154 | env[1] = vmid_str; | |
1155 | ||
1156 | return kobject_uevent_env(kobj, KOBJ_ADD, env); | |
1157 | } | |
1158 | ||
e39c5add ZW |
1159 | static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
1160 | void *p_data, unsigned int bytes) | |
1161 | { | |
1162 | u32 data; | |
1163 | int ret; | |
1164 | ||
1165 | write_vreg(vgpu, offset, p_data, bytes); | |
1166 | data = vgpu_vreg(vgpu, offset); | |
1167 | ||
1168 | switch (offset) { | |
1169 | case _vgtif_reg(display_ready): | |
04d348ae ZW |
1170 | send_display_ready_uevent(vgpu, data ? 1 : 0); |
1171 | break; | |
e39c5add ZW |
1172 | case _vgtif_reg(g2v_notify): |
1173 | ret = handle_g2v_notification(vgpu, data); | |
1174 | break; | |
1175 | /* add xhot and yhot to handled list to avoid error log */ | |
1176 | case 0x78830: | |
1177 | case 0x78834: | |
1178 | case _vgtif_reg(pdp[0].lo): | |
1179 | case _vgtif_reg(pdp[0].hi): | |
1180 | case _vgtif_reg(pdp[1].lo): | |
1181 | case _vgtif_reg(pdp[1].hi): | |
1182 | case _vgtif_reg(pdp[2].lo): | |
1183 | case _vgtif_reg(pdp[2].hi): | |
1184 | case _vgtif_reg(pdp[3].lo): | |
1185 | case _vgtif_reg(pdp[3].hi): | |
1186 | case _vgtif_reg(execlist_context_descriptor_lo): | |
1187 | case _vgtif_reg(execlist_context_descriptor_hi): | |
1188 | break; | |
a33fc7a0 MH |
1189 | case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): |
1190 | enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); | |
1191 | break; | |
e39c5add | 1192 | default: |
695fbc08 | 1193 | gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", |
e39c5add ZW |
1194 | offset, bytes, data); |
1195 | break; | |
1196 | } | |
1197 | return 0; | |
1198 | } | |
1199 | ||
04d348ae ZW |
1200 | static int pf_write(struct intel_vgpu *vgpu, |
1201 | unsigned int offset, void *p_data, unsigned int bytes) | |
1202 | { | |
1203 | u32 val = *(u32 *)p_data; | |
1204 | ||
1205 | if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || | |
1206 | offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || | |
1207 | offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { | |
1208 | WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", | |
1209 | vgpu->id); | |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); | |
1214 | } | |
1215 | ||
1216 | static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, | |
1217 | unsigned int offset, void *p_data, unsigned int bytes) | |
1218 | { | |
1219 | write_vreg(vgpu, offset, p_data, bytes); | |
1220 | ||
1221 | if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) | |
1222 | vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; | |
1223 | else | |
1224 | vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; | |
1225 | return 0; | |
1226 | } | |
1227 | ||
e39c5add ZW |
1228 | static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, |
1229 | unsigned int offset, void *p_data, unsigned int bytes) | |
1230 | { | |
1231 | write_vreg(vgpu, offset, p_data, bytes); | |
1232 | ||
1233 | if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) | |
1234 | vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; | |
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, | |
1239 | void *p_data, unsigned int bytes) | |
1240 | { | |
5f399f11 PG |
1241 | u32 mode; |
1242 | ||
1243 | write_vreg(vgpu, offset, p_data, bytes); | |
1244 | mode = vgpu_vreg(vgpu, offset); | |
e39c5add ZW |
1245 | |
1246 | if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { | |
7f48d0b4 | 1247 | WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", |
e39c5add ZW |
1248 | vgpu->id); |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, | |
1256 | void *p_data, unsigned int bytes) | |
1257 | { | |
1258 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
1259 | u32 trtte = *(u32 *)p_data; | |
1260 | ||
1261 | if ((trtte & 1) && (trtte & (1 << 1)) == 0) { | |
1262 | WARN(1, "VM(%d): Use physical address for TRTT!\n", | |
1263 | vgpu->id); | |
1264 | return -EINVAL; | |
1265 | } | |
1266 | write_vreg(vgpu, offset, p_data, bytes); | |
1267 | /* TRTTE is not per-context */ | |
1268 | I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, | |
1274 | void *p_data, unsigned int bytes) | |
1275 | { | |
1276 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
1277 | u32 val = *(u32 *)p_data; | |
1278 | ||
1279 | if (val & 1) { | |
1280 | /* unblock hw logic */ | |
1281 | I915_WRITE(_MMIO(offset), val); | |
1282 | } | |
1283 | write_vreg(vgpu, offset, p_data, bytes); | |
1284 | return 0; | |
1285 | } | |
1286 | ||
04d348ae ZW |
1287 | static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, |
1288 | void *p_data, unsigned int bytes) | |
1289 | { | |
1290 | u32 v = 0; | |
1291 | ||
1292 | if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) | |
1293 | v |= (1 << 0); | |
1294 | ||
1295 | if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) | |
1296 | v |= (1 << 8); | |
1297 | ||
1298 | if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) | |
1299 | v |= (1 << 16); | |
1300 | ||
1301 | if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) | |
1302 | v |= (1 << 24); | |
1303 | ||
1304 | vgpu_vreg(vgpu, offset) = v; | |
1305 | ||
1306 | return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); | |
1307 | } | |
1308 | ||
1309 | static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, | |
1310 | void *p_data, unsigned int bytes) | |
1311 | { | |
1312 | u32 value = *(u32 *)p_data; | |
1313 | u32 cmd = value & 0xff; | |
1314 | u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); | |
1315 | ||
1316 | switch (cmd) { | |
8bcd7c18 | 1317 | case GEN9_PCODE_READ_MEM_LATENCY: |
e3476c00 XH |
1318 | if (IS_SKYLAKE(vgpu->gvt->dev_priv) |
1319 | || IS_KABYLAKE(vgpu->gvt->dev_priv)) { | |
8bcd7c18 WL |
1320 | /** |
1321 | * "Read memory latency" command on gen9. | |
1322 | * Below memory latency values are read | |
1323 | * from skylake platform. | |
1324 | */ | |
1325 | if (!*data0) | |
1326 | *data0 = 0x1e1a1100; | |
1327 | else | |
1328 | *data0 = 0x61514b3d; | |
1329 | } | |
04d348ae | 1330 | break; |
d8a355be | 1331 | case SKL_PCODE_CDCLK_CONTROL: |
e3476c00 XH |
1332 | if (IS_SKYLAKE(vgpu->gvt->dev_priv) |
1333 | || IS_KABYLAKE(vgpu->gvt->dev_priv)) | |
8bcd7c18 | 1334 | *data0 = SKL_CDCLK_READY_FOR_CHANGE; |
d8a355be | 1335 | break; |
8bcd7c18 | 1336 | case GEN6_PCODE_READ_RC6VIDS: |
04d348ae ZW |
1337 | *data0 |= 0x1; |
1338 | break; | |
1339 | } | |
1340 | ||
1341 | gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", | |
1342 | vgpu->id, value, *data0); | |
d8a355be WL |
1343 | /** |
1344 | * PCODE_READY clear means ready for pcode read/write, | |
1345 | * PCODE_ERROR_MASK clear means no error happened. In GVT-g we | |
1346 | * always emulate as pcode read/write success and ready for access | |
1347 | * anytime, since we don't touch real physical registers here. | |
1348 | */ | |
1349 | value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); | |
04d348ae ZW |
1350 | return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); |
1351 | } | |
1352 | ||
1353 | static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, | |
1354 | unsigned int offset, void *p_data, unsigned int bytes) | |
1355 | { | |
1356 | u32 v = *(u32 *)p_data; | |
1357 | ||
1358 | v &= (1 << 31) | (1 << 29) | (1 << 9) | | |
1359 | (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); | |
1360 | v |= (v >> 1); | |
1361 | ||
1362 | return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); | |
1363 | } | |
1364 | ||
1365 | static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, | |
1366 | void *p_data, unsigned int bytes) | |
1367 | { | |
1368 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
1369 | i915_reg_t reg = {.reg = offset}; | |
1370 | ||
1371 | switch (offset) { | |
1372 | case 0x4ddc: | |
1373 | vgpu_vreg(vgpu, offset) = 0x8000003c; | |
d4362225 | 1374 | /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ |
955c1dd1 | 1375 | I915_WRITE(reg, vgpu_vreg(vgpu, offset)); |
04d348ae ZW |
1376 | break; |
1377 | case 0x42080: | |
1378 | vgpu_vreg(vgpu, offset) = 0x8000; | |
d4362225 | 1379 | /* WaCompressedResourceDisplayNewHashMode:skl */ |
955c1dd1 | 1380 | I915_WRITE(reg, vgpu_vreg(vgpu, offset)); |
04d348ae ZW |
1381 | break; |
1382 | default: | |
1383 | return -EINVAL; | |
1384 | } | |
1385 | ||
04d348ae ZW |
1386 | return 0; |
1387 | } | |
1388 | ||
1389 | static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, | |
1390 | void *p_data, unsigned int bytes) | |
1391 | { | |
1392 | u32 v = *(u32 *)p_data; | |
1393 | ||
1394 | /* other bits are MBZ. */ | |
1395 | v &= (1 << 31) | (1 << 30); | |
1396 | v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); | |
1397 | ||
1398 | vgpu_vreg(vgpu, offset) = v; | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
1403 | static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu, | |
1404 | unsigned int offset, void *p_data, unsigned int bytes) | |
1405 | { | |
1406 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
1407 | ||
1408 | vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); | |
1409 | return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); | |
1410 | } | |
1411 | ||
28c4c6ca ZW |
1412 | static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
1413 | void *p_data, unsigned int bytes) | |
1414 | { | |
1415 | int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); | |
1416 | struct intel_vgpu_execlist *execlist; | |
1417 | u32 data = *(u32 *)p_data; | |
6fb5082a | 1418 | int ret = 0; |
28c4c6ca | 1419 | |
0fac21e7 | 1420 | if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) |
28c4c6ca ZW |
1421 | return -EINVAL; |
1422 | ||
1423 | execlist = &vgpu->execlist[ring_id]; | |
1424 | ||
1425 | execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data; | |
6fb5082a | 1426 | if (execlist->elsp_dwords.index == 3) { |
f6504cce | 1427 | vgpu->last_ctx_submit_time = ktime_get(); |
28c4c6ca | 1428 | ret = intel_vgpu_submit_execlist(vgpu, ring_id); |
6fb5082a | 1429 | if(ret) |
695fbc08 TZ |
1430 | gvt_vgpu_err("fail submit workload on ring %d\n", |
1431 | ring_id); | |
6fb5082a | 1432 | } |
28c4c6ca ZW |
1433 | |
1434 | ++execlist->elsp_dwords.index; | |
1435 | execlist->elsp_dwords.index &= 0x3; | |
6fb5082a | 1436 | return ret; |
28c4c6ca ZW |
1437 | } |
1438 | ||
4b63960e ZW |
1439 | static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
1440 | void *p_data, unsigned int bytes) | |
1441 | { | |
1442 | u32 data = *(u32 *)p_data; | |
1443 | int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset); | |
1444 | bool enable_execlist; | |
1445 | ||
1446 | write_vreg(vgpu, offset, p_data, bytes); | |
fd64be63 MH |
1447 | |
1448 | /* when PPGTT mode enabled, we will check if guest has called | |
1449 | * pvinfo, if not, we will treat this guest as non-gvtg-aware | |
1450 | * guest, and stop emulating its cfg space, mmio, gtt, etc. | |
1451 | */ | |
1452 | if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || | |
1453 | (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) | |
1454 | && !vgpu->pv_notified) { | |
1455 | enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); | |
1456 | return 0; | |
1457 | } | |
4b63960e ZW |
1458 | if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) |
1459 | || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { | |
1460 | enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); | |
1461 | ||
1462 | gvt_dbg_core("EXECLIST %s on ring %d\n", | |
1463 | (enable_execlist ? "enabling" : "disabling"), | |
1464 | ring_id); | |
1465 | ||
1466 | if (enable_execlist) | |
1467 | intel_vgpu_start_schedule(vgpu); | |
1468 | } | |
1469 | return 0; | |
1470 | } | |
1471 | ||
17865713 ZW |
1472 | static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, |
1473 | unsigned int offset, void *p_data, unsigned int bytes) | |
1474 | { | |
17865713 ZW |
1475 | unsigned int id = 0; |
1476 | ||
f24940e0 | 1477 | write_vreg(vgpu, offset, p_data, bytes); |
4f3f1aed | 1478 | vgpu_vreg(vgpu, offset) = 0; |
f24940e0 | 1479 | |
17865713 ZW |
1480 | switch (offset) { |
1481 | case 0x4260: | |
1482 | id = RCS; | |
1483 | break; | |
1484 | case 0x4264: | |
1485 | id = VCS; | |
1486 | break; | |
1487 | case 0x4268: | |
1488 | id = VCS2; | |
1489 | break; | |
1490 | case 0x426c: | |
1491 | id = BCS; | |
1492 | break; | |
1493 | case 0x4270: | |
1494 | id = VECS; | |
1495 | break; | |
1496 | default: | |
a1201053 | 1497 | return -EINVAL; |
17865713 ZW |
1498 | } |
1499 | set_bit(id, (void *)vgpu->tlb_handle_pending); | |
1500 | ||
a1201053 | 1501 | return 0; |
17865713 ZW |
1502 | } |
1503 | ||
2fb39fad DC |
1504 | static int ring_reset_ctl_write(struct intel_vgpu *vgpu, |
1505 | unsigned int offset, void *p_data, unsigned int bytes) | |
1506 | { | |
1507 | u32 data; | |
1508 | ||
1509 | write_vreg(vgpu, offset, p_data, bytes); | |
1510 | data = vgpu_vreg(vgpu, offset); | |
1511 | ||
1512 | if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) | |
1513 | data |= RESET_CTL_READY_TO_RESET; | |
1514 | else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) | |
1515 | data &= ~RESET_CTL_READY_TO_RESET; | |
1516 | ||
1517 | vgpu_vreg(vgpu, offset) = data; | |
1518 | return 0; | |
1519 | } | |
1520 | ||
12d14cc4 ZW |
1521 | #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ |
1522 | ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ | |
1523 | f, s, am, rm, d, r, w); \ | |
1524 | if (ret) \ | |
1525 | return ret; \ | |
1526 | } while (0) | |
1527 | ||
1528 | #define MMIO_D(reg, d) \ | |
1529 | MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) | |
1530 | ||
1531 | #define MMIO_DH(reg, d, r, w) \ | |
1532 | MMIO_F(reg, 4, 0, 0, 0, d, r, w) | |
1533 | ||
1534 | #define MMIO_DFH(reg, d, f, r, w) \ | |
1535 | MMIO_F(reg, 4, f, 0, 0, d, r, w) | |
1536 | ||
1537 | #define MMIO_GM(reg, d, r, w) \ | |
1538 | MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) | |
1539 | ||
0aa5277c ZY |
1540 | #define MMIO_GM_RDR(reg, d, r, w) \ |
1541 | MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) | |
1542 | ||
12d14cc4 ZW |
1543 | #define MMIO_RO(reg, d, f, rm, r, w) \ |
1544 | MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) | |
1545 | ||
1546 | #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ | |
1547 | MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ | |
1548 | MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ | |
1549 | MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ | |
1550 | MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ | |
1551 | } while (0) | |
1552 | ||
1553 | #define MMIO_RING_D(prefix, d) \ | |
1554 | MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) | |
1555 | ||
1556 | #define MMIO_RING_DFH(prefix, d, f, r, w) \ | |
1557 | MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) | |
1558 | ||
1559 | #define MMIO_RING_GM(prefix, d, r, w) \ | |
1560 | MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) | |
1561 | ||
0aa5277c ZY |
1562 | #define MMIO_RING_GM_RDR(prefix, d, r, w) \ |
1563 | MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) | |
1564 | ||
12d14cc4 ZW |
1565 | #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ |
1566 | MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) | |
1567 | ||
1568 | static int init_generic_mmio_info(struct intel_gvt *gvt) | |
1569 | { | |
e39c5add | 1570 | struct drm_i915_private *dev_priv = gvt->dev_priv; |
12d14cc4 ZW |
1571 | int ret; |
1572 | ||
0aa5277c ZY |
1573 | MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, |
1574 | intel_vgpu_reg_imr_handler); | |
e39c5add ZW |
1575 | |
1576 | MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); | |
1577 | MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); | |
1578 | MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); | |
1579 | MMIO_D(SDEISR, D_ALL); | |
1580 | ||
0aa5277c | 1581 | MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); |
e39c5add | 1582 | |
0aa5277c ZY |
1583 | MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); |
1584 | MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); | |
1585 | MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); | |
1586 | MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); | |
e39c5add ZW |
1587 | |
1588 | #define RING_REG(base) (base + 0x28) | |
0aa5277c | 1589 | MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); |
e39c5add ZW |
1590 | #undef RING_REG |
1591 | ||
1592 | #define RING_REG(base) (base + 0x134) | |
0aa5277c | 1593 | MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); |
e39c5add ZW |
1594 | #undef RING_REG |
1595 | ||
0aa5277c ZY |
1596 | MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL); |
1597 | MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); | |
1598 | MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL); | |
e39c5add ZW |
1599 | MMIO_D(GEN7_CXT_SIZE, D_ALL); |
1600 | ||
0aa5277c ZY |
1601 | MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); |
1602 | MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1603 | MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1604 | MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1605 | MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); | |
e39c5add ZW |
1606 | |
1607 | /* RING MODE */ | |
1608 | #define RING_REG(base) (base + 0x29c) | |
0aa5277c ZY |
1609 | MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, |
1610 | ring_mode_mmio_write); | |
e39c5add ZW |
1611 | #undef RING_REG |
1612 | ||
0aa5277c ZY |
1613 | MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, |
1614 | NULL, NULL); | |
41bfab35 PZ |
1615 | MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, |
1616 | NULL, NULL); | |
04d348ae ZW |
1617 | MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, |
1618 | ring_timestamp_mmio_read, NULL); | |
1619 | MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, | |
1620 | ring_timestamp_mmio_read, NULL); | |
e39c5add | 1621 | |
0aa5277c ZY |
1622 | MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
1623 | MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, | |
1624 | NULL, NULL); | |
a045fba4 | 1625 | MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
0aa5277c ZY |
1626 | MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
1627 | MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
1628 | ||
1629 | MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
1630 | MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
1631 | MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
1632 | MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
1633 | MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
1634 | MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1635 | MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, | |
1636 | NULL, NULL); | |
a045fba4 | 1637 | MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
0aa5277c ZY |
1638 | MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL); |
1639 | MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1640 | MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1641 | MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1642 | MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1643 | MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1644 | MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
1645 | MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
a045fba4 | 1646 | MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
187447a1 | 1647 | MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
e39c5add ZW |
1648 | |
1649 | /* display */ | |
1650 | MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); | |
1651 | MMIO_D(0x602a0, D_ALL); | |
1652 | ||
1653 | MMIO_D(0x65050, D_ALL); | |
1654 | MMIO_D(0x650b4, D_ALL); | |
1655 | ||
1656 | MMIO_D(0xc4040, D_ALL); | |
1657 | MMIO_D(DERRMR, D_ALL); | |
1658 | ||
1659 | MMIO_D(PIPEDSL(PIPE_A), D_ALL); | |
1660 | MMIO_D(PIPEDSL(PIPE_B), D_ALL); | |
1661 | MMIO_D(PIPEDSL(PIPE_C), D_ALL); | |
1662 | MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); | |
1663 | ||
04d348ae ZW |
1664 | MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); |
1665 | MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); | |
1666 | MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); | |
1667 | MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); | |
e39c5add ZW |
1668 | |
1669 | MMIO_D(PIPESTAT(PIPE_A), D_ALL); | |
1670 | MMIO_D(PIPESTAT(PIPE_B), D_ALL); | |
1671 | MMIO_D(PIPESTAT(PIPE_C), D_ALL); | |
1672 | MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); | |
1673 | ||
1674 | MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); | |
1675 | MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); | |
1676 | MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); | |
1677 | MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); | |
1678 | ||
1679 | MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); | |
1680 | MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); | |
1681 | MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); | |
1682 | MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); | |
1683 | ||
1684 | MMIO_D(CURCNTR(PIPE_A), D_ALL); | |
1685 | MMIO_D(CURCNTR(PIPE_B), D_ALL); | |
1686 | MMIO_D(CURCNTR(PIPE_C), D_ALL); | |
1687 | ||
1688 | MMIO_D(CURPOS(PIPE_A), D_ALL); | |
1689 | MMIO_D(CURPOS(PIPE_B), D_ALL); | |
1690 | MMIO_D(CURPOS(PIPE_C), D_ALL); | |
1691 | ||
1692 | MMIO_D(CURBASE(PIPE_A), D_ALL); | |
1693 | MMIO_D(CURBASE(PIPE_B), D_ALL); | |
1694 | MMIO_D(CURBASE(PIPE_C), D_ALL); | |
1695 | ||
1696 | MMIO_D(0x700ac, D_ALL); | |
1697 | MMIO_D(0x710ac, D_ALL); | |
1698 | MMIO_D(0x720ac, D_ALL); | |
1699 | ||
1700 | MMIO_D(0x70090, D_ALL); | |
1701 | MMIO_D(0x70094, D_ALL); | |
1702 | MMIO_D(0x70098, D_ALL); | |
1703 | MMIO_D(0x7009c, D_ALL); | |
1704 | ||
1705 | MMIO_D(DSPCNTR(PIPE_A), D_ALL); | |
1706 | MMIO_D(DSPADDR(PIPE_A), D_ALL); | |
1707 | MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); | |
1708 | MMIO_D(DSPPOS(PIPE_A), D_ALL); | |
1709 | MMIO_D(DSPSIZE(PIPE_A), D_ALL); | |
04d348ae | 1710 | MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); |
e39c5add ZW |
1711 | MMIO_D(DSPOFFSET(PIPE_A), D_ALL); |
1712 | MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); | |
1713 | ||
1714 | MMIO_D(DSPCNTR(PIPE_B), D_ALL); | |
1715 | MMIO_D(DSPADDR(PIPE_B), D_ALL); | |
1716 | MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); | |
1717 | MMIO_D(DSPPOS(PIPE_B), D_ALL); | |
1718 | MMIO_D(DSPSIZE(PIPE_B), D_ALL); | |
04d348ae | 1719 | MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); |
e39c5add ZW |
1720 | MMIO_D(DSPOFFSET(PIPE_B), D_ALL); |
1721 | MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); | |
1722 | ||
1723 | MMIO_D(DSPCNTR(PIPE_C), D_ALL); | |
1724 | MMIO_D(DSPADDR(PIPE_C), D_ALL); | |
1725 | MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); | |
1726 | MMIO_D(DSPPOS(PIPE_C), D_ALL); | |
1727 | MMIO_D(DSPSIZE(PIPE_C), D_ALL); | |
04d348ae | 1728 | MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); |
e39c5add ZW |
1729 | MMIO_D(DSPOFFSET(PIPE_C), D_ALL); |
1730 | MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); | |
1731 | ||
1732 | MMIO_D(SPRCTL(PIPE_A), D_ALL); | |
1733 | MMIO_D(SPRLINOFF(PIPE_A), D_ALL); | |
1734 | MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); | |
1735 | MMIO_D(SPRPOS(PIPE_A), D_ALL); | |
1736 | MMIO_D(SPRSIZE(PIPE_A), D_ALL); | |
1737 | MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); | |
1738 | MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); | |
04d348ae | 1739 | MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); |
e39c5add ZW |
1740 | MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); |
1741 | MMIO_D(SPROFFSET(PIPE_A), D_ALL); | |
1742 | MMIO_D(SPRSCALE(PIPE_A), D_ALL); | |
1743 | MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); | |
1744 | ||
1745 | MMIO_D(SPRCTL(PIPE_B), D_ALL); | |
1746 | MMIO_D(SPRLINOFF(PIPE_B), D_ALL); | |
1747 | MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); | |
1748 | MMIO_D(SPRPOS(PIPE_B), D_ALL); | |
1749 | MMIO_D(SPRSIZE(PIPE_B), D_ALL); | |
1750 | MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); | |
1751 | MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); | |
04d348ae | 1752 | MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); |
e39c5add ZW |
1753 | MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); |
1754 | MMIO_D(SPROFFSET(PIPE_B), D_ALL); | |
1755 | MMIO_D(SPRSCALE(PIPE_B), D_ALL); | |
1756 | MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); | |
1757 | ||
1758 | MMIO_D(SPRCTL(PIPE_C), D_ALL); | |
1759 | MMIO_D(SPRLINOFF(PIPE_C), D_ALL); | |
1760 | MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); | |
1761 | MMIO_D(SPRPOS(PIPE_C), D_ALL); | |
1762 | MMIO_D(SPRSIZE(PIPE_C), D_ALL); | |
1763 | MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); | |
1764 | MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); | |
04d348ae | 1765 | MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); |
e39c5add ZW |
1766 | MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); |
1767 | MMIO_D(SPROFFSET(PIPE_C), D_ALL); | |
1768 | MMIO_D(SPRSCALE(PIPE_C), D_ALL); | |
1769 | MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); | |
1770 | ||
1771 | MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); | |
1772 | MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); | |
1773 | MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL); | |
1774 | ||
1775 | MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); | |
1776 | MMIO_D(HBLANK(TRANSCODER_A), D_ALL); | |
1777 | MMIO_D(HSYNC(TRANSCODER_A), D_ALL); | |
1778 | MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); | |
1779 | MMIO_D(VBLANK(TRANSCODER_A), D_ALL); | |
1780 | MMIO_D(VSYNC(TRANSCODER_A), D_ALL); | |
1781 | MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); | |
1782 | MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); | |
1783 | MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); | |
1784 | ||
1785 | MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); | |
1786 | MMIO_D(HBLANK(TRANSCODER_B), D_ALL); | |
1787 | MMIO_D(HSYNC(TRANSCODER_B), D_ALL); | |
1788 | MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); | |
1789 | MMIO_D(VBLANK(TRANSCODER_B), D_ALL); | |
1790 | MMIO_D(VSYNC(TRANSCODER_B), D_ALL); | |
1791 | MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); | |
1792 | MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); | |
1793 | MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); | |
1794 | ||
1795 | MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); | |
1796 | MMIO_D(HBLANK(TRANSCODER_C), D_ALL); | |
1797 | MMIO_D(HSYNC(TRANSCODER_C), D_ALL); | |
1798 | MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); | |
1799 | MMIO_D(VBLANK(TRANSCODER_C), D_ALL); | |
1800 | MMIO_D(VSYNC(TRANSCODER_C), D_ALL); | |
1801 | MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); | |
1802 | MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); | |
1803 | MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); | |
1804 | ||
1805 | MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); | |
1806 | MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); | |
1807 | MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); | |
1808 | MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); | |
1809 | MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); | |
1810 | MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); | |
1811 | MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); | |
1812 | MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); | |
1813 | ||
1814 | MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); | |
1815 | MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); | |
1816 | MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); | |
1817 | MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); | |
1818 | MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); | |
1819 | MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); | |
1820 | MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); | |
1821 | MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); | |
1822 | ||
1823 | MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); | |
1824 | MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); | |
1825 | MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); | |
1826 | MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); | |
1827 | MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); | |
1828 | MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); | |
1829 | MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); | |
1830 | MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); | |
1831 | ||
1832 | MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); | |
1833 | MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); | |
1834 | MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); | |
1835 | MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); | |
1836 | MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); | |
1837 | MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); | |
1838 | MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); | |
1839 | MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); | |
1840 | ||
1841 | MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); | |
1842 | MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); | |
1843 | MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); | |
1844 | MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); | |
1845 | MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); | |
1846 | MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); | |
1847 | MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); | |
1848 | MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); | |
1849 | ||
1850 | MMIO_D(PF_CTL(PIPE_A), D_ALL); | |
1851 | MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); | |
1852 | MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); | |
1853 | MMIO_D(PF_VSCALE(PIPE_A), D_ALL); | |
1854 | MMIO_D(PF_HSCALE(PIPE_A), D_ALL); | |
1855 | ||
1856 | MMIO_D(PF_CTL(PIPE_B), D_ALL); | |
1857 | MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); | |
1858 | MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); | |
1859 | MMIO_D(PF_VSCALE(PIPE_B), D_ALL); | |
1860 | MMIO_D(PF_HSCALE(PIPE_B), D_ALL); | |
1861 | ||
1862 | MMIO_D(PF_CTL(PIPE_C), D_ALL); | |
1863 | MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); | |
1864 | MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); | |
1865 | MMIO_D(PF_VSCALE(PIPE_C), D_ALL); | |
1866 | MMIO_D(PF_HSCALE(PIPE_C), D_ALL); | |
1867 | ||
1868 | MMIO_D(WM0_PIPEA_ILK, D_ALL); | |
1869 | MMIO_D(WM0_PIPEB_ILK, D_ALL); | |
1870 | MMIO_D(WM0_PIPEC_IVB, D_ALL); | |
1871 | MMIO_D(WM1_LP_ILK, D_ALL); | |
1872 | MMIO_D(WM2_LP_ILK, D_ALL); | |
1873 | MMIO_D(WM3_LP_ILK, D_ALL); | |
1874 | MMIO_D(WM1S_LP_ILK, D_ALL); | |
1875 | MMIO_D(WM2S_LP_IVB, D_ALL); | |
1876 | MMIO_D(WM3S_LP_IVB, D_ALL); | |
1877 | ||
1878 | MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); | |
1879 | MMIO_D(BLC_PWM_CPU_CTL, D_ALL); | |
1880 | MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); | |
1881 | MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); | |
1882 | ||
1883 | MMIO_D(0x48268, D_ALL); | |
1884 | ||
04d348ae ZW |
1885 | MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, |
1886 | gmbus_mmio_write); | |
1887 | MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); | |
e39c5add ZW |
1888 | MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); |
1889 | ||
04d348ae ZW |
1890 | MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, |
1891 | dp_aux_ch_ctl_mmio_write); | |
1892 | MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, | |
1893 | dp_aux_ch_ctl_mmio_write); | |
1894 | MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, | |
1895 | dp_aux_ch_ctl_mmio_write); | |
e39c5add | 1896 | |
04d348ae | 1897 | MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write); |
e39c5add | 1898 | |
04d348ae ZW |
1899 | MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); |
1900 | MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); | |
e39c5add | 1901 | |
04d348ae ZW |
1902 | MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); |
1903 | MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); | |
1904 | MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); | |
1905 | MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); | |
1906 | MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); | |
1907 | MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); | |
1908 | MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); | |
1909 | MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); | |
1910 | MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); | |
e39c5add ZW |
1911 | |
1912 | MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); | |
1913 | MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); | |
1914 | MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); | |
1915 | MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); | |
1916 | MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); | |
1917 | MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); | |
1918 | MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); | |
1919 | ||
1920 | MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); | |
1921 | MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); | |
1922 | MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); | |
1923 | MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); | |
1924 | MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); | |
1925 | MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); | |
1926 | MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); | |
1927 | ||
1928 | MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); | |
1929 | MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); | |
1930 | MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); | |
1931 | MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); | |
1932 | MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); | |
1933 | MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); | |
1934 | MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); | |
1935 | MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); | |
1936 | ||
1937 | MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); | |
1938 | MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); | |
1939 | MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); | |
1940 | ||
1941 | MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); | |
1942 | MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); | |
1943 | MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); | |
1944 | ||
1945 | MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); | |
1946 | MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); | |
1947 | MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); | |
1948 | ||
1949 | MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); | |
1950 | MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); | |
1951 | MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); | |
1952 | ||
1953 | MMIO_D(_FDI_RXA_MISC, D_ALL); | |
1954 | MMIO_D(_FDI_RXB_MISC, D_ALL); | |
1955 | MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); | |
1956 | MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); | |
1957 | MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); | |
1958 | MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); | |
1959 | ||
04d348ae | 1960 | MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); |
e39c5add ZW |
1961 | MMIO_D(PCH_PP_DIVISOR, D_ALL); |
1962 | MMIO_D(PCH_PP_STATUS, D_ALL); | |
1963 | MMIO_D(PCH_LVDS, D_ALL); | |
1964 | MMIO_D(_PCH_DPLL_A, D_ALL); | |
1965 | MMIO_D(_PCH_DPLL_B, D_ALL); | |
1966 | MMIO_D(_PCH_FPA0, D_ALL); | |
1967 | MMIO_D(_PCH_FPA1, D_ALL); | |
1968 | MMIO_D(_PCH_FPB0, D_ALL); | |
1969 | MMIO_D(_PCH_FPB1, D_ALL); | |
1970 | MMIO_D(PCH_DREF_CONTROL, D_ALL); | |
1971 | MMIO_D(PCH_RAWCLK_FREQ, D_ALL); | |
1972 | MMIO_D(PCH_DPLL_SEL, D_ALL); | |
1973 | ||
1974 | MMIO_D(0x61208, D_ALL); | |
1975 | MMIO_D(0x6120c, D_ALL); | |
1976 | MMIO_D(PCH_PP_ON_DELAYS, D_ALL); | |
1977 | MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); | |
1978 | ||
04d348ae ZW |
1979 | MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); |
1980 | MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); | |
1981 | MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); | |
1982 | MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); | |
1983 | MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL); | |
1984 | MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL); | |
e39c5add ZW |
1985 | |
1986 | MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, | |
1987 | PORTA_HOTPLUG_STATUS_MASK | |
1988 | | PORTB_HOTPLUG_STATUS_MASK | |
1989 | | PORTC_HOTPLUG_STATUS_MASK | |
1990 | | PORTD_HOTPLUG_STATUS_MASK, | |
1991 | NULL, NULL); | |
1992 | ||
04d348ae | 1993 | MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); |
e39c5add ZW |
1994 | MMIO_D(FUSE_STRAP, D_ALL); |
1995 | MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); | |
1996 | ||
1997 | MMIO_D(DISP_ARB_CTL, D_ALL); | |
1998 | MMIO_D(DISP_ARB_CTL2, D_ALL); | |
1999 | ||
2000 | MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); | |
2001 | MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); | |
2002 | MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); | |
2003 | ||
2004 | MMIO_D(SOUTH_CHICKEN1, D_ALL); | |
04d348ae | 2005 | MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); |
e39c5add ZW |
2006 | MMIO_D(_TRANSA_CHICKEN1, D_ALL); |
2007 | MMIO_D(_TRANSB_CHICKEN1, D_ALL); | |
2008 | MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); | |
2009 | MMIO_D(_TRANSA_CHICKEN2, D_ALL); | |
2010 | MMIO_D(_TRANSB_CHICKEN2, D_ALL); | |
2011 | ||
2012 | MMIO_D(ILK_DPFC_CB_BASE, D_ALL); | |
2013 | MMIO_D(ILK_DPFC_CONTROL, D_ALL); | |
2014 | MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); | |
2015 | MMIO_D(ILK_DPFC_STATUS, D_ALL); | |
2016 | MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); | |
2017 | MMIO_D(ILK_DPFC_CHICKEN, D_ALL); | |
2018 | MMIO_D(ILK_FBC_RT_BASE, D_ALL); | |
2019 | ||
2020 | MMIO_D(IPS_CTL, D_ALL); | |
2021 | ||
2022 | MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); | |
2023 | MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); | |
2024 | MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); | |
2025 | MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); | |
2026 | MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); | |
2027 | MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); | |
2028 | MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); | |
2029 | MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); | |
2030 | MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); | |
2031 | MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); | |
2032 | MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); | |
2033 | MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); | |
2034 | MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); | |
2035 | ||
2036 | MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); | |
2037 | MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); | |
2038 | MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); | |
2039 | MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); | |
2040 | MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); | |
2041 | MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); | |
2042 | MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); | |
2043 | MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); | |
2044 | MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); | |
2045 | MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); | |
2046 | MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); | |
2047 | MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); | |
2048 | MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); | |
2049 | ||
2050 | MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); | |
2051 | MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); | |
2052 | MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); | |
2053 | MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); | |
2054 | MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); | |
2055 | MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); | |
2056 | MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); | |
2057 | MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); | |
2058 | MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); | |
2059 | MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); | |
2060 | MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); | |
2061 | MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); | |
2062 | MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); | |
2063 | ||
04d348ae ZW |
2064 | MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); |
2065 | MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); | |
2066 | MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); | |
2067 | ||
2068 | MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); | |
2069 | MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); | |
2070 | MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); | |
2071 | ||
2072 | MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); | |
2073 | MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); | |
2074 | MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); | |
2075 | ||
e39c5add ZW |
2076 | MMIO_D(0x60110, D_ALL); |
2077 | MMIO_D(0x61110, D_ALL); | |
2078 | MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); | |
2079 | MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); | |
2080 | MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); | |
2081 | MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); | |
2082 | MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); | |
2083 | MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); | |
2084 | MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); | |
2085 | MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); | |
2086 | MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); | |
2087 | ||
2088 | MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); | |
2089 | MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); | |
2090 | MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); | |
2091 | MMIO_D(SPLL_CTL, D_ALL); | |
2092 | MMIO_D(_WRPLL_CTL1, D_ALL); | |
2093 | MMIO_D(_WRPLL_CTL2, D_ALL); | |
2094 | MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); | |
2095 | MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); | |
2096 | MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); | |
2097 | MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); | |
2098 | MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); | |
2099 | MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); | |
2100 | MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); | |
2101 | MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); | |
2102 | ||
2103 | MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); | |
2104 | MMIO_D(0x46508, D_ALL); | |
2105 | ||
2106 | MMIO_D(0x49080, D_ALL); | |
2107 | MMIO_D(0x49180, D_ALL); | |
2108 | MMIO_D(0x49280, D_ALL); | |
2109 | ||
2110 | MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); | |
2111 | MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); | |
2112 | MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); | |
2113 | ||
2114 | MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); | |
2115 | MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); | |
2116 | MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); | |
2117 | ||
e39c5add ZW |
2118 | MMIO_D(PIPE_MULT(PIPE_A), D_ALL); |
2119 | MMIO_D(PIPE_MULT(PIPE_B), D_ALL); | |
2120 | MMIO_D(PIPE_MULT(PIPE_C), D_ALL); | |
2121 | ||
2122 | MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); | |
2123 | MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); | |
2124 | MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); | |
2125 | ||
2126 | MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); | |
2127 | MMIO_D(SBI_ADDR, D_ALL); | |
04d348ae ZW |
2128 | MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); |
2129 | MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); | |
e39c5add ZW |
2130 | MMIO_D(PIXCLK_GATE, D_ALL); |
2131 | ||
04d348ae ZW |
2132 | MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, |
2133 | dp_aux_ch_ctl_mmio_write); | |
2134 | ||
2135 | MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); | |
2136 | MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); | |
2137 | MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); | |
2138 | MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); | |
2139 | MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); | |
2140 | ||
2141 | MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); | |
2142 | MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); | |
2143 | MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); | |
2144 | MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); | |
2145 | MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); | |
2146 | ||
2147 | MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); | |
2148 | MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); | |
2149 | MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); | |
2150 | MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); | |
2151 | MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); | |
e39c5add ZW |
2152 | |
2153 | MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); | |
2154 | MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); | |
2155 | MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); | |
2156 | MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); | |
2157 | MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); | |
2158 | ||
2159 | MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); | |
2160 | MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); | |
2161 | ||
2162 | MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); | |
2163 | MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); | |
2164 | MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); | |
2165 | MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); | |
2166 | ||
2167 | MMIO_D(_TRANSA_MSA_MISC, D_ALL); | |
2168 | MMIO_D(_TRANSB_MSA_MISC, D_ALL); | |
2169 | MMIO_D(_TRANSC_MSA_MISC, D_ALL); | |
2170 | MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); | |
2171 | ||
2172 | MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); | |
2173 | MMIO_D(FORCEWAKE_ACK, D_ALL); | |
2174 | MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); | |
2175 | MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); | |
0aa5277c ZY |
2176 | MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); |
2177 | MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
e39c5add ZW |
2178 | MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); |
2179 | MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL); | |
2180 | MMIO_D(ECOBUS, D_ALL); | |
2181 | MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); | |
2182 | MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); | |
2183 | MMIO_D(GEN6_RPNSWREQ, D_ALL); | |
2184 | MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); | |
2185 | MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); | |
2186 | MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); | |
2187 | MMIO_D(GEN6_RPSTAT1, D_ALL); | |
2188 | MMIO_D(GEN6_RP_CONTROL, D_ALL); | |
2189 | MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); | |
2190 | MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); | |
2191 | MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); | |
2192 | MMIO_D(GEN6_RP_CUR_UP, D_ALL); | |
2193 | MMIO_D(GEN6_RP_PREV_UP, D_ALL); | |
2194 | MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); | |
2195 | MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); | |
2196 | MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); | |
2197 | MMIO_D(GEN6_RP_UP_EI, D_ALL); | |
2198 | MMIO_D(GEN6_RP_DOWN_EI, D_ALL); | |
2199 | MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); | |
2200 | MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); | |
2201 | MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); | |
2202 | MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); | |
2203 | MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); | |
2204 | MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); | |
2205 | MMIO_D(GEN6_RC_SLEEP, D_ALL); | |
2206 | MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); | |
2207 | MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); | |
2208 | MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); | |
2209 | MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); | |
2210 | MMIO_D(GEN6_PMINTRMSK, D_ALL); | |
04d348ae ZW |
2211 | MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); |
2212 | MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); | |
2213 | MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); | |
2214 | MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); | |
2215 | MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); | |
2216 | MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write); | |
e39c5add ZW |
2217 | |
2218 | MMIO_D(RSTDBYCTL, D_ALL); | |
2219 | ||
2220 | MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); | |
2221 | MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); | |
2222 | MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write); | |
04d348ae | 2223 | MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); |
e39c5add ZW |
2224 | |
2225 | MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL); | |
2226 | ||
2227 | MMIO_D(TILECTL, D_ALL); | |
2228 | ||
2229 | MMIO_D(GEN6_UCGCTL1, D_ALL); | |
2230 | MMIO_D(GEN6_UCGCTL2, D_ALL); | |
2231 | ||
2232 | MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); | |
2233 | ||
8bcd7c18 | 2234 | MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_BDW); |
e39c5add ZW |
2235 | MMIO_D(GEN6_PCODE_DATA, D_ALL); |
2236 | MMIO_D(0x13812c, D_ALL); | |
2237 | MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); | |
2238 | MMIO_D(HSW_EDRAM_CAP, D_ALL); | |
2239 | MMIO_D(HSW_IDICR, D_ALL); | |
2240 | MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); | |
2241 | ||
2242 | MMIO_D(0x3c, D_ALL); | |
2243 | MMIO_D(0x860, D_ALL); | |
2244 | MMIO_D(ECOSKPD, D_ALL); | |
2245 | MMIO_D(0x121d0, D_ALL); | |
2246 | MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); | |
2247 | MMIO_D(0x41d0, D_ALL); | |
2248 | MMIO_D(GAC_ECO_BITS, D_ALL); | |
2249 | MMIO_D(0x6200, D_ALL); | |
2250 | MMIO_D(0x6204, D_ALL); | |
2251 | MMIO_D(0x6208, D_ALL); | |
2252 | MMIO_D(0x7118, D_ALL); | |
2253 | MMIO_D(0x7180, D_ALL); | |
2254 | MMIO_D(0x7408, D_ALL); | |
2255 | MMIO_D(0x7c00, D_ALL); | |
975629c3 | 2256 | MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); |
e39c5add ZW |
2257 | MMIO_D(0x911c, D_ALL); |
2258 | MMIO_D(0x9120, D_ALL); | |
a045fba4 | 2259 | MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); |
e39c5add ZW |
2260 | |
2261 | MMIO_D(GAB_CTL, D_ALL); | |
2262 | MMIO_D(0x48800, D_ALL); | |
2263 | MMIO_D(0xce044, D_ALL); | |
2264 | MMIO_D(0xe6500, D_ALL); | |
2265 | MMIO_D(0xe6504, D_ALL); | |
2266 | MMIO_D(0xe6600, D_ALL); | |
2267 | MMIO_D(0xe6604, D_ALL); | |
2268 | MMIO_D(0xe6700, D_ALL); | |
2269 | MMIO_D(0xe6704, D_ALL); | |
2270 | MMIO_D(0xe6800, D_ALL); | |
2271 | MMIO_D(0xe6804, D_ALL); | |
2272 | MMIO_D(PCH_GMBUS4, D_ALL); | |
2273 | MMIO_D(PCH_GMBUS5, D_ALL); | |
2274 | ||
2275 | MMIO_D(0x902c, D_ALL); | |
2276 | MMIO_D(0xec008, D_ALL); | |
2277 | MMIO_D(0xec00c, D_ALL); | |
2278 | MMIO_D(0xec008 + 0x18, D_ALL); | |
2279 | MMIO_D(0xec00c + 0x18, D_ALL); | |
2280 | MMIO_D(0xec008 + 0x18 * 2, D_ALL); | |
2281 | MMIO_D(0xec00c + 0x18 * 2, D_ALL); | |
2282 | MMIO_D(0xec008 + 0x18 * 3, D_ALL); | |
2283 | MMIO_D(0xec00c + 0x18 * 3, D_ALL); | |
2284 | MMIO_D(0xec408, D_ALL); | |
2285 | MMIO_D(0xec40c, D_ALL); | |
2286 | MMIO_D(0xec408 + 0x18, D_ALL); | |
2287 | MMIO_D(0xec40c + 0x18, D_ALL); | |
2288 | MMIO_D(0xec408 + 0x18 * 2, D_ALL); | |
2289 | MMIO_D(0xec40c + 0x18 * 2, D_ALL); | |
2290 | MMIO_D(0xec408 + 0x18 * 3, D_ALL); | |
2291 | MMIO_D(0xec40c + 0x18 * 3, D_ALL); | |
2292 | MMIO_D(0xfc810, D_ALL); | |
2293 | MMIO_D(0xfc81c, D_ALL); | |
2294 | MMIO_D(0xfc828, D_ALL); | |
2295 | MMIO_D(0xfc834, D_ALL); | |
2296 | MMIO_D(0xfcc00, D_ALL); | |
2297 | MMIO_D(0xfcc0c, D_ALL); | |
2298 | MMIO_D(0xfcc18, D_ALL); | |
2299 | MMIO_D(0xfcc24, D_ALL); | |
2300 | MMIO_D(0xfd000, D_ALL); | |
2301 | MMIO_D(0xfd00c, D_ALL); | |
2302 | MMIO_D(0xfd018, D_ALL); | |
2303 | MMIO_D(0xfd024, D_ALL); | |
2304 | MMIO_D(0xfd034, D_ALL); | |
2305 | ||
2306 | MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); | |
2307 | MMIO_D(0x2054, D_ALL); | |
2308 | MMIO_D(0x12054, D_ALL); | |
2309 | MMIO_D(0x22054, D_ALL); | |
2310 | MMIO_D(0x1a054, D_ALL); | |
2311 | ||
2312 | MMIO_D(0x44070, D_ALL); | |
41bfab35 | 2313 | MMIO_DFH(0x215c, D_HSW_PLUS, F_CMD_ACCESS, NULL, NULL); |
e39c5add ZW |
2314 | MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); |
2315 | MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2316 | MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2317 | MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2318 | ||
0aa5277c ZY |
2319 | MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_HSW_PLUS, NULL, NULL); |
2320 | MMIO_DFH(GEN7_OACONTROL, D_HSW, F_CMD_ACCESS, NULL, NULL); | |
e39c5add ZW |
2321 | MMIO_D(0x2b00, D_BDW_PLUS); |
2322 | MMIO_D(0x2360, D_BDW_PLUS); | |
0aa5277c ZY |
2323 | MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); |
2324 | MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2325 | MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
e39c5add ZW |
2326 | |
2327 | MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2328 | MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
0aa5277c ZY |
2329 | MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); |
2330 | ||
2331 | MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2332 | MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2333 | MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2334 | MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2335 | MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2336 | MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2337 | MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2338 | MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2339 | MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2340 | MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
2341 | MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); | |
17865713 ZW |
2342 | MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); |
2343 | MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); | |
2344 | MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); | |
2345 | MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); | |
2346 | MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); | |
e39c5add ZW |
2347 | MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
2348 | ||
9112caaf ZY |
2349 | MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
2350 | MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); | |
2351 | MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2352 | MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2353 | MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2354 | MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2355 | MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); | |
2356 | MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2357 | MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2358 | MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2359 | MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
12d14cc4 ZW |
2360 | return 0; |
2361 | } | |
2362 | ||
2363 | static int init_broadwell_mmio_info(struct intel_gvt *gvt) | |
2364 | { | |
e39c5add | 2365 | struct drm_i915_private *dev_priv = gvt->dev_priv; |
12d14cc4 ZW |
2366 | int ret; |
2367 | ||
0aa5277c | 2368 | MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL, |
e39c5add ZW |
2369 | intel_vgpu_reg_imr_handler); |
2370 | ||
2371 | MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); | |
2372 | MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); | |
2373 | MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); | |
2374 | MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); | |
2375 | ||
2376 | MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); | |
2377 | MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); | |
2378 | MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); | |
2379 | MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); | |
2380 | ||
2381 | MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); | |
2382 | MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); | |
2383 | MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); | |
2384 | MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); | |
2385 | ||
2386 | MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); | |
2387 | MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); | |
2388 | MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); | |
2389 | MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); | |
2390 | ||
2391 | MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, | |
2392 | intel_vgpu_reg_imr_handler); | |
2393 | MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, | |
2394 | intel_vgpu_reg_ier_handler); | |
2395 | MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, | |
2396 | intel_vgpu_reg_iir_handler); | |
2397 | MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); | |
2398 | ||
2399 | MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, | |
2400 | intel_vgpu_reg_imr_handler); | |
2401 | MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, | |
2402 | intel_vgpu_reg_ier_handler); | |
2403 | MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, | |
2404 | intel_vgpu_reg_iir_handler); | |
2405 | MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); | |
2406 | ||
2407 | MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, | |
2408 | intel_vgpu_reg_imr_handler); | |
2409 | MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, | |
2410 | intel_vgpu_reg_ier_handler); | |
2411 | MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, | |
2412 | intel_vgpu_reg_iir_handler); | |
2413 | MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); | |
2414 | ||
2415 | MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); | |
2416 | MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); | |
2417 | MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); | |
2418 | MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); | |
2419 | ||
2420 | MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); | |
2421 | MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); | |
2422 | MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); | |
2423 | MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); | |
2424 | ||
2425 | MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); | |
2426 | MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); | |
2427 | MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); | |
2428 | MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); | |
2429 | ||
2430 | MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, | |
2431 | intel_vgpu_reg_master_irq_handler); | |
2432 | ||
0aa5277c ZY |
2433 | MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, |
2434 | F_CMD_ACCESS, NULL, NULL); | |
2435 | MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2436 | ||
2437 | MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, | |
2438 | NULL, NULL); | |
2439 | MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS, | |
2440 | F_CMD_ACCESS, NULL, NULL); | |
2441 | MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); | |
2442 | MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, | |
2443 | NULL, NULL); | |
2444 | MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS, | |
2445 | F_CMD_ACCESS, NULL, NULL); | |
2446 | MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS, | |
2447 | F_CMD_ACCESS, NULL, NULL); | |
2448 | MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, | |
2449 | ring_mode_mmio_write); | |
2450 | MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, | |
2451 | F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
2452 | MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, | |
2453 | F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
04d348ae ZW |
2454 | MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, |
2455 | ring_timestamp_mmio_read, NULL); | |
e39c5add | 2456 | |
0aa5277c | 2457 | MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
e39c5add | 2458 | |
2fb39fad DC |
2459 | #define RING_REG(base) (base + 0xd0) |
2460 | MMIO_RING_F(RING_REG, 4, F_RO, 0, | |
2461 | ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, | |
2462 | ring_reset_ctl_write); | |
2463 | MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, | |
2464 | ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, | |
2465 | ring_reset_ctl_write); | |
2466 | #undef RING_REG | |
2467 | ||
e39c5add | 2468 | #define RING_REG(base) (base + 0x230) |
28c4c6ca ZW |
2469 | MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); |
2470 | MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write); | |
e39c5add ZW |
2471 | #undef RING_REG |
2472 | ||
2473 | #define RING_REG(base) (base + 0x234) | |
0aa5277c ZY |
2474 | MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, |
2475 | NULL, NULL); | |
2476 | MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0, | |
2477 | ~0LL, D_BDW_PLUS, NULL, NULL); | |
e39c5add ZW |
2478 | #undef RING_REG |
2479 | ||
2480 | #define RING_REG(base) (base + 0x244) | |
0aa5277c ZY |
2481 | MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
2482 | MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, | |
2483 | NULL, NULL); | |
e39c5add ZW |
2484 | #undef RING_REG |
2485 | ||
2486 | #define RING_REG(base) (base + 0x370) | |
2487 | MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); | |
2488 | MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS, | |
2489 | NULL, NULL); | |
2490 | #undef RING_REG | |
2491 | ||
2492 | #define RING_REG(base) (base + 0x3a0) | |
2493 | MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); | |
2494 | MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL); | |
2495 | #undef RING_REG | |
2496 | ||
2497 | MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); | |
2498 | MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); | |
2499 | MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); | |
2500 | MMIO_D(0x1c1d0, D_BDW_PLUS); | |
2501 | MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); | |
2502 | MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); | |
2503 | MMIO_D(0x1c054, D_BDW_PLUS); | |
2504 | ||
8bcd7c18 WL |
2505 | MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); |
2506 | ||
e39c5add ZW |
2507 | MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); |
2508 | MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); | |
2509 | ||
2510 | MMIO_D(GAMTARBMODE, D_BDW_PLUS); | |
2511 | ||
2512 | #define RING_REG(base) (base + 0x270) | |
2513 | MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); | |
2514 | MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); | |
2515 | #undef RING_REG | |
2516 | ||
0aa5277c ZY |
2517 | MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL); |
2518 | MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL); | |
e39c5add | 2519 | |
a045fba4 | 2520 | MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
e39c5add | 2521 | |
593e59b4 ZY |
2522 | MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); |
2523 | MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); | |
2524 | MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); | |
e39c5add ZW |
2525 | |
2526 | MMIO_D(WM_MISC, D_BDW); | |
2527 | MMIO_D(BDW_EDP_PSR_BASE, D_BDW); | |
2528 | ||
2529 | MMIO_D(0x66c00, D_BDW_PLUS); | |
2530 | MMIO_D(0x66c04, D_BDW_PLUS); | |
2531 | ||
2532 | MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); | |
2533 | ||
2534 | MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); | |
2535 | MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); | |
2536 | MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); | |
2537 | ||
593e59b4 | 2538 | MMIO_D(0xfdc, D_BDW_PLUS); |
0aa5277c ZY |
2539 | MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, |
2540 | NULL, NULL); | |
2541 | MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, | |
2542 | NULL, NULL); | |
2543 | MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
e39c5add | 2544 | |
0aa5277c ZY |
2545 | MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL); |
2546 | MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL); | |
e39c5add | 2547 | MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
0aa5277c ZY |
2548 | MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL); |
2549 | MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL); | |
e39c5add ZW |
2550 | MMIO_D(0xb110, D_BDW); |
2551 | ||
e6cedfea ZY |
2552 | MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, |
2553 | NULL, force_nonpriv_write); | |
e39c5add | 2554 | |
593e59b4 ZY |
2555 | MMIO_D(0x22040, D_BDW_PLUS); |
2556 | MMIO_D(0x44484, D_BDW_PLUS); | |
2557 | MMIO_D(0x4448c, D_BDW_PLUS); | |
2558 | ||
0aa5277c | 2559 | MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL); |
e39c5add ZW |
2560 | MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); |
2561 | ||
0aa5277c | 2562 | MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL); |
e39c5add ZW |
2563 | |
2564 | MMIO_D(0x110000, D_BDW_PLUS); | |
2565 | ||
2566 | MMIO_D(0x48400, D_BDW_PLUS); | |
2567 | ||
2568 | MMIO_D(0x6e570, D_BDW_PLUS); | |
2569 | MMIO_D(0x65f10, D_BDW_PLUS); | |
2570 | ||
a045fba4 PG |
2571 | MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
2572 | MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
2573 | MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
0aa5277c | 2574 | MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); |
e39c5add | 2575 | |
0aa5277c | 2576 | MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL); |
e39c5add | 2577 | |
9112caaf ZY |
2578 | MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); |
2579 | MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2580 | MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2581 | MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2582 | MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2583 | MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2584 | MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2585 | MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2586 | MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); | |
12d14cc4 ZW |
2587 | return 0; |
2588 | } | |
2589 | ||
e39c5add ZW |
2590 | static int init_skl_mmio_info(struct intel_gvt *gvt) |
2591 | { | |
2592 | struct drm_i915_private *dev_priv = gvt->dev_priv; | |
2593 | int ret; | |
2594 | ||
2595 | MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); | |
2596 | MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); | |
2597 | MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); | |
2598 | MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); | |
2599 | MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); | |
2600 | MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); | |
2601 | ||
5cf5fe8f XH |
2602 | MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, |
2603 | dp_aux_ch_ctl_mmio_write); | |
2604 | MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, | |
2605 | dp_aux_ch_ctl_mmio_write); | |
2606 | MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, | |
2607 | dp_aux_ch_ctl_mmio_write); | |
2608 | ||
2609 | MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS); | |
2610 | MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL, | |
2611 | skl_power_well_ctl_write); | |
2612 | MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write); | |
e39c5add | 2613 | |
e39c5add ZW |
2614 | MMIO_D(0xa210, D_SKL_PLUS); |
2615 | MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); | |
2616 | MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); | |
a045fba4 | 2617 | MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); |
5cf5fe8f XH |
2618 | MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, skl_misc_ctl_write); |
2619 | MMIO_DH(0x42080, D_SKL_PLUS, NULL, skl_misc_ctl_write); | |
2620 | MMIO_D(0x45504, D_SKL_PLUS); | |
2621 | MMIO_D(0x45520, D_SKL_PLUS); | |
2622 | MMIO_D(0x46000, D_SKL_PLUS); | |
2623 | MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write); | |
2624 | MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write); | |
2625 | MMIO_D(0x6C040, D_SKL | D_KBL); | |
2626 | MMIO_D(0x6C048, D_SKL | D_KBL); | |
2627 | MMIO_D(0x6C050, D_SKL | D_KBL); | |
2628 | MMIO_D(0x6C044, D_SKL | D_KBL); | |
2629 | MMIO_D(0x6C04C, D_SKL | D_KBL); | |
2630 | MMIO_D(0x6C054, D_SKL | D_KBL); | |
2631 | MMIO_D(0x6c058, D_SKL | D_KBL); | |
2632 | MMIO_D(0x6c05c, D_SKL | D_KBL); | |
2633 | MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL); | |
2634 | ||
2635 | MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); | |
2636 | MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); | |
2637 | MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); | |
2638 | MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); | |
2639 | MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); | |
2640 | MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); | |
2641 | ||
2642 | MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); | |
2643 | MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); | |
2644 | MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); | |
2645 | MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); | |
2646 | MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); | |
2647 | MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); | |
2648 | ||
2649 | MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); | |
2650 | MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); | |
2651 | MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); | |
2652 | MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); | |
2653 | MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); | |
2654 | MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); | |
2655 | ||
2656 | MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); | |
2657 | MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); | |
2658 | MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); | |
2659 | MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); | |
2660 | ||
2661 | MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); | |
2662 | MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); | |
2663 | MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); | |
2664 | MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); | |
2665 | ||
2666 | MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); | |
2667 | MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); | |
2668 | MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); | |
2669 | MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); | |
2670 | ||
2671 | MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); | |
2672 | MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); | |
2673 | MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); | |
2674 | ||
2675 | MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2676 | MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2677 | MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2678 | ||
2679 | MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2680 | MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2681 | MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2682 | ||
2683 | MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2684 | MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2685 | MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2686 | ||
2687 | MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2688 | MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2689 | MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2690 | ||
2691 | MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); | |
2692 | MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); | |
2693 | MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); | |
2694 | ||
2695 | MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); | |
2696 | MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); | |
2697 | MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); | |
2698 | ||
2699 | MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); | |
2700 | MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); | |
2701 | MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); | |
2702 | ||
2703 | MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); | |
2704 | MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); | |
2705 | MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); | |
2706 | ||
2707 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); | |
2708 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); | |
2709 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); | |
2710 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); | |
2711 | ||
2712 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); | |
2713 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); | |
2714 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); | |
2715 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); | |
2716 | ||
2717 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); | |
2718 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); | |
2719 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); | |
2720 | MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); | |
2721 | ||
2722 | MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); | |
2723 | MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); | |
2724 | MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); | |
2725 | MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); | |
2726 | ||
2727 | MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); | |
2728 | MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); | |
2729 | MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); | |
2730 | MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); | |
2731 | ||
2732 | MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); | |
2733 | MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); | |
2734 | MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); | |
2735 | MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); | |
2736 | ||
2737 | MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); | |
2738 | MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); | |
2739 | MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); | |
2740 | MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); | |
2741 | ||
2742 | MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); | |
2743 | MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); | |
2744 | MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); | |
2745 | MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); | |
2746 | ||
2747 | MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); | |
2748 | MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); | |
2749 | MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); | |
2750 | MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); | |
2751 | ||
2752 | MMIO_D(0x70380, D_SKL_PLUS); | |
2753 | MMIO_D(0x71380, D_SKL_PLUS); | |
2754 | MMIO_D(0x72380, D_SKL_PLUS); | |
2755 | MMIO_D(0x7039c, D_SKL_PLUS); | |
2756 | ||
2757 | MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL_PLUS, NULL, NULL); | |
2758 | MMIO_D(0x8f074, D_SKL | D_KBL); | |
2759 | MMIO_D(0x8f004, D_SKL | D_KBL); | |
2760 | MMIO_D(0x8f034, D_SKL | D_KBL); | |
2761 | ||
2762 | MMIO_D(0xb11c, D_SKL | D_KBL); | |
2763 | ||
2764 | MMIO_D(0x51000, D_SKL | D_KBL); | |
2765 | MMIO_D(0x6c00c, D_SKL_PLUS); | |
2766 | ||
2767 | MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); | |
2768 | MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); | |
2769 | ||
2770 | MMIO_D(0xd08, D_SKL_PLUS); | |
2771 | MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL); | |
2772 | MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); | |
e39c5add ZW |
2773 | |
2774 | /* TRTT */ | |
5cf5fe8f XH |
2775 | MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); |
2776 | MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); | |
2777 | MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); | |
2778 | MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); | |
2779 | MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); | |
2780 | MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write); | |
2781 | MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write); | |
e39c5add | 2782 | |
5cf5fe8f | 2783 | MMIO_D(0x45008, D_SKL | D_KBL); |
e39c5add | 2784 | |
5cf5fe8f | 2785 | MMIO_D(0x46430, D_SKL | D_KBL); |
e39c5add | 2786 | |
5cf5fe8f | 2787 | MMIO_D(0x46520, D_SKL | D_KBL); |
e39c5add | 2788 | |
5cf5fe8f XH |
2789 | MMIO_D(0xc403c, D_SKL | D_KBL); |
2790 | MMIO_D(0xb004, D_SKL_PLUS); | |
e39c5add ZW |
2791 | MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); |
2792 | ||
5cf5fe8f XH |
2793 | MMIO_D(0x65900, D_SKL_PLUS); |
2794 | MMIO_D(0x1082c0, D_SKL | D_KBL); | |
2795 | MMIO_D(0x4068, D_SKL | D_KBL); | |
2796 | MMIO_D(0x67054, D_SKL | D_KBL); | |
2797 | MMIO_D(0x6e560, D_SKL | D_KBL); | |
2798 | MMIO_D(0x6e554, D_SKL | D_KBL); | |
2799 | MMIO_D(0x2b20, D_SKL | D_KBL); | |
2800 | MMIO_D(0x65f00, D_SKL | D_KBL); | |
2801 | MMIO_D(0x65f08, D_SKL | D_KBL); | |
2802 | MMIO_D(0x320f0, D_SKL | D_KBL); | |
2803 | ||
2804 | MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2805 | MMIO_DFH(_REG_VECS_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); | |
2806 | MMIO_D(0x70034, D_SKL_PLUS); | |
2807 | MMIO_D(0x71034, D_SKL_PLUS); | |
2808 | MMIO_D(0x72034, D_SKL_PLUS); | |
2809 | ||
2810 | MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS); | |
2811 | MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS); | |
2812 | MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS); | |
2813 | MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS); | |
2814 | MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS); | |
2815 | MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS); | |
2816 | ||
2817 | MMIO_D(0x44500, D_SKL_PLUS); | |
0aa5277c | 2818 | MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); |
5cf5fe8f | 2819 | MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS, |
9112caaf | 2820 | NULL, NULL); |
5cf5fe8f XH |
2821 | |
2822 | MMIO_D(0x4ab8, D_KBL); | |
2823 | MMIO_D(0x940c, D_SKL_PLUS); | |
2824 | MMIO_D(0x2248, D_SKL_PLUS | D_KBL); | |
2825 | MMIO_D(0x4ab0, D_SKL | D_KBL); | |
2826 | MMIO_D(0x20d4, D_SKL | D_KBL); | |
2827 | ||
e39c5add ZW |
2828 | return 0; |
2829 | } | |
04d348ae | 2830 | |
12d14cc4 ZW |
2831 | /** |
2832 | * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset | |
2833 | * @gvt: GVT device | |
2834 | * @offset: register offset | |
2835 | * | |
2836 | * This function is used to find the MMIO information entry from hash table | |
2837 | * | |
2838 | * Returns: | |
2839 | * pointer to MMIO information entry, NULL if not exists | |
2840 | */ | |
2841 | struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, | |
2842 | unsigned int offset) | |
2843 | { | |
2844 | struct intel_gvt_mmio_info *e; | |
2845 | ||
2846 | WARN_ON(!IS_ALIGNED(offset, 4)); | |
2847 | ||
2848 | hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { | |
2849 | if (e->offset == offset) | |
2850 | return e; | |
2851 | } | |
2852 | return NULL; | |
2853 | } | |
2854 | ||
2855 | /** | |
2856 | * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device | |
2857 | * @gvt: GVT device | |
2858 | * | |
2859 | * This function is called at the driver unloading stage, to clean up the MMIO | |
2860 | * information table of GVT device | |
2861 | * | |
2862 | */ | |
2863 | void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) | |
2864 | { | |
2865 | struct hlist_node *tmp; | |
2866 | struct intel_gvt_mmio_info *e; | |
2867 | int i; | |
2868 | ||
2869 | hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) | |
2870 | kfree(e); | |
2871 | ||
2872 | vfree(gvt->mmio.mmio_attribute); | |
2873 | gvt->mmio.mmio_attribute = NULL; | |
2874 | } | |
2875 | ||
2876 | /** | |
2877 | * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device | |
2878 | * @gvt: GVT device | |
2879 | * | |
2880 | * This function is called at the initialization stage, to setup the MMIO | |
2881 | * information table for GVT device | |
2882 | * | |
2883 | * Returns: | |
2884 | * zero on success, negative if failed. | |
2885 | */ | |
2886 | int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) | |
2887 | { | |
2888 | struct intel_gvt_device_info *info = &gvt->device_info; | |
2889 | struct drm_i915_private *dev_priv = gvt->dev_priv; | |
2890 | int ret; | |
2891 | ||
2892 | gvt->mmio.mmio_attribute = vzalloc(info->mmio_size); | |
2893 | if (!gvt->mmio.mmio_attribute) | |
2894 | return -ENOMEM; | |
2895 | ||
2896 | ret = init_generic_mmio_info(gvt); | |
2897 | if (ret) | |
2898 | goto err; | |
2899 | ||
2900 | if (IS_BROADWELL(dev_priv)) { | |
2901 | ret = init_broadwell_mmio_info(gvt); | |
2902 | if (ret) | |
2903 | goto err; | |
e3476c00 XH |
2904 | } else if (IS_SKYLAKE(dev_priv) |
2905 | || IS_KABYLAKE(dev_priv)) { | |
e39c5add ZW |
2906 | ret = init_broadwell_mmio_info(gvt); |
2907 | if (ret) | |
2908 | goto err; | |
2909 | ret = init_skl_mmio_info(gvt); | |
2910 | if (ret) | |
2911 | goto err; | |
12d14cc4 ZW |
2912 | } |
2913 | return 0; | |
2914 | err: | |
2915 | intel_gvt_clean_mmio_info(gvt); | |
2916 | return ret; | |
2917 | } | |
e39c5add ZW |
2918 | |
2919 | /** | |
2920 | * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed | |
2921 | * @gvt: a GVT device | |
2922 | * @offset: register offset | |
2923 | * | |
2924 | */ | |
2925 | void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset) | |
2926 | { | |
2927 | gvt->mmio.mmio_attribute[offset >> 2] |= | |
2928 | F_ACCESSED; | |
2929 | } | |
2930 | ||
2931 | /** | |
2932 | * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command | |
2933 | * @gvt: a GVT device | |
2934 | * @offset: register offset | |
2935 | * | |
2936 | */ | |
2937 | bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt, | |
2938 | unsigned int offset) | |
2939 | { | |
2940 | return gvt->mmio.mmio_attribute[offset >> 2] & | |
2941 | F_CMD_ACCESS; | |
2942 | } | |
2943 | ||
2944 | /** | |
2945 | * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned | |
2946 | * @gvt: a GVT device | |
2947 | * @offset: register offset | |
2948 | * | |
2949 | */ | |
2950 | bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt, | |
2951 | unsigned int offset) | |
2952 | { | |
2953 | return gvt->mmio.mmio_attribute[offset >> 2] & | |
2954 | F_UNALIGN; | |
2955 | } | |
2956 | ||
2957 | /** | |
2958 | * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command | |
2959 | * @gvt: a GVT device | |
2960 | * @offset: register offset | |
2961 | * | |
2962 | */ | |
2963 | void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt, | |
2964 | unsigned int offset) | |
2965 | { | |
2966 | gvt->mmio.mmio_attribute[offset >> 2] |= | |
2967 | F_CMD_ACCESSED; | |
2968 | } | |
2969 | ||
2970 | /** | |
2971 | * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask | |
2972 | * @gvt: a GVT device | |
2973 | * @offset: register offset | |
2974 | * | |
2975 | * Returns: | |
2976 | * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. | |
2977 | * | |
2978 | */ | |
2979 | bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset) | |
2980 | { | |
2981 | return gvt->mmio.mmio_attribute[offset >> 2] & | |
2982 | F_MODE_MASK; | |
2983 | } | |
2984 | ||
2985 | /** | |
2986 | * intel_vgpu_default_mmio_read - default MMIO read handler | |
2987 | * @vgpu: a vGPU | |
2988 | * @offset: access offset | |
2989 | * @p_data: data return buffer | |
2990 | * @bytes: access data length | |
2991 | * | |
2992 | * Returns: | |
2993 | * Zero on success, negative error code if failed. | |
2994 | */ | |
2995 | int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, | |
2996 | void *p_data, unsigned int bytes) | |
2997 | { | |
2998 | read_vreg(vgpu, offset, p_data, bytes); | |
2999 | return 0; | |
3000 | } | |
3001 | ||
3002 | /** | |
3003 | * intel_t_default_mmio_write - default MMIO write handler | |
3004 | * @vgpu: a vGPU | |
3005 | * @offset: access offset | |
3006 | * @p_data: write data buffer | |
3007 | * @bytes: access data length | |
3008 | * | |
3009 | * Returns: | |
3010 | * Zero on success, negative error code if failed. | |
3011 | */ | |
3012 | int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
3013 | void *p_data, unsigned int bytes) | |
3014 | { | |
3015 | write_vreg(vgpu, offset, p_data, bytes); | |
3016 | return 0; | |
3017 | } | |
4938ca90 ZY |
3018 | |
3019 | /** | |
3020 | * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be | |
3021 | * force-nopriv register | |
3022 | * | |
3023 | * @gvt: a GVT device | |
3024 | * @offset: register offset | |
3025 | * | |
3026 | * Returns: | |
3027 | * True if the register is in force-nonpriv whitelist; | |
3028 | * False if outside; | |
3029 | */ | |
3030 | bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, | |
3031 | unsigned int offset) | |
3032 | { | |
3033 | return in_whitelist(offset); | |
3034 | } |