[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / gtt.h

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Zhi Wang <zhi.a.wang@intel.com>
 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 *    Xiao Zheng <xiao.zheng@intel.com>
 *
 * Contributors:
 *    Min He <min.he@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *
 */

#ifndef _GVT_GTT_H_
#define _GVT_GTT_H_

#include <linux/kernel.h>
#include <linux/kref.h>
#include <linux/mutex.h>
#include <linux/radix-tree.h>

#include "gt/intel_gtt.h"

struct intel_gvt;
struct intel_vgpu;
struct intel_vgpu_mm;

#define I915_GTT_PAGE_SHIFT         12

#define INTEL_GVT_INVALID_ADDR (~0UL)

struct intel_gvt_gtt_entry {
	u64 val64;
	int type;
};

struct intel_gvt_gtt_pte_ops {
	int (*get_entry)(void *pt,
			 struct intel_gvt_gtt_entry *e,
			 unsigned long index,
			 bool hypervisor_access,
			 unsigned long gpa,
			 struct intel_vgpu *vgpu);
	int (*set_entry)(void *pt,
			 struct intel_gvt_gtt_entry *e,
			 unsigned long index,
			 bool hypervisor_access,
			 unsigned long gpa,
			 struct intel_vgpu *vgpu);
	bool (*test_present)(struct intel_gvt_gtt_entry *e);
	void (*clear_present)(struct intel_gvt_gtt_entry *e);
	void (*set_present)(struct intel_gvt_gtt_entry *e);
	bool (*test_pse)(struct intel_gvt_gtt_entry *e);
	void (*clear_pse)(struct intel_gvt_gtt_entry *e);
	bool (*test_ips)(struct intel_gvt_gtt_entry *e);
	void (*clear_ips)(struct intel_gvt_gtt_entry *e);
	bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
	void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e);
	void (*set_64k_splited)(struct intel_gvt_gtt_entry *e);
	void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
	unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
};

struct intel_gvt_gtt_gma_ops {
	unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma);
	unsigned long (*gma_to_pte_index)(unsigned long gma);
	unsigned long (*gma_to_pde_index)(unsigned long gma);
	unsigned long (*gma_to_l3_pdp_index)(unsigned long gma);
	unsigned long (*gma_to_l4_pdp_index)(unsigned long gma);
	unsigned long (*gma_to_pml4_index)(unsigned long gma);
};

struct intel_gvt_gtt {
	const struct intel_gvt_gtt_pte_ops *pte_ops;
	const struct intel_gvt_gtt_gma_ops *gma_ops;
	int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
	struct list_head oos_page_use_list_head;
	struct list_head oos_page_free_list_head;
	struct mutex ppgtt_mm_lock;
	struct list_head ppgtt_mm_lru_list_head;

	struct page *scratch_page;
	unsigned long scratch_mfn;
};

enum intel_gvt_gtt_type {
	GTT_TYPE_INVALID = 0,

	GTT_TYPE_GGTT_PTE,

	GTT_TYPE_PPGTT_PTE_4K_ENTRY,
	GTT_TYPE_PPGTT_PTE_64K_ENTRY,
	GTT_TYPE_PPGTT_PTE_2M_ENTRY,
	GTT_TYPE_PPGTT_PTE_1G_ENTRY,

	GTT_TYPE_PPGTT_PTE_ENTRY,

	GTT_TYPE_PPGTT_PDE_ENTRY,
	GTT_TYPE_PPGTT_PDP_ENTRY,
	GTT_TYPE_PPGTT_PML4_ENTRY,

	GTT_TYPE_PPGTT_ROOT_ENTRY,

	GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
	GTT_TYPE_PPGTT_ROOT_L4_ENTRY,

	GTT_TYPE_PPGTT_ENTRY,

	GTT_TYPE_PPGTT_PTE_PT,
	GTT_TYPE_PPGTT_PDE_PT,
	GTT_TYPE_PPGTT_PDP_PT,
	GTT_TYPE_PPGTT_PML4_PT,

	GTT_TYPE_MAX,
};

enum intel_gvt_mm_type {
	INTEL_GVT_MM_GGTT,
	INTEL_GVT_MM_PPGTT,
};

#define GVT_RING_CTX_NR_PDPS	GEN8_3LVL_PDPES

struct intel_gvt_partial_pte {
	unsigned long offset;
	u64 data;
	struct list_head list;
};

struct intel_vgpu_mm {
	enum intel_gvt_mm_type type;
	struct intel_vgpu *vgpu;

	struct kref ref;
	atomic_t pincount;

	union {
		struct {
			enum intel_gvt_gtt_type root_entry_type;
			/*
			 * The 4 PDPs in ring context. For 48bit addressing,
			 * only PDP0 is valid and point to PML4. For 32it
			 * addressing, all 4 are used as true PDPs.
			 */
			u64 guest_pdps[GVT_RING_CTX_NR_PDPS];
			u64 shadow_pdps[GVT_RING_CTX_NR_PDPS];
			bool shadowed;

			struct list_head list;
			struct list_head lru_list;
			struct list_head link; /* possible LRI shadow mm list */
		} ppgtt_mm;
		struct {
			void *virtual_ggtt;
			/* Save/restore for PM */
			u64 *host_ggtt_aperture;
			u64 *host_ggtt_hidden;
			struct list_head partial_pte_list;
		} ggtt_mm;
	};
};

struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
		enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);

static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm)
{
	kref_get(&mm->ref);
}

void _intel_vgpu_mm_release(struct kref *mm_ref);

static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm)
{
	kref_put(&mm->ref, _intel_vgpu_mm_release);
}

static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm)
{
	intel_vgpu_mm_put(mm);
}

struct intel_vgpu_guest_page;

struct intel_vgpu_scratch_pt {
	struct page *page;
	unsigned long page_mfn;
};

struct intel_vgpu_gtt {
	struct intel_vgpu_mm *ggtt_mm;
	unsigned long active_ppgtt_mm_bitmap;
	struct list_head ppgtt_mm_list_head;
	struct radix_tree_root spt_tree;
	struct list_head oos_page_list_head;
	struct list_head post_shadow_list_head;
	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
};

int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);

int intel_gvt_init_gtt(struct intel_gvt *gvt);
void intel_gvt_clean_gtt(struct intel_gvt *gvt);

struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
					      int page_table_level,
					      void *root_entry);

struct intel_vgpu_oos_page {
	struct intel_vgpu_ppgtt_spt *spt;
	struct list_head list;
	struct list_head vm_list;
	int id;
	void *mem;
};

#define GTT_ENTRY_NUM_IN_ONE_PAGE 512

/* Represent a vgpu shadow page table. */
struct intel_vgpu_ppgtt_spt {
	atomic_t refcount;
	struct intel_vgpu *vgpu;

	struct {
		enum intel_gvt_gtt_type type;
		bool pde_ips; /* for 64KB PTEs */
		void *vaddr;
		struct page *page;
		unsigned long mfn;
	} shadow_page;

	struct {
		enum intel_gvt_gtt_type type;
		bool pde_ips; /* for 64KB PTEs */
		unsigned long gfn;
		unsigned long write_cnt;
		struct intel_vgpu_oos_page *oos_page;
	} guest_page;

	DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE);
	struct list_head post_shadow_list;
};

int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu);

int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu);

int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm);

void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm);

unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm,
		unsigned long gma);

struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
		u64 pdps[]);

struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
		enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);

int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]);

int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
	unsigned int off, void *p_data, unsigned int bytes);

int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
	unsigned int off, void *p_data, unsigned int bytes);

void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu);
void intel_gvt_restore_ggtt(struct intel_gvt *gvt);

#endif /* _GVT_GTT_H_ */
Commit	Line	Data
2707e444 ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Zhi Wang <zhi.a.wang@intel.com>
	25	* Zhenyu Wang <zhenyuw@linux.intel.com>
	26	* Xiao Zheng <xiao.zheng@intel.com>
	27	*
	28	* Contributors:
	29	* Min He <min.he@intel.com>
	30	* Bing Niu <bing.niu@intel.com>
	31	*
	32	*/
	33
	34	#ifndef _GVT_GTT_H_
	35	#define _GVT_GTT_H_
	36
33a357da JN	37	#include <linux/kernel.h>
	38	#include <linux/kref.h>
	39	#include <linux/mutex.h>
	40	#include <linux/radix-tree.h>
	41
	42	#include "gt/intel_gtt.h"
2707e444	43
33a357da JN	44	struct intel_gvt;
33a357da JN	45	struct intel_vgpu;
2707e444 ZW	46	struct intel_vgpu_mm;
2707e444 ZW	47
33a357da JN	48	#define I915_GTT_PAGE_SHIFT 12
33a357da JN	49
2707e444 ZW	50	#define INTEL_GVT_INVALID_ADDR (~0UL)
	51
	52	struct intel_gvt_gtt_entry {
	53	u64 val64;
	54	int type;
	55	};
	56
	57	struct intel_gvt_gtt_pte_ops {
4b2dbbc2 CD	58	int (get_entry)(void pt,
	59	struct intel_gvt_gtt_entry *e,
	60	unsigned long index,
	61	bool hypervisor_access,
	62	unsigned long gpa,
	63	struct intel_vgpu *vgpu);
	64	int (set_entry)(void pt,
	65	struct intel_gvt_gtt_entry *e,
	66	unsigned long index,
	67	bool hypervisor_access,
	68	unsigned long gpa,
	69	struct intel_vgpu *vgpu);
2707e444 ZW	70	bool (test_present)(struct intel_gvt_gtt_entry e);
2707e444 ZW	71	void (clear_present)(struct intel_gvt_gtt_entry e);
655c64ef	72	void (set_present)(struct intel_gvt_gtt_entry e);
2707e444	73	bool (test_pse)(struct intel_gvt_gtt_entry e);
c3e69763	74	void (clear_pse)(struct intel_gvt_gtt_entry e);
6fd79378 CD	75	bool (test_ips)(struct intel_gvt_gtt_entry e);
6fd79378 CD	76	void (clear_ips)(struct intel_gvt_gtt_entry e);
71634848 CD	77	bool (test_64k_splited)(struct intel_gvt_gtt_entry e);
	78	void (clear_64k_splited)(struct intel_gvt_gtt_entry e);
	79	void (set_64k_splited)(struct intel_gvt_gtt_entry e);
2707e444 ZW	80	void (set_pfn)(struct intel_gvt_gtt_entry e, unsigned long pfn);
	81	unsigned long (get_pfn)(struct intel_gvt_gtt_entry e);
	82	};
	83
	84	struct intel_gvt_gtt_gma_ops {
	85	unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma);
	86	unsigned long (*gma_to_pte_index)(unsigned long gma);
	87	unsigned long (*gma_to_pde_index)(unsigned long gma);
	88	unsigned long (*gma_to_l3_pdp_index)(unsigned long gma);
	89	unsigned long (*gma_to_l4_pdp_index)(unsigned long gma);
	90	unsigned long (*gma_to_pml4_index)(unsigned long gma);
	91	};
	92
	93	struct intel_gvt_gtt {
5512445c	94	const struct intel_gvt_gtt_pte_ops *pte_ops;
c41aadd2	95	const struct intel_gvt_gtt_gma_ops *gma_ops;
2707e444 ZW	96	int (mm_alloc_page_table)(struct intel_vgpu_mm mm);
	97	void (mm_free_page_table)(struct intel_vgpu_mm mm);
	98	struct list_head oos_page_use_list_head;
	99	struct list_head oos_page_free_list_head;
72aabfb8	100	struct mutex ppgtt_mm_lock;
ede9d0cf	101	struct list_head ppgtt_mm_lru_list_head;
d650ac06	102
22115cef ZW	103	struct page *scratch_page;
22115cef ZW	104	unsigned long scratch_mfn;
2707e444 ZW	105	};
2707e444 ZW	106
0cf8f58d AG	107	enum intel_gvt_gtt_type {
0cf8f58d AG	108	GTT_TYPE_INVALID = 0,
3b6411c2 PG	109
	110	GTT_TYPE_GGTT_PTE,
	111
	112	GTT_TYPE_PPGTT_PTE_4K_ENTRY,
b294657d	113	GTT_TYPE_PPGTT_PTE_64K_ENTRY,
3b6411c2 PG	114	GTT_TYPE_PPGTT_PTE_2M_ENTRY,
	115	GTT_TYPE_PPGTT_PTE_1G_ENTRY,
	116
	117	GTT_TYPE_PPGTT_PTE_ENTRY,
	118
	119	GTT_TYPE_PPGTT_PDE_ENTRY,
	120	GTT_TYPE_PPGTT_PDP_ENTRY,
	121	GTT_TYPE_PPGTT_PML4_ENTRY,
	122
	123	GTT_TYPE_PPGTT_ROOT_ENTRY,
	124
	125	GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
	126	GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
	127
	128	GTT_TYPE_PPGTT_ENTRY,
	129
	130	GTT_TYPE_PPGTT_PTE_PT,
	131	GTT_TYPE_PPGTT_PDE_PT,
	132	GTT_TYPE_PPGTT_PDP_PT,
	133	GTT_TYPE_PPGTT_PML4_PT,
	134
	135	GTT_TYPE_MAX,
0cf8f58d	136	};
3b6411c2	137
ede9d0cf CD	138	enum intel_gvt_mm_type {
	139	INTEL_GVT_MM_GGTT,
	140	INTEL_GVT_MM_PPGTT,
	141	};
2707e444	142
ede9d0cf	143	#define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES
2707e444	144
bc0686ff HY	145	struct intel_gvt_partial_pte {
	146	unsigned long offset;
	147	u64 data;
	148	struct list_head list;
	149	};
	150
ede9d0cf CD	151	struct intel_vgpu_mm {
	152	enum intel_gvt_mm_type type;
	153	struct intel_vgpu *vgpu;
2707e444	154
2707e444 ZW	155	struct kref ref;
2707e444 ZW	156	atomic_t pincount;
ede9d0cf CD	157
	158	union {
	159	struct {
0cf8f58d	160	enum intel_gvt_gtt_type root_entry_type;
ede9d0cf CD	161	/*
	162	* The 4 PDPs in ring context. For 48bit addressing,
	163	* only PDP0 is valid and point to PML4. For 32it
	164	* addressing, all 4 are used as true PDPs.
	165	*/
	166	u64 guest_pdps[GVT_RING_CTX_NR_PDPS];
	167	u64 shadow_pdps[GVT_RING_CTX_NR_PDPS];
	168	bool shadowed;
	169
	170	struct list_head list;
	171	struct list_head lru_list;
bec3df93	172	struct list_head link; /* possible LRI shadow mm list */
ede9d0cf CD	173	} ppgtt_mm;
	174	struct {
	175	void *virtual_ggtt;
5f60b12e CX	176	/* Save/restore for PM */
	177	u64 *host_ggtt_aperture;
	178	u64 *host_ggtt_hidden;
bc0686ff	179	struct list_head partial_pte_list;
ede9d0cf CD	180	} ggtt_mm;
ede9d0cf CD	181	};
2707e444 ZW	182	};
2707e444 ZW	183
ede9d0cf	184	struct intel_vgpu_mm intel_vgpu_create_ppgtt_mm(struct intel_vgpu vgpu,
0cf8f58d	185	enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);
1bc25851 CD	186
	187	static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm)
	188	{
	189	kref_get(&mm->ref);
	190	}
	191
	192	void _intel_vgpu_mm_release(struct kref *mm_ref);
	193
	194	static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm)
	195	{
	196	kref_put(&mm->ref, _intel_vgpu_mm_release);
	197	}
	198
	199	static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm)
	200	{
	201	intel_vgpu_mm_put(mm);
	202	}
2707e444 ZW	203
	204	struct intel_vgpu_guest_page;
	205
5c35258d	206	struct intel_vgpu_scratch_pt {
3b6411c2	207	struct page *page;
5c35258d	208	unsigned long page_mfn;
3b6411c2 PG	209	};
3b6411c2 PG	210
2707e444 ZW	211	struct intel_vgpu_gtt {
	212	struct intel_vgpu_mm *ggtt_mm;
	213	unsigned long active_ppgtt_mm_bitmap;
ede9d0cf	214	struct list_head ppgtt_mm_list_head;
b6c126a3	215	struct radix_tree_root spt_tree;
2707e444 ZW	216	struct list_head oos_page_list_head;
2707e444 ZW	217	struct list_head post_shadow_list_head;
5c35258d	218	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
2707e444 ZW	219	};
2707e444 ZW	220
b5893ffc JK	221	int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
b5893ffc JK	222	void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
f4c43db3	223	void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
730c8ead	224	void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
2707e444	225
b5893ffc	226	int intel_gvt_init_gtt(struct intel_gvt *gvt);
b5893ffc	227	void intel_gvt_clean_gtt(struct intel_gvt *gvt);
2707e444	228
b5893ffc JK	229	struct intel_vgpu_mm intel_gvt_find_ppgtt_mm(struct intel_vgpu vgpu,
	230	int page_table_level,
	231	void *root_entry);
2707e444	232
2707e444	233	struct intel_vgpu_oos_page {
44b46733	234	struct intel_vgpu_ppgtt_spt *spt;
2707e444 ZW	235	struct list_head list;
	236	struct list_head vm_list;
	237	int id;
ed47c5cb	238	void *mem;
2707e444 ZW	239	};
	240
	241	#define GTT_ENTRY_NUM_IN_ONE_PAGE 512
	242
44b46733	243	/* Represent a vgpu shadow page table. */
2707e444	244	struct intel_vgpu_ppgtt_spt {
2707e444 ZW	245	atomic_t refcount;
2707e444 ZW	246	struct intel_vgpu *vgpu;
44b46733 CD	247
44b46733 CD	248	struct {
0cf8f58d	249	enum intel_gvt_gtt_type type;
40b27176	250	bool pde_ips; /* for 64KB PTEs */
44b46733 CD	251	void *vaddr;
	252	struct page *page;
	253	unsigned long mfn;
	254	} shadow_page;
	255
	256	struct {
0cf8f58d	257	enum intel_gvt_gtt_type type;
40b27176	258	bool pde_ips; /* for 64KB PTEs */
44b46733 CD	259	unsigned long gfn;
44b46733 CD	260	unsigned long write_cnt;
44b46733 CD	261	struct intel_vgpu_oos_page *oos_page;
	262	} guest_page;
	263
2707e444 ZW	264	DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE);
	265	struct list_head post_shadow_list;
	266	};
	267
2707e444 ZW	268	int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu);
	269
	270	int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu);
	271
2707e444 ZW	272	int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm);
	273
	274	void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm);
	275
	276	unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm,
	277	unsigned long gma);
	278
	279	struct intel_vgpu_mm intel_vgpu_find_ppgtt_mm(struct intel_vgpu vgpu,
ede9d0cf	280	u64 pdps[]);
2707e444	281
e6e9c46f	282	struct intel_vgpu_mm intel_vgpu_get_ppgtt_mm(struct intel_vgpu vgpu,
0cf8f58d	283	enum intel_gvt_gtt_type root_entry_type, u64 pdps[]);
2707e444	284
e6e9c46f	285	int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]);
2707e444	286
a143cef7	287	int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
2707e444 ZW	288	unsigned int off, void *p_data, unsigned int bytes);
2707e444 ZW	289
a143cef7	290	int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
2707e444 ZW	291	unsigned int off, void *p_data, unsigned int bytes);
2707e444 ZW	292
ba25d977	293	void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu);
5f60b12e	294	void intel_gvt_restore_ggtt(struct intel_gvt *gvt);
ba25d977	295
2707e444	296	#endif /* _GVT_GTT_H_ */