[linux-block.git] / drivers / gpu / drm / i915 / gvt / fb_decoder.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Kevin Tian <kevin.tian@intel.com>
 *
 * Contributors:
 *    Bing Niu <bing.niu@intel.com>
 *    Xu Han <xu.han@intel.com>
 *    Ping Gao <ping.a.gao@intel.com>
 *    Xiaoguang Chen <xiaoguang.chen@intel.com>
 *    Yang Liu <yang2.liu@intel.com>
 *    Tina Zhang <tina.zhang@intel.com>
 *
 */

#include <uapi/drm/drm_fourcc.h>
#include "i915_drv.h"
#include "gvt.h"

#define PRIMARY_FORMAT_NUM	16
struct pixel_format {
	int	drm_format;	/* Pixel format in DRM definition */
	int	bpp;		/* Bits per pixel, 0 indicates invalid */
	char	*desc;		/* The description */
};

static struct pixel_format bdw_pixel_formats[] = {
	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},

	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},

	/* non-supported format has bpp default to 0 */
	{0, 0, NULL},
};

static struct pixel_format skl_pixel_formats[] = {
	{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
	{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
	{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
	{DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},

	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
	{DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},

	{DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},

	/* non-supported format has bpp default to 0 */
	{0, 0, NULL},
};

static int bdw_format_to_drm(int format)
{
	int bdw_pixel_formats_index = 6;

	switch (format) {
	case DISPPLANE_8BPP:
		bdw_pixel_formats_index = 0;
		break;
	case DISPPLANE_BGRX565:
		bdw_pixel_formats_index = 1;
		break;
	case DISPPLANE_BGRX888:
		bdw_pixel_formats_index = 2;
		break;
	case DISPPLANE_RGBX101010:
		bdw_pixel_formats_index = 3;
		break;
	case DISPPLANE_BGRX101010:
		bdw_pixel_formats_index = 4;
		break;
	case DISPPLANE_RGBX888:
		bdw_pixel_formats_index = 5;
		break;

	default:
		break;
	}

	return bdw_pixel_formats_index;
}

static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
	int yuv_order)
{
	int skl_pixel_formats_index = 12;

	switch (format) {
	case PLANE_CTL_FORMAT_INDEXED:
		skl_pixel_formats_index = 4;
		break;
	case PLANE_CTL_FORMAT_RGB_565:
		skl_pixel_formats_index = 5;
		break;
	case PLANE_CTL_FORMAT_XRGB_8888:
		if (rgb_order)
			skl_pixel_formats_index = alpha ? 6 : 7;
		else
			skl_pixel_formats_index = alpha ? 8 : 9;
		break;
	case PLANE_CTL_FORMAT_XRGB_2101010:
		skl_pixel_formats_index = rgb_order ? 10 : 11;
		break;
	case PLANE_CTL_FORMAT_YUV422:
		skl_pixel_formats_index = yuv_order >> 16;
		if (skl_pixel_formats_index > 3)
			return -EINVAL;
		break;

	default:
		break;
	}

	return skl_pixel_formats_index;
}

static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
	u32 tiled, int stride_mask, int bpp)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
	u32 stride = stride_reg;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
		switch (tiled) {
		case PLANE_CTL_TILED_LINEAR:
			stride = stride_reg * 64;
			break;
		case PLANE_CTL_TILED_X:
			stride = stride_reg * 512;
			break;
		case PLANE_CTL_TILED_Y:
			stride = stride_reg * 128;
			break;
		case PLANE_CTL_TILED_YF:
			if (bpp == 8)
				stride = stride_reg * 64;
			else if (bpp == 16 || bpp == 32 || bpp == 64)
				stride = stride_reg * 128;
			else
				gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
			break;
		default:
			gvt_dbg_core("skl: unsupported tile format:%x\n",
				tiled);
		}
	}

	return stride;
}

static int get_active_pipe(struct intel_vgpu *vgpu)
{
	int i;

	for (i = 0; i < I915_MAX_PIPES; i++)
		if (pipe_is_enabled(vgpu, i))
			break;

	return i;
}

/**
 * intel_vgpu_decode_primary_plane - Decode primary plane
 * @vgpu: input vgpu
 * @plane: primary plane to save decoded info
 * This function is called for decoding plane
 *
 * Returns:
 * 0 on success, non-zero if failed.
 */
int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
	struct intel_vgpu_primary_plane_format *plane)
{
	u32 val, fmt;
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	int pipe;

	pipe = get_active_pipe(vgpu);
	if (pipe >= I915_MAX_PIPES)
		return -ENODEV;

	val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
	plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
	if (!plane->enabled)
		return -ENODEV;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
		plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
		_PLANE_CTL_TILED_SHIFT;
		fmt = skl_format_to_drm(
			val & PLANE_CTL_FORMAT_MASK,
			val & PLANE_CTL_ORDER_RGBX,
			val & PLANE_CTL_ALPHA_MASK,
			val & PLANE_CTL_YUV422_ORDER_MASK);

		if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
			gvt_vgpu_err("Out-of-bounds pixel format index\n");
			return -EINVAL;
		}

		plane->bpp = skl_pixel_formats[fmt].bpp;
		plane->drm_format = skl_pixel_formats[fmt].drm_format;
	} else {
		plane->tiled = !!(val & DISPPLANE_TILED);
		fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
		plane->bpp = bdw_pixel_formats[fmt].bpp;
		plane->drm_format = bdw_pixel_formats[fmt].drm_format;
	}

	if (!plane->bpp) {
		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
		return -EINVAL;
	}

	plane->hw_format = fmt;

	plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
		return  -EINVAL;

	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
		gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
				plane->base);
		return  -EINVAL;
	}

	plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
		(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ?
			(_PRI_PLANE_STRIDE_MASK >> 6) :
				_PRI_PLANE_STRIDE_MASK, plane->bpp);

	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
		_PIPE_H_SRCSZ_SHIFT;
	plane->width += 1;
	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
			_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
	plane->height += 1;	/* raw height is one minus the real value */

	val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
		_PRI_PLANE_X_OFF_SHIFT;
	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
		_PRI_PLANE_Y_OFF_SHIFT;

	return 0;
}

#define CURSOR_FORMAT_NUM	(1 << 6)
struct cursor_mode_format {
	int	drm_format;	/* Pixel format in DRM definition */
	u8	bpp;		/* Bits per pixel; 0 indicates invalid */
	u32	width;		/* In pixel */
	u32	height;		/* In lines */
	char	*desc;		/* The description */
};

static struct cursor_mode_format cursor_pixel_formats[] = {
	{DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
	{DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},

	/* non-supported format has bpp default to 0 */
	{0, 0, 0, 0, NULL},
};

static int cursor_mode_to_drm(int mode)
{
	int cursor_pixel_formats_index = 4;

	switch (mode) {
	case CURSOR_MODE_128_ARGB_AX:
		cursor_pixel_formats_index = 0;
		break;
	case CURSOR_MODE_256_ARGB_AX:
		cursor_pixel_formats_index = 1;
		break;
	case CURSOR_MODE_64_ARGB_AX:
		cursor_pixel_formats_index = 2;
		break;
	case CURSOR_MODE_64_32B_AX:
		cursor_pixel_formats_index = 3;
		break;

	default:
		break;
	}

	return cursor_pixel_formats_index;
}

/**
 * intel_vgpu_decode_cursor_plane - Decode sprite plane
 * @vgpu: input vgpu
 * @plane: cursor plane to save decoded info
 * This function is called for decoding plane
 *
 * Returns:
 * 0 on success, non-zero if failed.
 */
int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
	struct intel_vgpu_cursor_plane_format *plane)
{
	u32 val, mode, index;
	u32 alpha_plane, alpha_force;
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	int pipe;

	pipe = get_active_pipe(vgpu);
	if (pipe >= I915_MAX_PIPES)
		return -ENODEV;

	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
	mode = val & CURSOR_MODE;
	plane->enabled = (mode != CURSOR_MODE_DISABLE);
	if (!plane->enabled)
		return -ENODEV;

	index = cursor_mode_to_drm(mode);

	if (!cursor_pixel_formats[index].bpp) {
		gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
		return -EINVAL;
	}
	plane->mode = mode;
	plane->bpp = cursor_pixel_formats[index].bpp;
	plane->drm_format = cursor_pixel_formats[index].drm_format;
	plane->width = cursor_pixel_formats[index].width;
	plane->height = cursor_pixel_formats[index].height;

	alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
				_CURSOR_ALPHA_PLANE_SHIFT;
	alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
				_CURSOR_ALPHA_FORCE_SHIFT;
	if (alpha_plane || alpha_force)
		gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
			alpha_plane, alpha_force);

	plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
		return  -EINVAL;

	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
		gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
				plane->base);
		return  -EINVAL;
	}

	val = vgpu_vreg_t(vgpu, CURPOS(pipe));
	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;

	return 0;
}

#define SPRITE_FORMAT_NUM	(1 << 3)

static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
	[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
	[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
	[0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
	[0x4] = {DRM_FORMAT_AYUV, 32,
		"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
};

/**
 * intel_vgpu_decode_sprite_plane - Decode sprite plane
 * @vgpu: input vgpu
 * @plane: sprite plane to save decoded info
 * This function is called for decoding plane
 *
 * Returns:
 * 0 on success, non-zero if failed.
 */
int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
	struct intel_vgpu_sprite_plane_format *plane)
{
	u32 val, fmt;
	u32 color_order, yuv_order;
	int drm_format;
	int pipe;

	pipe = get_active_pipe(vgpu);
	if (pipe >= I915_MAX_PIPES)
		return -ENODEV;

	val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
	plane->enabled = !!(val & SPRITE_ENABLE);
	if (!plane->enabled)
		return -ENODEV;

	plane->tiled = !!(val & SPRITE_TILED);
	color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
	yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
				_SPRITE_YUV_ORDER_SHIFT;

	fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
	if (!sprite_pixel_formats[fmt].bpp) {
		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
		return -EINVAL;
	}
	plane->hw_format = fmt;
	plane->bpp = sprite_pixel_formats[fmt].bpp;
	drm_format = sprite_pixel_formats[fmt].drm_format;

	/* Order of RGB values in an RGBxxx buffer may be ordered RGB or
	 * BGR depending on the state of the color_order field
	 */
	if (!color_order) {
		if (drm_format == DRM_FORMAT_XRGB2101010)
			drm_format = DRM_FORMAT_XBGR2101010;
		else if (drm_format == DRM_FORMAT_XRGB8888)
			drm_format = DRM_FORMAT_XBGR8888;
	}

	if (drm_format == DRM_FORMAT_YUV422) {
		switch (yuv_order) {
		case 0:
			drm_format = DRM_FORMAT_YUYV;
			break;
		case 1:
			drm_format = DRM_FORMAT_UYVY;
			break;
		case 2:
			drm_format = DRM_FORMAT_YVYU;
			break;
		case 3:
			drm_format = DRM_FORMAT_VYUY;
			break;
		default:
			/* yuv_order has only 2 bits */
			break;
		}
	}

	plane->drm_format = drm_format;

	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
		return  -EINVAL;

	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
		gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
				plane->base);
		return  -EINVAL;
	}

	plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
				_SPRITE_STRIDE_MASK;

	val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
		_SPRITE_SIZE_HEIGHT_SHIFT;
	plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
		_SPRITE_SIZE_WIDTH_SHIFT;
	plane->height += 1;	/* raw height is one minus the real value */
	plane->width += 1;	/* raw width is one minus the real value */

	val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
	plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
	plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;

	val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
	plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
			   _SPRITE_OFFSET_START_X_SHIFT;
	plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
			   _SPRITE_OFFSET_START_Y_SHIFT;

	return 0;
}
Commit	Line	Data
9f31d106 TZ	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Kevin Tian <kevin.tian@intel.com>
	25	*
	26	* Contributors:
	27	* Bing Niu <bing.niu@intel.com>
	28	* Xu Han <xu.han@intel.com>
	29	* Ping Gao <ping.a.gao@intel.com>
	30	* Xiaoguang Chen <xiaoguang.chen@intel.com>
	31	* Yang Liu <yang2.liu@intel.com>
	32	* Tina Zhang <tina.zhang@intel.com>
	33	*
	34	*/
	35
	36	#include <uapi/drm/drm_fourcc.h>
	37	#include "i915_drv.h"
	38	#include "gvt.h"
	39
	40	#define PRIMARY_FORMAT_NUM 16
	41	struct pixel_format {
	42	int drm_format; /* Pixel format in DRM definition */
	43	int bpp; /* Bits per pixel, 0 indicates invalid */
	44	char desc; / The description */
	45	};
	46
	47	static struct pixel_format bdw_pixel_formats[] = {
	48	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
	49	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
	50	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
	51	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
	52
	53	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
	54	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
	55
	56	/* non-supported format has bpp default to 0 */
	57	{0, 0, NULL},
	58	};
	59
	60	static struct pixel_format skl_pixel_formats[] = {
	61	{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
	62	{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
	63	{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
	64	{DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
65
66	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
67	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
68	{DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
69	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
70
71	{DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
72	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
73	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
74	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
75
76	/* non-supported format has bpp default to 0 */
77	{0, 0, NULL},
78	};
79
80	static int bdw_format_to_drm(int format)
81	{
82	int bdw_pixel_formats_index = 6;
83
84	switch (format) {
85	case DISPPLANE_8BPP:
86	bdw_pixel_formats_index = 0;
87	break;
88	case DISPPLANE_BGRX565:
89	bdw_pixel_formats_index = 1;
90	break;
91	case DISPPLANE_BGRX888:
92	bdw_pixel_formats_index = 2;
93	break;
94	case DISPPLANE_RGBX101010:
95	bdw_pixel_formats_index = 3;
96	break;
97	case DISPPLANE_BGRX101010:
98	bdw_pixel_formats_index = 4;
99	break;
100	case DISPPLANE_RGBX888:
101	bdw_pixel_formats_index = 5;
102	break;
103
104	default:
105	break;
106	}
107
108	return bdw_pixel_formats_index;
109	}
110
111	static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
112	int yuv_order)
113	{
114	int skl_pixel_formats_index = 12;
115
116	switch (format) {
117	case PLANE_CTL_FORMAT_INDEXED:
118	skl_pixel_formats_index = 4;
119	break;
120	case PLANE_CTL_FORMAT_RGB_565:
121	skl_pixel_formats_index = 5;
122	break;
123	case PLANE_CTL_FORMAT_XRGB_8888:
124	if (rgb_order)
125	skl_pixel_formats_index = alpha ? 6 : 7;
126	else
127	skl_pixel_formats_index = alpha ? 8 : 9;
128	break;
129	case PLANE_CTL_FORMAT_XRGB_2101010:
130	skl_pixel_formats_index = rgb_order ? 10 : 11;
131	break;
132	case PLANE_CTL_FORMAT_YUV422:
133	skl_pixel_formats_index = yuv_order >> 16;
134	if (skl_pixel_formats_index > 3)
135	return -EINVAL;
136	break;
137
138	default:
139	break;
140	}
141
142	return skl_pixel_formats_index;
143	}
144
145	static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
146	u32 tiled, int stride_mask, int bpp)
147	{
148	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
149
90551a12	150	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
9f31d106 TZ	151	u32 stride = stride_reg;
9f31d106 TZ	152
4a136d59	153	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) {
9f31d106 TZ	154	switch (tiled) {
	155	case PLANE_CTL_TILED_LINEAR:
	156	stride = stride_reg * 64;
	157	break;
	158	case PLANE_CTL_TILED_X:
	159	stride = stride_reg * 512;
	160	break;
	161	case PLANE_CTL_TILED_Y:
	162	stride = stride_reg * 128;
	163	break;
	164	case PLANE_CTL_TILED_YF:
	165	if (bpp == 8)
	166	stride = stride_reg * 64;
	167	else if (bpp == 16 \|\| bpp == 32 \|\| bpp == 64)
	168	stride = stride_reg * 128;
	169	else
	170	gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
	171	break;
	172	default:
	173	gvt_dbg_core("skl: unsupported tile format:%x\n",
	174	tiled);
	175	}
	176	}
	177
	178	return stride;
	179	}
	180
	181	static int get_active_pipe(struct intel_vgpu *vgpu)
	182	{
	183	int i;
	184
	185	for (i = 0; i < I915_MAX_PIPES; i++)
	186	if (pipe_is_enabled(vgpu, i))
	187	break;
	188
	189	return i;
	190	}
	191
	192	/**
	193	* intel_vgpu_decode_primary_plane - Decode primary plane
	194	* @vgpu: input vgpu
	195	* @plane: primary plane to save decoded info
	196	* This function is called for decoding plane
	197	*
	198	* Returns:
	199	* 0 on success, non-zero if failed.
	200	*/
	201	int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
	202	struct intel_vgpu_primary_plane_format *plane)
	203	{
	204	u32 val, fmt;
	205	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	206	int pipe;
	207
	208	pipe = get_active_pipe(vgpu);
	209	if (pipe >= I915_MAX_PIPES)
	210	return -ENODEV;
	211
90551a12	212	val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
9f31d106 TZ	213	plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
	214	if (!plane->enabled)
	215	return -ENODEV;
	216
4a136d59	217	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) {
9f31d106 TZ	218	plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
	219	_PLANE_CTL_TILED_SHIFT;
	220	fmt = skl_format_to_drm(
	221	val & PLANE_CTL_FORMAT_MASK,
	222	val & PLANE_CTL_ORDER_RGBX,
	223	val & PLANE_CTL_ALPHA_MASK,
	224	val & PLANE_CTL_YUV422_ORDER_MASK);
461bd622 GS	225
	226	if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
	227	gvt_vgpu_err("Out-of-bounds pixel format index\n");
	228	return -EINVAL;
	229	}
	230
9f31d106 TZ	231	plane->bpp = skl_pixel_formats[fmt].bpp;
	232	plane->drm_format = skl_pixel_formats[fmt].drm_format;
	233	} else {
	234	plane->tiled = !!(val & DISPPLANE_TILED);
	235	fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
	236	plane->bpp = bdw_pixel_formats[fmt].bpp;
	237	plane->drm_format = bdw_pixel_formats[fmt].drm_format;
	238	}
	239
	240	if (!plane->bpp) {
	241	gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
	242	return -EINVAL;
	243	}
	244
	245	plane->hw_format = fmt;
	246
90551a12	247	plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
a733390f	248	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
9f31d106	249	return -EINVAL;
9f31d106 TZ	250
	251	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
	252	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
a733390f XZ	253	gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
a733390f XZ	254	plane->base);
9f31d106 TZ	255	return -EINVAL;
	256	}
	257
	258	plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
4a136d59 TZ	259	(IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) ?
	260	(_PRI_PLANE_STRIDE_MASK >> 6) :
	261	_PRI_PLANE_STRIDE_MASK, plane->bpp);
9f31d106	262
90551a12	263	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
9f31d106 TZ	264	_PIPE_H_SRCSZ_SHIFT;
9f31d106 TZ	265	plane->width += 1;
90551a12	266	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
9f31d106 TZ	267	_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
	268	plane->height += 1; /* raw height is one minus the real value */
	269
90551a12	270	val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
9f31d106 TZ	271	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
	272	_PRI_PLANE_X_OFF_SHIFT;
	273	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
	274	_PRI_PLANE_Y_OFF_SHIFT;
	275
	276	return 0;
	277	}
	278
	279	#define CURSOR_FORMAT_NUM (1 << 6)
	280	struct cursor_mode_format {
	281	int drm_format; /* Pixel format in DRM definition */
	282	u8 bpp; /* Bits per pixel; 0 indicates invalid */
	283	u32 width; /* In pixel */
	284	u32 height; /* In lines */
	285	char desc; / The description */
	286	};
	287
	288	static struct cursor_mode_format cursor_pixel_formats[] = {
	289	{DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
	290	{DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
	291	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
	292	{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
	293
	294	/* non-supported format has bpp default to 0 */
	295	{0, 0, 0, 0, NULL},
	296	};
	297
	298	static int cursor_mode_to_drm(int mode)
	299	{
	300	int cursor_pixel_formats_index = 4;
	301
	302	switch (mode) {
	303	case CURSOR_MODE_128_ARGB_AX:
	304	cursor_pixel_formats_index = 0;
	305	break;
	306	case CURSOR_MODE_256_ARGB_AX:
	307	cursor_pixel_formats_index = 1;
	308	break;
	309	case CURSOR_MODE_64_ARGB_AX:
	310	cursor_pixel_formats_index = 2;
	311	break;
	312	case CURSOR_MODE_64_32B_AX:
	313	cursor_pixel_formats_index = 3;
	314	break;
	315
	316	default:
	317	break;
	318	}
	319
	320	return cursor_pixel_formats_index;
	321	}
	322
	323	/**
	324	* intel_vgpu_decode_cursor_plane - Decode sprite plane
	325	* @vgpu: input vgpu
	326	* @plane: cursor plane to save decoded info
	327	* This function is called for decoding plane
	328	*
	329	* Returns:
	330	* 0 on success, non-zero if failed.
	331	*/
	332	int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
	333	struct intel_vgpu_cursor_plane_format *plane)
	334	{
335	u32 val, mode, index;
336	u32 alpha_plane, alpha_force;
337	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
338	int pipe;
339
340	pipe = get_active_pipe(vgpu);
341	if (pipe >= I915_MAX_PIPES)
342	return -ENODEV;
343
90551a12	344	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
9f31d106 TZ	345	mode = val & CURSOR_MODE;
	346	plane->enabled = (mode != CURSOR_MODE_DISABLE);
	347	if (!plane->enabled)
	348	return -ENODEV;
	349
	350	index = cursor_mode_to_drm(mode);
	351
	352	if (!cursor_pixel_formats[index].bpp) {
	353	gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
	354	return -EINVAL;
	355	}
	356	plane->mode = mode;
	357	plane->bpp = cursor_pixel_formats[index].bpp;
	358	plane->drm_format = cursor_pixel_formats[index].drm_format;
	359	plane->width = cursor_pixel_formats[index].width;
	360	plane->height = cursor_pixel_formats[index].height;
	361
	362	alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
	363	_CURSOR_ALPHA_PLANE_SHIFT;
	364	alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
	365	_CURSOR_ALPHA_FORCE_SHIFT;
	366	if (alpha_plane \|\| alpha_force)
	367	gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
	368	alpha_plane, alpha_force);
	369
90551a12	370	plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
a733390f	371	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
9f31d106	372	return -EINVAL;
9f31d106 TZ	373
	374	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
	375	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
a733390f XZ	376	gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
a733390f XZ	377	plane->base);
9f31d106 TZ	378	return -EINVAL;
	379	}
	380
90551a12	381	val = vgpu_vreg_t(vgpu, CURPOS(pipe));
9f31d106 TZ	382	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
	383	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
	384	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
	385	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
	386
	387	return 0;
	388	}
	389
	390	#define SPRITE_FORMAT_NUM (1 << 3)
	391
	392	static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
	393	[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
	394	[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
	395	[0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
	396	[0x4] = {DRM_FORMAT_AYUV, 32,
	397	"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
	398	};
	399
	400	/**
	401	* intel_vgpu_decode_sprite_plane - Decode sprite plane
	402	* @vgpu: input vgpu
	403	* @plane: sprite plane to save decoded info
	404	* This function is called for decoding plane
	405	*
	406	* Returns:
	407	* 0 on success, non-zero if failed.
	408	*/
	409	int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
	410	struct intel_vgpu_sprite_plane_format *plane)
	411	{
	412	u32 val, fmt;
	413	u32 color_order, yuv_order;
	414	int drm_format;
	415	int pipe;
	416
	417	pipe = get_active_pipe(vgpu);
	418	if (pipe >= I915_MAX_PIPES)
	419	return -ENODEV;
	420
90551a12	421	val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
9f31d106 TZ	422	plane->enabled = !!(val & SPRITE_ENABLE);
	423	if (!plane->enabled)
	424	return -ENODEV;
	425
	426	plane->tiled = !!(val & SPRITE_TILED);
	427	color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
	428	yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
	429	_SPRITE_YUV_ORDER_SHIFT;
	430
	431	fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
	432	if (!sprite_pixel_formats[fmt].bpp) {
	433	gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
	434	return -EINVAL;
	435	}
	436	plane->hw_format = fmt;
	437	plane->bpp = sprite_pixel_formats[fmt].bpp;
	438	drm_format = sprite_pixel_formats[fmt].drm_format;
	439
	440	/* Order of RGB values in an RGBxxx buffer may be ordered RGB or
	441	* BGR depending on the state of the color_order field
	442	*/
	443	if (!color_order) {
	444	if (drm_format == DRM_FORMAT_XRGB2101010)
	445	drm_format = DRM_FORMAT_XBGR2101010;
	446	else if (drm_format == DRM_FORMAT_XRGB8888)
	447	drm_format = DRM_FORMAT_XBGR8888;
	448	}
	449
	450	if (drm_format == DRM_FORMAT_YUV422) {
	451	switch (yuv_order) {
	452	case 0:
	453	drm_format = DRM_FORMAT_YUYV;
	454	break;
	455	case 1:
	456	drm_format = DRM_FORMAT_UYVY;
	457	break;
	458	case 2:
	459	drm_format = DRM_FORMAT_YVYU;
	460	break;
	461	case 3:
	462	drm_format = DRM_FORMAT_VYUY;
	463	break;
	464	default:
	465	/* yuv_order has only 2 bits */
	466	break;
	467	}
	468	}
	469
	470	plane->drm_format = drm_format;
	471
90551a12	472	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
a733390f	473	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
9f31d106	474	return -EINVAL;
9f31d106 TZ	475
	476	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
	477	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
a733390f XZ	478	gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
a733390f XZ	479	plane->base);
9f31d106 TZ	480	return -EINVAL;
	481	}
	482
90551a12	483	plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
9f31d106 TZ	484	_SPRITE_STRIDE_MASK;
9f31d106 TZ	485
90551a12	486	val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
9f31d106 TZ	487	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
	488	_SPRITE_SIZE_HEIGHT_SHIFT;
	489	plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
	490	_SPRITE_SIZE_WIDTH_SHIFT;
	491	plane->height += 1; /* raw height is one minus the real value */
	492	plane->width += 1; /* raw width is one minus the real value */
	493
90551a12	494	val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
9f31d106 TZ	495	plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
	496	plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
	497
90551a12	498	val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
9f31d106 TZ	499	plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
	500	_SPRITE_OFFSET_START_X_SHIFT;
	501	plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
	502	_SPRITE_OFFSET_START_Y_SHIFT;
	503
	504	return 0;
	505	}