[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / display.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Ke Yu
 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
 *
 * Contributors:
 *    Terrence Xu <terrence.xu@intel.com>
 *    Changbin Du <changbin.du@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#include "i915_drv.h"
#include "gvt.h"

static int get_edp_pipe(struct intel_vgpu *vgpu)
{
	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
	int pipe = -1;

	switch (data & TRANS_DDI_EDP_INPUT_MASK) {
	case TRANS_DDI_EDP_INPUT_A_ON:
	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		pipe = PIPE_A;
		break;
	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		pipe = PIPE_B;
		break;
	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		pipe = PIPE_C;
		break;
	}
	return pipe;
}

static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
		return 0;

	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
		return 0;
	return 1;
}

static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
		return -EINVAL;

	if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
		return 1;

	if (edp_pipe_is_enabled(vgpu) &&
			get_edp_pipe(vgpu) == pipe)
		return 1;
	return 0;
}

/* EDID with 1024x768 as its resolution */
static unsigned char virtual_dp_monitor_edid[] = {
	/*Header*/
	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
	/* Vendor & Product Identification */
	0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
	/* Version & Revision */
	0x01, 0x04,
	/* Basic Display Parameters & Features */
	0xa5, 0x34, 0x20, 0x78, 0x23,
	/* Color Characteristics */
	0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
	/* Established Timings: maximum resolution is 1024x768 */
	0x21, 0x08, 0x00,
	/* Standard Timings. All invalid */
	0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
	0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
	/* 18 Byte Data Blocks 1: invalid */
	0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
	0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
	/* 18 Byte Data Blocks 2: invalid */
	0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
	0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
	/* 18 Byte Data Blocks 3: invalid */
	0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
	0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
	/* 18 Byte Data Blocks 4: invalid */
	0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
	0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
	/* Extension Block Count */
	0x00,
	/* Checksum */
	0xef,
};

#define DPCD_HEADER_SIZE        0xb

u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
	0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};

static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
			SDE_PORTC_HOTPLUG_CPT |
			SDE_PORTD_HOTPLUG_CPT);

	if (IS_SKYLAKE(dev_priv))
		vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
				SDE_PORTE_HOTPLUG_SPT);

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B))
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C))
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D))
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

	if (IS_SKYLAKE(dev_priv) &&
			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
		if (IS_BROADWELL(dev_priv))
			vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=
				GEN8_PORT_DP_A_HOTPLUG;
		else
			vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
	}
}

static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
{
	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);

	kfree(port->edid);
	port->edid = NULL;

	kfree(port->dpcd);
	port->dpcd = NULL;
}

static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
		int type)
{
	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);

	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
	if (!port->edid)
		return -ENOMEM;

	port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
	if (!port->dpcd) {
		kfree(port->edid);
		return -ENOMEM;
	}

	memcpy(port->edid->edid_block, virtual_dp_monitor_edid,
			EDID_SIZE);
	port->edid->data_valid = true;

	memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
	port->dpcd->data_valid = true;
	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
	port->type = type;

	emulate_monitor_status_change(vgpu);
	return 0;
}

/**
 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
 * be turned on/off when a virtual pipe is enabled/disabled.
 * @gvt: a GVT device
 *
 * This function is used to turn on/off vblank timer according to currently
 * enabled/disabled virtual pipes.
 *
 */
void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
{
	struct intel_gvt_irq *irq = &gvt->irq;
	struct intel_vgpu *vgpu;
	bool have_enabled_pipe = false;
	int pipe, id;

	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
		return;

	hrtimer_cancel(&irq->vblank_timer.timer);

	for_each_active_vgpu(gvt, vgpu, id) {
		for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
			have_enabled_pipe =
				pipe_is_enabled(vgpu, pipe);
			if (have_enabled_pipe)
				break;
		}
	}

	if (have_enabled_pipe)
		hrtimer_start(&irq->vblank_timer.timer,
			ktime_add_ns(ktime_get(), irq->vblank_timer.period),
			HRTIMER_MODE_ABS);
}

static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	struct intel_vgpu_irq *irq = &vgpu->irq;
	int vblank_event[] = {
		[PIPE_A] = PIPE_A_VBLANK,
		[PIPE_B] = PIPE_B_VBLANK,
		[PIPE_C] = PIPE_C_VBLANK,
	};
	int event;

	if (pipe < PIPE_A || pipe > PIPE_C)
		return;

	for_each_set_bit(event, irq->flip_done_event[pipe],
			INTEL_GVT_EVENT_MAX) {
		clear_bit(event, irq->flip_done_event[pipe]);
		if (!pipe_is_enabled(vgpu, pipe))
			continue;

		vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
		intel_vgpu_trigger_virtual_event(vgpu, event);
	}

	if (pipe_is_enabled(vgpu, pipe)) {
		vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
	}
}

static void emulate_vblank(struct intel_vgpu *vgpu)
{
	int pipe;

	for_each_pipe(vgpu->gvt->dev_priv, pipe)
		emulate_vblank_on_pipe(vgpu, pipe);
}

/**
 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
 * @gvt: a GVT device
 *
 * This function is used to trigger vblank interrupts for vGPUs on GVT device
 *
 */
void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
{
	struct intel_vgpu *vgpu;
	int id;

	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
		return;

	for_each_active_vgpu(gvt, vgpu, id)
		emulate_vblank(vgpu);
}

/**
 * intel_vgpu_clean_display - clean vGPU virtual display emulation
 * @vgpu: a vGPU
 *
 * This function is used to clean vGPU virtual display emulation stuffs
 *
 */
void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	if (IS_SKYLAKE(dev_priv))
		clean_virtual_dp_monitor(vgpu, PORT_D);
	else
		clean_virtual_dp_monitor(vgpu, PORT_B);
}

/**
 * intel_vgpu_init_display- initialize vGPU virtual display emulation
 * @vgpu: a vGPU
 *
 * This function is used to initialize vGPU virtual display emulation stuffs
 *
 * Returns:
 * Zero on success, negative error code if failed.
 *
 */
int intel_vgpu_init_display(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	intel_vgpu_init_i2c_edid(vgpu);

	if (IS_SKYLAKE(dev_priv))
		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D);
	else
		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B);
}
Commit	Line	Data
04d348ae ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Ke Yu
	25	* Zhiyuan Lv <zhiyuan.lv@intel.com>
	26	*
	27	* Contributors:
	28	* Terrence Xu <terrence.xu@intel.com>
	29	* Changbin Du <changbin.du@intel.com>
	30	* Bing Niu <bing.niu@intel.com>
	31	* Zhi Wang <zhi.a.wang@intel.com>
	32	*
	33	*/
	34
	35	#include "i915_drv.h"
feddf6e8	36	#include "gvt.h"
04d348ae ZW	37
	38	static int get_edp_pipe(struct intel_vgpu *vgpu)
	39	{
	40	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
	41	int pipe = -1;
	42
	43	switch (data & TRANS_DDI_EDP_INPUT_MASK) {
	44	case TRANS_DDI_EDP_INPUT_A_ON:
	45	case TRANS_DDI_EDP_INPUT_A_ONOFF:
	46	pipe = PIPE_A;
	47	break;
	48	case TRANS_DDI_EDP_INPUT_B_ONOFF:
	49	pipe = PIPE_B;
	50	break;
	51	case TRANS_DDI_EDP_INPUT_C_ONOFF:
	52	pipe = PIPE_C;
	53	break;
	54	}
	55	return pipe;
	56	}
	57
	58	static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
	59	{
	60	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	61
	62	if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
	63	return 0;
	64
	65	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
	66	return 0;
	67	return 1;
	68	}
	69
	70	static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
	71	{
	72	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	73
	74	if (WARN_ON(pipe < PIPE_A \|\| pipe >= I915_MAX_PIPES))
	75	return -EINVAL;
	76
	77	if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
	78	return 1;
	79
	80	if (edp_pipe_is_enabled(vgpu) &&
	81	get_edp_pipe(vgpu) == pipe)
	82	return 1;
	83	return 0;
	84	}
	85
	86	/* EDID with 1024x768 as its resolution */
	87	static unsigned char virtual_dp_monitor_edid[] = {
	88	/Header/
	89	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
	90	/* Vendor & Product Identification */
	91	0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
	92	/* Version & Revision */
	93	0x01, 0x04,
	94	/* Basic Display Parameters & Features */
	95	0xa5, 0x34, 0x20, 0x78, 0x23,
	96	/* Color Characteristics */
	97	0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
	98	/* Established Timings: maximum resolution is 1024x768 */
	99	0x21, 0x08, 0x00,
	100	/* Standard Timings. All invalid */
101	0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
102	0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
103	/* 18 Byte Data Blocks 1: invalid */
104	0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
105	0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
106	/* 18 Byte Data Blocks 2: invalid */
107	0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
108	0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
109	/* 18 Byte Data Blocks 3: invalid */
110	0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
111	0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
112	/* 18 Byte Data Blocks 4: invalid */
113	0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
114	0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
115	/* Extension Block Count */
116	0x00,
117	/* Checksum */
118	0xef,
119	};
120
121	#define DPCD_HEADER_SIZE 0xb
122
123	u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
124	0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
125	};
126
127	static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
128	{
129	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
130	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT \|
131	SDE_PORTC_HOTPLUG_CPT \|
132	SDE_PORTD_HOTPLUG_CPT);
133
134	if (IS_SKYLAKE(dev_priv))
135	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT \|
136	SDE_PORTE_HOTPLUG_SPT);
137
138	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B))
139	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTB_HOTPLUG_CPT;
140
141	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C))
142	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTC_HOTPLUG_CPT;
143
144	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D))
145	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTD_HOTPLUG_CPT;
146
147	if (IS_SKYLAKE(dev_priv) &&
148	intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
149	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTE_HOTPLUG_SPT;
150	}
151
152	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
153	if (IS_BROADWELL(dev_priv))
154	vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) \|=
155	GEN8_PORT_DP_A_HOTPLUG;
156	else
157	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTA_HOTPLUG_SPT;
158	}
159	}
160
161	static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
162	{
163	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
164
165	kfree(port->edid);
166	port->edid = NULL;
167
168	kfree(port->dpcd);
169	port->dpcd = NULL;
170	}
171
172	static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
173	int type)
174	{
175	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
176
177	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
178	if (!port->edid)
179	return -ENOMEM;
180
181	port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
182	if (!port->dpcd) {
183	kfree(port->edid);
184	return -ENOMEM;
185	}
186
187	memcpy(port->edid->edid_block, virtual_dp_monitor_edid,
188	EDID_SIZE);
189	port->edid->data_valid = true;
190
191	memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
192	port->dpcd->data_valid = true;
193	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
194	port->type = type;
195
196	emulate_monitor_status_change(vgpu);
197	return 0;
198	}
199
200	/**
201	* intel_gvt_check_vblank_emulation - check if vblank emulation timer should
202	* be turned on/off when a virtual pipe is enabled/disabled.
203	* @gvt: a GVT device
204	*
205	* This function is used to turn on/off vblank timer according to currently
206	* enabled/disabled virtual pipes.
207	*
208	*/
209	void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
210	{
211	struct intel_gvt_irq *irq = &gvt->irq;
212	struct intel_vgpu *vgpu;
213	bool have_enabled_pipe = false;
214	int pipe, id;
215
216	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
217	return;
218
219	hrtimer_cancel(&irq->vblank_timer.timer);
220
221	for_each_active_vgpu(gvt, vgpu, id) {
222	for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
223	have_enabled_pipe =
224	pipe_is_enabled(vgpu, pipe);
225	if (have_enabled_pipe)
226	break;
227	}
228	}
229
230	if (have_enabled_pipe)
231	hrtimer_start(&irq->vblank_timer.timer,
232	ktime_add_ns(ktime_get(), irq->vblank_timer.period),
233	HRTIMER_MODE_ABS);
234	}
235
236	static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
237	{
238	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
239	struct intel_vgpu_irq *irq = &vgpu->irq;
240	int vblank_event[] = {
241	[PIPE_A] = PIPE_A_VBLANK,
242	[PIPE_B] = PIPE_B_VBLANK,
243	[PIPE_C] = PIPE_C_VBLANK,
244	};
245	int event;
246
247	if (pipe < PIPE_A \|\| pipe > PIPE_C)
248	return;
249
250	for_each_set_bit(event, irq->flip_done_event[pipe],
251	INTEL_GVT_EVENT_MAX) {
252	clear_bit(event, irq->flip_done_event[pipe]);
253	if (!pipe_is_enabled(vgpu, pipe))
254	continue;
255
256	vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
257	intel_vgpu_trigger_virtual_event(vgpu, event);
258	}
259
260	if (pipe_is_enabled(vgpu, pipe)) {
261	vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
262	intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
263	}
264	}
265
266	static void emulate_vblank(struct intel_vgpu *vgpu)
267	{
268	int pipe;
269
270	for_each_pipe(vgpu->gvt->dev_priv, pipe)
271	emulate_vblank_on_pipe(vgpu, pipe);
272	}
273
274	/**
275	* intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
276	* @gvt: a GVT device
277	*
278	* This function is used to trigger vblank interrupts for vGPUs on GVT device
279	*
280	*/
281	void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
282	{
283	struct intel_vgpu *vgpu;
284	int id;
285
286	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
287	return;
288
289	for_each_active_vgpu(gvt, vgpu, id)
290	emulate_vblank(vgpu);
291	}
292
293	/**
294	* intel_vgpu_clean_display - clean vGPU virtual display emulation
295	* @vgpu: a vGPU
296	*
297	* This function is used to clean vGPU virtual display emulation stuffs
298	*
299	*/
300	void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
301	{
302	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
303
304	if (IS_SKYLAKE(dev_priv))
305	clean_virtual_dp_monitor(vgpu, PORT_D);
306	else
307	clean_virtual_dp_monitor(vgpu, PORT_B);
308	}
309
310	/**
311	* intel_vgpu_init_display- initialize vGPU virtual display emulation
312	* @vgpu: a vGPU
313	*
314	* This function is used to initialize vGPU virtual display emulation stuffs
315	*
316	* Returns:
317	* Zero on success, negative error code if failed.
318	*
319	*/
320	int intel_vgpu_init_display(struct intel_vgpu *vgpu)
321	{
322	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
323
324	intel_vgpu_init_i2c_edid(vgpu);
325
326	if (IS_SKYLAKE(dev_priv))
327	return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D);
328	else
329	return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B);
330	}