[linux-2.6-block.git] / drivers / gpu / drm / i915 / gvt / display.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Ke Yu
 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
 *
 * Contributors:
 *    Terrence Xu <terrence.xu@intel.com>
 *    Changbin Du <changbin.du@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#include "i915_drv.h"
#include "gvt.h"

static int get_edp_pipe(struct intel_vgpu *vgpu)
{
	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
	int pipe = -1;

	switch (data & TRANS_DDI_EDP_INPUT_MASK) {
	case TRANS_DDI_EDP_INPUT_A_ON:
	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		pipe = PIPE_A;
		break;
	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		pipe = PIPE_B;
		break;
	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		pipe = PIPE_C;
		break;
	}
	return pipe;
}

static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
		return 0;

	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
		return 0;
	return 1;
}

static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
		return -EINVAL;

	if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
		return 1;

	if (edp_pipe_is_enabled(vgpu) &&
			get_edp_pipe(vgpu) == pipe)
		return 1;
	return 0;
}

static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
	{
/* EDID with 1024x768 as its resolution */
		/*Header*/
		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
		/* Vendor & Product Identification */
		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
		/* Version & Revision */
		0x01, 0x04,
		/* Basic Display Parameters & Features */
		0xa5, 0x34, 0x20, 0x78, 0x23,
		/* Color Characteristics */
		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
		/* Established Timings: maximum resolution is 1024x768 */
		0x21, 0x08, 0x00,
		/* Standard Timings. All invalid */
		0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
		0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
		/* 18 Byte Data Blocks 1: invalid */
		0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
		/* 18 Byte Data Blocks 2: invalid */
		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
		/* 18 Byte Data Blocks 3: invalid */
		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
		/* 18 Byte Data Blocks 4: invalid */
		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
		/* Extension Block Count */
		0x00,
		/* Checksum */
		0xef,
	},
	{
/* EDID with 1920x1200 as its resolution */
		/*Header*/
		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
		/* Vendor & Product Identification */
		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
		/* Version & Revision */
		0x01, 0x04,
		/* Basic Display Parameters & Features */
		0xa5, 0x34, 0x20, 0x78, 0x23,
		/* Color Characteristics */
		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
		/* Established Timings: maximum resolution is 1024x768 */
		0x21, 0x08, 0x00,
		/*
		 * Standard Timings.
		 * below new resolutions can be supported:
		 * 1920x1080, 1280x720, 1280x960, 1280x1024,
		 * 1440x900, 1600x1200, 1680x1050
		 */
		0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
		0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
		/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
		0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
		/* 18 Byte Data Blocks 2: invalid */
		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
		/* 18 Byte Data Blocks 3: invalid */
		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
		/* 18 Byte Data Blocks 4: invalid */
		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
		/* Extension Block Count */
		0x00,
		/* Checksum */
		0x45,
	},
};

#define DPCD_HEADER_SIZE        0xb

/* let the virtual display supports DP1.2 */
static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};

static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
			SDE_PORTC_HOTPLUG_CPT |
			SDE_PORTD_HOTPLUG_CPT);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
		vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
				SDE_PORTE_HOTPLUG_SPT);
		vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=
				SKL_FUSE_DOWNLOAD_STATUS |
				SKL_FUSE_PG0_DIST_STATUS |
				SKL_FUSE_PG1_DIST_STATUS |
				SKL_FUSE_PG2_DIST_STATUS;
		vgpu_vreg(vgpu, LCPLL1_CTL) |=
				LCPLL_PLL_ENABLE |
				LCPLL_PLL_LOCK;
		vgpu_vreg(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;

	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
	}

	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
		if (IS_BROADWELL(dev_priv))
			vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=
				GEN8_PORT_DP_A_HOTPLUG;
		else
			vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
	}
}

static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
{
	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);

	kfree(port->edid);
	port->edid = NULL;

	kfree(port->dpcd);
	port->dpcd = NULL;
}

static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
				    int type, unsigned int resolution)
{
	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);

	if (WARN_ON(resolution >= GVT_EDID_NUM))
		return -EINVAL;

	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
	if (!port->edid)
		return -ENOMEM;

	port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
	if (!port->dpcd) {
		kfree(port->edid);
		return -ENOMEM;
	}

	memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
			EDID_SIZE);
	port->edid->data_valid = true;

	memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
	port->dpcd->data_valid = true;
	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
	port->type = type;

	emulate_monitor_status_change(vgpu);
	return 0;
}

/**
 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
 * be turned on/off when a virtual pipe is enabled/disabled.
 * @gvt: a GVT device
 *
 * This function is used to turn on/off vblank timer according to currently
 * enabled/disabled virtual pipes.
 *
 */
void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
{
	struct intel_gvt_irq *irq = &gvt->irq;
	struct intel_vgpu *vgpu;
	bool have_enabled_pipe = false;
	int pipe, id;

	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
		return;

	hrtimer_cancel(&irq->vblank_timer.timer);

	for_each_active_vgpu(gvt, vgpu, id) {
		for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
			have_enabled_pipe =
				pipe_is_enabled(vgpu, pipe);
			if (have_enabled_pipe)
				break;
		}
	}

	if (have_enabled_pipe)
		hrtimer_start(&irq->vblank_timer.timer,
			ktime_add_ns(ktime_get(), irq->vblank_timer.period),
			HRTIMER_MODE_ABS);
}

static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	struct intel_vgpu_irq *irq = &vgpu->irq;
	int vblank_event[] = {
		[PIPE_A] = PIPE_A_VBLANK,
		[PIPE_B] = PIPE_B_VBLANK,
		[PIPE_C] = PIPE_C_VBLANK,
	};
	int event;

	if (pipe < PIPE_A || pipe > PIPE_C)
		return;

	for_each_set_bit(event, irq->flip_done_event[pipe],
			INTEL_GVT_EVENT_MAX) {
		clear_bit(event, irq->flip_done_event[pipe]);
		if (!pipe_is_enabled(vgpu, pipe))
			continue;

		vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
		intel_vgpu_trigger_virtual_event(vgpu, event);
	}

	if (pipe_is_enabled(vgpu, pipe)) {
		vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
	}
}

static void emulate_vblank(struct intel_vgpu *vgpu)
{
	int pipe;

	for_each_pipe(vgpu->gvt->dev_priv, pipe)
		emulate_vblank_on_pipe(vgpu, pipe);
}

/**
 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
 * @gvt: a GVT device
 *
 * This function is used to trigger vblank interrupts for vGPUs on GVT device
 *
 */
void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
{
	struct intel_vgpu *vgpu;
	int id;

	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
		return;

	for_each_active_vgpu(gvt, vgpu, id)
		emulate_vblank(vgpu);
}

/**
 * intel_vgpu_clean_display - clean vGPU virtual display emulation
 * @vgpu: a vGPU
 *
 * This function is used to clean vGPU virtual display emulation stuffs
 *
 */
void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
		clean_virtual_dp_monitor(vgpu, PORT_D);
	else
		clean_virtual_dp_monitor(vgpu, PORT_B);
}

/**
 * intel_vgpu_init_display- initialize vGPU virtual display emulation
 * @vgpu: a vGPU
 *
 * This function is used to initialize vGPU virtual display emulation stuffs
 *
 * Returns:
 * Zero on success, negative error code if failed.
 *
 */
int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	intel_vgpu_init_i2c_edid(vgpu);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
						resolution);
	else
		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
						resolution);
}

/**
 * intel_vgpu_reset_display- reset vGPU virtual display emulation
 * @vgpu: a vGPU
 *
 * This function is used to reset vGPU virtual display emulation stuffs
 *
 */
void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
{
	emulate_monitor_status_change(vgpu);
}
Commit	Line	Data
04d348ae ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Ke Yu
	25	* Zhiyuan Lv <zhiyuan.lv@intel.com>
	26	*
	27	* Contributors:
	28	* Terrence Xu <terrence.xu@intel.com>
	29	* Changbin Du <changbin.du@intel.com>
	30	* Bing Niu <bing.niu@intel.com>
	31	* Zhi Wang <zhi.a.wang@intel.com>
	32	*
	33	*/
	34
	35	#include "i915_drv.h"
feddf6e8	36	#include "gvt.h"
04d348ae ZW	37
	38	static int get_edp_pipe(struct intel_vgpu *vgpu)
	39	{
	40	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
	41	int pipe = -1;
	42
	43	switch (data & TRANS_DDI_EDP_INPUT_MASK) {
	44	case TRANS_DDI_EDP_INPUT_A_ON:
	45	case TRANS_DDI_EDP_INPUT_A_ONOFF:
	46	pipe = PIPE_A;
	47	break;
	48	case TRANS_DDI_EDP_INPUT_B_ONOFF:
	49	pipe = PIPE_B;
	50	break;
	51	case TRANS_DDI_EDP_INPUT_C_ONOFF:
	52	pipe = PIPE_C;
	53	break;
	54	}
	55	return pipe;
	56	}
	57
	58	static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
	59	{
	60	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	61
	62	if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
	63	return 0;
	64
	65	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
	66	return 0;
	67	return 1;
	68	}
	69
	70	static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
	71	{
	72	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	73
	74	if (WARN_ON(pipe < PIPE_A \|\| pipe >= I915_MAX_PIPES))
	75	return -EINVAL;
	76
	77	if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
	78	return 1;
	79
	80	if (edp_pipe_is_enabled(vgpu) &&
	81	get_edp_pipe(vgpu) == pipe)
	82	return 1;
	83	return 0;
	84	}
	85
bca5609f ZW	86	static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
	87	{
	88	/* EDID with 1024x768 as its resolution */
	89	/Header/
	90	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
	91	/* Vendor & Product Identification */
	92	0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
	93	/* Version & Revision */
	94	0x01, 0x04,
	95	/* Basic Display Parameters & Features */
	96	0xa5, 0x34, 0x20, 0x78, 0x23,
	97	/* Color Characteristics */
	98	0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
	99	/* Established Timings: maximum resolution is 1024x768 */
	100	0x21, 0x08, 0x00,
	101	/* Standard Timings. All invalid */
	102	0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
	103	0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
	104	/* 18 Byte Data Blocks 1: invalid */
	105	0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
	106	0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
	107	/* 18 Byte Data Blocks 2: invalid */
	108	0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
	109	0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
	110	/* 18 Byte Data Blocks 3: invalid */
	111	0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
	112	0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
	113	/* 18 Byte Data Blocks 4: invalid */
	114	0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
	115	0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
	116	/* Extension Block Count */
	117	0x00,
	118	/* Checksum */
	119	0xef,
	120	},
	121	{
2c883136	122	/* EDID with 1920x1200 as its resolution */
bca5609f ZW	123	/Header/
	124	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
	125	/* Vendor & Product Identification */
	126	0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
	127	/* Version & Revision */
	128	0x01, 0x04,
	129	/* Basic Display Parameters & Features */
	130	0xa5, 0x34, 0x20, 0x78, 0x23,
	131	/* Color Characteristics */
	132	0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
	133	/* Established Timings: maximum resolution is 1024x768 */
	134	0x21, 0x08, 0x00,
	135	/*
	136	* Standard Timings.
	137	* below new resolutions can be supported:
	138	* 1920x1080, 1280x720, 1280x960, 1280x1024,
	139	* 1440x900, 1600x1200, 1680x1050
	140	*/
	141	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
	142	0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
	143	/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
	144	0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
	145	0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
	146	/* 18 Byte Data Blocks 2: invalid */
	147	0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
	148	0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
	149	/* 18 Byte Data Blocks 3: invalid */
	150	0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
	151	0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
	152	/* 18 Byte Data Blocks 4: invalid */
	153	0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
	154	0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
	155	/* Extension Block Count */
	156	0x00,
	157	/* Checksum */
	158	0x45,
	159	},
04d348ae ZW	160	};
	161
	162	#define DPCD_HEADER_SIZE 0xb
	163
e2e02cbb	164	/* let the virtual display supports DP1.2 */
999ccb40	165	static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
e2e02cbb	166	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
04d348ae ZW	167	};
	168
	169	static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
	170	{
	171	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	172	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT \|
	173	SDE_PORTC_HOTPLUG_CPT \|
	174	SDE_PORTD_HOTPLUG_CPT);
	175
e3476c00	176	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) {
04d348ae ZW	177	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT \|
04d348ae ZW	178	SDE_PORTE_HOTPLUG_SPT);
88a16b64 WL	179	vgpu_vreg(vgpu, SKL_FUSE_STATUS) \|=
	180	SKL_FUSE_DOWNLOAD_STATUS \|
	181	SKL_FUSE_PG0_DIST_STATUS \|
	182	SKL_FUSE_PG1_DIST_STATUS \|
	183	SKL_FUSE_PG2_DIST_STATUS;
	184	vgpu_vreg(vgpu, LCPLL1_CTL) \|=
	185	LCPLL_PLL_ENABLE \|
	186	LCPLL_PLL_LOCK;
	187	vgpu_vreg(vgpu, LCPLL2_CTL) \|= LCPLL_PLL_ENABLE;
	188
	189	}
04d348ae	190
858b0f57	191	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
04d348ae	192	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTB_HOTPLUG_CPT;
858b0f57 BN	193	vgpu_vreg(vgpu, SFUSE_STRAP) \|= SFUSE_STRAP_DDIB_DETECTED;
858b0f57 BN	194	}
04d348ae	195
858b0f57	196	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
04d348ae	197	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTC_HOTPLUG_CPT;
858b0f57 BN	198	vgpu_vreg(vgpu, SFUSE_STRAP) \|= SFUSE_STRAP_DDIC_DETECTED;
858b0f57 BN	199	}
04d348ae	200
858b0f57	201	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
04d348ae	202	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTD_HOTPLUG_CPT;
858b0f57 BN	203	vgpu_vreg(vgpu, SFUSE_STRAP) \|= SFUSE_STRAP_DDID_DETECTED;
858b0f57 BN	204	}
04d348ae	205
e3476c00	206	if ((IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) &&
04d348ae ZW	207	intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
	208	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTE_HOTPLUG_SPT;
	209	}
	210
	211	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
	212	if (IS_BROADWELL(dev_priv))
	213	vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) \|=
	214	GEN8_PORT_DP_A_HOTPLUG;
	215	else
	216	vgpu_vreg(vgpu, SDEISR) \|= SDE_PORTA_HOTPLUG_SPT;
858b0f57 BN	217
858b0f57 BN	218	vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) \|= DDI_INIT_DISPLAY_DETECTED;
04d348ae ZW	219	}
	220	}
	221
	222	static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
	223	{
	224	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
	225
	226	kfree(port->edid);
	227	port->edid = NULL;
	228
	229	kfree(port->dpcd);
	230	port->dpcd = NULL;
	231	}
	232
	233	static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
d1a513be	234	int type, unsigned int resolution)
04d348ae ZW	235	{
	236	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
	237
d1a513be ZW	238	if (WARN_ON(resolution >= GVT_EDID_NUM))
	239	return -EINVAL;
	240
04d348ae ZW	241	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
	242	if (!port->edid)
	243	return -ENOMEM;
	244
	245	port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
	246	if (!port->dpcd) {
	247	kfree(port->edid);
	248	return -ENOMEM;
	249	}
	250
d1a513be	251	memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
04d348ae ZW	252	EDID_SIZE);
	253	port->edid->data_valid = true;
	254
	255	memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
	256	port->dpcd->data_valid = true;
	257	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
	258	port->type = type;
	259
	260	emulate_monitor_status_change(vgpu);
	261	return 0;
	262	}
	263
	264	/**
	265	* intel_gvt_check_vblank_emulation - check if vblank emulation timer should
	266	* be turned on/off when a virtual pipe is enabled/disabled.
	267	* @gvt: a GVT device
	268	*
	269	* This function is used to turn on/off vblank timer according to currently
	270	* enabled/disabled virtual pipes.
	271	*
	272	*/
	273	void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
	274	{
	275	struct intel_gvt_irq *irq = &gvt->irq;
	276	struct intel_vgpu *vgpu;
	277	bool have_enabled_pipe = false;
	278	int pipe, id;
	279
	280	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
	281	return;
	282
	283	hrtimer_cancel(&irq->vblank_timer.timer);
	284
	285	for_each_active_vgpu(gvt, vgpu, id) {
	286	for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
	287	have_enabled_pipe =
	288	pipe_is_enabled(vgpu, pipe);
	289	if (have_enabled_pipe)
	290	break;
	291	}
	292	}
	293
	294	if (have_enabled_pipe)
	295	hrtimer_start(&irq->vblank_timer.timer,
	296	ktime_add_ns(ktime_get(), irq->vblank_timer.period),
	297	HRTIMER_MODE_ABS);
	298	}
	299
	300	static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
	301	{
	302	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	303	struct intel_vgpu_irq *irq = &vgpu->irq;
	304	int vblank_event[] = {
	305	[PIPE_A] = PIPE_A_VBLANK,
	306	[PIPE_B] = PIPE_B_VBLANK,
	307	[PIPE_C] = PIPE_C_VBLANK,
	308	};
	309	int event;
	310
	311	if (pipe < PIPE_A \|\| pipe > PIPE_C)
	312	return;
	313
	314	for_each_set_bit(event, irq->flip_done_event[pipe],
	315	INTEL_GVT_EVENT_MAX) {
316	clear_bit(event, irq->flip_done_event[pipe]);
317	if (!pipe_is_enabled(vgpu, pipe))
318	continue;
319
320	vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
321	intel_vgpu_trigger_virtual_event(vgpu, event);
322	}
323
324	if (pipe_is_enabled(vgpu, pipe)) {
325	vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
326	intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
327	}
328	}
329
330	static void emulate_vblank(struct intel_vgpu *vgpu)
331	{
332	int pipe;
333
334	for_each_pipe(vgpu->gvt->dev_priv, pipe)
335	emulate_vblank_on_pipe(vgpu, pipe);
336	}
337
338	/**
339	* intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
340	* @gvt: a GVT device
341	*
342	* This function is used to trigger vblank interrupts for vGPUs on GVT device
343	*
344	*/
345	void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
346	{
347	struct intel_vgpu *vgpu;
348	int id;
349
350	if (WARN_ON(!mutex_is_locked(&gvt->lock)))
351	return;
352
353	for_each_active_vgpu(gvt, vgpu, id)
354	emulate_vblank(vgpu);
355	}
356
357	/**
358	* intel_vgpu_clean_display - clean vGPU virtual display emulation
359	* @vgpu: a vGPU
360	*
361	* This function is used to clean vGPU virtual display emulation stuffs
362	*
363	*/
364	void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
365	{
366	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
367
e3476c00	368	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv))
04d348ae ZW	369	clean_virtual_dp_monitor(vgpu, PORT_D);
	370	else
	371	clean_virtual_dp_monitor(vgpu, PORT_B);
	372	}
	373
	374	/**
	375	* intel_vgpu_init_display- initialize vGPU virtual display emulation
	376	* @vgpu: a vGPU
	377	*
	378	* This function is used to initialize vGPU virtual display emulation stuffs
	379	*
	380	* Returns:
	381	* Zero on success, negative error code if failed.
	382	*
	383	*/
d1a513be	384	int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
04d348ae ZW	385	{
	386	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
	387
	388	intel_vgpu_init_i2c_edid(vgpu);
	389
e3476c00	390	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv))
d1a513be ZW	391	return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
d1a513be ZW	392	resolution);
04d348ae	393	else
d1a513be ZW	394	return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
d1a513be ZW	395	resolution);
04d348ae	396	}
6294b61b CD	397
	398	/**
	399	* intel_vgpu_reset_display- reset vGPU virtual display emulation
	400	* @vgpu: a vGPU
	401	*
	402	* This function is used to reset vGPU virtual display emulation stuffs
	403	*
	404	*/
	405	void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
	406	{
	407	emulate_monitor_status_change(vgpu);
	408	}