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1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ke Yu | |
25 | * Zhiyuan Lv <zhiyuan.lv@intel.com> | |
26 | * | |
27 | * Contributors: | |
28 | * Terrence Xu <terrence.xu@intel.com> | |
29 | * Changbin Du <changbin.du@intel.com> | |
30 | * Bing Niu <bing.niu@intel.com> | |
31 | * Zhi Wang <zhi.a.wang@intel.com> | |
32 | * | |
33 | */ | |
34 | ||
35 | #include "i915_drv.h" | |
36 | ||
37 | static int get_edp_pipe(struct intel_vgpu *vgpu) | |
38 | { | |
39 | u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); | |
40 | int pipe = -1; | |
41 | ||
42 | switch (data & TRANS_DDI_EDP_INPUT_MASK) { | |
43 | case TRANS_DDI_EDP_INPUT_A_ON: | |
44 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
45 | pipe = PIPE_A; | |
46 | break; | |
47 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
48 | pipe = PIPE_B; | |
49 | break; | |
50 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
51 | pipe = PIPE_C; | |
52 | break; | |
53 | } | |
54 | return pipe; | |
55 | } | |
56 | ||
57 | static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) | |
58 | { | |
59 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
60 | ||
61 | if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) | |
62 | return 0; | |
63 | ||
64 | if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) | |
65 | return 0; | |
66 | return 1; | |
67 | } | |
68 | ||
69 | static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) | |
70 | { | |
71 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
72 | ||
73 | if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) | |
74 | return -EINVAL; | |
75 | ||
76 | if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) | |
77 | return 1; | |
78 | ||
79 | if (edp_pipe_is_enabled(vgpu) && | |
80 | get_edp_pipe(vgpu) == pipe) | |
81 | return 1; | |
82 | return 0; | |
83 | } | |
84 | ||
85 | /* EDID with 1024x768 as its resolution */ | |
86 | static unsigned char virtual_dp_monitor_edid[] = { | |
87 | /*Header*/ | |
88 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, | |
89 | /* Vendor & Product Identification */ | |
90 | 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, | |
91 | /* Version & Revision */ | |
92 | 0x01, 0x04, | |
93 | /* Basic Display Parameters & Features */ | |
94 | 0xa5, 0x34, 0x20, 0x78, 0x23, | |
95 | /* Color Characteristics */ | |
96 | 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, | |
97 | /* Established Timings: maximum resolution is 1024x768 */ | |
98 | 0x21, 0x08, 0x00, | |
99 | /* Standard Timings. All invalid */ | |
100 | 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, | |
101 | 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, | |
102 | /* 18 Byte Data Blocks 1: invalid */ | |
103 | 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, | |
104 | 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, | |
105 | /* 18 Byte Data Blocks 2: invalid */ | |
106 | 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, | |
107 | 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, | |
108 | /* 18 Byte Data Blocks 3: invalid */ | |
109 | 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, | |
110 | 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, | |
111 | /* 18 Byte Data Blocks 4: invalid */ | |
112 | 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, | |
113 | 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, | |
114 | /* Extension Block Count */ | |
115 | 0x00, | |
116 | /* Checksum */ | |
117 | 0xef, | |
118 | }; | |
119 | ||
120 | #define DPCD_HEADER_SIZE 0xb | |
121 | ||
122 | u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { | |
123 | 0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 | |
124 | }; | |
125 | ||
126 | static void emulate_monitor_status_change(struct intel_vgpu *vgpu) | |
127 | { | |
128 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
129 | vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | | |
130 | SDE_PORTC_HOTPLUG_CPT | | |
131 | SDE_PORTD_HOTPLUG_CPT); | |
132 | ||
133 | if (IS_SKYLAKE(dev_priv)) | |
134 | vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | | |
135 | SDE_PORTE_HOTPLUG_SPT); | |
136 | ||
137 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) | |
138 | vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; | |
139 | ||
140 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) | |
141 | vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; | |
142 | ||
143 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) | |
144 | vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; | |
145 | ||
146 | if (IS_SKYLAKE(dev_priv) && | |
147 | intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { | |
148 | vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; | |
149 | } | |
150 | ||
151 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { | |
152 | if (IS_BROADWELL(dev_priv)) | |
153 | vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |= | |
154 | GEN8_PORT_DP_A_HOTPLUG; | |
155 | else | |
156 | vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; | |
157 | } | |
158 | } | |
159 | ||
160 | static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) | |
161 | { | |
162 | struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); | |
163 | ||
164 | kfree(port->edid); | |
165 | port->edid = NULL; | |
166 | ||
167 | kfree(port->dpcd); | |
168 | port->dpcd = NULL; | |
169 | } | |
170 | ||
171 | static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, | |
172 | int type) | |
173 | { | |
174 | struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); | |
175 | ||
176 | port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); | |
177 | if (!port->edid) | |
178 | return -ENOMEM; | |
179 | ||
180 | port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); | |
181 | if (!port->dpcd) { | |
182 | kfree(port->edid); | |
183 | return -ENOMEM; | |
184 | } | |
185 | ||
186 | memcpy(port->edid->edid_block, virtual_dp_monitor_edid, | |
187 | EDID_SIZE); | |
188 | port->edid->data_valid = true; | |
189 | ||
190 | memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); | |
191 | port->dpcd->data_valid = true; | |
192 | port->dpcd->data[DPCD_SINK_COUNT] = 0x1; | |
193 | port->type = type; | |
194 | ||
195 | emulate_monitor_status_change(vgpu); | |
196 | return 0; | |
197 | } | |
198 | ||
199 | /** | |
200 | * intel_gvt_check_vblank_emulation - check if vblank emulation timer should | |
201 | * be turned on/off when a virtual pipe is enabled/disabled. | |
202 | * @gvt: a GVT device | |
203 | * | |
204 | * This function is used to turn on/off vblank timer according to currently | |
205 | * enabled/disabled virtual pipes. | |
206 | * | |
207 | */ | |
208 | void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) | |
209 | { | |
210 | struct intel_gvt_irq *irq = &gvt->irq; | |
211 | struct intel_vgpu *vgpu; | |
212 | bool have_enabled_pipe = false; | |
213 | int pipe, id; | |
214 | ||
215 | if (WARN_ON(!mutex_is_locked(&gvt->lock))) | |
216 | return; | |
217 | ||
218 | hrtimer_cancel(&irq->vblank_timer.timer); | |
219 | ||
220 | for_each_active_vgpu(gvt, vgpu, id) { | |
221 | for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { | |
222 | have_enabled_pipe = | |
223 | pipe_is_enabled(vgpu, pipe); | |
224 | if (have_enabled_pipe) | |
225 | break; | |
226 | } | |
227 | } | |
228 | ||
229 | if (have_enabled_pipe) | |
230 | hrtimer_start(&irq->vblank_timer.timer, | |
231 | ktime_add_ns(ktime_get(), irq->vblank_timer.period), | |
232 | HRTIMER_MODE_ABS); | |
233 | } | |
234 | ||
235 | static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) | |
236 | { | |
237 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
238 | struct intel_vgpu_irq *irq = &vgpu->irq; | |
239 | int vblank_event[] = { | |
240 | [PIPE_A] = PIPE_A_VBLANK, | |
241 | [PIPE_B] = PIPE_B_VBLANK, | |
242 | [PIPE_C] = PIPE_C_VBLANK, | |
243 | }; | |
244 | int event; | |
245 | ||
246 | if (pipe < PIPE_A || pipe > PIPE_C) | |
247 | return; | |
248 | ||
249 | for_each_set_bit(event, irq->flip_done_event[pipe], | |
250 | INTEL_GVT_EVENT_MAX) { | |
251 | clear_bit(event, irq->flip_done_event[pipe]); | |
252 | if (!pipe_is_enabled(vgpu, pipe)) | |
253 | continue; | |
254 | ||
255 | vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; | |
256 | intel_vgpu_trigger_virtual_event(vgpu, event); | |
257 | } | |
258 | ||
259 | if (pipe_is_enabled(vgpu, pipe)) { | |
260 | vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; | |
261 | intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); | |
262 | } | |
263 | } | |
264 | ||
265 | static void emulate_vblank(struct intel_vgpu *vgpu) | |
266 | { | |
267 | int pipe; | |
268 | ||
269 | for_each_pipe(vgpu->gvt->dev_priv, pipe) | |
270 | emulate_vblank_on_pipe(vgpu, pipe); | |
271 | } | |
272 | ||
273 | /** | |
274 | * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device | |
275 | * @gvt: a GVT device | |
276 | * | |
277 | * This function is used to trigger vblank interrupts for vGPUs on GVT device | |
278 | * | |
279 | */ | |
280 | void intel_gvt_emulate_vblank(struct intel_gvt *gvt) | |
281 | { | |
282 | struct intel_vgpu *vgpu; | |
283 | int id; | |
284 | ||
285 | if (WARN_ON(!mutex_is_locked(&gvt->lock))) | |
286 | return; | |
287 | ||
288 | for_each_active_vgpu(gvt, vgpu, id) | |
289 | emulate_vblank(vgpu); | |
290 | } | |
291 | ||
292 | /** | |
293 | * intel_vgpu_clean_display - clean vGPU virtual display emulation | |
294 | * @vgpu: a vGPU | |
295 | * | |
296 | * This function is used to clean vGPU virtual display emulation stuffs | |
297 | * | |
298 | */ | |
299 | void intel_vgpu_clean_display(struct intel_vgpu *vgpu) | |
300 | { | |
301 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
302 | ||
303 | if (IS_SKYLAKE(dev_priv)) | |
304 | clean_virtual_dp_monitor(vgpu, PORT_D); | |
305 | else | |
306 | clean_virtual_dp_monitor(vgpu, PORT_B); | |
307 | } | |
308 | ||
309 | /** | |
310 | * intel_vgpu_init_display- initialize vGPU virtual display emulation | |
311 | * @vgpu: a vGPU | |
312 | * | |
313 | * This function is used to initialize vGPU virtual display emulation stuffs | |
314 | * | |
315 | * Returns: | |
316 | * Zero on success, negative error code if failed. | |
317 | * | |
318 | */ | |
319 | int intel_vgpu_init_display(struct intel_vgpu *vgpu) | |
320 | { | |
321 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | |
322 | ||
323 | intel_vgpu_init_i2c_edid(vgpu); | |
324 | ||
325 | if (IS_SKYLAKE(dev_priv)) | |
326 | return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D); | |
327 | else | |
328 | return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B); | |
329 | } |