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1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ke Yu | |
25 | * Kevin Tian <kevin.tian@intel.com> | |
26 | * Zhiyuan Lv <zhiyuan.lv@intel.com> | |
27 | * | |
28 | * Contributors: | |
29 | * Min He <min.he@intel.com> | |
30 | * Ping Gao <ping.a.gao@intel.com> | |
31 | * Tina Zhang <tina.zhang@intel.com> | |
32 | * Yulei Zhang <yulei.zhang@intel.com> | |
33 | * Zhi Wang <zhi.a.wang@intel.com> | |
34 | * | |
35 | */ | |
36 | ||
37 | #include <linux/slab.h> | |
38 | #include "i915_drv.h" | |
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39 | #include "gvt.h" |
40 | #include "i915_pvinfo.h" | |
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41 | #include "trace.h" |
42 | ||
43 | #define INVALID_OP (~0U) | |
44 | ||
45 | #define OP_LEN_MI 9 | |
46 | #define OP_LEN_2D 10 | |
47 | #define OP_LEN_3D_MEDIA 16 | |
48 | #define OP_LEN_MFX_VC 16 | |
49 | #define OP_LEN_VEBOX 16 | |
50 | ||
51 | #define CMD_TYPE(cmd) (((cmd) >> 29) & 7) | |
52 | ||
53 | struct sub_op_bits { | |
54 | int hi; | |
55 | int low; | |
56 | }; | |
57 | struct decode_info { | |
ed8cce30 | 58 | const char *name; |
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59 | int op_len; |
60 | int nr_sub_op; | |
ed8cce30 | 61 | const struct sub_op_bits *sub_op; |
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62 | }; |
63 | ||
64 | #define MAX_CMD_BUDGET 0x7fffffff | |
65 | #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15) | |
66 | #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9) | |
67 | #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1) | |
68 | ||
69 | #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20) | |
70 | #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10) | |
71 | #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2) | |
72 | ||
73 | /* Render Command Map */ | |
74 | ||
75 | /* MI_* command Opcode (28:23) */ | |
76 | #define OP_MI_NOOP 0x0 | |
77 | #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */ | |
78 | #define OP_MI_USER_INTERRUPT 0x2 | |
79 | #define OP_MI_WAIT_FOR_EVENT 0x3 | |
80 | #define OP_MI_FLUSH 0x4 | |
81 | #define OP_MI_ARB_CHECK 0x5 | |
82 | #define OP_MI_RS_CONTROL 0x6 /* HSW+ */ | |
83 | #define OP_MI_REPORT_HEAD 0x7 | |
84 | #define OP_MI_ARB_ON_OFF 0x8 | |
85 | #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */ | |
86 | #define OP_MI_BATCH_BUFFER_END 0xA | |
87 | #define OP_MI_SUSPEND_FLUSH 0xB | |
88 | #define OP_MI_PREDICATE 0xC /* IVB+ */ | |
89 | #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */ | |
90 | #define OP_MI_SET_APPID 0xE /* IVB+ */ | |
91 | #define OP_MI_RS_CONTEXT 0xF /* HSW+ */ | |
92 | #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */ | |
93 | #define OP_MI_DISPLAY_FLIP 0x14 | |
94 | #define OP_MI_SEMAPHORE_MBOX 0x16 | |
95 | #define OP_MI_SET_CONTEXT 0x18 | |
96 | #define OP_MI_MATH 0x1A | |
97 | #define OP_MI_URB_CLEAR 0x19 | |
98 | #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */ | |
99 | #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */ | |
100 | ||
101 | #define OP_MI_STORE_DATA_IMM 0x20 | |
102 | #define OP_MI_STORE_DATA_INDEX 0x21 | |
103 | #define OP_MI_LOAD_REGISTER_IMM 0x22 | |
104 | #define OP_MI_UPDATE_GTT 0x23 | |
105 | #define OP_MI_STORE_REGISTER_MEM 0x24 | |
106 | #define OP_MI_FLUSH_DW 0x26 | |
107 | #define OP_MI_CLFLUSH 0x27 | |
108 | #define OP_MI_REPORT_PERF_COUNT 0x28 | |
109 | #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */ | |
110 | #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */ | |
111 | #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */ | |
112 | #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */ | |
113 | #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */ | |
114 | #define OP_MI_2E 0x2E /* BDW+ */ | |
115 | #define OP_MI_2F 0x2F /* BDW+ */ | |
116 | #define OP_MI_BATCH_BUFFER_START 0x31 | |
117 | ||
118 | /* Bit definition for dword 0 */ | |
119 | #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8) | |
120 | ||
121 | #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36 | |
122 | ||
123 | #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2)) | |
124 | #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U)) | |
125 | #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U) | |
126 | #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U) | |
127 | ||
128 | /* 2D command: Opcode (28:22) */ | |
129 | #define OP_2D(x) ((2<<7) | x) | |
130 | ||
131 | #define OP_XY_SETUP_BLT OP_2D(0x1) | |
132 | #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3) | |
133 | #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11) | |
134 | #define OP_XY_PIXEL_BLT OP_2D(0x24) | |
135 | #define OP_XY_SCANLINES_BLT OP_2D(0x25) | |
136 | #define OP_XY_TEXT_BLT OP_2D(0x26) | |
137 | #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31) | |
138 | #define OP_XY_COLOR_BLT OP_2D(0x50) | |
139 | #define OP_XY_PAT_BLT OP_2D(0x51) | |
140 | #define OP_XY_MONO_PAT_BLT OP_2D(0x52) | |
141 | #define OP_XY_SRC_COPY_BLT OP_2D(0x53) | |
142 | #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54) | |
143 | #define OP_XY_FULL_BLT OP_2D(0x55) | |
144 | #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56) | |
145 | #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57) | |
146 | #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58) | |
147 | #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59) | |
148 | #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71) | |
149 | #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72) | |
150 | #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73) | |
151 | #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74) | |
152 | #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75) | |
153 | #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76) | |
154 | #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77) | |
155 | ||
156 | /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */ | |
157 | #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \ | |
158 | ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode)) | |
159 | ||
160 | #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03) | |
161 | ||
162 | #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01) | |
163 | #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02) | |
164 | #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04) | |
165 | ||
166 | #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B) | |
167 | ||
168 | #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04) | |
169 | ||
170 | #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0) | |
171 | #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1) | |
172 | #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2) | |
173 | #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3) | |
174 | #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4) | |
02b966c1 | 175 | #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5) |
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176 | |
177 | #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0) | |
178 | #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2) | |
179 | #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3) | |
180 | #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5) | |
181 | ||
182 | #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */ | |
183 | #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */ | |
184 | #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */ | |
185 | #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */ | |
186 | #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08) | |
187 | #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09) | |
188 | #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A) | |
189 | #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B) | |
190 | #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */ | |
191 | #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E) | |
192 | #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F) | |
193 | #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10) | |
194 | #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11) | |
195 | #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12) | |
196 | #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13) | |
197 | #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14) | |
198 | #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15) | |
199 | #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16) | |
200 | #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17) | |
201 | #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18) | |
202 | #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */ | |
203 | #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */ | |
204 | #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */ | |
205 | #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */ | |
206 | #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */ | |
207 | #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */ | |
208 | #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */ | |
209 | #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */ | |
210 | #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */ | |
211 | #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */ | |
212 | #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */ | |
213 | #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */ | |
214 | #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */ | |
215 | #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */ | |
216 | #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */ | |
217 | #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */ | |
218 | #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */ | |
219 | #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */ | |
220 | #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */ | |
221 | #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */ | |
222 | #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */ | |
223 | #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */ | |
224 | #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */ | |
225 | #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */ | |
226 | #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */ | |
227 | #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */ | |
228 | #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */ | |
229 | #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */ | |
230 | #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */ | |
231 | #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */ | |
232 | #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */ | |
233 | #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */ | |
234 | #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */ | |
235 | #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */ | |
236 | #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */ | |
237 | #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */ | |
238 | #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */ | |
239 | #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */ | |
240 | #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */ | |
241 | #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */ | |
242 | #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */ | |
243 | #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */ | |
244 | #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */ | |
245 | #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */ | |
246 | #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */ | |
247 | #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */ | |
248 | ||
249 | #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */ | |
250 | #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */ | |
251 | #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */ | |
252 | #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */ | |
253 | #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */ | |
254 | #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */ | |
255 | #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */ | |
256 | #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */ | |
257 | #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */ | |
258 | #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */ | |
259 | #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */ | |
260 | ||
261 | #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00) | |
262 | #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02) | |
263 | #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04) | |
264 | #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05) | |
265 | #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06) | |
266 | #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07) | |
267 | #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08) | |
268 | #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A) | |
269 | #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B) | |
270 | #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C) | |
271 | #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D) | |
272 | #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E) | |
273 | #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F) | |
274 | #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10) | |
275 | #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11) | |
276 | #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */ | |
277 | #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */ | |
278 | #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */ | |
279 | #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */ | |
280 | #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */ | |
281 | #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17) | |
282 | #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18) | |
283 | #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */ | |
284 | #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */ | |
285 | #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */ | |
286 | #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C) | |
287 | #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00) | |
288 | #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00) | |
289 | ||
290 | /* VCCP Command Parser */ | |
291 | ||
292 | /* | |
293 | * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License) | |
294 | * git://anongit.freedesktop.org/vaapi/intel-driver | |
295 | * src/i965_defines.h | |
296 | * | |
297 | */ | |
298 | ||
299 | #define OP_MFX(pipeline, op, sub_opa, sub_opb) \ | |
300 | (3 << 13 | \ | |
301 | (pipeline) << 11 | \ | |
302 | (op) << 8 | \ | |
303 | (sub_opa) << 5 | \ | |
304 | (sub_opb)) | |
305 | ||
306 | #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */ | |
307 | #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */ | |
308 | #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */ | |
309 | #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */ | |
310 | #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */ | |
311 | #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */ | |
312 | #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */ | |
313 | #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */ | |
314 | #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */ | |
315 | #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */ | |
316 | #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */ | |
317 | ||
318 | #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */ | |
319 | ||
320 | #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */ | |
321 | #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */ | |
322 | #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */ | |
323 | #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */ | |
324 | #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */ | |
325 | #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */ | |
326 | #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */ | |
327 | #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */ | |
328 | #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */ | |
329 | #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */ | |
330 | #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */ | |
331 | #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */ | |
332 | ||
333 | #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */ | |
334 | #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */ | |
335 | #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */ | |
336 | #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */ | |
337 | #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */ | |
338 | ||
339 | #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */ | |
340 | #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */ | |
341 | #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */ | |
342 | #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */ | |
343 | #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */ | |
344 | ||
345 | #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */ | |
346 | #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */ | |
347 | #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */ | |
348 | ||
349 | #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0) | |
350 | #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2) | |
351 | #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8) | |
352 | ||
353 | #define OP_VEB(pipeline, op, sub_opa, sub_opb) \ | |
354 | (3 << 13 | \ | |
355 | (pipeline) << 11 | \ | |
356 | (op) << 8 | \ | |
357 | (sub_opa) << 5 | \ | |
358 | (sub_opb)) | |
359 | ||
360 | #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0) | |
361 | #define OP_VEB_STATE OP_VEB(2, 4, 0, 2) | |
362 | #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3) | |
363 | ||
364 | struct parser_exec_state; | |
365 | ||
366 | typedef int (*parser_cmd_handler)(struct parser_exec_state *s); | |
367 | ||
368 | #define GVT_CMD_HASH_BITS 7 | |
369 | ||
370 | /* which DWords need address fix */ | |
371 | #define ADDR_FIX_1(x1) (1 << (x1)) | |
372 | #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2)) | |
373 | #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3)) | |
374 | #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4)) | |
375 | #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5)) | |
376 | ||
377 | struct cmd_info { | |
b007065a | 378 | const char *name; |
be1da707 ZW |
379 | u32 opcode; |
380 | ||
381 | #define F_LEN_MASK (1U<<0) | |
382 | #define F_LEN_CONST 1U | |
383 | #define F_LEN_VAR 0U | |
384 | ||
385 | /* | |
386 | * command has its own ip advance logic | |
387 | * e.g. MI_BATCH_START, MI_BATCH_END | |
388 | */ | |
389 | #define F_IP_ADVANCE_CUSTOM (1<<1) | |
390 | ||
391 | #define F_POST_HANDLE (1<<2) | |
392 | u32 flag; | |
393 | ||
394 | #define R_RCS (1 << RCS) | |
395 | #define R_VCS1 (1 << VCS) | |
396 | #define R_VCS2 (1 << VCS2) | |
397 | #define R_VCS (R_VCS1 | R_VCS2) | |
398 | #define R_BCS (1 << BCS) | |
399 | #define R_VECS (1 << VECS) | |
400 | #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) | |
401 | /* rings that support this cmd: BLT/RCS/VCS/VECS */ | |
2e679d48 | 402 | u16 rings; |
be1da707 ZW |
403 | |
404 | /* devices that support this cmd: SNB/IVB/HSW/... */ | |
2e679d48 | 405 | u16 devices; |
be1da707 ZW |
406 | |
407 | /* which DWords are address that need fix up. | |
408 | * bit 0 means a 32-bit non address operand in command | |
409 | * bit 1 means address operand, which could be 32-bit | |
410 | * or 64-bit depending on different architectures.( | |
411 | * defined by "gmadr_bytes_in_cmd" in intel_gvt. | |
412 | * No matter the address length, each address only takes | |
413 | * one bit in the bitmap. | |
414 | */ | |
2e679d48 | 415 | u16 addr_bitmap; |
be1da707 ZW |
416 | |
417 | /* flag == F_LEN_CONST : command length | |
418 | * flag == F_LEN_VAR : length bias bits | |
419 | * Note: length is in DWord | |
420 | */ | |
2e679d48 | 421 | u8 len; |
be1da707 ZW |
422 | |
423 | parser_cmd_handler handler; | |
424 | }; | |
425 | ||
426 | struct cmd_entry { | |
427 | struct hlist_node hlist; | |
b007065a | 428 | const struct cmd_info *info; |
be1da707 ZW |
429 | }; |
430 | ||
431 | enum { | |
432 | RING_BUFFER_INSTRUCTION, | |
433 | BATCH_BUFFER_INSTRUCTION, | |
434 | BATCH_BUFFER_2ND_LEVEL, | |
435 | }; | |
436 | ||
437 | enum { | |
438 | GTT_BUFFER, | |
439 | PPGTT_BUFFER | |
440 | }; | |
441 | ||
442 | struct parser_exec_state { | |
443 | struct intel_vgpu *vgpu; | |
444 | int ring_id; | |
445 | ||
446 | int buf_type; | |
447 | ||
448 | /* batch buffer address type */ | |
449 | int buf_addr_type; | |
450 | ||
451 | /* graphics memory address of ring buffer start */ | |
452 | unsigned long ring_start; | |
453 | unsigned long ring_size; | |
454 | unsigned long ring_head; | |
455 | unsigned long ring_tail; | |
456 | ||
457 | /* instruction graphics memory address */ | |
458 | unsigned long ip_gma; | |
459 | ||
460 | /* mapped va of the instr_gma */ | |
461 | void *ip_va; | |
462 | void *rb_va; | |
463 | ||
464 | void *ret_bb_va; | |
465 | /* next instruction when return from batch buffer to ring buffer */ | |
466 | unsigned long ret_ip_gma_ring; | |
467 | ||
468 | /* next instruction when return from 2nd batch buffer to batch buffer */ | |
469 | unsigned long ret_ip_gma_bb; | |
470 | ||
471 | /* batch buffer address type (GTT or PPGTT) | |
472 | * used when ret from 2nd level batch buffer | |
473 | */ | |
474 | int saved_buf_addr_type; | |
ef75c685 | 475 | bool is_ctx_wa; |
be1da707 | 476 | |
b007065a | 477 | const struct cmd_info *info; |
be1da707 ZW |
478 | |
479 | struct intel_vgpu_workload *workload; | |
480 | }; | |
481 | ||
482 | #define gmadr_dw_number(s) \ | |
483 | (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2) | |
484 | ||
999ccb40 | 485 | static unsigned long bypass_scan_mask = 0; |
be1da707 ZW |
486 | |
487 | /* ring ALL, type = 0 */ | |
ed8cce30 | 488 | static const struct sub_op_bits sub_op_mi[] = { |
be1da707 ZW |
489 | {31, 29}, |
490 | {28, 23}, | |
491 | }; | |
492 | ||
ed8cce30 | 493 | static const struct decode_info decode_info_mi = { |
be1da707 ZW |
494 | "MI", |
495 | OP_LEN_MI, | |
496 | ARRAY_SIZE(sub_op_mi), | |
497 | sub_op_mi, | |
498 | }; | |
499 | ||
500 | /* ring RCS, command type 2 */ | |
ed8cce30 | 501 | static const struct sub_op_bits sub_op_2d[] = { |
be1da707 ZW |
502 | {31, 29}, |
503 | {28, 22}, | |
504 | }; | |
505 | ||
ed8cce30 | 506 | static const struct decode_info decode_info_2d = { |
be1da707 ZW |
507 | "2D", |
508 | OP_LEN_2D, | |
509 | ARRAY_SIZE(sub_op_2d), | |
510 | sub_op_2d, | |
511 | }; | |
512 | ||
513 | /* ring RCS, command type 3 */ | |
ed8cce30 | 514 | static const struct sub_op_bits sub_op_3d_media[] = { |
be1da707 ZW |
515 | {31, 29}, |
516 | {28, 27}, | |
517 | {26, 24}, | |
518 | {23, 16}, | |
519 | }; | |
520 | ||
ed8cce30 | 521 | static const struct decode_info decode_info_3d_media = { |
be1da707 ZW |
522 | "3D_Media", |
523 | OP_LEN_3D_MEDIA, | |
524 | ARRAY_SIZE(sub_op_3d_media), | |
525 | sub_op_3d_media, | |
526 | }; | |
527 | ||
528 | /* ring VCS, command type 3 */ | |
ed8cce30 | 529 | static const struct sub_op_bits sub_op_mfx_vc[] = { |
be1da707 ZW |
530 | {31, 29}, |
531 | {28, 27}, | |
532 | {26, 24}, | |
533 | {23, 21}, | |
534 | {20, 16}, | |
535 | }; | |
536 | ||
ed8cce30 | 537 | static const struct decode_info decode_info_mfx_vc = { |
be1da707 ZW |
538 | "MFX_VC", |
539 | OP_LEN_MFX_VC, | |
540 | ARRAY_SIZE(sub_op_mfx_vc), | |
541 | sub_op_mfx_vc, | |
542 | }; | |
543 | ||
544 | /* ring VECS, command type 3 */ | |
ed8cce30 | 545 | static const struct sub_op_bits sub_op_vebox[] = { |
be1da707 ZW |
546 | {31, 29}, |
547 | {28, 27}, | |
548 | {26, 24}, | |
549 | {23, 21}, | |
550 | {20, 16}, | |
551 | }; | |
552 | ||
ed8cce30 | 553 | static const struct decode_info decode_info_vebox = { |
be1da707 ZW |
554 | "VEBOX", |
555 | OP_LEN_VEBOX, | |
556 | ARRAY_SIZE(sub_op_vebox), | |
557 | sub_op_vebox, | |
558 | }; | |
559 | ||
ed8cce30 | 560 | static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = { |
be1da707 ZW |
561 | [RCS] = { |
562 | &decode_info_mi, | |
563 | NULL, | |
564 | NULL, | |
565 | &decode_info_3d_media, | |
566 | NULL, | |
567 | NULL, | |
568 | NULL, | |
569 | NULL, | |
570 | }, | |
571 | ||
572 | [VCS] = { | |
573 | &decode_info_mi, | |
574 | NULL, | |
575 | NULL, | |
576 | &decode_info_mfx_vc, | |
577 | NULL, | |
578 | NULL, | |
579 | NULL, | |
580 | NULL, | |
581 | }, | |
582 | ||
583 | [BCS] = { | |
584 | &decode_info_mi, | |
585 | NULL, | |
586 | &decode_info_2d, | |
587 | NULL, | |
588 | NULL, | |
589 | NULL, | |
590 | NULL, | |
591 | NULL, | |
592 | }, | |
593 | ||
594 | [VECS] = { | |
595 | &decode_info_mi, | |
596 | NULL, | |
597 | NULL, | |
598 | &decode_info_vebox, | |
599 | NULL, | |
600 | NULL, | |
601 | NULL, | |
602 | NULL, | |
603 | }, | |
604 | ||
605 | [VCS2] = { | |
606 | &decode_info_mi, | |
607 | NULL, | |
608 | NULL, | |
609 | &decode_info_mfx_vc, | |
610 | NULL, | |
611 | NULL, | |
612 | NULL, | |
613 | NULL, | |
614 | }, | |
615 | }; | |
616 | ||
617 | static inline u32 get_opcode(u32 cmd, int ring_id) | |
618 | { | |
ed8cce30 | 619 | const struct decode_info *d_info; |
be1da707 | 620 | |
be1da707 ZW |
621 | d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; |
622 | if (d_info == NULL) | |
623 | return INVALID_OP; | |
624 | ||
625 | return cmd >> (32 - d_info->op_len); | |
626 | } | |
627 | ||
b007065a | 628 | static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt, |
be1da707 ZW |
629 | unsigned int opcode, int ring_id) |
630 | { | |
631 | struct cmd_entry *e; | |
632 | ||
633 | hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { | |
634 | if ((opcode == e->info->opcode) && | |
635 | (e->info->rings & (1 << ring_id))) | |
636 | return e->info; | |
637 | } | |
638 | return NULL; | |
639 | } | |
640 | ||
b007065a | 641 | static inline const struct cmd_info *get_cmd_info(struct intel_gvt *gvt, |
be1da707 ZW |
642 | u32 cmd, int ring_id) |
643 | { | |
644 | u32 opcode; | |
645 | ||
646 | opcode = get_opcode(cmd, ring_id); | |
647 | if (opcode == INVALID_OP) | |
648 | return NULL; | |
649 | ||
650 | return find_cmd_entry(gvt, opcode, ring_id); | |
651 | } | |
652 | ||
653 | static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low) | |
654 | { | |
655 | return (cmd >> low) & ((1U << (hi - low + 1)) - 1); | |
656 | } | |
657 | ||
658 | static inline void print_opcode(u32 cmd, int ring_id) | |
659 | { | |
ed8cce30 | 660 | const struct decode_info *d_info; |
be1da707 ZW |
661 | int i; |
662 | ||
be1da707 ZW |
663 | d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)]; |
664 | if (d_info == NULL) | |
665 | return; | |
666 | ||
627c845c | 667 | gvt_dbg_cmd("opcode=0x%x %s sub_ops:", |
be1da707 ZW |
668 | cmd >> (32 - d_info->op_len), d_info->name); |
669 | ||
670 | for (i = 0; i < d_info->nr_sub_op; i++) | |
671 | pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi, | |
672 | d_info->sub_op[i].low)); | |
673 | ||
674 | pr_err("\n"); | |
675 | } | |
676 | ||
677 | static inline u32 *cmd_ptr(struct parser_exec_state *s, int index) | |
678 | { | |
679 | return s->ip_va + (index << 2); | |
680 | } | |
681 | ||
682 | static inline u32 cmd_val(struct parser_exec_state *s, int index) | |
683 | { | |
684 | return *cmd_ptr(s, index); | |
685 | } | |
686 | ||
687 | static void parser_exec_state_dump(struct parser_exec_state *s) | |
688 | { | |
689 | int cnt = 0; | |
690 | int i; | |
691 | ||
627c845c | 692 | gvt_dbg_cmd(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)" |
be1da707 ZW |
693 | " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id, |
694 | s->ring_id, s->ring_start, s->ring_start + s->ring_size, | |
695 | s->ring_head, s->ring_tail); | |
696 | ||
627c845c | 697 | gvt_dbg_cmd(" %s %s ip_gma(%08lx) ", |
be1da707 ZW |
698 | s->buf_type == RING_BUFFER_INSTRUCTION ? |
699 | "RING_BUFFER" : "BATCH_BUFFER", | |
700 | s->buf_addr_type == GTT_BUFFER ? | |
701 | "GTT" : "PPGTT", s->ip_gma); | |
702 | ||
703 | if (s->ip_va == NULL) { | |
627c845c | 704 | gvt_dbg_cmd(" ip_va(NULL)"); |
be1da707 ZW |
705 | return; |
706 | } | |
707 | ||
627c845c | 708 | gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n", |
be1da707 ZW |
709 | s->ip_va, cmd_val(s, 0), cmd_val(s, 1), |
710 | cmd_val(s, 2), cmd_val(s, 3)); | |
711 | ||
712 | print_opcode(cmd_val(s, 0), s->ring_id); | |
713 | ||
be1da707 ZW |
714 | s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12); |
715 | ||
716 | while (cnt < 1024) { | |
e4aeba69 | 717 | gvt_dbg_cmd("ip_va=%p: ", s->ip_va); |
be1da707 | 718 | for (i = 0; i < 8; i++) |
e4aeba69 CD |
719 | gvt_dbg_cmd("%08x ", cmd_val(s, i)); |
720 | gvt_dbg_cmd("\n"); | |
be1da707 ZW |
721 | |
722 | s->ip_va += 8 * sizeof(u32); | |
723 | cnt += 8; | |
724 | } | |
725 | } | |
726 | ||
727 | static inline void update_ip_va(struct parser_exec_state *s) | |
728 | { | |
729 | unsigned long len = 0; | |
730 | ||
731 | if (WARN_ON(s->ring_head == s->ring_tail)) | |
732 | return; | |
733 | ||
734 | if (s->buf_type == RING_BUFFER_INSTRUCTION) { | |
735 | unsigned long ring_top = s->ring_start + s->ring_size; | |
736 | ||
737 | if (s->ring_head > s->ring_tail) { | |
738 | if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top) | |
739 | len = (s->ip_gma - s->ring_head); | |
740 | else if (s->ip_gma >= s->ring_start && | |
741 | s->ip_gma <= s->ring_tail) | |
742 | len = (ring_top - s->ring_head) + | |
743 | (s->ip_gma - s->ring_start); | |
744 | } else | |
745 | len = (s->ip_gma - s->ring_head); | |
746 | ||
747 | s->ip_va = s->rb_va + len; | |
748 | } else {/* shadow batch buffer */ | |
749 | s->ip_va = s->ret_bb_va; | |
750 | } | |
751 | } | |
752 | ||
753 | static inline int ip_gma_set(struct parser_exec_state *s, | |
754 | unsigned long ip_gma) | |
755 | { | |
756 | WARN_ON(!IS_ALIGNED(ip_gma, 4)); | |
757 | ||
758 | s->ip_gma = ip_gma; | |
759 | update_ip_va(s); | |
760 | return 0; | |
761 | } | |
762 | ||
763 | static inline int ip_gma_advance(struct parser_exec_state *s, | |
764 | unsigned int dw_len) | |
765 | { | |
766 | s->ip_gma += (dw_len << 2); | |
767 | ||
768 | if (s->buf_type == RING_BUFFER_INSTRUCTION) { | |
769 | if (s->ip_gma >= s->ring_start + s->ring_size) | |
770 | s->ip_gma -= s->ring_size; | |
771 | update_ip_va(s); | |
772 | } else { | |
773 | s->ip_va += (dw_len << 2); | |
774 | } | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
b007065a | 779 | static inline int get_cmd_length(const struct cmd_info *info, u32 cmd) |
be1da707 ZW |
780 | { |
781 | if ((info->flag & F_LEN_MASK) == F_LEN_CONST) | |
782 | return info->len; | |
783 | else | |
784 | return (cmd & ((1U << info->len) - 1)) + 2; | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static inline int cmd_length(struct parser_exec_state *s) | |
789 | { | |
790 | return get_cmd_length(s->info, cmd_val(s, 0)); | |
791 | } | |
792 | ||
793 | /* do not remove this, some platform may need clflush here */ | |
794 | #define patch_value(s, addr, val) do { \ | |
795 | *addr = val; \ | |
796 | } while (0) | |
797 | ||
798 | static bool is_shadowed_mmio(unsigned int offset) | |
799 | { | |
800 | bool ret = false; | |
801 | ||
802 | if ((offset == 0x2168) || /*BB current head register UDW */ | |
803 | (offset == 0x2140) || /*BB current header register */ | |
804 | (offset == 0x211c) || /*second BB header register UDW */ | |
805 | (offset == 0x2114)) { /*second BB header register UDW */ | |
806 | ret = true; | |
807 | } | |
808 | return ret; | |
809 | } | |
810 | ||
4938ca90 ZY |
811 | static inline bool is_force_nonpriv_mmio(unsigned int offset) |
812 | { | |
813 | return (offset >= 0x24d0 && offset < 0x2500); | |
814 | } | |
815 | ||
816 | static int force_nonpriv_reg_handler(struct parser_exec_state *s, | |
cb8ba171 | 817 | unsigned int offset, unsigned int index, char *cmd) |
4938ca90 ZY |
818 | { |
819 | struct intel_gvt *gvt = s->vgpu->gvt; | |
cb8ba171 | 820 | unsigned int data; |
3d8b9e25 ZY |
821 | u32 ring_base; |
822 | u32 nopid; | |
823 | struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; | |
4938ca90 | 824 | |
cb8ba171 ZY |
825 | if (!strcmp(cmd, "lri")) |
826 | data = cmd_val(s, index + 1); | |
827 | else { | |
828 | gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n", | |
829 | offset, cmd); | |
830 | return -EINVAL; | |
831 | } | |
832 | ||
3d8b9e25 ZY |
833 | ring_base = dev_priv->engine[s->ring_id]->mmio_base; |
834 | nopid = i915_mmio_reg_offset(RING_NOPID(ring_base)); | |
835 | ||
836 | if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) && | |
837 | data != nopid) { | |
4938ca90 ZY |
838 | gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n", |
839 | offset, data); | |
0438a105 ZY |
840 | patch_value(s, cmd_ptr(s, index), nopid); |
841 | return 0; | |
4938ca90 ZY |
842 | } |
843 | return 0; | |
844 | } | |
845 | ||
f402f2d6 WL |
846 | static inline bool is_mocs_mmio(unsigned int offset) |
847 | { | |
848 | return ((offset >= 0xc800) && (offset <= 0xcff8)) || | |
849 | ((offset >= 0xb020) && (offset <= 0xb0a0)); | |
850 | } | |
851 | ||
852 | static int mocs_cmd_reg_handler(struct parser_exec_state *s, | |
853 | unsigned int offset, unsigned int index) | |
854 | { | |
855 | if (!is_mocs_mmio(offset)) | |
856 | return -EINVAL; | |
857 | vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); | |
858 | return 0; | |
859 | } | |
860 | ||
be1da707 ZW |
861 | static int cmd_reg_handler(struct parser_exec_state *s, |
862 | unsigned int offset, unsigned int index, char *cmd) | |
863 | { | |
864 | struct intel_vgpu *vgpu = s->vgpu; | |
865 | struct intel_gvt *gvt = vgpu->gvt; | |
6cef21a1 | 866 | u32 ctx_sr_ctl; |
be1da707 ZW |
867 | |
868 | if (offset + 4 > gvt->device_info.mmio_size) { | |
695fbc08 | 869 | gvt_vgpu_err("%s access to (%x) outside of MMIO range\n", |
be1da707 | 870 | cmd, offset); |
5c56883a | 871 | return -EFAULT; |
be1da707 ZW |
872 | } |
873 | ||
874 | if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) { | |
695fbc08 TZ |
875 | gvt_vgpu_err("%s access to non-render register (%x)\n", |
876 | cmd, offset); | |
8d458ea0 | 877 | return -EBADRQC; |
be1da707 ZW |
878 | } |
879 | ||
880 | if (is_shadowed_mmio(offset)) { | |
695fbc08 | 881 | gvt_vgpu_err("found access of shadowed MMIO %x\n", offset); |
be1da707 ZW |
882 | return 0; |
883 | } | |
884 | ||
f402f2d6 WL |
885 | if (is_mocs_mmio(offset) && |
886 | mocs_cmd_reg_handler(s, offset, index)) | |
887 | return -EINVAL; | |
888 | ||
4938ca90 | 889 | if (is_force_nonpriv_mmio(offset) && |
cb8ba171 | 890 | force_nonpriv_reg_handler(s, offset, index, cmd)) |
5c56883a | 891 | return -EPERM; |
4938ca90 | 892 | |
be1da707 ZW |
893 | if (offset == i915_mmio_reg_offset(DERRMR) || |
894 | offset == i915_mmio_reg_offset(FORCEWAKE_MT)) { | |
895 | /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */ | |
896 | patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE); | |
897 | } | |
898 | ||
6cef21a1 HY |
899 | /* TODO |
900 | * Right now only scan LRI command on KBL and in inhibit context. | |
901 | * It's good enough to support initializing mmio by lri command in | |
902 | * vgpu inhibit context on KBL. | |
903 | */ | |
c3b5a843 | 904 | if ((IS_KABYLAKE(s->vgpu->gvt->dev_priv) |
905 | || IS_COFFEELAKE(s->vgpu->gvt->dev_priv)) && | |
6cef21a1 HY |
906 | intel_gvt_mmio_is_in_ctx(gvt, offset) && |
907 | !strncmp(cmd, "lri", 3)) { | |
908 | intel_gvt_hypervisor_read_gpa(s->vgpu, | |
909 | s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4); | |
910 | /* check inhibit context */ | |
911 | if (ctx_sr_ctl & 1) { | |
912 | u32 data = cmd_val(s, index + 1); | |
913 | ||
914 | if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset)) | |
915 | intel_vgpu_mask_mmio_write(vgpu, | |
916 | offset, &data, 4); | |
917 | else | |
918 | vgpu_vreg(vgpu, offset) = data; | |
919 | } | |
920 | } | |
921 | ||
be1da707 ZW |
922 | /* TODO: Update the global mask if this MMIO is a masked-MMIO */ |
923 | intel_gvt_mmio_set_cmd_accessed(gvt, offset); | |
924 | return 0; | |
925 | } | |
926 | ||
927 | #define cmd_reg(s, i) \ | |
928 | (cmd_val(s, i) & GENMASK(22, 2)) | |
929 | ||
930 | #define cmd_reg_inhibit(s, i) \ | |
931 | (cmd_val(s, i) & GENMASK(22, 18)) | |
932 | ||
933 | #define cmd_gma(s, i) \ | |
934 | (cmd_val(s, i) & GENMASK(31, 2)) | |
935 | ||
936 | #define cmd_gma_hi(s, i) \ | |
937 | (cmd_val(s, i) & GENMASK(15, 0)) | |
938 | ||
939 | static int cmd_handler_lri(struct parser_exec_state *s) | |
940 | { | |
941 | int i, ret = 0; | |
942 | int cmd_len = cmd_length(s); | |
943 | struct intel_gvt *gvt = s->vgpu->gvt; | |
944 | ||
945 | for (i = 1; i < cmd_len; i += 2) { | |
946 | if (IS_BROADWELL(gvt->dev_priv) && | |
947 | (s->ring_id != RCS)) { | |
948 | if (s->ring_id == BCS && | |
949 | cmd_reg(s, i) == | |
950 | i915_mmio_reg_offset(DERRMR)) | |
951 | ret |= 0; | |
952 | else | |
5c56883a | 953 | ret |= (cmd_reg_inhibit(s, i)) ? |
954 | -EBADRQC : 0; | |
be1da707 ZW |
955 | } |
956 | if (ret) | |
957 | break; | |
958 | ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri"); | |
5c56883a | 959 | if (ret) |
960 | break; | |
be1da707 ZW |
961 | } |
962 | return ret; | |
963 | } | |
964 | ||
965 | static int cmd_handler_lrr(struct parser_exec_state *s) | |
966 | { | |
967 | int i, ret = 0; | |
968 | int cmd_len = cmd_length(s); | |
969 | ||
970 | for (i = 1; i < cmd_len; i += 2) { | |
971 | if (IS_BROADWELL(s->vgpu->gvt->dev_priv)) | |
972 | ret |= ((cmd_reg_inhibit(s, i) || | |
973 | (cmd_reg_inhibit(s, i + 1)))) ? | |
5c56883a | 974 | -EBADRQC : 0; |
be1da707 ZW |
975 | if (ret) |
976 | break; | |
977 | ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src"); | |
5c56883a | 978 | if (ret) |
979 | break; | |
be1da707 | 980 | ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst"); |
5c56883a | 981 | if (ret) |
982 | break; | |
be1da707 ZW |
983 | } |
984 | return ret; | |
985 | } | |
986 | ||
987 | static inline int cmd_address_audit(struct parser_exec_state *s, | |
988 | unsigned long guest_gma, int op_size, bool index_mode); | |
989 | ||
990 | static int cmd_handler_lrm(struct parser_exec_state *s) | |
991 | { | |
992 | struct intel_gvt *gvt = s->vgpu->gvt; | |
993 | int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; | |
994 | unsigned long gma; | |
995 | int i, ret = 0; | |
996 | int cmd_len = cmd_length(s); | |
997 | ||
998 | for (i = 1; i < cmd_len;) { | |
999 | if (IS_BROADWELL(gvt->dev_priv)) | |
5c56883a | 1000 | ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0; |
be1da707 ZW |
1001 | if (ret) |
1002 | break; | |
1003 | ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm"); | |
5c56883a | 1004 | if (ret) |
1005 | break; | |
be1da707 ZW |
1006 | if (cmd_val(s, 0) & (1 << 22)) { |
1007 | gma = cmd_gma(s, i + 1); | |
1008 | if (gmadr_bytes == 8) | |
1009 | gma |= (cmd_gma_hi(s, i + 2)) << 32; | |
1010 | ret |= cmd_address_audit(s, gma, sizeof(u32), false); | |
5c56883a | 1011 | if (ret) |
1012 | break; | |
be1da707 ZW |
1013 | } |
1014 | i += gmadr_dw_number(s) + 1; | |
1015 | } | |
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | static int cmd_handler_srm(struct parser_exec_state *s) | |
1020 | { | |
1021 | int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; | |
1022 | unsigned long gma; | |
1023 | int i, ret = 0; | |
1024 | int cmd_len = cmd_length(s); | |
1025 | ||
1026 | for (i = 1; i < cmd_len;) { | |
1027 | ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm"); | |
5c56883a | 1028 | if (ret) |
1029 | break; | |
be1da707 ZW |
1030 | if (cmd_val(s, 0) & (1 << 22)) { |
1031 | gma = cmd_gma(s, i + 1); | |
1032 | if (gmadr_bytes == 8) | |
1033 | gma |= (cmd_gma_hi(s, i + 2)) << 32; | |
1034 | ret |= cmd_address_audit(s, gma, sizeof(u32), false); | |
5c56883a | 1035 | if (ret) |
1036 | break; | |
be1da707 ZW |
1037 | } |
1038 | i += gmadr_dw_number(s) + 1; | |
1039 | } | |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | struct cmd_interrupt_event { | |
1044 | int pipe_control_notify; | |
1045 | int mi_flush_dw; | |
1046 | int mi_user_interrupt; | |
1047 | }; | |
1048 | ||
999ccb40 | 1049 | static struct cmd_interrupt_event cmd_interrupt_events[] = { |
be1da707 ZW |
1050 | [RCS] = { |
1051 | .pipe_control_notify = RCS_PIPE_CONTROL, | |
1052 | .mi_flush_dw = INTEL_GVT_EVENT_RESERVED, | |
1053 | .mi_user_interrupt = RCS_MI_USER_INTERRUPT, | |
1054 | }, | |
1055 | [BCS] = { | |
1056 | .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, | |
1057 | .mi_flush_dw = BCS_MI_FLUSH_DW, | |
1058 | .mi_user_interrupt = BCS_MI_USER_INTERRUPT, | |
1059 | }, | |
1060 | [VCS] = { | |
1061 | .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, | |
1062 | .mi_flush_dw = VCS_MI_FLUSH_DW, | |
1063 | .mi_user_interrupt = VCS_MI_USER_INTERRUPT, | |
1064 | }, | |
1065 | [VCS2] = { | |
1066 | .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, | |
1067 | .mi_flush_dw = VCS2_MI_FLUSH_DW, | |
1068 | .mi_user_interrupt = VCS2_MI_USER_INTERRUPT, | |
1069 | }, | |
1070 | [VECS] = { | |
1071 | .pipe_control_notify = INTEL_GVT_EVENT_RESERVED, | |
1072 | .mi_flush_dw = VECS_MI_FLUSH_DW, | |
1073 | .mi_user_interrupt = VECS_MI_USER_INTERRUPT, | |
1074 | }, | |
1075 | }; | |
1076 | ||
1077 | static int cmd_handler_pipe_control(struct parser_exec_state *s) | |
1078 | { | |
1079 | int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; | |
1080 | unsigned long gma; | |
1081 | bool index_mode = false; | |
1082 | unsigned int post_sync; | |
1083 | int ret = 0; | |
1084 | ||
1085 | post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14; | |
1086 | ||
1087 | /* LRI post sync */ | |
1088 | if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE) | |
1089 | ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl"); | |
1090 | /* post sync */ | |
1091 | else if (post_sync) { | |
1092 | if (post_sync == 2) | |
1093 | ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl"); | |
1094 | else if (post_sync == 3) | |
1095 | ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl"); | |
1096 | else if (post_sync == 1) { | |
1097 | /* check ggtt*/ | |
3f765a34 | 1098 | if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) { |
be1da707 ZW |
1099 | gma = cmd_val(s, 2) & GENMASK(31, 3); |
1100 | if (gmadr_bytes == 8) | |
1101 | gma |= (cmd_gma_hi(s, 3)) << 32; | |
1102 | /* Store Data Index */ | |
1103 | if (cmd_val(s, 1) & (1 << 21)) | |
1104 | index_mode = true; | |
1105 | ret |= cmd_address_audit(s, gma, sizeof(u64), | |
1106 | index_mode); | |
1107 | } | |
1108 | } | |
1109 | } | |
1110 | ||
1111 | if (ret) | |
1112 | return ret; | |
1113 | ||
1114 | if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY) | |
1115 | set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify, | |
1116 | s->workload->pending_events); | |
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s) | |
1121 | { | |
1122 | set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt, | |
1123 | s->workload->pending_events); | |
5da795b0 | 1124 | patch_value(s, cmd_ptr(s, 0), MI_NOOP); |
be1da707 ZW |
1125 | return 0; |
1126 | } | |
1127 | ||
1128 | static int cmd_advance_default(struct parser_exec_state *s) | |
1129 | { | |
1130 | return ip_gma_advance(s, cmd_length(s)); | |
1131 | } | |
1132 | ||
1133 | static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s) | |
1134 | { | |
1135 | int ret; | |
1136 | ||
1137 | if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { | |
1138 | s->buf_type = BATCH_BUFFER_INSTRUCTION; | |
1139 | ret = ip_gma_set(s, s->ret_ip_gma_bb); | |
1140 | s->buf_addr_type = s->saved_buf_addr_type; | |
1141 | } else { | |
1142 | s->buf_type = RING_BUFFER_INSTRUCTION; | |
1143 | s->buf_addr_type = GTT_BUFFER; | |
1144 | if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size) | |
1145 | s->ret_ip_gma_ring -= s->ring_size; | |
1146 | ret = ip_gma_set(s, s->ret_ip_gma_ring); | |
1147 | } | |
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | struct mi_display_flip_command_info { | |
1152 | int pipe; | |
1153 | int plane; | |
1154 | int event; | |
1155 | i915_reg_t stride_reg; | |
1156 | i915_reg_t ctrl_reg; | |
1157 | i915_reg_t surf_reg; | |
1158 | u64 stride_val; | |
1159 | u64 tile_val; | |
1160 | u64 surf_val; | |
1161 | bool async_flip; | |
1162 | }; | |
1163 | ||
1164 | struct plane_code_mapping { | |
1165 | int pipe; | |
1166 | int plane; | |
1167 | int event; | |
1168 | }; | |
1169 | ||
1170 | static int gen8_decode_mi_display_flip(struct parser_exec_state *s, | |
1171 | struct mi_display_flip_command_info *info) | |
1172 | { | |
1173 | struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; | |
1174 | struct plane_code_mapping gen8_plane_code[] = { | |
1175 | [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, | |
1176 | [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, | |
1177 | [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, | |
1178 | [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, | |
1179 | [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, | |
1180 | [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, | |
1181 | }; | |
1182 | u32 dword0, dword1, dword2; | |
1183 | u32 v; | |
1184 | ||
1185 | dword0 = cmd_val(s, 0); | |
1186 | dword1 = cmd_val(s, 1); | |
1187 | dword2 = cmd_val(s, 2); | |
1188 | ||
1189 | v = (dword0 & GENMASK(21, 19)) >> 19; | |
1190 | if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code))) | |
5c56883a | 1191 | return -EBADRQC; |
be1da707 ZW |
1192 | |
1193 | info->pipe = gen8_plane_code[v].pipe; | |
1194 | info->plane = gen8_plane_code[v].plane; | |
1195 | info->event = gen8_plane_code[v].event; | |
1196 | info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; | |
1197 | info->tile_val = (dword1 & 0x1); | |
1198 | info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; | |
1199 | info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); | |
1200 | ||
1201 | if (info->plane == PLANE_A) { | |
1202 | info->ctrl_reg = DSPCNTR(info->pipe); | |
1203 | info->stride_reg = DSPSTRIDE(info->pipe); | |
1204 | info->surf_reg = DSPSURF(info->pipe); | |
1205 | } else if (info->plane == PLANE_B) { | |
1206 | info->ctrl_reg = SPRCTL(info->pipe); | |
1207 | info->stride_reg = SPRSTRIDE(info->pipe); | |
1208 | info->surf_reg = SPRSURF(info->pipe); | |
1209 | } else { | |
1210 | WARN_ON(1); | |
5c56883a | 1211 | return -EBADRQC; |
be1da707 ZW |
1212 | } |
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static int skl_decode_mi_display_flip(struct parser_exec_state *s, | |
1217 | struct mi_display_flip_command_info *info) | |
1218 | { | |
1219 | struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; | |
695fbc08 | 1220 | struct intel_vgpu *vgpu = s->vgpu; |
be1da707 ZW |
1221 | u32 dword0 = cmd_val(s, 0); |
1222 | u32 dword1 = cmd_val(s, 1); | |
1223 | u32 dword2 = cmd_val(s, 2); | |
1224 | u32 plane = (dword0 & GENMASK(12, 8)) >> 8; | |
1225 | ||
6e27d514 XH |
1226 | info->plane = PRIMARY_PLANE; |
1227 | ||
be1da707 ZW |
1228 | switch (plane) { |
1229 | case MI_DISPLAY_FLIP_SKL_PLANE_1_A: | |
1230 | info->pipe = PIPE_A; | |
1231 | info->event = PRIMARY_A_FLIP_DONE; | |
1232 | break; | |
1233 | case MI_DISPLAY_FLIP_SKL_PLANE_1_B: | |
1234 | info->pipe = PIPE_B; | |
1235 | info->event = PRIMARY_B_FLIP_DONE; | |
1236 | break; | |
1237 | case MI_DISPLAY_FLIP_SKL_PLANE_1_C: | |
64fafcf5 | 1238 | info->pipe = PIPE_C; |
be1da707 ZW |
1239 | info->event = PRIMARY_C_FLIP_DONE; |
1240 | break; | |
6e27d514 XH |
1241 | |
1242 | case MI_DISPLAY_FLIP_SKL_PLANE_2_A: | |
1243 | info->pipe = PIPE_A; | |
1244 | info->event = SPRITE_A_FLIP_DONE; | |
1245 | info->plane = SPRITE_PLANE; | |
1246 | break; | |
1247 | case MI_DISPLAY_FLIP_SKL_PLANE_2_B: | |
1248 | info->pipe = PIPE_B; | |
1249 | info->event = SPRITE_B_FLIP_DONE; | |
1250 | info->plane = SPRITE_PLANE; | |
1251 | break; | |
1252 | case MI_DISPLAY_FLIP_SKL_PLANE_2_C: | |
1253 | info->pipe = PIPE_C; | |
1254 | info->event = SPRITE_C_FLIP_DONE; | |
1255 | info->plane = SPRITE_PLANE; | |
1256 | break; | |
1257 | ||
be1da707 | 1258 | default: |
695fbc08 | 1259 | gvt_vgpu_err("unknown plane code %d\n", plane); |
5c56883a | 1260 | return -EBADRQC; |
be1da707 ZW |
1261 | } |
1262 | ||
be1da707 ZW |
1263 | info->stride_val = (dword1 & GENMASK(15, 6)) >> 6; |
1264 | info->tile_val = (dword1 & GENMASK(2, 0)); | |
1265 | info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; | |
1266 | info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); | |
1267 | ||
1268 | info->ctrl_reg = DSPCNTR(info->pipe); | |
1269 | info->stride_reg = DSPSTRIDE(info->pipe); | |
1270 | info->surf_reg = DSPSURF(info->pipe); | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static int gen8_check_mi_display_flip(struct parser_exec_state *s, | |
1276 | struct mi_display_flip_command_info *info) | |
1277 | { | |
1278 | struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; | |
1279 | u32 stride, tile; | |
1280 | ||
1281 | if (!info->async_flip) | |
1282 | return 0; | |
1283 | ||
c3b5a843 | 1284 | if (INTEL_GEN(dev_priv) >= 9) { |
90551a12 ZW |
1285 | stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); |
1286 | tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & | |
be1da707 ZW |
1287 | GENMASK(12, 10)) >> 10; |
1288 | } else { | |
90551a12 | 1289 | stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & |
be1da707 | 1290 | GENMASK(15, 6)) >> 6; |
90551a12 | 1291 | tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; |
be1da707 ZW |
1292 | } |
1293 | ||
1294 | if (stride != info->stride_val) | |
1295 | gvt_dbg_cmd("cannot change stride during async flip\n"); | |
1296 | ||
1297 | if (tile != info->tile_val) | |
1298 | gvt_dbg_cmd("cannot change tile during async flip\n"); | |
1299 | ||
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static int gen8_update_plane_mmio_from_mi_display_flip( | |
1304 | struct parser_exec_state *s, | |
1305 | struct mi_display_flip_command_info *info) | |
1306 | { | |
1307 | struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; | |
1308 | struct intel_vgpu *vgpu = s->vgpu; | |
1309 | ||
90551a12 | 1310 | set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), |
99c79fd4 | 1311 | info->surf_val << 12); |
c3b5a843 | 1312 | if (INTEL_GEN(dev_priv) >= 9) { |
90551a12 | 1313 | set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), |
99c79fd4 | 1314 | info->stride_val); |
90551a12 | 1315 | set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), |
99c79fd4 DC |
1316 | info->tile_val << 10); |
1317 | } else { | |
90551a12 | 1318 | set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), |
99c79fd4 | 1319 | info->stride_val << 6); |
90551a12 | 1320 | set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), |
99c79fd4 DC |
1321 | info->tile_val << 10); |
1322 | } | |
be1da707 | 1323 | |
90551a12 | 1324 | vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++; |
be1da707 ZW |
1325 | intel_vgpu_trigger_virtual_event(vgpu, info->event); |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static int decode_mi_display_flip(struct parser_exec_state *s, | |
1330 | struct mi_display_flip_command_info *info) | |
1331 | { | |
1332 | struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv; | |
1333 | ||
1334 | if (IS_BROADWELL(dev_priv)) | |
1335 | return gen8_decode_mi_display_flip(s, info); | |
c3b5a843 | 1336 | if (INTEL_GEN(dev_priv) >= 9) |
be1da707 ZW |
1337 | return skl_decode_mi_display_flip(s, info); |
1338 | ||
1339 | return -ENODEV; | |
1340 | } | |
1341 | ||
1342 | static int check_mi_display_flip(struct parser_exec_state *s, | |
1343 | struct mi_display_flip_command_info *info) | |
1344 | { | |
f093f182 | 1345 | return gen8_check_mi_display_flip(s, info); |
be1da707 ZW |
1346 | } |
1347 | ||
1348 | static int update_plane_mmio_from_mi_display_flip( | |
1349 | struct parser_exec_state *s, | |
1350 | struct mi_display_flip_command_info *info) | |
1351 | { | |
f093f182 | 1352 | return gen8_update_plane_mmio_from_mi_display_flip(s, info); |
be1da707 ZW |
1353 | } |
1354 | ||
1355 | static int cmd_handler_mi_display_flip(struct parser_exec_state *s) | |
1356 | { | |
1357 | struct mi_display_flip_command_info info; | |
695fbc08 | 1358 | struct intel_vgpu *vgpu = s->vgpu; |
be1da707 ZW |
1359 | int ret; |
1360 | int i; | |
1361 | int len = cmd_length(s); | |
1362 | ||
1363 | ret = decode_mi_display_flip(s, &info); | |
1364 | if (ret) { | |
695fbc08 | 1365 | gvt_vgpu_err("fail to decode MI display flip command\n"); |
be1da707 ZW |
1366 | return ret; |
1367 | } | |
1368 | ||
1369 | ret = check_mi_display_flip(s, &info); | |
1370 | if (ret) { | |
695fbc08 | 1371 | gvt_vgpu_err("invalid MI display flip command\n"); |
be1da707 ZW |
1372 | return ret; |
1373 | } | |
1374 | ||
1375 | ret = update_plane_mmio_from_mi_display_flip(s, &info); | |
1376 | if (ret) { | |
695fbc08 | 1377 | gvt_vgpu_err("fail to update plane mmio\n"); |
be1da707 ZW |
1378 | return ret; |
1379 | } | |
1380 | ||
1381 | for (i = 0; i < len; i++) | |
1382 | patch_value(s, cmd_ptr(s, i), MI_NOOP); | |
1383 | return 0; | |
1384 | } | |
1385 | ||
1386 | static bool is_wait_for_flip_pending(u32 cmd) | |
1387 | { | |
1388 | return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING | | |
1389 | MI_WAIT_FOR_PLANE_B_FLIP_PENDING | | |
1390 | MI_WAIT_FOR_PLANE_C_FLIP_PENDING | | |
1391 | MI_WAIT_FOR_SPRITE_A_FLIP_PENDING | | |
1392 | MI_WAIT_FOR_SPRITE_B_FLIP_PENDING | | |
1393 | MI_WAIT_FOR_SPRITE_C_FLIP_PENDING); | |
1394 | } | |
1395 | ||
1396 | static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s) | |
1397 | { | |
1398 | u32 cmd = cmd_val(s, 0); | |
1399 | ||
1400 | if (!is_wait_for_flip_pending(cmd)) | |
1401 | return 0; | |
1402 | ||
1403 | patch_value(s, cmd_ptr(s, 0), MI_NOOP); | |
1404 | return 0; | |
1405 | } | |
1406 | ||
1407 | static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index) | |
1408 | { | |
1409 | unsigned long addr; | |
1410 | unsigned long gma_high, gma_low; | |
5c56883a | 1411 | struct intel_vgpu *vgpu = s->vgpu; |
1412 | int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd; | |
be1da707 | 1413 | |
5c56883a | 1414 | if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) { |
1415 | gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes); | |
be1da707 | 1416 | return INTEL_GVT_INVALID_ADDR; |
5c56883a | 1417 | } |
be1da707 ZW |
1418 | |
1419 | gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK; | |
1420 | if (gmadr_bytes == 4) { | |
1421 | addr = gma_low; | |
1422 | } else { | |
1423 | gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK; | |
1424 | addr = (((unsigned long)gma_high) << 32) | gma_low; | |
1425 | } | |
1426 | return addr; | |
1427 | } | |
1428 | ||
1429 | static inline int cmd_address_audit(struct parser_exec_state *s, | |
1430 | unsigned long guest_gma, int op_size, bool index_mode) | |
1431 | { | |
1432 | struct intel_vgpu *vgpu = s->vgpu; | |
1433 | u32 max_surface_size = vgpu->gvt->device_info.max_surface_size; | |
1434 | int i; | |
1435 | int ret; | |
1436 | ||
1437 | if (op_size > max_surface_size) { | |
695fbc08 TZ |
1438 | gvt_vgpu_err("command address audit fail name %s\n", |
1439 | s->info->name); | |
5c56883a | 1440 | return -EFAULT; |
be1da707 ZW |
1441 | } |
1442 | ||
1443 | if (index_mode) { | |
13bcb80b | 1444 | if (guest_gma >= I915_GTT_PAGE_SIZE) { |
5c56883a | 1445 | ret = -EFAULT; |
be1da707 ZW |
1446 | goto err; |
1447 | } | |
64d8bb83 | 1448 | } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) { |
5c56883a | 1449 | ret = -EFAULT; |
be1da707 ZW |
1450 | goto err; |
1451 | } | |
64d8bb83 | 1452 | |
be1da707 | 1453 | return 0; |
64d8bb83 | 1454 | |
be1da707 | 1455 | err: |
695fbc08 | 1456 | gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", |
be1da707 ZW |
1457 | s->info->name, guest_gma, op_size); |
1458 | ||
1459 | pr_err("cmd dump: "); | |
1460 | for (i = 0; i < cmd_length(s); i++) { | |
1461 | if (!(i % 4)) | |
1462 | pr_err("\n%08x ", cmd_val(s, i)); | |
1463 | else | |
1464 | pr_err("%08x ", cmd_val(s, i)); | |
1465 | } | |
1466 | pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n", | |
1467 | vgpu->id, | |
1468 | vgpu_aperture_gmadr_base(vgpu), | |
1469 | vgpu_aperture_gmadr_end(vgpu), | |
1470 | vgpu_hidden_gmadr_base(vgpu), | |
1471 | vgpu_hidden_gmadr_end(vgpu)); | |
1472 | return ret; | |
1473 | } | |
1474 | ||
1475 | static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s) | |
1476 | { | |
1477 | int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; | |
1478 | int op_size = (cmd_length(s) - 3) * sizeof(u32); | |
1479 | int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0; | |
1480 | unsigned long gma, gma_low, gma_high; | |
1481 | int ret = 0; | |
1482 | ||
1483 | /* check ppggt */ | |
1484 | if (!(cmd_val(s, 0) & (1 << 22))) | |
1485 | return 0; | |
1486 | ||
1487 | gma = cmd_val(s, 2) & GENMASK(31, 2); | |
1488 | ||
1489 | if (gmadr_bytes == 8) { | |
1490 | gma_low = cmd_val(s, 1) & GENMASK(31, 2); | |
1491 | gma_high = cmd_val(s, 2) & GENMASK(15, 0); | |
1492 | gma = (gma_high << 32) | gma_low; | |
1493 | core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0; | |
1494 | } | |
1495 | ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false); | |
1496 | return ret; | |
1497 | } | |
1498 | ||
1499 | static inline int unexpected_cmd(struct parser_exec_state *s) | |
1500 | { | |
695fbc08 TZ |
1501 | struct intel_vgpu *vgpu = s->vgpu; |
1502 | ||
1503 | gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name); | |
1504 | ||
5c56883a | 1505 | return -EBADRQC; |
be1da707 ZW |
1506 | } |
1507 | ||
1508 | static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s) | |
1509 | { | |
1510 | return unexpected_cmd(s); | |
1511 | } | |
1512 | ||
1513 | static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s) | |
1514 | { | |
1515 | return unexpected_cmd(s); | |
1516 | } | |
1517 | ||
1518 | static int cmd_handler_mi_op_2e(struct parser_exec_state *s) | |
1519 | { | |
1520 | return unexpected_cmd(s); | |
1521 | } | |
1522 | ||
1523 | static int cmd_handler_mi_op_2f(struct parser_exec_state *s) | |
1524 | { | |
1525 | int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; | |
173bcc60 ZW |
1526 | int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) * |
1527 | sizeof(u32); | |
be1da707 ZW |
1528 | unsigned long gma, gma_high; |
1529 | int ret = 0; | |
1530 | ||
1531 | if (!(cmd_val(s, 0) & (1 << 22))) | |
1532 | return ret; | |
1533 | ||
1534 | gma = cmd_val(s, 1) & GENMASK(31, 2); | |
1535 | if (gmadr_bytes == 8) { | |
1536 | gma_high = cmd_val(s, 2) & GENMASK(15, 0); | |
1537 | gma = (gma_high << 32) | gma; | |
1538 | } | |
1539 | ret = cmd_address_audit(s, gma, op_size, false); | |
1540 | return ret; | |
1541 | } | |
1542 | ||
1543 | static int cmd_handler_mi_store_data_index(struct parser_exec_state *s) | |
1544 | { | |
1545 | return unexpected_cmd(s); | |
1546 | } | |
1547 | ||
1548 | static int cmd_handler_mi_clflush(struct parser_exec_state *s) | |
1549 | { | |
1550 | return unexpected_cmd(s); | |
1551 | } | |
1552 | ||
1553 | static int cmd_handler_mi_conditional_batch_buffer_end( | |
1554 | struct parser_exec_state *s) | |
1555 | { | |
1556 | return unexpected_cmd(s); | |
1557 | } | |
1558 | ||
1559 | static int cmd_handler_mi_update_gtt(struct parser_exec_state *s) | |
1560 | { | |
1561 | return unexpected_cmd(s); | |
1562 | } | |
1563 | ||
1564 | static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) | |
1565 | { | |
1566 | int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd; | |
1567 | unsigned long gma; | |
1568 | bool index_mode = false; | |
1569 | int ret = 0; | |
1570 | ||
1571 | /* Check post-sync and ppgtt bit */ | |
1572 | if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) { | |
1573 | gma = cmd_val(s, 1) & GENMASK(31, 3); | |
1574 | if (gmadr_bytes == 8) | |
1575 | gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32; | |
1576 | /* Store Data Index */ | |
1577 | if (cmd_val(s, 0) & (1 << 21)) | |
1578 | index_mode = true; | |
1579 | ret = cmd_address_audit(s, gma, sizeof(u64), index_mode); | |
1580 | } | |
1581 | /* Check notify bit */ | |
1582 | if ((cmd_val(s, 0) & (1 << 8))) | |
1583 | set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw, | |
1584 | s->workload->pending_events); | |
1585 | return ret; | |
1586 | } | |
1587 | ||
1588 | static void addr_type_update_snb(struct parser_exec_state *s) | |
1589 | { | |
1590 | if ((s->buf_type == RING_BUFFER_INSTRUCTION) && | |
1591 | (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) { | |
1592 | s->buf_addr_type = PPGTT_BUFFER; | |
1593 | } | |
1594 | } | |
1595 | ||
1596 | ||
1597 | static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm, | |
1598 | unsigned long gma, unsigned long end_gma, void *va) | |
1599 | { | |
1600 | unsigned long copy_len, offset; | |
1601 | unsigned long len = 0; | |
1602 | unsigned long gpa; | |
1603 | ||
1604 | while (gma != end_gma) { | |
1605 | gpa = intel_vgpu_gma_to_gpa(mm, gma); | |
1606 | if (gpa == INTEL_GVT_INVALID_ADDR) { | |
695fbc08 | 1607 | gvt_vgpu_err("invalid gma address: %lx\n", gma); |
be1da707 ZW |
1608 | return -EFAULT; |
1609 | } | |
1610 | ||
9556e118 | 1611 | offset = gma & (I915_GTT_PAGE_SIZE - 1); |
be1da707 | 1612 | |
9556e118 ZW |
1613 | copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ? |
1614 | I915_GTT_PAGE_SIZE - offset : end_gma - gma; | |
be1da707 ZW |
1615 | |
1616 | intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len); | |
1617 | ||
1618 | len += copy_len; | |
1619 | gma += copy_len; | |
1620 | } | |
73dec95e | 1621 | return len; |
be1da707 ZW |
1622 | } |
1623 | ||
1624 | ||
1625 | /* | |
1626 | * Check whether a batch buffer needs to be scanned. Currently | |
1627 | * the only criteria is based on privilege. | |
1628 | */ | |
1629 | static int batch_buffer_needs_scan(struct parser_exec_state *s) | |
1630 | { | |
f093f182 CX |
1631 | /* Decide privilege based on address space */ |
1632 | if (cmd_val(s, 0) & (1 << 8) && | |
96bebe39 | 1633 | !(s->vgpu->scan_nonprivbb & (1 << s->ring_id))) |
f093f182 | 1634 | return 0; |
be1da707 ZW |
1635 | return 1; |
1636 | } | |
1637 | ||
58facf8c | 1638 | static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size) |
be1da707 ZW |
1639 | { |
1640 | unsigned long gma = 0; | |
b007065a | 1641 | const struct cmd_info *info; |
2e679d48 | 1642 | u32 cmd_len = 0; |
58facf8c | 1643 | bool bb_end = false; |
695fbc08 | 1644 | struct intel_vgpu *vgpu = s->vgpu; |
be1da707 | 1645 | u32 cmd; |
96bebe39 ZY |
1646 | struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ? |
1647 | s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm; | |
be1da707 | 1648 | |
58facf8c ZW |
1649 | *bb_size = 0; |
1650 | ||
be1da707 ZW |
1651 | /* get the start gm address of the batch buffer */ |
1652 | gma = get_gma_bb_from_cmd(s, 1); | |
5c56883a | 1653 | if (gma == INTEL_GVT_INVALID_ADDR) |
1654 | return -EFAULT; | |
1655 | ||
be1da707 | 1656 | cmd = cmd_val(s, 0); |
be1da707 ZW |
1657 | info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); |
1658 | if (info == NULL) { | |
96bebe39 ZY |
1659 | gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n", |
1660 | cmd, get_opcode(cmd, s->ring_id), | |
1661 | (s->buf_addr_type == PPGTT_BUFFER) ? | |
1662 | "ppgtt" : "ggtt", s->ring_id, s->workload); | |
5c56883a | 1663 | return -EBADRQC; |
be1da707 ZW |
1664 | } |
1665 | do { | |
96bebe39 | 1666 | if (copy_gma_to_hva(s->vgpu, mm, |
5c56883a | 1667 | gma, gma + 4, &cmd) < 0) |
1668 | return -EFAULT; | |
be1da707 ZW |
1669 | info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); |
1670 | if (info == NULL) { | |
96bebe39 ZY |
1671 | gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n", |
1672 | cmd, get_opcode(cmd, s->ring_id), | |
1673 | (s->buf_addr_type == PPGTT_BUFFER) ? | |
1674 | "ppgtt" : "ggtt", s->ring_id, s->workload); | |
5c56883a | 1675 | return -EBADRQC; |
be1da707 ZW |
1676 | } |
1677 | ||
1678 | if (info->opcode == OP_MI_BATCH_BUFFER_END) { | |
58facf8c | 1679 | bb_end = true; |
be1da707 | 1680 | } else if (info->opcode == OP_MI_BATCH_BUFFER_START) { |
58facf8c | 1681 | if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) |
be1da707 | 1682 | /* chained batch buffer */ |
58facf8c | 1683 | bb_end = true; |
be1da707 ZW |
1684 | } |
1685 | cmd_len = get_cmd_length(info, cmd) << 2; | |
58facf8c | 1686 | *bb_size += cmd_len; |
be1da707 | 1687 | gma += cmd_len; |
58facf8c | 1688 | } while (!bb_end); |
be1da707 | 1689 | |
58facf8c | 1690 | return 0; |
be1da707 ZW |
1691 | } |
1692 | ||
be1da707 ZW |
1693 | static int perform_bb_shadow(struct parser_exec_state *s) |
1694 | { | |
695fbc08 | 1695 | struct intel_vgpu *vgpu = s->vgpu; |
f52c380a | 1696 | struct intel_vgpu_shadow_bb *bb; |
be1da707 | 1697 | unsigned long gma = 0; |
58facf8c | 1698 | unsigned long bb_size; |
be1da707 | 1699 | int ret = 0; |
96bebe39 ZY |
1700 | struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ? |
1701 | s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm; | |
1702 | unsigned long gma_start_offset = 0; | |
be1da707 ZW |
1703 | |
1704 | /* get the start gm address of the batch buffer */ | |
1705 | gma = get_gma_bb_from_cmd(s, 1); | |
5c56883a | 1706 | if (gma == INTEL_GVT_INVALID_ADDR) |
1707 | return -EFAULT; | |
be1da707 | 1708 | |
58facf8c ZW |
1709 | ret = find_bb_size(s, &bb_size); |
1710 | if (ret) | |
1711 | return ret; | |
be1da707 | 1712 | |
f52c380a ZW |
1713 | bb = kzalloc(sizeof(*bb), GFP_KERNEL); |
1714 | if (!bb) | |
be1da707 ZW |
1715 | return -ENOMEM; |
1716 | ||
96bebe39 ZY |
1717 | bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true; |
1718 | ||
1719 | /* the gma_start_offset stores the batch buffer's start gma's | |
1720 | * offset relative to page boundary. so for non-privileged batch | |
1721 | * buffer, the shadowed gem object holds exactly the same page | |
1722 | * layout as original gem object. This is for the convience of | |
1723 | * replacing the whole non-privilged batch buffer page to this | |
1724 | * shadowed one in PPGTT at the same gma address. (this replacing | |
1725 | * action is not implemented yet now, but may be necessary in | |
1726 | * future). | |
1727 | * for prileged batch buffer, we just change start gma address to | |
1728 | * that of shadowed page. | |
1729 | */ | |
1730 | if (bb->ppgtt) | |
1731 | gma_start_offset = gma & ~I915_GTT_PAGE_MASK; | |
1732 | ||
f52c380a | 1733 | bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv, |
96bebe39 | 1734 | roundup(bb_size + gma_start_offset, PAGE_SIZE)); |
f52c380a ZW |
1735 | if (IS_ERR(bb->obj)) { |
1736 | ret = PTR_ERR(bb->obj); | |
1737 | goto err_free_bb; | |
894cf7d1 | 1738 | } |
be1da707 | 1739 | |
f52c380a ZW |
1740 | ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush); |
1741 | if (ret) | |
1742 | goto err_free_obj; | |
be1da707 | 1743 | |
f52c380a ZW |
1744 | bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); |
1745 | if (IS_ERR(bb->va)) { | |
1746 | ret = PTR_ERR(bb->va); | |
1747 | goto err_finish_shmem_access; | |
be1da707 ZW |
1748 | } |
1749 | ||
f52c380a ZW |
1750 | if (bb->clflush & CLFLUSH_BEFORE) { |
1751 | drm_clflush_virt_range(bb->va, bb->obj->base.size); | |
1752 | bb->clflush &= ~CLFLUSH_BEFORE; | |
1753 | } | |
be1da707 | 1754 | |
96bebe39 | 1755 | ret = copy_gma_to_hva(s->vgpu, mm, |
a2861504 | 1756 | gma, gma + bb_size, |
96bebe39 | 1757 | bb->va + gma_start_offset); |
8bcad07a | 1758 | if (ret < 0) { |
695fbc08 | 1759 | gvt_vgpu_err("fail to copy guest ring buffer\n"); |
f52c380a ZW |
1760 | ret = -EFAULT; |
1761 | goto err_unmap; | |
be1da707 ZW |
1762 | } |
1763 | ||
f52c380a ZW |
1764 | INIT_LIST_HEAD(&bb->list); |
1765 | list_add(&bb->list, &s->workload->shadow_bb); | |
1766 | ||
1767 | bb->accessing = true; | |
1768 | bb->bb_start_cmd_va = s->ip_va; | |
1769 | ||
ef75c685 | 1770 | if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa)) |
1771 | bb->bb_offset = s->ip_va - s->rb_va; | |
1772 | else | |
1773 | bb->bb_offset = 0; | |
1774 | ||
be1da707 ZW |
1775 | /* |
1776 | * ip_va saves the virtual address of the shadow batch buffer, while | |
1777 | * ip_gma saves the graphics address of the original batch buffer. | |
1778 | * As the shadow batch buffer is just a copy from the originial one, | |
1779 | * it should be right to use shadow batch buffer'va and original batch | |
1780 | * buffer's gma in pair. After all, we don't want to pin the shadow | |
1781 | * buffer here (too early). | |
1782 | */ | |
96bebe39 | 1783 | s->ip_va = bb->va + gma_start_offset; |
be1da707 | 1784 | s->ip_gma = gma; |
be1da707 | 1785 | return 0; |
f52c380a ZW |
1786 | err_unmap: |
1787 | i915_gem_object_unpin_map(bb->obj); | |
1788 | err_finish_shmem_access: | |
1789 | i915_gem_obj_finish_shmem_access(bb->obj); | |
1790 | err_free_obj: | |
1791 | i915_gem_object_put(bb->obj); | |
1792 | err_free_bb: | |
1793 | kfree(bb); | |
be1da707 ZW |
1794 | return ret; |
1795 | } | |
1796 | ||
1797 | static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s) | |
1798 | { | |
1799 | bool second_level; | |
1800 | int ret = 0; | |
695fbc08 | 1801 | struct intel_vgpu *vgpu = s->vgpu; |
be1da707 ZW |
1802 | |
1803 | if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) { | |
695fbc08 | 1804 | gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n"); |
5c56883a | 1805 | return -EFAULT; |
be1da707 ZW |
1806 | } |
1807 | ||
1808 | second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1; | |
1809 | if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) { | |
695fbc08 | 1810 | gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n"); |
5c56883a | 1811 | return -EFAULT; |
be1da707 ZW |
1812 | } |
1813 | ||
1814 | s->saved_buf_addr_type = s->buf_addr_type; | |
1815 | addr_type_update_snb(s); | |
1816 | if (s->buf_type == RING_BUFFER_INSTRUCTION) { | |
1817 | s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32); | |
1818 | s->buf_type = BATCH_BUFFER_INSTRUCTION; | |
1819 | } else if (second_level) { | |
1820 | s->buf_type = BATCH_BUFFER_2ND_LEVEL; | |
1821 | s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32); | |
1822 | s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32); | |
1823 | } | |
1824 | ||
1825 | if (batch_buffer_needs_scan(s)) { | |
1826 | ret = perform_bb_shadow(s); | |
1827 | if (ret < 0) | |
695fbc08 | 1828 | gvt_vgpu_err("invalid shadow batch buffer\n"); |
be1da707 ZW |
1829 | } else { |
1830 | /* emulate a batch buffer end to do return right */ | |
1831 | ret = cmd_handler_mi_batch_buffer_end(s); | |
1832 | if (ret < 0) | |
1833 | return ret; | |
1834 | } | |
be1da707 ZW |
1835 | return ret; |
1836 | } | |
1837 | ||
db47685d ZY |
1838 | static int mi_noop_index; |
1839 | ||
b007065a | 1840 | static const struct cmd_info cmd_info[] = { |
be1da707 ZW |
1841 | {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, |
1842 | ||
1843 | {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL, | |
1844 | 0, 1, NULL}, | |
1845 | ||
1846 | {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL, | |
1847 | 0, 1, cmd_handler_mi_user_interrupt}, | |
1848 | ||
1849 | {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS, | |
1850 | D_ALL, 0, 1, cmd_handler_mi_wait_for_event}, | |
1851 | ||
1852 | {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, | |
1853 | ||
1854 | {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1, | |
1855 | NULL}, | |
1856 | ||
1857 | {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1, | |
1858 | NULL}, | |
1859 | ||
1860 | {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1, | |
1861 | NULL}, | |
1862 | ||
1863 | {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1, | |
1864 | NULL}, | |
1865 | ||
1866 | {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS, | |
1867 | D_ALL, 0, 1, NULL}, | |
1868 | ||
1869 | {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END, | |
1870 | F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1, | |
1871 | cmd_handler_mi_batch_buffer_end}, | |
1872 | ||
1873 | {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL, | |
1874 | 0, 1, NULL}, | |
1875 | ||
1876 | {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1, | |
1877 | NULL}, | |
1878 | ||
1879 | {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL, | |
1880 | D_ALL, 0, 1, NULL}, | |
1881 | ||
1882 | {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1, | |
1883 | NULL}, | |
1884 | ||
1885 | {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1, | |
1886 | NULL}, | |
1887 | ||
1888 | {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE, | |
1889 | R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip}, | |
1890 | ||
1891 | {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL, | |
1892 | 0, 8, NULL}, | |
1893 | ||
1894 | {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL}, | |
1895 | ||
1896 | {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
1897 | ||
d58b3363 | 1898 | {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL, |
be1da707 ZW |
1899 | D_BDW_PLUS, 0, 8, NULL}, |
1900 | ||
d58b3363 XL |
1901 | {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, |
1902 | D_BDW_PLUS, ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait}, | |
be1da707 ZW |
1903 | |
1904 | {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS, | |
1905 | ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm}, | |
1906 | ||
1907 | {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL, | |
1908 | 0, 8, cmd_handler_mi_store_data_index}, | |
1909 | ||
1910 | {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL, | |
1911 | D_ALL, 0, 8, cmd_handler_lri}, | |
1912 | ||
1913 | {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10, | |
1914 | cmd_handler_mi_update_gtt}, | |
1915 | ||
1916 | {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL, | |
1917 | D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm}, | |
1918 | ||
1919 | {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6, | |
1920 | cmd_handler_mi_flush_dw}, | |
1921 | ||
1922 | {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1), | |
1923 | 10, cmd_handler_mi_clflush}, | |
1924 | ||
1925 | {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL, | |
1926 | D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count}, | |
1927 | ||
1928 | {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL, | |
1929 | D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm}, | |
1930 | ||
1931 | {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL, | |
1932 | D_ALL, 0, 8, cmd_handler_lrr}, | |
1933 | ||
1934 | {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS, | |
1935 | D_ALL, 0, 8, NULL}, | |
1936 | ||
1937 | {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL, | |
1938 | ADDR_FIX_1(2), 8, NULL}, | |
1939 | ||
1940 | {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL, | |
1941 | ADDR_FIX_1(2), 8, NULL}, | |
1942 | ||
1943 | {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2), | |
1944 | 8, cmd_handler_mi_op_2e}, | |
1945 | ||
1946 | {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1), | |
1947 | 8, cmd_handler_mi_op_2f}, | |
1948 | ||
1949 | {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START, | |
1950 | F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8, | |
1951 | cmd_handler_mi_batch_buffer_start}, | |
1952 | ||
1953 | {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END, | |
1954 | F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8, | |
1955 | cmd_handler_mi_conditional_batch_buffer_end}, | |
1956 | ||
1957 | {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST, | |
1958 | R_RCS | R_BCS, D_ALL, 0, 2, NULL}, | |
1959 | ||
1960 | {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1961 | ADDR_FIX_2(4, 7), 8, NULL}, | |
1962 | ||
1963 | {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1964 | 0, 8, NULL}, | |
1965 | ||
1966 | {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT, | |
1967 | F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, | |
1968 | ||
1969 | {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, | |
1970 | ||
1971 | {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1972 | 0, 8, NULL}, | |
1973 | ||
1974 | {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1975 | ADDR_FIX_1(3), 8, NULL}, | |
1976 | ||
1977 | {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS, | |
1978 | D_ALL, 0, 8, NULL}, | |
1979 | ||
1980 | {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1981 | ADDR_FIX_1(4), 8, NULL}, | |
1982 | ||
1983 | {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1984 | ADDR_FIX_2(4, 5), 8, NULL}, | |
1985 | ||
1986 | {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1987 | ADDR_FIX_1(4), 8, NULL}, | |
1988 | ||
1989 | {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
1990 | ADDR_FIX_2(4, 7), 8, NULL}, | |
1991 | ||
1992 | {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS, | |
1993 | D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, | |
1994 | ||
1995 | {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL}, | |
1996 | ||
1997 | {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS, | |
1998 | D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL}, | |
1999 | ||
2000 | {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR, | |
2001 | R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, | |
2002 | ||
2003 | {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT", | |
2004 | OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT, | |
2005 | F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, | |
2006 | ||
2007 | {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS, | |
2008 | D_ALL, ADDR_FIX_1(4), 8, NULL}, | |
2009 | ||
2010 | {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT, | |
2011 | F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, | |
2012 | ||
2013 | {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS, | |
2014 | D_ALL, ADDR_FIX_1(4), 8, NULL}, | |
2015 | ||
2016 | {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS, | |
2017 | D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, | |
2018 | ||
2019 | {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT, | |
2020 | F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL}, | |
2021 | ||
2022 | {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT", | |
2023 | OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT, | |
2024 | F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL}, | |
2025 | ||
2026 | {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL, | |
2027 | ADDR_FIX_2(4, 5), 8, NULL}, | |
2028 | ||
2029 | {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE, | |
2030 | F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL}, | |
2031 | ||
2032 | {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", | |
2033 | OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, | |
2034 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2035 | ||
2036 | {"3DSTATE_VIEWPORT_STATE_POINTERS_CC", | |
2037 | OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC, | |
2038 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2039 | ||
2040 | {"3DSTATE_BLEND_STATE_POINTERS", | |
2041 | OP_3DSTATE_BLEND_STATE_POINTERS, | |
2042 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2043 | ||
2044 | {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS", | |
2045 | OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, | |
2046 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2047 | ||
2048 | {"3DSTATE_BINDING_TABLE_POINTERS_VS", | |
2049 | OP_3DSTATE_BINDING_TABLE_POINTERS_VS, | |
2050 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2051 | ||
2052 | {"3DSTATE_BINDING_TABLE_POINTERS_HS", | |
2053 | OP_3DSTATE_BINDING_TABLE_POINTERS_HS, | |
2054 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2055 | ||
2056 | {"3DSTATE_BINDING_TABLE_POINTERS_DS", | |
2057 | OP_3DSTATE_BINDING_TABLE_POINTERS_DS, | |
2058 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2059 | ||
2060 | {"3DSTATE_BINDING_TABLE_POINTERS_GS", | |
2061 | OP_3DSTATE_BINDING_TABLE_POINTERS_GS, | |
2062 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2063 | ||
2064 | {"3DSTATE_BINDING_TABLE_POINTERS_PS", | |
2065 | OP_3DSTATE_BINDING_TABLE_POINTERS_PS, | |
2066 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2067 | ||
2068 | {"3DSTATE_SAMPLER_STATE_POINTERS_VS", | |
2069 | OP_3DSTATE_SAMPLER_STATE_POINTERS_VS, | |
2070 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2071 | ||
2072 | {"3DSTATE_SAMPLER_STATE_POINTERS_HS", | |
2073 | OP_3DSTATE_SAMPLER_STATE_POINTERS_HS, | |
2074 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2075 | ||
2076 | {"3DSTATE_SAMPLER_STATE_POINTERS_DS", | |
2077 | OP_3DSTATE_SAMPLER_STATE_POINTERS_DS, | |
2078 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2079 | ||
2080 | {"3DSTATE_SAMPLER_STATE_POINTERS_GS", | |
2081 | OP_3DSTATE_SAMPLER_STATE_POINTERS_GS, | |
2082 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2083 | ||
2084 | {"3DSTATE_SAMPLER_STATE_POINTERS_PS", | |
2085 | OP_3DSTATE_SAMPLER_STATE_POINTERS_PS, | |
2086 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2087 | ||
2088 | {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL, | |
2089 | 0, 8, NULL}, | |
2090 | ||
2091 | {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL, | |
2092 | 0, 8, NULL}, | |
2093 | ||
2094 | {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL, | |
2095 | 0, 8, NULL}, | |
2096 | ||
2097 | {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL, | |
2098 | 0, 8, NULL}, | |
2099 | ||
2100 | {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS, | |
2101 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2102 | ||
2103 | {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS, | |
2104 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2105 | ||
2106 | {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS, | |
2107 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2108 | ||
2109 | {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS, | |
2110 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2111 | ||
2112 | {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS, | |
2113 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2114 | ||
2115 | {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS, | |
2116 | F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, | |
2117 | ||
2118 | {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS, | |
2119 | F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL}, | |
2120 | ||
2121 | {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS, | |
2122 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2123 | ||
2124 | {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS, | |
2125 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2126 | ||
2127 | {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS, | |
2128 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2129 | ||
2130 | {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS, | |
2131 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2132 | ||
2133 | {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS, | |
2134 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2135 | ||
2136 | {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS, | |
2137 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2138 | ||
2139 | {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS, | |
2140 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2141 | ||
2142 | {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS, | |
2143 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2144 | ||
2145 | {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS, | |
2146 | F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, | |
2147 | ||
2148 | {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS, | |
2149 | F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, | |
2150 | ||
2151 | {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS, | |
2152 | F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, | |
2153 | ||
2154 | {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS, | |
2155 | F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, | |
2156 | ||
2157 | {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS, | |
2158 | F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL}, | |
2159 | ||
2160 | {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS, | |
2161 | D_BDW_PLUS, 0, 8, NULL}, | |
2162 | ||
2163 | {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, | |
2164 | NULL}, | |
2165 | ||
2166 | {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS, | |
2167 | D_BDW_PLUS, 0, 8, NULL}, | |
2168 | ||
2169 | {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS, | |
2170 | D_BDW_PLUS, 0, 8, NULL}, | |
2171 | ||
2172 | {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, | |
2173 | 8, NULL}, | |
2174 | ||
2175 | {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR, | |
2176 | R_RCS, D_BDW_PLUS, 0, 8, NULL}, | |
2177 | ||
2178 | {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, | |
2179 | 8, NULL}, | |
2180 | ||
2181 | {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, | |
2182 | NULL}, | |
2183 | ||
2184 | {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, | |
2185 | NULL}, | |
2186 | ||
2187 | {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8, | |
2188 | NULL}, | |
2189 | ||
2190 | {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS, | |
2191 | D_BDW_PLUS, 0, 8, NULL}, | |
2192 | ||
2193 | {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR, | |
2194 | R_RCS, D_ALL, 0, 8, NULL}, | |
2195 | ||
2196 | {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS, | |
2197 | D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL}, | |
2198 | ||
2199 | {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST, | |
2200 | R_RCS, D_ALL, 0, 1, NULL}, | |
2201 | ||
2202 | {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2203 | ||
2204 | {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR, | |
2205 | R_RCS, D_ALL, 0, 8, NULL}, | |
2206 | ||
2207 | {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS, | |
2208 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2209 | ||
2210 | {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2211 | ||
2212 | {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2213 | ||
2214 | {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2215 | ||
2216 | {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS, | |
2217 | D_BDW_PLUS, 0, 8, NULL}, | |
2218 | ||
2219 | {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS, | |
2220 | D_BDW_PLUS, 0, 8, NULL}, | |
2221 | ||
2222 | {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS, | |
2223 | D_ALL, 0, 8, NULL}, | |
2224 | ||
2225 | {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS, | |
2226 | D_BDW_PLUS, 0, 8, NULL}, | |
2227 | ||
2228 | {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS, | |
2229 | D_BDW_PLUS, 0, 8, NULL}, | |
2230 | ||
2231 | {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2232 | ||
2233 | {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2234 | ||
2235 | {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2236 | ||
2237 | {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS, | |
2238 | D_ALL, 0, 8, NULL}, | |
2239 | ||
2240 | {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2241 | ||
2242 | {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2243 | ||
2244 | {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR, | |
2245 | R_RCS, D_ALL, 0, 8, NULL}, | |
2246 | ||
2247 | {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0, | |
2248 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2249 | ||
2250 | {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL, | |
2251 | 0, 8, NULL}, | |
2252 | ||
2253 | {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS, | |
2254 | D_ALL, ADDR_FIX_1(2), 8, NULL}, | |
2255 | ||
2256 | {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET, | |
2257 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2258 | ||
2259 | {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN, | |
2260 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2261 | ||
2262 | {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS, | |
2263 | D_ALL, 0, 8, NULL}, | |
2264 | ||
2265 | {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS, | |
2266 | D_ALL, 0, 8, NULL}, | |
2267 | ||
2268 | {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS, | |
2269 | D_ALL, 0, 8, NULL}, | |
2270 | ||
2271 | {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1, | |
2272 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2273 | ||
2274 | {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS, | |
2275 | D_BDW_PLUS, 0, 8, NULL}, | |
2276 | ||
2277 | {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS, | |
2278 | D_ALL, ADDR_FIX_1(2), 8, NULL}, | |
2279 | ||
2280 | {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR, | |
2281 | R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL}, | |
2282 | ||
2283 | {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR, | |
2284 | R_RCS, D_ALL, 0, 8, NULL}, | |
2285 | ||
2286 | {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS, | |
2287 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2288 | ||
2289 | {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS, | |
2290 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2291 | ||
2292 | {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS, | |
2293 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2294 | ||
2295 | {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS, | |
2296 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2297 | ||
2298 | {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS, | |
2299 | F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2300 | ||
2301 | {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR, | |
2302 | R_RCS, D_ALL, 0, 8, NULL}, | |
2303 | ||
2304 | {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS, | |
2305 | D_ALL, 0, 9, NULL}, | |
2306 | ||
2307 | {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS, | |
2308 | ADDR_FIX_2(2, 4), 8, NULL}, | |
2309 | ||
2310 | {"3DSTATE_BINDING_TABLE_POOL_ALLOC", | |
2311 | OP_3DSTATE_BINDING_TABLE_POOL_ALLOC, | |
2312 | F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, | |
2313 | ||
2314 | {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC, | |
2315 | F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, | |
2316 | ||
2317 | {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC", | |
2318 | OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, | |
2319 | F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL}, | |
2320 | ||
2321 | {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS, | |
2322 | D_BDW_PLUS, 0, 8, NULL}, | |
2323 | ||
2324 | {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL, | |
2325 | ADDR_FIX_1(2), 8, cmd_handler_pipe_control}, | |
2326 | ||
2327 | {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2328 | ||
2329 | {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0, | |
2330 | 1, NULL}, | |
2331 | ||
2332 | {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL, | |
2333 | ADDR_FIX_1(1), 8, NULL}, | |
2334 | ||
2335 | {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2336 | ||
2337 | {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS, | |
2338 | ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL}, | |
2339 | ||
2340 | {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL, | |
2341 | ADDR_FIX_1(1), 8, NULL}, | |
2342 | ||
2343 | {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2344 | ||
2345 | {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL}, | |
2346 | ||
2347 | {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS, | |
2348 | 0, 8, NULL}, | |
2349 | ||
2350 | {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS, | |
2351 | D_SKL_PLUS, 0, 8, NULL}, | |
2352 | ||
2353 | {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD, | |
2354 | F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, | |
2355 | ||
2356 | {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL, | |
2357 | 0, 16, NULL}, | |
2358 | ||
2359 | {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL, | |
2360 | 0, 16, NULL}, | |
2361 | ||
02b966c1 CX |
2362 | {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL, |
2363 | 0, 16, NULL}, | |
2364 | ||
be1da707 ZW |
2365 | {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL}, |
2366 | ||
2367 | {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL, | |
2368 | 0, 16, NULL}, | |
2369 | ||
2370 | {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL, | |
2371 | 0, 16, NULL}, | |
2372 | ||
2373 | {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL, | |
2374 | 0, 16, NULL}, | |
2375 | ||
2376 | {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL, | |
2377 | 0, 8, NULL}, | |
2378 | ||
2379 | {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16, | |
2380 | NULL}, | |
2381 | ||
2382 | {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45, | |
2383 | F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL}, | |
2384 | ||
2385 | {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR, | |
2386 | R_VCS, D_ALL, 0, 12, NULL}, | |
2387 | ||
2388 | {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR, | |
2389 | R_VCS, D_ALL, 0, 12, NULL}, | |
2390 | ||
2391 | {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR, | |
2392 | R_VCS, D_BDW_PLUS, 0, 12, NULL}, | |
2393 | ||
2394 | {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE, | |
2395 | F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, | |
2396 | ||
2397 | {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE, | |
2398 | F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL}, | |
2399 | ||
2400 | {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL}, | |
2401 | ||
2402 | {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR, | |
2403 | R_VCS, D_ALL, 0, 12, NULL}, | |
2404 | ||
2405 | {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR, | |
2406 | R_VCS, D_ALL, 0, 12, NULL}, | |
2407 | ||
2408 | {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR, | |
2409 | R_VCS, D_ALL, 0, 12, NULL}, | |
2410 | ||
2411 | {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR, | |
2412 | R_VCS, D_ALL, 0, 12, NULL}, | |
2413 | ||
2414 | {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR, | |
2415 | R_VCS, D_ALL, 0, 12, NULL}, | |
2416 | ||
2417 | {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR, | |
2418 | R_VCS, D_ALL, 0, 12, NULL}, | |
2419 | ||
2420 | {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR, | |
2421 | R_VCS, D_ALL, 0, 6, NULL}, | |
2422 | ||
2423 | {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR, | |
2424 | R_VCS, D_ALL, 0, 12, NULL}, | |
2425 | ||
2426 | {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR, | |
2427 | R_VCS, D_ALL, 0, 12, NULL}, | |
2428 | ||
2429 | {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR, | |
2430 | R_VCS, D_ALL, 0, 12, NULL}, | |
2431 | ||
2432 | {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR, | |
2433 | R_VCS, D_ALL, 0, 12, NULL}, | |
2434 | ||
2435 | {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR, | |
2436 | R_VCS, D_ALL, 0, 12, NULL}, | |
2437 | ||
2438 | {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR, | |
2439 | R_VCS, D_ALL, 0, 12, NULL}, | |
2440 | ||
2441 | {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR, | |
2442 | R_VCS, D_ALL, 0, 12, NULL}, | |
2443 | {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR, | |
2444 | R_VCS, D_ALL, 0, 12, NULL}, | |
2445 | ||
2446 | {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR, | |
2447 | R_VCS, D_ALL, 0, 12, NULL}, | |
2448 | ||
2449 | {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR, | |
2450 | R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL}, | |
2451 | ||
2452 | {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR, | |
2453 | R_VCS, D_ALL, 0, 12, NULL}, | |
2454 | ||
2455 | {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR, | |
2456 | R_VCS, D_ALL, 0, 12, NULL}, | |
2457 | ||
2458 | {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR, | |
2459 | R_VCS, D_ALL, 0, 12, NULL}, | |
2460 | ||
2461 | {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR, | |
2462 | R_VCS, D_ALL, 0, 12, NULL}, | |
2463 | ||
2464 | {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR, | |
2465 | R_VCS, D_ALL, 0, 12, NULL}, | |
2466 | ||
2467 | {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR, | |
2468 | R_VCS, D_ALL, 0, 12, NULL}, | |
2469 | ||
2470 | {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR, | |
2471 | R_VCS, D_ALL, 0, 12, NULL}, | |
2472 | ||
2473 | {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR, | |
2474 | R_VCS, D_ALL, 0, 12, NULL}, | |
2475 | ||
2476 | {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR, | |
2477 | R_VCS, D_ALL, 0, 12, NULL}, | |
2478 | ||
2479 | {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR, | |
2480 | R_VCS, D_ALL, 0, 12, NULL}, | |
2481 | ||
2482 | {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR, | |
2483 | R_VCS, D_ALL, 0, 12, NULL}, | |
2484 | ||
2485 | {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL, | |
2486 | 0, 16, NULL}, | |
2487 | ||
2488 | {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, | |
2489 | ||
2490 | {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL}, | |
2491 | ||
2492 | {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR, | |
2493 | R_VCS, D_ALL, 0, 12, NULL}, | |
2494 | ||
2495 | {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR, | |
2496 | R_VCS, D_ALL, 0, 12, NULL}, | |
2497 | ||
2498 | {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR, | |
2499 | R_VCS, D_ALL, 0, 12, NULL}, | |
2500 | ||
2501 | {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL}, | |
2502 | ||
2503 | {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL, | |
2504 | 0, 12, NULL}, | |
2505 | ||
2506 | {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS, | |
2507 | 0, 20, NULL}, | |
2508 | }; | |
2509 | ||
2510 | static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e) | |
2511 | { | |
2512 | hash_add(gvt->cmd_table, &e->hlist, e->info->opcode); | |
2513 | } | |
2514 | ||
be1da707 ZW |
2515 | /* call the cmd handler, and advance ip */ |
2516 | static int cmd_parser_exec(struct parser_exec_state *s) | |
2517 | { | |
ffc19776 | 2518 | struct intel_vgpu *vgpu = s->vgpu; |
b007065a | 2519 | const struct cmd_info *info; |
be1da707 ZW |
2520 | u32 cmd; |
2521 | int ret = 0; | |
be1da707 ZW |
2522 | |
2523 | cmd = cmd_val(s, 0); | |
2524 | ||
db47685d ZY |
2525 | /* fastpath for MI_NOOP */ |
2526 | if (cmd == MI_NOOP) | |
2527 | info = &cmd_info[mi_noop_index]; | |
2528 | else | |
2529 | info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id); | |
2530 | ||
be1da707 | 2531 | if (info == NULL) { |
96bebe39 ZY |
2532 | gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n", |
2533 | cmd, get_opcode(cmd, s->ring_id), | |
2534 | (s->buf_addr_type == PPGTT_BUFFER) ? | |
2535 | "ppgtt" : "ggtt", s->ring_id, s->workload); | |
5c56883a | 2536 | return -EBADRQC; |
be1da707 ZW |
2537 | } |
2538 | ||
be1da707 ZW |
2539 | s->info = info; |
2540 | ||
ffc19776 | 2541 | trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va, |
96bebe39 ZY |
2542 | cmd_length(s), s->buf_type, s->buf_addr_type, |
2543 | s->workload, info->name); | |
be1da707 ZW |
2544 | |
2545 | if (info->handler) { | |
2546 | ret = info->handler(s); | |
2547 | if (ret < 0) { | |
695fbc08 | 2548 | gvt_vgpu_err("%s handler error\n", info->name); |
be1da707 ZW |
2549 | return ret; |
2550 | } | |
2551 | } | |
be1da707 ZW |
2552 | |
2553 | if (!(info->flag & F_IP_ADVANCE_CUSTOM)) { | |
2554 | ret = cmd_advance_default(s); | |
2555 | if (ret) { | |
695fbc08 | 2556 | gvt_vgpu_err("%s IP advance error\n", info->name); |
be1da707 ZW |
2557 | return ret; |
2558 | } | |
2559 | } | |
2560 | return 0; | |
2561 | } | |
2562 | ||
2563 | static inline bool gma_out_of_range(unsigned long gma, | |
2564 | unsigned long gma_head, unsigned int gma_tail) | |
2565 | { | |
2566 | if (gma_tail >= gma_head) | |
2567 | return (gma < gma_head) || (gma > gma_tail); | |
2568 | else | |
2569 | return (gma > gma_tail) && (gma < gma_head); | |
2570 | } | |
2571 | ||
5c56883a | 2572 | /* Keep the consistent return type, e.g EBADRQC for unknown |
2573 | * cmd, EFAULT for invalid address, EPERM for nonpriv. later | |
2574 | * works as the input of VM healthy status. | |
2575 | */ | |
be1da707 ZW |
2576 | static int command_scan(struct parser_exec_state *s, |
2577 | unsigned long rb_head, unsigned long rb_tail, | |
2578 | unsigned long rb_start, unsigned long rb_len) | |
2579 | { | |
2580 | ||
2581 | unsigned long gma_head, gma_tail, gma_bottom; | |
2582 | int ret = 0; | |
695fbc08 | 2583 | struct intel_vgpu *vgpu = s->vgpu; |
be1da707 ZW |
2584 | |
2585 | gma_head = rb_start + rb_head; | |
2586 | gma_tail = rb_start + rb_tail; | |
2587 | gma_bottom = rb_start + rb_len; | |
2588 | ||
be1da707 ZW |
2589 | while (s->ip_gma != gma_tail) { |
2590 | if (s->buf_type == RING_BUFFER_INSTRUCTION) { | |
2591 | if (!(s->ip_gma >= rb_start) || | |
2592 | !(s->ip_gma < gma_bottom)) { | |
695fbc08 | 2593 | gvt_vgpu_err("ip_gma %lx out of ring scope." |
be1da707 ZW |
2594 | "(base:0x%lx, bottom: 0x%lx)\n", |
2595 | s->ip_gma, rb_start, | |
2596 | gma_bottom); | |
2597 | parser_exec_state_dump(s); | |
5c56883a | 2598 | return -EFAULT; |
be1da707 ZW |
2599 | } |
2600 | if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) { | |
695fbc08 | 2601 | gvt_vgpu_err("ip_gma %lx out of range." |
be1da707 ZW |
2602 | "base 0x%lx head 0x%lx tail 0x%lx\n", |
2603 | s->ip_gma, rb_start, | |
2604 | rb_head, rb_tail); | |
2605 | parser_exec_state_dump(s); | |
2606 | break; | |
2607 | } | |
2608 | } | |
2609 | ret = cmd_parser_exec(s); | |
2610 | if (ret) { | |
695fbc08 | 2611 | gvt_vgpu_err("cmd parser error\n"); |
be1da707 ZW |
2612 | parser_exec_state_dump(s); |
2613 | break; | |
2614 | } | |
2615 | } | |
2616 | ||
be1da707 ZW |
2617 | return ret; |
2618 | } | |
2619 | ||
2620 | static int scan_workload(struct intel_vgpu_workload *workload) | |
2621 | { | |
2622 | unsigned long gma_head, gma_tail, gma_bottom; | |
2623 | struct parser_exec_state s; | |
2624 | int ret = 0; | |
2625 | ||
2626 | /* ring base is page aligned */ | |
9556e118 | 2627 | if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE))) |
be1da707 ZW |
2628 | return -EINVAL; |
2629 | ||
2630 | gma_head = workload->rb_start + workload->rb_head; | |
2631 | gma_tail = workload->rb_start + workload->rb_tail; | |
2632 | gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl); | |
2633 | ||
2634 | s.buf_type = RING_BUFFER_INSTRUCTION; | |
2635 | s.buf_addr_type = GTT_BUFFER; | |
2636 | s.vgpu = workload->vgpu; | |
2637 | s.ring_id = workload->ring_id; | |
2638 | s.ring_start = workload->rb_start; | |
2639 | s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); | |
2640 | s.ring_head = gma_head; | |
2641 | s.ring_tail = gma_tail; | |
2642 | s.rb_va = workload->shadow_ring_buffer_va; | |
2643 | s.workload = workload; | |
ef75c685 | 2644 | s.is_ctx_wa = false; |
be1da707 | 2645 | |
0aaee4cc PZ |
2646 | if ((bypass_scan_mask & (1 << workload->ring_id)) || |
2647 | gma_head == gma_tail) | |
be1da707 ZW |
2648 | return 0; |
2649 | ||
3364bf5f PG |
2650 | if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) { |
2651 | ret = -EINVAL; | |
2652 | goto out; | |
2653 | } | |
2654 | ||
be1da707 ZW |
2655 | ret = ip_gma_set(&s, gma_head); |
2656 | if (ret) | |
2657 | goto out; | |
2658 | ||
2659 | ret = command_scan(&s, workload->rb_head, workload->rb_tail, | |
2660 | workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl)); | |
2661 | ||
2662 | out: | |
2663 | return ret; | |
2664 | } | |
2665 | ||
2666 | static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) | |
2667 | { | |
2668 | ||
2669 | unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail; | |
2670 | struct parser_exec_state s; | |
2671 | int ret = 0; | |
c10c1255 TZ |
2672 | struct intel_vgpu_workload *workload = container_of(wa_ctx, |
2673 | struct intel_vgpu_workload, | |
2674 | wa_ctx); | |
be1da707 ZW |
2675 | |
2676 | /* ring base is page aligned */ | |
9556e118 ZW |
2677 | if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, |
2678 | I915_GTT_PAGE_SIZE))) | |
be1da707 ZW |
2679 | return -EINVAL; |
2680 | ||
2e679d48 | 2681 | ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32); |
be1da707 ZW |
2682 | ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, |
2683 | PAGE_SIZE); | |
2684 | gma_head = wa_ctx->indirect_ctx.guest_gma; | |
2685 | gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail; | |
2686 | gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size; | |
2687 | ||
2688 | s.buf_type = RING_BUFFER_INSTRUCTION; | |
2689 | s.buf_addr_type = GTT_BUFFER; | |
c10c1255 TZ |
2690 | s.vgpu = workload->vgpu; |
2691 | s.ring_id = workload->ring_id; | |
be1da707 ZW |
2692 | s.ring_start = wa_ctx->indirect_ctx.guest_gma; |
2693 | s.ring_size = ring_size; | |
2694 | s.ring_head = gma_head; | |
2695 | s.ring_tail = gma_tail; | |
2696 | s.rb_va = wa_ctx->indirect_ctx.shadow_va; | |
c10c1255 | 2697 | s.workload = workload; |
ef75c685 | 2698 | s.is_ctx_wa = true; |
be1da707 | 2699 | |
3364bf5f PG |
2700 | if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) { |
2701 | ret = -EINVAL; | |
2702 | goto out; | |
2703 | } | |
2704 | ||
be1da707 ZW |
2705 | ret = ip_gma_set(&s, gma_head); |
2706 | if (ret) | |
2707 | goto out; | |
2708 | ||
2709 | ret = command_scan(&s, 0, ring_tail, | |
2710 | wa_ctx->indirect_ctx.guest_gma, ring_size); | |
2711 | out: | |
2712 | return ret; | |
2713 | } | |
2714 | ||
2715 | static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) | |
2716 | { | |
2717 | struct intel_vgpu *vgpu = workload->vgpu; | |
325eb94a | 2718 | struct intel_vgpu_submission *s = &vgpu->submission; |
be1da707 | 2719 | unsigned long gma_head, gma_tail, gma_top, guest_rb_size; |
0a53bc07 | 2720 | void *shadow_ring_buffer_va; |
2721 | int ring_id = workload->ring_id; | |
be1da707 ZW |
2722 | int ret; |
2723 | ||
2724 | guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl); | |
2725 | ||
2726 | /* calculate workload ring buffer size */ | |
2727 | workload->rb_len = (workload->rb_tail + guest_rb_size - | |
2728 | workload->rb_head) % guest_rb_size; | |
2729 | ||
2730 | gma_head = workload->rb_start + workload->rb_head; | |
2731 | gma_tail = workload->rb_start + workload->rb_tail; | |
2732 | gma_top = workload->rb_start + guest_rb_size; | |
2733 | ||
325eb94a | 2734 | if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) { |
8cf80a2e | 2735 | void *p; |
bf4097ea | 2736 | |
0a53bc07 | 2737 | /* realloc the new ring buffer if needed */ |
325eb94a | 2738 | p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len, |
8cf80a2e | 2739 | GFP_KERNEL); |
bf4097ea | 2740 | if (!p) { |
8cf80a2e | 2741 | gvt_vgpu_err("fail to re-alloc ring scan buffer\n"); |
0a53bc07 | 2742 | return -ENOMEM; |
2743 | } | |
325eb94a ZW |
2744 | s->ring_scan_buffer[ring_id] = p; |
2745 | s->ring_scan_buffer_size[ring_id] = workload->rb_len; | |
0a53bc07 | 2746 | } |
2747 | ||
325eb94a | 2748 | shadow_ring_buffer_va = s->ring_scan_buffer[ring_id]; |
be1da707 ZW |
2749 | |
2750 | /* get shadow ring buffer va */ | |
0a53bc07 | 2751 | workload->shadow_ring_buffer_va = shadow_ring_buffer_va; |
be1da707 ZW |
2752 | |
2753 | /* head > tail --> copy head <-> top */ | |
2754 | if (gma_head > gma_tail) { | |
2755 | ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, | |
0a53bc07 | 2756 | gma_head, gma_top, shadow_ring_buffer_va); |
8bcad07a | 2757 | if (ret < 0) { |
695fbc08 | 2758 | gvt_vgpu_err("fail to copy guest ring buffer\n"); |
be1da707 ZW |
2759 | return ret; |
2760 | } | |
0a53bc07 | 2761 | shadow_ring_buffer_va += ret; |
be1da707 ZW |
2762 | gma_head = workload->rb_start; |
2763 | } | |
2764 | ||
2765 | /* copy head or start <-> tail */ | |
0a53bc07 | 2766 | ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail, |
2767 | shadow_ring_buffer_va); | |
8bcad07a | 2768 | if (ret < 0) { |
695fbc08 | 2769 | gvt_vgpu_err("fail to copy guest ring buffer\n"); |
be1da707 ZW |
2770 | return ret; |
2771 | } | |
be1da707 ZW |
2772 | return 0; |
2773 | } | |
2774 | ||
89ea20b9 | 2775 | int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) |
be1da707 ZW |
2776 | { |
2777 | int ret; | |
695fbc08 | 2778 | struct intel_vgpu *vgpu = workload->vgpu; |
be1da707 ZW |
2779 | |
2780 | ret = shadow_workload_ring_buffer(workload); | |
2781 | if (ret) { | |
695fbc08 | 2782 | gvt_vgpu_err("fail to shadow workload ring_buffer\n"); |
be1da707 ZW |
2783 | return ret; |
2784 | } | |
2785 | ||
2786 | ret = scan_workload(workload); | |
2787 | if (ret) { | |
695fbc08 | 2788 | gvt_vgpu_err("scan workload error\n"); |
be1da707 ZW |
2789 | return ret; |
2790 | } | |
2791 | return 0; | |
2792 | } | |
2793 | ||
2794 | static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) | |
2795 | { | |
be1da707 ZW |
2796 | int ctx_size = wa_ctx->indirect_ctx.size; |
2797 | unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma; | |
c10c1255 TZ |
2798 | struct intel_vgpu_workload *workload = container_of(wa_ctx, |
2799 | struct intel_vgpu_workload, | |
2800 | wa_ctx); | |
2801 | struct intel_vgpu *vgpu = workload->vgpu; | |
894cf7d1 | 2802 | struct drm_i915_gem_object *obj; |
be1da707 | 2803 | int ret = 0; |
bcd0aede | 2804 | void *map; |
be1da707 | 2805 | |
c10c1255 | 2806 | obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv, |
894cf7d1 CW |
2807 | roundup(ctx_size + CACHELINE_BYTES, |
2808 | PAGE_SIZE)); | |
2809 | if (IS_ERR(obj)) | |
2810 | return PTR_ERR(obj); | |
be1da707 | 2811 | |
be1da707 | 2812 | /* get the va of the shadow batch buffer */ |
bcd0aede CW |
2813 | map = i915_gem_object_pin_map(obj, I915_MAP_WB); |
2814 | if (IS_ERR(map)) { | |
695fbc08 | 2815 | gvt_vgpu_err("failed to vmap shadow indirect ctx\n"); |
bcd0aede CW |
2816 | ret = PTR_ERR(map); |
2817 | goto put_obj; | |
be1da707 ZW |
2818 | } |
2819 | ||
894cf7d1 | 2820 | ret = i915_gem_object_set_to_cpu_domain(obj, false); |
be1da707 | 2821 | if (ret) { |
695fbc08 | 2822 | gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n"); |
be1da707 ZW |
2823 | goto unmap_src; |
2824 | } | |
2825 | ||
c10c1255 TZ |
2826 | ret = copy_gma_to_hva(workload->vgpu, |
2827 | workload->vgpu->gtt.ggtt_mm, | |
bcd0aede CW |
2828 | guest_gma, guest_gma + ctx_size, |
2829 | map); | |
8bcad07a | 2830 | if (ret < 0) { |
695fbc08 | 2831 | gvt_vgpu_err("fail to copy guest indirect ctx\n"); |
894cf7d1 | 2832 | goto unmap_src; |
be1da707 ZW |
2833 | } |
2834 | ||
894cf7d1 | 2835 | wa_ctx->indirect_ctx.obj = obj; |
bcd0aede | 2836 | wa_ctx->indirect_ctx.shadow_va = map; |
be1da707 ZW |
2837 | return 0; |
2838 | ||
2839 | unmap_src: | |
bcd0aede | 2840 | i915_gem_object_unpin_map(obj); |
894cf7d1 | 2841 | put_obj: |
ffeaf9aa | 2842 | i915_gem_object_put(obj); |
be1da707 ZW |
2843 | return ret; |
2844 | } | |
2845 | ||
2846 | static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) | |
2847 | { | |
2e679d48 | 2848 | u32 per_ctx_start[CACHELINE_DWORDS] = {0}; |
be1da707 ZW |
2849 | unsigned char *bb_start_sva; |
2850 | ||
8f63fc2b ZW |
2851 | if (!wa_ctx->per_ctx.valid) |
2852 | return 0; | |
2853 | ||
be1da707 ZW |
2854 | per_ctx_start[0] = 0x18800001; |
2855 | per_ctx_start[1] = wa_ctx->per_ctx.guest_gma; | |
2856 | ||
2857 | bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va + | |
2858 | wa_ctx->indirect_ctx.size; | |
2859 | ||
2860 | memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); | |
2861 | ||
2862 | return 0; | |
2863 | } | |
2864 | ||
2865 | int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) | |
2866 | { | |
2867 | int ret; | |
c10c1255 TZ |
2868 | struct intel_vgpu_workload *workload = container_of(wa_ctx, |
2869 | struct intel_vgpu_workload, | |
2870 | wa_ctx); | |
2871 | struct intel_vgpu *vgpu = workload->vgpu; | |
be1da707 ZW |
2872 | |
2873 | if (wa_ctx->indirect_ctx.size == 0) | |
2874 | return 0; | |
2875 | ||
2876 | ret = shadow_indirect_ctx(wa_ctx); | |
2877 | if (ret) { | |
695fbc08 | 2878 | gvt_vgpu_err("fail to shadow indirect ctx\n"); |
be1da707 ZW |
2879 | return ret; |
2880 | } | |
2881 | ||
2882 | combine_wa_ctx(wa_ctx); | |
2883 | ||
2884 | ret = scan_wa_ctx(wa_ctx); | |
2885 | if (ret) { | |
695fbc08 | 2886 | gvt_vgpu_err("scan wa ctx error\n"); |
be1da707 ZW |
2887 | return ret; |
2888 | } | |
2889 | ||
2890 | return 0; | |
2891 | } | |
2892 | ||
b007065a | 2893 | static const struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt, |
65e74392 | 2894 | unsigned int opcode, unsigned long rings) |
be1da707 | 2895 | { |
b007065a | 2896 | const struct cmd_info *info = NULL; |
be1da707 ZW |
2897 | unsigned int ring; |
2898 | ||
65e74392 | 2899 | for_each_set_bit(ring, &rings, I915_NUM_ENGINES) { |
be1da707 ZW |
2900 | info = find_cmd_entry(gvt, opcode, ring); |
2901 | if (info) | |
2902 | break; | |
2903 | } | |
2904 | return info; | |
2905 | } | |
2906 | ||
2907 | static int init_cmd_table(struct intel_gvt *gvt) | |
2908 | { | |
2909 | int i; | |
2910 | struct cmd_entry *e; | |
b007065a | 2911 | const struct cmd_info *info; |
be1da707 ZW |
2912 | unsigned int gen_type; |
2913 | ||
2914 | gen_type = intel_gvt_get_device_type(gvt); | |
2915 | ||
2916 | for (i = 0; i < ARRAY_SIZE(cmd_info); i++) { | |
2917 | if (!(cmd_info[i].devices & gen_type)) | |
2918 | continue; | |
2919 | ||
2920 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
2921 | if (!e) | |
2922 | return -ENOMEM; | |
2923 | ||
2924 | e->info = &cmd_info[i]; | |
2925 | info = find_cmd_entry_any_ring(gvt, | |
2926 | e->info->opcode, e->info->rings); | |
2927 | if (info) { | |
2928 | gvt_err("%s %s duplicated\n", e->info->name, | |
2929 | info->name); | |
ffdf16ed | 2930 | kfree(e); |
be1da707 ZW |
2931 | return -EEXIST; |
2932 | } | |
db47685d ZY |
2933 | if (cmd_info[i].opcode == OP_MI_NOOP) |
2934 | mi_noop_index = i; | |
be1da707 ZW |
2935 | |
2936 | INIT_HLIST_NODE(&e->hlist); | |
2937 | add_cmd_entry(gvt, e); | |
2938 | gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n", | |
2939 | e->info->name, e->info->opcode, e->info->flag, | |
2940 | e->info->devices, e->info->rings); | |
2941 | } | |
2942 | return 0; | |
2943 | } | |
2944 | ||
2945 | static void clean_cmd_table(struct intel_gvt *gvt) | |
2946 | { | |
2947 | struct hlist_node *tmp; | |
2948 | struct cmd_entry *e; | |
2949 | int i; | |
2950 | ||
2951 | hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist) | |
2952 | kfree(e); | |
2953 | ||
2954 | hash_init(gvt->cmd_table); | |
2955 | } | |
2956 | ||
2957 | void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt) | |
2958 | { | |
2959 | clean_cmd_table(gvt); | |
2960 | } | |
2961 | ||
2962 | int intel_gvt_init_cmd_parser(struct intel_gvt *gvt) | |
2963 | { | |
2964 | int ret; | |
2965 | ||
2966 | ret = init_cmd_table(gvt); | |
2967 | if (ret) { | |
2968 | intel_gvt_clean_cmd_parser(gvt); | |
2969 | return ret; | |
2970 | } | |
2971 | return 0; | |
2972 | } |