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f0c02c1b TU |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef I915_TIMELINE_H | |
26 | #define I915_TIMELINE_H | |
27 | ||
28 | #include <linux/lockdep.h> | |
29 | ||
30 | #include "i915_active.h" | |
31 | #include "i915_syncmap.h" | |
d1bf5dd8 | 32 | #include "intel_timeline_types.h" |
f0c02c1b | 33 | |
0986317a CW |
34 | struct drm_printer; |
35 | ||
f0c02c1b | 36 | struct intel_timeline * |
d1bf5dd8 CW |
37 | __intel_timeline_create(struct intel_gt *gt, |
38 | struct i915_vma *global_hwsp, | |
39 | unsigned int offset); | |
40 | ||
41 | static inline struct intel_timeline * | |
42 | intel_timeline_create(struct intel_gt *gt) | |
43 | { | |
44 | return __intel_timeline_create(gt, NULL, 0); | |
45 | } | |
46 | ||
b436a5f8 | 47 | struct intel_timeline * |
d1bf5dd8 | 48 | intel_timeline_create_from_engine(struct intel_engine_cs *engine, |
b436a5f8 | 49 | unsigned int offset); |
f0c02c1b TU |
50 | |
51 | static inline struct intel_timeline * | |
52 | intel_timeline_get(struct intel_timeline *timeline) | |
53 | { | |
54 | kref_get(&timeline->kref); | |
55 | return timeline; | |
56 | } | |
57 | ||
58 | void __intel_timeline_free(struct kref *kref); | |
59 | static inline void intel_timeline_put(struct intel_timeline *timeline) | |
60 | { | |
61 | kref_put(&timeline->kref, __intel_timeline_free); | |
62 | } | |
63 | ||
64 | static inline int __intel_timeline_sync_set(struct intel_timeline *tl, | |
65 | u64 context, u32 seqno) | |
66 | { | |
67 | return i915_syncmap_set(&tl->sync, context, seqno); | |
68 | } | |
69 | ||
70 | static inline int intel_timeline_sync_set(struct intel_timeline *tl, | |
71 | const struct dma_fence *fence) | |
72 | { | |
73 | return __intel_timeline_sync_set(tl, fence->context, fence->seqno); | |
74 | } | |
75 | ||
76 | static inline bool __intel_timeline_sync_is_later(struct intel_timeline *tl, | |
77 | u64 context, u32 seqno) | |
78 | { | |
79 | return i915_syncmap_is_later(&tl->sync, context, seqno); | |
80 | } | |
81 | ||
82 | static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl, | |
83 | const struct dma_fence *fence) | |
84 | { | |
85 | return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno); | |
86 | } | |
87 | ||
47b08693 ML |
88 | void __intel_timeline_pin(struct intel_timeline *tl); |
89 | int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww); | |
531958f6 | 90 | void intel_timeline_enter(struct intel_timeline *tl); |
f0c02c1b TU |
91 | int intel_timeline_get_seqno(struct intel_timeline *tl, |
92 | struct i915_request *rq, | |
93 | u32 *seqno); | |
531958f6 | 94 | void intel_timeline_exit(struct intel_timeline *tl); |
f0c02c1b TU |
95 | void intel_timeline_unpin(struct intel_timeline *tl); |
96 | ||
bd3ec9e7 CW |
97 | void intel_timeline_reset_seqno(const struct intel_timeline *tl); |
98 | ||
f0c02c1b TU |
99 | int intel_timeline_read_hwsp(struct i915_request *from, |
100 | struct i915_request *until, | |
101 | u32 *hwsp_offset); | |
102 | ||
4605bb73 CW |
103 | void intel_gt_init_timelines(struct intel_gt *gt); |
104 | void intel_gt_fini_timelines(struct intel_gt *gt); | |
f0c02c1b | 105 | |
0986317a CW |
106 | void intel_gt_show_timelines(struct intel_gt *gt, |
107 | struct drm_printer *m, | |
108 | void (*show_request)(struct drm_printer *m, | |
109 | const struct i915_request *rq, | |
110 | const char *prefix, | |
111 | int indent)); | |
112 | ||
b1ad5f6d CW |
113 | static inline bool |
114 | intel_timeline_is_last(const struct intel_timeline *tl, | |
115 | const struct i915_request *rq) | |
116 | { | |
117 | return list_is_last_rcu(&rq->link, &tl->requests); | |
118 | } | |
119 | ||
f0c02c1b | 120 | #endif |