[linux-block.git] / drivers / gpu / drm / i915 / gt / intel_lrc.h

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef _INTEL_LRC_H_
#define _INTEL_LRC_H_

#include "intel_engine.h"

/* Execlists regs */
#define RING_ELSP(base)				_MMIO((base) + 0x230)
#define RING_EXECLIST_STATUS_LO(base)		_MMIO((base) + 0x234)
#define RING_EXECLIST_STATUS_HI(base)		_MMIO((base) + 0x234 + 4)
#define RING_CONTEXT_CONTROL(base)		_MMIO((base) + 0x244)
#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
#define   CTX_CTRL_RS_CTX_ENABLE		(1 << 1)
#define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
#define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)
#define RING_EXECLIST_SQ_CONTENTS(base)		_MMIO((base) + 0x510)
#define RING_EXECLIST_CONTROL(base)		_MMIO((base) + 0x550)

#define	  EL_CTRL_LOAD				(1 << 0)

/* The docs specify that the write pointer wraps around after 5h, "After status
 * is written out to the last available status QW at offset 5h, this pointer
 * wraps to 0."
 *
 * Therefore, one must infer than even though there are 3 bits available, 6 and
 * 7 appear to be * reserved.
 */
#define GEN8_CSB_ENTRIES 6
#define GEN8_CSB_PTR_MASK 0x7
#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)

#define GEN11_CSB_ENTRIES 12
#define GEN11_CSB_PTR_MASK 0xf
#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)

enum {
	INTEL_CONTEXT_SCHEDULE_IN = 0,
	INTEL_CONTEXT_SCHEDULE_OUT,
	INTEL_CONTEXT_SCHEDULE_PREEMPTED,
};

/* Logical Rings */
void intel_logical_ring_cleanup(struct intel_engine_cs *engine);

int intel_execlists_submission_setup(struct intel_engine_cs *engine);
int intel_execlists_submission_init(struct intel_engine_cs *engine);

/* Logical Ring Contexts */

/*
 * We allocate a header at the start of the context image for our own
 * use, therefore the actual location of the logical state is offset
 * from the start of the VMA. The layout is
 *
 * | [guc]          | [hwsp] [logical state] |
 * |<- our header ->|<- context image      ->|
 *
 */
/* The first page is used for sharing data with the GuC */
#define LRC_GUCSHR_PN	(0)
#define LRC_GUCSHR_SZ	(1)
/* At the start of the context image is its per-process HWS page */
#define LRC_PPHWSP_PN	(LRC_GUCSHR_PN + LRC_GUCSHR_SZ)
#define LRC_PPHWSP_SZ	(1)
/* Finally we have the logical state for the context */
#define LRC_STATE_PN	(LRC_PPHWSP_PN + LRC_PPHWSP_SZ)

/*
 * Currently we include the PPHWSP in __intel_engine_context_size() so
 * the size of the header is synonymous with the start of the PPHWSP.
 */
#define LRC_HEADER_PAGES LRC_PPHWSP_PN

struct drm_printer;

struct drm_i915_private;

void intel_execlists_set_default_submission(struct intel_engine_cs *engine);

void intel_lr_context_reset(struct intel_engine_cs *engine,
			    struct intel_context *ce,
			    u32 head,
			    bool scrub);

void intel_execlists_show_requests(struct intel_engine_cs *engine,
				   struct drm_printer *m,
				   void (*show_request)(struct drm_printer *m,
							struct i915_request *rq,
							const char *prefix),
				   unsigned int max);

struct intel_context *
intel_execlists_create_virtual(struct i915_gem_context *ctx,
			       struct intel_engine_cs **siblings,
			       unsigned int count);

struct intel_context *
intel_execlists_clone_virtual(struct i915_gem_context *ctx,
			      struct intel_engine_cs *src);

#endif /* _INTEL_LRC_H_ */
Commit	Line	Data
b20385f1 OM	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#ifndef _INTEL_LRC_H_
	25	#define _INTEL_LRC_H_
	26
112ed2d3	27	#include "intel_engine.h"
e73bdd20	28
4ba70e44	29	/* Execlists regs */
baba6e57 DCS	30	#define RING_ELSP(base) _MMIO((base) + 0x230)
	31	#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
	32	#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
	33	#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
5baa22c5 ZW	34	#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
5baa22c5 ZW	35	#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
baba6e57	36	#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
517aaffe	37	#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
baba6e57 DCS	38	#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
	39	#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
	40	#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
7d4c75d9	41
05f0addd	42	#define EL_CTRL_LOAD (1 << 0)
4ba70e44	43
5590a5f0 BW	44	/* The docs specify that the write pointer wraps around after 5h, "After status
	45	* is written out to the last available status QW at offset 5h, this pointer
	46	* wraps to 0."
	47	*
	48	* Therefore, one must infer than even though there are 3 bits available, 6 and
	49	* 7 appear to be * reserved.
	50	*/
	51	#define GEN8_CSB_ENTRIES 6
	52	#define GEN8_CSB_PTR_MASK 0x7
	53	#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
	54	#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
7d4c75d9 MK	55
	56	#define GEN11_CSB_ENTRIES 12
	57	#define GEN11_CSB_PTR_MASK 0xf
	58	#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
	59	#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
5590a5f0	60
3c7ba635 ZW	61	enum {
	62	INTEL_CONTEXT_SCHEDULE_IN = 0,
	63	INTEL_CONTEXT_SCHEDULE_OUT,
d6c05113	64	INTEL_CONTEXT_SCHEDULE_PREEMPTED,
3c7ba635 ZW	65	};
3c7ba635 ZW	66
454afebd	67	/* Logical Rings */
0bc40be8	68	void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
11334c6a CW	69
	70	int intel_execlists_submission_setup(struct intel_engine_cs *engine);
	71	int intel_execlists_submission_init(struct intel_engine_cs *engine);
88d2ba2e	72
ede7d42b	73	/* Logical Ring Contexts */
d1675198	74
0b29c75a MT	75	/*
	76	* We allocate a header at the start of the context image for our own
	77	* use, therefore the actual location of the logical state is offset
	78	* from the start of the VMA. The layout is
	79	*
	80	* \| [guc] \| [hwsp] [logical state] \|
	81	* \|<- our header ->\|<- context image ->\|
	82	*
	83	*/
	84	/* The first page is used for sharing data with the GuC */
d1675198	85	#define LRC_GUCSHR_PN (0)
0b29c75a MT	86	#define LRC_GUCSHR_SZ (1)
	87	/* At the start of the context image is its per-process HWS page */
	88	#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + LRC_GUCSHR_SZ)
	89	#define LRC_PPHWSP_SZ (1)
	90	/* Finally we have the logical state for the context */
	91	#define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ)
	92
	93	/*
	94	* Currently we include the PPHWSP in __intel_engine_context_size() so
	95	* the size of the header is synonymous with the start of the PPHWSP.
	96	*/
	97	#define LRC_HEADER_PAGES LRC_PPHWSP_PN
d1675198	98
0212bdef CW	99	struct drm_printer;
0212bdef CW	100
e8a9c58f	101	struct drm_i915_private;
e2efd130	102
209b7955 CW	103	void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
209b7955 CW	104
292ad25c CW	105	void intel_lr_context_reset(struct intel_engine_cs *engine,
	106	struct intel_context *ce,
	107	u32 head,
	108	bool scrub);
	109
0212bdef CW	110	void intel_execlists_show_requests(struct intel_engine_cs *engine,
	111	struct drm_printer *m,
	112	void (show_request)(struct drm_printer m,
	113	struct i915_request *rq,
	114	const char *prefix),
	115	unsigned int max);
	116
6d06779e CW	117	struct intel_context *
	118	intel_execlists_create_virtual(struct i915_gem_context *ctx,
	119	struct intel_engine_cs **siblings,
	120	unsigned int count);
	121
	122	struct intel_context *
	123	intel_execlists_clone_virtual(struct i915_gem_context *ctx,
	124	struct intel_engine_cs *src);
	125
b20385f1	126	#endif /* _INTEL_LRC_H_ */