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e5be5c7a TU |
1 | /* SPDX-License-Identifier: MIT */ |
2 | /* | |
3 | * Copyright © 2019 Intel Corporation | |
4 | */ | |
5 | ||
6 | #ifndef __INTEL_GT_TYPES__ | |
7 | #define __INTEL_GT_TYPES__ | |
8 | ||
9 | #include <linux/ktime.h> | |
10 | #include <linux/list.h> | |
9b4d0598 | 11 | #include <linux/llist.h> |
e5be5c7a TU |
12 | #include <linux/mutex.h> |
13 | #include <linux/notifier.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/types.h> | |
9b4d0598 | 16 | #include <linux/workqueue.h> |
e5be5c7a | 17 | |
8b5689d7 | 18 | #include "uc/intel_uc.h" |
1e3dc1d8 | 19 | #include "intel_gsc.h" |
8b5689d7 | 20 | |
e5be5c7a | 21 | #include "i915_vma.h" |
3d7b3039 | 22 | #include "intel_engine_types.h" |
16e87459 | 23 | #include "intel_gt_buffer_pool_types.h" |
8781f051 | 24 | #include "intel_hwconfig.h" |
0dc3c562 | 25 | #include "intel_llc_types.h" |
cb823ed9 | 26 | #include "intel_reset_types.h" |
c1132367 | 27 | #include "intel_rc6_types.h" |
3e7abf81 | 28 | #include "intel_rps_types.h" |
94ce0d65 | 29 | #include "intel_migrate_types.h" |
e5be5c7a | 30 | #include "intel_wakeref.h" |
3ad2dd9c | 31 | #include "pxp/intel_pxp_types.h" |
e5be5c7a | 32 | |
724e9564 | 33 | struct drm_i915_private; |
d8a44248 | 34 | struct i915_ggtt; |
750e76b4 | 35 | struct intel_engine_cs; |
724e9564 TU |
36 | struct intel_uncore; |
37 | ||
0957e931 MR |
38 | struct intel_mmio_range { |
39 | u32 start; | |
40 | u32 end; | |
41 | }; | |
42 | ||
43 | /* | |
44 | * The hardware has multiple kinds of multicast register ranges that need | |
45 | * special register steering (and future platforms are expected to add | |
46 | * additional types). | |
47 | * | |
48 | * During driver startup, we initialize the steering control register to | |
49 | * direct reads to a slice/subslice that are valid for the 'subslice' class | |
50 | * of multicast registers. If another type of steering does not have any | |
51 | * overlap in valid steering targets with 'subslice' style registers, we will | |
52 | * need to explicitly re-steer reads of registers of the other type. | |
3ffe82d7 DCS |
53 | * |
54 | * Only the replication types that may need additional non-default steering | |
55 | * are listed here. | |
0957e931 MR |
56 | */ |
57 | enum intel_steering_type { | |
31939274 | 58 | L3BANK, |
3ffe82d7 DCS |
59 | MSLICE, |
60 | LNCF, | |
31939274 | 61 | |
0957e931 MR |
62 | NUM_STEERING_TYPES |
63 | }; | |
64 | ||
c92c36ed CW |
65 | enum intel_submission_method { |
66 | INTEL_SUBMISSION_RING, | |
67 | INTEL_SUBMISSION_ELSP, | |
68 | INTEL_SUBMISSION_GUC, | |
69 | }; | |
70 | ||
e5be5c7a | 71 | struct intel_gt { |
724e9564 TU |
72 | struct drm_i915_private *i915; |
73 | struct intel_uncore *uncore; | |
d8a44248 | 74 | struct i915_ggtt *ggtt; |
724e9564 | 75 | |
8b5689d7 | 76 | struct intel_uc uc; |
1e3dc1d8 | 77 | struct intel_gsc gsc; |
8b5689d7 | 78 | |
7938d615 TU |
79 | struct mutex tlb_invalidate_lock; |
80 | ||
d0a65249 VSD |
81 | struct i915_wa_list wa_list; |
82 | ||
c6fe28b0 | 83 | struct intel_gt_timelines { |
338aade9 | 84 | spinlock_t lock; /* protects active_list */ |
e5be5c7a | 85 | struct list_head active_list; |
e5be5c7a TU |
86 | } timelines; |
87 | ||
66101975 CW |
88 | struct intel_gt_requests { |
89 | /** | |
90 | * We leave the user IRQ off as much as possible, | |
91 | * but this means that requests will finish and never | |
92 | * be retired once the system goes idle. Set a timer to | |
93 | * fire periodically while the ring is running. When it | |
94 | * fires, go retire requests. | |
95 | */ | |
96 | struct delayed_work retire_work; | |
97 | } requests; | |
98 | ||
9b4d0598 TU |
99 | struct { |
100 | struct llist_head list; | |
101 | struct work_struct work; | |
102 | } watchdog; | |
103 | ||
e5be5c7a | 104 | struct intel_wakeref wakeref; |
16ffe73c | 105 | atomic_t user_wakeref; |
e5be5c7a TU |
106 | |
107 | struct list_head closed_vma; | |
108 | spinlock_t closed_lock; /* guards the list of closed_vma */ | |
109 | ||
9c878557 | 110 | ktime_t last_init_time; |
cb823ed9 CW |
111 | struct intel_reset reset; |
112 | ||
e5be5c7a TU |
113 | /** |
114 | * Is the GPU currently considered idle, or busy executing | |
115 | * userspace requests? Whilst idle, we allow runtime power | |
116 | * management to power down the hardware and display clocks. | |
117 | * In order to reduce the effect on performance, there | |
118 | * is a slight delay before we do so. | |
119 | */ | |
120 | intel_wakeref_t awake; | |
121 | ||
9c878557 | 122 | u32 clock_frequency; |
f170523a | 123 | u32 clock_period_ns; |
9c878557 | 124 | |
0dc3c562 | 125 | struct intel_llc llc; |
c1132367 | 126 | struct intel_rc6 rc6; |
3e7abf81 | 127 | struct intel_rps rps; |
c1132367 | 128 | |
d762043f | 129 | spinlock_t irq_lock; |
cf1c97dc | 130 | u32 gt_imr; |
58820574 | 131 | u32 pm_ier; |
d762043f | 132 | u32 pm_imr; |
2239e6df DCS |
133 | |
134 | u32 pm_guc_events; | |
750e76b4 | 135 | |
8c3b1ba0 CW |
136 | struct { |
137 | bool active; | |
138 | ||
139 | /** | |
140 | * @lock: Lock protecting the below fields. | |
141 | */ | |
142 | seqcount_mutex_t lock; | |
143 | ||
144 | /** | |
145 | * @total: Total time this engine was busy. | |
146 | * | |
147 | * Accumulated time not counting the most recent block in cases | |
148 | * where engine is currently busy (active > 0). | |
149 | */ | |
150 | ktime_t total; | |
151 | ||
152 | /** | |
153 | * @start: Timestamp of the last idle to active transition. | |
154 | * | |
155 | * Idle is defined as active == 0, active is active > 0. | |
156 | */ | |
157 | ktime_t start; | |
158 | } stats; | |
159 | ||
f1c4d157 | 160 | struct intel_engine_cs *engine[I915_NUM_ENGINES]; |
750e76b4 CW |
161 | struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] |
162 | [MAX_ENGINE_INSTANCE + 1]; | |
c92c36ed | 163 | enum intel_submission_method submission_method; |
e6ba7648 CW |
164 | |
165 | /* | |
166 | * Default address space (either GGTT or ppGTT depending on arch). | |
167 | * | |
168 | * Reserved for exclusive use by the kernel. | |
169 | */ | |
170 | struct i915_address_space *vm; | |
9c878557 | 171 | |
16e87459 CW |
172 | /* |
173 | * A pool of objects to use as shadow copies of client batch buffers | |
174 | * when the command parser is enabled. Prevents the client from | |
175 | * modifying the batch contents after software parsing. | |
176 | * | |
177 | * Buffers older than 1s are periodically reaped from the pool, | |
178 | * or may be reclaimed by the shrinker before then. | |
179 | */ | |
180 | struct intel_gt_buffer_pool buffer_pool; | |
181 | ||
9c878557 | 182 | struct i915_vma *scratch; |
792592e7 | 183 | |
94ce0d65 CW |
184 | struct intel_migrate migrate; |
185 | ||
0957e931 MR |
186 | const struct intel_mmio_range *steering_table[NUM_STEERING_TYPES]; |
187 | ||
b7563ec7 MR |
188 | struct { |
189 | u8 groupid; | |
190 | u8 instanceid; | |
191 | } default_steering; | |
192 | ||
bec68cc9 TU |
193 | /* |
194 | * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT. | |
195 | */ | |
196 | phys_addr_t phys_addr; | |
197 | ||
792592e7 | 198 | struct intel_gt_info { |
bec68cc9 TU |
199 | unsigned int id; |
200 | ||
792592e7 | 201 | intel_engine_mask_t engine_mask; |
938c778f JH |
202 | |
203 | u32 l3bank_mask; | |
204 | ||
792592e7 DCS |
205 | u8 num_engines; |
206 | ||
ff04f8be MR |
207 | /* General presence of SFC units */ |
208 | u8 sfc_mask; | |
209 | ||
792592e7 DCS |
210 | /* Media engine access to SFC per instance */ |
211 | u8 vdbox_sfc_access; | |
0b6613c6 VSD |
212 | |
213 | /* Slice/subslice/EU info */ | |
214 | struct sseu_dev_info sseu; | |
3ffe82d7 DCS |
215 | |
216 | unsigned long mslice_mask; | |
8781f051 JH |
217 | |
218 | /** @hwconfig: hardware configuration data */ | |
219 | struct intel_hwconfig hwconfig; | |
792592e7 | 220 | } info; |
b62aa57e AS |
221 | |
222 | struct { | |
223 | u8 uc_index; | |
224 | } mocs; | |
3ad2dd9c DCS |
225 | |
226 | struct intel_pxp pxp; | |
e5be5c7a TU |
227 | }; |
228 | ||
46c5847e LL |
229 | enum intel_gt_scratch_field { |
230 | /* 8 bytes */ | |
231 | INTEL_GT_SCRATCH_FIELD_DEFAULT = 0, | |
232 | ||
46c5847e LL |
233 | /* 8 bytes */ |
234 | INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128, | |
235 | ||
236 | /* 8 bytes */ | |
237 | INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256, | |
238 | ||
daed3e44 LL |
239 | /* 6 * 8 bytes */ |
240 | INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048, | |
241 | ||
242 | /* 4 bytes */ | |
243 | INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096, | |
46c5847e LL |
244 | }; |
245 | ||
e5be5c7a | 246 | #endif /* __INTEL_GT_TYPES_H__ */ |