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Merge tag 'probes-fixes-v6.16-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / gpu / drm / i915 / gt / intel_gt_sysfs_pm.c
CommitLineData
80cf8af1
AS		 1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include <drm/drm_device.h>
7#include <linux/sysfs.h>
8#include <linux/printk.h>
9
10#include "i915_drv.h"
fa68bff7 11#include "i915_reg.h"
80cf8af1
AS		 12#include "i915_sysfs.h"
13#include "intel_gt.h"
67804e48 14#include "intel_gt_print.h"
80cf8af1
AS		 15#include "intel_gt_regs.h"
16#include "intel_gt_sysfs.h"
17#include "intel_gt_sysfs_pm.h"
9d15dd1b 18#include "intel_pcode.h"
80cf8af1 19#include "intel_rc6.h"
56a709cf 20#include "intel_rps.h"
80cf8af1 21
80cf8af1
AS		 22enum intel_gt_sysfs_op {
23 INTEL_GT_SYSFS_MIN = 0,
24 INTEL_GT_SYSFS_MAX,
25};
26
56a709cf 27static int
a8a4f046 28sysfs_gt_attribute_w_func(struct kobject *kobj, struct attribute *attr,
56a709cf
AS		 29 int (func)(struct intel_gt *gt, u32 val), u32 val)
30{
31 struct intel_gt *gt;
32 int ret;
33
a8a4f046 34 if (!is_object_gt(kobj)) {
56a709cf 35 int i;
a8a4f046 36 struct device *dev = kobj_to_dev(kobj);
56a709cf
AS		 37 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
38
39 for_each_gt(gt, i915, i) {
40 ret = func(gt, val);
41 if (ret)
42 break;
43 }
44 } else {
a8a4f046 45 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
56a709cf
AS		 46 ret = func(gt, val);
47 }
48
49 return ret;
50}
51
80cf8af1 52static u32
a8a4f046 53sysfs_gt_attribute_r_func(struct kobject *kobj, struct attribute *attr,
80cf8af1
AS		 54 u32 (func)(struct intel_gt *gt),
55 enum intel_gt_sysfs_op op)
56{
57 struct intel_gt *gt;
58 u32 ret;
59
60 ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
61
a8a4f046 62 if (!is_object_gt(kobj)) {
80cf8af1 63 int i;
a8a4f046 64 struct device *dev = kobj_to_dev(kobj);
80cf8af1
AS		 65 struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
66
67 for_each_gt(gt, i915, i) {
68 u32 val = func(gt);
69
70 switch (op) {
71 case INTEL_GT_SYSFS_MIN:
72 if (val < ret)
73 ret = val;
74 break;
75
76 case INTEL_GT_SYSFS_MAX:
77 if (val > ret)
78 ret = val;
79 break;
80 }
81 }
82 } else {
a8a4f046 83 gt = intel_gt_sysfs_get_drvdata(kobj, attr->name);
80cf8af1
AS		 84 ret = func(gt);
85 }
86
87 return ret;
88}
89
90/* RC6 interfaces will show the minimum RC6 residency value */
91#define sysfs_gt_attribute_r_min_func(d, a, f) \
92 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
93
56a709cf 94/* Frequency interfaces will show the maximum frequency value */
80cf8af1
AS		 95#define sysfs_gt_attribute_r_max_func(d, a, f) \
96 sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
97
a8a4f046
NC		 98#define INTEL_GT_SYSFS_SHOW(_name, _attr_type) \
99 static ssize_t _name##_show_common(struct kobject *kobj, \
100 struct attribute *attr, char *buff) \
101 { \
102 u32 val = sysfs_gt_attribute_r_##_attr_type##_func(kobj, attr, \
103 __##_name##_show); \
104 \
105 return sysfs_emit(buff, "%u\n", val); \
106 } \
107 static ssize_t _name##_show(struct kobject *kobj, \
108 struct kobj_attribute *attr, char *buff) \
109 { \
110 return _name ##_show_common(kobj, &attr->attr, buff); \
111 } \
112 static ssize_t _name##_dev_show(struct device *dev, \
113 struct device_attribute *attr, char *buff) \
114 { \
115 return _name##_show_common(&dev->kobj, &attr->attr, buff); \
116 }
117
118#define INTEL_GT_SYSFS_STORE(_name, _func) \
119 static ssize_t _name##_store_common(struct kobject *kobj, \
120 struct attribute *attr, \
121 const char *buff, size_t count) \
122 { \
123 int ret; \
124 u32 val; \
125 \
126 ret = kstrtou32(buff, 0, &val); \
127 if (ret) \
128 return ret; \
129 \
130 ret = sysfs_gt_attribute_w_func(kobj, attr, _func, val); \
131 \
132 return ret ?: count; \
133 } \
134 static ssize_t _name##_store(struct kobject *kobj, \
135 struct kobj_attribute *attr, const char *buff, \
136 size_t count) \
137 { \
138 return _name##_store_common(kobj, &attr->attr, buff, count); \
139 } \
140 static ssize_t _name##_dev_store(struct device *dev, \
141 struct device_attribute *attr, \
142 const char *buff, size_t count) \
143 { \
144 return _name##_store_common(&dev->kobj, &attr->attr, buff, count); \
145 }
146
147#define INTEL_GT_SYSFS_SHOW_MAX(_name) INTEL_GT_SYSFS_SHOW(_name, max)
148#define INTEL_GT_SYSFS_SHOW_MIN(_name) INTEL_GT_SYSFS_SHOW(_name, min)
149
150#define INTEL_GT_ATTR_RW(_name) \
151 static struct kobj_attribute attr_##_name = __ATTR_RW(_name)
152
153#define INTEL_GT_ATTR_RO(_name) \
154 static struct kobj_attribute attr_##_name = __ATTR_RO(_name)
155
156#define INTEL_GT_DUAL_ATTR_RW(_name) \
157 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0644, \
158 _name##_dev_show, \
159 _name##_dev_store); \
160 INTEL_GT_ATTR_RW(_name)
161
162#define INTEL_GT_DUAL_ATTR_RO(_name) \
163 static struct device_attribute dev_attr_##_name = __ATTR(_name, 0444, \
164 _name##_dev_show, \
165 NULL); \
166 INTEL_GT_ATTR_RO(_name)
167
78d0b455 168static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
80cf8af1
AS		 169{
170 intel_wakeref_t wakeref;
171 u64 res = 0;
172
173 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
78d0b455 174 res = intel_rc6_residency_us(&gt->rc6, id);
80cf8af1
AS		 175
176 return DIV_ROUND_CLOSEST_ULL(res, 1000);
177}
178
a8a4f046
NC		 179static ssize_t rc6_enable_show(struct kobject *kobj,
180 struct kobj_attribute *attr,
181 char *buff)
80cf8af1 182{
a8a4f046
NC		 183 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
184
4104e634 185 return sysfs_emit(buff, "%x\n", gt->rc6.enabled);
80cf8af1
AS		 186}
187
a8a4f046
NC		 188static ssize_t rc6_enable_dev_show(struct device *dev,
189 struct device_attribute *attr,
190 char *buff)
80cf8af1 191{
a8a4f046 192 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(&dev->kobj, attr->attr.name);
80cf8af1 193
4104e634 194 return sysfs_emit(buff, "%x\n", gt->rc6.enabled);
80cf8af1
AS		 195}
196
a8a4f046 197static u32 __rc6_residency_ms_show(struct intel_gt *gt)
80cf8af1 198{
78d0b455 199 return get_residency(gt, INTEL_RC6_RES_RC6);
80cf8af1
AS		 200}
201
a8a4f046 202static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
80cf8af1 203{
78d0b455 204 return get_residency(gt, INTEL_RC6_RES_RC6p);
80cf8af1
AS		 205}
206
207static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
208{
78d0b455 209 return get_residency(gt, INTEL_RC6_RES_RC6pp);
80cf8af1
AS		 210}
211
80cf8af1
AS		 212static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
213{
78d0b455 214 return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
80cf8af1
AS		 215}
216
a8a4f046
NC		 217INTEL_GT_SYSFS_SHOW_MIN(rc6_residency_ms);
218INTEL_GT_SYSFS_SHOW_MIN(rc6p_residency_ms);
219INTEL_GT_SYSFS_SHOW_MIN(rc6pp_residency_ms);
220INTEL_GT_SYSFS_SHOW_MIN(media_rc6_residency_ms);
80cf8af1 221
a8a4f046
NC		 222INTEL_GT_DUAL_ATTR_RO(rc6_enable);
223INTEL_GT_DUAL_ATTR_RO(rc6_residency_ms);
224INTEL_GT_DUAL_ATTR_RO(rc6p_residency_ms);
225INTEL_GT_DUAL_ATTR_RO(rc6pp_residency_ms);
226INTEL_GT_DUAL_ATTR_RO(media_rc6_residency_ms);
80cf8af1
AS		 227
228static struct attribute *rc6_attrs[] = {
a8a4f046
NC		 229 &attr_rc6_enable.attr,
230 &attr_rc6_residency_ms.attr,
231 NULL
232};
233
234static struct attribute *rc6p_attrs[] = {
235 &attr_rc6p_residency_ms.attr,
236 &attr_rc6pp_residency_ms.attr,
237 NULL
238};
239
240static struct attribute *media_rc6_attrs[] = {
241 &attr_media_rc6_residency_ms.attr,
242 NULL
243};
244
245static struct attribute *rc6_dev_attrs[] = {
80cf8af1
AS		 246 &dev_attr_rc6_enable.attr,
247 &dev_attr_rc6_residency_ms.attr,
248 NULL
249};
250
a8a4f046 251static struct attribute *rc6p_dev_attrs[] = {
80cf8af1
AS		 252 &dev_attr_rc6p_residency_ms.attr,
253 &dev_attr_rc6pp_residency_ms.attr,
254 NULL
255};
256
a8a4f046 257static struct attribute *media_rc6_dev_attrs[] = {
80cf8af1
AS		 258 &dev_attr_media_rc6_residency_ms.attr,
259 NULL
260};
261
262static const struct attribute_group rc6_attr_group[] = {
263 { .attrs = rc6_attrs, },
a8a4f046 264 { .name = power_group_name, .attrs = rc6_dev_attrs, },
80cf8af1
AS		 265};
266
267static const struct attribute_group rc6p_attr_group[] = {
268 { .attrs = rc6p_attrs, },
a8a4f046 269 { .name = power_group_name, .attrs = rc6p_dev_attrs, },
80cf8af1
AS		 270};
271
272static const struct attribute_group media_rc6_attr_group[] = {
273 { .attrs = media_rc6_attrs, },
a8a4f046 274 { .name = power_group_name, .attrs = media_rc6_dev_attrs, },
80cf8af1
AS		 275};
276
277static int __intel_gt_sysfs_create_group(struct kobject *kobj,
278 const struct attribute_group *grp)
279{
280 return is_object_gt(kobj) ?
281 sysfs_create_group(kobj, &grp[0]) :
282 sysfs_merge_group(kobj, &grp[1]);
283}
284
285static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
286{
287 int ret;
288
196c9226 289 if (!IS_ENABLED(CONFIG_PM) || !HAS_RC6(gt->i915))
80cf8af1
AS		 290 return;
291
292 ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
293 if (ret)
67804e48 294 gt_warn(gt, "failed to create RC6 sysfs files (%pe)\n", ERR_PTR(ret));
80cf8af1
AS		 295
296 /*
297 * cannot use the is_visible() attribute because
298 * the upper object inherits from the parent group.
299 */
300 if (HAS_RC6p(gt->i915)) {
301 ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
302 if (ret)
67804e48 303 gt_warn(gt, "failed to create RC6p sysfs files (%pe)\n", ERR_PTR(ret));
80cf8af1
AS		 304 }
305
306 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
307 ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
308 if (ret)
67804e48 309 gt_warn(gt, "failed to create media RC6 sysfs files (%pe)\n", ERR_PTR(ret));
80cf8af1
AS		 310 }
311}
80cf8af1 312
56a709cf
AS		 313static u32 __act_freq_mhz_show(struct intel_gt *gt)
314{
315 return intel_rps_read_actual_frequency(&gt->rps);
316}
317
56a709cf
AS		 318static u32 __cur_freq_mhz_show(struct intel_gt *gt)
319{
320 return intel_rps_get_requested_frequency(&gt->rps);
321}
322
56a709cf
AS		 323static u32 __boost_freq_mhz_show(struct intel_gt *gt)
324{
325 return intel_rps_get_boost_frequency(&gt->rps);
326}
327
56a709cf
AS		 328static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
329{
330 return intel_rps_set_boost_frequency(&gt->rps, val);
331}
332
a8a4f046 333static u32 __RP0_freq_mhz_show(struct intel_gt *gt)
56a709cf
AS		 334{
335 return intel_rps_get_rp0_frequency(&gt->rps);
336}
337
a8a4f046 338static u32 __RPn_freq_mhz_show(struct intel_gt *gt)
56a709cf
AS		 339{
340 return intel_rps_get_rpn_frequency(&gt->rps);
341}
342
a8a4f046 343static u32 __RP1_freq_mhz_show(struct intel_gt *gt)
56a709cf 344{
a8a4f046 345 return intel_rps_get_rp1_frequency(&gt->rps);
56a709cf
AS		 346}
347
348static u32 __max_freq_mhz_show(struct intel_gt *gt)
349{
350 return intel_rps_get_max_frequency(&gt->rps);
351}
352
56a709cf
AS		 353static int __set_max_freq(struct intel_gt *gt, u32 val)
354{
355 return intel_rps_set_max_frequency(&gt->rps, val);
356}
357
56a709cf
AS		 358static u32 __min_freq_mhz_show(struct intel_gt *gt)
359{
360 return intel_rps_get_min_frequency(&gt->rps);
361}
362
56a709cf
AS		 363static int __set_min_freq(struct intel_gt *gt, u32 val)
364{
365 return intel_rps_set_min_frequency(&gt->rps, val);
366}
367
56a709cf
AS		 368static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
369{
370 struct intel_rps *rps = &gt->rps;
371
372 return intel_gpu_freq(rps, rps->efficient_freq);
373}
374
a8a4f046
NC		 375INTEL_GT_SYSFS_SHOW_MAX(act_freq_mhz);
376INTEL_GT_SYSFS_SHOW_MAX(boost_freq_mhz);
377INTEL_GT_SYSFS_SHOW_MAX(cur_freq_mhz);
378INTEL_GT_SYSFS_SHOW_MAX(RP0_freq_mhz);
379INTEL_GT_SYSFS_SHOW_MAX(RP1_freq_mhz);
380INTEL_GT_SYSFS_SHOW_MAX(RPn_freq_mhz);
381INTEL_GT_SYSFS_SHOW_MAX(max_freq_mhz);
382INTEL_GT_SYSFS_SHOW_MIN(min_freq_mhz);
383INTEL_GT_SYSFS_SHOW_MAX(vlv_rpe_freq_mhz);
384INTEL_GT_SYSFS_STORE(boost_freq_mhz, __boost_freq_mhz_store);
385INTEL_GT_SYSFS_STORE(max_freq_mhz, __set_max_freq);
386INTEL_GT_SYSFS_STORE(min_freq_mhz, __set_min_freq);
387
388#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store, _show_dev, _store_dev) \
389 static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, \
390 _show_dev, _store_dev); \
391 static struct kobj_attribute attr_rps_##_name = __ATTR(rps_##_name, _mode, \
392 _show, _store)
393
394#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
395 INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL, \
396 _name##_dev_show, NULL)
397#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
398 INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store, \
399 _name##_dev_show, _name##_dev_store)
56a709cf 400
1ade3081
AS		 401/* The below macros generate static structures */
402INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
403INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
404INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
405INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
406INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
407INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
408INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
409INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
a8a4f046
NC		 410INTEL_GT_RPS_SYSFS_ATTR_RO(vlv_rpe_freq_mhz);
411
412#define GEN6_ATTR(p, s) { \
413 &p##attr_##s##_act_freq_mhz.attr, \
414 &p##attr_##s##_cur_freq_mhz.attr, \
415 &p##attr_##s##_boost_freq_mhz.attr, \
416 &p##attr_##s##_max_freq_mhz.attr, \
417 &p##attr_##s##_min_freq_mhz.attr, \
418 &p##attr_##s##_RP0_freq_mhz.attr, \
419 &p##attr_##s##_RP1_freq_mhz.attr, \
420 &p##attr_##s##_RPn_freq_mhz.attr, \
56a709cf
AS		 421 NULL, \
422 }
423
a8a4f046
NC		 424#define GEN6_RPS_ATTR GEN6_ATTR(, rps)
425#define GEN6_GT_ATTR GEN6_ATTR(dev_, gt)
56a709cf
AS		 426
427static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
428static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
429
a8a4f046
NC		 430static ssize_t punit_req_freq_mhz_show(struct kobject *kobj,
431 struct kobj_attribute *attr,
fa68bff7
SS		 432 char *buff)
433{
a8a4f046 434 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
fa68bff7
SS		 435 u32 preq = intel_rps_read_punit_req_frequency(&gt->rps);
436
437 return sysfs_emit(buff, "%u\n", preq);
438}
439
55f9720d
VB		 440static ssize_t slpc_ignore_eff_freq_show(struct kobject *kobj,
441 struct kobj_attribute *attr,
442 char *buff)
443{
444 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
01b2b8cc 445 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc;
55f9720d
VB		 446
447 return sysfs_emit(buff, "%u\n", slpc->ignore_eff_freq);
448}
449
450static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj,
451 struct kobj_attribute *attr,
452 const char *buff, size_t count)
453{
454 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
01b2b8cc 455 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc;
55f9720d
VB		 456 int err;
457 u32 val;
458
459 err = kstrtou32(buff, 0, &val);
460 if (err)
461 return err;
462
463 err = intel_guc_slpc_set_ignore_eff_freq(slpc, val);
464 return err ?: count;
465}
466
4a82ceb0
VB		 467static ssize_t slpc_power_profile_show(struct kobject *kobj,
468 struct kobj_attribute *attr,
469 char *buff)
470{
471 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
472 struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
473
474 switch (slpc->power_profile) {
475 case SLPC_POWER_PROFILES_BASE:
476 return sysfs_emit(buff, "[%s] %s\n", "base", "power_saving");
477 case SLPC_POWER_PROFILES_POWER_SAVING:
478 return sysfs_emit(buff, "%s [%s]\n", "base", "power_saving");
479 }
480
481 return sysfs_emit(buff, "%u\n", slpc->power_profile);
482}
483
484static ssize_t slpc_power_profile_store(struct kobject *kobj,
485 struct kobj_attribute *attr,
486 const char *buff, size_t count)
487{
488 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
489 struct intel_guc_slpc *slpc = &gt->uc.guc.slpc;
490 char power_saving[] = "power_saving";
491 char base[] = "base";
492 int err;
493 u32 val;
494
495 if (!strncmp(buff, power_saving, sizeof(power_saving) - 1))
496 val = SLPC_POWER_PROFILES_POWER_SAVING;
497 else if (!strncmp(buff, base, sizeof(base) - 1))
498 val = SLPC_POWER_PROFILES_BASE;
499 else
500 return -EINVAL;
501
502 err = intel_guc_slpc_set_power_profile(slpc, val);
503 return err ?: count;
504}
505
fa68bff7
SS		 506struct intel_gt_bool_throttle_attr {
507 struct attribute attr;
a8a4f046 508 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
fa68bff7 509 char *buf);
1551b916 510 i915_reg_t (*reg32)(struct intel_gt *gt);
fa68bff7
SS		 511 u32 mask;
512};
513
a8a4f046
NC		 514static ssize_t throttle_reason_bool_show(struct kobject *kobj,
515 struct kobj_attribute *attr,
fa68bff7
SS		 516 char *buff)
517{
a8a4f046 518 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
fa68bff7
SS		 519 struct intel_gt_bool_throttle_attr *t_attr =
520 (struct intel_gt_bool_throttle_attr *) attr;
1551b916 521 bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32(gt), t_attr->mask);
fa68bff7
SS		 522
523 return sysfs_emit(buff, "%u\n", val);
524}
525
526#define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
527struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
528 .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
529 .show = throttle_reason_bool_show, \
1551b916 530 .reg32 = intel_gt_perf_limit_reasons_reg, \
fa68bff7
SS		 531 .mask = mask__, \
532}
533
a8a4f046 534INTEL_GT_ATTR_RO(punit_req_freq_mhz);
fa68bff7
SS		 535static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
536static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
537static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
538static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
539static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
540static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
541static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
542static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
543static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
544
0d2d2010 545static const struct attribute *throttle_reason_attrs[] = {
fa68bff7
SS		 546 &attr_throttle_reason_status.attr,
547 &attr_throttle_reason_pl1.attr,
548 &attr_throttle_reason_pl2.attr,
549 &attr_throttle_reason_pl4.attr,
550 &attr_throttle_reason_thermal.attr,
551 &attr_throttle_reason_prochot.attr,
552 &attr_throttle_reason_ratl.attr,
553 &attr_throttle_reason_vr_thermalert.attr,
554 &attr_throttle_reason_vr_tdc.attr,
555 NULL
556};
557
26be7cd8
AD		 558/*
559 * Scaling for multipliers (aka frequency factors).
560 * The format of the value in the register is u8.8.
561 *
562 * The presentation to userspace is inspired by the perf event framework.
563 * See:
564 * Documentation/ABI/testing/sysfs-bus-event_source-devices-events
565 * for description of:
566 * /sys/bus/event_source/devices/<pmu>/events/<event>.scale
567 *
568 * Summary: Expose two sysfs files for each multiplier.
569 *
570 * 1. File <attr> contains a raw hardware value.
571 * 2. File <attr>.scale contains the multiplicative scale factor to be
572 * used by userspace to compute the actual value.
573 *
574 * So userspace knows that to get the frequency_factor it multiplies the
575 * provided value by the specified scale factor and vice-versa.
576 *
577 * That way there is no precision loss in the kernel interface and API
578 * is future proof should one day the hardware register change to u16.u16,
579 * on some platform. (Or any other fixed point representation.)
580 *
581 * Example:
582 * File <attr> contains the value 2.5, represented as u8.8 0x0280, which
583 * is comprised of:
584 * - an integer part of 2
585 * - a fractional part of 0x80 (representing 0x80 / 2^8 == 0x80 / 256).
586 * File <attr>.scale contains a string representation of floating point
587 * value 0.00390625 (which is (1 / 256)).
588 * Userspace computes the actual value:
589 * 0x0280 * 0.00390625 -> 2.5
590 * or converts an actual value to the value to be written into <attr>:
591 * 2.5 / 0.00390625 -> 0x0280
592 */
593
594#define U8_8_VAL_MASK 0xffff
595#define U8_8_SCALE_TO_VALUE "0.00390625"
596
a8a4f046
NC		 597static ssize_t freq_factor_scale_show(struct kobject *kobj,
598 struct kobj_attribute *attr,
26be7cd8
AD		 599 char *buff)
600{
601 return sysfs_emit(buff, "%s\n", U8_8_SCALE_TO_VALUE);
602}
603
604static u32 media_ratio_mode_to_factor(u32 mode)
605{
606 /* 0 -> 0, 1 -> 256, 2 -> 128 */
607 return !mode ? mode : 256 / mode;
608}
609
a8a4f046
NC		 610static ssize_t media_freq_factor_show(struct kobject *kobj,
611 struct kobj_attribute *attr,
26be7cd8
AD		 612 char *buff)
613{
a8a4f046 614 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
26be7cd8
AD		 615 intel_wakeref_t wakeref;
616 u32 mode;
617
618 /*
619 * Retrieve media_ratio_mode from GEN6_RPNSWREQ bit 13 set by
620 * GuC. GEN6_RPNSWREQ:13 value 0 represents 1:2 and 1 represents 1:1
621 */
cb4046d2
LDM		 622 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
623 mode = intel_uncore_read(gt->uncore, GEN6_RPNSWREQ);
624
625 mode = REG_FIELD_GET(GEN12_MEDIA_FREQ_RATIO, mode) ?
626 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE :
627 SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO;
26be7cd8
AD		 628
629 return sysfs_emit(buff, "%u\n", media_ratio_mode_to_factor(mode));
630}
631
a8a4f046
NC		 632static ssize_t media_freq_factor_store(struct kobject *kobj,
633 struct kobj_attribute *attr,
26be7cd8
AD		 634 const char *buff, size_t count)
635{
a8a4f046 636 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
01b2b8cc 637 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc;
26be7cd8
AD		 638 u32 factor, mode;
639 int err;
640
641 err = kstrtou32(buff, 0, &factor);
642 if (err)
643 return err;
644
645 for (mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
646 mode <= SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO; mode++)
647 if (factor == media_ratio_mode_to_factor(mode))
648 break;
649
650 if (mode > SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO)
651 return -EINVAL;
652
653 err = intel_guc_slpc_set_media_ratio_mode(slpc, mode);
654 if (!err) {
655 slpc->media_ratio_mode = mode;
656 DRM_DEBUG("Set slpc->media_ratio_mode to %d", mode);
657 }
658 return err ?: count;
659}
660
a8a4f046
NC		 661static ssize_t media_RP0_freq_mhz_show(struct kobject *kobj,
662 struct kobj_attribute *attr,
9d15dd1b
DS		 663 char *buff)
664{
a8a4f046 665 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
9d15dd1b
DS		 666 u32 val;
667 int err;
668
7d809707 669 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
9d15dd1b
DS		 670 PCODE_MBOX_FC_SC_READ_FUSED_P0,
671 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
672
673 if (err)
674 return err;
675
676 /* Fused media RP0 read from pcode is in units of 50 MHz */
677 val *= GT_FREQUENCY_MULTIPLIER;
678
679 return sysfs_emit(buff, "%u\n", val);
680}
681
a8a4f046
NC		 682static ssize_t media_RPn_freq_mhz_show(struct kobject *kobj,
683 struct kobj_attribute *attr,
9d15dd1b
DS		 684 char *buff)
685{
a8a4f046 686 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
9d15dd1b
DS		 687 u32 val;
688 int err;
689
7d809707 690 err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,
9d15dd1b
DS		 691 PCODE_MBOX_FC_SC_READ_FUSED_PN,
692 PCODE_MBOX_DOMAIN_MEDIAFF, &val);
693
694 if (err)
695 return err;
696
697 /* Fused media RPn read from pcode is in units of 50 MHz */
698 val *= GT_FREQUENCY_MULTIPLIER;
699
700 return sysfs_emit(buff, "%u\n", val);
701}
702
a8a4f046
NC		 703INTEL_GT_ATTR_RW(media_freq_factor);
704static struct kobj_attribute attr_media_freq_factor_scale =
26be7cd8 705 __ATTR(media_freq_factor.scale, 0444, freq_factor_scale_show, NULL);
a8a4f046
NC		 706INTEL_GT_ATTR_RO(media_RP0_freq_mhz);
707INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
26be7cd8 708
55f9720d 709INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
4a82ceb0 710INTEL_GT_ATTR_RW(slpc_power_profile);
55f9720d 711
26be7cd8 712static const struct attribute *media_perf_power_attrs[] = {
a8a4f046
NC		 713 &attr_media_freq_factor.attr,
714 &attr_media_freq_factor_scale.attr,
715 &attr_media_RP0_freq_mhz.attr,
716 &attr_media_RPn_freq_mhz.attr,
26be7cd8
AD		 717 NULL
718};
719
d84990a6
TU		 720static ssize_t
721rps_up_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
722 char *buf)
723{
724 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
725 struct intel_rps *rps = &gt->rps;
726
727 return sysfs_emit(buf, "%u\n", intel_rps_get_up_threshold(rps));
728}
729
730static ssize_t
731rps_up_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
732 const char *buf, size_t count)
733{
734 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
735 struct intel_rps *rps = &gt->rps;
736 int ret;
737 u8 val;
738
739 ret = kstrtou8(buf, 10, &val);
740 if (ret)
741 return ret;
742
743 ret = intel_rps_set_up_threshold(rps, val);
744
745 return ret == 0 ? count : ret;
746}
747
748static struct kobj_attribute rps_up_threshold_pct =
749 __ATTR(rps_up_threshold_pct,
750 0664,
751 rps_up_threshold_pct_show,
752 rps_up_threshold_pct_store);
753
754static ssize_t
755rps_down_threshold_pct_show(struct kobject *kobj, struct kobj_attribute *attr,
756 char *buf)
757{
758 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
759 struct intel_rps *rps = &gt->rps;
760
761 return sysfs_emit(buf, "%u\n", intel_rps_get_down_threshold(rps));
762}
763
764static ssize_t
765rps_down_threshold_pct_store(struct kobject *kobj, struct kobj_attribute *attr,
766 const char *buf, size_t count)
767{
768 struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
769 struct intel_rps *rps = &gt->rps;
770 int ret;
771 u8 val;
772
773 ret = kstrtou8(buf, 10, &val);
774 if (ret)
775 return ret;
776
777 ret = intel_rps_set_down_threshold(rps, val);
778
779 return ret == 0 ? count : ret;
780}
781
782static struct kobj_attribute rps_down_threshold_pct =
783 __ATTR(rps_down_threshold_pct,
784 0664,
785 rps_down_threshold_pct_show,
786 rps_down_threshold_pct_store);
787
788static const struct attribute * const gen6_gt_rps_attrs[] = {
789 &rps_up_threshold_pct.attr,
790 &rps_down_threshold_pct.attr,
791 NULL
792};
793
fdff0a85
AD		 794static ssize_t
795default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
796{
797 struct intel_gt *gt = kobj_to_gt(kobj->parent);
798
799 return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
800}
801
802static struct kobj_attribute default_min_freq_mhz =
803__ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
804
805static ssize_t
806default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
807{
808 struct intel_gt *gt = kobj_to_gt(kobj->parent);
809
810 return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
811}
812
813static struct kobj_attribute default_max_freq_mhz =
814__ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
815
d84990a6
TU		 816static ssize_t
817default_rps_up_threshold_pct_show(struct kobject *kobj,
818 struct kobj_attribute *attr,
819 char *buf)
820{
821 struct intel_gt *gt = kobj_to_gt(kobj->parent);
822
823 return sysfs_emit(buf, "%u\n", gt->defaults.rps_up_threshold);
824}
825
826static struct kobj_attribute default_rps_up_threshold_pct =
827__ATTR(rps_up_threshold_pct, 0444, default_rps_up_threshold_pct_show, NULL);
828
829static ssize_t
830default_rps_down_threshold_pct_show(struct kobject *kobj,
831 struct kobj_attribute *attr,
832 char *buf)
833{
834 struct intel_gt *gt = kobj_to_gt(kobj->parent);
835
836 return sysfs_emit(buf, "%u\n", gt->defaults.rps_down_threshold);
837}
838
839static struct kobj_attribute default_rps_down_threshold_pct =
840__ATTR(rps_down_threshold_pct, 0444, default_rps_down_threshold_pct_show, NULL);
841
fdff0a85
AD		 842static const struct attribute * const rps_defaults_attrs[] = {
843 &default_min_freq_mhz.attr,
844 &default_max_freq_mhz.attr,
d84990a6
TU		 845 &default_rps_up_threshold_pct.attr,
846 &default_rps_down_threshold_pct.attr,
fdff0a85
AD		 847 NULL
848};
849
a8a4f046 850static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
56a709cf 851{
a8a4f046
NC		 852 const struct attribute * const *attrs;
853 struct attribute *vlv_attr;
56a709cf
AS		 854 int ret;
855
856 if (GRAPHICS_VER(gt->i915) < 6)
857 return 0;
858
a8a4f046
NC		 859 if (is_object_gt(kobj)) {
860 attrs = gen6_rps_attrs;
861 vlv_attr = &attr_rps_vlv_rpe_freq_mhz.attr;
862 } else {
863 attrs = gen6_gt_attrs;
864 vlv_attr = &dev_attr_gt_vlv_rpe_freq_mhz.attr;
865 }
866
56a709cf
AS		 867 ret = sysfs_create_files(kobj, attrs);
868 if (ret)
869 return ret;
870
871 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
a8a4f046 872 ret = sysfs_create_file(kobj, vlv_attr);
56a709cf 873
d84990a6
TU		 874 if (is_object_gt(kobj) && !intel_uc_uses_guc_slpc(&gt->uc)) {
875 ret = sysfs_create_files(kobj, gen6_gt_rps_attrs);
876 if (ret)
877 return ret;
878 }
879
56a709cf
AS		 880 return ret;
881}
882
80cf8af1
AS		 883void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
884{
56a709cf
AS		 885 int ret;
886
80cf8af1 887 intel_sysfs_rc6_init(gt, kobj);
56a709cf 888
a8a4f046 889 ret = intel_sysfs_rps_init(gt, kobj);
56a709cf 890 if (ret)
67804e48 891 gt_warn(gt, "failed to create RPS sysfs files (%pe)", ERR_PTR(ret));
fa68bff7
SS		 892
893 /* end of the legacy interfaces */
894 if (!is_object_gt(kobj))
895 return;
896
a8a4f046 897 ret = sysfs_create_file(kobj, &attr_punit_req_freq_mhz.attr);
fa68bff7 898 if (ret)
67804e48 899 gt_warn(gt, "failed to create punit_req_freq_mhz sysfs (%pe)", ERR_PTR(ret));
26be7cd8 900
55f9720d
VB		 901 if (intel_uc_uses_guc_slpc(&gt->uc)) {
902 ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
903 if (ret)
904 gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret));
905 }
906
4a82ceb0
VB		 907 if (intel_uc_uses_guc_slpc(&gt->uc)) {
908 ret = sysfs_create_file(kobj, &attr_slpc_power_profile.attr);
909 if (ret)
910 gt_warn(gt, "failed to create slpc_power_profile sysfs (%pe)",
911 ERR_PTR(ret));
912 }
913
0d2d2010
AD		 914 if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
915 ret = sysfs_create_files(kobj, throttle_reason_attrs);
916 if (ret)
67804e48 917 gt_warn(gt, "failed to create throttle sysfs files (%pe)", ERR_PTR(ret));
0d2d2010
AD		 918 }
919
26be7cd8
AD		 920 if (HAS_MEDIA_RATIO_MODE(gt->i915) && intel_uc_uses_guc_slpc(&gt->uc)) {
921 ret = sysfs_create_files(kobj, media_perf_power_attrs);
922 if (ret)
67804e48
JH		 923 gt_warn(gt, "failed to create media_perf_power_attrs sysfs (%pe)\n",
924 ERR_PTR(ret));
26be7cd8 925 }
fdff0a85
AD		 926
927 ret = sysfs_create_files(gt->sysfs_defaults, rps_defaults_attrs);
928 if (ret)
67804e48 929 gt_warn(gt, "failed to add rps defaults (%pe)\n", ERR_PTR(ret));
80cf8af1 930}
Linux 6.x block layer and io_uring tree(s)