projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| e7858254 MR |
1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* | |
| 3 | * Copyright © 2022 Intel Corporation | |
| 4 | */ | |
| 5 | ||
| 6 | #ifndef __INTEL_GT_MCR__ | |
| 7 | #define __INTEL_GT_MCR__ | |
| 8 | ||
| 9 | #include "intel_gt_types.h" | |
| 10 | ||
| 11 | void intel_gt_mcr_init(struct intel_gt *gt); | |
| 12 | ||
| 3fe6c7f5 MR |
13 | u32 intel_gt_mcr_read(struct intel_gt *gt, |
| 14 | i915_reg_t reg, | |
| 15 | int group, int instance); | |
| 16 | u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg); | |
| 17 | u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg); | |
| 18 | ||
| 19 | void intel_gt_mcr_unicast_write(struct intel_gt *gt, | |
| 20 | i915_reg_t reg, u32 value, | |
| 21 | int group, int instance); | |
| 22 | void intel_gt_mcr_multicast_write(struct intel_gt *gt, | |
| 23 | i915_reg_t reg, u32 value); | |
| 24 | void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, | |
| 25 | i915_reg_t reg, u32 value); | |
| 26 | ||
| 851435ec MR |
27 | u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_reg_t reg, |
| 28 | u32 clear, u32 set); | |
| 29 | ||
| 3fe6c7f5 MR |
30 | void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, |
| 31 | i915_reg_t reg, | |
| 32 | u8 *group, u8 *instance); | |
| 33 | ||
| 34 | void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, | |
| 35 | bool dump_table); | |
| e7858254 | 36 | |
| 9a92732f MR |
37 | void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, |
| 38 | unsigned int *group, unsigned int *instance); | |
| 39 | ||
| 40 | /* | |
| 41 | * Helper for for_each_ss_steering loop. On pre-Xe_HP platforms, subslice | |
| 42 | * presence is determined by using the group/instance as direct lookups in the | |
| 43 | * slice/subslice topology. On Xe_HP and beyond, the steering is unrelated to | |
| 44 | * the topology, so we lookup the DSS ID directly in "slice 0." | |
| 45 | */ | |
| 46 | #define _HAS_SS(ss_, gt_, group_, instance_) ( \ | |
| 47 | GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \ | |
| 48 | intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \ | |
| 49 | intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_)) | |
| 50 | ||
| 51 | /* | |
| 52 | * Loop over each subslice/DSS and determine the group and instance IDs that | |
| 53 | * should be used to steer MCR accesses toward this DSS. | |
| 54 | */ | |
| 55 | #define for_each_ss_steering(ss_, gt_, group_, instance_) \ | |
| 56 | for (ss_ = 0, intel_gt_mcr_get_ss_steering(gt_, 0, &group_, &instance_); \ | |
| 57 | ss_ < I915_MAX_SS_FUSE_BITS; \ | |
| 58 | ss_++, intel_gt_mcr_get_ss_steering(gt_, ss_, &group_, &instance_)) \ | |
| 59 | for_each_if(_HAS_SS(ss_, gt_, group_, instance_)) | |
| 60 | ||
| e7858254 | 61 | #endif /* __INTEL_GT_MCR__ */ |