[linux-block.git] / drivers / gpu / drm / i915 / gt / intel_gt.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2019 Intel Corporation
 */

#ifndef __INTEL_GT__
#define __INTEL_GT__

#include "intel_engine_types.h"
#include "intel_gt_types.h"
#include "intel_reset.h"

struct drm_i915_private;
struct drm_printer;

/*
 * Check that the GT is a graphics GT and has an IP version within the
 * specified range (inclusive).
 */
#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \
	BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
	BUILD_BUG_ON_ZERO((until) < (from)) + \
	((gt)->type != GT_MEDIA && \
	 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
	 GRAPHICS_VER_FULL((gt)->i915) <= (until)))

/*
 * Check that the GT is a media GT and has an IP version within the
 * specified range (inclusive).
 *
 * Only usable on platforms with a standalone media design (i.e., IP version 13
 * and higher).
 */
#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
	BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
	BUILD_BUG_ON_ZERO((until) < (from)) + \
	((gt) && (gt)->type == GT_MEDIA && \
	 MEDIA_VER_FULL((gt)->i915) >= (from) && \
	 MEDIA_VER_FULL((gt)->i915) <= (until)))

/*
 * Check that the GT is a graphics GT with a specific IP version and has
 * a stepping in the range [from, until).  The lower stepping bound is
 * inclusive, the upper bound is exclusive.  The most common use-case of this
 * macro is for checking bounds for workarounds, which usually have a stepping
 * ("from") at which the hardware issue is first present and another stepping
 * ("until") at which a hardware fix is present and the software workaround is
 * no longer necessary.  E.g.,
 *
 *    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)
 *    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER)
 *
 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
 * stepping bound for the specified IP version.
 */
#define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \
	BUILD_BUG_ON_ZERO((until) <= (from)) + \
	(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
	 IS_GRAPHICS_STEP((gt)->i915, (from), (until))))

/*
 * Check that the GT is a media GT with a specific IP version and has
 * a stepping in the range [from, until).  The lower stepping bound is
 * inclusive, the upper bound is exclusive.  The most common use-case of this
 * macro is for checking bounds for workarounds, which usually have a stepping
 * ("from") at which the hardware issue is first present and another stepping
 * ("until") at which a hardware fix is present and the software workaround is
 * no longer necessary.  "STEP_FOREVER" can be passed as "until" for
 * workarounds that have no upper stepping bound for the specified IP version.
 *
 * This macro may only be used to match on platforms that have a standalone
 * media design (i.e., media version 13 or higher).
 */
#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
	BUILD_BUG_ON_ZERO((until) <= (from)) + \
	(IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
	 IS_MEDIA_STEP((gt)->i915, (from), (until))))

#define GT_TRACE(gt, fmt, ...) do {					\
	const struct intel_gt *gt__ __maybe_unused = (gt);		\
	GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),		\
		  ##__VA_ARGS__);					\
} while (0)

static inline bool gt_is_root(struct intel_gt *gt)
{
	return !gt->info.id;
}

bool intel_gt_needs_wa_16018031267(struct intel_gt *gt);
bool intel_gt_needs_wa_22016122933(struct intel_gt *gt);

#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
	intel_gt_needs_wa_16018031267(engine->gt) && \
	engine->class == COPY_ENGINE_CLASS && engine->instance == 0)

static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
{
	return container_of(uc, struct intel_gt, uc);
}

static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
{
	return container_of(guc, struct intel_gt, uc.guc);
}

static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
{
	return container_of(huc, struct intel_gt, uc.huc);
}

static inline struct intel_gt *gsc_uc_to_gt(struct intel_gsc_uc *gsc_uc)
{
	return container_of(gsc_uc, struct intel_gt, uc.gsc);
}

static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
{
	return container_of(gsc, struct intel_gt, gsc);
}

static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return guc_to_gt(guc)->i915;
}

void intel_gt_common_init_early(struct intel_gt *gt);
int intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
int intel_gt_init(struct intel_gt *gt);
void intel_gt_driver_register(struct intel_gt *gt);

void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);

int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);

void intel_gt_check_and_clear_faults(struct intel_gt *gt);
i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
void intel_gt_clear_error_registers(struct intel_gt *gt,
				    intel_engine_mask_t engine_mask);

void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
void intel_gt_chipset_flush(struct intel_gt *gt);

static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
					  enum intel_gt_scratch_field field)
{
	return i915_ggtt_offset(gt->scratch) + field;
}

static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt)
{
	return test_bit(I915_WEDGED_ON_INIT, &gt->reset.flags) ||
	       test_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
}

static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
{
	GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) &&
		   !test_bit(I915_WEDGED, &gt->reset.flags));

	return unlikely(test_bit(I915_WEDGED, &gt->reset.flags));
}

int intel_gt_probe_all(struct drm_i915_private *i915);
int intel_gt_tiles_init(struct drm_i915_private *i915);
void intel_gt_release_all(struct drm_i915_private *i915);

#define for_each_gt(gt__, i915__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_MAX_GT; \
	     (id__)++) \
		for_each_if(((gt__) = (i915__)->gt[(id__)]))

/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, gt__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (gt__)->engine[(id__)])

/* Iterator over subset of engines selected by mask */
#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
	for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
	     (tmp__) ? \
	     ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
	     0;)

void intel_gt_info_print(const struct intel_gt_info *info,
			 struct drm_printer *p);

void intel_gt_watchdog_work(struct work_struct *work);

enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
					      struct drm_i915_gem_object *obj,
					      bool always_coherent);

void intel_gt_bind_context_set_ready(struct intel_gt *gt);
void intel_gt_bind_context_set_unready(struct intel_gt *gt);
bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
#endif /* __INTEL_GT_H__ */
Commit	Line	Data
24635c51 TU	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_GT__
	7	#define __INTEL_GT__
	8
eaf522f6	9	#include "intel_engine_types.h"
24635c51	10	#include "intel_gt_types.h"
cb823ed9	11	#include "intel_reset.h"
24635c51	12
724e9564	13	struct drm_i915_private;
792592e7	14	struct drm_printer;
724e9564	15
f7696ded MR	16	/*
	17	* Check that the GT is a graphics GT and has an IP version within the
	18	* specified range (inclusive).
	19	*/
	20	#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \
	21	BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
	22	BUILD_BUG_ON_ZERO((until) < (from)) + \
	23	((gt)->type != GT_MEDIA && \
	24	GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
	25	GRAPHICS_VER_FULL((gt)->i915) <= (until)))
	26
81af8abe MR	27	/*
	28	* Check that the GT is a media GT and has an IP version within the
	29	* specified range (inclusive).
	30	*
	31	* Only usable on platforms with a standalone media design (i.e., IP version 13
	32	* and higher).
	33	*/
	34	#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
	35	BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
	36	BUILD_BUG_ON_ZERO((until) < (from)) + \
	37	((gt) && (gt)->type == GT_MEDIA && \
	38	MEDIA_VER_FULL((gt)->i915) >= (from) && \
	39	MEDIA_VER_FULL((gt)->i915) <= (until)))
	40
5a213086 MR	41	/*
	42	* Check that the GT is a graphics GT with a specific IP version and has
	43	* a stepping in the range [from, until). The lower stepping bound is
	44	* inclusive, the upper bound is exclusive. The most common use-case of this
	45	* macro is for checking bounds for workarounds, which usually have a stepping
	46	* ("from") at which the hardware issue is first present and another stepping
	47	* ("until") at which a hardware fix is present and the software workaround is
	48	* no longer necessary. E.g.,
	49	*
	50	* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)
	51	* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER)
	52	*
	53	* "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
	54	* stepping bound for the specified IP version.
	55	*/
	56	#define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \
	57	BUILD_BUG_ON_ZERO((until) <= (from)) + \
	58	(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
	59	IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
	60
81af8abe MR	61	/*
	62	* Check that the GT is a media GT with a specific IP version and has
	63	* a stepping in the range [from, until). The lower stepping bound is
	64	* inclusive, the upper bound is exclusive. The most common use-case of this
	65	* macro is for checking bounds for workarounds, which usually have a stepping
	66	* ("from") at which the hardware issue is first present and another stepping
	67	* ("until") at which a hardware fix is present and the software workaround is
	68	* no longer necessary. "STEP_FOREVER" can be passed as "until" for
	69	* workarounds that have no upper stepping bound for the specified IP version.
	70	*
	71	* This macro may only be used to match on platforms that have a standalone
	72	* media design (i.e., media version 13 or higher).
	73	*/
	74	#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
	75	BUILD_BUG_ON_ZERO((until) <= (from)) + \
	76	(IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
	77	IS_MEDIA_STEP((gt)->i915, (from), (until))))
	78
88405440 VSD	79	#define GT_TRACE(gt, fmt, ...) do { \
88405440 VSD	80	const struct intel_gt *gt__ __maybe_unused = (gt); \
9c92aa48	81	GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
639f2f24 VSD	82	##__VA_ARGS__); \
	83	} while (0)
	84
b9741faa AS	85	static inline bool gt_is_root(struct intel_gt *gt)
	86	{
	87	return !gt->info.id;
	88	}
	89
94bf3e60	90	bool intel_gt_needs_wa_16018031267(struct intel_gt *gt);
82b1e8f7	91	bool intel_gt_needs_wa_22016122933(struct intel_gt *gt);
f1530f91	92
94bf3e60 AS	93	#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
	94	intel_gt_needs_wa_16018031267(engine->gt) && \
	95	engine->class == COPY_ENGINE_CLASS && engine->instance == 0)
	96
ca7b2c1b DCS	97	static inline struct intel_gt uc_to_gt(struct intel_uc uc)
	98	{
	99	return container_of(uc, struct intel_gt, uc);
	100	}
	101
84b1ca2f DCS	102	static inline struct intel_gt guc_to_gt(struct intel_guc guc)
	103	{
	104	return container_of(guc, struct intel_gt, uc.guc);
	105	}
	106
	107	static inline struct intel_gt huc_to_gt(struct intel_huc huc)
	108	{
	109	return container_of(huc, struct intel_gt, uc.huc);
	110	}
	111
242c4b91 DCS	112	static inline struct intel_gt gsc_uc_to_gt(struct intel_gsc_uc gsc_uc)
	113	{
	114	return container_of(gsc_uc, struct intel_gt, uc.gsc);
	115	}
	116
1e3dc1d8 TW	117	static inline struct intel_gt gsc_to_gt(struct intel_gsc gsc)
	118	{
	119	return container_of(gsc, struct intel_gt, gsc);
	120	}
	121
be5bcc4b AS	122	static inline struct drm_i915_private guc_to_i915(struct intel_guc guc)
	123	{
	124	return guc_to_gt(guc)->i915;
	125	}
	126
4ecd56fd	127	void intel_gt_common_init_early(struct intel_gt *gt);
03d2c54d	128	int intel_root_gt_init_early(struct drm_i915_private *i915);
cdeea858	129	int intel_gt_assign_ggtt(struct intel_gt *gt);
d0eb6866	130	int intel_gt_init_mmio(struct intel_gt *gt);
61fa60ff	131	int __must_check intel_gt_init_hw(struct intel_gt *gt);
42014f69 AS	132	int intel_gt_init(struct intel_gt *gt);
	133	void intel_gt_driver_register(struct intel_gt *gt);
	134
	135	void intel_gt_driver_unregister(struct intel_gt *gt);
	136	void intel_gt_driver_remove(struct intel_gt *gt);
	137	void intel_gt_driver_release(struct intel_gt *gt);
bec68cc9	138	void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
cb823ed9	139
b97060a9 MB	140	int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
b97060a9 MB	141
eaf522f6	142	void intel_gt_check_and_clear_faults(struct intel_gt *gt);
1551b916	143	i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
eaf522f6 TU	144	void intel_gt_clear_error_registers(struct intel_gt *gt,
	145	intel_engine_mask_t engine_mask);
	146
a1c8a09e	147	void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
baea429d	148	void intel_gt_chipset_flush(struct intel_gt *gt);
a1c8a09e	149
46c5847e LL	150	static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
46c5847e LL	151	enum intel_gt_scratch_field field)
db56f974	152	{
46c5847e	153	return i915_ggtt_offset(gt->scratch) + field;
db56f974 TU	154	}
db56f974 TU	155
3f04bdce	156	static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt)
cb823ed9	157	{
3f04bdce MW	158	return test_bit(I915_WEDGED_ON_INIT, &gt->reset.flags) \|\|
3f04bdce MW	159	test_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
cb823ed9 CW	160	}
cb823ed9 CW	161
3f04bdce	162	static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
b761a7b4	163	{
3f04bdce MW	164	GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) &&
	165	!test_bit(I915_WEDGED, &gt->reset.flags));
	166
	167	return unlikely(test_bit(I915_WEDGED, &gt->reset.flags));
b761a7b4 CW	168	}
b761a7b4 CW	169
bec68cc9 TU	170	int intel_gt_probe_all(struct drm_i915_private *i915);
	171	int intel_gt_tiles_init(struct drm_i915_private *i915);
	172	void intel_gt_release_all(struct drm_i915_private *i915);
	173
	174	#define for_each_gt(gt__, i915__, id__) \
	175	for ((id__) = 0; \
	176	(id__) < I915_MAX_GT; \
	177	(id__)++) \
	178	for_each_if(((gt__) = (i915__)->gt[(id__)]))
	179
22d54ab6 TU	180	/* Simple iterator over all initialised engines */
	181	#define for_each_engine(engine__, gt__, id__) \
	182	for ((id__) = 0; \
	183	(id__) < I915_NUM_ENGINES; \
	184	(id__)++) \
	185	for_each_if ((engine__) = (gt__)->engine[(id__)])
	186
	187	/* Iterator over subset of engines selected by mask */
	188	#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
	189	for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
	190	(tmp__) ? \
	191	((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
	192	0;)
	193
792592e7 DCS	194	void intel_gt_info_print(const struct intel_gt_info *info,
	195	struct drm_printer *p);
	196
9b4d0598 TU	197	void intel_gt_watchdog_work(struct work_struct *work);
9b4d0598 TU	198
115cdcca JC	199	enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
	200	struct drm_i915_gem_object *obj,
	201	bool always_coherent);
	202
b3527499 ND	203	void intel_gt_bind_context_set_ready(struct intel_gt *gt);
	204	void intel_gt_bind_context_set_unready(struct intel_gt *gt);
	205	bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
24635c51	206	#endif /* __INTEL_GT_H__ */