[linux-2.6-block.git] / drivers / gpu / drm / i915 / gt / intel_gpu_commands.h

/* SPDX-License-Identifier: MIT*/
/*
 * Copyright © 2003-2018 Intel Corporation
 */

#ifndef _INTEL_GPU_COMMANDS_H_
#define _INTEL_GPU_COMMANDS_H_

#include <linux/bitops.h>

/*
 * Target address alignments required for GPU access e.g.
 * MI_STORE_DWORD_IMM.
 */
#define alignof_dword 4
#define alignof_qword 8

/*
 * Instruction field definitions used by the command parser
 */
#define INSTR_CLIENT_SHIFT      29
#define   INSTR_MI_CLIENT       0x0
#define   INSTR_BC_CLIENT       0x2
#define   INSTR_RC_CLIENT       0x3
#define INSTR_SUBCLIENT_SHIFT   27
#define INSTR_SUBCLIENT_MASK    0x18000000
#define   INSTR_MEDIA_SUBCLIENT 0x2
#define INSTR_26_TO_24_MASK	0x7000000
#define   INSTR_26_TO_24_SHIFT	24

#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)

/*
 * Memory interface instructions used by the kernel
 */
#define MI_INSTR(opcode, flags) \
	(__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
#define  MI_GLOBAL_GTT    (1<<22)

#define MI_NOOP			MI_INSTR(0, 0)
#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
#define   MI_WAIT_FOR_OVERLAY_FLIP	(1<<16)
#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
#define MI_FLUSH		MI_INSTR(0x04, 0)
#define   MI_READ_FLUSH		(1 << 0)
#define   MI_EXE_FLUSH		(1 << 1)
#define   MI_NO_WRITE_FLUSH	(1 << 2)
#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
#define   MI_INVALIDATE_ISP	(1 << 5) /* invalidate indirect state pointers */
#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
#define MI_ARB_ON_OFF		MI_INSTR(0x08, 0)
#define   MI_ARB_ENABLE			(1<<0)
#define   MI_ARB_DISABLE		(0<<0)
#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
#define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
#define   MI_SUSPEND_FLUSH_EN	(1<<0)
#define MI_SET_APPID		MI_INSTR(0x0e, 0)
#define   MI_SET_APPID_SESSION_ID(x)	((x) << 0)
#define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
#define   MI_OVERLAY_CONTINUE	(0x0<<21)
#define   MI_OVERLAY_ON		(0x1<<21)
#define   MI_OVERLAY_OFF	(0x2<<21)
#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
#define MI_DISPLAY_FLIP		MI_INSTR(0x14, 2)
#define MI_DISPLAY_FLIP_I915	MI_INSTR(0x14, 1)
#define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
/* IVB has funny definitions for which plane to flip. */
#define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
#define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
#define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
#define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
#define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
#define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
/* SKL ones */
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_A	(0 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_B	(1 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_1_C	(2 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_A	(4 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_B	(5 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_2_C	(6 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_A	(7 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_B	(8 << 8)
#define   MI_DISPLAY_FLIP_SKL_PLANE_3_C	(9 << 8)
#define MI_SEMAPHORE_MBOX	MI_INSTR(0x16, 1) /* gen6, gen7 */
#define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
#define   MI_SEMAPHORE_UPDATE	    (1<<21)
#define   MI_SEMAPHORE_COMPARE	    (1<<20)
#define   MI_SEMAPHORE_REGISTER	    (1<<18)
#define   MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS  wait for VCS  (RVSYNC) */
#define   MI_SEMAPHORE_SYNC_VER	    (1<<16) /* RCS  wait for VECS (RVESYNC) */
#define   MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS  wait for BCS  (RBSYNC) */
#define   MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS  wait for BCS  (VBSYNC) */
#define   MI_SEMAPHORE_SYNC_VEV	    (1<<16) /* VCS  wait for VECS (VVESYNC) */
#define   MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS  wait for RCS  (VRSYNC) */
#define   MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS  wait for RCS  (BRSYNC) */
#define   MI_SEMAPHORE_SYNC_VEB	    (1<<16) /* BCS  wait for VECS (BVESYNC) */
#define   MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS  wait for VCS  (BVSYNC) */
#define   MI_SEMAPHORE_SYNC_BVE	    (0<<16) /* VECS wait for BCS  (VEBSYNC) */
#define   MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */
#define   MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */
#define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
#define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
#define MI_SET_CONTEXT		MI_INSTR(0x18, 0)
#define   MI_MM_SPACE_GTT		(1<<8)
#define   MI_MM_SPACE_PHYSICAL		(0<<8)
#define   MI_SAVE_EXT_STATE_EN		(1<<3)
#define   MI_RESTORE_EXT_STATE_EN	(1<<2)
#define   MI_FORCE_RESTORE		(1<<1)
#define   MI_RESTORE_INHIBIT		(1<<0)
#define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
#define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
#define MI_SEMAPHORE_SIGNAL	MI_INSTR(0x1b, 0) /* GEN8+ */
#define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
#define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
#define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
#define   MI_SEMAPHORE_POLL		(1 << 15)
#define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
#define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)
#define   MI_SEMAPHORE_SAD_LT_SDD	(2 << 12)
#define   MI_SEMAPHORE_SAD_LTE_SDD	(3 << 12)
#define   MI_SEMAPHORE_SAD_EQ_SDD	(4 << 12)
#define   MI_SEMAPHORE_SAD_NEQ_SDD	(5 << 12)
#define   MI_SEMAPHORE_TOKEN_MASK	REG_GENMASK(9, 5)
#define   MI_SEMAPHORE_TOKEN_SHIFT	5
#define MI_STORE_DATA_IMM	MI_INSTR(0x20, 0)
#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
#define MI_STORE_DWORD_IMM_GEN4	MI_INSTR(0x20, 2)
#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
#define   MI_MEM_VIRTUAL	(1 << 22) /* 945,g33,965 */
#define   MI_USE_GGTT		(1 << 22) /* g4x+ */
#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
/*
 * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
 *   simply ignores the register load under certain conditions.
 * - One can actually load arbitrary many arbitrary registers: Simply issue x
 *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
 */
#define MI_LOAD_REGISTER_IMM(x)	MI_INSTR(0x22, 2*(x)-1)
/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
#define   MI_LRI_LRM_CS_MMIO		REG_BIT(19)
#define   MI_LRI_MMIO_REMAP_EN		REG_BIT(17)
#define   MI_LRI_FORCE_POSTED		(1<<12)
#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
#define   MI_SRM_LRM_GLOBAL_GTT		(1<<22)
#define MI_FLUSH_DW		MI_INSTR(0x26, 1) /* for GEN6 */
#define   MI_FLUSH_DW_PROTECTED_MEM_EN	(1 << 22)
#define   MI_FLUSH_DW_STORE_INDEX	(1<<21)
#define   MI_INVALIDATE_TLB		(1<<18)
#define   MI_FLUSH_DW_OP_STOREDW	(1<<14)
#define   MI_FLUSH_DW_OP_MASK		(3<<14)
#define   MI_FLUSH_DW_NOTIFY		(1<<8)
#define   MI_INVALIDATE_BSD		(1<<7)
#define   MI_FLUSH_DW_USE_GTT		(1<<2)
#define   MI_FLUSH_DW_USE_PPGTT		(0<<2)
#define MI_LOAD_REGISTER_MEM	   MI_INSTR(0x29, 1)
#define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
#define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 1)
#define   MI_LRR_SOURCE_CS_MMIO		REG_BIT(18)
#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
#define   MI_BATCH_NON_SECURE		(1)
/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
#define   MI_BATCH_NON_SECURE_I965	(1<<8)
#define   MI_BATCH_PPGTT_HSW		(1<<8)
#define   MI_BATCH_NON_SECURE_HSW	(1<<13)
#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
#define   MI_BATCH_GTT		    (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8	MI_INSTR(0x31, 1)
#define   MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
#define   MI_BATCH_PREDICATE         REG_BIT(15) /* HSW+ on RCS only*/

/*
 * 3D instructions used by the kernel
 */
#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))

#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define   SC_UPDATE_SCISSOR       (0x1<<1)
#define   SC_ENABLE_MASK          (0x1<<0)
#define   SC_ENABLE               (0x1<<0)
#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
#define   SCI_YMIN_MASK      (0xffff<<16)
#define   SCI_XMIN_MASK      (0xffff<<0)
#define   SCI_YMAX_MASK      (0xffff<<16)
#define   SCI_XMAX_MASK      (0xffff<<0)
#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)

#define COLOR_BLT_CMD			(2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD		(2 << 29 | 0x50 << 22)
#define SRC_COPY_BLT_CMD		(2 << 29 | 0x43 << 22)
#define GEN9_XY_FAST_COPY_BLT_CMD	(2 << 29 | 0x42 << 22)
#define XY_SRC_COPY_BLT_CMD		(2 << 29 | 0x53 << 22)
#define XY_MONO_SRC_COPY_IMM_BLT	(2 << 29 | 0x71 << 22 | 5)
#define   BLT_WRITE_A			(2<<20)
#define   BLT_WRITE_RGB			(1<<20)
#define   BLT_WRITE_RGBA		(BLT_WRITE_RGB | BLT_WRITE_A)
#define   BLT_DEPTH_8			(0<<24)
#define   BLT_DEPTH_16_565		(1<<24)
#define   BLT_DEPTH_16_1555		(2<<24)
#define   BLT_DEPTH_32			(3<<24)
#define   BLT_ROP_SRC_COPY		(0xcc<<16)
#define   BLT_ROP_COLOR_COPY		(0xf0<<16)
#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
#define   ASYNC_FLIP                (1<<22)
#define   DISPLAY_PLANE_A           (0<<20)
#define   DISPLAY_PLANE_B           (1<<20)
#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
#define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29) /* gen11+ */
#define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28) /* gen11+ */
#define   PIPE_CONTROL_FLUSH_L3				(1<<27)
#define   PIPE_CONTROL_AMFS_FLUSH			(1<<25) /* gen12+ */
#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
#define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
#define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
#define   PIPE_CONTROL_CS_STALL				(1<<20)
#define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET		(1<<19)
#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
#define   PIPE_CONTROL_PSD_SYNC				(1<<17) /* gen11+ */
#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
#define   PIPE_CONTROL_WRITE_TIMESTAMP			(3<<14)
#define   PIPE_CONTROL_QW_WRITE				(1<<14)
#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */
#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
#define   PIPE_CONTROL0_HDC_PIPELINE_FLUSH		REG_BIT(9)  /* gen12 */
#define   PIPE_CONTROL_NOTIFY				(1<<8)
#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
#define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
#define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
#define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */

/* 3D-related flags can't be set on compute engine */
#define PIPE_CONTROL_3D_FLAGS (\
		PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
		PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
		PIPE_CONTROL_TILE_CACHE_FLUSH | \
		PIPE_CONTROL_DEPTH_STALL | \
		PIPE_CONTROL_STALL_AT_SCOREBOARD | \
		PIPE_CONTROL_PSD_SYNC | \
		PIPE_CONTROL_AMFS_FLUSH | \
		PIPE_CONTROL_VF_CACHE_INVALIDATE | \
		PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)

#define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)
#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
/* Opcodes for MI_MATH_INSTR */
#define   MI_MATH_NOOP			MI_MATH_INSTR(0x000, 0x0, 0x0)
#define   MI_MATH_LOAD(op1, op2)	MI_MATH_INSTR(0x080, op1, op2)
#define   MI_MATH_LOADINV(op1, op2)	MI_MATH_INSTR(0x480, op1, op2)
#define   MI_MATH_LOAD0(op1)		MI_MATH_INSTR(0x081, op1)
#define   MI_MATH_LOAD1(op1)		MI_MATH_INSTR(0x481, op1)
#define   MI_MATH_ADD			MI_MATH_INSTR(0x100, 0x0, 0x0)
#define   MI_MATH_SUB			MI_MATH_INSTR(0x101, 0x0, 0x0)
#define   MI_MATH_AND			MI_MATH_INSTR(0x102, 0x0, 0x0)
#define   MI_MATH_OR			MI_MATH_INSTR(0x103, 0x0, 0x0)
#define   MI_MATH_XOR			MI_MATH_INSTR(0x104, 0x0, 0x0)
#define   MI_MATH_STORE(op1, op2)	MI_MATH_INSTR(0x180, op1, op2)
#define   MI_MATH_STOREINV(op1, op2)	MI_MATH_INSTR(0x580, op1, op2)
/* Registers used as operands in MI_MATH_INSTR */
#define   MI_MATH_REG(x)		(x)
#define   MI_MATH_REG_SRCA		0x20
#define   MI_MATH_REG_SRCB		0x21
#define   MI_MATH_REG_ACCU		0x31
#define   MI_MATH_REG_ZF		0x32
#define   MI_MATH_REG_CF		0x33

/*
 * Media instructions used by the kernel
 */
#define MEDIA_INSTR(pipe, op, sub_op, flags) \
	(__INSTR(INSTR_RC_CLIENT) | (pipe) << INSTR_SUBCLIENT_SHIFT | \
	(op) << INSTR_26_TO_24_SHIFT | (sub_op) << 16 | (flags))

#define MFX_WAIT				MEDIA_INSTR(1, 0, 0, 0)
#define  MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG	REG_BIT(8)
#define  MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG	REG_BIT(9)

#define CRYPTO_KEY_EXCHANGE			MEDIA_INSTR(2, 6, 9, 0)

/*
 * Commands used only by the command parser
 */
#define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
#define MI_ARB_CHECK            MI_INSTR(0x05, 0)
#define MI_RS_CONTROL           MI_INSTR(0x06, 0)
#define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
#define MI_PREDICATE            MI_INSTR(0x0C, 0)
#define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
#define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
#define MI_URB_CLEAR            MI_INSTR(0x19, 0)
#define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
#define MI_CLFLUSH              MI_INSTR(0x27, 0)
#define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
#define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
#define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
#define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
#define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)

#define STATE_BASE_ADDRESS \
	((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 16))
#define BASE_ADDRESS_MODIFY		REG_BIT(0)
#define PIPELINE_SELECT \
	((0x3 << 29) | (0x1 << 27) | (0x1 << 24) | (0x4 << 16))
#define PIPELINE_SELECT_MEDIA	       REG_BIT(0)
#define GFX_OP_3DSTATE_VF_STATISTICS \
	((0x3 << 29) | (0x1 << 27) | (0x0 << 24) | (0xB << 16))
#define MEDIA_VFE_STATE \
	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x0 << 16))
#define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD \
	((0x3 << 29) | (0x2 << 27) | (0x0 << 24) | (0x2 << 16))
#define MEDIA_OBJECT \
	((0x3 << 29) | (0x2 << 27) | (0x1 << 24) | (0x0 << 16))
#define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
#define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
#define GFX_OP_3DSTATE_SO_DECL_LIST \
	((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))

#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
	((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))

#define COLOR_BLT     ((0x2<<29)|(0x40<<22))
#define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))

/*
 * Used to convert any address to canonical form.
 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
 * addresses to be in a canonical form:
 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
 * canonical form [63:48] == [47]."
 */
#define GEN8_HIGH_ADDRESS_BIT 47
static inline u64 gen8_canonical_addr(u64 address)
{
	return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
}

static inline u64 gen8_noncanonical_addr(u64 address)
{
	return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
}

static inline u32 *__gen6_emit_bb_start(u32 *cs, u32 addr, unsigned int flags)
{
	*cs++ = MI_BATCH_BUFFER_START | flags;
	*cs++ = addr;

	return cs;
}

#endif /* _INTEL_GPU_COMMANDS_H_ */
Commit	Line	Data
24f90d66	1	/* SPDX-License-Identifier: MIT*/
c080363f	2	/*
e52e4a31	3	* Copyright © 2003-2018 Intel Corporation
c080363f MW	4	*/
	5
	6	#ifndef _INTEL_GPU_COMMANDS_H_
	7	#define _INTEL_GPU_COMMANDS_H_
	8
755bf8a8 CW	9	#include <linux/bitops.h>
755bf8a8 CW	10
bf1315b8 CW	11	/*
	12	* Target address alignments required for GPU access e.g.
	13	* MI_STORE_DWORD_IMM.
	14	*/
	15	#define alignof_dword 4
	16	#define alignof_qword 8
	17
c080363f MW	18	/*
	19	* Instruction field definitions used by the command parser
	20	*/
	21	#define INSTR_CLIENT_SHIFT 29
	22	#define INSTR_MI_CLIENT 0x0
	23	#define INSTR_BC_CLIENT 0x2
	24	#define INSTR_RC_CLIENT 0x3
	25	#define INSTR_SUBCLIENT_SHIFT 27
	26	#define INSTR_SUBCLIENT_MASK 0x18000000
	27	#define INSTR_MEDIA_SUBCLIENT 0x2
	28	#define INSTR_26_TO_24_MASK 0x7000000
	29	#define INSTR_26_TO_24_SHIFT 24
	30
95c9e122 HS	31	#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
95c9e122 HS	32
c080363f MW	33	/*
	34	* Memory interface instructions used by the kernel
	35	*/
95c9e122 HS	36	#define MI_INSTR(opcode, flags) \
95c9e122 HS	37	(__INSTR(INSTR_MI_CLIENT) \| (opcode) << 23 \| (flags))
c080363f MW	38	/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
	39	#define MI_GLOBAL_GTT (1<<22)
	40
	41	#define MI_NOOP MI_INSTR(0, 0)
	42	#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
	43	#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
	44	#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
	45	#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
	46	#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
	47	#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
	48	#define MI_FLUSH MI_INSTR(0x04, 0)
	49	#define MI_READ_FLUSH (1 << 0)
	50	#define MI_EXE_FLUSH (1 << 1)
	51	#define MI_NO_WRITE_FLUSH (1 << 2)
	52	#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
	53	#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
	54	#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
	55	#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
	56	#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
	57	#define MI_ARB_ENABLE (1<<0)
	58	#define MI_ARB_DISABLE (0<<0)
	59	#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
	60	#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
	61	#define MI_SUSPEND_FLUSH_EN (1<<0)
	62	#define MI_SET_APPID MI_INSTR(0x0e, 0)
95c9e122	63	#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
c080363f MW	64	#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
	65	#define MI_OVERLAY_CONTINUE (0x0<<21)
	66	#define MI_OVERLAY_ON (0x1<<21)
	67	#define MI_OVERLAY_OFF (0x2<<21)
	68	#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
	69	#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
	70	#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
	71	#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
	72	/* IVB has funny definitions for which plane to flip. */
	73	#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
	74	#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
	75	#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
	76	#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
	77	#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
	78	#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
	79	/* SKL ones */
	80	#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
	81	#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
	82	#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
	83	#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
	84	#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
	85	#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
	86	#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
	87	#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
	88	#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
	89	#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
	90	#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
	91	#define MI_SEMAPHORE_UPDATE (1<<21)
	92	#define MI_SEMAPHORE_COMPARE (1<<20)
	93	#define MI_SEMAPHORE_REGISTER (1<<18)
	94	#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
	95	#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
	96	#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
	97	#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
	98	#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
	99	#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
	100	#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
	101	#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
	102	#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
	103	#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
	104	#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
	105	#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
	106	#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
	107	#define MI_SEMAPHORE_SYNC_MASK (3<<16)
	108	#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
	109	#define MI_MM_SPACE_GTT (1<<8)
	110	#define MI_MM_SPACE_PHYSICAL (0<<8)
	111	#define MI_SAVE_EXT_STATE_EN (1<<3)
	112	#define MI_RESTORE_EXT_STATE_EN (1<<2)
	113	#define MI_FORCE_RESTORE (1<<1)
	114	#define MI_RESTORE_INHIBIT (1<<0)
	115	#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
	116	#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
	117	#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
	118	#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
	119	#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
c210e85b	120	#define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */
e8861964 CW	121	#define MI_SEMAPHORE_POLL (1 << 15)
	122	#define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
	123	#define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)
	124	#define MI_SEMAPHORE_SAD_LT_SDD (2 << 12)
	125	#define MI_SEMAPHORE_SAD_LTE_SDD (3 << 12)
	126	#define MI_SEMAPHORE_SAD_EQ_SDD (4 << 12)
	127	#define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
c210e85b CW	128	#define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
c210e85b CW	129	#define MI_SEMAPHORE_TOKEN_SHIFT 5
cf586021	130	#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
c080363f MW	131	#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
c080363f MW	132	#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
cf586021	133	#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) \| REG_BIT(21))
c080363f MW	134	#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
	135	#define MI_USE_GGTT (1 << 22) /* g4x+ */
	136	#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
c080363f MW	137	/*
	138	* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
	139	* - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
	140	* simply ignores the register load under certain conditions.
	141	* - One can actually load arbitrary many arbitrary registers: Simply issue x
	142	* address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
	143	*/
	144	#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
cdb736fa	145	/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
685d2109	146	#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
d8b93201	147	#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
c080363f	148	#define MI_LRI_FORCE_POSTED (1<<12)
6a45008a	149	#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
c080363f MW	150	#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
	151	#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
	152	#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
	153	#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
95c9e122	154	#define MI_FLUSH_DW_PROTECTED_MEM_EN (1 << 22)
c080363f MW	155	#define MI_FLUSH_DW_STORE_INDEX (1<<21)
	156	#define MI_INVALIDATE_TLB (1<<18)
	157	#define MI_FLUSH_DW_OP_STOREDW (1<<14)
	158	#define MI_FLUSH_DW_OP_MASK (3<<14)
	159	#define MI_FLUSH_DW_NOTIFY (1<<8)
	160	#define MI_INVALIDATE_BSD (1<<7)
	161	#define MI_FLUSH_DW_USE_GTT (1<<2)
	162	#define MI_FLUSH_DW_USE_PPGTT (0<<2)
	163	#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
	164	#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
7d5255e0	165	#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
685d2109	166	#define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)
c080363f MW	167	#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
	168	#define MI_BATCH_NON_SECURE (1)
	169	/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
	170	#define MI_BATCH_NON_SECURE_I965 (1<<8)
	171	#define MI_BATCH_PPGTT_HSW (1<<8)
	172	#define MI_BATCH_NON_SECURE_HSW (1<<13)
	173	#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
	174	#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
	175	#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
daed3e44 LL	176	#define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
daed3e44 LL	177	#define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
c080363f MW	178
	179	/*
	180	* 3D instructions used by the kernel
	181	*/
	182	#define GFX_INSTR(opcode, flags) ((0x3 << 29) \| ((opcode) << 24) \| (flags))
	183
	184	#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) \| (0x2 << 27) \| (0x5 << 16) \| 4)
	185	#define GEN9_MEDIA_POOL_ENABLE (1 << 31)
	186	#define GFX_OP_RASTER_RULES ((0x3<<29)\|(0x7<<24))
	187	#define GFX_OP_SCISSOR ((0x3<<29)\|(0x1c<<24)\|(0x10<<19))
	188	#define SC_UPDATE_SCISSOR (0x1<<1)
	189	#define SC_ENABLE_MASK (0x1<<0)
	190	#define SC_ENABLE (0x1<<0)
	191	#define GFX_OP_LOAD_INDIRECT ((0x3<<29)\|(0x1d<<24)\|(0x7<<16))
	192	#define GFX_OP_SCISSOR_INFO ((0x3<<29)\|(0x1d<<24)\|(0x81<<16)\|(0x1))
	193	#define SCI_YMIN_MASK (0xffff<<16)
	194	#define SCI_XMIN_MASK (0xffff<<0)
	195	#define SCI_YMAX_MASK (0xffff<<16)
	196	#define SCI_XMAX_MASK (0xffff<<0)
	197	#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)\|(0x1c<<24)\|(0x10<<19))
	198	#define GFX_OP_SCISSOR_RECT ((0x3<<29)\|(0x1d<<24)\|(0x81<<16)\|1)
	199	#define GFX_OP_COLOR_FACTOR ((0x3<<29)\|(0x1d<<24)\|(0x1<<16)\|0x0)
	200	#define GFX_OP_STIPPLE ((0x3<<29)\|(0x1d<<24)\|(0x83<<16))
	201	#define GFX_OP_MAP_INFO ((0x3<<29)\|(0x1d<<24)\|0x4)
	202	#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)\|(0x1d<<24)\|(0x85<<16)\|0x0)
	203	#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)\|(0x1d<<24)\|(0x8e<<16)\|1)
	204	#define GFX_OP_DRAWRECT_INFO ((0x3<<29)\|(0x1d<<24)\|(0x80<<16)\|(0x3))
	205	#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)\|0x2)
	206
05f219d7	207	#define COLOR_BLT_CMD (2 << 29 \| 0x40 << 22 \| (5 - 2))
6501aa4e	208	#define XY_COLOR_BLT_CMD (2 << 29 \| 0x50 << 22)
05f219d7 MA	209	#define SRC_COPY_BLT_CMD (2 << 29 \| 0x43 << 22)
	210	#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 \| 0x42 << 22)
	211	#define XY_SRC_COPY_BLT_CMD (2 << 29 \| 0x53 << 22)
	212	#define XY_MONO_SRC_COPY_IMM_BLT (2 << 29 \| 0x71 << 22 \| 5)
c080363f MW	213	#define BLT_WRITE_A (2<<20)
	214	#define BLT_WRITE_RGB (1<<20)
	215	#define BLT_WRITE_RGBA (BLT_WRITE_RGB \| BLT_WRITE_A)
	216	#define BLT_DEPTH_8 (0<<24)
	217	#define BLT_DEPTH_16_565 (1<<24)
	218	#define BLT_DEPTH_16_1555 (2<<24)
	219	#define BLT_DEPTH_32 (3<<24)
	220	#define BLT_ROP_SRC_COPY (0xcc<<16)
	221	#define BLT_ROP_COLOR_COPY (0xf0<<16)
	222	#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
	223	#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
	224	#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)\|(0x14<<23)\|2)
	225	#define ASYNC_FLIP (1<<22)
	226	#define DISPLAY_PLANE_A (0<<20)
	227	#define DISPLAY_PLANE_B (1<<20)
	228	#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)\|(0x3<<27)\|(0x2<<24)\|((len)-2))
8a8b540a	229	#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */
cfba6bd8	230	#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */
c080363f	231	#define PIPE_CONTROL_FLUSH_L3 (1<<27)
803efd29	232	#define PIPE_CONTROL_AMFS_FLUSH (1<<25) /* gen12+ */
c080363f MW	233	#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
	234	#define PIPE_CONTROL_MMIO_WRITE (1<<23)
	235	#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
	236	#define PIPE_CONTROL_CS_STALL (1<<20)
803efd29	237	#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
c080363f	238	#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
803efd29	239	#define PIPE_CONTROL_PSD_SYNC (1<<17) /* gen11+ */
c080363f	240	#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
daed3e44	241	#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
c080363f MW	242	#define PIPE_CONTROL_QW_WRITE (1<<14)
	243	#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
	244	#define PIPE_CONTROL_DEPTH_STALL (1<<13)
	245	#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
	246	#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
	247	#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
	248	#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
	249	#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
32d7171e	250	#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
c080363f MW	251	#define PIPE_CONTROL_NOTIFY (1<<8)
	252	#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
	253	#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
	254	#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
	255	#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
	256	#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
	257	#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
	258	#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
	259	#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
	260
803efd29 DCS	261	/* 3D-related flags can't be set on compute engine */
	262	#define PIPE_CONTROL_3D_FLAGS (\
	263	PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH \| \
	264	PIPE_CONTROL_DEPTH_CACHE_FLUSH \| \
	265	PIPE_CONTROL_TILE_CACHE_FLUSH \| \
	266	PIPE_CONTROL_DEPTH_STALL \| \
	267	PIPE_CONTROL_STALL_AT_SCOREBOARD \| \
	268	PIPE_CONTROL_PSD_SYNC \| \
	269	PIPE_CONTROL_AMFS_FLUSH \| \
	270	PIPE_CONTROL_VF_CACHE_INVALIDATE \| \
	271	PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
	272
74b2089a MW	273	#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
	274	#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 \| (op1) << 10 \| (op2))
	275	/* Opcodes for MI_MATH_INSTR */
	276	#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
	277	#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
	278	#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
	279	#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
	280	#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
	281	#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
	282	#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
	283	#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
	284	#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
	285	#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
	286	#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
	287	#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
	288	/* Registers used as operands in MI_MATH_INSTR */
	289	#define MI_MATH_REG(x) (x)
	290	#define MI_MATH_REG_SRCA 0x20
	291	#define MI_MATH_REG_SRCB 0x21
	292	#define MI_MATH_REG_ACCU 0x31
	293	#define MI_MATH_REG_ZF 0x32
	294	#define MI_MATH_REG_CF 0x33
	295
95c9e122 HS	296	/*
	297	* Media instructions used by the kernel
	298	*/
	299	#define MEDIA_INSTR(pipe, op, sub_op, flags) \
	300	(__INSTR(INSTR_RC_CLIENT) \| (pipe) << INSTR_SUBCLIENT_SHIFT \| \
	301	(op) << INSTR_26_TO_24_SHIFT \| (sub_op) << 16 \| (flags))
	302
	303	#define MFX_WAIT MEDIA_INSTR(1, 0, 0, 0)
	304	#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
	305	#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
	306
	307	#define CRYPTO_KEY_EXCHANGE MEDIA_INSTR(2, 6, 9, 0)
	308
c080363f MW	309	/*
	310	* Commands used only by the command parser
	311	*/
	312	#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
	313	#define MI_ARB_CHECK MI_INSTR(0x05, 0)
	314	#define MI_RS_CONTROL MI_INSTR(0x06, 0)
	315	#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
	316	#define MI_PREDICATE MI_INSTR(0x0C, 0)
	317	#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
	318	#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
	319	#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
	320	#define MI_URB_CLEAR MI_INSTR(0x19, 0)
	321	#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
	322	#define MI_CLFLUSH MI_INSTR(0x27, 0)
	323	#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
	324	#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
c080363f MW	325	#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
	326	#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
	327	#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
	328	#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
	329
47f8253d PKV	330	#define STATE_BASE_ADDRESS \
	331	((0x3 << 29) \| (0x0 << 27) \| (0x1 << 24) \| (0x1 << 16))
	332	#define BASE_ADDRESS_MODIFY REG_BIT(0)
	333	#define PIPELINE_SELECT \
	334	((0x3 << 29) \| (0x1 << 27) \| (0x1 << 24) \| (0x4 << 16))
	335	#define PIPELINE_SELECT_MEDIA REG_BIT(0)
	336	#define GFX_OP_3DSTATE_VF_STATISTICS \
	337	((0x3 << 29) \| (0x1 << 27) \| (0x0 << 24) \| (0xB << 16))
	338	#define MEDIA_VFE_STATE \
	339	((0x3 << 29) \| (0x2 << 27) \| (0x0 << 24) \| (0x0 << 16))
c080363f	340	#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
47f8253d PKV	341	#define MEDIA_INTERFACE_DESCRIPTOR_LOAD \
	342	((0x3 << 29) \| (0x2 << 27) \| (0x0 << 24) \| (0x2 << 16))
	343	#define MEDIA_OBJECT \
	344	((0x3 << 29) \| (0x2 << 27) \| (0x1 << 24) \| (0x0 << 16))
c080363f MW	345	#define GPGPU_OBJECT ((0x3<<29)\|(0x2<<27)\|(0x1<<24)\|(0x4<<16))
	346	#define GPGPU_WALKER ((0x3<<29)\|(0x2<<27)\|(0x1<<24)\|(0x5<<16))
	347	#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
	348	((0x3<<29)\|(0x3<<27)\|(0x0<<24)\|(0x39<<16))
	349	#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
	350	((0x3<<29)\|(0x3<<27)\|(0x0<<24)\|(0x3A<<16))
	351	#define GFX_OP_3DSTATE_SO_DECL_LIST \
	352	((0x3<<29)\|(0x3<<27)\|(0x1<<24)\|(0x17<<16))
	353
	354	#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
	355	((0x3<<29)\|(0x3<<27)\|(0x0<<24)\|(0x43<<16))
	356	#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
	357	((0x3<<29)\|(0x3<<27)\|(0x0<<24)\|(0x44<<16))
	358	#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
	359	((0x3<<29)\|(0x3<<27)\|(0x0<<24)\|(0x45<<16))
	360	#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
	361	((0x3<<29)\|(0x3<<27)\|(0x0<<24)\|(0x46<<16))
	362	#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
	363	((0x3<<29)\|(0x3<<27)\|(0x0<<24)\|(0x47<<16))
	364
c080363f MW	365	#define COLOR_BLT ((0x2<<29)\|(0x40<<22))
	366	#define SRC_COPY_BLT ((0x2<<29)\|(0x43<<22))
	367
755bf8a8 CW	368	/*
	369	* Used to convert any address to canonical form.
	370	* Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
	371	* MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
	372	* addresses to be in a canonical form:
	373	* "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
	374	* canonical form [63:48] == [47]."
	375	*/
	376	#define GEN8_HIGH_ADDRESS_BIT 47
	377	static inline u64 gen8_canonical_addr(u64 address)
	378	{
	379	return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
	380	}
	381
	382	static inline u64 gen8_noncanonical_addr(u64 address)
	383	{
	384	return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
	385	}
	386
32d94048 CW	387	static inline u32 __gen6_emit_bb_start(u32 cs, u32 addr, unsigned int flags)
	388	{
	389	*cs++ = MI_BATCH_BUFFER_START \| flags;
	390	*cs++ = addr;
	391
	392	return cs;
	393	}
	394
c080363f	395	#endif /* _INTEL_GPU_COMMANDS_H_ */