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39e2f501 CW |
1 | /* |
2 | * SPDX-License-Identifier: MIT | |
3 | * | |
4 | * Copyright © 2019 Intel Corporation | |
5 | */ | |
6 | ||
7 | #ifndef __INTEL_CONTEXT_TYPES__ | |
8 | #define __INTEL_CONTEXT_TYPES__ | |
9 | ||
1883a0a4 | 10 | #include <linux/average.h> |
4c5896dc | 11 | #include <linux/kref.h> |
39e2f501 | 12 | #include <linux/list.h> |
08819549 | 13 | #include <linux/mutex.h> |
39e2f501 CW |
14 | #include <linux/types.h> |
15 | ||
16 | #include "i915_active_types.h" | |
22b7a426 | 17 | #include "i915_utils.h" |
ca6e56f6 | 18 | #include "intel_engine_types.h" |
09407579 | 19 | #include "intel_sseu.h" |
39e2f501 | 20 | |
1d0e2c93 CW |
21 | #define CONTEXT_REDZONE POISON_INUSE |
22 | ||
1883a0a4 TU |
23 | DECLARE_EWMA(runtime, 3, 8); |
24 | ||
39e2f501 | 25 | struct i915_gem_context; |
47b08693 | 26 | struct i915_gem_ww_ctx; |
39e2f501 | 27 | struct i915_vma; |
c744d503 | 28 | struct intel_breadcrumbs; |
39e2f501 CW |
29 | struct intel_context; |
30 | struct intel_ring; | |
31 | ||
32 | struct intel_context_ops { | |
cc1557ca CW |
33 | unsigned long flags; |
34 | #define COPS_HAS_INFLIGHT_BIT 0 | |
35 | #define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT) | |
36 | ||
4c60b1aa CW |
37 | int (*alloc)(struct intel_context *ce); |
38 | ||
47b08693 | 39 | int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr); |
3999a708 | 40 | int (*pin)(struct intel_context *ce, void *vaddr); |
39e2f501 | 41 | void (*unpin)(struct intel_context *ce); |
3999a708 | 42 | void (*post_unpin)(struct intel_context *ce); |
4c5896dc | 43 | |
6eee33e8 CW |
44 | void (*enter)(struct intel_context *ce); |
45 | void (*exit)(struct intel_context *ce); | |
46 | ||
9726920b | 47 | void (*reset)(struct intel_context *ce); |
4c5896dc | 48 | void (*destroy)(struct kref *kref); |
39e2f501 CW |
49 | }; |
50 | ||
39e2f501 | 51 | struct intel_context { |
14d1eaf0 CW |
52 | /* |
53 | * Note: Some fields may be accessed under RCU. | |
54 | * | |
55 | * Unless otherwise noted a field can safely be assumed to be protected | |
56 | * by strong reference counting. | |
57 | */ | |
58 | union { | |
59 | struct kref ref; /* no kref_get_unless_zero()! */ | |
60 | struct rcu_head rcu; | |
61 | }; | |
4c5896dc | 62 | |
39e2f501 | 63 | struct intel_engine_cs *engine; |
754f7a0b | 64 | struct intel_engine_cs *inflight; |
6f0726b4 CW |
65 | #define __intel_context_inflight(engine) ptr_mask_bits(engine, 3) |
66 | #define __intel_context_inflight_count(engine) ptr_unmask_bits(engine, 3) | |
67 | #define intel_context_inflight(ce) \ | |
68 | __intel_context_inflight(READ_ONCE((ce)->inflight)) | |
69 | #define intel_context_inflight_count(ce) \ | |
70 | __intel_context_inflight_count(READ_ONCE((ce)->inflight)) | |
08819549 | 71 | |
f5d974f9 | 72 | struct i915_address_space *vm; |
6a8679c0 | 73 | struct i915_gem_context __rcu *gem_context; |
f5d974f9 | 74 | |
c744d503 CW |
75 | /* |
76 | * @signal_lock protects the list of requests that need signaling, | |
77 | * @signals. While there are any requests that need signaling, | |
78 | * we add the context to the breadcrumbs worker, and remove it | |
79 | * upon completion/cancellation of the last request. | |
80 | */ | |
81 | struct list_head signal_link; /* Accessed under RCU */ | |
82 | struct list_head signals; /* Guarded by signal_lock */ | |
83 | spinlock_t signal_lock; /* protects signals, the list of requests */ | |
08819549 | 84 | |
39e2f501 CW |
85 | struct i915_vma *state; |
86 | struct intel_ring *ring; | |
75d0a7f3 | 87 | struct intel_timeline *timeline; |
08819549 | 88 | |
4c60b1aa | 89 | unsigned long flags; |
e6ba7648 CW |
90 | #define CONTEXT_BARRIER_BIT 0 |
91 | #define CONTEXT_ALLOC_BIT 1 | |
093a0bea ML |
92 | #define CONTEXT_INIT_BIT 2 |
93 | #define CONTEXT_VALID_BIT 3 | |
94 | #define CONTEXT_CLOSED_BIT 4 | |
95 | #define CONTEXT_USE_SEMAPHORES 5 | |
96 | #define CONTEXT_BANNED 6 | |
97 | #define CONTEXT_FORCE_SINGLE_SUBMISSION 7 | |
98 | #define CONTEXT_NOPREEMPT 8 | |
4c60b1aa | 99 | |
39e2f501 | 100 | u32 *lrc_reg_state; |
2632f174 CW |
101 | union { |
102 | struct { | |
103 | u32 lrca; | |
104 | u32 ccid; | |
105 | }; | |
106 | u64 desc; | |
107 | } lrc; | |
2935ed53 | 108 | u32 tag; /* cookie passed to HW to track this context on submission */ |
08819549 | 109 | |
1883a0a4 TU |
110 | /* Time on GPU as tracked by the hw. */ |
111 | struct { | |
112 | struct ewma_runtime avg; | |
113 | u64 total; | |
114 | u32 last; | |
115 | I915_SELFTEST_DECLARE(u32 num_underflow); | |
116 | I915_SELFTEST_DECLARE(u32 max_underflow); | |
117 | } runtime; | |
118 | ||
6c69a454 | 119 | unsigned int active_count; /* protected by timeline->mutex */ |
6eee33e8 | 120 | |
08819549 CW |
121 | atomic_t pin_count; |
122 | struct mutex pin_mutex; /* guards pinning and associated on-gpuing */ | |
39e2f501 CW |
123 | |
124 | /** | |
ce476c80 CW |
125 | * active: Active tracker for the rq activity (inc. external) on this |
126 | * intel_context object. | |
39e2f501 | 127 | */ |
ce476c80 | 128 | struct i915_active active; |
39e2f501 CW |
129 | |
130 | const struct intel_context_ops *ops; | |
131 | ||
132 | /** sseu: Control eu/slice partitioning */ | |
133 | struct intel_sseu sseu; | |
685d2109 MK |
134 | |
135 | u8 wa_bb_page; /* if set, page num reserved for context workarounds */ | |
39e2f501 CW |
136 | }; |
137 | ||
138 | #endif /* __INTEL_CONTEXT_TYPES__ */ |