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1 | /* SPDX-License-Identifier: MIT */ |
2 | /* | |
3 | * Copyright © 2020 Intel Corporation | |
4 | */ | |
5 | ||
6 | #ifndef __GEN2_ENGINE_CS_H__ | |
7 | #define __GEN2_ENGINE_CS_H__ | |
8 | ||
9 | #include <linux/types.h> | |
10 | ||
11 | struct i915_request; | |
12 | struct intel_engine_cs; | |
13 | ||
14 | int gen2_emit_flush(struct i915_request *rq, u32 mode); | |
15 | int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode); | |
16 | int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode); | |
17 | ||
18 | u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs); | |
19 | u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs); | |
20 | ||
21 | int i830_emit_bb_start(struct i915_request *rq, | |
22 | u64 offset, u32 len, | |
23 | unsigned int dispatch_flags); | |
24 | int gen3_emit_bb_start(struct i915_request *rq, | |
25 | u64 offset, u32 len, | |
26 | unsigned int dispatch_flags); | |
27 | int gen4_emit_bb_start(struct i915_request *rq, | |
28 | u64 offset, u32 length, | |
29 | unsigned int dispatch_flags); | |
30 | ||
31 | void gen2_irq_enable(struct intel_engine_cs *engine); | |
32 | void gen2_irq_disable(struct intel_engine_cs *engine); | |
33 | void gen3_irq_enable(struct intel_engine_cs *engine); | |
34 | void gen3_irq_disable(struct intel_engine_cs *engine); | |
35 | void gen5_irq_enable(struct intel_engine_cs *engine); | |
36 | void gen5_irq_disable(struct intel_engine_cs *engine); | |
37 | ||
38 | #endif /* __GEN2_ENGINE_CS_H__ */ |