[linux-2.6-block.git] / drivers / gpu / drm / i915 / gem / selftests / i915_gem_object_blt.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2019 Intel Corporation
 */

#include "gt/intel_gt.h"

#include "i915_selftest.h"

#include "selftests/igt_flush_test.h"
#include "selftests/mock_drm.h"
#include "mock_context.h"

static int igt_fill_blt(void *arg)
{
	struct drm_i915_private *i915 = arg;
	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
	struct drm_i915_gem_object *obj;
	struct rnd_state prng;
	IGT_TIMEOUT(end);
	u32 *vaddr;
	int err = 0;

	prandom_seed_state(&prng, i915_selftest.random_seed);

	do {
		u32 sz = prandom_u32_state(&prng) % SZ_32M;
		u32 val = prandom_u32_state(&prng);
		u32 i;

		sz = round_up(sz, PAGE_SIZE);

		pr_debug("%s with sz=%x, val=%x\n", __func__, sz, val);

		obj = i915_gem_object_create_internal(i915, sz);
		if (IS_ERR(obj)) {
			err = PTR_ERR(obj);
			goto err_flush;
		}

		vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
		if (IS_ERR(vaddr)) {
			err = PTR_ERR(vaddr);
			goto err_put;
		}

		/*
		 * Make sure the potentially async clflush does its job, if
		 * required.
		 */
		memset32(vaddr, val ^ 0xdeadbeaf, obj->base.size / sizeof(u32));

		if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
			obj->cache_dirty = true;

		mutex_lock(&i915->drm.struct_mutex);
		err = i915_gem_object_fill_blt(obj, ce, val);
		mutex_unlock(&i915->drm.struct_mutex);
		if (err)
			goto err_unpin;

		i915_gem_object_lock(obj);
		err = i915_gem_object_set_to_cpu_domain(obj, false);
		i915_gem_object_unlock(obj);
		if (err)
			goto err_unpin;

		for (i = 0; i < obj->base.size / sizeof(u32); ++i) {
			if (vaddr[i] != val) {
				pr_err("vaddr[%u]=%x, expected=%x\n", i,
				       vaddr[i], val);
				err = -EINVAL;
				goto err_unpin;
			}
		}

		i915_gem_object_unpin_map(obj);
		i915_gem_object_put(obj);
	} while (!time_after(jiffies, end));

	goto err_flush;

err_unpin:
	i915_gem_object_unpin_map(obj);
err_put:
	i915_gem_object_put(obj);
err_flush:
	if (err == -ENOMEM)
		err = 0;

	return err;
}

int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915)
{
	static const struct i915_subtest tests[] = {
		SUBTEST(igt_fill_blt),
	};

	if (intel_gt_is_wedged(&i915->gt))
		return 0;

	if (!HAS_ENGINE(i915, BCS0))
		return 0;

	return i915_live_subtests(tests, i915);
}
Commit	Line	Data
6501aa4e MA	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
cb823ed9 CW	6	#include "gt/intel_gt.h"
cb823ed9 CW	7
6501aa4e MA	8	#include "i915_selftest.h"
	9
	10	#include "selftests/igt_flush_test.h"
	11	#include "selftests/mock_drm.h"
	12	#include "mock_context.h"
	13
	14	static int igt_fill_blt(void *arg)
	15	{
63251685 CW	16	struct drm_i915_private *i915 = arg;
63251685 CW	17	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
6501aa4e MA	18	struct drm_i915_gem_object *obj;
	19	struct rnd_state prng;
	20	IGT_TIMEOUT(end);
	21	u32 *vaddr;
	22	int err = 0;
	23
	24	prandom_seed_state(&prng, i915_selftest.random_seed);
	25
	26	do {
	27	u32 sz = prandom_u32_state(&prng) % SZ_32M;
	28	u32 val = prandom_u32_state(&prng);
	29	u32 i;
	30
	31	sz = round_up(sz, PAGE_SIZE);
	32
	33	pr_debug("%s with sz=%x, val=%x\n", __func__, sz, val);
	34
	35	obj = i915_gem_object_create_internal(i915, sz);
	36	if (IS_ERR(obj)) {
fd1e194f	37	err = PTR_ERR(obj);
6501aa4e MA	38	goto err_flush;
	39	}
	40
	41	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
	42	if (IS_ERR(vaddr)) {
	43	err = PTR_ERR(vaddr);
	44	goto err_put;
	45	}
	46
	47	/*
	48	* Make sure the potentially async clflush does its job, if
	49	* required.
	50	*/
	51	memset32(vaddr, val ^ 0xdeadbeaf, obj->base.size / sizeof(u32));
	52
	53	if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
	54	obj->cache_dirty = true;
	55
	56	mutex_lock(&i915->drm.struct_mutex);
	57	err = i915_gem_object_fill_blt(obj, ce, val);
	58	mutex_unlock(&i915->drm.struct_mutex);
	59	if (err)
	60	goto err_unpin;
	61
	62	i915_gem_object_lock(obj);
	63	err = i915_gem_object_set_to_cpu_domain(obj, false);
	64	i915_gem_object_unlock(obj);
	65	if (err)
	66	goto err_unpin;
	67
	68	for (i = 0; i < obj->base.size / sizeof(u32); ++i) {
	69	if (vaddr[i] != val) {
	70	pr_err("vaddr[%u]=%x, expected=%x\n", i,
	71	vaddr[i], val);
	72	err = -EINVAL;
	73	goto err_unpin;
	74	}
	75	}
	76
	77	i915_gem_object_unpin_map(obj);
	78	i915_gem_object_put(obj);
	79	} while (!time_after(jiffies, end));
	80
	81	goto err_flush;
	82
	83	err_unpin:
	84	i915_gem_object_unpin_map(obj);
	85	err_put:
	86	i915_gem_object_put(obj);
	87	err_flush:
6501aa4e MA	88	if (err == -ENOMEM)
	89	err = 0;
	90
	91	return err;
	92	}
	93
	94	int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915)
	95	{
	96	static const struct i915_subtest tests[] = {
	97	SUBTEST(igt_fill_blt),
	98	};
	99
cb823ed9	100	if (intel_gt_is_wedged(&i915->gt))
6501aa4e MA	101	return 0;
	102
	103	if (!HAS_ENGINE(i915, BCS0))
	104	return 0;
	105
63251685	106	return i915_live_subtests(tests, i915);
6501aa4e	107	}