Commit | Line | Data |
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54cf91dc | 1 | /* |
10be98a7 | 2 | * SPDX-License-Identifier: MIT |
54cf91dc | 3 | * |
10be98a7 | 4 | * Copyright © 2008,2010 Intel Corporation |
54cf91dc CW |
5 | */ |
6 | ||
daedaa33 | 7 | #include <linux/intel-iommu.h> |
52791eee | 8 | #include <linux/dma-resv.h> |
fec0445c | 9 | #include <linux/sync_file.h> |
ad778f89 CW |
10 | #include <linux/uaccess.h> |
11 | ||
cf6e7bac | 12 | #include <drm/drm_syncobj.h> |
ad778f89 | 13 | |
df0566a6 JN |
14 | #include "display/intel_frontbuffer.h" |
15 | ||
afa13085 | 16 | #include "gem/i915_gem_ioctls.h" |
10be98a7 | 17 | #include "gt/intel_context.h" |
b40d7378 | 18 | #include "gt/intel_engine_pool.h" |
baea429d | 19 | #include "gt/intel_gt.h" |
8f2a1057 | 20 | #include "gt/intel_gt_pm.h" |
2871ea85 | 21 | #include "gt/intel_ring.h" |
8f2a1057 | 22 | |
6da4a2c4 | 23 | #include "i915_drv.h" |
57822dc6 | 24 | #include "i915_gem_clflush.h" |
10be98a7 | 25 | #include "i915_gem_context.h" |
6da4a2c4 | 26 | #include "i915_gem_ioctls.h" |
686c7c35 | 27 | #include "i915_sw_fence_work.h" |
54cf91dc | 28 | #include "i915_trace.h" |
54cf91dc | 29 | |
7d6236bb CW |
30 | struct eb_vma { |
31 | struct i915_vma *vma; | |
32 | unsigned int flags; | |
33 | ||
34 | /** This vma's place in the execbuf reservation list */ | |
35 | struct drm_i915_gem_exec_object2 *exec; | |
36 | struct list_head bind_link; | |
37 | struct list_head reloc_link; | |
38 | ||
39 | struct hlist_node node; | |
40 | u32 handle; | |
41 | }; | |
42 | ||
7dd4f672 CW |
43 | enum { |
44 | FORCE_CPU_RELOC = 1, | |
45 | FORCE_GTT_RELOC, | |
46 | FORCE_GPU_RELOC, | |
47 | #define DBG_FORCE_RELOC 0 /* choose one of the above! */ | |
48 | }; | |
d50415cc | 49 | |
003d8b91 CW |
50 | #define __EXEC_OBJECT_HAS_PIN BIT(31) |
51 | #define __EXEC_OBJECT_HAS_FENCE BIT(30) | |
52 | #define __EXEC_OBJECT_NEEDS_MAP BIT(29) | |
53 | #define __EXEC_OBJECT_NEEDS_BIAS BIT(28) | |
54 | #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ | |
2889caa9 CW |
55 | #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) |
56 | ||
57 | #define __EXEC_HAS_RELOC BIT(31) | |
003d8b91 | 58 | #define __EXEC_INTERNAL_FLAGS (~0u << 31) |
2889caa9 | 59 | #define UPDATE PIN_OFFSET_FIXED |
d23db88c CW |
60 | |
61 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 62 | |
650bc635 | 63 | #define __I915_EXEC_ILLEGAL_FLAGS \ |
08e3e21a LDM |
64 | (__I915_EXEC_UNKNOWN_FLAGS | \ |
65 | I915_EXEC_CONSTANTS_MASK | \ | |
66 | I915_EXEC_RESOURCE_STREAMER) | |
5b043f4e | 67 | |
d20ac620 CW |
68 | /* Catch emission of unexpected errors for CI! */ |
69 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) | |
70 | #undef EINVAL | |
71 | #define EINVAL ({ \ | |
72 | DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \ | |
73 | 22; \ | |
74 | }) | |
75 | #endif | |
76 | ||
2889caa9 CW |
77 | /** |
78 | * DOC: User command execution | |
79 | * | |
80 | * Userspace submits commands to be executed on the GPU as an instruction | |
81 | * stream within a GEM object we call a batchbuffer. This instructions may | |
82 | * refer to other GEM objects containing auxiliary state such as kernels, | |
83 | * samplers, render targets and even secondary batchbuffers. Userspace does | |
84 | * not know where in the GPU memory these objects reside and so before the | |
85 | * batchbuffer is passed to the GPU for execution, those addresses in the | |
86 | * batchbuffer and auxiliary objects are updated. This is known as relocation, | |
87 | * or patching. To try and avoid having to relocate each object on the next | |
88 | * execution, userspace is told the location of those objects in this pass, | |
89 | * but this remains just a hint as the kernel may choose a new location for | |
90 | * any object in the future. | |
91 | * | |
99d7e4ee KR |
92 | * At the level of talking to the hardware, submitting a batchbuffer for the |
93 | * GPU to execute is to add content to a buffer from which the HW | |
94 | * command streamer is reading. | |
95 | * | |
96 | * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e. | |
97 | * Execlists, this command is not placed on the same buffer as the | |
98 | * remaining items. | |
99 | * | |
100 | * 2. Add a command to invalidate caches to the buffer. | |
101 | * | |
102 | * 3. Add a batchbuffer start command to the buffer; the start command is | |
103 | * essentially a token together with the GPU address of the batchbuffer | |
104 | * to be executed. | |
105 | * | |
106 | * 4. Add a pipeline flush to the buffer. | |
107 | * | |
108 | * 5. Add a memory write command to the buffer to record when the GPU | |
109 | * is done executing the batchbuffer. The memory write writes the | |
110 | * global sequence number of the request, ``i915_request::global_seqno``; | |
111 | * the i915 driver uses the current value in the register to determine | |
112 | * if the GPU has completed the batchbuffer. | |
113 | * | |
114 | * 6. Add a user interrupt command to the buffer. This command instructs | |
115 | * the GPU to issue an interrupt when the command, pipeline flush and | |
116 | * memory write are completed. | |
117 | * | |
118 | * 7. Inform the hardware of the additional commands added to the buffer | |
119 | * (by updating the tail pointer). | |
120 | * | |
2889caa9 CW |
121 | * Processing an execbuf ioctl is conceptually split up into a few phases. |
122 | * | |
123 | * 1. Validation - Ensure all the pointers, handles and flags are valid. | |
124 | * 2. Reservation - Assign GPU address space for every object | |
125 | * 3. Relocation - Update any addresses to point to the final locations | |
126 | * 4. Serialisation - Order the request with respect to its dependencies | |
127 | * 5. Construction - Construct a request to execute the batchbuffer | |
128 | * 6. Submission (at some point in the future execution) | |
129 | * | |
130 | * Reserving resources for the execbuf is the most complicated phase. We | |
131 | * neither want to have to migrate the object in the address space, nor do | |
132 | * we want to have to update any relocations pointing to this object. Ideally, | |
133 | * we want to leave the object where it is and for all the existing relocations | |
134 | * to match. If the object is given a new address, or if userspace thinks the | |
135 | * object is elsewhere, we have to parse all the relocation entries and update | |
136 | * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that | |
137 | * all the target addresses in all of its objects match the value in the | |
138 | * relocation entries and that they all match the presumed offsets given by the | |
139 | * list of execbuffer objects. Using this knowledge, we know that if we haven't | |
140 | * moved any buffers, all the relocation entries are valid and we can skip | |
141 | * the update. (If userspace is wrong, the likely outcome is an impromptu GPU | |
142 | * hang.) The requirement for using I915_EXEC_NO_RELOC are: | |
143 | * | |
144 | * The addresses written in the objects must match the corresponding | |
145 | * reloc.presumed_offset which in turn must match the corresponding | |
146 | * execobject.offset. | |
147 | * | |
148 | * Any render targets written to in the batch must be flagged with | |
149 | * EXEC_OBJECT_WRITE. | |
150 | * | |
151 | * To avoid stalling, execobject.offset should match the current | |
152 | * address of that object within the active context. | |
153 | * | |
154 | * The reservation is done is multiple phases. First we try and keep any | |
155 | * object already bound in its current location - so as long as meets the | |
156 | * constraints imposed by the new execbuffer. Any object left unbound after the | |
157 | * first pass is then fitted into any available idle space. If an object does | |
158 | * not fit, all objects are removed from the reservation and the process rerun | |
159 | * after sorting the objects into a priority order (more difficult to fit | |
160 | * objects are tried first). Failing that, the entire VM is cleared and we try | |
161 | * to fit the execbuf once last time before concluding that it simply will not | |
162 | * fit. | |
163 | * | |
164 | * A small complication to all of this is that we allow userspace not only to | |
165 | * specify an alignment and a size for the object in the address space, but | |
166 | * we also allow userspace to specify the exact offset. This objects are | |
167 | * simpler to place (the location is known a priori) all we have to do is make | |
168 | * sure the space is available. | |
169 | * | |
170 | * Once all the objects are in place, patching up the buried pointers to point | |
171 | * to the final locations is a fairly simple job of walking over the relocation | |
172 | * entry arrays, looking up the right address and rewriting the value into | |
173 | * the object. Simple! ... The relocation entries are stored in user memory | |
174 | * and so to access them we have to copy them into a local buffer. That copy | |
175 | * has to avoid taking any pagefaults as they may lead back to a GEM object | |
176 | * requiring the struct_mutex (i.e. recursive deadlock). So once again we split | |
177 | * the relocation into multiple passes. First we try to do everything within an | |
178 | * atomic context (avoid the pagefaults) which requires that we never wait. If | |
179 | * we detect that we may wait, or if we need to fault, then we have to fallback | |
180 | * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm | |
181 | * bells yet?) Dropping the mutex means that we lose all the state we have | |
182 | * built up so far for the execbuf and we must reset any global data. However, | |
183 | * we do leave the objects pinned in their final locations - which is a | |
184 | * potential issue for concurrent execbufs. Once we have left the mutex, we can | |
185 | * allocate and copy all the relocation entries into a large array at our | |
186 | * leisure, reacquire the mutex, reclaim all the objects and other state and | |
187 | * then proceed to update any incorrect addresses with the objects. | |
188 | * | |
189 | * As we process the relocation entries, we maintain a record of whether the | |
190 | * object is being written to. Using NORELOC, we expect userspace to provide | |
191 | * this information instead. We also check whether we can skip the relocation | |
192 | * by comparing the expected value inside the relocation entry with the target's | |
193 | * final address. If they differ, we have to map the current object and rewrite | |
194 | * the 4 or 8 byte pointer within. | |
195 | * | |
196 | * Serialising an execbuf is quite simple according to the rules of the GEM | |
197 | * ABI. Execution within each context is ordered by the order of submission. | |
198 | * Writes to any GEM object are in order of submission and are exclusive. Reads | |
199 | * from a GEM object are unordered with respect to other reads, but ordered by | |
200 | * writes. A write submitted after a read cannot occur before the read, and | |
201 | * similarly any read submitted after a write cannot occur before the write. | |
202 | * Writes are ordered between engines such that only one write occurs at any | |
203 | * time (completing any reads beforehand) - using semaphores where available | |
204 | * and CPU serialisation otherwise. Other GEM access obey the same rules, any | |
205 | * write (either via mmaps using set-domain, or via pwrite) must flush all GPU | |
206 | * reads before starting, and any read (either using set-domain or pread) must | |
207 | * flush all GPU writes before starting. (Note we only employ a barrier before, | |
208 | * we currently rely on userspace not concurrently starting a new execution | |
209 | * whilst reading or writing to an object. This may be an advantage or not | |
210 | * depending on how much you trust userspace not to shoot themselves in the | |
211 | * foot.) Serialisation may just result in the request being inserted into | |
212 | * a DAG awaiting its turn, but most simple is to wait on the CPU until | |
213 | * all dependencies are resolved. | |
214 | * | |
215 | * After all of that, is just a matter of closing the request and handing it to | |
216 | * the hardware (well, leaving it in a queue to be executed). However, we also | |
217 | * offer the ability for batchbuffers to be run with elevated privileges so | |
218 | * that they access otherwise hidden registers. (Used to adjust L3 cache etc.) | |
219 | * Before any batch is given extra privileges we first must check that it | |
220 | * contains no nefarious instructions, we check that each instruction is from | |
221 | * our whitelist and all registers are also from an allowed list. We first | |
222 | * copy the user's batchbuffer to a shadow (so that the user doesn't have | |
223 | * access to it, either by the CPU or GPU as we scan it) and then parse each | |
224 | * instruction. If everything is ok, we set a flag telling the hardware to run | |
225 | * the batchbuffer in trusted mode, otherwise the ioctl is rejected. | |
226 | */ | |
227 | ||
650bc635 | 228 | struct i915_execbuffer { |
2889caa9 CW |
229 | struct drm_i915_private *i915; /** i915 backpointer */ |
230 | struct drm_file *file; /** per-file lookup tables and limits */ | |
231 | struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */ | |
232 | struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */ | |
7d6236bb | 233 | struct eb_vma *vma; |
2889caa9 CW |
234 | |
235 | struct intel_engine_cs *engine; /** engine to queue the request to */ | |
8f2a1057 CW |
236 | struct intel_context *context; /* logical state for the request */ |
237 | struct i915_gem_context *gem_context; /** caller's context */ | |
2889caa9 | 238 | |
e61e0f51 | 239 | struct i915_request *request; /** our request to build */ |
7d6236bb | 240 | struct eb_vma *batch; /** identity of the batch obj/vma */ |
32d94048 | 241 | struct i915_vma *trampoline; /** trampoline used for chaining */ |
2889caa9 CW |
242 | |
243 | /** actual size of execobj[] as we may extend it for the cmdparser */ | |
244 | unsigned int buffer_count; | |
245 | ||
246 | /** list of vma not yet bound during reservation phase */ | |
247 | struct list_head unbound; | |
248 | ||
249 | /** list of vma that have execobj.relocation_count */ | |
250 | struct list_head relocs; | |
251 | ||
252 | /** | |
253 | * Track the most recently used object for relocations, as we | |
254 | * frequently have to perform multiple relocations within the same | |
255 | * obj/page | |
256 | */ | |
650bc635 | 257 | struct reloc_cache { |
2889caa9 CW |
258 | struct drm_mm_node node; /** temporary GTT binding */ |
259 | unsigned long vaddr; /** Current kmap address */ | |
260 | unsigned long page; /** Currently mapped page index */ | |
7dd4f672 | 261 | unsigned int gen; /** Cached value of INTEL_GEN */ |
650bc635 | 262 | bool use_64bit_reloc : 1; |
2889caa9 CW |
263 | bool has_llc : 1; |
264 | bool has_fence : 1; | |
265 | bool needs_unfenced : 1; | |
7dd4f672 | 266 | |
e61e0f51 | 267 | struct i915_request *rq; |
7dd4f672 CW |
268 | u32 *rq_cmd; |
269 | unsigned int rq_size; | |
650bc635 | 270 | } reloc_cache; |
2889caa9 CW |
271 | |
272 | u64 invalid_flags; /** Set of execobj.flags that are invalid */ | |
273 | u32 context_flags; /** Set of execobj.flags to insert from the ctx */ | |
274 | ||
275 | u32 batch_start_offset; /** Location within object of batch */ | |
276 | u32 batch_len; /** Length of batch within object */ | |
277 | u32 batch_flags; /** Flags composed for emit_bb_start() */ | |
278 | ||
279 | /** | |
280 | * Indicate either the size of the hastable used to resolve | |
281 | * relocation handles, or if negative that we are using a direct | |
282 | * index into the execobj[]. | |
283 | */ | |
284 | int lut_size; | |
285 | struct hlist_head *buckets; /** ht for relocation handles */ | |
67731b87 CW |
286 | }; |
287 | ||
3dbf26ed CW |
288 | static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) |
289 | { | |
311a50e7 | 290 | return intel_engine_requires_cmd_parser(eb->engine) || |
435e8fc0 JB |
291 | (intel_engine_using_cmd_parser(eb->engine) && |
292 | eb->args->batch_len); | |
3dbf26ed CW |
293 | } |
294 | ||
650bc635 | 295 | static int eb_create(struct i915_execbuffer *eb) |
67731b87 | 296 | { |
2889caa9 CW |
297 | if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { |
298 | unsigned int size = 1 + ilog2(eb->buffer_count); | |
4ff4b44c | 299 | |
2889caa9 CW |
300 | /* |
301 | * Without a 1:1 association between relocation handles and | |
302 | * the execobject[] index, we instead create a hashtable. | |
303 | * We size it dynamically based on available memory, starting | |
304 | * first with 1:1 assocative hash and scaling back until | |
305 | * the allocation succeeds. | |
306 | * | |
307 | * Later on we use a positive lut_size to indicate we are | |
308 | * using this hashtable, and a negative value to indicate a | |
309 | * direct lookup. | |
310 | */ | |
4ff4b44c | 311 | do { |
0d95c883 | 312 | gfp_t flags; |
4d470f73 CW |
313 | |
314 | /* While we can still reduce the allocation size, don't | |
315 | * raise a warning and allow the allocation to fail. | |
316 | * On the last pass though, we want to try as hard | |
317 | * as possible to perform the allocation and warn | |
318 | * if it fails. | |
319 | */ | |
0ee931c4 | 320 | flags = GFP_KERNEL; |
4d470f73 CW |
321 | if (size > 1) |
322 | flags |= __GFP_NORETRY | __GFP_NOWARN; | |
323 | ||
4ff4b44c | 324 | eb->buckets = kzalloc(sizeof(struct hlist_head) << size, |
4d470f73 | 325 | flags); |
4ff4b44c CW |
326 | if (eb->buckets) |
327 | break; | |
328 | } while (--size); | |
329 | ||
4d470f73 CW |
330 | if (unlikely(!size)) |
331 | return -ENOMEM; | |
eef90ccb | 332 | |
2889caa9 | 333 | eb->lut_size = size; |
650bc635 | 334 | } else { |
2889caa9 | 335 | eb->lut_size = -eb->buffer_count; |
650bc635 | 336 | } |
eef90ccb | 337 | |
650bc635 | 338 | return 0; |
67731b87 CW |
339 | } |
340 | ||
2889caa9 CW |
341 | static bool |
342 | eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, | |
c7c6e46f CW |
343 | const struct i915_vma *vma, |
344 | unsigned int flags) | |
2889caa9 | 345 | { |
2889caa9 CW |
346 | if (vma->node.size < entry->pad_to_size) |
347 | return true; | |
348 | ||
349 | if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) | |
350 | return true; | |
351 | ||
c7c6e46f | 352 | if (flags & EXEC_OBJECT_PINNED && |
2889caa9 CW |
353 | vma->node.start != entry->offset) |
354 | return true; | |
355 | ||
c7c6e46f | 356 | if (flags & __EXEC_OBJECT_NEEDS_BIAS && |
2889caa9 CW |
357 | vma->node.start < BATCH_OFFSET_BIAS) |
358 | return true; | |
359 | ||
c7c6e46f | 360 | if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && |
2889caa9 CW |
361 | (vma->node.start + vma->node.size - 1) >> 32) |
362 | return true; | |
363 | ||
1d033beb CW |
364 | if (flags & __EXEC_OBJECT_NEEDS_MAP && |
365 | !i915_vma_is_map_and_fenceable(vma)) | |
366 | return true; | |
367 | ||
2889caa9 CW |
368 | return false; |
369 | } | |
370 | ||
c7c6e46f | 371 | static inline bool |
2889caa9 | 372 | eb_pin_vma(struct i915_execbuffer *eb, |
c7c6e46f | 373 | const struct drm_i915_gem_exec_object2 *entry, |
7d6236bb | 374 | struct eb_vma *ev) |
2889caa9 | 375 | { |
7d6236bb | 376 | struct i915_vma *vma = ev->vma; |
c7c6e46f | 377 | u64 pin_flags; |
2889caa9 | 378 | |
616d9cee | 379 | if (vma->node.size) |
c7c6e46f | 380 | pin_flags = vma->node.start; |
616d9cee | 381 | else |
c7c6e46f | 382 | pin_flags = entry->offset & PIN_OFFSET_MASK; |
616d9cee | 383 | |
c7c6e46f | 384 | pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; |
7d6236bb | 385 | if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT)) |
c7c6e46f | 386 | pin_flags |= PIN_GLOBAL; |
616d9cee | 387 | |
c7c6e46f CW |
388 | if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) |
389 | return false; | |
2889caa9 | 390 | |
7d6236bb | 391 | if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) { |
3bd40735 | 392 | if (unlikely(i915_vma_pin_fence(vma))) { |
2889caa9 | 393 | i915_vma_unpin(vma); |
c7c6e46f | 394 | return false; |
2889caa9 CW |
395 | } |
396 | ||
3bd40735 | 397 | if (vma->fence) |
7d6236bb | 398 | ev->flags |= __EXEC_OBJECT_HAS_FENCE; |
2889caa9 CW |
399 | } |
400 | ||
7d6236bb CW |
401 | ev->flags |= __EXEC_OBJECT_HAS_PIN; |
402 | return !eb_vma_misplaced(entry, vma, ev->flags); | |
2889caa9 CW |
403 | } |
404 | ||
c7c6e46f | 405 | static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) |
d55495b4 | 406 | { |
c7c6e46f | 407 | GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); |
2889caa9 | 408 | |
c7c6e46f | 409 | if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) |
3bd40735 | 410 | __i915_vma_unpin_fence(vma); |
d55495b4 | 411 | |
2889caa9 | 412 | __i915_vma_unpin(vma); |
d55495b4 CW |
413 | } |
414 | ||
2889caa9 | 415 | static inline void |
7d6236bb | 416 | eb_unreserve_vma(struct eb_vma *ev) |
d55495b4 | 417 | { |
7d6236bb | 418 | if (!(ev->flags & __EXEC_OBJECT_HAS_PIN)) |
2889caa9 | 419 | return; |
d55495b4 | 420 | |
7d6236bb CW |
421 | __eb_unreserve_vma(ev->vma, ev->flags); |
422 | ev->flags &= ~__EXEC_OBJECT_RESERVED; | |
d55495b4 CW |
423 | } |
424 | ||
2889caa9 CW |
425 | static int |
426 | eb_validate_vma(struct i915_execbuffer *eb, | |
427 | struct drm_i915_gem_exec_object2 *entry, | |
428 | struct i915_vma *vma) | |
67731b87 | 429 | { |
2889caa9 CW |
430 | if (unlikely(entry->flags & eb->invalid_flags)) |
431 | return -EINVAL; | |
d55495b4 | 432 | |
2920516b MA |
433 | if (unlikely(entry->alignment && |
434 | !is_power_of_2_u64(entry->alignment))) | |
2889caa9 CW |
435 | return -EINVAL; |
436 | ||
437 | /* | |
438 | * Offset can be used as input (EXEC_OBJECT_PINNED), reject | |
439 | * any non-page-aligned or non-canonical addresses. | |
440 | */ | |
441 | if (unlikely(entry->flags & EXEC_OBJECT_PINNED && | |
6fc4e48f | 442 | entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK))) |
2889caa9 CW |
443 | return -EINVAL; |
444 | ||
445 | /* pad_to_size was once a reserved field, so sanitize it */ | |
446 | if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) { | |
447 | if (unlikely(offset_in_page(entry->pad_to_size))) | |
448 | return -EINVAL; | |
449 | } else { | |
450 | entry->pad_to_size = 0; | |
d55495b4 | 451 | } |
2889caa9 CW |
452 | /* |
453 | * From drm_mm perspective address space is continuous, | |
454 | * so from this point we're always using non-canonical | |
455 | * form internally. | |
456 | */ | |
457 | entry->offset = gen8_noncanonical_addr(entry->offset); | |
458 | ||
c7c6e46f CW |
459 | if (!eb->reloc_cache.has_fence) { |
460 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
461 | } else { | |
462 | if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || | |
463 | eb->reloc_cache.needs_unfenced) && | |
464 | i915_gem_object_is_tiled(vma->obj)) | |
465 | entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; | |
466 | } | |
467 | ||
468 | if (!(entry->flags & EXEC_OBJECT_PINNED)) | |
469 | entry->flags |= eb->context_flags; | |
470 | ||
2889caa9 | 471 | return 0; |
67731b87 CW |
472 | } |
473 | ||
003d8b91 | 474 | static void |
746c8f14 CW |
475 | eb_add_vma(struct i915_execbuffer *eb, |
476 | unsigned int i, unsigned batch_idx, | |
477 | struct i915_vma *vma) | |
59bfa124 | 478 | { |
c7c6e46f | 479 | struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; |
7d6236bb | 480 | struct eb_vma *ev = &eb->vma[i]; |
2889caa9 CW |
481 | |
482 | GEM_BUG_ON(i915_vma_is_closed(vma)); | |
483 | ||
003d8b91 | 484 | ev->vma = i915_vma_get(vma); |
7d6236bb CW |
485 | ev->exec = entry; |
486 | ev->flags = entry->flags; | |
487 | ||
4d470f73 | 488 | if (eb->lut_size > 0) { |
7d6236bb CW |
489 | ev->handle = entry->handle; |
490 | hlist_add_head(&ev->node, | |
2889caa9 CW |
491 | &eb->buckets[hash_32(entry->handle, |
492 | eb->lut_size)]); | |
4ff4b44c | 493 | } |
59bfa124 | 494 | |
2889caa9 | 495 | if (entry->relocation_count) |
7d6236bb | 496 | list_add_tail(&ev->reloc_link, &eb->relocs); |
2889caa9 | 497 | |
746c8f14 CW |
498 | /* |
499 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
500 | * to negative relocation deltas. Usually that works out ok since the | |
501 | * relocate address is still positive, except when the batch is placed | |
502 | * very low in the GTT. Ensure this doesn't happen. | |
503 | * | |
504 | * Note that actual hangs have only been observed on gen7, but for | |
505 | * paranoia do it everywhere. | |
506 | */ | |
507 | if (i == batch_idx) { | |
827db9d8 | 508 | if (entry->relocation_count && |
7d6236bb CW |
509 | !(ev->flags & EXEC_OBJECT_PINNED)) |
510 | ev->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
746c8f14 | 511 | if (eb->reloc_cache.has_fence) |
7d6236bb | 512 | ev->flags |= EXEC_OBJECT_NEEDS_FENCE; |
746c8f14 | 513 | |
7d6236bb | 514 | eb->batch = ev; |
746c8f14 CW |
515 | } |
516 | ||
7d6236bb | 517 | if (eb_pin_vma(eb, entry, ev)) { |
2889caa9 CW |
518 | if (entry->offset != vma->node.start) { |
519 | entry->offset = vma->node.start | UPDATE; | |
520 | eb->args->flags |= __EXEC_HAS_RELOC; | |
521 | } | |
c7c6e46f | 522 | } else { |
7d6236bb | 523 | eb_unreserve_vma(ev); |
7d6236bb | 524 | list_add_tail(&ev->bind_link, &eb->unbound); |
2889caa9 | 525 | } |
2889caa9 CW |
526 | } |
527 | ||
528 | static inline int use_cpu_reloc(const struct reloc_cache *cache, | |
529 | const struct drm_i915_gem_object *obj) | |
530 | { | |
531 | if (!i915_gem_object_has_struct_page(obj)) | |
532 | return false; | |
533 | ||
7dd4f672 CW |
534 | if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) |
535 | return true; | |
536 | ||
537 | if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) | |
538 | return false; | |
2889caa9 CW |
539 | |
540 | return (cache->has_llc || | |
541 | obj->cache_dirty || | |
542 | obj->cache_level != I915_CACHE_NONE); | |
543 | } | |
544 | ||
545 | static int eb_reserve_vma(const struct i915_execbuffer *eb, | |
7d6236bb | 546 | struct eb_vma *ev, |
2920bb94 | 547 | u64 pin_flags) |
2889caa9 | 548 | { |
7d6236bb CW |
549 | struct drm_i915_gem_exec_object2 *entry = ev->exec; |
550 | unsigned int exec_flags = ev->flags; | |
551 | struct i915_vma *vma = ev->vma; | |
2889caa9 CW |
552 | int err; |
553 | ||
c7c6e46f CW |
554 | if (exec_flags & EXEC_OBJECT_NEEDS_GTT) |
555 | pin_flags |= PIN_GLOBAL; | |
2889caa9 CW |
556 | |
557 | /* | |
558 | * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, | |
559 | * limit address to the first 4GBs for unflagged objects. | |
560 | */ | |
c7c6e46f CW |
561 | if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) |
562 | pin_flags |= PIN_ZONE_4G; | |
2889caa9 | 563 | |
c7c6e46f CW |
564 | if (exec_flags & __EXEC_OBJECT_NEEDS_MAP) |
565 | pin_flags |= PIN_MAPPABLE; | |
2889caa9 | 566 | |
2920bb94 | 567 | if (exec_flags & EXEC_OBJECT_PINNED) |
c7c6e46f | 568 | pin_flags |= entry->offset | PIN_OFFSET_FIXED; |
2920bb94 | 569 | else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) |
c7c6e46f | 570 | pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; |
2889caa9 | 571 | |
003d8b91 CW |
572 | if (drm_mm_node_allocated(&vma->node) && |
573 | eb_vma_misplaced(entry, vma, ev->flags)) { | |
574 | err = i915_vma_unbind(vma); | |
575 | if (err) | |
576 | return err; | |
577 | } | |
578 | ||
c7c6e46f CW |
579 | err = i915_vma_pin(vma, |
580 | entry->pad_to_size, entry->alignment, | |
581 | pin_flags); | |
2889caa9 CW |
582 | if (err) |
583 | return err; | |
584 | ||
585 | if (entry->offset != vma->node.start) { | |
586 | entry->offset = vma->node.start | UPDATE; | |
587 | eb->args->flags |= __EXEC_HAS_RELOC; | |
588 | } | |
589 | ||
c7c6e46f | 590 | if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { |
3bd40735 | 591 | err = i915_vma_pin_fence(vma); |
2889caa9 CW |
592 | if (unlikely(err)) { |
593 | i915_vma_unpin(vma); | |
594 | return err; | |
595 | } | |
596 | ||
3bd40735 | 597 | if (vma->fence) |
c7c6e46f | 598 | exec_flags |= __EXEC_OBJECT_HAS_FENCE; |
2889caa9 CW |
599 | } |
600 | ||
7d6236bb CW |
601 | ev->flags = exec_flags | __EXEC_OBJECT_HAS_PIN; |
602 | GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags)); | |
1da7b54c | 603 | |
2889caa9 CW |
604 | return 0; |
605 | } | |
606 | ||
607 | static int eb_reserve(struct i915_execbuffer *eb) | |
608 | { | |
609 | const unsigned int count = eb->buffer_count; | |
2920bb94 | 610 | unsigned int pin_flags = PIN_USER | PIN_NONBLOCK; |
2889caa9 | 611 | struct list_head last; |
7d6236bb | 612 | struct eb_vma *ev; |
2889caa9 | 613 | unsigned int i, pass; |
ef398881 | 614 | int err = 0; |
2889caa9 CW |
615 | |
616 | /* | |
617 | * Attempt to pin all of the buffers into the GTT. | |
618 | * This is done in 3 phases: | |
619 | * | |
620 | * 1a. Unbind all objects that do not match the GTT constraints for | |
621 | * the execbuffer (fenceable, mappable, alignment etc). | |
622 | * 1b. Increment pin count for already bound objects. | |
623 | * 2. Bind new objects. | |
624 | * 3. Decrement pin count. | |
625 | * | |
626 | * This avoid unnecessary unbinding of later objects in order to make | |
627 | * room for the earlier objects *unless* we need to defragment. | |
628 | */ | |
629 | ||
ef398881 CW |
630 | if (mutex_lock_interruptible(&eb->i915->drm.struct_mutex)) |
631 | return -EINTR; | |
632 | ||
2889caa9 | 633 | pass = 0; |
2889caa9 | 634 | do { |
7d6236bb CW |
635 | list_for_each_entry(ev, &eb->unbound, bind_link) { |
636 | err = eb_reserve_vma(eb, ev, pin_flags); | |
2889caa9 CW |
637 | if (err) |
638 | break; | |
639 | } | |
003d8b91 | 640 | if (!(err == -ENOSPC || err == -EAGAIN)) |
ef398881 | 641 | break; |
2889caa9 CW |
642 | |
643 | /* Resort *all* the objects into priority order */ | |
644 | INIT_LIST_HEAD(&eb->unbound); | |
645 | INIT_LIST_HEAD(&last); | |
646 | for (i = 0; i < count; i++) { | |
7d6236bb | 647 | unsigned int flags; |
2889caa9 | 648 | |
7d6236bb CW |
649 | ev = &eb->vma[i]; |
650 | flags = ev->flags; | |
c7c6e46f CW |
651 | if (flags & EXEC_OBJECT_PINNED && |
652 | flags & __EXEC_OBJECT_HAS_PIN) | |
2889caa9 CW |
653 | continue; |
654 | ||
7d6236bb | 655 | eb_unreserve_vma(ev); |
2889caa9 | 656 | |
c7c6e46f | 657 | if (flags & EXEC_OBJECT_PINNED) |
35e882a4 | 658 | /* Pinned must have their slot */ |
7d6236bb | 659 | list_add(&ev->bind_link, &eb->unbound); |
c7c6e46f | 660 | else if (flags & __EXEC_OBJECT_NEEDS_MAP) |
35e882a4 | 661 | /* Map require the lowest 256MiB (aperture) */ |
7d6236bb | 662 | list_add_tail(&ev->bind_link, &eb->unbound); |
35e882a4 CW |
663 | else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) |
664 | /* Prioritise 4GiB region for restricted bo */ | |
7d6236bb | 665 | list_add(&ev->bind_link, &last); |
2889caa9 | 666 | else |
7d6236bb | 667 | list_add_tail(&ev->bind_link, &last); |
2889caa9 CW |
668 | } |
669 | list_splice_tail(&last, &eb->unbound); | |
670 | ||
003d8b91 | 671 | if (err == -EAGAIN) { |
ef398881 | 672 | mutex_unlock(&eb->i915->drm.struct_mutex); |
003d8b91 | 673 | flush_workqueue(eb->i915->mm.userptr_wq); |
ef398881 | 674 | mutex_lock(&eb->i915->drm.struct_mutex); |
003d8b91 CW |
675 | continue; |
676 | } | |
677 | ||
2889caa9 CW |
678 | switch (pass++) { |
679 | case 0: | |
680 | break; | |
681 | ||
682 | case 1: | |
683 | /* Too fragmented, unbind everything and retry */ | |
2850748e | 684 | mutex_lock(&eb->context->vm->mutex); |
f5d974f9 | 685 | err = i915_gem_evict_vm(eb->context->vm); |
2850748e | 686 | mutex_unlock(&eb->context->vm->mutex); |
2889caa9 | 687 | if (err) |
ef398881 | 688 | goto unlock; |
2889caa9 CW |
689 | break; |
690 | ||
691 | default: | |
ef398881 CW |
692 | err = -ENOSPC; |
693 | goto unlock; | |
2889caa9 | 694 | } |
2920bb94 CW |
695 | |
696 | pin_flags = PIN_USER; | |
2889caa9 | 697 | } while (1); |
ef398881 CW |
698 | |
699 | unlock: | |
700 | mutex_unlock(&eb->i915->drm.struct_mutex); | |
701 | return err; | |
4ff4b44c | 702 | } |
59bfa124 | 703 | |
2889caa9 CW |
704 | static unsigned int eb_batch_index(const struct i915_execbuffer *eb) |
705 | { | |
1a71cf2f CW |
706 | if (eb->args->flags & I915_EXEC_BATCH_FIRST) |
707 | return 0; | |
708 | else | |
709 | return eb->buffer_count - 1; | |
2889caa9 CW |
710 | } |
711 | ||
712 | static int eb_select_context(struct i915_execbuffer *eb) | |
713 | { | |
714 | struct i915_gem_context *ctx; | |
715 | ||
716 | ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1); | |
1acfc104 CW |
717 | if (unlikely(!ctx)) |
718 | return -ENOENT; | |
2889caa9 | 719 | |
8f2a1057 | 720 | eb->gem_context = ctx; |
a4e7ccda | 721 | if (rcu_access_pointer(ctx->vm)) |
4f2c7337 | 722 | eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT; |
2889caa9 CW |
723 | |
724 | eb->context_flags = 0; | |
d3f3e5e4 | 725 | if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags)) |
2889caa9 CW |
726 | eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS; |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
731 | static int eb_lookup_vmas(struct i915_execbuffer *eb) | |
3b96eff4 | 732 | { |
8f2a1057 | 733 | struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma; |
ac70ebe8 | 734 | struct drm_i915_gem_object *obj; |
746c8f14 | 735 | unsigned int i, batch; |
2889caa9 | 736 | int err; |
3b96eff4 | 737 | |
003d8b91 CW |
738 | if (unlikely(i915_gem_context_is_closed(eb->gem_context))) |
739 | return -ENOENT; | |
740 | ||
2889caa9 CW |
741 | INIT_LIST_HEAD(&eb->relocs); |
742 | INIT_LIST_HEAD(&eb->unbound); | |
d55495b4 | 743 | |
746c8f14 CW |
744 | batch = eb_batch_index(eb); |
745 | ||
170fa29b CW |
746 | for (i = 0; i < eb->buffer_count; i++) { |
747 | u32 handle = eb->exec[i].handle; | |
d1b48c1e | 748 | struct i915_lut_handle *lut; |
170fa29b | 749 | struct i915_vma *vma; |
4ff4b44c | 750 | |
d1b48c1e CW |
751 | vma = radix_tree_lookup(handles_vma, handle); |
752 | if (likely(vma)) | |
170fa29b | 753 | goto add_vma; |
4ff4b44c | 754 | |
170fa29b | 755 | obj = i915_gem_object_lookup(eb->file, handle); |
4ff4b44c | 756 | if (unlikely(!obj)) { |
2889caa9 | 757 | err = -ENOENT; |
170fa29b | 758 | goto err_vma; |
3b96eff4 CW |
759 | } |
760 | ||
f5d974f9 | 761 | vma = i915_vma_instance(obj, eb->context->vm, NULL); |
772b5408 | 762 | if (IS_ERR(vma)) { |
2889caa9 | 763 | err = PTR_ERR(vma); |
170fa29b | 764 | goto err_obj; |
27173f1f BW |
765 | } |
766 | ||
13f1bfd3 | 767 | lut = i915_lut_handle_alloc(); |
d1b48c1e CW |
768 | if (unlikely(!lut)) { |
769 | err = -ENOMEM; | |
770 | goto err_obj; | |
771 | } | |
772 | ||
773 | err = radix_tree_insert(handles_vma, handle, vma); | |
774 | if (unlikely(err)) { | |
13f1bfd3 | 775 | i915_lut_handle_free(lut); |
d1b48c1e | 776 | goto err_obj; |
eef90ccb | 777 | } |
4ff4b44c | 778 | |
155ab883 CW |
779 | /* transfer ref to lut */ |
780 | if (!atomic_fetch_inc(&vma->open_count)) | |
3365e226 | 781 | i915_vma_reopen(vma); |
d1b48c1e | 782 | lut->handle = handle; |
155ab883 CW |
783 | lut->ctx = eb->gem_context; |
784 | ||
785 | i915_gem_object_lock(obj); | |
786 | list_add(&lut->obj_link, &obj->lut_list); | |
787 | i915_gem_object_unlock(obj); | |
d1b48c1e | 788 | |
170fa29b | 789 | add_vma: |
003d8b91 | 790 | err = eb_validate_vma(eb, &eb->exec[i], vma); |
2889caa9 | 791 | if (unlikely(err)) |
ac70ebe8 | 792 | goto err_vma; |
dade2a61 | 793 | |
003d8b91 | 794 | eb_add_vma(eb, i, batch, vma); |
4ff4b44c CW |
795 | } |
796 | ||
003d8b91 | 797 | return 0; |
2889caa9 | 798 | |
170fa29b | 799 | err_obj: |
ac70ebe8 | 800 | i915_gem_object_put(obj); |
170fa29b | 801 | err_vma: |
7d6236bb | 802 | eb->vma[i].vma = NULL; |
2889caa9 | 803 | return err; |
3b96eff4 CW |
804 | } |
805 | ||
7d6236bb | 806 | static struct eb_vma * |
2889caa9 | 807 | eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) |
67731b87 | 808 | { |
2889caa9 CW |
809 | if (eb->lut_size < 0) { |
810 | if (handle >= -eb->lut_size) | |
eef90ccb | 811 | return NULL; |
7d6236bb | 812 | return &eb->vma[handle]; |
eef90ccb CW |
813 | } else { |
814 | struct hlist_head *head; | |
7d6236bb | 815 | struct eb_vma *ev; |
67731b87 | 816 | |
2889caa9 | 817 | head = &eb->buckets[hash_32(handle, eb->lut_size)]; |
7d6236bb CW |
818 | hlist_for_each_entry(ev, head, node) { |
819 | if (ev->handle == handle) | |
820 | return ev; | |
eef90ccb CW |
821 | } |
822 | return NULL; | |
823 | } | |
67731b87 CW |
824 | } |
825 | ||
2889caa9 | 826 | static void eb_release_vmas(const struct i915_execbuffer *eb) |
a415d355 | 827 | { |
2889caa9 CW |
828 | const unsigned int count = eb->buffer_count; |
829 | unsigned int i; | |
830 | ||
831 | for (i = 0; i < count; i++) { | |
7d6236bb CW |
832 | struct eb_vma *ev = &eb->vma[i]; |
833 | struct i915_vma *vma = ev->vma; | |
650bc635 | 834 | |
2889caa9 | 835 | if (!vma) |
170fa29b | 836 | break; |
bcffc3fa | 837 | |
7d6236bb | 838 | eb->vma[i].vma = NULL; |
9e53d9be | 839 | |
7d6236bb CW |
840 | if (ev->flags & __EXEC_OBJECT_HAS_PIN) |
841 | __eb_unreserve_vma(vma, ev->flags); | |
dade2a61 | 842 | |
003d8b91 | 843 | i915_vma_put(vma); |
2889caa9 | 844 | } |
dabdfe02 CW |
845 | } |
846 | ||
2889caa9 | 847 | static void eb_destroy(const struct i915_execbuffer *eb) |
934acce3 | 848 | { |
7dd4f672 CW |
849 | GEM_BUG_ON(eb->reloc_cache.rq); |
850 | ||
4d470f73 | 851 | if (eb->lut_size > 0) |
2889caa9 | 852 | kfree(eb->buckets); |
934acce3 MW |
853 | } |
854 | ||
2889caa9 | 855 | static inline u64 |
d50415cc | 856 | relocation_target(const struct drm_i915_gem_relocation_entry *reloc, |
2889caa9 | 857 | const struct i915_vma *target) |
934acce3 | 858 | { |
2889caa9 | 859 | return gen8_canonical_addr((int)reloc->delta + target->node.start); |
934acce3 MW |
860 | } |
861 | ||
d50415cc CW |
862 | static void reloc_cache_init(struct reloc_cache *cache, |
863 | struct drm_i915_private *i915) | |
5032d871 | 864 | { |
31a39207 | 865 | cache->page = -1; |
d50415cc | 866 | cache->vaddr = 0; |
dfc5148f | 867 | /* Must be a variable in the struct to allow GCC to unroll. */ |
7dd4f672 | 868 | cache->gen = INTEL_GEN(i915); |
2889caa9 | 869 | cache->has_llc = HAS_LLC(i915); |
dfc5148f | 870 | cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); |
7dd4f672 CW |
871 | cache->has_fence = cache->gen < 4; |
872 | cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; | |
4ee92c71 | 873 | cache->node.flags = 0; |
7dd4f672 CW |
874 | cache->rq = NULL; |
875 | cache->rq_size = 0; | |
d50415cc | 876 | } |
5032d871 | 877 | |
d50415cc CW |
878 | static inline void *unmask_page(unsigned long p) |
879 | { | |
880 | return (void *)(uintptr_t)(p & PAGE_MASK); | |
881 | } | |
882 | ||
883 | static inline unsigned int unmask_flags(unsigned long p) | |
884 | { | |
885 | return p & ~PAGE_MASK; | |
31a39207 CW |
886 | } |
887 | ||
d50415cc CW |
888 | #define KMAP 0x4 /* after CLFLUSH_FLAGS */ |
889 | ||
650bc635 CW |
890 | static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) |
891 | { | |
892 | struct drm_i915_private *i915 = | |
893 | container_of(cache, struct i915_execbuffer, reloc_cache)->i915; | |
894 | return &i915->ggtt; | |
895 | } | |
896 | ||
7dd4f672 CW |
897 | static void reloc_gpu_flush(struct reloc_cache *cache) |
898 | { | |
1aaea847 CW |
899 | struct drm_i915_gem_object *obj = cache->rq->batch->obj; |
900 | ||
901 | GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32)); | |
7dd4f672 | 902 | cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END; |
a679f58d | 903 | |
1aaea847 CW |
904 | __i915_gem_object_flush_map(obj, 0, sizeof(u32) * (cache->rq_size + 1)); |
905 | i915_gem_object_unpin_map(obj); | |
a679f58d | 906 | |
baea429d | 907 | intel_gt_chipset_flush(cache->rq->engine->gt); |
7dd4f672 | 908 | |
697b9a87 | 909 | i915_request_add(cache->rq); |
7dd4f672 CW |
910 | cache->rq = NULL; |
911 | } | |
912 | ||
650bc635 | 913 | static void reloc_cache_reset(struct reloc_cache *cache) |
31a39207 | 914 | { |
d50415cc | 915 | void *vaddr; |
5032d871 | 916 | |
7dd4f672 CW |
917 | if (cache->rq) |
918 | reloc_gpu_flush(cache); | |
919 | ||
31a39207 CW |
920 | if (!cache->vaddr) |
921 | return; | |
3c94ceee | 922 | |
d50415cc CW |
923 | vaddr = unmask_page(cache->vaddr); |
924 | if (cache->vaddr & KMAP) { | |
925 | if (cache->vaddr & CLFLUSH_AFTER) | |
926 | mb(); | |
3c94ceee | 927 | |
d50415cc | 928 | kunmap_atomic(vaddr); |
f0e4a063 | 929 | i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); |
d50415cc | 930 | } else { |
576f0586 CW |
931 | struct i915_ggtt *ggtt = cache_to_ggtt(cache); |
932 | ||
933 | intel_gt_flush_ggtt_writes(ggtt->vm.gt); | |
d50415cc | 934 | io_mapping_unmap_atomic((void __iomem *)vaddr); |
e8cb909a | 935 | |
b290a78b | 936 | if (drm_mm_node_allocated(&cache->node)) { |
82ad6443 CW |
937 | ggtt->vm.clear_range(&ggtt->vm, |
938 | cache->node.start, | |
939 | cache->node.size); | |
2850748e | 940 | mutex_lock(&ggtt->vm.mutex); |
e8cb909a | 941 | drm_mm_remove_node(&cache->node); |
2850748e | 942 | mutex_unlock(&ggtt->vm.mutex); |
e8cb909a CW |
943 | } else { |
944 | i915_vma_unpin((struct i915_vma *)cache->node.mm); | |
3c94ceee | 945 | } |
31a39207 | 946 | } |
650bc635 CW |
947 | |
948 | cache->vaddr = 0; | |
949 | cache->page = -1; | |
31a39207 CW |
950 | } |
951 | ||
952 | static void *reloc_kmap(struct drm_i915_gem_object *obj, | |
953 | struct reloc_cache *cache, | |
2889caa9 | 954 | unsigned long page) |
31a39207 | 955 | { |
d50415cc CW |
956 | void *vaddr; |
957 | ||
958 | if (cache->vaddr) { | |
959 | kunmap_atomic(unmask_page(cache->vaddr)); | |
960 | } else { | |
961 | unsigned int flushes; | |
2889caa9 | 962 | int err; |
31a39207 | 963 | |
f0e4a063 | 964 | err = i915_gem_object_prepare_write(obj, &flushes); |
2889caa9 CW |
965 | if (err) |
966 | return ERR_PTR(err); | |
d50415cc CW |
967 | |
968 | BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); | |
969 | BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); | |
3c94ceee | 970 | |
d50415cc CW |
971 | cache->vaddr = flushes | KMAP; |
972 | cache->node.mm = (void *)obj; | |
973 | if (flushes) | |
974 | mb(); | |
3c94ceee BW |
975 | } |
976 | ||
d50415cc CW |
977 | vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); |
978 | cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; | |
31a39207 | 979 | cache->page = page; |
5032d871 | 980 | |
d50415cc | 981 | return vaddr; |
5032d871 RB |
982 | } |
983 | ||
d50415cc CW |
984 | static void *reloc_iomap(struct drm_i915_gem_object *obj, |
985 | struct reloc_cache *cache, | |
2889caa9 | 986 | unsigned long page) |
5032d871 | 987 | { |
650bc635 | 988 | struct i915_ggtt *ggtt = cache_to_ggtt(cache); |
e8cb909a | 989 | unsigned long offset; |
d50415cc | 990 | void *vaddr; |
5032d871 | 991 | |
d50415cc | 992 | if (cache->vaddr) { |
576f0586 | 993 | intel_gt_flush_ggtt_writes(ggtt->vm.gt); |
615e5000 | 994 | io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); |
d50415cc CW |
995 | } else { |
996 | struct i915_vma *vma; | |
2889caa9 | 997 | int err; |
5032d871 | 998 | |
1f7fd484 CW |
999 | if (i915_gem_object_is_tiled(obj)) |
1000 | return ERR_PTR(-EINVAL); | |
1001 | ||
2889caa9 | 1002 | if (use_cpu_reloc(cache, obj)) |
d50415cc | 1003 | return NULL; |
3c94ceee | 1004 | |
6951e589 | 1005 | i915_gem_object_lock(obj); |
2889caa9 | 1006 | err = i915_gem_object_set_to_gtt_domain(obj, true); |
6951e589 | 1007 | i915_gem_object_unlock(obj); |
2889caa9 CW |
1008 | if (err) |
1009 | return ERR_PTR(err); | |
3c94ceee | 1010 | |
d50415cc | 1011 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
3c755c5b | 1012 | PIN_MAPPABLE | |
6846895f CW |
1013 | PIN_NONBLOCK /* NOWARN */ | |
1014 | PIN_NOEVICT); | |
e8cb909a CW |
1015 | if (IS_ERR(vma)) { |
1016 | memset(&cache->node, 0, sizeof(cache->node)); | |
2850748e | 1017 | mutex_lock(&ggtt->vm.mutex); |
2889caa9 | 1018 | err = drm_mm_insert_node_in_range |
82ad6443 | 1019 | (&ggtt->vm.mm, &cache->node, |
f51455d4 | 1020 | PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, |
e8cb909a | 1021 | 0, ggtt->mappable_end, |
4e64e553 | 1022 | DRM_MM_INSERT_LOW); |
2850748e | 1023 | mutex_unlock(&ggtt->vm.mutex); |
2889caa9 | 1024 | if (err) /* no inactive aperture space, use cpu reloc */ |
c92fa4fe | 1025 | return NULL; |
e8cb909a | 1026 | } else { |
e8cb909a CW |
1027 | cache->node.start = vma->node.start; |
1028 | cache->node.mm = (void *)vma; | |
3c94ceee | 1029 | } |
e8cb909a | 1030 | } |
3c94ceee | 1031 | |
e8cb909a | 1032 | offset = cache->node.start; |
b290a78b | 1033 | if (drm_mm_node_allocated(&cache->node)) { |
82ad6443 CW |
1034 | ggtt->vm.insert_page(&ggtt->vm, |
1035 | i915_gem_object_get_dma_address(obj, page), | |
1036 | offset, I915_CACHE_NONE, 0); | |
e8cb909a CW |
1037 | } else { |
1038 | offset += page << PAGE_SHIFT; | |
3c94ceee BW |
1039 | } |
1040 | ||
73ebd503 | 1041 | vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, |
650bc635 | 1042 | offset); |
d50415cc CW |
1043 | cache->page = page; |
1044 | cache->vaddr = (unsigned long)vaddr; | |
5032d871 | 1045 | |
d50415cc | 1046 | return vaddr; |
5032d871 RB |
1047 | } |
1048 | ||
d50415cc CW |
1049 | static void *reloc_vaddr(struct drm_i915_gem_object *obj, |
1050 | struct reloc_cache *cache, | |
2889caa9 | 1051 | unsigned long page) |
edf4427b | 1052 | { |
d50415cc | 1053 | void *vaddr; |
5032d871 | 1054 | |
d50415cc CW |
1055 | if (cache->page == page) { |
1056 | vaddr = unmask_page(cache->vaddr); | |
1057 | } else { | |
1058 | vaddr = NULL; | |
1059 | if ((cache->vaddr & KMAP) == 0) | |
1060 | vaddr = reloc_iomap(obj, cache, page); | |
1061 | if (!vaddr) | |
1062 | vaddr = reloc_kmap(obj, cache, page); | |
3c94ceee BW |
1063 | } |
1064 | ||
d50415cc | 1065 | return vaddr; |
edf4427b CW |
1066 | } |
1067 | ||
d50415cc | 1068 | static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) |
edf4427b | 1069 | { |
d50415cc CW |
1070 | if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { |
1071 | if (flushes & CLFLUSH_BEFORE) { | |
1072 | clflushopt(addr); | |
1073 | mb(); | |
1074 | } | |
edf4427b | 1075 | |
d50415cc | 1076 | *addr = value; |
edf4427b | 1077 | |
2889caa9 CW |
1078 | /* |
1079 | * Writes to the same cacheline are serialised by the CPU | |
d50415cc CW |
1080 | * (including clflush). On the write path, we only require |
1081 | * that it hits memory in an orderly fashion and place | |
1082 | * mb barriers at the start and end of the relocation phase | |
1083 | * to ensure ordering of clflush wrt to the system. | |
1084 | */ | |
1085 | if (flushes & CLFLUSH_AFTER) | |
1086 | clflushopt(addr); | |
1087 | } else | |
1088 | *addr = value; | |
edf4427b | 1089 | } |
edf4427b | 1090 | |
6951e589 CW |
1091 | static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) |
1092 | { | |
1093 | struct drm_i915_gem_object *obj = vma->obj; | |
1094 | int err; | |
1095 | ||
1096 | i915_vma_lock(vma); | |
1097 | ||
1098 | if (obj->cache_dirty & ~obj->cache_coherent) | |
1099 | i915_gem_clflush_object(obj, 0); | |
1100 | obj->write_domain = 0; | |
1101 | ||
1102 | err = i915_request_await_object(rq, vma->obj, true); | |
1103 | if (err == 0) | |
1104 | err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); | |
1105 | ||
1106 | i915_vma_unlock(vma); | |
1107 | ||
1108 | return err; | |
1109 | } | |
1110 | ||
7dd4f672 CW |
1111 | static int __reloc_gpu_alloc(struct i915_execbuffer *eb, |
1112 | struct i915_vma *vma, | |
1113 | unsigned int len) | |
1114 | { | |
1115 | struct reloc_cache *cache = &eb->reloc_cache; | |
b40d7378 | 1116 | struct intel_engine_pool_node *pool; |
e61e0f51 | 1117 | struct i915_request *rq; |
7dd4f672 CW |
1118 | struct i915_vma *batch; |
1119 | u32 *cmd; | |
1120 | int err; | |
1121 | ||
cccdce1d | 1122 | pool = intel_engine_get_pool(eb->engine, PAGE_SIZE); |
b40d7378 CW |
1123 | if (IS_ERR(pool)) |
1124 | return PTR_ERR(pool); | |
7dd4f672 | 1125 | |
b40d7378 | 1126 | cmd = i915_gem_object_pin_map(pool->obj, |
a575c676 CW |
1127 | cache->has_llc ? |
1128 | I915_MAP_FORCE_WB : | |
1129 | I915_MAP_FORCE_WC); | |
b40d7378 CW |
1130 | if (IS_ERR(cmd)) { |
1131 | err = PTR_ERR(cmd); | |
1132 | goto out_pool; | |
1133 | } | |
7dd4f672 | 1134 | |
b40d7378 | 1135 | batch = i915_vma_instance(pool->obj, vma->vm, NULL); |
7dd4f672 CW |
1136 | if (IS_ERR(batch)) { |
1137 | err = PTR_ERR(batch); | |
1138 | goto err_unmap; | |
1139 | } | |
1140 | ||
1141 | err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK); | |
1142 | if (err) | |
1143 | goto err_unmap; | |
1144 | ||
d92f77de | 1145 | rq = i915_request_create(eb->context); |
7dd4f672 CW |
1146 | if (IS_ERR(rq)) { |
1147 | err = PTR_ERR(rq); | |
1148 | goto err_unpin; | |
1149 | } | |
1150 | ||
b40d7378 CW |
1151 | err = intel_engine_pool_mark_active(pool, rq); |
1152 | if (err) | |
1153 | goto err_request; | |
1154 | ||
6951e589 | 1155 | err = reloc_move_to_gpu(rq, vma); |
7dd4f672 CW |
1156 | if (err) |
1157 | goto err_request; | |
1158 | ||
7dd4f672 CW |
1159 | err = eb->engine->emit_bb_start(rq, |
1160 | batch->node.start, PAGE_SIZE, | |
1161 | cache->gen > 5 ? 0 : I915_DISPATCH_SECURE); | |
1162 | if (err) | |
6951e589 | 1163 | goto skip_request; |
7dd4f672 | 1164 | |
6951e589 | 1165 | i915_vma_lock(batch); |
70d6894d CW |
1166 | err = i915_request_await_object(rq, batch->obj, false); |
1167 | if (err == 0) | |
1168 | err = i915_vma_move_to_active(batch, rq, 0); | |
6951e589 | 1169 | i915_vma_unlock(batch); |
a5236978 CW |
1170 | if (err) |
1171 | goto skip_request; | |
7dd4f672 CW |
1172 | |
1173 | rq->batch = batch; | |
a5236978 | 1174 | i915_vma_unpin(batch); |
7dd4f672 CW |
1175 | |
1176 | cache->rq = rq; | |
1177 | cache->rq_cmd = cmd; | |
1178 | cache->rq_size = 0; | |
1179 | ||
1180 | /* Return with batch mapping (cmd) still pinned */ | |
b40d7378 | 1181 | goto out_pool; |
7dd4f672 | 1182 | |
a5236978 | 1183 | skip_request: |
36e191f0 | 1184 | i915_request_set_error_once(rq, err); |
7dd4f672 | 1185 | err_request: |
e61e0f51 | 1186 | i915_request_add(rq); |
7dd4f672 CW |
1187 | err_unpin: |
1188 | i915_vma_unpin(batch); | |
1189 | err_unmap: | |
b40d7378 CW |
1190 | i915_gem_object_unpin_map(pool->obj); |
1191 | out_pool: | |
1192 | intel_engine_pool_put(pool); | |
7dd4f672 CW |
1193 | return err; |
1194 | } | |
1195 | ||
1196 | static u32 *reloc_gpu(struct i915_execbuffer *eb, | |
1197 | struct i915_vma *vma, | |
1198 | unsigned int len) | |
1199 | { | |
1200 | struct reloc_cache *cache = &eb->reloc_cache; | |
1201 | u32 *cmd; | |
1202 | ||
1203 | if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1)) | |
1204 | reloc_gpu_flush(cache); | |
1205 | ||
1206 | if (unlikely(!cache->rq)) { | |
1207 | int err; | |
1208 | ||
90cad095 CW |
1209 | if (!intel_engine_can_store_dword(eb->engine)) |
1210 | return ERR_PTR(-ENODEV); | |
1211 | ||
7dd4f672 CW |
1212 | err = __reloc_gpu_alloc(eb, vma, len); |
1213 | if (unlikely(err)) | |
1214 | return ERR_PTR(err); | |
1215 | } | |
1216 | ||
1217 | cmd = cache->rq_cmd + cache->rq_size; | |
1218 | cache->rq_size += len; | |
1219 | ||
1220 | return cmd; | |
1221 | } | |
1222 | ||
2889caa9 CW |
1223 | static u64 |
1224 | relocate_entry(struct i915_vma *vma, | |
d50415cc | 1225 | const struct drm_i915_gem_relocation_entry *reloc, |
2889caa9 CW |
1226 | struct i915_execbuffer *eb, |
1227 | const struct i915_vma *target) | |
edf4427b | 1228 | { |
d50415cc | 1229 | u64 offset = reloc->offset; |
2889caa9 CW |
1230 | u64 target_offset = relocation_target(reloc, target); |
1231 | bool wide = eb->reloc_cache.use_64bit_reloc; | |
d50415cc | 1232 | void *vaddr; |
edf4427b | 1233 | |
7dd4f672 CW |
1234 | if (!eb->reloc_cache.vaddr && |
1235 | (DBG_FORCE_RELOC == FORCE_GPU_RELOC || | |
52791eee | 1236 | !dma_resv_test_signaled_rcu(vma->resv, true))) { |
7dd4f672 CW |
1237 | const unsigned int gen = eb->reloc_cache.gen; |
1238 | unsigned int len; | |
1239 | u32 *batch; | |
1240 | u64 addr; | |
1241 | ||
1242 | if (wide) | |
1243 | len = offset & 7 ? 8 : 5; | |
1244 | else if (gen >= 4) | |
1245 | len = 4; | |
f2f5c061 | 1246 | else |
a889580c | 1247 | len = 3; |
7dd4f672 CW |
1248 | |
1249 | batch = reloc_gpu(eb, vma, len); | |
1250 | if (IS_ERR(batch)) | |
1251 | goto repeat; | |
1252 | ||
1253 | addr = gen8_canonical_addr(vma->node.start + offset); | |
1254 | if (wide) { | |
1255 | if (offset & 7) { | |
1256 | *batch++ = MI_STORE_DWORD_IMM_GEN4; | |
1257 | *batch++ = lower_32_bits(addr); | |
1258 | *batch++ = upper_32_bits(addr); | |
1259 | *batch++ = lower_32_bits(target_offset); | |
1260 | ||
1261 | addr = gen8_canonical_addr(addr + 4); | |
1262 | ||
1263 | *batch++ = MI_STORE_DWORD_IMM_GEN4; | |
1264 | *batch++ = lower_32_bits(addr); | |
1265 | *batch++ = upper_32_bits(addr); | |
1266 | *batch++ = upper_32_bits(target_offset); | |
1267 | } else { | |
1268 | *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1; | |
1269 | *batch++ = lower_32_bits(addr); | |
1270 | *batch++ = upper_32_bits(addr); | |
1271 | *batch++ = lower_32_bits(target_offset); | |
1272 | *batch++ = upper_32_bits(target_offset); | |
1273 | } | |
1274 | } else if (gen >= 6) { | |
1275 | *batch++ = MI_STORE_DWORD_IMM_GEN4; | |
1276 | *batch++ = 0; | |
1277 | *batch++ = addr; | |
1278 | *batch++ = target_offset; | |
1279 | } else if (gen >= 4) { | |
1280 | *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; | |
1281 | *batch++ = 0; | |
1282 | *batch++ = addr; | |
1283 | *batch++ = target_offset; | |
1284 | } else { | |
1285 | *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
1286 | *batch++ = addr; | |
1287 | *batch++ = target_offset; | |
1288 | } | |
1289 | ||
1290 | goto out; | |
1291 | } | |
1292 | ||
d50415cc | 1293 | repeat: |
95ff7c7d | 1294 | vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT); |
d50415cc CW |
1295 | if (IS_ERR(vaddr)) |
1296 | return PTR_ERR(vaddr); | |
1297 | ||
1298 | clflush_write32(vaddr + offset_in_page(offset), | |
1299 | lower_32_bits(target_offset), | |
2889caa9 | 1300 | eb->reloc_cache.vaddr); |
d50415cc CW |
1301 | |
1302 | if (wide) { | |
1303 | offset += sizeof(u32); | |
1304 | target_offset >>= 32; | |
1305 | wide = false; | |
1306 | goto repeat; | |
edf4427b | 1307 | } |
edf4427b | 1308 | |
7dd4f672 | 1309 | out: |
2889caa9 | 1310 | return target->node.start | UPDATE; |
edf4427b | 1311 | } |
edf4427b | 1312 | |
2889caa9 CW |
1313 | static u64 |
1314 | eb_relocate_entry(struct i915_execbuffer *eb, | |
7d6236bb | 1315 | struct eb_vma *ev, |
2889caa9 | 1316 | const struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc | 1317 | { |
baa89ba3 | 1318 | struct drm_i915_private *i915 = eb->i915; |
7d6236bb | 1319 | struct eb_vma *target; |
2889caa9 | 1320 | int err; |
54cf91dc | 1321 | |
67731b87 | 1322 | /* we've already hold a reference to all valid objects */ |
507d977f CW |
1323 | target = eb_get_vma(eb, reloc->target_handle); |
1324 | if (unlikely(!target)) | |
54cf91dc | 1325 | return -ENOENT; |
e844b990 | 1326 | |
54cf91dc | 1327 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 1328 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
baa89ba3 | 1329 | drm_dbg(&i915->drm, "reloc with multiple write domains: " |
507d977f | 1330 | "target %d offset %d " |
54cf91dc | 1331 | "read %08x write %08x", |
507d977f | 1332 | reloc->target_handle, |
54cf91dc CW |
1333 | (int) reloc->offset, |
1334 | reloc->read_domains, | |
1335 | reloc->write_domain); | |
8b78f0e5 | 1336 | return -EINVAL; |
54cf91dc | 1337 | } |
4ca4a250 DV |
1338 | if (unlikely((reloc->write_domain | reloc->read_domains) |
1339 | & ~I915_GEM_GPU_DOMAINS)) { | |
baa89ba3 | 1340 | drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: " |
507d977f | 1341 | "target %d offset %d " |
54cf91dc | 1342 | "read %08x write %08x", |
507d977f | 1343 | reloc->target_handle, |
54cf91dc CW |
1344 | (int) reloc->offset, |
1345 | reloc->read_domains, | |
1346 | reloc->write_domain); | |
8b78f0e5 | 1347 | return -EINVAL; |
54cf91dc | 1348 | } |
54cf91dc | 1349 | |
2889caa9 | 1350 | if (reloc->write_domain) { |
7d6236bb | 1351 | target->flags |= EXEC_OBJECT_WRITE; |
507d977f | 1352 | |
2889caa9 CW |
1353 | /* |
1354 | * Sandybridge PPGTT errata: We need a global gtt mapping | |
1355 | * for MI and pipe_control writes because the gpu doesn't | |
1356 | * properly redirect them through the ppgtt for non_secure | |
1357 | * batchbuffers. | |
1358 | */ | |
1359 | if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
cf819eff | 1360 | IS_GEN(eb->i915, 6)) { |
7d6236bb CW |
1361 | err = i915_vma_bind(target->vma, |
1362 | target->vma->obj->cache_level, | |
2850748e | 1363 | PIN_GLOBAL, NULL); |
2889caa9 CW |
1364 | if (WARN_ONCE(err, |
1365 | "Unexpected failure to bind target VMA!")) | |
1366 | return err; | |
1367 | } | |
507d977f | 1368 | } |
54cf91dc | 1369 | |
2889caa9 CW |
1370 | /* |
1371 | * If the relocation already has the right value in it, no | |
54cf91dc CW |
1372 | * more work needs to be done. |
1373 | */ | |
7dd4f672 | 1374 | if (!DBG_FORCE_RELOC && |
7d6236bb | 1375 | gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) |
67731b87 | 1376 | return 0; |
54cf91dc CW |
1377 | |
1378 | /* Check that the relocation address is valid... */ | |
3c94ceee | 1379 | if (unlikely(reloc->offset > |
7d6236bb | 1380 | ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) { |
baa89ba3 | 1381 | drm_dbg(&i915->drm, "Relocation beyond object bounds: " |
507d977f CW |
1382 | "target %d offset %d size %d.\n", |
1383 | reloc->target_handle, | |
1384 | (int)reloc->offset, | |
7d6236bb | 1385 | (int)ev->vma->size); |
8b78f0e5 | 1386 | return -EINVAL; |
54cf91dc | 1387 | } |
b8f7ab17 | 1388 | if (unlikely(reloc->offset & 3)) { |
baa89ba3 | 1389 | drm_dbg(&i915->drm, "Relocation not 4-byte aligned: " |
507d977f CW |
1390 | "target %d offset %d.\n", |
1391 | reloc->target_handle, | |
1392 | (int)reloc->offset); | |
8b78f0e5 | 1393 | return -EINVAL; |
54cf91dc CW |
1394 | } |
1395 | ||
071750e5 CW |
1396 | /* |
1397 | * If we write into the object, we need to force the synchronisation | |
1398 | * barrier, either with an asynchronous clflush or if we executed the | |
1399 | * patching using the GPU (though that should be serialised by the | |
1400 | * timeline). To be completely sure, and since we are required to | |
1401 | * do relocations we are already stalling, disable the user's opt | |
0519bcb1 | 1402 | * out of our synchronisation. |
071750e5 | 1403 | */ |
7d6236bb | 1404 | ev->flags &= ~EXEC_OBJECT_ASYNC; |
071750e5 | 1405 | |
54cf91dc | 1406 | /* and update the user's relocation entry */ |
7d6236bb | 1407 | return relocate_entry(ev->vma, reloc, eb, target->vma); |
54cf91dc CW |
1408 | } |
1409 | ||
7d6236bb | 1410 | static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) |
54cf91dc | 1411 | { |
1d83f442 | 1412 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
2889caa9 CW |
1413 | struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; |
1414 | struct drm_i915_gem_relocation_entry __user *urelocs; | |
7d6236bb | 1415 | const struct drm_i915_gem_exec_object2 *entry = ev->exec; |
2889caa9 | 1416 | unsigned int remain; |
54cf91dc | 1417 | |
2889caa9 | 1418 | urelocs = u64_to_user_ptr(entry->relocs_ptr); |
1d83f442 | 1419 | remain = entry->relocation_count; |
2889caa9 CW |
1420 | if (unlikely(remain > N_RELOC(ULONG_MAX))) |
1421 | return -EINVAL; | |
ebc0808f | 1422 | |
2889caa9 CW |
1423 | /* |
1424 | * We must check that the entire relocation array is safe | |
1425 | * to read. However, if the array is not writable the user loses | |
1426 | * the updated relocation values. | |
1427 | */ | |
96d4f267 | 1428 | if (unlikely(!access_ok(urelocs, remain*sizeof(*urelocs)))) |
2889caa9 CW |
1429 | return -EFAULT; |
1430 | ||
1431 | do { | |
1432 | struct drm_i915_gem_relocation_entry *r = stack; | |
1433 | unsigned int count = | |
1434 | min_t(unsigned int, remain, ARRAY_SIZE(stack)); | |
1435 | unsigned int copied; | |
1d83f442 | 1436 | |
2889caa9 CW |
1437 | /* |
1438 | * This is the fast path and we cannot handle a pagefault | |
ebc0808f CW |
1439 | * whilst holding the struct mutex lest the user pass in the |
1440 | * relocations contained within a mmaped bo. For in such a case | |
1441 | * we, the page fault handler would call i915_gem_fault() and | |
1442 | * we would try to acquire the struct mutex again. Obviously | |
1443 | * this is bad and so lockdep complains vehemently. | |
1444 | */ | |
7dc8f114 | 1445 | copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); |
2889caa9 CW |
1446 | if (unlikely(copied)) { |
1447 | remain = -EFAULT; | |
31a39207 CW |
1448 | goto out; |
1449 | } | |
54cf91dc | 1450 | |
2889caa9 | 1451 | remain -= count; |
1d83f442 | 1452 | do { |
7d6236bb | 1453 | u64 offset = eb_relocate_entry(eb, ev, r); |
54cf91dc | 1454 | |
2889caa9 CW |
1455 | if (likely(offset == 0)) { |
1456 | } else if ((s64)offset < 0) { | |
1457 | remain = (int)offset; | |
31a39207 | 1458 | goto out; |
2889caa9 CW |
1459 | } else { |
1460 | /* | |
1461 | * Note that reporting an error now | |
1462 | * leaves everything in an inconsistent | |
1463 | * state as we have *already* changed | |
1464 | * the relocation value inside the | |
1465 | * object. As we have not changed the | |
1466 | * reloc.presumed_offset or will not | |
1467 | * change the execobject.offset, on the | |
1468 | * call we may not rewrite the value | |
1469 | * inside the object, leaving it | |
1470 | * dangling and causing a GPU hang. Unless | |
1471 | * userspace dynamically rebuilds the | |
1472 | * relocations on each execbuf rather than | |
1473 | * presume a static tree. | |
1474 | * | |
1475 | * We did previously check if the relocations | |
1476 | * were writable (access_ok), an error now | |
1477 | * would be a strange race with mprotect, | |
1478 | * having already demonstrated that we | |
1479 | * can read from this userspace address. | |
1480 | */ | |
1481 | offset = gen8_canonical_addr(offset & ~UPDATE); | |
721017cf CW |
1482 | __put_user(offset, |
1483 | &urelocs[r - stack].presumed_offset); | |
1d83f442 | 1484 | } |
2889caa9 CW |
1485 | } while (r++, --count); |
1486 | urelocs += ARRAY_SIZE(stack); | |
1487 | } while (remain); | |
31a39207 | 1488 | out: |
650bc635 | 1489 | reloc_cache_reset(&eb->reloc_cache); |
2889caa9 | 1490 | return remain; |
54cf91dc CW |
1491 | } |
1492 | ||
2889caa9 | 1493 | static int eb_relocate(struct i915_execbuffer *eb) |
54cf91dc | 1494 | { |
003d8b91 CW |
1495 | int err; |
1496 | ||
1497 | mutex_lock(&eb->gem_context->mutex); | |
1498 | err = eb_lookup_vmas(eb); | |
1499 | mutex_unlock(&eb->gem_context->mutex); | |
1500 | if (err) | |
1501 | return err; | |
1502 | ||
ef398881 CW |
1503 | if (!list_empty(&eb->unbound)) { |
1504 | err = eb_reserve(eb); | |
1505 | if (err) | |
1506 | return err; | |
1507 | } | |
2889caa9 CW |
1508 | |
1509 | /* The objects are in their final locations, apply the relocations. */ | |
1510 | if (eb->args->flags & __EXEC_HAS_RELOC) { | |
7d6236bb | 1511 | struct eb_vma *ev; |
2889caa9 | 1512 | |
7d6236bb | 1513 | list_for_each_entry(ev, &eb->relocs, reloc_link) { |
7dc8f114 CW |
1514 | err = eb_relocate_vma(eb, ev); |
1515 | if (err) | |
1516 | return err; | |
2889caa9 CW |
1517 | } |
1518 | } | |
1519 | ||
1520 | return 0; | |
2889caa9 CW |
1521 | } |
1522 | ||
2889caa9 CW |
1523 | static int eb_move_to_gpu(struct i915_execbuffer *eb) |
1524 | { | |
1525 | const unsigned int count = eb->buffer_count; | |
6951e589 | 1526 | struct ww_acquire_ctx acquire; |
2889caa9 | 1527 | unsigned int i; |
6951e589 CW |
1528 | int err = 0; |
1529 | ||
1530 | ww_acquire_init(&acquire, &reservation_ww_class); | |
54cf91dc | 1531 | |
2889caa9 | 1532 | for (i = 0; i < count; i++) { |
7d6236bb CW |
1533 | struct eb_vma *ev = &eb->vma[i]; |
1534 | struct i915_vma *vma = ev->vma; | |
6951e589 CW |
1535 | |
1536 | err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); | |
6951e589 CW |
1537 | if (err == -EDEADLK) { |
1538 | GEM_BUG_ON(i == 0); | |
1539 | do { | |
1540 | int j = i - 1; | |
1541 | ||
7d6236bb | 1542 | ww_mutex_unlock(&eb->vma[j].vma->resv->lock); |
6951e589 | 1543 | |
6951e589 | 1544 | swap(eb->vma[i], eb->vma[j]); |
6951e589 | 1545 | } while (--i); |
6951e589 CW |
1546 | |
1547 | err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, | |
1548 | &acquire); | |
1549 | } | |
1550 | if (err) | |
1551 | break; | |
1552 | } | |
1553 | ww_acquire_done(&acquire); | |
1554 | ||
1555 | while (i--) { | |
7d6236bb CW |
1556 | struct eb_vma *ev = &eb->vma[i]; |
1557 | struct i915_vma *vma = ev->vma; | |
1558 | unsigned int flags = ev->flags; | |
27173f1f | 1559 | struct drm_i915_gem_object *obj = vma->obj; |
03ade511 | 1560 | |
6951e589 CW |
1561 | assert_vma_held(vma); |
1562 | ||
c7c6e46f | 1563 | if (flags & EXEC_OBJECT_CAPTURE) { |
e61e0f51 | 1564 | struct i915_capture_list *capture; |
b0fd47ad CW |
1565 | |
1566 | capture = kmalloc(sizeof(*capture), GFP_KERNEL); | |
6951e589 CW |
1567 | if (capture) { |
1568 | capture->next = eb->request->capture_list; | |
1569 | capture->vma = vma; | |
1570 | eb->request->capture_list = capture; | |
1571 | } | |
b0fd47ad CW |
1572 | } |
1573 | ||
b8f55be6 CW |
1574 | /* |
1575 | * If the GPU is not _reading_ through the CPU cache, we need | |
1576 | * to make sure that any writes (both previous GPU writes from | |
1577 | * before a change in snooping levels and normal CPU writes) | |
1578 | * caught in that cache are flushed to main memory. | |
1579 | * | |
1580 | * We want to say | |
1581 | * obj->cache_dirty && | |
1582 | * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) | |
1583 | * but gcc's optimiser doesn't handle that as well and emits | |
1584 | * two jumps instead of one. Maybe one day... | |
1585 | */ | |
1586 | if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) { | |
0f46daa1 | 1587 | if (i915_gem_clflush_object(obj, 0)) |
c7c6e46f | 1588 | flags &= ~EXEC_OBJECT_ASYNC; |
0f46daa1 CW |
1589 | } |
1590 | ||
6951e589 CW |
1591 | if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) { |
1592 | err = i915_request_await_object | |
1593 | (eb->request, obj, flags & EXEC_OBJECT_WRITE); | |
1594 | } | |
2889caa9 | 1595 | |
6951e589 CW |
1596 | if (err == 0) |
1597 | err = i915_vma_move_to_active(vma, eb->request, flags); | |
c7c6e46f | 1598 | |
6951e589 | 1599 | i915_vma_unlock(vma); |
2889caa9 | 1600 | |
c7c6e46f | 1601 | __eb_unreserve_vma(vma, flags); |
003d8b91 | 1602 | i915_vma_put(vma); |
7d6236bb CW |
1603 | |
1604 | ev->vma = NULL; | |
c59a333f | 1605 | } |
6951e589 CW |
1606 | ww_acquire_fini(&acquire); |
1607 | ||
1608 | if (unlikely(err)) | |
1609 | goto err_skip; | |
1610 | ||
2889caa9 | 1611 | eb->exec = NULL; |
c59a333f | 1612 | |
dcd79934 | 1613 | /* Unconditionally flush any chipset caches (for streaming writes). */ |
baea429d | 1614 | intel_gt_chipset_flush(eb->engine->gt); |
2113184c | 1615 | return 0; |
6951e589 CW |
1616 | |
1617 | err_skip: | |
36e191f0 | 1618 | i915_request_set_error_once(eb->request, err); |
6951e589 | 1619 | return err; |
54cf91dc CW |
1620 | } |
1621 | ||
00aff3f6 | 1622 | static int i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) |
54cf91dc | 1623 | { |
650bc635 | 1624 | if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS) |
00aff3f6 | 1625 | return -EINVAL; |
ed5982e6 | 1626 | |
2f5945bc | 1627 | /* Kernel clipping was a DRI1 misfeature */ |
cf6e7bac JE |
1628 | if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) { |
1629 | if (exec->num_cliprects || exec->cliprects_ptr) | |
00aff3f6 | 1630 | return -EINVAL; |
cf6e7bac | 1631 | } |
2f5945bc CW |
1632 | |
1633 | if (exec->DR4 == 0xffffffff) { | |
1634 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1635 | exec->DR4 = 0; | |
1636 | } | |
1637 | if (exec->DR1 || exec->DR4) | |
00aff3f6 | 1638 | return -EINVAL; |
2f5945bc CW |
1639 | |
1640 | if ((exec->batch_start_offset | exec->batch_len) & 0x7) | |
00aff3f6 | 1641 | return -EINVAL; |
2f5945bc | 1642 | |
00aff3f6 | 1643 | return 0; |
54cf91dc CW |
1644 | } |
1645 | ||
e61e0f51 | 1646 | static int i915_reset_gen7_sol_offsets(struct i915_request *rq) |
ae662d31 | 1647 | { |
73dec95e TU |
1648 | u32 *cs; |
1649 | int i; | |
ae662d31 | 1650 | |
8a68d464 | 1651 | if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) { |
d0bf4582 | 1652 | drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n"); |
9d662da8 DV |
1653 | return -EINVAL; |
1654 | } | |
ae662d31 | 1655 | |
e61e0f51 | 1656 | cs = intel_ring_begin(rq, 4 * 2 + 2); |
73dec95e TU |
1657 | if (IS_ERR(cs)) |
1658 | return PTR_ERR(cs); | |
ae662d31 | 1659 | |
2889caa9 | 1660 | *cs++ = MI_LOAD_REGISTER_IMM(4); |
ae662d31 | 1661 | for (i = 0; i < 4; i++) { |
73dec95e TU |
1662 | *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); |
1663 | *cs++ = 0; | |
ae662d31 | 1664 | } |
2889caa9 | 1665 | *cs++ = MI_NOOP; |
e61e0f51 | 1666 | intel_ring_advance(rq, cs); |
ae662d31 EA |
1667 | |
1668 | return 0; | |
1669 | } | |
1670 | ||
4f7af194 | 1671 | static struct i915_vma * |
32d94048 CW |
1672 | shadow_batch_pin(struct drm_i915_gem_object *obj, |
1673 | struct i915_address_space *vm, | |
1674 | unsigned int flags) | |
4f7af194 | 1675 | { |
b291ce0a | 1676 | struct i915_vma *vma; |
b291ce0a | 1677 | int err; |
4f7af194 | 1678 | |
b291ce0a CW |
1679 | vma = i915_vma_instance(obj, vm, NULL); |
1680 | if (IS_ERR(vma)) | |
1681 | return vma; | |
1682 | ||
1683 | err = i915_vma_pin(vma, 0, 0, flags); | |
1684 | if (err) | |
1685 | return ERR_PTR(err); | |
1686 | ||
1687 | return vma; | |
4f7af194 JB |
1688 | } |
1689 | ||
686c7c35 CW |
1690 | struct eb_parse_work { |
1691 | struct dma_fence_work base; | |
1692 | struct intel_engine_cs *engine; | |
1693 | struct i915_vma *batch; | |
1694 | struct i915_vma *shadow; | |
1695 | struct i915_vma *trampoline; | |
1696 | unsigned int batch_offset; | |
1697 | unsigned int batch_length; | |
1698 | }; | |
1699 | ||
1700 | static int __eb_parse(struct dma_fence_work *work) | |
1701 | { | |
1702 | struct eb_parse_work *pw = container_of(work, typeof(*pw), base); | |
1703 | ||
1704 | return intel_engine_cmd_parser(pw->engine, | |
1705 | pw->batch, | |
1706 | pw->batch_offset, | |
1707 | pw->batch_length, | |
1708 | pw->shadow, | |
1709 | pw->trampoline); | |
1710 | } | |
1711 | ||
36c8e356 CW |
1712 | static void __eb_parse_release(struct dma_fence_work *work) |
1713 | { | |
1714 | struct eb_parse_work *pw = container_of(work, typeof(*pw), base); | |
1715 | ||
1716 | if (pw->trampoline) | |
1717 | i915_active_release(&pw->trampoline->active); | |
1718 | i915_active_release(&pw->shadow->active); | |
1719 | i915_active_release(&pw->batch->active); | |
1720 | } | |
1721 | ||
686c7c35 CW |
1722 | static const struct dma_fence_work_ops eb_parse_ops = { |
1723 | .name = "eb_parse", | |
1724 | .work = __eb_parse, | |
36c8e356 | 1725 | .release = __eb_parse_release, |
686c7c35 CW |
1726 | }; |
1727 | ||
1728 | static int eb_parse_pipeline(struct i915_execbuffer *eb, | |
1729 | struct i915_vma *shadow, | |
1730 | struct i915_vma *trampoline) | |
1731 | { | |
1732 | struct eb_parse_work *pw; | |
1733 | int err; | |
1734 | ||
1735 | pw = kzalloc(sizeof(*pw), GFP_KERNEL); | |
1736 | if (!pw) | |
1737 | return -ENOMEM; | |
1738 | ||
7d6236bb | 1739 | err = i915_active_acquire(&eb->batch->vma->active); |
36c8e356 CW |
1740 | if (err) |
1741 | goto err_free; | |
1742 | ||
1743 | err = i915_active_acquire(&shadow->active); | |
1744 | if (err) | |
1745 | goto err_batch; | |
1746 | ||
1747 | if (trampoline) { | |
1748 | err = i915_active_acquire(&trampoline->active); | |
1749 | if (err) | |
1750 | goto err_shadow; | |
1751 | } | |
1752 | ||
686c7c35 CW |
1753 | dma_fence_work_init(&pw->base, &eb_parse_ops); |
1754 | ||
1755 | pw->engine = eb->engine; | |
7d6236bb | 1756 | pw->batch = eb->batch->vma; |
686c7c35 CW |
1757 | pw->batch_offset = eb->batch_start_offset; |
1758 | pw->batch_length = eb->batch_len; | |
1759 | pw->shadow = shadow; | |
1760 | pw->trampoline = trampoline; | |
1761 | ||
36c8e356 CW |
1762 | err = dma_resv_lock_interruptible(pw->batch->resv, NULL); |
1763 | if (err) | |
1764 | goto err_trampoline; | |
686c7c35 CW |
1765 | |
1766 | err = dma_resv_reserve_shared(pw->batch->resv, 1); | |
1767 | if (err) | |
1768 | goto err_batch_unlock; | |
1769 | ||
1770 | /* Wait for all writes (and relocs) into the batch to complete */ | |
1771 | err = i915_sw_fence_await_reservation(&pw->base.chain, | |
1772 | pw->batch->resv, NULL, false, | |
1773 | 0, I915_FENCE_GFP); | |
1774 | if (err < 0) | |
1775 | goto err_batch_unlock; | |
1776 | ||
1777 | /* Keep the batch alive and unwritten as we parse */ | |
1778 | dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma); | |
1779 | ||
1780 | dma_resv_unlock(pw->batch->resv); | |
1781 | ||
1782 | /* Force execution to wait for completion of the parser */ | |
1783 | dma_resv_lock(shadow->resv, NULL); | |
1784 | dma_resv_add_excl_fence(shadow->resv, &pw->base.dma); | |
1785 | dma_resv_unlock(shadow->resv); | |
1786 | ||
1787 | dma_fence_work_commit(&pw->base); | |
1788 | return 0; | |
1789 | ||
1790 | err_batch_unlock: | |
1791 | dma_resv_unlock(pw->batch->resv); | |
36c8e356 CW |
1792 | err_trampoline: |
1793 | if (trampoline) | |
1794 | i915_active_release(&trampoline->active); | |
1795 | err_shadow: | |
1796 | i915_active_release(&shadow->active); | |
1797 | err_batch: | |
7d6236bb | 1798 | i915_active_release(&eb->batch->vma->active); |
36c8e356 | 1799 | err_free: |
686c7c35 CW |
1800 | kfree(pw); |
1801 | return err; | |
1802 | } | |
1803 | ||
51696691 | 1804 | static int eb_parse(struct i915_execbuffer *eb) |
71745376 | 1805 | { |
baa89ba3 | 1806 | struct drm_i915_private *i915 = eb->i915; |
b40d7378 | 1807 | struct intel_engine_pool_node *pool; |
32d94048 CW |
1808 | struct i915_vma *shadow, *trampoline; |
1809 | unsigned int len; | |
2889caa9 | 1810 | int err; |
71745376 | 1811 | |
51696691 CW |
1812 | if (!eb_use_cmdparser(eb)) |
1813 | return 0; | |
1814 | ||
32d94048 CW |
1815 | len = eb->batch_len; |
1816 | if (!CMDPARSER_USES_GGTT(eb->i915)) { | |
1817 | /* | |
1818 | * ppGTT backed shadow buffers must be mapped RO, to prevent | |
1819 | * post-scan tampering | |
1820 | */ | |
1821 | if (!eb->context->vm->has_read_only) { | |
baa89ba3 WK |
1822 | drm_dbg(&i915->drm, |
1823 | "Cannot prevent post-scan tampering without RO capable vm\n"); | |
32d94048 CW |
1824 | return -EINVAL; |
1825 | } | |
1826 | } else { | |
1827 | len += I915_CMD_PARSER_TRAMPOLINE_SIZE; | |
1828 | } | |
1829 | ||
1830 | pool = intel_engine_get_pool(eb->engine, len); | |
b40d7378 | 1831 | if (IS_ERR(pool)) |
51696691 | 1832 | return PTR_ERR(pool); |
71745376 | 1833 | |
32d94048 CW |
1834 | shadow = shadow_batch_pin(pool->obj, eb->context->vm, PIN_USER); |
1835 | if (IS_ERR(shadow)) { | |
1836 | err = PTR_ERR(shadow); | |
f8c08d8f | 1837 | goto err; |
51696691 | 1838 | } |
32d94048 CW |
1839 | i915_gem_object_set_readonly(shadow->obj); |
1840 | ||
1841 | trampoline = NULL; | |
1842 | if (CMDPARSER_USES_GGTT(eb->i915)) { | |
1843 | trampoline = shadow; | |
1844 | ||
1845 | shadow = shadow_batch_pin(pool->obj, | |
1846 | &eb->engine->gt->ggtt->vm, | |
1847 | PIN_GLOBAL); | |
1848 | if (IS_ERR(shadow)) { | |
1849 | err = PTR_ERR(shadow); | |
1850 | shadow = trampoline; | |
1851 | goto err_shadow; | |
1852 | } | |
1853 | ||
1854 | eb->batch_flags |= I915_DISPATCH_SECURE; | |
1855 | } | |
f8c08d8f | 1856 | |
686c7c35 | 1857 | err = eb_parse_pipeline(eb, shadow, trampoline); |
32d94048 CW |
1858 | if (err) |
1859 | goto err_trampoline; | |
71745376 | 1860 | |
7d6236bb | 1861 | eb->vma[eb->buffer_count].vma = i915_vma_get(shadow); |
003d8b91 | 1862 | eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN; |
7d6236bb | 1863 | eb->batch = &eb->vma[eb->buffer_count++]; |
71745376 | 1864 | |
32d94048 | 1865 | eb->trampoline = trampoline; |
4f7af194 | 1866 | eb->batch_start_offset = 0; |
4f7af194 | 1867 | |
32d94048 | 1868 | shadow->private = pool; |
51696691 | 1869 | return 0; |
b40d7378 | 1870 | |
32d94048 CW |
1871 | err_trampoline: |
1872 | if (trampoline) | |
1873 | i915_vma_unpin(trampoline); | |
1874 | err_shadow: | |
1875 | i915_vma_unpin(shadow); | |
b40d7378 CW |
1876 | err: |
1877 | intel_engine_pool_put(pool); | |
51696691 | 1878 | return err; |
71745376 | 1879 | } |
5c6c6003 | 1880 | |
c8659efa | 1881 | static void |
e61e0f51 | 1882 | add_to_client(struct i915_request *rq, struct drm_file *file) |
c8659efa | 1883 | { |
44c22f3f CW |
1884 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1885 | ||
1886 | rq->file_priv = file_priv; | |
1887 | ||
1888 | spin_lock(&file_priv->mm.lock); | |
1889 | list_add_tail(&rq->client_link, &file_priv->mm.request_list); | |
1890 | spin_unlock(&file_priv->mm.lock); | |
c8659efa CW |
1891 | } |
1892 | ||
7d6236bb | 1893 | static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) |
78382593 | 1894 | { |
2889caa9 | 1895 | int err; |
78382593 | 1896 | |
2889caa9 CW |
1897 | err = eb_move_to_gpu(eb); |
1898 | if (err) | |
1899 | return err; | |
78382593 | 1900 | |
650bc635 | 1901 | if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) { |
2889caa9 CW |
1902 | err = i915_reset_gen7_sol_offsets(eb->request); |
1903 | if (err) | |
1904 | return err; | |
78382593 OM |
1905 | } |
1906 | ||
85474441 CW |
1907 | /* |
1908 | * After we completed waiting for other engines (using HW semaphores) | |
1909 | * then we can signal that this request/batch is ready to run. This | |
1910 | * allows us to determine if the batch is still waiting on the GPU | |
1911 | * or actually running by checking the breadcrumb. | |
1912 | */ | |
1913 | if (eb->engine->emit_init_breadcrumb) { | |
1914 | err = eb->engine->emit_init_breadcrumb(eb->request); | |
1915 | if (err) | |
1916 | return err; | |
1917 | } | |
1918 | ||
2889caa9 | 1919 | err = eb->engine->emit_bb_start(eb->request, |
7d6236bb | 1920 | batch->node.start + |
650bc635 CW |
1921 | eb->batch_start_offset, |
1922 | eb->batch_len, | |
2889caa9 CW |
1923 | eb->batch_flags); |
1924 | if (err) | |
1925 | return err; | |
78382593 | 1926 | |
32d94048 CW |
1927 | if (eb->trampoline) { |
1928 | GEM_BUG_ON(eb->batch_start_offset); | |
1929 | err = eb->engine->emit_bb_start(eb->request, | |
1930 | eb->trampoline->node.start + | |
1931 | eb->batch_len, | |
1932 | 0, 0); | |
1933 | if (err) | |
1934 | return err; | |
1935 | } | |
1936 | ||
9f3ccd40 | 1937 | if (intel_context_nopreempt(eb->context)) |
e1c31fb5 | 1938 | __set_bit(I915_FENCE_FLAG_NOPREEMPT, &eb->request->fence.flags); |
9cd20ef7 | 1939 | |
2f5945bc | 1940 | return 0; |
78382593 OM |
1941 | } |
1942 | ||
d5b2a3a4 CW |
1943 | static int num_vcs_engines(const struct drm_i915_private *i915) |
1944 | { | |
1945 | return hweight64(INTEL_INFO(i915)->engine_mask & | |
1946 | GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0)); | |
1947 | } | |
1948 | ||
204bcfef | 1949 | /* |
a8ebba75 | 1950 | * Find one BSD ring to dispatch the corresponding BSD command. |
c80ff16e | 1951 | * The engine index is returned. |
a8ebba75 | 1952 | */ |
de1add36 | 1953 | static unsigned int |
c80ff16e CW |
1954 | gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, |
1955 | struct drm_file *file) | |
a8ebba75 | 1956 | { |
a8ebba75 ZY |
1957 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1958 | ||
de1add36 | 1959 | /* Check whether the file_priv has already selected one ring. */ |
6f633402 | 1960 | if ((int)file_priv->bsd_engine < 0) |
1a07e86c CW |
1961 | file_priv->bsd_engine = |
1962 | get_random_int() % num_vcs_engines(dev_priv); | |
d23db88c | 1963 | |
c80ff16e | 1964 | return file_priv->bsd_engine; |
d23db88c CW |
1965 | } |
1966 | ||
5e2a0419 | 1967 | static const enum intel_engine_id user_ring_map[] = { |
8a68d464 CW |
1968 | [I915_EXEC_DEFAULT] = RCS0, |
1969 | [I915_EXEC_RENDER] = RCS0, | |
1970 | [I915_EXEC_BLT] = BCS0, | |
1971 | [I915_EXEC_BSD] = VCS0, | |
1972 | [I915_EXEC_VEBOX] = VECS0 | |
de1add36 TU |
1973 | }; |
1974 | ||
e5dadff4 CW |
1975 | static struct i915_request *eb_throttle(struct intel_context *ce) |
1976 | { | |
1977 | struct intel_ring *ring = ce->ring; | |
1978 | struct intel_timeline *tl = ce->timeline; | |
1979 | struct i915_request *rq; | |
1980 | ||
1981 | /* | |
1982 | * Completely unscientific finger-in-the-air estimates for suitable | |
1983 | * maximum user request size (to avoid blocking) and then backoff. | |
1984 | */ | |
1985 | if (intel_ring_update_space(ring) >= PAGE_SIZE) | |
1986 | return NULL; | |
1987 | ||
1988 | /* | |
1989 | * Find a request that after waiting upon, there will be at least half | |
1990 | * the ring available. The hysteresis allows us to compete for the | |
1991 | * shared ring and should mean that we sleep less often prior to | |
1992 | * claiming our resources, but not so long that the ring completely | |
1993 | * drains before we can submit our next request. | |
1994 | */ | |
1995 | list_for_each_entry(rq, &tl->requests, link) { | |
1996 | if (rq->ring != ring) | |
1997 | continue; | |
1998 | ||
1999 | if (__intel_ring_space(rq->postfix, | |
2000 | ring->emit, ring->size) > ring->size / 2) | |
2001 | break; | |
2002 | } | |
2003 | if (&rq->link == &tl->requests) | |
2004 | return NULL; /* weird, we will check again later for real */ | |
2005 | ||
2006 | return i915_request_get(rq); | |
2007 | } | |
2008 | ||
e5dadff4 CW |
2009 | static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) |
2010 | { | |
2011 | struct intel_timeline *tl; | |
2012 | struct i915_request *rq; | |
2013 | int err; | |
2014 | ||
8f2a1057 CW |
2015 | /* |
2016 | * ABI: Before userspace accesses the GPU (e.g. execbuffer), report | |
2017 | * EIO if the GPU is already wedged. | |
2018 | */ | |
cb823ed9 | 2019 | err = intel_gt_terminally_wedged(ce->engine->gt); |
8f2a1057 CW |
2020 | if (err) |
2021 | return err; | |
2022 | ||
9f3ccd40 CW |
2023 | if (unlikely(intel_context_is_banned(ce))) |
2024 | return -EIO; | |
2025 | ||
8f2a1057 CW |
2026 | /* |
2027 | * Pinning the contexts may generate requests in order to acquire | |
2028 | * GGTT space, so do this first before we reserve a seqno for | |
2029 | * ourselves. | |
2030 | */ | |
2850748e | 2031 | err = intel_context_pin(ce); |
fa9f6681 CW |
2032 | if (err) |
2033 | return err; | |
8f2a1057 | 2034 | |
a4e57f90 CW |
2035 | /* |
2036 | * Take a local wakeref for preparing to dispatch the execbuf as | |
2037 | * we expect to access the hardware fairly frequently in the | |
2038 | * process, and require the engine to be kept awake between accesses. | |
2039 | * Upon dispatch, we acquire another prolonged wakeref that we hold | |
2040 | * until the timeline is idle, which in turn releases the wakeref | |
2041 | * taken on the engine, and the parent device. | |
2042 | */ | |
e5dadff4 CW |
2043 | tl = intel_context_timeline_lock(ce); |
2044 | if (IS_ERR(tl)) { | |
2045 | err = PTR_ERR(tl); | |
a4e57f90 | 2046 | goto err_unpin; |
e5dadff4 | 2047 | } |
a4e57f90 CW |
2048 | |
2049 | intel_context_enter(ce); | |
e5dadff4 CW |
2050 | rq = eb_throttle(ce); |
2051 | ||
2052 | intel_context_timeline_unlock(tl); | |
2053 | ||
2054 | if (rq) { | |
cb4d5dc3 CW |
2055 | bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; |
2056 | long timeout; | |
2057 | ||
2058 | timeout = MAX_SCHEDULE_TIMEOUT; | |
2059 | if (nonblock) | |
2060 | timeout = 0; | |
e5dadff4 | 2061 | |
cb4d5dc3 CW |
2062 | timeout = i915_request_wait(rq, |
2063 | I915_WAIT_INTERRUPTIBLE, | |
2064 | timeout); | |
e5dadff4 | 2065 | i915_request_put(rq); |
cb4d5dc3 CW |
2066 | |
2067 | if (timeout < 0) { | |
2068 | err = nonblock ? -EWOULDBLOCK : timeout; | |
2069 | goto err_exit; | |
2070 | } | |
e5dadff4 | 2071 | } |
a4e57f90 | 2072 | |
5e2a0419 | 2073 | eb->engine = ce->engine; |
8f2a1057 CW |
2074 | eb->context = ce; |
2075 | return 0; | |
a4e57f90 | 2076 | |
e5dadff4 CW |
2077 | err_exit: |
2078 | mutex_lock(&tl->mutex); | |
2079 | intel_context_exit(ce); | |
2080 | intel_context_timeline_unlock(tl); | |
a4e57f90 | 2081 | err_unpin: |
2850748e | 2082 | intel_context_unpin(ce); |
a4e57f90 | 2083 | return err; |
8f2a1057 CW |
2084 | } |
2085 | ||
e5dadff4 | 2086 | static void eb_unpin_engine(struct i915_execbuffer *eb) |
8f2a1057 | 2087 | { |
a4e57f90 | 2088 | struct intel_context *ce = eb->context; |
75d0a7f3 | 2089 | struct intel_timeline *tl = ce->timeline; |
a4e57f90 CW |
2090 | |
2091 | mutex_lock(&tl->mutex); | |
2092 | intel_context_exit(ce); | |
2093 | mutex_unlock(&tl->mutex); | |
2094 | ||
2850748e | 2095 | intel_context_unpin(ce); |
8f2a1057 | 2096 | } |
de1add36 | 2097 | |
5e2a0419 CW |
2098 | static unsigned int |
2099 | eb_select_legacy_ring(struct i915_execbuffer *eb, | |
2100 | struct drm_file *file, | |
2101 | struct drm_i915_gem_execbuffer2 *args) | |
de1add36 | 2102 | { |
8f2a1057 | 2103 | struct drm_i915_private *i915 = eb->i915; |
de1add36 | 2104 | unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; |
de1add36 | 2105 | |
5e2a0419 CW |
2106 | if (user_ring_id != I915_EXEC_BSD && |
2107 | (args->flags & I915_EXEC_BSD_MASK)) { | |
baa89ba3 WK |
2108 | drm_dbg(&i915->drm, |
2109 | "execbuf with non bsd ring but with invalid " | |
2110 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
5e2a0419 | 2111 | return -1; |
de1add36 TU |
2112 | } |
2113 | ||
d5b2a3a4 | 2114 | if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) { |
de1add36 TU |
2115 | unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; |
2116 | ||
2117 | if (bsd_idx == I915_EXEC_BSD_DEFAULT) { | |
8f2a1057 | 2118 | bsd_idx = gen8_dispatch_bsd_engine(i915, file); |
de1add36 TU |
2119 | } else if (bsd_idx >= I915_EXEC_BSD_RING1 && |
2120 | bsd_idx <= I915_EXEC_BSD_RING2) { | |
d9da6aa0 | 2121 | bsd_idx >>= I915_EXEC_BSD_SHIFT; |
de1add36 TU |
2122 | bsd_idx--; |
2123 | } else { | |
baa89ba3 WK |
2124 | drm_dbg(&i915->drm, |
2125 | "execbuf with unknown bsd ring: %u\n", | |
2126 | bsd_idx); | |
5e2a0419 | 2127 | return -1; |
de1add36 TU |
2128 | } |
2129 | ||
5e2a0419 | 2130 | return _VCS(bsd_idx); |
de1add36 TU |
2131 | } |
2132 | ||
5e2a0419 | 2133 | if (user_ring_id >= ARRAY_SIZE(user_ring_map)) { |
baa89ba3 WK |
2134 | drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n", |
2135 | user_ring_id); | |
5e2a0419 | 2136 | return -1; |
de1add36 TU |
2137 | } |
2138 | ||
5e2a0419 CW |
2139 | return user_ring_map[user_ring_id]; |
2140 | } | |
2141 | ||
2142 | static int | |
e5dadff4 CW |
2143 | eb_pin_engine(struct i915_execbuffer *eb, |
2144 | struct drm_file *file, | |
2145 | struct drm_i915_gem_execbuffer2 *args) | |
5e2a0419 CW |
2146 | { |
2147 | struct intel_context *ce; | |
2148 | unsigned int idx; | |
2149 | int err; | |
2150 | ||
976b55f0 CW |
2151 | if (i915_gem_context_user_engines(eb->gem_context)) |
2152 | idx = args->flags & I915_EXEC_RING_MASK; | |
2153 | else | |
2154 | idx = eb_select_legacy_ring(eb, file, args); | |
5e2a0419 CW |
2155 | |
2156 | ce = i915_gem_context_get_engine(eb->gem_context, idx); | |
2157 | if (IS_ERR(ce)) | |
2158 | return PTR_ERR(ce); | |
2159 | ||
e5dadff4 | 2160 | err = __eb_pin_engine(eb, ce); |
5e2a0419 CW |
2161 | intel_context_put(ce); |
2162 | ||
2163 | return err; | |
de1add36 TU |
2164 | } |
2165 | ||
cf6e7bac JE |
2166 | static void |
2167 | __free_fence_array(struct drm_syncobj **fences, unsigned int n) | |
2168 | { | |
2169 | while (n--) | |
2170 | drm_syncobj_put(ptr_mask_bits(fences[n], 2)); | |
2171 | kvfree(fences); | |
2172 | } | |
2173 | ||
2174 | static struct drm_syncobj ** | |
2175 | get_fence_array(struct drm_i915_gem_execbuffer2 *args, | |
2176 | struct drm_file *file) | |
2177 | { | |
d710fc16 | 2178 | const unsigned long nfences = args->num_cliprects; |
cf6e7bac JE |
2179 | struct drm_i915_gem_exec_fence __user *user; |
2180 | struct drm_syncobj **fences; | |
d710fc16 | 2181 | unsigned long n; |
cf6e7bac JE |
2182 | int err; |
2183 | ||
2184 | if (!(args->flags & I915_EXEC_FENCE_ARRAY)) | |
2185 | return NULL; | |
2186 | ||
d710fc16 CW |
2187 | /* Check multiplication overflow for access_ok() and kvmalloc_array() */ |
2188 | BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long)); | |
2189 | if (nfences > min_t(unsigned long, | |
2190 | ULONG_MAX / sizeof(*user), | |
2191 | SIZE_MAX / sizeof(*fences))) | |
cf6e7bac JE |
2192 | return ERR_PTR(-EINVAL); |
2193 | ||
2194 | user = u64_to_user_ptr(args->cliprects_ptr); | |
96d4f267 | 2195 | if (!access_ok(user, nfences * sizeof(*user))) |
cf6e7bac JE |
2196 | return ERR_PTR(-EFAULT); |
2197 | ||
d710fc16 | 2198 | fences = kvmalloc_array(nfences, sizeof(*fences), |
0ee931c4 | 2199 | __GFP_NOWARN | GFP_KERNEL); |
cf6e7bac JE |
2200 | if (!fences) |
2201 | return ERR_PTR(-ENOMEM); | |
2202 | ||
2203 | for (n = 0; n < nfences; n++) { | |
2204 | struct drm_i915_gem_exec_fence fence; | |
2205 | struct drm_syncobj *syncobj; | |
2206 | ||
2207 | if (__copy_from_user(&fence, user++, sizeof(fence))) { | |
2208 | err = -EFAULT; | |
2209 | goto err; | |
2210 | } | |
2211 | ||
ebcaa1ff TU |
2212 | if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) { |
2213 | err = -EINVAL; | |
2214 | goto err; | |
2215 | } | |
2216 | ||
cf6e7bac JE |
2217 | syncobj = drm_syncobj_find(file, fence.handle); |
2218 | if (!syncobj) { | |
2219 | DRM_DEBUG("Invalid syncobj handle provided\n"); | |
2220 | err = -ENOENT; | |
2221 | goto err; | |
2222 | } | |
2223 | ||
ebcaa1ff TU |
2224 | BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) & |
2225 | ~__I915_EXEC_FENCE_UNKNOWN_FLAGS); | |
2226 | ||
cf6e7bac JE |
2227 | fences[n] = ptr_pack_bits(syncobj, fence.flags, 2); |
2228 | } | |
2229 | ||
2230 | return fences; | |
2231 | ||
2232 | err: | |
2233 | __free_fence_array(fences, n); | |
2234 | return ERR_PTR(err); | |
2235 | } | |
2236 | ||
2237 | static void | |
2238 | put_fence_array(struct drm_i915_gem_execbuffer2 *args, | |
2239 | struct drm_syncobj **fences) | |
2240 | { | |
2241 | if (fences) | |
2242 | __free_fence_array(fences, args->num_cliprects); | |
2243 | } | |
2244 | ||
2245 | static int | |
2246 | await_fence_array(struct i915_execbuffer *eb, | |
2247 | struct drm_syncobj **fences) | |
2248 | { | |
2249 | const unsigned int nfences = eb->args->num_cliprects; | |
2250 | unsigned int n; | |
2251 | int err; | |
2252 | ||
2253 | for (n = 0; n < nfences; n++) { | |
2254 | struct drm_syncobj *syncobj; | |
2255 | struct dma_fence *fence; | |
2256 | unsigned int flags; | |
2257 | ||
2258 | syncobj = ptr_unpack_bits(fences[n], &flags, 2); | |
2259 | if (!(flags & I915_EXEC_FENCE_WAIT)) | |
2260 | continue; | |
2261 | ||
afca4216 | 2262 | fence = drm_syncobj_fence_get(syncobj); |
cf6e7bac JE |
2263 | if (!fence) |
2264 | return -EINVAL; | |
2265 | ||
e61e0f51 | 2266 | err = i915_request_await_dma_fence(eb->request, fence); |
cf6e7bac JE |
2267 | dma_fence_put(fence); |
2268 | if (err < 0) | |
2269 | return err; | |
2270 | } | |
2271 | ||
2272 | return 0; | |
2273 | } | |
2274 | ||
2275 | static void | |
2276 | signal_fence_array(struct i915_execbuffer *eb, | |
2277 | struct drm_syncobj **fences) | |
2278 | { | |
2279 | const unsigned int nfences = eb->args->num_cliprects; | |
2280 | struct dma_fence * const fence = &eb->request->fence; | |
2281 | unsigned int n; | |
2282 | ||
2283 | for (n = 0; n < nfences; n++) { | |
2284 | struct drm_syncobj *syncobj; | |
2285 | unsigned int flags; | |
2286 | ||
2287 | syncobj = ptr_unpack_bits(fences[n], &flags, 2); | |
2288 | if (!(flags & I915_EXEC_FENCE_SIGNAL)) | |
2289 | continue; | |
2290 | ||
0b258ed1 | 2291 | drm_syncobj_replace_fence(syncobj, fence); |
cf6e7bac JE |
2292 | } |
2293 | } | |
2294 | ||
61231f6b CW |
2295 | static void retire_requests(struct intel_timeline *tl, struct i915_request *end) |
2296 | { | |
2297 | struct i915_request *rq, *rn; | |
2298 | ||
2299 | list_for_each_entry_safe(rq, rn, &tl->requests, link) | |
2300 | if (rq == end || !i915_request_retire(rq)) | |
2301 | break; | |
2302 | } | |
2303 | ||
2304 | static void eb_request_add(struct i915_execbuffer *eb) | |
2305 | { | |
2306 | struct i915_request *rq = eb->request; | |
2307 | struct intel_timeline * const tl = i915_request_timeline(rq); | |
2308 | struct i915_sched_attr attr = {}; | |
2309 | struct i915_request *prev; | |
2310 | ||
2311 | lockdep_assert_held(&tl->mutex); | |
2312 | lockdep_unpin_lock(&tl->mutex, rq->cookie); | |
2313 | ||
2314 | trace_i915_request_add(rq); | |
2315 | ||
2316 | prev = __i915_request_commit(rq); | |
2317 | ||
2318 | /* Check that the context wasn't destroyed before submission */ | |
2e46a2a0 | 2319 | if (likely(!intel_context_is_closed(eb->context))) { |
61231f6b CW |
2320 | attr = eb->gem_context->sched; |
2321 | ||
2322 | /* | |
2323 | * Boost actual workloads past semaphores! | |
2324 | * | |
2325 | * With semaphores we spin on one engine waiting for another, | |
2326 | * simply to reduce the latency of starting our work when | |
2327 | * the signaler completes. However, if there is any other | |
2328 | * work that we could be doing on this engine instead, that | |
2329 | * is better utilisation and will reduce the overall duration | |
2330 | * of the current work. To avoid PI boosting a semaphore | |
2331 | * far in the distance past over useful work, we keep a history | |
2332 | * of any semaphore use along our dependency chain. | |
2333 | */ | |
2334 | if (!(rq->sched.flags & I915_SCHED_HAS_SEMAPHORE_CHAIN)) | |
2335 | attr.priority |= I915_PRIORITY_NOSEMAPHORE; | |
2336 | ||
2337 | /* | |
2338 | * Boost priorities to new clients (new request flows). | |
2339 | * | |
2340 | * Allow interactive/synchronous clients to jump ahead of | |
2341 | * the bulk clients. (FQ_CODEL) | |
2342 | */ | |
2343 | if (list_empty(&rq->sched.signalers_list)) | |
2344 | attr.priority |= I915_PRIORITY_WAIT; | |
2345 | } else { | |
2346 | /* Serialise with context_close via the add_to_timeline */ | |
36e191f0 CW |
2347 | i915_request_set_error_once(rq, -ENOENT); |
2348 | __i915_request_skip(rq); | |
61231f6b CW |
2349 | } |
2350 | ||
2351 | local_bh_disable(); | |
2352 | __i915_request_queue(rq, &attr); | |
2353 | local_bh_enable(); /* Kick the execlists tasklet if just scheduled */ | |
2354 | ||
2355 | /* Try to clean up the client's timeline after submitting the request */ | |
2356 | if (prev) | |
2357 | retire_requests(tl, prev); | |
2358 | ||
2359 | mutex_unlock(&tl->mutex); | |
2360 | } | |
2361 | ||
54cf91dc | 2362 | static int |
650bc635 | 2363 | i915_gem_do_execbuffer(struct drm_device *dev, |
54cf91dc CW |
2364 | struct drm_file *file, |
2365 | struct drm_i915_gem_execbuffer2 *args, | |
cf6e7bac JE |
2366 | struct drm_i915_gem_exec_object2 *exec, |
2367 | struct drm_syncobj **fences) | |
54cf91dc | 2368 | { |
44157641 | 2369 | struct drm_i915_private *i915 = to_i915(dev); |
650bc635 | 2370 | struct i915_execbuffer eb; |
fec0445c | 2371 | struct dma_fence *in_fence = NULL; |
a88b6e4c | 2372 | struct dma_fence *exec_fence = NULL; |
fec0445c | 2373 | struct sync_file *out_fence = NULL; |
7d6236bb | 2374 | struct i915_vma *batch; |
fec0445c | 2375 | int out_fence_fd = -1; |
2889caa9 | 2376 | int err; |
432e58ed | 2377 | |
74c1c694 | 2378 | BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS); |
2889caa9 CW |
2379 | BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & |
2380 | ~__EXEC_OBJECT_UNKNOWN_FLAGS); | |
54cf91dc | 2381 | |
44157641 | 2382 | eb.i915 = i915; |
650bc635 CW |
2383 | eb.file = file; |
2384 | eb.args = args; | |
7dd4f672 | 2385 | if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) |
2889caa9 | 2386 | args->flags |= __EXEC_HAS_RELOC; |
c7c6e46f | 2387 | |
650bc635 | 2388 | eb.exec = exec; |
7d6236bb CW |
2389 | eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); |
2390 | eb.vma[0].vma = NULL; | |
c7c6e46f | 2391 | |
2889caa9 | 2392 | eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; |
650bc635 CW |
2393 | reloc_cache_init(&eb.reloc_cache, eb.i915); |
2394 | ||
2889caa9 | 2395 | eb.buffer_count = args->buffer_count; |
650bc635 CW |
2396 | eb.batch_start_offset = args->batch_start_offset; |
2397 | eb.batch_len = args->batch_len; | |
32d94048 | 2398 | eb.trampoline = NULL; |
650bc635 | 2399 | |
2889caa9 | 2400 | eb.batch_flags = 0; |
d7d4eedd | 2401 | if (args->flags & I915_EXEC_SECURE) { |
44157641 JB |
2402 | if (INTEL_GEN(i915) >= 11) |
2403 | return -ENODEV; | |
2404 | ||
2405 | /* Return -EPERM to trigger fallback code on old binaries. */ | |
2406 | if (!HAS_SECURE_BATCHES(i915)) | |
2407 | return -EPERM; | |
2408 | ||
b3ac9f25 | 2409 | if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) |
44157641 | 2410 | return -EPERM; |
d7d4eedd | 2411 | |
2889caa9 | 2412 | eb.batch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 2413 | } |
b45305fc | 2414 | if (args->flags & I915_EXEC_IS_PINNED) |
2889caa9 | 2415 | eb.batch_flags |= I915_DISPATCH_PINNED; |
54cf91dc | 2416 | |
fec0445c CW |
2417 | if (args->flags & I915_EXEC_FENCE_IN) { |
2418 | in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); | |
4a04e371 DCS |
2419 | if (!in_fence) |
2420 | return -EINVAL; | |
fec0445c CW |
2421 | } |
2422 | ||
a88b6e4c CW |
2423 | if (args->flags & I915_EXEC_FENCE_SUBMIT) { |
2424 | if (in_fence) { | |
2425 | err = -EINVAL; | |
2426 | goto err_in_fence; | |
2427 | } | |
2428 | ||
2429 | exec_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); | |
2430 | if (!exec_fence) { | |
2431 | err = -EINVAL; | |
2432 | goto err_in_fence; | |
2433 | } | |
2434 | } | |
2435 | ||
fec0445c CW |
2436 | if (args->flags & I915_EXEC_FENCE_OUT) { |
2437 | out_fence_fd = get_unused_fd_flags(O_CLOEXEC); | |
2438 | if (out_fence_fd < 0) { | |
2889caa9 | 2439 | err = out_fence_fd; |
a88b6e4c | 2440 | goto err_exec_fence; |
fec0445c CW |
2441 | } |
2442 | } | |
2443 | ||
4d470f73 CW |
2444 | err = eb_create(&eb); |
2445 | if (err) | |
2446 | goto err_out_fence; | |
2447 | ||
2448 | GEM_BUG_ON(!eb.lut_size); | |
2889caa9 | 2449 | |
1acfc104 CW |
2450 | err = eb_select_context(&eb); |
2451 | if (unlikely(err)) | |
2452 | goto err_destroy; | |
2453 | ||
e5dadff4 | 2454 | err = eb_pin_engine(&eb, file, args); |
d6f328bf | 2455 | if (unlikely(err)) |
e5dadff4 | 2456 | goto err_context; |
d6f328bf | 2457 | |
2889caa9 | 2458 | err = eb_relocate(&eb); |
1f727d9e | 2459 | if (err) { |
2889caa9 CW |
2460 | /* |
2461 | * If the user expects the execobject.offset and | |
2462 | * reloc.presumed_offset to be an exact match, | |
2463 | * as for using NO_RELOC, then we cannot update | |
2464 | * the execobject.offset until we have completed | |
2465 | * relocation. | |
2466 | */ | |
2467 | args->flags &= ~__EXEC_HAS_RELOC; | |
2889caa9 | 2468 | goto err_vma; |
1f727d9e | 2469 | } |
54cf91dc | 2470 | |
7d6236bb | 2471 | if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) { |
baa89ba3 WK |
2472 | drm_dbg(&i915->drm, |
2473 | "Attempting to use self-modifying batch buffer\n"); | |
2889caa9 CW |
2474 | err = -EINVAL; |
2475 | goto err_vma; | |
54cf91dc | 2476 | } |
7d6236bb CW |
2477 | |
2478 | if (range_overflows_t(u64, | |
2479 | eb.batch_start_offset, eb.batch_len, | |
2480 | eb.batch->vma->size)) { | |
baa89ba3 | 2481 | drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); |
2889caa9 CW |
2482 | err = -EINVAL; |
2483 | goto err_vma; | |
0b537272 | 2484 | } |
54cf91dc | 2485 | |
435e8fc0 | 2486 | if (eb.batch_len == 0) |
7d6236bb | 2487 | eb.batch_len = eb.batch->vma->size - eb.batch_start_offset; |
435e8fc0 | 2488 | |
51696691 CW |
2489 | err = eb_parse(&eb); |
2490 | if (err) | |
2491 | goto err_vma; | |
351e3db2 | 2492 | |
2889caa9 CW |
2493 | /* |
2494 | * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure | |
d7d4eedd | 2495 | * batch" bit. Hence we need to pin secure batches into the global gtt. |
28cf5415 | 2496 | * hsw should have this fixed, but bdw mucks it up again. */ |
7d6236bb | 2497 | batch = eb.batch->vma; |
2889caa9 | 2498 | if (eb.batch_flags & I915_DISPATCH_SECURE) { |
058d88c4 | 2499 | struct i915_vma *vma; |
59bfa124 | 2500 | |
da51a1e7 DV |
2501 | /* |
2502 | * So on first glance it looks freaky that we pin the batch here | |
2503 | * outside of the reservation loop. But: | |
2504 | * - The batch is already pinned into the relevant ppgtt, so we | |
2505 | * already have the backing storage fully allocated. | |
2506 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 2507 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
2508 | * fitting due to fragmentation. |
2509 | * So this is actually safe. | |
2510 | */ | |
7d6236bb | 2511 | vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); |
058d88c4 | 2512 | if (IS_ERR(vma)) { |
2889caa9 | 2513 | err = PTR_ERR(vma); |
2c59fd06 | 2514 | goto err_parse; |
058d88c4 | 2515 | } |
d7d4eedd | 2516 | |
7d6236bb | 2517 | batch = vma; |
59bfa124 | 2518 | } |
d7d4eedd | 2519 | |
7dd4f672 CW |
2520 | /* All GPU relocation batches must be submitted prior to the user rq */ |
2521 | GEM_BUG_ON(eb.reloc_cache.rq); | |
2522 | ||
0c8dac88 | 2523 | /* Allocate a request for this batch buffer nice and early. */ |
8f2a1057 | 2524 | eb.request = i915_request_create(eb.context); |
650bc635 | 2525 | if (IS_ERR(eb.request)) { |
2889caa9 | 2526 | err = PTR_ERR(eb.request); |
0c8dac88 | 2527 | goto err_batch_unpin; |
26827088 | 2528 | } |
0c8dac88 | 2529 | |
fec0445c | 2530 | if (in_fence) { |
e61e0f51 | 2531 | err = i915_request_await_dma_fence(eb.request, in_fence); |
2889caa9 | 2532 | if (err < 0) |
fec0445c CW |
2533 | goto err_request; |
2534 | } | |
2535 | ||
a88b6e4c CW |
2536 | if (exec_fence) { |
2537 | err = i915_request_await_execution(eb.request, exec_fence, | |
2538 | eb.engine->bond_execute); | |
2539 | if (err < 0) | |
2540 | goto err_request; | |
2541 | } | |
2542 | ||
cf6e7bac JE |
2543 | if (fences) { |
2544 | err = await_fence_array(&eb, fences); | |
2545 | if (err) | |
2546 | goto err_request; | |
2547 | } | |
2548 | ||
fec0445c | 2549 | if (out_fence_fd != -1) { |
650bc635 | 2550 | out_fence = sync_file_create(&eb.request->fence); |
fec0445c | 2551 | if (!out_fence) { |
2889caa9 | 2552 | err = -ENOMEM; |
fec0445c CW |
2553 | goto err_request; |
2554 | } | |
2555 | } | |
2556 | ||
2889caa9 CW |
2557 | /* |
2558 | * Whilst this request exists, batch_obj will be on the | |
17f298cf CW |
2559 | * active_list, and so will hold the active reference. Only when this |
2560 | * request is retired will the the batch_obj be moved onto the | |
2561 | * inactive_list and lose its active reference. Hence we do not need | |
2562 | * to explicitly hold another reference here. | |
2563 | */ | |
7d6236bb CW |
2564 | eb.request->batch = batch; |
2565 | if (batch->private) | |
2566 | intel_engine_pool_mark_active(batch->private, eb.request); | |
5f19e2bf | 2567 | |
e61e0f51 | 2568 | trace_i915_request_queue(eb.request, eb.batch_flags); |
7d6236bb | 2569 | err = eb_submit(&eb, batch); |
aa9b7810 | 2570 | err_request: |
650bc635 | 2571 | add_to_client(eb.request, file); |
e14177f1 | 2572 | i915_request_get(eb.request); |
61231f6b | 2573 | eb_request_add(&eb); |
c8659efa | 2574 | |
cf6e7bac JE |
2575 | if (fences) |
2576 | signal_fence_array(&eb, fences); | |
2577 | ||
fec0445c | 2578 | if (out_fence) { |
2889caa9 | 2579 | if (err == 0) { |
fec0445c | 2580 | fd_install(out_fence_fd, out_fence->file); |
b6a88e4a | 2581 | args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */ |
fec0445c CW |
2582 | args->rsvd2 |= (u64)out_fence_fd << 32; |
2583 | out_fence_fd = -1; | |
2584 | } else { | |
2585 | fput(out_fence->file); | |
2586 | } | |
2587 | } | |
e14177f1 | 2588 | i915_request_put(eb.request); |
54cf91dc | 2589 | |
0c8dac88 | 2590 | err_batch_unpin: |
2889caa9 | 2591 | if (eb.batch_flags & I915_DISPATCH_SECURE) |
7d6236bb | 2592 | i915_vma_unpin(batch); |
2c59fd06 | 2593 | err_parse: |
7d6236bb CW |
2594 | if (batch->private) |
2595 | intel_engine_pool_put(batch->private); | |
2889caa9 CW |
2596 | err_vma: |
2597 | if (eb.exec) | |
2598 | eb_release_vmas(&eb); | |
32d94048 CW |
2599 | if (eb.trampoline) |
2600 | i915_vma_unpin(eb.trampoline); | |
e5dadff4 | 2601 | eb_unpin_engine(&eb); |
a4e57f90 | 2602 | err_context: |
8f2a1057 | 2603 | i915_gem_context_put(eb.gem_context); |
1acfc104 | 2604 | err_destroy: |
2889caa9 | 2605 | eb_destroy(&eb); |
4d470f73 | 2606 | err_out_fence: |
fec0445c CW |
2607 | if (out_fence_fd != -1) |
2608 | put_unused_fd(out_fence_fd); | |
a88b6e4c CW |
2609 | err_exec_fence: |
2610 | dma_fence_put(exec_fence); | |
4a04e371 | 2611 | err_in_fence: |
fec0445c | 2612 | dma_fence_put(in_fence); |
2889caa9 | 2613 | return err; |
54cf91dc CW |
2614 | } |
2615 | ||
d710fc16 CW |
2616 | static size_t eb_element_size(void) |
2617 | { | |
7d6236bb | 2618 | return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma); |
d710fc16 CW |
2619 | } |
2620 | ||
2621 | static bool check_buffer_count(size_t count) | |
2622 | { | |
2623 | const size_t sz = eb_element_size(); | |
2624 | ||
2625 | /* | |
2626 | * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup | |
2627 | * array size (see eb_create()). Otherwise, we can accept an array as | |
2628 | * large as can be addressed (though use large arrays at your peril)! | |
2629 | */ | |
2630 | ||
2631 | return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1); | |
2632 | } | |
2633 | ||
54cf91dc CW |
2634 | /* |
2635 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
2636 | * list array and passes it to the real function. | |
2637 | */ | |
2638 | int | |
6a20fe7b VS |
2639 | i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, |
2640 | struct drm_file *file) | |
54cf91dc | 2641 | { |
d0bf4582 | 2642 | struct drm_i915_private *i915 = to_i915(dev); |
54cf91dc CW |
2643 | struct drm_i915_gem_execbuffer *args = data; |
2644 | struct drm_i915_gem_execbuffer2 exec2; | |
2645 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
2646 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
d710fc16 | 2647 | const size_t count = args->buffer_count; |
2889caa9 CW |
2648 | unsigned int i; |
2649 | int err; | |
54cf91dc | 2650 | |
d710fc16 | 2651 | if (!check_buffer_count(count)) { |
d0bf4582 | 2652 | drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count); |
54cf91dc CW |
2653 | return -EINVAL; |
2654 | } | |
2655 | ||
2889caa9 CW |
2656 | exec2.buffers_ptr = args->buffers_ptr; |
2657 | exec2.buffer_count = args->buffer_count; | |
2658 | exec2.batch_start_offset = args->batch_start_offset; | |
2659 | exec2.batch_len = args->batch_len; | |
2660 | exec2.DR1 = args->DR1; | |
2661 | exec2.DR4 = args->DR4; | |
2662 | exec2.num_cliprects = args->num_cliprects; | |
2663 | exec2.cliprects_ptr = args->cliprects_ptr; | |
2664 | exec2.flags = I915_EXEC_RENDER; | |
2665 | i915_execbuffer2_set_context_id(exec2, 0); | |
2666 | ||
00aff3f6 TU |
2667 | err = i915_gem_check_execbuffer(&exec2); |
2668 | if (err) | |
2669 | return err; | |
2889caa9 | 2670 | |
54cf91dc | 2671 | /* Copy in the exec list from userland */ |
d710fc16 | 2672 | exec_list = kvmalloc_array(count, sizeof(*exec_list), |
0ee931c4 | 2673 | __GFP_NOWARN | GFP_KERNEL); |
d710fc16 | 2674 | exec2_list = kvmalloc_array(count + 1, eb_element_size(), |
0ee931c4 | 2675 | __GFP_NOWARN | GFP_KERNEL); |
54cf91dc | 2676 | if (exec_list == NULL || exec2_list == NULL) { |
d0bf4582 WK |
2677 | drm_dbg(&i915->drm, |
2678 | "Failed to allocate exec list for %d buffers\n", | |
2679 | args->buffer_count); | |
2098105e MH |
2680 | kvfree(exec_list); |
2681 | kvfree(exec2_list); | |
54cf91dc CW |
2682 | return -ENOMEM; |
2683 | } | |
2889caa9 | 2684 | err = copy_from_user(exec_list, |
3ed605bc | 2685 | u64_to_user_ptr(args->buffers_ptr), |
d710fc16 | 2686 | sizeof(*exec_list) * count); |
2889caa9 | 2687 | if (err) { |
d0bf4582 WK |
2688 | drm_dbg(&i915->drm, "copy %d exec entries failed %d\n", |
2689 | args->buffer_count, err); | |
2098105e MH |
2690 | kvfree(exec_list); |
2691 | kvfree(exec2_list); | |
54cf91dc CW |
2692 | return -EFAULT; |
2693 | } | |
2694 | ||
2695 | for (i = 0; i < args->buffer_count; i++) { | |
2696 | exec2_list[i].handle = exec_list[i].handle; | |
2697 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
2698 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
2699 | exec2_list[i].alignment = exec_list[i].alignment; | |
2700 | exec2_list[i].offset = exec_list[i].offset; | |
f0836b72 | 2701 | if (INTEL_GEN(to_i915(dev)) < 4) |
54cf91dc CW |
2702 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
2703 | else | |
2704 | exec2_list[i].flags = 0; | |
2705 | } | |
2706 | ||
cf6e7bac | 2707 | err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL); |
2889caa9 | 2708 | if (exec2.flags & __EXEC_HAS_RELOC) { |
9aab8bff | 2709 | struct drm_i915_gem_exec_object __user *user_exec_list = |
3ed605bc | 2710 | u64_to_user_ptr(args->buffers_ptr); |
9aab8bff | 2711 | |
54cf91dc | 2712 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff | 2713 | for (i = 0; i < args->buffer_count; i++) { |
2889caa9 CW |
2714 | if (!(exec2_list[i].offset & UPDATE)) |
2715 | continue; | |
2716 | ||
934acce3 | 2717 | exec2_list[i].offset = |
2889caa9 CW |
2718 | gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK); |
2719 | exec2_list[i].offset &= PIN_OFFSET_MASK; | |
2720 | if (__copy_to_user(&user_exec_list[i].offset, | |
2721 | &exec2_list[i].offset, | |
2722 | sizeof(user_exec_list[i].offset))) | |
9aab8bff | 2723 | break; |
54cf91dc CW |
2724 | } |
2725 | } | |
2726 | ||
2098105e MH |
2727 | kvfree(exec_list); |
2728 | kvfree(exec2_list); | |
2889caa9 | 2729 | return err; |
54cf91dc CW |
2730 | } |
2731 | ||
2732 | int | |
6a20fe7b VS |
2733 | i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, |
2734 | struct drm_file *file) | |
54cf91dc | 2735 | { |
d0bf4582 | 2736 | struct drm_i915_private *i915 = to_i915(dev); |
54cf91dc | 2737 | struct drm_i915_gem_execbuffer2 *args = data; |
2889caa9 | 2738 | struct drm_i915_gem_exec_object2 *exec2_list; |
cf6e7bac | 2739 | struct drm_syncobj **fences = NULL; |
d710fc16 | 2740 | const size_t count = args->buffer_count; |
2889caa9 | 2741 | int err; |
54cf91dc | 2742 | |
d710fc16 | 2743 | if (!check_buffer_count(count)) { |
d0bf4582 | 2744 | drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count); |
54cf91dc CW |
2745 | return -EINVAL; |
2746 | } | |
2747 | ||
00aff3f6 TU |
2748 | err = i915_gem_check_execbuffer(args); |
2749 | if (err) | |
2750 | return err; | |
2889caa9 CW |
2751 | |
2752 | /* Allocate an extra slot for use by the command parser */ | |
d710fc16 | 2753 | exec2_list = kvmalloc_array(count + 1, eb_element_size(), |
0ee931c4 | 2754 | __GFP_NOWARN | GFP_KERNEL); |
54cf91dc | 2755 | if (exec2_list == NULL) { |
d0bf4582 WK |
2756 | drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", |
2757 | count); | |
54cf91dc CW |
2758 | return -ENOMEM; |
2759 | } | |
2889caa9 CW |
2760 | if (copy_from_user(exec2_list, |
2761 | u64_to_user_ptr(args->buffers_ptr), | |
d710fc16 | 2762 | sizeof(*exec2_list) * count)) { |
d0bf4582 | 2763 | drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count); |
2098105e | 2764 | kvfree(exec2_list); |
54cf91dc CW |
2765 | return -EFAULT; |
2766 | } | |
2767 | ||
cf6e7bac JE |
2768 | if (args->flags & I915_EXEC_FENCE_ARRAY) { |
2769 | fences = get_fence_array(args, file); | |
2770 | if (IS_ERR(fences)) { | |
2771 | kvfree(exec2_list); | |
2772 | return PTR_ERR(fences); | |
2773 | } | |
2774 | } | |
2775 | ||
2776 | err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences); | |
2889caa9 CW |
2777 | |
2778 | /* | |
2779 | * Now that we have begun execution of the batchbuffer, we ignore | |
2780 | * any new error after this point. Also given that we have already | |
2781 | * updated the associated relocations, we try to write out the current | |
2782 | * object locations irrespective of any error. | |
2783 | */ | |
2784 | if (args->flags & __EXEC_HAS_RELOC) { | |
d593d992 | 2785 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
2889caa9 CW |
2786 | u64_to_user_ptr(args->buffers_ptr); |
2787 | unsigned int i; | |
9aab8bff | 2788 | |
2889caa9 | 2789 | /* Copy the new buffer offsets back to the user's exec list. */ |
594cc251 LT |
2790 | /* |
2791 | * Note: count * sizeof(*user_exec_list) does not overflow, | |
2792 | * because we checked 'count' in check_buffer_count(). | |
2793 | * | |
2794 | * And this range already got effectively checked earlier | |
2795 | * when we did the "copy_from_user()" above. | |
2796 | */ | |
2797 | if (!user_access_begin(user_exec_list, count * sizeof(*user_exec_list))) | |
8f4faed0 | 2798 | goto end; |
594cc251 | 2799 | |
9aab8bff | 2800 | for (i = 0; i < args->buffer_count; i++) { |
2889caa9 CW |
2801 | if (!(exec2_list[i].offset & UPDATE)) |
2802 | continue; | |
2803 | ||
934acce3 | 2804 | exec2_list[i].offset = |
2889caa9 CW |
2805 | gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK); |
2806 | unsafe_put_user(exec2_list[i].offset, | |
2807 | &user_exec_list[i].offset, | |
2808 | end_user); | |
54cf91dc | 2809 | } |
2889caa9 CW |
2810 | end_user: |
2811 | user_access_end(); | |
8f4faed0 | 2812 | end:; |
54cf91dc CW |
2813 | } |
2814 | ||
2889caa9 | 2815 | args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS; |
cf6e7bac | 2816 | put_fence_array(args, fences); |
2098105e | 2817 | kvfree(exec2_list); |
2889caa9 | 2818 | return err; |
54cf91dc | 2819 | } |