[linux-2.6-block.git] / drivers / gpu / drm / i915 / dvo_ivch.c

/*
 * Copyright © 2006 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Thomas Richter <thor@math.tu-berlin.de>
 *
 * Minor modifications (Dithering enable):
 *    Thomas Richter <thor@math.tu-berlin.de>
 *
 */

#include "dvo.h"

/*
 * register definitions for the i82807aa.
 *
 * Documentation on this chipset can be found in datasheet #29069001 at
 * intel.com.
 */

/*
 * VCH Revision & GMBus Base Addr
 */
#define VR00		0x00
# define VR00_BASE_ADDRESS_MASK		0x007f

/*
 * Functionality Enable
 */
#define VR01		0x01

/*
 * Enable the panel fitter
 */
# define VR01_PANEL_FIT_ENABLE		(1 << 3)
/*
 * Enables the LCD display.
 *
 * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
 */
# define VR01_LCD_ENABLE		(1 << 2)
/** Enables the DVO repeater. */
# define VR01_DVO_BYPASS_ENABLE		(1 << 1)
/** Enables the DVO clock */
# define VR01_DVO_ENABLE		(1 << 0)
/** Enable dithering for 18bpp panels. Not documented. */
# define VR01_DITHER_ENABLE             (1 << 4)

/*
 * LCD Interface Format
 */
#define VR10		0x10
/** Enables LVDS output instead of CMOS */
# define VR10_LVDS_ENABLE		(1 << 4)
/** Enables 18-bit LVDS output. */
# define VR10_INTERFACE_1X18		(0 << 2)
/** Enables 24-bit LVDS or CMOS output */
# define VR10_INTERFACE_1X24		(1 << 2)
/** Enables 2x18-bit LVDS or CMOS output. */
# define VR10_INTERFACE_2X18		(2 << 2)
/** Enables 2x24-bit LVDS output */
# define VR10_INTERFACE_2X24		(3 << 2)
/** Mask that defines the depth of the pipeline */
# define VR10_INTERFACE_DEPTH_MASK      (3 << 2)

/*
 * VR20 LCD Horizontal Display Size
 */
#define VR20	0x20

/*
 * LCD Vertical Display Size
 */
#define VR21	0x21

/*
 * Panel power down status
 */
#define VR30		0x30
/** Read only bit indicating that the panel is not in a safe poweroff state. */
# define VR30_PANEL_ON			(1 << 15)

#define VR40		0x40
# define VR40_STALL_ENABLE		(1 << 13)
# define VR40_VERTICAL_INTERP_ENABLE	(1 << 12)
# define VR40_ENHANCED_PANEL_FITTING	(1 << 11)
# define VR40_HORIZONTAL_INTERP_ENABLE	(1 << 10)
# define VR40_AUTO_RATIO_ENABLE		(1 << 9)
# define VR40_CLOCK_GATING_ENABLE	(1 << 8)

/*
 * Panel Fitting Vertical Ratio
 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
 */
#define VR41		0x41

/*
 * Panel Fitting Horizontal Ratio
 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
 */
#define VR42		0x42

/*
 * Horizontal Image Size
 */
#define VR43		0x43

/* VR80 GPIO 0
 */
#define VR80	    0x80
#define VR81	    0x81
#define VR82	    0x82
#define VR83	    0x83
#define VR84	    0x84
#define VR85	    0x85
#define VR86	    0x86
#define VR87	    0x87

/* VR88 GPIO 8
 */
#define VR88	    0x88

/* Graphics BIOS scratch 0
 */
#define VR8E	    0x8E
# define VR8E_PANEL_TYPE_MASK		(0xf << 0)
# define VR8E_PANEL_INTERFACE_CMOS	(0 << 4)
# define VR8E_PANEL_INTERFACE_LVDS	(1 << 4)
# define VR8E_FORCE_DEFAULT_PANEL	(1 << 5)

/* Graphics BIOS scratch 1
 */
#define VR8F	    0x8F
# define VR8F_VCH_PRESENT		(1 << 0)
# define VR8F_DISPLAY_CONN		(1 << 1)
# define VR8F_POWER_MASK		(0x3c)
# define VR8F_POWER_POS			(2)

/* Some Bios implementations do not restore the DVO state upon
 * resume from standby. Thus, this driver has to handle it
 * instead. The following list contains all registers that
 * require saving.
 */
static const uint16_t backup_addresses[] = {
	0x11, 0x12,
	0x18, 0x19, 0x1a, 0x1f,
	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
	0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
	0x8e, 0x8f,
	0x10		/* this must come last */
};


struct ivch_priv {
	bool quiet;

	uint16_t width, height;

	/* Register backup */

	uint16_t reg_backup[ARRAY_SIZE(backup_addresses)];
};


static void ivch_dump_regs(struct intel_dvo_device *dvo);
/**
 * Reads a register on the ivch.
 *
 * Each of the 256 registers are 16 bits long.
 */
static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
{
	struct ivch_priv *priv = dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	u8 out_buf[1];
	u8 in_buf[2];

	struct i2c_msg msgs[] = {
		{
			.addr = dvo->slave_addr,
			.flags = I2C_M_RD,
			.len = 0,
		},
		{
			.addr = 0,
			.flags = I2C_M_NOSTART,
			.len = 1,
			.buf = out_buf,
		},
		{
			.addr = dvo->slave_addr,
			.flags = I2C_M_RD | I2C_M_NOSTART,
			.len = 2,
			.buf = in_buf,
		}
	};

	out_buf[0] = addr;

	if (i2c_transfer(adapter, msgs, 3) == 3) {
		*data = (in_buf[1] << 8) | in_buf[0];
		return true;
	}

	if (!priv->quiet) {
		DRM_DEBUG_KMS("Unable to read register 0x%02x from "
				"%s:%02x.\n",
			  addr, adapter->name, dvo->slave_addr);
	}
	return false;
}

/** Writes a 16-bit register on the ivch */
static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
{
	struct ivch_priv *priv = dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	u8 out_buf[3];
	struct i2c_msg msg = {
		.addr = dvo->slave_addr,
		.flags = 0,
		.len = 3,
		.buf = out_buf,
	};

	out_buf[0] = addr;
	out_buf[1] = data & 0xff;
	out_buf[2] = data >> 8;

	if (i2c_transfer(adapter, &msg, 1) == 1)
		return true;

	if (!priv->quiet) {
		DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
			  addr, adapter->name, dvo->slave_addr);
	}

	return false;
}

/** Probes the given bus and slave address for an ivch */
static bool ivch_init(struct intel_dvo_device *dvo,
		      struct i2c_adapter *adapter)
{
	struct ivch_priv *priv;
	uint16_t temp;
	int i;

	priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
	if (priv == NULL)
		return false;

	dvo->i2c_bus = adapter;
	dvo->dev_priv = priv;
	priv->quiet = true;

	if (!ivch_read(dvo, VR00, &temp))
		goto out;
	priv->quiet = false;

	/* Since the identification bits are probably zeroes, which doesn't seem
	 * very unique, check that the value in the base address field matches
	 * the address it's responding on.
	 */
	if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
		DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
			  "(%d vs %d)\n",
			  (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
		goto out;
	}

	ivch_read(dvo, VR20, &priv->width);
	ivch_read(dvo, VR21, &priv->height);

	/* Make a backup of the registers to be able to restore them
	 * upon suspend.
	 */
	for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
		ivch_read(dvo, backup_addresses[i], priv->reg_backup + i);

	ivch_dump_regs(dvo);

	return true;

out:
	kfree(priv);
	return false;
}

static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
{
	return connector_status_connected;
}

static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
					    struct drm_display_mode *mode)
{
	if (mode->clock > 112000)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

/* Restore the DVO registers after a resume
 * from RAM. Registers have been saved during
 * the initialization.
 */
static void ivch_reset(struct intel_dvo_device *dvo)
{
	struct ivch_priv *priv = dvo->dev_priv;
	int i;

	DRM_DEBUG_KMS("Resetting the IVCH registers\n");

	ivch_write(dvo, VR10, 0x0000);

	for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
		ivch_write(dvo, backup_addresses[i], priv->reg_backup[i]);
}

/** Sets the power state of the panel connected to the ivch */
static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
{
	int i;
	uint16_t vr01, vr30, backlight;

	ivch_reset(dvo);

	/* Set the new power state of the panel. */
	if (!ivch_read(dvo, VR01, &vr01))
		return;

	if (enable)
		backlight = 1;
	else
		backlight = 0;

	ivch_write(dvo, VR80, backlight);

	if (enable)
		vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
	else
		vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);

	ivch_write(dvo, VR01, vr01);

	/* Wait for the panel to make its state transition */
	for (i = 0; i < 100; i++) {
		if (!ivch_read(dvo, VR30, &vr30))
			break;

		if (((vr30 & VR30_PANEL_ON) != 0) == enable)
			break;
		udelay(1000);
	}
	/* wait some more; vch may fail to resync sometimes without this */
	udelay(16 * 1000);
}

static bool ivch_get_hw_state(struct intel_dvo_device *dvo)
{
	uint16_t vr01;

	ivch_reset(dvo);

	/* Set the new power state of the panel. */
	if (!ivch_read(dvo, VR01, &vr01))
		return false;

	if (vr01 & VR01_LCD_ENABLE)
		return true;
	else
		return false;
}

static void ivch_mode_set(struct intel_dvo_device *dvo,
			  const struct drm_display_mode *mode,
			  const struct drm_display_mode *adjusted_mode)
{
	struct ivch_priv *priv = dvo->dev_priv;
	uint16_t vr40 = 0;
	uint16_t vr01 = 0;
	uint16_t vr10;

	ivch_reset(dvo);

	vr10 = priv->reg_backup[ARRAY_SIZE(backup_addresses) - 1];

	/* Enable dithering for 18 bpp pipelines */
	vr10 &= VR10_INTERFACE_DEPTH_MASK;
	if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18)
		vr01 = VR01_DITHER_ENABLE;

	vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
		VR40_HORIZONTAL_INTERP_ENABLE);

	if (mode->hdisplay != adjusted_mode->crtc_hdisplay ||
	    mode->vdisplay != adjusted_mode->crtc_vdisplay) {
		uint16_t x_ratio, y_ratio;

		vr01 |= VR01_PANEL_FIT_ENABLE;
		vr40 |= VR40_CLOCK_GATING_ENABLE;
		x_ratio = (((mode->hdisplay - 1) << 16) /
			   (adjusted_mode->crtc_hdisplay - 1)) >> 2;
		y_ratio = (((mode->vdisplay - 1) << 16) /
			   (adjusted_mode->crtc_vdisplay - 1)) >> 2;
		ivch_write(dvo, VR42, x_ratio);
		ivch_write(dvo, VR41, y_ratio);
	} else {
		vr01 &= ~VR01_PANEL_FIT_ENABLE;
		vr40 &= ~VR40_CLOCK_GATING_ENABLE;
	}
	vr40 &= ~VR40_AUTO_RATIO_ENABLE;

	ivch_write(dvo, VR01, vr01);
	ivch_write(dvo, VR40, vr40);
}

static void ivch_dump_regs(struct intel_dvo_device *dvo)
{
	uint16_t val;

	ivch_read(dvo, VR00, &val);
	DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
	ivch_read(dvo, VR01, &val);
	DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
	ivch_read(dvo, VR10, &val);
	DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
	ivch_read(dvo, VR30, &val);
	DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
	ivch_read(dvo, VR40, &val);
	DRM_DEBUG_KMS("VR40: 0x%04x\n", val);

	/* GPIO registers */
	ivch_read(dvo, VR80, &val);
	DRM_DEBUG_KMS("VR80: 0x%04x\n", val);
	ivch_read(dvo, VR81, &val);
	DRM_DEBUG_KMS("VR81: 0x%04x\n", val);
	ivch_read(dvo, VR82, &val);
	DRM_DEBUG_KMS("VR82: 0x%04x\n", val);
	ivch_read(dvo, VR83, &val);
	DRM_DEBUG_KMS("VR83: 0x%04x\n", val);
	ivch_read(dvo, VR84, &val);
	DRM_DEBUG_KMS("VR84: 0x%04x\n", val);
	ivch_read(dvo, VR85, &val);
	DRM_DEBUG_KMS("VR85: 0x%04x\n", val);
	ivch_read(dvo, VR86, &val);
	DRM_DEBUG_KMS("VR86: 0x%04x\n", val);
	ivch_read(dvo, VR87, &val);
	DRM_DEBUG_KMS("VR87: 0x%04x\n", val);
	ivch_read(dvo, VR88, &val);
	DRM_DEBUG_KMS("VR88: 0x%04x\n", val);

	/* Scratch register 0 - AIM Panel type */
	ivch_read(dvo, VR8E, &val);
	DRM_DEBUG_KMS("VR8E: 0x%04x\n", val);

	/* Scratch register 1 - Status register */
	ivch_read(dvo, VR8F, &val);
	DRM_DEBUG_KMS("VR8F: 0x%04x\n", val);
}

static void ivch_destroy(struct intel_dvo_device *dvo)
{
	struct ivch_priv *priv = dvo->dev_priv;

	if (priv) {
		kfree(priv);
		dvo->dev_priv = NULL;
	}
}

const struct intel_dvo_dev_ops ivch_ops = {
	.init = ivch_init,
	.dpms = ivch_dpms,
	.get_hw_state = ivch_get_hw_state,
	.mode_valid = ivch_mode_valid,
	.mode_set = ivch_mode_set,
	.detect = ivch_detect,
	.dump_regs = ivch_dump_regs,
	.destroy = ivch_destroy,
};
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright © 2006 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
ac3f918d	25	* Thomas Richter <thor@math.tu-berlin.de>
79e53945	26	*
b728d726 TR	27	* Minor modifications (Dithering enable):
	28	* Thomas Richter <thor@math.tu-berlin.de>
	29	*
79e53945 JB	30	*/
	31
	32	#include "dvo.h"
	33
	34	/*
	35	* register definitions for the i82807aa.
	36	*
	37	* Documentation on this chipset can be found in datasheet #29069001 at
	38	* intel.com.
	39	*/
	40
	41	/*
	42	* VCH Revision & GMBus Base Addr
	43	*/
	44	#define VR00 0x00
	45	# define VR00_BASE_ADDRESS_MASK 0x007f
	46
	47	/*
	48	* Functionality Enable
	49	*/
	50	#define VR01 0x01
	51
	52	/*
	53	* Enable the panel fitter
	54	*/
	55	# define VR01_PANEL_FIT_ENABLE (1 << 3)
	56	/*
	57	* Enables the LCD display.
	58	*
	59	* This must not be set while VR01_DVO_BYPASS_ENABLE is set.
	60	*/
	61	# define VR01_LCD_ENABLE (1 << 2)
	62	/** Enables the DVO repeater. */
	63	# define VR01_DVO_BYPASS_ENABLE (1 << 1)
	64	/** Enables the DVO clock */
	65	# define VR01_DVO_ENABLE (1 << 0)
b728d726 TR	66	/** Enable dithering for 18bpp panels. Not documented. */
b728d726 TR	67	# define VR01_DITHER_ENABLE (1 << 4)
79e53945 JB	68
	69	/*
	70	* LCD Interface Format
	71	*/
	72	#define VR10 0x10
	73	/** Enables LVDS output instead of CMOS */
	74	# define VR10_LVDS_ENABLE (1 << 4)
	75	/** Enables 18-bit LVDS output. */
	76	# define VR10_INTERFACE_1X18 (0 << 2)
	77	/** Enables 24-bit LVDS or CMOS output */
	78	# define VR10_INTERFACE_1X24 (1 << 2)
	79	/** Enables 2x18-bit LVDS or CMOS output. */
	80	# define VR10_INTERFACE_2X18 (2 << 2)
	81	/** Enables 2x24-bit LVDS output */
	82	# define VR10_INTERFACE_2X24 (3 << 2)
b728d726 TR	83	/** Mask that defines the depth of the pipeline */
b728d726 TR	84	# define VR10_INTERFACE_DEPTH_MASK (3 << 2)
79e53945 JB	85
	86	/*
	87	* VR20 LCD Horizontal Display Size
	88	*/
	89	#define VR20 0x20
	90
	91	/*
	92	* LCD Vertical Display Size
	93	*/
ac3f918d	94	#define VR21 0x21
79e53945 JB	95
	96	/*
	97	* Panel power down status
	98	*/
	99	#define VR30 0x30
	100	/** Read only bit indicating that the panel is not in a safe poweroff state. */
	101	# define VR30_PANEL_ON (1 << 15)
	102
	103	#define VR40 0x40
	104	# define VR40_STALL_ENABLE (1 << 13)
	105	# define VR40_VERTICAL_INTERP_ENABLE (1 << 12)
	106	# define VR40_ENHANCED_PANEL_FITTING (1 << 11)
	107	# define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10)
	108	# define VR40_AUTO_RATIO_ENABLE (1 << 9)
	109	# define VR40_CLOCK_GATING_ENABLE (1 << 8)
	110
	111	/*
	112	* Panel Fitting Vertical Ratio
	113	* (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
	114	*/
	115	#define VR41 0x41
	116
	117	/*
	118	* Panel Fitting Horizontal Ratio
	119	* (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
	120	*/
	121	#define VR42 0x42
	122
	123	/*
	124	* Horizontal Image Size
	125	*/
	126	#define VR43 0x43
	127
	128	/* VR80 GPIO 0
	129	*/
	130	#define VR80 0x80
	131	#define VR81 0x81
	132	#define VR82 0x82
	133	#define VR83 0x83
	134	#define VR84 0x84
	135	#define VR85 0x85
	136	#define VR86 0x86
	137	#define VR87 0x87
	138
	139	/* VR88 GPIO 8
	140	*/
	141	#define VR88 0x88
	142
	143	/* Graphics BIOS scratch 0
	144	*/
	145	#define VR8E 0x8E
	146	# define VR8E_PANEL_TYPE_MASK (0xf << 0)
	147	# define VR8E_PANEL_INTERFACE_CMOS (0 << 4)
	148	# define VR8E_PANEL_INTERFACE_LVDS (1 << 4)
	149	# define VR8E_FORCE_DEFAULT_PANEL (1 << 5)
	150
	151	/* Graphics BIOS scratch 1
	152	*/
	153	#define VR8F 0x8F
	154	# define VR8F_VCH_PRESENT (1 << 0)
	155	# define VR8F_DISPLAY_CONN (1 << 1)
	156	# define VR8F_POWER_MASK (0x3c)
	157	# define VR8F_POWER_POS (2)
	158
ac3f918d TR	159	/* Some Bios implementations do not restore the DVO state upon
	160	* resume from standby. Thus, this driver has to handle it
	161	* instead. The following list contains all registers that
	162	* require saving.
	163	*/
	164	static const uint16_t backup_addresses[] = {
	165	0x11, 0x12,
	166	0x18, 0x19, 0x1a, 0x1f,
	167	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
	168	0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
	169	0x8e, 0x8f,
	170	0x10 /* this must come last */
	171	};
	172
79e53945 JB	173
	174	struct ivch_priv {
	175	bool quiet;
	176
	177	uint16_t width, height;
ac3f918d TR	178
	179	/* Register backup */
	180
	181	uint16_t reg_backup[ARRAY_SIZE(backup_addresses)];
79e53945 JB	182	};
	183
	184
	185	static void ivch_dump_regs(struct intel_dvo_device *dvo);
79e53945 JB	186	/**
	187	* Reads a register on the ivch.
	188	*
	189	* Each of the 256 registers are 16 bits long.
	190	*/
	191	static bool ivch_read(struct intel_dvo_device dvo, int addr, uint16_t data)
	192	{
	193	struct ivch_priv *priv = dvo->dev_priv;
f9c10a9b	194	struct i2c_adapter *adapter = dvo->i2c_bus;
79e53945 JB	195	u8 out_buf[1];
	196	u8 in_buf[2];
	197
	198	struct i2c_msg msgs[] = {
	199	{
f9c10a9b	200	.addr = dvo->slave_addr,
79e53945 JB	201	.flags = I2C_M_RD,
	202	.len = 0,
	203	},
	204	{
	205	.addr = 0,
	206	.flags = I2C_M_NOSTART,
	207	.len = 1,
	208	.buf = out_buf,
	209	},
	210	{
f9c10a9b	211	.addr = dvo->slave_addr,
79e53945 JB	212	.flags = I2C_M_RD \| I2C_M_NOSTART,
	213	.len = 2,
	214	.buf = in_buf,
	215	}
	216	};
	217
	218	out_buf[0] = addr;
	219
f899fc64	220	if (i2c_transfer(adapter, msgs, 3) == 3) {
79e53945 JB	221	*data = (in_buf[1] << 8) \| in_buf[0];
79e53945 JB	222	return true;
6ed6bd84	223	}
79e53945 JB	224
79e53945 JB	225	if (!priv->quiet) {
d0c3b04a ZY	226	DRM_DEBUG_KMS("Unable to read register 0x%02x from "
d0c3b04a ZY	227	"%s:%02x.\n",
f899fc64	228	addr, adapter->name, dvo->slave_addr);
79e53945 JB	229	}
	230	return false;
	231	}
	232
	233	/** Writes a 16-bit register on the ivch */
	234	static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
	235	{
	236	struct ivch_priv *priv = dvo->dev_priv;
f9c10a9b	237	struct i2c_adapter *adapter = dvo->i2c_bus;
79e53945 JB	238	u8 out_buf[3];
79e53945 JB	239	struct i2c_msg msg = {
f9c10a9b	240	.addr = dvo->slave_addr,
79e53945 JB	241	.flags = 0,
	242	.len = 3,
	243	.buf = out_buf,
	244	};
	245
	246	out_buf[0] = addr;
	247	out_buf[1] = data & 0xff;
	248	out_buf[2] = data >> 8;
	249
f899fc64	250	if (i2c_transfer(adapter, &msg, 1) == 1)
79e53945 JB	251	return true;
	252
	253	if (!priv->quiet) {
d0c3b04a	254	DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
f899fc64	255	addr, adapter->name, dvo->slave_addr);
79e53945 JB	256	}
	257
	258	return false;
	259	}
	260
	261	/** Probes the given bus and slave address for an ivch */
	262	static bool ivch_init(struct intel_dvo_device *dvo,
f9c10a9b	263	struct i2c_adapter *adapter)
79e53945 JB	264	{
	265	struct ivch_priv *priv;
	266	uint16_t temp;
ac3f918d	267	int i;
79e53945 JB	268
	269	priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
	270	if (priv == NULL)
	271	return false;
	272
f9c10a9b	273	dvo->i2c_bus = adapter;
79e53945 JB	274	dvo->dev_priv = priv;
	275	priv->quiet = true;
	276
	277	if (!ivch_read(dvo, VR00, &temp))
	278	goto out;
	279	priv->quiet = false;
	280
	281	/* Since the identification bits are probably zeroes, which doesn't seem
	282	* very unique, check that the value in the base address field matches
	283	* the address it's responding on.
	284	*/
	285	if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
d0c3b04a	286	DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
79e53945 JB	287	"(%d vs %d)\n",
	288	(temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
	289	goto out;
	290	}
	291
	292	ivch_read(dvo, VR20, &priv->width);
	293	ivch_read(dvo, VR21, &priv->height);
	294
ac3f918d TR	295	/* Make a backup of the registers to be able to restore them
	296	* upon suspend.
	297	*/
	298	for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
	299	ivch_read(dvo, backup_addresses[i], priv->reg_backup + i);
	300
	301	ivch_dump_regs(dvo);
	302
79e53945 JB	303	return true;
	304
	305	out:
	306	kfree(priv);
	307	return false;
	308	}
	309
	310	static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
	311	{
	312	return connector_status_connected;
	313	}
	314
	315	static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
	316	struct drm_display_mode *mode)
	317	{
	318	if (mode->clock > 112000)
	319	return MODE_CLOCK_HIGH;
	320
	321	return MODE_OK;
	322	}
	323
ac3f918d TR	324	/* Restore the DVO registers after a resume
	325	* from RAM. Registers have been saved during
	326	* the initialization.
	327	*/
	328	static void ivch_reset(struct intel_dvo_device *dvo)
	329	{
	330	struct ivch_priv *priv = dvo->dev_priv;
	331	int i;
	332
	333	DRM_DEBUG_KMS("Resetting the IVCH registers\n");
	334
	335	ivch_write(dvo, VR10, 0x0000);
	336
	337	for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
	338	ivch_write(dvo, backup_addresses[i], priv->reg_backup[i]);
	339	}
	340
79e53945	341	/** Sets the power state of the panel connected to the ivch */
fac3274c	342	static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
79e53945 JB	343	{
	344	int i;
	345	uint16_t vr01, vr30, backlight;
	346
ac3f918d TR	347	ivch_reset(dvo);
ac3f918d TR	348
79e53945 JB	349	/* Set the new power state of the panel. */
	350	if (!ivch_read(dvo, VR01, &vr01))
	351	return;
	352
fac3274c	353	if (enable)
79e53945 JB	354	backlight = 1;
	355	else
	356	backlight = 0;
ac3f918d	357
79e53945 JB	358	ivch_write(dvo, VR80, backlight);
79e53945 JB	359
fac3274c	360	if (enable)
79e53945 JB	361	vr01 \|= VR01_LCD_ENABLE \| VR01_DVO_ENABLE;
	362	else
	363	vr01 &= ~(VR01_LCD_ENABLE \| VR01_DVO_ENABLE);
	364
	365	ivch_write(dvo, VR01, vr01);
	366
	367	/* Wait for the panel to make its state transition */
	368	for (i = 0; i < 100; i++) {
	369	if (!ivch_read(dvo, VR30, &vr30))
	370	break;
	371
fac3274c	372	if (((vr30 & VR30_PANEL_ON) != 0) == enable)
79e53945 JB	373	break;
	374	udelay(1000);
	375	}
	376	/* wait some more; vch may fail to resync sometimes without this */
	377	udelay(16 * 1000);
	378	}
	379
732ce74f DV	380	static bool ivch_get_hw_state(struct intel_dvo_device *dvo)
	381	{
	382	uint16_t vr01;
	383
ac3f918d TR	384	ivch_reset(dvo);
ac3f918d TR	385
732ce74f DV	386	/* Set the new power state of the panel. */
	387	if (!ivch_read(dvo, VR01, &vr01))
	388	return false;
	389
	390	if (vr01 & VR01_LCD_ENABLE)
	391	return true;
	392	else
	393	return false;
	394	}
	395
79e53945	396	static void ivch_mode_set(struct intel_dvo_device *dvo,
7c5f93b0 VS	397	const struct drm_display_mode *mode,
7c5f93b0 VS	398	const struct drm_display_mode *adjusted_mode)
79e53945	399	{
ac3f918d	400	struct ivch_priv *priv = dvo->dev_priv;
79e53945	401	uint16_t vr40 = 0;
b728d726 TR	402	uint16_t vr01 = 0;
	403	uint16_t vr10;
	404
ac3f918d TR	405	ivch_reset(dvo);
	406
	407	vr10 = priv->reg_backup[ARRAY_SIZE(backup_addresses) - 1];
	408
b728d726 TR	409	/* Enable dithering for 18 bpp pipelines */
	410	vr10 &= VR10_INTERFACE_DEPTH_MASK;
	411	if (vr10 == VR10_INTERFACE_2X18 \|\| vr10 == VR10_INTERFACE_1X18)
	412	vr01 = VR01_DITHER_ENABLE;
79e53945	413
79e53945 JB	414	vr40 = (VR40_STALL_ENABLE \| VR40_VERTICAL_INTERP_ENABLE \|
	415	VR40_HORIZONTAL_INTERP_ENABLE);
	416
aad941d5 VS	417	if (mode->hdisplay != adjusted_mode->crtc_hdisplay \|\|
aad941d5 VS	418	mode->vdisplay != adjusted_mode->crtc_vdisplay) {
79e53945 JB	419	uint16_t x_ratio, y_ratio;
	420
	421	vr01 \|= VR01_PANEL_FIT_ENABLE;
ac3f918d	422	vr40 \|= VR40_CLOCK_GATING_ENABLE;
79e53945	423	x_ratio = (((mode->hdisplay - 1) << 16) /
aad941d5	424	(adjusted_mode->crtc_hdisplay - 1)) >> 2;
79e53945	425	y_ratio = (((mode->vdisplay - 1) << 16) /
aad941d5	426	(adjusted_mode->crtc_vdisplay - 1)) >> 2;
0206e353 AJ	427	ivch_write(dvo, VR42, x_ratio);
0206e353 AJ	428	ivch_write(dvo, VR41, y_ratio);
79e53945 JB	429	} else {
	430	vr01 &= ~VR01_PANEL_FIT_ENABLE;
	431	vr40 &= ~VR40_CLOCK_GATING_ENABLE;
	432	}
	433	vr40 &= ~VR40_AUTO_RATIO_ENABLE;
	434
	435	ivch_write(dvo, VR01, vr01);
	436	ivch_write(dvo, VR40, vr40);
79e53945 JB	437	}
	438
	439	static void ivch_dump_regs(struct intel_dvo_device *dvo)
	440	{
	441	uint16_t val;
	442
	443	ivch_read(dvo, VR00, &val);
29139e4b	444	DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
79e53945	445	ivch_read(dvo, VR01, &val);
29139e4b	446	DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
b728d726 TR	447	ivch_read(dvo, VR10, &val);
b728d726 TR	448	DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
79e53945	449	ivch_read(dvo, VR30, &val);
29139e4b	450	DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
79e53945	451	ivch_read(dvo, VR40, &val);
29139e4b	452	DRM_DEBUG_KMS("VR40: 0x%04x\n", val);
79e53945 JB	453
	454	/* GPIO registers */
	455	ivch_read(dvo, VR80, &val);
29139e4b	456	DRM_DEBUG_KMS("VR80: 0x%04x\n", val);
79e53945	457	ivch_read(dvo, VR81, &val);
29139e4b	458	DRM_DEBUG_KMS("VR81: 0x%04x\n", val);
79e53945	459	ivch_read(dvo, VR82, &val);
29139e4b	460	DRM_DEBUG_KMS("VR82: 0x%04x\n", val);
79e53945	461	ivch_read(dvo, VR83, &val);
29139e4b	462	DRM_DEBUG_KMS("VR83: 0x%04x\n", val);
79e53945	463	ivch_read(dvo, VR84, &val);
29139e4b	464	DRM_DEBUG_KMS("VR84: 0x%04x\n", val);
79e53945	465	ivch_read(dvo, VR85, &val);
29139e4b	466	DRM_DEBUG_KMS("VR85: 0x%04x\n", val);
79e53945	467	ivch_read(dvo, VR86, &val);
29139e4b	468	DRM_DEBUG_KMS("VR86: 0x%04x\n", val);
79e53945	469	ivch_read(dvo, VR87, &val);
29139e4b	470	DRM_DEBUG_KMS("VR87: 0x%04x\n", val);
79e53945	471	ivch_read(dvo, VR88, &val);
29139e4b	472	DRM_DEBUG_KMS("VR88: 0x%04x\n", val);
79e53945 JB	473
	474	/* Scratch register 0 - AIM Panel type */
	475	ivch_read(dvo, VR8E, &val);
29139e4b	476	DRM_DEBUG_KMS("VR8E: 0x%04x\n", val);
79e53945 JB	477
	478	/* Scratch register 1 - Status register */
	479	ivch_read(dvo, VR8F, &val);
29139e4b	480	DRM_DEBUG_KMS("VR8F: 0x%04x\n", val);
79e53945 JB	481	}
79e53945 JB	482
79e53945 JB	483	static void ivch_destroy(struct intel_dvo_device *dvo)
	484	{
	485	struct ivch_priv *priv = dvo->dev_priv;
	486
	487	if (priv) {
	488	kfree(priv);
	489	dvo->dev_priv = NULL;
	490	}
	491	}
	492
0f555644	493	const struct intel_dvo_dev_ops ivch_ops = {
79e53945 JB	494	.init = ivch_init,
79e53945 JB	495	.dpms = ivch_dpms,
732ce74f	496	.get_hw_state = ivch_get_hw_state,
79e53945 JB	497	.mode_valid = ivch_mode_valid,
	498	.mode_set = ivch_mode_set,
	499	.detect = ivch_detect,
	500	.dump_regs = ivch_dump_regs,
	501	.destroy = ivch_destroy,
	502	};