[linux-2.6-block.git] / drivers / gpu / drm / i915 / dvo_ch7xxx.c

/**************************************************************************

Copyright © 2006 Dave Airlie

All Rights Reserved.

Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

**************************************************************************/

#include "dvo.h"

#define CH7xxx_REG_VID		0x4a
#define CH7xxx_REG_DID		0x4b

#define CH7011_VID		0x83 /* 7010 as well */
#define CH7009A_VID		0x84
#define CH7009B_VID		0x85
#define CH7301_VID		0x95

#define CH7xxx_VID		0x84
#define CH7xxx_DID		0x17

#define CH7xxx_NUM_REGS		0x4c

#define CH7xxx_CM		0x1c
#define CH7xxx_CM_XCM		(1<<0)
#define CH7xxx_CM_MCP		(1<<2)
#define CH7xxx_INPUT_CLOCK	0x1d
#define CH7xxx_GPIO		0x1e
#define CH7xxx_GPIO_HPIR	(1<<3)
#define CH7xxx_IDF		0x1f

#define CH7xxx_IDF_HSP		(1<<3)
#define CH7xxx_IDF_VSP		(1<<4)

#define CH7xxx_CONNECTION_DETECT 0x20
#define CH7xxx_CDET_DVI		(1<<5)

#define CH7301_DAC_CNTL		0x21
#define CH7301_HOTPLUG		0x23
#define CH7xxx_TCTL		0x31
#define CH7xxx_TVCO		0x32
#define CH7xxx_TPCP		0x33
#define CH7xxx_TPD		0x34
#define CH7xxx_TPVT		0x35
#define CH7xxx_TLPF		0x36
#define CH7xxx_TCT		0x37
#define CH7301_TEST_PATTERN	0x48

#define CH7xxx_PM		0x49
#define CH7xxx_PM_FPD		(1<<0)
#define CH7301_PM_DACPD0	(1<<1)
#define CH7301_PM_DACPD1	(1<<2)
#define CH7301_PM_DACPD2	(1<<3)
#define CH7xxx_PM_DVIL		(1<<6)
#define CH7xxx_PM_DVIP		(1<<7)

#define CH7301_SYNC_POLARITY	0x56
#define CH7301_SYNC_RGB_YUV	(1<<0)
#define CH7301_SYNC_POL_DVI	(1<<5)

/** @file
 * driver for the Chrontel 7xxx DVI chip over DVO.
 */

static struct ch7xxx_id_struct {
	uint8_t vid;
	char *name;
} ch7xxx_ids[] = {
	{ CH7011_VID, "CH7011" },
	{ CH7009A_VID, "CH7009A" },
	{ CH7009B_VID, "CH7009B" },
	{ CH7301_VID, "CH7301" },
};

struct ch7xxx_reg_state {
    uint8_t regs[CH7xxx_NUM_REGS];
};

struct ch7xxx_priv {
	bool quiet;

	struct ch7xxx_reg_state save_reg;
	struct ch7xxx_reg_state mode_reg;
	uint8_t save_TCTL, save_TPCP, save_TPD, save_TPVT;
	uint8_t save_TLPF, save_TCT, save_PM, save_IDF;
};

static void ch7xxx_save(struct intel_dvo_device *dvo);

static char *ch7xxx_get_id(uint8_t vid)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) {
		if (ch7xxx_ids[i].vid == vid)
			return ch7xxx_ids[i].name;
	}

	return NULL;
}

/** Reads an 8 bit register */
static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
{
	struct ch7xxx_priv *ch7xxx= dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
	u8 out_buf[2];
	u8 in_buf[2];

	struct i2c_msg msgs[] = {
		{
			.addr = dvo->slave_addr,
			.flags = 0,
			.len = 1,
			.buf = out_buf,
		},
		{
			.addr = dvo->slave_addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = in_buf,
		}
	};

	out_buf[0] = addr;
	out_buf[1] = 0;

	if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
		*ch = in_buf[0];
		return true;
	};

	if (!ch7xxx->quiet) {
		DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
			  addr, i2cbus->adapter.name, dvo->slave_addr);
	}
	return false;
}

/** Writes an 8 bit register */
static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
{
	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
	uint8_t out_buf[2];
	struct i2c_msg msg = {
		.addr = dvo->slave_addr,
		.flags = 0,
		.len = 2,
		.buf = out_buf,
	};

	out_buf[0] = addr;
	out_buf[1] = ch;

	if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
		return true;

	if (!ch7xxx->quiet) {
		DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
			  addr, i2cbus->adapter.name, dvo->slave_addr);
	}

	return false;
}

static bool ch7xxx_init(struct intel_dvo_device *dvo,
			struct i2c_adapter *adapter)
{
	/* this will detect the CH7xxx chip on the specified i2c bus */
	struct ch7xxx_priv *ch7xxx;
	uint8_t vendor, device;
	char *name;

	ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL);
	if (ch7xxx == NULL)
		return false;

	dvo->i2c_bus = adapter;
	dvo->dev_priv = ch7xxx;
	ch7xxx->quiet = true;

	if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor))
		goto out;

	name = ch7xxx_get_id(vendor);
	if (!name) {
		DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
				"slave %d.\n",
			  vendor, adapter->name, dvo->slave_addr);
		goto out;
	}


	if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device))
		goto out;

	if (device != CH7xxx_DID) {
		DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
				"slave %d.\n",
			  vendor, adapter->name, dvo->slave_addr);
		goto out;
	}

	ch7xxx->quiet = false;
	DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
		  name, vendor, device);
	return true;
out:
	kfree(ch7xxx);
	return false;
}

static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo)
{
	uint8_t cdet, orig_pm, pm;

	ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm);

	pm = orig_pm;
	pm &= ~CH7xxx_PM_FPD;
	pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP;

	ch7xxx_writeb(dvo, CH7xxx_PM, pm);

	ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet);

	ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm);

	if (cdet & CH7xxx_CDET_DVI)
		return connector_status_connected;
	return connector_status_disconnected;
}

static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo,
					      struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
			    struct drm_display_mode *mode,
			    struct drm_display_mode *adjusted_mode)
{
	uint8_t tvco, tpcp, tpd, tlpf, idf;

	if (mode->clock <= 65000) {
		tvco = 0x23;
		tpcp = 0x08;
		tpd = 0x16;
		tlpf = 0x60;
	} else {
		tvco = 0x2d;
		tpcp = 0x06;
		tpd = 0x26;
		tlpf = 0xa0;
	}

	ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00);
	ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco);
	ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp);
	ch7xxx_writeb(dvo, CH7xxx_TPD, tpd);
	ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30);
	ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf);
	ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00);

	ch7xxx_readb(dvo, CH7xxx_IDF, &idf);

	idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
		idf |= CH7xxx_IDF_HSP;

	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
		idf |= CH7xxx_IDF_HSP;

	ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
}

/* set the CH7xxx power state */
static void ch7xxx_dpms(struct intel_dvo_device *dvo, int mode)
{
	if (mode == DRM_MODE_DPMS_ON)
		ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP);
	else
		ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD);
}

static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
{
	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
	int i;

	for (i = 0; i < CH7xxx_NUM_REGS; i++) {
		if ((i % 8) == 0 )
			DRM_LOG_KMS("\n %02X: ", i);
		DRM_LOG_KMS("%02X ", ch7xxx->mode_reg.regs[i]);
	}
}

static void ch7xxx_save(struct intel_dvo_device *dvo)
{
	struct ch7xxx_priv *ch7xxx= dvo->dev_priv;

	ch7xxx_readb(dvo, CH7xxx_TCTL, &ch7xxx->save_TCTL);
	ch7xxx_readb(dvo, CH7xxx_TPCP, &ch7xxx->save_TPCP);
	ch7xxx_readb(dvo, CH7xxx_TPD, &ch7xxx->save_TPD);
	ch7xxx_readb(dvo, CH7xxx_TPVT, &ch7xxx->save_TPVT);
	ch7xxx_readb(dvo, CH7xxx_TLPF, &ch7xxx->save_TLPF);
	ch7xxx_readb(dvo, CH7xxx_PM, &ch7xxx->save_PM);
	ch7xxx_readb(dvo, CH7xxx_IDF, &ch7xxx->save_IDF);
}

static void ch7xxx_restore(struct intel_dvo_device *dvo)
{
	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

	ch7xxx_writeb(dvo, CH7xxx_TCTL, ch7xxx->save_TCTL);
	ch7xxx_writeb(dvo, CH7xxx_TPCP, ch7xxx->save_TPCP);
	ch7xxx_writeb(dvo, CH7xxx_TPD, ch7xxx->save_TPD);
	ch7xxx_writeb(dvo, CH7xxx_TPVT, ch7xxx->save_TPVT);
	ch7xxx_writeb(dvo, CH7xxx_TLPF, ch7xxx->save_TLPF);
	ch7xxx_writeb(dvo, CH7xxx_IDF, ch7xxx->save_IDF);
	ch7xxx_writeb(dvo, CH7xxx_PM, ch7xxx->save_PM);
}

static void ch7xxx_destroy(struct intel_dvo_device *dvo)
{
	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;

	if (ch7xxx) {
		kfree(ch7xxx);
		dvo->dev_priv = NULL;
	}
}

struct intel_dvo_dev_ops ch7xxx_ops = {
	.init = ch7xxx_init,
	.detect = ch7xxx_detect,
	.mode_valid = ch7xxx_mode_valid,
	.mode_set = ch7xxx_mode_set,
	.dpms = ch7xxx_dpms,
	.dump_regs = ch7xxx_dump_regs,
	.save = ch7xxx_save,
	.restore = ch7xxx_restore,
	.destroy = ch7xxx_destroy,
};
Commit	Line	Data
79e53945 JB	1	/**************************************************************************
	2
	3	Copyright © 2006 Dave Airlie
	4
	5	All Rights Reserved.
	6
	7	Permission is hereby granted, free of charge, to any person obtaining a
	8	copy of this software and associated documentation files (the
	9	"Software"), to deal in the Software without restriction, including
	10	without limitation the rights to use, copy, modify, merge, publish,
	11	distribute, sub license, and/or sell copies of the Software, and to
	12	permit persons to whom the Software is furnished to do so, subject to
	13	the following conditions:
	14
	15	The above copyright notice and this permission notice (including the
	16	next paragraph) shall be included in all copies or substantial portions
	17	of the Software.
	18
	19	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	20	OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	21	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
	22	IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	23	ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
	24	TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
	25	SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	26
	27	**************************************************************************/
	28
	29	#include "dvo.h"
	30
	31	#define CH7xxx_REG_VID 0x4a
	32	#define CH7xxx_REG_DID 0x4b
	33
	34	#define CH7011_VID 0x83 /* 7010 as well */
	35	#define CH7009A_VID 0x84
	36	#define CH7009B_VID 0x85
	37	#define CH7301_VID 0x95
	38
	39	#define CH7xxx_VID 0x84
	40	#define CH7xxx_DID 0x17
	41
	42	#define CH7xxx_NUM_REGS 0x4c
	43
	44	#define CH7xxx_CM 0x1c
	45	#define CH7xxx_CM_XCM (1<<0)
	46	#define CH7xxx_CM_MCP (1<<2)
	47	#define CH7xxx_INPUT_CLOCK 0x1d
	48	#define CH7xxx_GPIO 0x1e
	49	#define CH7xxx_GPIO_HPIR (1<<3)
	50	#define CH7xxx_IDF 0x1f
	51
	52	#define CH7xxx_IDF_HSP (1<<3)
	53	#define CH7xxx_IDF_VSP (1<<4)
	54
	55	#define CH7xxx_CONNECTION_DETECT 0x20
	56	#define CH7xxx_CDET_DVI (1<<5)
	57
	58	#define CH7301_DAC_CNTL 0x21
	59	#define CH7301_HOTPLUG 0x23
	60	#define CH7xxx_TCTL 0x31
	61	#define CH7xxx_TVCO 0x32
	62	#define CH7xxx_TPCP 0x33
	63	#define CH7xxx_TPD 0x34
	64	#define CH7xxx_TPVT 0x35
65	#define CH7xxx_TLPF 0x36
66	#define CH7xxx_TCT 0x37
67	#define CH7301_TEST_PATTERN 0x48
68
69	#define CH7xxx_PM 0x49
70	#define CH7xxx_PM_FPD (1<<0)
71	#define CH7301_PM_DACPD0 (1<<1)
72	#define CH7301_PM_DACPD1 (1<<2)
73	#define CH7301_PM_DACPD2 (1<<3)
74	#define CH7xxx_PM_DVIL (1<<6)
75	#define CH7xxx_PM_DVIP (1<<7)
76
77	#define CH7301_SYNC_POLARITY 0x56
78	#define CH7301_SYNC_RGB_YUV (1<<0)
79	#define CH7301_SYNC_POL_DVI (1<<5)
80
81	/** @file
82	* driver for the Chrontel 7xxx DVI chip over DVO.
83	*/
84
85	static struct ch7xxx_id_struct {
86	uint8_t vid;
87	char *name;
88	} ch7xxx_ids[] = {
89	{ CH7011_VID, "CH7011" },
90	{ CH7009A_VID, "CH7009A" },
91	{ CH7009B_VID, "CH7009B" },
92	{ CH7301_VID, "CH7301" },
93	};
94
95	struct ch7xxx_reg_state {
96	uint8_t regs[CH7xxx_NUM_REGS];
97	};
98
99	struct ch7xxx_priv {
100	bool quiet;
101
102	struct ch7xxx_reg_state save_reg;
103	struct ch7xxx_reg_state mode_reg;
104	uint8_t save_TCTL, save_TPCP, save_TPD, save_TPVT;
105	uint8_t save_TLPF, save_TCT, save_PM, save_IDF;
106	};
107
108	static void ch7xxx_save(struct intel_dvo_device *dvo);
109
110	static char *ch7xxx_get_id(uint8_t vid)
111	{
112	int i;
113
114	for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) {
115	if (ch7xxx_ids[i].vid == vid)
116	return ch7xxx_ids[i].name;
117	}
118
119	return NULL;
120	}
121
122	/** Reads an 8 bit register */
123	static bool ch7xxx_readb(struct intel_dvo_device dvo, int addr, uint8_t ch)
124	{
125	struct ch7xxx_priv *ch7xxx= dvo->dev_priv;
f9c10a9b KP	126	struct i2c_adapter *adapter = dvo->i2c_bus;
f9c10a9b KP	127	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
79e53945 JB	128	u8 out_buf[2];
	129	u8 in_buf[2];
	130
	131	struct i2c_msg msgs[] = {
	132	{
f9c10a9b	133	.addr = dvo->slave_addr,
79e53945 JB	134	.flags = 0,
	135	.len = 1,
	136	.buf = out_buf,
	137	},
	138	{
f9c10a9b	139	.addr = dvo->slave_addr,
79e53945 JB	140	.flags = I2C_M_RD,
	141	.len = 1,
	142	.buf = in_buf,
	143	}
	144	};
	145
	146	out_buf[0] = addr;
	147	out_buf[1] = 0;
	148
	149	if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
	150	*ch = in_buf[0];
	151	return true;
	152	};
	153
	154	if (!ch7xxx->quiet) {
d0c3b04a	155	DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
f9c10a9b	156	addr, i2cbus->adapter.name, dvo->slave_addr);
79e53945 JB	157	}
	158	return false;
	159	}
	160
	161	/** Writes an 8 bit register */
	162	static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
	163	{
	164	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
f9c10a9b KP	165	struct i2c_adapter *adapter = dvo->i2c_bus;
f9c10a9b KP	166	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
79e53945 JB	167	uint8_t out_buf[2];
79e53945 JB	168	struct i2c_msg msg = {
f9c10a9b	169	.addr = dvo->slave_addr,
79e53945 JB	170	.flags = 0,
	171	.len = 2,
	172	.buf = out_buf,
	173	};
	174
	175	out_buf[0] = addr;
	176	out_buf[1] = ch;
	177
	178	if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
	179	return true;
	180
	181	if (!ch7xxx->quiet) {
d0c3b04a	182	DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
f9c10a9b	183	addr, i2cbus->adapter.name, dvo->slave_addr);
79e53945 JB	184	}
	185
	186	return false;
	187	}
	188
	189	static bool ch7xxx_init(struct intel_dvo_device *dvo,
f9c10a9b	190	struct i2c_adapter *adapter)
79e53945 JB	191	{
	192	/* this will detect the CH7xxx chip on the specified i2c bus */
	193	struct ch7xxx_priv *ch7xxx;
	194	uint8_t vendor, device;
	195	char *name;
	196
	197	ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL);
	198	if (ch7xxx == NULL)
	199	return false;
	200
f9c10a9b	201	dvo->i2c_bus = adapter;
79e53945 JB	202	dvo->dev_priv = ch7xxx;
	203	ch7xxx->quiet = true;
	204
	205	if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor))
	206	goto out;
	207
	208	name = ch7xxx_get_id(vendor);
	209	if (!name) {
d0c3b04a ZY	210	DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
d0c3b04a ZY	211	"slave %d.\n",
f9c10a9b	212	vendor, adapter->name, dvo->slave_addr);
79e53945 JB	213	goto out;
	214	}
	215
	216
	217	if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device))
	218	goto out;
	219
	220	if (device != CH7xxx_DID) {
d0c3b04a ZY	221	DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
d0c3b04a ZY	222	"slave %d.\n",
f9c10a9b	223	vendor, adapter->name, dvo->slave_addr);
79e53945 JB	224	goto out;
	225	}
	226
	227	ch7xxx->quiet = false;
d0c3b04a	228	DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
79e53945 JB	229	name, vendor, device);
	230	return true;
	231	out:
	232	kfree(ch7xxx);
	233	return false;
	234	}
	235
	236	static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo)
	237	{
	238	uint8_t cdet, orig_pm, pm;
	239
	240	ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm);
	241
	242	pm = orig_pm;
	243	pm &= ~CH7xxx_PM_FPD;
	244	pm \|= CH7xxx_PM_DVIL \| CH7xxx_PM_DVIP;
	245
	246	ch7xxx_writeb(dvo, CH7xxx_PM, pm);
	247
	248	ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet);
	249
	250	ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm);
	251
	252	if (cdet & CH7xxx_CDET_DVI)
	253	return connector_status_connected;
	254	return connector_status_disconnected;
	255	}
	256
	257	static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo,
	258	struct drm_display_mode *mode)
	259	{
	260	if (mode->clock > 165000)
	261	return MODE_CLOCK_HIGH;
	262
	263	return MODE_OK;
	264	}
	265
	266	static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
	267	struct drm_display_mode *mode,
	268	struct drm_display_mode *adjusted_mode)
	269	{
	270	uint8_t tvco, tpcp, tpd, tlpf, idf;
	271
	272	if (mode->clock <= 65000) {
	273	tvco = 0x23;
	274	tpcp = 0x08;
	275	tpd = 0x16;
	276	tlpf = 0x60;
	277	} else {
	278	tvco = 0x2d;
	279	tpcp = 0x06;
	280	tpd = 0x26;
	281	tlpf = 0xa0;
	282	}
	283
	284	ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00);
	285	ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco);
	286	ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp);
	287	ch7xxx_writeb(dvo, CH7xxx_TPD, tpd);
	288	ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30);
	289	ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf);
	290	ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00);
	291
	292	ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
293
294	idf &= ~(CH7xxx_IDF_HSP \| CH7xxx_IDF_VSP);
295	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
296	idf \|= CH7xxx_IDF_HSP;
297
298	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
299	idf \|= CH7xxx_IDF_HSP;
300
301	ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
302	}
303
304	/* set the CH7xxx power state */
305	static void ch7xxx_dpms(struct intel_dvo_device *dvo, int mode)
306	{
307	if (mode == DRM_MODE_DPMS_ON)
308	ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL \| CH7xxx_PM_DVIP);
309	else
310	ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD);
311	}
312
313	static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
314	{
315	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
316	int i;
317
318	for (i = 0; i < CH7xxx_NUM_REGS; i++) {
319	if ((i % 8) == 0 )
d0c3b04a ZY	320	DRM_LOG_KMS("\n %02X: ", i);
d0c3b04a ZY	321	DRM_LOG_KMS("%02X ", ch7xxx->mode_reg.regs[i]);
79e53945 JB	322	}
	323	}
	324
	325	static void ch7xxx_save(struct intel_dvo_device *dvo)
	326	{
	327	struct ch7xxx_priv *ch7xxx= dvo->dev_priv;
	328
	329	ch7xxx_readb(dvo, CH7xxx_TCTL, &ch7xxx->save_TCTL);
	330	ch7xxx_readb(dvo, CH7xxx_TPCP, &ch7xxx->save_TPCP);
	331	ch7xxx_readb(dvo, CH7xxx_TPD, &ch7xxx->save_TPD);
	332	ch7xxx_readb(dvo, CH7xxx_TPVT, &ch7xxx->save_TPVT);
	333	ch7xxx_readb(dvo, CH7xxx_TLPF, &ch7xxx->save_TLPF);
	334	ch7xxx_readb(dvo, CH7xxx_PM, &ch7xxx->save_PM);
	335	ch7xxx_readb(dvo, CH7xxx_IDF, &ch7xxx->save_IDF);
	336	}
	337
	338	static void ch7xxx_restore(struct intel_dvo_device *dvo)
	339	{
	340	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
	341
	342	ch7xxx_writeb(dvo, CH7xxx_TCTL, ch7xxx->save_TCTL);
	343	ch7xxx_writeb(dvo, CH7xxx_TPCP, ch7xxx->save_TPCP);
	344	ch7xxx_writeb(dvo, CH7xxx_TPD, ch7xxx->save_TPD);
	345	ch7xxx_writeb(dvo, CH7xxx_TPVT, ch7xxx->save_TPVT);
	346	ch7xxx_writeb(dvo, CH7xxx_TLPF, ch7xxx->save_TLPF);
	347	ch7xxx_writeb(dvo, CH7xxx_IDF, ch7xxx->save_IDF);
	348	ch7xxx_writeb(dvo, CH7xxx_PM, ch7xxx->save_PM);
	349	}
	350
	351	static void ch7xxx_destroy(struct intel_dvo_device *dvo)
	352	{
	353	struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
	354
	355	if (ch7xxx) {
	356	kfree(ch7xxx);
	357	dvo->dev_priv = NULL;
	358	}
	359	}
	360
	361	struct intel_dvo_dev_ops ch7xxx_ops = {
	362	.init = ch7xxx_init,
	363	.detect = ch7xxx_detect,
	364	.mode_valid = ch7xxx_mode_valid,
	365	.mode_set = ch7xxx_mode_set,
	366	.dpms = ch7xxx_dpms,
	367	.dump_regs = ch7xxx_dump_regs,
	368	.save = ch7xxx_save,
	369	.restore = ch7xxx_restore,
	370	.destroy = ch7xxx_destroy,
	371	};