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Merge tag 'x86-asm-2024-03-11' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_tv.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29/** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ec7f29ff 36
79e53945 37#include "i915_drv.h"
f84a27f9 38#include "i915_reg.h"
ec7f29ff 39#include "intel_connector.h"
fd2b94a5 40#include "intel_crtc.h"
7785ae0b 41#include "intel_de.h"
2b874a02 42#include "intel_display_irq.h"
1d455f8d 43#include "intel_display_types.h"
1bba5543 44#include "intel_dpll.h"
dbeb38d9 45#include "intel_hotplug.h"
b13604c0 46#include "intel_load_detect.h"
efe57eea 47#include "intel_tv.h"
f84a27f9 48#include "intel_tv_regs.h"
79e53945
JB		 49
50enum tv_margin {
51 TV_MARGIN_LEFT, TV_MARGIN_TOP,
52 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
53};
54
ea5b213a
CW		 55struct intel_tv {
56 struct intel_encoder base;
57
79e53945 58 int type;
79e53945
JB		 59};
60
61struct video_levels {
db49296b
TU		 62 u16 blank, black;
63 u8 burst;
79e53945
JB		 64};
65
66struct color_conversion {
67 u16 ry, gy, by, ay;
68 u16 ru, gu, bu, au;
69 u16 rv, gv, bv, av;
70};
71
72static const u32 filter_table[] = {
73 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
74 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
75 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
76 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
77 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
78 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
79 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
80 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
81 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
82 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
83 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
84 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
85 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
86 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
87 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
88 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
89 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
90 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
91 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
92 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
93 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
94 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
95 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
96 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
97 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
98 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
99 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
100 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
101 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
102 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
103 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
104 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
105 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
106 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
107 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
108 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
109 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
110 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
111 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
112 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
113 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
114 0x2D002CC0, 0x30003640, 0x2D0036C0,
115 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
116 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
117 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
118 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
119 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
120 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
121 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
122 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
123 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
124 0x28003100, 0x28002F00, 0x00003100,
125};
126
127/*
128 * Color conversion values have 3 separate fixed point formats:
129 *
130 * 10 bit fields (ay, au)
131 * 1.9 fixed point (b.bbbbbbbbb)
132 * 11 bit fields (ry, by, ru, gu, gv)
133 * exp.mantissa (ee.mmmmmmmmm)
134 * ee = 00 = 10^-1 (0.mmmmmmmmm)
135 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
136 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
137 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
138 * 12 bit fields (gy, rv, bu)
139 * exp.mantissa (eee.mmmmmmmmm)
140 * eee = 000 = 10^-1 (0.mmmmmmmmm)
141 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
142 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
143 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
144 * eee = 100 = reserved
145 * eee = 101 = reserved
146 * eee = 110 = reserved
147 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
148 *
149 * Saturation and contrast are 8 bits, with their own representation:
150 * 8 bit field (saturation, contrast)
151 * exp.mantissa (ee.mmmmmm)
152 * ee = 00 = 10^-1 (0.mmmmmm)
153 * ee = 01 = 10^0 (m.mmmmm)
154 * ee = 10 = 10^1 (mm.mmmm)
155 * ee = 11 = 10^2 (mmm.mmm)
156 *
157 * Simple conversion function:
158 *
159 * static u32
160 * float_to_csc_11(float f)
161 * {
162 * u32 exp;
163 * u32 mant;
164 * u32 ret;
165 *
166 * if (f < 0)
167 * f = -f;
168 *
169 * if (f >= 1) {
170 * exp = 0x7;
0206e353 171 * mant = 1 << 8;
79e53945
JB		 172 * } else {
173 * for (exp = 0; exp < 3 && f < 0.5; exp++)
0206e353 174 * f *= 2.0;
79e53945
JB		 175 * mant = (f * (1 << 9) + 0.5);
176 * if (mant >= (1 << 9))
177 * mant = (1 << 9) - 1;
178 * }
179 * ret = (exp << 9) | mant;
180 * return ret;
181 * }
182 */
183
184/*
185 * Behold, magic numbers! If we plant them they might grow a big
186 * s-video cable to the sky... or something.
187 *
188 * Pre-converted to appropriate hex value.
189 */
190
191/*
192 * PAL & NTSC values for composite & s-video connections
193 */
194static const struct color_conversion ntsc_m_csc_composite = {
195 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 196 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
197 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 198};
199
200static const struct video_levels ntsc_m_levels_composite = {
201 .blank = 225, .black = 267, .burst = 113,
202};
203
204static const struct color_conversion ntsc_m_csc_svideo = {
ba01079c
ZW		 205 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
206 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
207 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 208};
209
210static const struct video_levels ntsc_m_levels_svideo = {
211 .blank = 266, .black = 316, .burst = 133,
212};
213
214static const struct color_conversion ntsc_j_csc_composite = {
215 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
ba01079c
ZW		 216 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
217 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
79e53945
JB		 218};
219
220static const struct video_levels ntsc_j_levels_composite = {
221 .blank = 225, .black = 225, .burst = 113,
222};
223
224static const struct color_conversion ntsc_j_csc_svideo = {
225 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
ba01079c
ZW		 226 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
227 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
79e53945
JB		 228};
229
230static const struct video_levels ntsc_j_levels_svideo = {
231 .blank = 266, .black = 266, .burst = 133,
232};
233
234static const struct color_conversion pal_csc_composite = {
235 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
ba01079c
ZW		 236 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
237 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
79e53945
JB		 238};
239
240static const struct video_levels pal_levels_composite = {
241 .blank = 237, .black = 237, .burst = 118,
242};
243
244static const struct color_conversion pal_csc_svideo = {
245 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
ba01079c
ZW		 246 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
247 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
79e53945
JB		 248};
249
250static const struct video_levels pal_levels_svideo = {
251 .blank = 280, .black = 280, .burst = 139,
252};
253
254static const struct color_conversion pal_m_csc_composite = {
255 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 256 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
257 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 258};
259
260static const struct video_levels pal_m_levels_composite = {
261 .blank = 225, .black = 267, .burst = 113,
262};
263
264static const struct color_conversion pal_m_csc_svideo = {
ba01079c
ZW		 265 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
266 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
267 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 268};
269
270static const struct video_levels pal_m_levels_svideo = {
271 .blank = 266, .black = 316, .burst = 133,
272};
273
274static const struct color_conversion pal_n_csc_composite = {
275 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 276 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
277 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 278};
279
280static const struct video_levels pal_n_levels_composite = {
281 .blank = 225, .black = 267, .burst = 118,
282};
283
284static const struct color_conversion pal_n_csc_svideo = {
ba01079c
ZW		 285 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
286 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
287 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 288};
289
290static const struct video_levels pal_n_levels_svideo = {
291 .blank = 266, .black = 316, .burst = 139,
292};
293
294/*
295 * Component connections
296 */
297static const struct color_conversion sdtv_csc_yprpb = {
ba01079c
ZW		 298 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
299 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
300 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
79e53945
JB		 301};
302
79e53945 303static const struct color_conversion hdtv_csc_yprpb = {
ba01079c
ZW		 304 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
305 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
306 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
79e53945
JB		 307};
308
79e53945
JB		 309static const struct video_levels component_levels = {
310 .blank = 279, .black = 279, .burst = 0,
311};
312
313
314struct tv_mode {
763a4a01 315 const char *name;
db49296b
TU		 316
317 u32 clock;
318 u16 refresh; /* in millihertz (for precision) */
4f503798 319 u8 oversample;
db49296b
TU		 320 u8 hsync_end;
321 u16 hblank_start, hblank_end, htotal;
322 bool progressive : 1, trilevel_sync : 1, component_only : 1;
323 u8 vsync_start_f1, vsync_start_f2, vsync_len;
324 bool veq_ena : 1;
325 u8 veq_start_f1, veq_start_f2, veq_len;
326 u8 vi_end_f1, vi_end_f2;
327 u16 nbr_end;
328 bool burst_ena : 1;
329 u8 hburst_start, hburst_len;
330 u8 vburst_start_f1;
331 u16 vburst_end_f1;
332 u8 vburst_start_f2;
333 u16 vburst_end_f2;
334 u8 vburst_start_f3;
335 u16 vburst_end_f3;
336 u8 vburst_start_f4;
337 u16 vburst_end_f4;
79e53945
JB		 338 /*
339 * subcarrier programming
340 */
db49296b
TU		 341 u16 dda2_size, dda3_size;
342 u8 dda1_inc;
343 u16 dda2_inc, dda3_inc;
79e53945 344 u32 sc_reset;
db49296b 345 bool pal_burst : 1;
79e53945
JB		 346 /*
347 * blank/black levels
348 */
349 const struct video_levels *composite_levels, *svideo_levels;
350 const struct color_conversion *composite_color, *svideo_color;
351 const u32 *filter_table;
79e53945
JB		 352};
353
354
355/*
356 * Sub carrier DDA
357 *
358 * I think this works as follows:
359 *
360 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
361 *
362 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
363 *
364 * So,
365 * dda1_ideal = subcarrier/pixel * 4096
366 * dda1_inc = floor (dda1_ideal)
367 * dda2 = dda1_ideal - dda1_inc
368 *
369 * then pick a ratio for dda2 that gives the closest approximation. If
370 * you can't get close enough, you can play with dda3 as well. This
371 * seems likely to happen when dda2 is small as the jumps would be larger
372 *
373 * To invert this,
374 *
375 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
376 *
377 * The constants below were all computed using a 107.520MHz clock
378 */
379
3930f18a 380/*
79e53945
JB		 381 * Register programming values for TV modes.
382 *
383 * These values account for -1s required.
384 */
005568be 385static const struct tv_mode tv_modes[] = {
79e53945
JB		 386 {
387 .name = "NTSC-M",
ba01079c 388 .clock = 108000,
23bd15ec 389 .refresh = 59940,
4f503798 390 .oversample = 8,
56f62308 391 .component_only = false,
79e53945
JB		 392 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
393
394 .hsync_end = 64, .hblank_end = 124,
395 .hblank_start = 836, .htotal = 857,
396
397 .progressive = false, .trilevel_sync = false,
398
399 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
400 .vsync_len = 6,
401
0206e353 402 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 403 .veq_start_f2 = 1, .veq_len = 18,
404
405 .vi_end_f1 = 20, .vi_end_f2 = 21,
406 .nbr_end = 240,
407
408 .burst_ena = true,
409 .hburst_start = 72, .hburst_len = 34,
410 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
411 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
412 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
413 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
414
415 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 416 .dda1_inc = 135,
417 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 418 .dda3_inc = 0, .dda3_size = 0,
419 .sc_reset = TV_SC_RESET_EVERY_4,
420 .pal_burst = false,
421
422 .composite_levels = &ntsc_m_levels_composite,
423 .composite_color = &ntsc_m_csc_composite,
424 .svideo_levels = &ntsc_m_levels_svideo,
425 .svideo_color = &ntsc_m_csc_svideo,
426
427 .filter_table = filter_table,
428 },
429 {
430 .name = "NTSC-443",
ba01079c 431 .clock = 108000,
23bd15ec 432 .refresh = 59940,
4f503798 433 .oversample = 8,
56f62308 434 .component_only = false,
79e53945
JB		 435 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
436 .hsync_end = 64, .hblank_end = 124,
437 .hblank_start = 836, .htotal = 857,
438
439 .progressive = false, .trilevel_sync = false,
440
441 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
442 .vsync_len = 6,
443
0206e353 444 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 445 .veq_start_f2 = 1, .veq_len = 18,
446
447 .vi_end_f1 = 20, .vi_end_f2 = 21,
448 .nbr_end = 240,
449
3ca87e82 450 .burst_ena = true,
79e53945
JB		 451 .hburst_start = 72, .hburst_len = 34,
452 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
453 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
454 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
455 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
456
457 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
458 .dda1_inc = 168,
ba01079c
ZW		 459 .dda2_inc = 4093, .dda2_size = 27456,
460 .dda3_inc = 310, .dda3_size = 525,
461 .sc_reset = TV_SC_RESET_NEVER,
462 .pal_burst = false,
79e53945
JB		 463
464 .composite_levels = &ntsc_m_levels_composite,
465 .composite_color = &ntsc_m_csc_composite,
466 .svideo_levels = &ntsc_m_levels_svideo,
467 .svideo_color = &ntsc_m_csc_svideo,
468
469 .filter_table = filter_table,
470 },
471 {
472 .name = "NTSC-J",
ba01079c 473 .clock = 108000,
23bd15ec 474 .refresh = 59940,
4f503798 475 .oversample = 8,
56f62308 476 .component_only = false,
79e53945
JB		 477
478 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
479 .hsync_end = 64, .hblank_end = 124,
480 .hblank_start = 836, .htotal = 857,
481
482 .progressive = false, .trilevel_sync = false,
483
484 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
485 .vsync_len = 6,
486
0206e353 487 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 488 .veq_start_f2 = 1, .veq_len = 18,
489
490 .vi_end_f1 = 20, .vi_end_f2 = 21,
491 .nbr_end = 240,
492
493 .burst_ena = true,
494 .hburst_start = 72, .hburst_len = 34,
495 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
496 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
497 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
498 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
499
500 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 501 .dda1_inc = 135,
502 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 503 .dda3_inc = 0, .dda3_size = 0,
504 .sc_reset = TV_SC_RESET_EVERY_4,
505 .pal_burst = false,
506
507 .composite_levels = &ntsc_j_levels_composite,
508 .composite_color = &ntsc_j_csc_composite,
509 .svideo_levels = &ntsc_j_levels_svideo,
510 .svideo_color = &ntsc_j_csc_svideo,
511
512 .filter_table = filter_table,
513 },
514 {
515 .name = "PAL-M",
ba01079c 516 .clock = 108000,
23bd15ec 517 .refresh = 59940,
4f503798 518 .oversample = 8,
56f62308 519 .component_only = false,
79e53945
JB		 520
521 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
522 .hsync_end = 64, .hblank_end = 124,
523 .hblank_start = 836, .htotal = 857,
524
525 .progressive = false, .trilevel_sync = false,
526
527 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
528 .vsync_len = 6,
529
0206e353 530 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 531 .veq_start_f2 = 1, .veq_len = 18,
532
533 .vi_end_f1 = 20, .vi_end_f2 = 21,
534 .nbr_end = 240,
535
536 .burst_ena = true,
537 .hburst_start = 72, .hburst_len = 34,
538 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
539 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
540 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
541 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
542
543 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 544 .dda1_inc = 135,
545 .dda2_inc = 16704, .dda2_size = 27456,
79e53945 546 .dda3_inc = 0, .dda3_size = 0,
ba01079c
ZW		 547 .sc_reset = TV_SC_RESET_EVERY_8,
548 .pal_burst = true,
79e53945
JB		 549
550 .composite_levels = &pal_m_levels_composite,
551 .composite_color = &pal_m_csc_composite,
552 .svideo_levels = &pal_m_levels_svideo,
553 .svideo_color = &pal_m_csc_svideo,
554
555 .filter_table = filter_table,
556 },
557 {
558 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
559 .name = "PAL-N",
ba01079c 560 .clock = 108000,
23bd15ec 561 .refresh = 50000,
4f503798 562 .oversample = 8,
56f62308 563 .component_only = false,
79e53945
JB		 564
565 .hsync_end = 64, .hblank_end = 128,
566 .hblank_start = 844, .htotal = 863,
567
568 .progressive = false, .trilevel_sync = false,
569
570
571 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
572 .vsync_len = 6,
573
0206e353 574 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 575 .veq_start_f2 = 1, .veq_len = 18,
576
577 .vi_end_f1 = 24, .vi_end_f2 = 25,
578 .nbr_end = 286,
579
580 .burst_ena = true,
0206e353 581 .hburst_start = 73, .hburst_len = 34,
79e53945
JB		 582 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
583 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
584 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
585 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
586
587
588 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
ba01079c
ZW		 589 .dda1_inc = 135,
590 .dda2_inc = 23578, .dda2_size = 27648,
591 .dda3_inc = 134, .dda3_size = 625,
79e53945
JB		 592 .sc_reset = TV_SC_RESET_EVERY_8,
593 .pal_burst = true,
594
595 .composite_levels = &pal_n_levels_composite,
596 .composite_color = &pal_n_csc_composite,
597 .svideo_levels = &pal_n_levels_svideo,
598 .svideo_color = &pal_n_csc_svideo,
599
600 .filter_table = filter_table,
601 },
602 {
603 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
604 .name = "PAL",
ba01079c 605 .clock = 108000,
23bd15ec 606 .refresh = 50000,
4f503798 607 .oversample = 8,
56f62308 608 .component_only = false,
79e53945 609
ba01079c 610 .hsync_end = 64, .hblank_end = 142,
79e53945
JB		 611 .hblank_start = 844, .htotal = 863,
612
613 .progressive = false, .trilevel_sync = false,
614
615 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
616 .vsync_len = 5,
617
0206e353 618 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 619 .veq_start_f2 = 1, .veq_len = 15,
620
621 .vi_end_f1 = 24, .vi_end_f2 = 25,
622 .nbr_end = 286,
623
624 .burst_ena = true,
625 .hburst_start = 73, .hburst_len = 32,
626 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
627 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
628 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
629 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
630
631 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
632 .dda1_inc = 168,
ba01079c
ZW		 633 .dda2_inc = 4122, .dda2_size = 27648,
634 .dda3_inc = 67, .dda3_size = 625,
79e53945
JB		 635 .sc_reset = TV_SC_RESET_EVERY_8,
636 .pal_burst = true,
637
638 .composite_levels = &pal_levels_composite,
639 .composite_color = &pal_csc_composite,
640 .svideo_levels = &pal_levels_svideo,
641 .svideo_color = &pal_csc_svideo,
642
643 .filter_table = filter_table,
644 },
9589919f
RV		 645 {
646 .name = "480p",
d5152823 647 .clock = 108000,
9589919f 648 .refresh = 59940,
4f503798 649 .oversample = 4,
56f62308 650 .component_only = true,
9589919f
RV		 651
652 .hsync_end = 64, .hblank_end = 122,
653 .hblank_start = 842, .htotal = 857,
654
655 .progressive = true, .trilevel_sync = false,
656
657 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
658 .vsync_len = 12,
659
660 .veq_ena = false,
661
662 .vi_end_f1 = 44, .vi_end_f2 = 44,
663 .nbr_end = 479,
664
665 .burst_ena = false,
666
667 .filter_table = filter_table,
668 },
669 {
670 .name = "576p",
d5152823 671 .clock = 108000,
9589919f 672 .refresh = 50000,
4f503798 673 .oversample = 4,
56f62308 674 .component_only = true,
9589919f
RV		 675
676 .hsync_end = 64, .hblank_end = 139,
677 .hblank_start = 859, .htotal = 863,
678
679 .progressive = true, .trilevel_sync = false,
680
681 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
682 .vsync_len = 10,
683
684 .veq_ena = false,
685
686 .vi_end_f1 = 48, .vi_end_f2 = 48,
687 .nbr_end = 575,
688
689 .burst_ena = false,
690
691 .filter_table = filter_table,
692 },
79e53945
JB		 693 {
694 .name = "720p@60Hz",
d5152823 695 .clock = 148500,
79e53945 696 .refresh = 60000,
4f503798 697 .oversample = 2,
56f62308 698 .component_only = true,
79e53945
JB		 699
700 .hsync_end = 80, .hblank_end = 300,
701 .hblank_start = 1580, .htotal = 1649,
702
0206e353 703 .progressive = true, .trilevel_sync = true,
79e53945
JB		 704
705 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
706 .vsync_len = 10,
707
708 .veq_ena = false,
709
710 .vi_end_f1 = 29, .vi_end_f2 = 29,
711 .nbr_end = 719,
712
713 .burst_ena = false,
714
715 .filter_table = filter_table,
716 },
79e53945
JB		 717 {
718 .name = "720p@50Hz",
d5152823 719 .clock = 148500,
79e53945 720 .refresh = 50000,
4f503798 721 .oversample = 2,
56f62308 722 .component_only = true,
79e53945
JB		 723
724 .hsync_end = 80, .hblank_end = 300,
725 .hblank_start = 1580, .htotal = 1979,
726
0206e353 727 .progressive = true, .trilevel_sync = true,
79e53945
JB		 728
729 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
730 .vsync_len = 10,
731
732 .veq_ena = false,
733
734 .vi_end_f1 = 29, .vi_end_f2 = 29,
735 .nbr_end = 719,
736
737 .burst_ena = false,
738
739 .filter_table = filter_table,
79e53945
JB		 740 },
741 {
742 .name = "1080i@50Hz",
d5152823 743 .clock = 148500,
23bd15ec 744 .refresh = 50000,
4f503798 745 .oversample = 2,
56f62308 746 .component_only = true,
79e53945
JB		 747
748 .hsync_end = 88, .hblank_end = 235,
749 .hblank_start = 2155, .htotal = 2639,
750
0206e353 751 .progressive = false, .trilevel_sync = true,
79e53945
JB		 752
753 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
754 .vsync_len = 10,
755
0206e353 756 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 757 .veq_start_f2 = 4, .veq_len = 10,
758
759
760 .vi_end_f1 = 21, .vi_end_f2 = 22,
761 .nbr_end = 539,
762
763 .burst_ena = false,
764
765 .filter_table = filter_table,
766 },
767 {
768 .name = "1080i@60Hz",
d5152823 769 .clock = 148500,
23bd15ec 770 .refresh = 60000,
4f503798 771 .oversample = 2,
56f62308 772 .component_only = true,
79e53945
JB		 773
774 .hsync_end = 88, .hblank_end = 235,
775 .hblank_start = 2155, .htotal = 2199,
776
0206e353 777 .progressive = false, .trilevel_sync = true,
79e53945
JB		 778
779 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
780 .vsync_len = 10,
781
0206e353 782 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 783 .veq_start_f2 = 4, .veq_len = 10,
784
785
786 .vi_end_f1 = 21, .vi_end_f2 = 22,
787 .nbr_end = 539,
788
789 .burst_ena = false,
790
79e53945
JB		 791 .filter_table = filter_table,
792 },
a0ff6779
VS		 793
794 {
795 .name = "1080p@30Hz",
796 .clock = 148500,
797 .refresh = 30000,
798 .oversample = 2,
799 .component_only = true,
800
801 .hsync_end = 88, .hblank_end = 235,
802 .hblank_start = 2155, .htotal = 2199,
803
804 .progressive = true, .trilevel_sync = true,
805
806 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
807 .vsync_len = 10,
808
809 .veq_ena = false, .veq_start_f1 = 0,
810 .veq_start_f2 = 0, .veq_len = 0,
811
812 .vi_end_f1 = 44, .vi_end_f2 = 44,
813 .nbr_end = 1079,
814
815 .burst_ena = false,
816
817 .filter_table = filter_table,
818 },
819
820 {
821 .name = "1080p@50Hz",
822 .clock = 148500,
823 .refresh = 50000,
824 .oversample = 1,
825 .component_only = true,
826
827 .hsync_end = 88, .hblank_end = 235,
828 .hblank_start = 2155, .htotal = 2639,
829
830 .progressive = true, .trilevel_sync = true,
831
832 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
833 .vsync_len = 10,
834
835 .veq_ena = false, .veq_start_f1 = 0,
836 .veq_start_f2 = 0, .veq_len = 0,
837
838 .vi_end_f1 = 44, .vi_end_f2 = 44,
839 .nbr_end = 1079,
840
841 .burst_ena = false,
842
843 .filter_table = filter_table,
844 },
845
846 {
847 .name = "1080p@60Hz",
848 .clock = 148500,
849 .refresh = 60000,
850 .oversample = 1,
851 .component_only = true,
852
853 .hsync_end = 88, .hblank_end = 235,
854 .hblank_start = 2155, .htotal = 2199,
855
856 .progressive = true, .trilevel_sync = true,
857
858 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
859 .vsync_len = 10,
860
861 .veq_ena = false, .veq_start_f1 = 0,
862 .veq_start_f2 = 0, .veq_len = 0,
863
864 .vi_end_f1 = 44, .vi_end_f2 = 44,
865 .nbr_end = 1079,
866
867 .burst_ena = false,
868
869 .filter_table = filter_table,
870 },
79e53945
JB		 871};
872
690157f0
VS		 873struct intel_tv_connector_state {
874 struct drm_connector_state base;
875
876 /*
877 * May need to override the user margins for
878 * gen3 >1024 wide source vertical centering.
879 */
880 struct {
881 u16 top, bottom;
882 } margins;
883
884 bool bypass_vfilter;
885};
886
887#define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base)
888
889static struct drm_connector_state *
890intel_tv_connector_duplicate_state(struct drm_connector *connector)
891{
892 struct intel_tv_connector_state *state;
893
894 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
895 if (!state)
896 return NULL;
897
898 __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
899 return &state->base;
900}
901
cd91ef23 902static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
ea5b213a 903{
cd91ef23 904 return container_of(encoder, struct intel_tv, base);
ea5b213a
CW		 905}
906
43a6d19c 907static struct intel_tv *intel_attached_tv(struct intel_connector *connector)
df0e9248 908{
cd91ef23 909 return enc_to_tv(intel_attached_encoder(connector));
df0e9248
CW		 910}
911
9a8ee983
DV		 912static bool
913intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
914{
4add0f6b 915 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
988ff27b 916 u32 tmp = intel_de_read(dev_priv, TV_CTL);
9a8ee983 917
4add0f6b 918 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
9a8ee983 919
4add0f6b 920 return tmp & TV_ENC_ENABLE;
9a8ee983
DV		 921}
922
79e53945 923static void
ede9771d
VS		 924intel_enable_tv(struct intel_atomic_state *state,
925 struct intel_encoder *encoder,
5f88a9c6
VS		 926 const struct intel_crtc_state *pipe_config,
927 const struct drm_connector_state *conn_state)
79e53945 928{
6b5756a0 929 struct drm_device *dev = encoder->base.dev;
fac5e23e 930 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 931
7a98948f 932 /* Prevents vblank waits from timing out in intel_tv_detect_type() */
7b06894b 933 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
7a98948f 934
59ea2887 935 intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE);
6b5756a0
DV		 936}
937
938static void
ede9771d
VS		 939intel_disable_tv(struct intel_atomic_state *state,
940 struct intel_encoder *encoder,
5f88a9c6
VS		 941 const struct intel_crtc_state *old_crtc_state,
942 const struct drm_connector_state *old_conn_state)
6b5756a0
DV		 943{
944 struct drm_device *dev = encoder->base.dev;
fac5e23e 945 struct drm_i915_private *dev_priv = to_i915(dev);
6b5756a0 946
59ea2887 947 intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0);
79e53945
JB		 948}
949
5f88a9c6 950static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
79e53945 951{
fb1e8812 952 int format = conn_state->tv.legacy_mode;
79e53945 953
0e891b3f 954 return &tv_modes[format];
79e53945
JB		 955}
956
957static enum drm_mode_status
763a4a01
CW		 958intel_tv_mode_valid(struct drm_connector *connector,
959 struct drm_display_mode *mode)
79e53945 960{
e0ef2daa 961 struct drm_i915_private *i915 = to_i915(connector->dev);
0e891b3f 962 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
e0ef2daa
VS		 963 int max_dotclk = i915->max_dotclk_freq;
964 enum drm_mode_status status;
965
966 status = intel_cpu_transcoder_mode_valid(i915, mode);
967 if (status != MODE_OK)
968 return status;
54c032b3 969
e4dd27aa
VS		 970 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
971 return MODE_NO_DBLESCAN;
972
54c032b3
MK		 973 if (mode->clock > max_dotclk)
974 return MODE_CLOCK_HIGH;
79e53945
JB		 975
976 /* Ensure TV refresh is close to desired refresh */
15de0889
VS		 977 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000)
978 return MODE_CLOCK_RANGE;
763a4a01 979
15de0889 980 return MODE_OK;
79e53945
JB		 981}
982
65ddf7f9
VS		 983static int
984intel_tv_mode_vdisplay(const struct tv_mode *tv_mode)
985{
986 if (tv_mode->progressive)
987 return tv_mode->nbr_end + 1;
988 else
989 return 2 * (tv_mode->nbr_end + 1);
990}
79e53945 991
e3bb355c
VS		 992static void
993intel_tv_mode_to_mode(struct drm_display_mode *mode,
1bba5543
VS		 994 const struct tv_mode *tv_mode,
995 int clock)
e3bb355c 996{
1bba5543 997 mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive);
e3bb355c
VS		 998
999 /*
1000 * tv_mode horizontal timings:
1001 *
1002 * hsync_end
1003 * | hblank_end
1004 * | | hblank_start
1005 * | | | htotal
1006 * | _______ |
1007 * ____/ \___
1008 * \__/ \
1009 */
1010 mode->hdisplay =
1011 tv_mode->hblank_start - tv_mode->hblank_end;
1012 mode->hsync_start = mode->hdisplay +
1013 tv_mode->htotal - tv_mode->hblank_start;
1014 mode->hsync_end = mode->hsync_start +
1015 tv_mode->hsync_end;
1016 mode->htotal = tv_mode->htotal + 1;
1017
1018 /*
1019 * tv_mode vertical timings:
1020 *
1021 * vsync_start
1022 * | vsync_end
1023 * | | vi_end nbr_end
1024 * | | | |
1025 * | | _______
1026 * \__ ____/ \
1027 * \__/
1028 */
1029 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode);
1030 if (tv_mode->progressive) {
1031 mode->vsync_start = mode->vdisplay +
1032 tv_mode->vsync_start_f1 + 1;
1033 mode->vsync_end = mode->vsync_start +
1034 tv_mode->vsync_len;
1035 mode->vtotal = mode->vdisplay +
1036 tv_mode->vi_end_f1 + 1;
1037 } else {
1038 mode->vsync_start = mode->vdisplay +
1039 tv_mode->vsync_start_f1 + 1 +
1040 tv_mode->vsync_start_f2 + 1;
1041 mode->vsync_end = mode->vsync_start +
1042 2 * tv_mode->vsync_len;
1043 mode->vtotal = mode->vdisplay +
1044 tv_mode->vi_end_f1 + 1 +
1045 tv_mode->vi_end_f2 + 1;
1046 }
1047
1048 /* TV has it's own notion of sync and other mode flags, so clear them. */
1049 mode->flags = 0;
1050
e3bb355c
VS		 1051 snprintf(mode->name, sizeof(mode->name),
1052 "%dx%d%c (%s)",
1053 mode->hdisplay, mode->vdisplay,
1054 tv_mode->progressive ? 'p' : 'i',
1055 tv_mode->name);
1056}
1057
1058static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode,
1059 int hdisplay, int left_margin,
1060 int right_margin)
1061{
1062 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin;
1063 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin;
1064 int new_htotal = mode->htotal * hdisplay /
1065 (mode->hdisplay - left_margin - right_margin);
1066
1067 mode->clock = mode->clock * new_htotal / mode->htotal;
1068
1069 mode->hdisplay = hdisplay;
1070 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal;
1071 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal;
1072 mode->htotal = new_htotal;
1073}
1074
1075static void intel_tv_scale_mode_vert(struct drm_display_mode *mode,
1076 int vdisplay, int top_margin,
1077 int bottom_margin)
1078{
1079 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin;
1080 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin;
1081 int new_vtotal = mode->vtotal * vdisplay /
1082 (mode->vdisplay - top_margin - bottom_margin);
1083
1084 mode->clock = mode->clock * new_vtotal / mode->vtotal;
1085
1086 mode->vdisplay = vdisplay;
1087 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal;
1088 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal;
1089 mode->vtotal = new_vtotal;
1090}
1091
7a495cfd
DV		 1092static void
1093intel_tv_get_config(struct intel_encoder *encoder,
5cec258b 1094 struct intel_crtc_state *pipe_config)
7a495cfd 1095{
e3bb355c
VS		 1096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1097 struct drm_display_mode *adjusted_mode =
1326a92c 1098 &pipe_config->hw.adjusted_mode;
e3bb355c
VS		 1099 struct drm_display_mode mode = {};
1100 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
1101 struct tv_mode tv_mode = {};
1102 int hdisplay = adjusted_mode->crtc_hdisplay;
1103 int vdisplay = adjusted_mode->crtc_vdisplay;
1104 int xsize, ysize, xpos, ypos;
1105
e1214b95
VS		 1106 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
1107
988ff27b
JN		 1108 tv_ctl = intel_de_read(dev_priv, TV_CTL);
1109 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
1110 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
1111 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
1112 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
e3bb355c
VS		 1113
1114 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
1115 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
1116
1117 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT;
1118 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT;
1119
1120 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT;
1121 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT;
1122 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT;
1123
1124 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT;
1125 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT;
1126 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT;
1127
1128 tv_mode.clock = pipe_config->port_clock;
1129
1130 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE;
1131
1132 switch (tv_ctl & TV_OVERSAMPLE_MASK) {
1133 case TV_OVERSAMPLE_8X:
1134 tv_mode.oversample = 8;
1135 break;
1136 case TV_OVERSAMPLE_4X:
1137 tv_mode.oversample = 4;
1138 break;
1139 case TV_OVERSAMPLE_2X:
1140 tv_mode.oversample = 2;
1141 break;
1142 default:
1143 tv_mode.oversample = 1;
1144 break;
1145 }
1146
988ff27b 1147 tmp = intel_de_read(dev_priv, TV_WIN_POS);
e3bb355c
VS		 1148 xpos = tmp >> 16;
1149 ypos = tmp & 0xffff;
1150
988ff27b 1151 tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
e3bb355c
VS		 1152 xsize = tmp >> 16;
1153 ysize = tmp & 0xffff;
1154
1bba5543 1155 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock);
e3bb355c 1156
f01bae2d
VS		 1157 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1158 DRM_MODE_ARG(&mode));
e3bb355c
VS		 1159
1160 intel_tv_scale_mode_horiz(&mode, hdisplay,
1161 xpos, mode.hdisplay - xsize - xpos);
1162 intel_tv_scale_mode_vert(&mode, vdisplay,
1163 ypos, mode.vdisplay - ysize - ypos);
1164
1165 adjusted_mode->crtc_clock = mode.clock;
addc80f0
VS		 1166 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1167 adjusted_mode->crtc_clock /= 2;
8a920e24
VS		 1168
1169 /* pixel counter doesn't work on i965gm TV output */
1170 if (IS_I965GM(dev_priv))
af157b76 1171 pipe_config->mode_flags |=
8a920e24 1172 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
7a495cfd
DV		 1173}
1174
68e94f62
VS		 1175static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
1176 int hdisplay)
1177{
93e7e61e 1178 return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
68e94f62
VS		 1179}
1180
1181static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
1182 const struct drm_connector_state *conn_state,
1183 int vdisplay)
1184{
1185 return tv_mode->crtc_vdisplay -
1186 conn_state->tv.margins.top -
1187 conn_state->tv.margins.bottom !=
1188 vdisplay;
1189}
1190
204474a6 1191static int
5d2d38dd 1192intel_tv_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1193 struct intel_crtc_state *pipe_config,
1194 struct drm_connector_state *conn_state)
79e53945 1195{
1bba5543
VS		 1196 struct intel_atomic_state *state =
1197 to_intel_atomic_state(pipe_config->uapi.state);
1198 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
690157f0
VS		 1199 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1200 struct intel_tv_connector_state *tv_conn_state =
1201 to_intel_tv_connector_state(conn_state);
0e891b3f 1202 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
e4dd27aa 1203 struct drm_display_mode *adjusted_mode =
1326a92c 1204 &pipe_config->hw.adjusted_mode;
e3bb355c
VS		 1205 int hdisplay = adjusted_mode->crtc_hdisplay;
1206 int vdisplay = adjusted_mode->crtc_vdisplay;
1bba5543 1207 int ret;
79e53945
JB		 1208
1209 if (!tv_mode)
204474a6 1210 return -EINVAL;
79e53945 1211
e4dd27aa 1212 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
204474a6 1213 return -EINVAL;
e4dd27aa 1214
a04d27cd 1215 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
d9facae6 1216 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
e3bb355c 1217
025c2e19 1218 drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
5d2d38dd
DV		 1219 pipe_config->pipe_bpp = 8*3;
1220
e3bb355c
VS		 1221 pipe_config->port_clock = tv_mode->clock;
1222
1bba5543
VS		 1223 ret = intel_dpll_crtc_compute_clock(state, crtc);
1224 if (ret)
1225 return ret;
1226
1227 pipe_config->clock_set = true;
1228
1229 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock);
690157f0
VS		 1230 drm_mode_set_crtcinfo(adjusted_mode, 0);
1231
68e94f62
VS		 1232 if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
1233 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
690157f0
VS		 1234 int extra, top, bottom;
1235
1236 extra = adjusted_mode->crtc_vdisplay - vdisplay;
1237
1238 if (extra < 0) {
025c2e19
WK		 1239 drm_dbg_kms(&dev_priv->drm,
1240 "No vertical scaling for >1024 pixel wide modes\n");
6a2a9404 1241 return -EINVAL;
690157f0
VS		 1242 }
1243
1244 /* Need to turn off the vertical filter and center the image */
1245
1246 /* Attempt to maintain the relative sizes of the margins */
1247 top = conn_state->tv.margins.top;
1248 bottom = conn_state->tv.margins.bottom;
1249
1250 if (top + bottom)
1251 top = extra * top / (top + bottom);
1252 else
1253 top = extra / 2;
1254 bottom = extra - top;
1255
1256 tv_conn_state->margins.top = top;
1257 tv_conn_state->margins.bottom = bottom;
1258
1259 tv_conn_state->bypass_vfilter = true;
1260
addc80f0
VS		 1261 if (!tv_mode->progressive) {
1262 adjusted_mode->clock /= 2;
1263 adjusted_mode->crtc_clock /= 2;
690157f0 1264 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
addc80f0 1265 }
690157f0
VS		 1266 } else {
1267 tv_conn_state->margins.top = conn_state->tv.margins.top;
1268 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom;
1269
1270 tv_conn_state->bypass_vfilter = false;
1271 }
e3bb355c 1272
f01bae2d
VS		 1273 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1274 DRM_MODE_ARG(adjusted_mode));
1062b815
DV		 1275
1276 /*
e3bb355c
VS		 1277 * The pipe scanline counter behaviour looks as follows when
1278 * using the TV encoder:
1279 *
1280 * time ->
1281 *
1282 * dsl=vtotal-1 | |
1283 * || ||
1284 * ___| | ___| |
1285 * / | / |
1286 * / | / |
1287 * dsl=0 ___/ |_____/ |
1288 * | | | | | |
1289 * ^ ^ ^ ^ ^
1290 * | | | | pipe vblank/first part of tv vblank
1291 * | | | bottom margin
1292 * | | active
1293 * | top margin
1294 * remainder of tv vblank
1295 *
1296 * When the TV encoder is used the pipe wants to run faster
1297 * than expected rate. During the active portion the TV
1298 * encoder stalls the pipe every few lines to keep it in
1299 * check. When the TV encoder reaches the bottom margin the
1300 * pipe simply stops. Once we reach the TV vblank the pipe is
1301 * no longer stalled and it runs at the max rate (apparently
1302 * oversample clock on gen3, cdclk on gen4). Once the pipe
1303 * reaches the pipe vtotal the pipe stops for the remainder
1304 * of the TV vblank/top margin. The pipe starts up again when
1305 * the TV encoder exits the top margin.
1306 *
1307 * To avoid huge hassles for vblank timestamping we scale
1308 * the pipe timings as if the pipe always runs at the average
1309 * rate it maintains during the active period. This also
1310 * gives us a reasonable guesstimate as to the pixel rate.
1311 * Due to the variation in the actual pipe speed the scanline
1312 * counter will give us slightly erroneous results during the
1313 * TV vblank/margins. But since vtotal was selected such that
1314 * it matches the average rate of the pipe during the active
1315 * portion the error shouldn't cause any serious grief to
1316 * vblank timestamps.
1317 *
1318 * For posterity here is the empirically derived formula
1319 * that gives us the maximum length of the pipe vblank
1320 * we can use without causing display corruption. Following
1321 * this would allow us to have a ticking scanline counter
1322 * everywhere except during the bottom margin (there the
1323 * pipe always stops). Ie. this would eliminate the second
1324 * flat portion of the above graph. However this would also
1325 * complicate vblank timestamping as the pipe vtotal would
1326 * no longer match the average rate the pipe runs at during
1327 * the active portion. Hence following this formula seems
1328 * more trouble that it's worth.
1329 *
07960a4c 1330 * if (GRAPHICS_VER(dev_priv) == 4) {
e3bb355c
VS		 1331 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
1332 * den = tv_mode->clock;
1333 * } else {
1334 * num = tv_mode->oversample >> !tv_mode->progressive;
1335 * den = 1;
1336 * }
1337 * max_pipe_vblank_len ~=
1338 * (num * tv_htotal * (tv_vblank_len + top_margin)) /
1339 * (den * pipe_htotal);
1062b815 1340 */
e3bb355c
VS		 1341 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay,
1342 conn_state->tv.margins.left,
1343 conn_state->tv.margins.right);
1344 intel_tv_scale_mode_vert(adjusted_mode, vdisplay,
690157f0
VS		 1345 tv_conn_state->margins.top,
1346 tv_conn_state->margins.bottom);
e3bb355c
VS		 1347 drm_mode_set_crtcinfo(adjusted_mode, 0);
1348 adjusted_mode->name[0] = '\0';
1062b815 1349
8a920e24
VS		 1350 /* pixel counter doesn't work on i965gm TV output */
1351 if (IS_I965GM(dev_priv))
af157b76 1352 pipe_config->mode_flags |=
8a920e24
VS		 1353 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1354
204474a6 1355 return 0;
79e53945
JB		 1356}
1357
8cb92203
DV		 1358static void
1359set_tv_mode_timings(struct drm_i915_private *dev_priv,
1360 const struct tv_mode *tv_mode,
1361 bool burst_ena)
1362{
1363 u32 hctl1, hctl2, hctl3;
1364 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
1365
1366 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
1367 (tv_mode->htotal << TV_HTOTAL_SHIFT);
1368
1369 hctl2 = (tv_mode->hburst_start << 16) |
1370 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
1371
1372 if (burst_ena)
1373 hctl2 |= TV_BURST_ENA;
1374
1375 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
1376 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
1377
1378 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
1379 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
1380 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
1381
1382 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
1383 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
1384 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
1385
1386 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
1387 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1388 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1389
1390 if (tv_mode->veq_ena)
1391 vctl3 |= TV_EQUAL_ENA;
1392
1393 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1394 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1395
1396 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1397 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1398
1399 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1400 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1401
1402 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1403 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1404
988ff27b
JN		 1405 intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
1406 intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
1407 intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
1408 intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
1409 intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
1410 intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
1411 intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
1412 intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
1413 intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
1414 intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
8cb92203
DV		 1415}
1416
b8866ef8
DV		 1417static void set_color_conversion(struct drm_i915_private *dev_priv,
1418 const struct color_conversion *color_conversion)
1419{
988ff27b
JN		 1420 intel_de_write(dev_priv, TV_CSC_Y,
1421 (color_conversion->ry << 16) | color_conversion->gy);
1422 intel_de_write(dev_priv, TV_CSC_Y2,
1423 (color_conversion->by << 16) | color_conversion->ay);
1424 intel_de_write(dev_priv, TV_CSC_U,
1425 (color_conversion->ru << 16) | color_conversion->gu);
1426 intel_de_write(dev_priv, TV_CSC_U2,
1427 (color_conversion->bu << 16) | color_conversion->au);
1428 intel_de_write(dev_priv, TV_CSC_V,
1429 (color_conversion->rv << 16) | color_conversion->gv);
1430 intel_de_write(dev_priv, TV_CSC_V2,
1431 (color_conversion->bv << 16) | color_conversion->av);
b8866ef8
DV		 1432}
1433
ede9771d
VS		 1434static void intel_tv_pre_enable(struct intel_atomic_state *state,
1435 struct intel_encoder *encoder,
5f88a9c6
VS		 1436 const struct intel_crtc_state *pipe_config,
1437 const struct drm_connector_state *conn_state)
79e53945 1438{
66478475 1439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f15f01a7 1440 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
cd91ef23 1441 struct intel_tv *intel_tv = enc_to_tv(encoder);
690157f0
VS		 1442 const struct intel_tv_connector_state *tv_conn_state =
1443 to_intel_tv_connector_state(conn_state);
0e891b3f 1444 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
690157f0 1445 u32 tv_ctl, tv_filter_ctl;
79e53945
JB		 1446 u32 scctl1, scctl2, scctl3;
1447 int i, j;
1448 const struct video_levels *video_levels;
1449 const struct color_conversion *color_conversion;
1450 bool burst_ena;
bda5f532 1451 int xpos, ypos;
3fa2dd14 1452 unsigned int xsize, ysize;
79e53945 1453
988ff27b 1454 tv_ctl = intel_de_read(dev_priv, TV_CTL);
d2d9f232 1455 tv_ctl &= TV_CTL_SAVE;
79e53945 1456
ea5b213a 1457 switch (intel_tv->type) {
79e53945
JB		 1458 default:
1459 case DRM_MODE_CONNECTOR_Unknown:
1460 case DRM_MODE_CONNECTOR_Composite:
1461 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1462 video_levels = tv_mode->composite_levels;
1463 color_conversion = tv_mode->composite_color;
1464 burst_ena = tv_mode->burst_ena;
1465 break;
1466 case DRM_MODE_CONNECTOR_Component:
1467 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1468 video_levels = &component_levels;
1469 if (tv_mode->burst_ena)
1470 color_conversion = &sdtv_csc_yprpb;
1471 else
1472 color_conversion = &hdtv_csc_yprpb;
1473 burst_ena = false;
1474 break;
1475 case DRM_MODE_CONNECTOR_SVIDEO:
1476 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1477 video_levels = tv_mode->svideo_levels;
1478 color_conversion = tv_mode->svideo_color;
1479 burst_ena = tv_mode->burst_ena;
1480 break;
1481 }
79e53945 1482
f15f01a7 1483 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
4f503798
VS		 1484
1485 switch (tv_mode->oversample) {
1486 case 8:
1487 tv_ctl |= TV_OVERSAMPLE_8X;
1488 break;
1489 case 4:
1490 tv_ctl |= TV_OVERSAMPLE_4X;
1491 break;
1492 case 2:
1493 tv_ctl |= TV_OVERSAMPLE_2X;
1494 break;
1495 default:
1496 tv_ctl |= TV_OVERSAMPLE_NONE;
1497 break;
1498 }
79e53945
JB		 1499
1500 if (tv_mode->progressive)
1501 tv_ctl |= TV_PROGRESSIVE;
1502 if (tv_mode->trilevel_sync)
1503 tv_ctl |= TV_TRILEVEL_SYNC;
1504 if (tv_mode->pal_burst)
1505 tv_ctl |= TV_PAL_BURST;
d271817b 1506
79e53945 1507 scctl1 = 0;
d271817b 1508 if (tv_mode->dda1_inc)
79e53945 1509 scctl1 |= TV_SC_DDA1_EN;
79e53945
JB		 1510 if (tv_mode->dda2_inc)
1511 scctl1 |= TV_SC_DDA2_EN;
79e53945
JB		 1512 if (tv_mode->dda3_inc)
1513 scctl1 |= TV_SC_DDA3_EN;
79e53945 1514 scctl1 |= tv_mode->sc_reset;
d271817b
CW		 1515 if (video_levels)
1516 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
79e53945
JB		 1517 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1518
1519 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1520 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1521
1522 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1523 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1524
1525 /* Enable two fixes for the chips that need them. */
50a0bc90 1526 if (IS_I915GM(dev_priv))
79e53945
JB		 1527 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1528
8cb92203
DV		 1529 set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
1530
988ff27b
JN		 1531 intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
1532 intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
1533 intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
79e53945 1534
b8866ef8 1535 set_color_conversion(dev_priv, color_conversion);
79e53945 1536
005e9537 1537 if (DISPLAY_VER(dev_priv) >= 4)
988ff27b 1538 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
d2d9f232 1539 else
988ff27b 1540 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
d2d9f232 1541
79e53945 1542 if (video_levels)
988ff27b
JN		 1543 intel_de_write(dev_priv, TV_CLR_LEVEL,
1544 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
3fa2dd14 1545
8c66081b 1546 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
3fa2dd14
DV		 1547
1548 /* Filter ctl must be set before TV_WIN_SIZE */
690157f0
VS		 1549 tv_filter_ctl = TV_AUTO_SCALE;
1550 if (tv_conn_state->bypass_vfilter)
1551 tv_filter_ctl |= TV_V_FILTER_BYPASS;
988ff27b 1552 intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
690157f0 1553
3fa2dd14 1554 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
65ddf7f9 1555 ysize = intel_tv_mode_vdisplay(tv_mode);
3fa2dd14 1556
bda5f532 1557 xpos = conn_state->tv.margins.left;
690157f0 1558 ypos = tv_conn_state->margins.top;
0e891b3f
ML		 1559 xsize -= (conn_state->tv.margins.left +
1560 conn_state->tv.margins.right);
690157f0
VS		 1561 ysize -= (tv_conn_state->margins.top +
1562 tv_conn_state->margins.bottom);
988ff27b
JN		 1563 intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
1564 intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
79e53945
JB		 1565
1566 j = 0;
1567 for (i = 0; i < 60; i++)
988ff27b
JN		 1568 intel_de_write(dev_priv, TV_H_LUMA(i),
1569 tv_mode->filter_table[j++]);
79e53945 1570 for (i = 0; i < 60; i++)
988ff27b
JN		 1571 intel_de_write(dev_priv, TV_H_CHROMA(i),
1572 tv_mode->filter_table[j++]);
79e53945 1573 for (i = 0; i < 43; i++)
988ff27b
JN		 1574 intel_de_write(dev_priv, TV_V_LUMA(i),
1575 tv_mode->filter_table[j++]);
79e53945 1576 for (i = 0; i < 43; i++)
988ff27b
JN		 1577 intel_de_write(dev_priv, TV_V_CHROMA(i),
1578 tv_mode->filter_table[j++]);
1579 intel_de_write(dev_priv, TV_DAC,
1580 intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
1581 intel_de_write(dev_priv, TV_CTL, tv_ctl);
79e53945
JB		 1582}
1583
79e53945 1584static int
0206e353 1585intel_tv_detect_type(struct intel_tv *intel_tv,
8102e126 1586 struct drm_connector *connector)
79e53945 1587{
f15f01a7 1588 struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc);
0eadc624 1589 struct drm_device *dev = connector->dev;
fac5e23e 1590 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 1591 u32 tv_ctl, save_tv_ctl;
1592 u32 tv_dac, save_tv_dac;
974b9331 1593 int type;
79e53945
JB		 1594
1595 /* Disable TV interrupts around load detect or we'll recurse */
8102e126 1596 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1597 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1598 i915_disable_pipestat(dev_priv, 0,
755e9019
ID		 1599 PIPE_HOTPLUG_INTERRUPT_STATUS |
1600 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1601 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1602 }
79e53945 1603
988ff27b
JN		 1604 save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
1605 save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
974b9331
CW		 1606
1607 /* Poll for TV detection */
4add0f6b 1608 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
8ed9a5bc 1609 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
f15f01a7 1610 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
974b9331
CW		 1611
1612 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
8ed9a5bc 1613 tv_dac |= (TVDAC_STATE_CHG_EN |
1614 TVDAC_A_SENSE_CTL |
1615 TVDAC_B_SENSE_CTL |
1616 TVDAC_C_SENSE_CTL |
1617 DAC_CTL_OVERRIDE |
1618 DAC_A_0_7_V |
1619 DAC_B_0_7_V |
1620 DAC_C_0_7_V);
974b9331 1621
d42c9e2c
DV		 1622
1623 /*
1624 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1625 * the TV is misdetected. This is hardware requirement.
1626 */
50a0bc90 1627 if (IS_GM45(dev_priv))
d42c9e2c
DV		 1628 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1629 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1630
988ff27b
JN		 1631 intel_de_write(dev_priv, TV_CTL, tv_ctl);
1632 intel_de_write(dev_priv, TV_DAC, tv_dac);
1633 intel_de_posting_read(dev_priv, TV_DAC);
4f233eff 1634
7b06894b 1635 intel_crtc_wait_for_next_vblank(crtc);
29e1316a 1636
974b9331 1637 type = -1;
988ff27b 1638 tv_dac = intel_de_read(dev_priv, TV_DAC);
025c2e19 1639 drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
2bf71160
KP		 1640 /*
1641 * A B C
1642 * 0 1 1 Composite
1643 * 1 0 X svideo
1644 * 0 0 0 Component
1645 */
1646 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
025c2e19
WK		 1647 drm_dbg_kms(&dev_priv->drm,
1648 "Detected Composite TV connection\n");
2bf71160
KP		 1649 type = DRM_MODE_CONNECTOR_Composite;
1650 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
025c2e19
WK		 1651 drm_dbg_kms(&dev_priv->drm,
1652 "Detected S-Video TV connection\n");
2bf71160
KP		 1653 type = DRM_MODE_CONNECTOR_SVIDEO;
1654 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
025c2e19
WK		 1655 drm_dbg_kms(&dev_priv->drm,
1656 "Detected Component TV connection\n");
2bf71160
KP		 1657 type = DRM_MODE_CONNECTOR_Component;
1658 } else {
025c2e19 1659 drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n");
2bf71160 1660 type = -1;
79e53945
JB		 1661 }
1662
988ff27b
JN		 1663 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1664 intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
1665 intel_de_posting_read(dev_priv, TV_CTL);
bf2125e2
DV		 1666
1667 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
7b06894b 1668 intel_crtc_wait_for_next_vblank(crtc);
974b9331 1669
79e53945 1670 /* Restore interrupt config */
8102e126 1671 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1672 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1673 i915_enable_pipestat(dev_priv, 0,
755e9019
ID		 1674 PIPE_HOTPLUG_INTERRUPT_STATUS |
1675 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1676 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1677 }
79e53945
JB		 1678
1679 return type;
1680}
1681
213c2e64
ML		 1682/*
1683 * Here we set accurate tv format according to connector type
1684 * i.e Component TV should not be assigned by NTSC or PAL
1685 */
1686static void intel_tv_find_better_format(struct drm_connector *connector)
1687{
43a6d19c 1688 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
0e891b3f 1689 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
213c2e64
ML		 1690 int i;
1691
e94390aa
VS		 1692 /* Component supports everything so we can keep the current mode */
1693 if (intel_tv->type == DRM_MODE_CONNECTOR_Component)
213c2e64
ML		 1694 return;
1695
e94390aa
VS		 1696 /* If the current mode is fine don't change it */
1697 if (!tv_mode->component_only)
1698 return;
213c2e64 1699
53abb679 1700 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
e94390aa 1701 tv_mode = &tv_modes[i];
213c2e64 1702
e94390aa 1703 if (!tv_mode->component_only)
213c2e64
ML		 1704 break;
1705 }
1706
fb1e8812 1707 connector->state->tv.legacy_mode = i;
213c2e64
ML		 1708}
1709
6c5ed5ae
ML		 1710static int
1711intel_tv_detect(struct drm_connector *connector,
1712 struct drm_modeset_acquire_ctx *ctx,
1713 bool force)
79e53945 1714{
7bee031d 1715 struct drm_i915_private *i915 = to_i915(connector->dev);
43a6d19c 1716 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
bbfb44e8 1717 enum drm_connector_status status;
ea5b213a 1718 int type;
79e53945 1719
7bee031d
JN		 1720 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n",
1721 connector->base.id, connector->name, force);
164c8598 1722
fe63ea7c 1723 if (!intel_display_device_enabled(i915))
b81dddb9
VS		 1724 return connector_status_disconnected;
1725
38de45c5 1726 if (force) {
8902a55d 1727 struct drm_atomic_state *state;
ea5b213a 1728
8902a55d
JN		 1729 state = intel_load_detect_get_pipe(connector, ctx);
1730 if (IS_ERR(state))
1731 return PTR_ERR(state);
208bf9fd 1732
8902a55d 1733 if (state) {
8102e126 1734 type = intel_tv_detect_type(intel_tv, connector);
8902a55d 1735 intel_load_detect_release_pipe(connector, state, ctx);
bbfb44e8
VS		 1736 status = type < 0 ?
1737 connector_status_disconnected :
1738 connector_status_connected;
8902a55d 1739 } else {
bbfb44e8 1740 status = connector_status_unknown;
8902a55d 1741 }
bf5a269a 1742
0e891b3f
ML		 1743 if (status == connector_status_connected) {
1744 intel_tv->type = type;
1745 intel_tv_find_better_format(connector);
1746 }
d5627663 1747
0e891b3f
ML		 1748 return status;
1749 } else
1750 return connector->status;
79e53945
JB		 1751}
1752
763a4a01 1753static const struct input_res {
5023520f 1754 u16 w, h;
763a4a01 1755} input_res_table[] = {
5023520f
VS		 1756 { 640, 480 },
1757 { 800, 600 },
1758 { 1024, 768 },
1759 { 1280, 1024 },
1760 { 848, 480 },
1761 { 1280, 720 },
1762 { 1920, 1080 },
79e53945
JB		 1763};
1764
65ddf7f9
VS		 1765/* Choose preferred mode according to line number of TV format */
1766static bool
1767intel_tv_is_preferred_mode(const struct drm_display_mode *mode,
1768 const struct tv_mode *tv_mode)
1769{
1770 int vdisplay = intel_tv_mode_vdisplay(tv_mode);
1771
1772 /* prefer 480 line modes for all SD TV modes */
1773 if (vdisplay <= 576)
1774 vdisplay = 480;
1775
1776 return vdisplay == mode->vdisplay;
1777}
1778
bcae2ca8 1779static void
65ddf7f9
VS		 1780intel_tv_set_mode_type(struct drm_display_mode *mode,
1781 const struct tv_mode *tv_mode)
bcae2ca8 1782{
65ddf7f9
VS		 1783 mode->type = DRM_MODE_TYPE_DRIVER;
1784
1785 if (intel_tv_is_preferred_mode(mode, tv_mode))
1786 mode->type |= DRM_MODE_TYPE_PREFERRED;
bcae2ca8 1787}
1788
79e53945
JB		 1789static int
1790intel_tv_get_modes(struct drm_connector *connector)
1791{
0bb1ffe4 1792 struct drm_i915_private *dev_priv = to_i915(connector->dev);
0e891b3f 1793 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
e3bb355c 1794 int i, count = 0;
79e53945 1795
e3bb355c
VS		 1796 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) {
1797 const struct input_res *input = &input_res_table[i];
1798 struct drm_display_mode *mode;
79e53945 1799
e3bb355c
VS		 1800 if (input->w > 1024 &&
1801 !tv_mode->progressive &&
1802 !tv_mode->component_only)
79e53945
JB		 1803 continue;
1804
0bb1ffe4 1805 /* no vertical scaling with wide sources on gen3 */
93e7e61e 1806 if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
0bb1ffe4
VS		 1807 input->h > intel_tv_mode_vdisplay(tv_mode))
1808 continue;
1809
e3bb355c
VS		 1810 mode = drm_mode_create(connector->dev);
1811 if (!mode)
02c5dd98 1812 continue;
79e53945 1813
e3bb355c
VS		 1814 /*
1815 * We take the TV mode and scale it to look
1816 * like it had the expected h/vdisplay. This
1817 * provides the most information to userspace
1818 * about the actual timings of the mode. We
1819 * do ignore the margins though.
1820 */
1bba5543 1821 intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock);
e3bb355c 1822 if (count == 0) {
f01bae2d
VS		 1823 drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1824 DRM_MODE_ARG(mode));
e3bb355c
VS		 1825 }
1826 intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
1827 intel_tv_scale_mode_vert(mode, input->h, 0, 0);
1828 intel_tv_set_mode_type(mode, tv_mode);
5023520f 1829
e3bb355c 1830 drm_mode_set_name(mode);
5023520f 1831
e3bb355c 1832 drm_mode_probed_add(connector, mode);
02c5dd98 1833 count++;
79e53945
JB		 1834 }
1835
02c5dd98 1836 return count;
79e53945
JB		 1837}
1838
79e53945 1839static const struct drm_connector_funcs intel_tv_connector_funcs = {
1ebaa0b9 1840 .late_register = intel_connector_register,
c191eca1 1841 .early_unregister = intel_connector_unregister,
d4b26e4f 1842 .destroy = intel_connector_destroy,
79e53945 1843 .fill_modes = drm_helper_probe_single_connector_modes,
c6f95f27 1844 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
690157f0 1845 .atomic_duplicate_state = intel_tv_connector_duplicate_state,
79e53945
JB		 1846};
1847
0e891b3f 1848static int intel_tv_atomic_check(struct drm_connector *connector,
6f3b6278 1849 struct drm_atomic_state *state)
0e891b3f 1850{
6f3b6278 1851 struct drm_connector_state *new_state;
0e891b3f
ML		 1852 struct drm_crtc_state *new_crtc_state;
1853 struct drm_connector_state *old_state;
1854
6f3b6278 1855 new_state = drm_atomic_get_new_connector_state(state, connector);
0e891b3f
ML		 1856 if (!new_state->crtc)
1857 return 0;
1858
6f3b6278
SP		 1859 old_state = drm_atomic_get_old_connector_state(state, connector);
1860 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
0e891b3f 1861
fb1e8812 1862 if (old_state->tv.legacy_mode != new_state->tv.legacy_mode ||
0e891b3f
ML		 1863 old_state->tv.margins.left != new_state->tv.margins.left ||
1864 old_state->tv.margins.right != new_state->tv.margins.right ||
1865 old_state->tv.margins.top != new_state->tv.margins.top ||
1866 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
1867 /* Force a modeset. */
1868
1869 new_crtc_state->connectors_changed = true;
1870 }
1871
1872 return 0;
1873}
1874
79e53945 1875static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
6c5ed5ae 1876 .detect_ctx = intel_tv_detect,
79e53945
JB		 1877 .mode_valid = intel_tv_mode_valid,
1878 .get_modes = intel_tv_get_modes,
0e891b3f 1879 .atomic_check = intel_tv_atomic_check,
79e53945
JB		 1880};
1881
79e53945 1882static const struct drm_encoder_funcs intel_tv_enc_funcs = {
ea5b213a 1883 .destroy = intel_encoder_destroy,
79e53945
JB		 1884};
1885
d7e4a257
VS		 1886static void intel_tv_add_properties(struct drm_connector *connector)
1887{
1888 struct drm_i915_private *i915 = to_i915(connector->dev);
1889 struct drm_connector_state *conn_state = connector->state;
1890 const char *tv_format_names[ARRAY_SIZE(tv_modes)];
1891 int i;
1892
1893 /* BIOS margin values */
1894 conn_state->tv.margins.left = 54;
1895 conn_state->tv.margins.top = 36;
1896 conn_state->tv.margins.right = 46;
1897 conn_state->tv.margins.bottom = 37;
1898
fb1e8812 1899 conn_state->tv.legacy_mode = 0;
d7e4a257
VS		 1900
1901 /* Create TV properties then attach current values */
1902 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1903 /* 1080p50/1080p60 not supported on gen3 */
1904 if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1)
1905 break;
1906
1907 tv_format_names[i] = tv_modes[i].name;
1908 }
80ed86d4 1909 drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names);
d7e4a257
VS		 1910
1911 drm_object_attach_property(&connector->base,
1fd4a5a3 1912 i915->drm.mode_config.legacy_tv_mode_property,
fb1e8812 1913 conn_state->tv.legacy_mode);
d7e4a257
VS		 1914 drm_object_attach_property(&connector->base,
1915 i915->drm.mode_config.tv_left_margin_property,
1916 conn_state->tv.margins.left);
1917 drm_object_attach_property(&connector->base,
1918 i915->drm.mode_config.tv_top_margin_property,
1919 conn_state->tv.margins.top);
1920 drm_object_attach_property(&connector->base,
1921 i915->drm.mode_config.tv_right_margin_property,
1922 conn_state->tv.margins.right);
1923 drm_object_attach_property(&connector->base,
1924 i915->drm.mode_config.tv_bottom_margin_property,
1925 conn_state->tv.margins.bottom);
1926}
1927
79e53945 1928void
c39055b0 1929intel_tv_init(struct drm_i915_private *dev_priv)
79e53945 1930{
79e53945 1931 struct drm_connector *connector;
ea5b213a 1932 struct intel_tv *intel_tv;
21d40d37 1933 struct intel_encoder *intel_encoder;
0c41ee2b 1934 struct intel_connector *intel_connector;
79e53945 1935 u32 tv_dac_on, tv_dac_off, save_tv_dac;
79e53945 1936
988ff27b 1937 if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
79e53945
JB		 1938 return;
1939
3bdd14d5 1940 if (!intel_bios_is_tv_present(dev_priv)) {
025c2e19 1941 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
c3561438
ZY		 1942 return;
1943 }
79e53945
JB		 1944
1945 /*
1946 * Sanity check the TV output by checking to see if the
1947 * DAC register holds a value
1948 */
988ff27b 1949 save_tv_dac = intel_de_read(dev_priv, TV_DAC);
79e53945 1950
988ff27b
JN		 1951 intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1952 tv_dac_on = intel_de_read(dev_priv, TV_DAC);
79e53945 1953
988ff27b
JN		 1954 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1955 tv_dac_off = intel_de_read(dev_priv, TV_DAC);
79e53945 1956
988ff27b 1957 intel_de_write(dev_priv, TV_DAC, save_tv_dac);
79e53945
JB		 1958
1959 /*
1960 * If the register does not hold the state change enable
1961 * bit, (either as a 0 or a 1), assume it doesn't really
1962 * exist
1963 */
1964 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1965 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1966 return;
1967
b14c5679 1968 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
ea5b213a 1969 if (!intel_tv) {
79e53945
JB		 1970 return;
1971 }
f8aed700 1972
08d9bc92 1973 intel_connector = intel_connector_alloc();
0c41ee2b 1974 if (!intel_connector) {
ea5b213a 1975 kfree(intel_tv);
0c41ee2b
ZW		 1976 return;
1977 }
1978
ea5b213a 1979 intel_encoder = &intel_tv->base;
0c41ee2b 1980 connector = &intel_connector->base;
79e53945 1981
3930f18a
CW		 1982 /*
1983 * The documentation, for the older chipsets at least, recommend
8102e126
CW		 1984 * using a polling method rather than hotplug detection for TVs.
1985 * This is because in order to perform the hotplug detection, the PLLs
1986 * for the TV must be kept alive increasing power drain and starving
1987 * bandwidth from other encoders. Notably for instance, it causes
1988 * pipe underruns on Crestline when this encoder is supposedly idle.
1989 *
1990 * More recent chipsets favour HDMI rather than integrated S-Video.
1991 */
821450c6 1992 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
8102e126 1993
3703060d 1994 drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs,
79e53945
JB		 1995 DRM_MODE_CONNECTOR_SVIDEO);
1996
3703060d 1997 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs,
580d8ed5 1998 DRM_MODE_ENCODER_TVDAC, "TV");
79e53945 1999
5d2d38dd 2000 intel_encoder->compute_config = intel_tv_compute_config;
7a495cfd 2001 intel_encoder->get_config = intel_tv_get_config;
809a2a8b 2002 intel_encoder->pre_enable = intel_tv_pre_enable;
6b5756a0
DV		 2003 intel_encoder->enable = intel_enable_tv;
2004 intel_encoder->disable = intel_disable_tv;
9a8ee983
DV		 2005 intel_encoder->get_hw_state = intel_tv_get_hw_state;
2006 intel_connector->get_hw_state = intel_connector_get_hw_state;
6b5756a0 2007
df0e9248 2008 intel_connector_attach_encoder(intel_connector, intel_encoder);
03cdc1d4 2009
21d40d37 2010 intel_encoder->type = INTEL_OUTPUT_TVOUT;
79f255a0 2011 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 2012 intel_encoder->port = PORT_NONE;
34053ee1 2013 intel_encoder->pipe_mask = ~0;
bc079e8b 2014 intel_encoder->cloneable = 0;
ea5b213a 2015 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
79e53945 2016
79e53945 2017 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
79e53945 2018
d7e4a257 2019 intel_tv_add_properties(connector);
79e53945 2020}
Linux 6.x block layer and io_uring tree(s)