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drm/i915: Pass intel_connector to intel_panel_{init,fini}()
[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_tv.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29/** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ec7f29ff 36
79e53945 37#include "i915_drv.h"
ec7f29ff 38#include "intel_connector.h"
fd2b94a5 39#include "intel_crtc.h"
7785ae0b 40#include "intel_de.h"
1d455f8d 41#include "intel_display_types.h"
dbeb38d9 42#include "intel_hotplug.h"
efe57eea 43#include "intel_tv.h"
79e53945
JB		 44
45enum tv_margin {
46 TV_MARGIN_LEFT, TV_MARGIN_TOP,
47 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
48};
49
ea5b213a
CW		 50struct intel_tv {
51 struct intel_encoder base;
52
79e53945 53 int type;
79e53945
JB		 54};
55
56struct video_levels {
db49296b
TU		 57 u16 blank, black;
58 u8 burst;
79e53945
JB		 59};
60
61struct color_conversion {
62 u16 ry, gy, by, ay;
63 u16 ru, gu, bu, au;
64 u16 rv, gv, bv, av;
65};
66
67static const u32 filter_table[] = {
68 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
69 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
70 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
71 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
72 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
73 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
74 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
75 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
76 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
77 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
78 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
79 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
80 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
81 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
82 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
83 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
84 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
85 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
86 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
87 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
88 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
89 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
90 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
91 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
92 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
93 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
94 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
95 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
96 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
97 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
98 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
99 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
100 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
101 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
102 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
103 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
104 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
105 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
106 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
107 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
108 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
109 0x2D002CC0, 0x30003640, 0x2D0036C0,
110 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
111 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
112 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
113 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
114 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
115 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
116 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
117 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
118 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
119 0x28003100, 0x28002F00, 0x00003100,
120};
121
122/*
123 * Color conversion values have 3 separate fixed point formats:
124 *
125 * 10 bit fields (ay, au)
126 * 1.9 fixed point (b.bbbbbbbbb)
127 * 11 bit fields (ry, by, ru, gu, gv)
128 * exp.mantissa (ee.mmmmmmmmm)
129 * ee = 00 = 10^-1 (0.mmmmmmmmm)
130 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
131 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
132 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
133 * 12 bit fields (gy, rv, bu)
134 * exp.mantissa (eee.mmmmmmmmm)
135 * eee = 000 = 10^-1 (0.mmmmmmmmm)
136 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
137 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
138 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
139 * eee = 100 = reserved
140 * eee = 101 = reserved
141 * eee = 110 = reserved
142 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
143 *
144 * Saturation and contrast are 8 bits, with their own representation:
145 * 8 bit field (saturation, contrast)
146 * exp.mantissa (ee.mmmmmm)
147 * ee = 00 = 10^-1 (0.mmmmmm)
148 * ee = 01 = 10^0 (m.mmmmm)
149 * ee = 10 = 10^1 (mm.mmmm)
150 * ee = 11 = 10^2 (mmm.mmm)
151 *
152 * Simple conversion function:
153 *
154 * static u32
155 * float_to_csc_11(float f)
156 * {
157 * u32 exp;
158 * u32 mant;
159 * u32 ret;
160 *
161 * if (f < 0)
162 * f = -f;
163 *
164 * if (f >= 1) {
165 * exp = 0x7;
0206e353 166 * mant = 1 << 8;
79e53945
JB		 167 * } else {
168 * for (exp = 0; exp < 3 && f < 0.5; exp++)
0206e353 169 * f *= 2.0;
79e53945
JB		 170 * mant = (f * (1 << 9) + 0.5);
171 * if (mant >= (1 << 9))
172 * mant = (1 << 9) - 1;
173 * }
174 * ret = (exp << 9) | mant;
175 * return ret;
176 * }
177 */
178
179/*
180 * Behold, magic numbers! If we plant them they might grow a big
181 * s-video cable to the sky... or something.
182 *
183 * Pre-converted to appropriate hex value.
184 */
185
186/*
187 * PAL & NTSC values for composite & s-video connections
188 */
189static const struct color_conversion ntsc_m_csc_composite = {
190 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 191 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
192 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 193};
194
195static const struct video_levels ntsc_m_levels_composite = {
196 .blank = 225, .black = 267, .burst = 113,
197};
198
199static const struct color_conversion ntsc_m_csc_svideo = {
ba01079c
ZW		 200 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
201 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
202 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 203};
204
205static const struct video_levels ntsc_m_levels_svideo = {
206 .blank = 266, .black = 316, .burst = 133,
207};
208
209static const struct color_conversion ntsc_j_csc_composite = {
210 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
ba01079c
ZW		 211 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
212 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
79e53945
JB		 213};
214
215static const struct video_levels ntsc_j_levels_composite = {
216 .blank = 225, .black = 225, .burst = 113,
217};
218
219static const struct color_conversion ntsc_j_csc_svideo = {
220 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
ba01079c
ZW		 221 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
222 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
79e53945
JB		 223};
224
225static const struct video_levels ntsc_j_levels_svideo = {
226 .blank = 266, .black = 266, .burst = 133,
227};
228
229static const struct color_conversion pal_csc_composite = {
230 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
ba01079c
ZW		 231 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
232 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
79e53945
JB		 233};
234
235static const struct video_levels pal_levels_composite = {
236 .blank = 237, .black = 237, .burst = 118,
237};
238
239static const struct color_conversion pal_csc_svideo = {
240 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
ba01079c
ZW		 241 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
242 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
79e53945
JB		 243};
244
245static const struct video_levels pal_levels_svideo = {
246 .blank = 280, .black = 280, .burst = 139,
247};
248
249static const struct color_conversion pal_m_csc_composite = {
250 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 251 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
252 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 253};
254
255static const struct video_levels pal_m_levels_composite = {
256 .blank = 225, .black = 267, .burst = 113,
257};
258
259static const struct color_conversion pal_m_csc_svideo = {
ba01079c
ZW		 260 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
261 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
262 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 263};
264
265static const struct video_levels pal_m_levels_svideo = {
266 .blank = 266, .black = 316, .burst = 133,
267};
268
269static const struct color_conversion pal_n_csc_composite = {
270 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 271 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
272 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 273};
274
275static const struct video_levels pal_n_levels_composite = {
276 .blank = 225, .black = 267, .burst = 118,
277};
278
279static const struct color_conversion pal_n_csc_svideo = {
ba01079c
ZW		 280 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
281 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
282 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 283};
284
285static const struct video_levels pal_n_levels_svideo = {
286 .blank = 266, .black = 316, .burst = 139,
287};
288
289/*
290 * Component connections
291 */
292static const struct color_conversion sdtv_csc_yprpb = {
ba01079c
ZW		 293 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
294 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
295 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
79e53945
JB		 296};
297
79e53945 298static const struct color_conversion hdtv_csc_yprpb = {
ba01079c
ZW		 299 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
300 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
301 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
79e53945
JB		 302};
303
79e53945
JB		 304static const struct video_levels component_levels = {
305 .blank = 279, .black = 279, .burst = 0,
306};
307
308
309struct tv_mode {
763a4a01 310 const char *name;
db49296b
TU		 311
312 u32 clock;
313 u16 refresh; /* in millihertz (for precision) */
4f503798 314 u8 oversample;
db49296b
TU		 315 u8 hsync_end;
316 u16 hblank_start, hblank_end, htotal;
317 bool progressive : 1, trilevel_sync : 1, component_only : 1;
318 u8 vsync_start_f1, vsync_start_f2, vsync_len;
319 bool veq_ena : 1;
320 u8 veq_start_f1, veq_start_f2, veq_len;
321 u8 vi_end_f1, vi_end_f2;
322 u16 nbr_end;
323 bool burst_ena : 1;
324 u8 hburst_start, hburst_len;
325 u8 vburst_start_f1;
326 u16 vburst_end_f1;
327 u8 vburst_start_f2;
328 u16 vburst_end_f2;
329 u8 vburst_start_f3;
330 u16 vburst_end_f3;
331 u8 vburst_start_f4;
332 u16 vburst_end_f4;
79e53945
JB		 333 /*
334 * subcarrier programming
335 */
db49296b
TU		 336 u16 dda2_size, dda3_size;
337 u8 dda1_inc;
338 u16 dda2_inc, dda3_inc;
79e53945 339 u32 sc_reset;
db49296b 340 bool pal_burst : 1;
79e53945
JB		 341 /*
342 * blank/black levels
343 */
344 const struct video_levels *composite_levels, *svideo_levels;
345 const struct color_conversion *composite_color, *svideo_color;
346 const u32 *filter_table;
79e53945
JB		 347};
348
349
350/*
351 * Sub carrier DDA
352 *
353 * I think this works as follows:
354 *
355 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
356 *
357 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
358 *
359 * So,
360 * dda1_ideal = subcarrier/pixel * 4096
361 * dda1_inc = floor (dda1_ideal)
362 * dda2 = dda1_ideal - dda1_inc
363 *
364 * then pick a ratio for dda2 that gives the closest approximation. If
365 * you can't get close enough, you can play with dda3 as well. This
366 * seems likely to happen when dda2 is small as the jumps would be larger
367 *
368 * To invert this,
369 *
370 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
371 *
372 * The constants below were all computed using a 107.520MHz clock
373 */
374
3930f18a 375/*
79e53945
JB		 376 * Register programming values for TV modes.
377 *
378 * These values account for -1s required.
379 */
005568be 380static const struct tv_mode tv_modes[] = {
79e53945
JB		 381 {
382 .name = "NTSC-M",
ba01079c 383 .clock = 108000,
23bd15ec 384 .refresh = 59940,
4f503798 385 .oversample = 8,
56f62308 386 .component_only = false,
79e53945
JB		 387 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
388
389 .hsync_end = 64, .hblank_end = 124,
390 .hblank_start = 836, .htotal = 857,
391
392 .progressive = false, .trilevel_sync = false,
393
394 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
395 .vsync_len = 6,
396
0206e353 397 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 398 .veq_start_f2 = 1, .veq_len = 18,
399
400 .vi_end_f1 = 20, .vi_end_f2 = 21,
401 .nbr_end = 240,
402
403 .burst_ena = true,
404 .hburst_start = 72, .hburst_len = 34,
405 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
406 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
407 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
408 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
409
410 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 411 .dda1_inc = 135,
412 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 413 .dda3_inc = 0, .dda3_size = 0,
414 .sc_reset = TV_SC_RESET_EVERY_4,
415 .pal_burst = false,
416
417 .composite_levels = &ntsc_m_levels_composite,
418 .composite_color = &ntsc_m_csc_composite,
419 .svideo_levels = &ntsc_m_levels_svideo,
420 .svideo_color = &ntsc_m_csc_svideo,
421
422 .filter_table = filter_table,
423 },
424 {
425 .name = "NTSC-443",
ba01079c 426 .clock = 108000,
23bd15ec 427 .refresh = 59940,
4f503798 428 .oversample = 8,
56f62308 429 .component_only = false,
79e53945
JB		 430 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
431 .hsync_end = 64, .hblank_end = 124,
432 .hblank_start = 836, .htotal = 857,
433
434 .progressive = false, .trilevel_sync = false,
435
436 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
437 .vsync_len = 6,
438
0206e353 439 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 440 .veq_start_f2 = 1, .veq_len = 18,
441
442 .vi_end_f1 = 20, .vi_end_f2 = 21,
443 .nbr_end = 240,
444
3ca87e82 445 .burst_ena = true,
79e53945
JB		 446 .hburst_start = 72, .hburst_len = 34,
447 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
448 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
449 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
450 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
451
452 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
453 .dda1_inc = 168,
ba01079c
ZW		 454 .dda2_inc = 4093, .dda2_size = 27456,
455 .dda3_inc = 310, .dda3_size = 525,
456 .sc_reset = TV_SC_RESET_NEVER,
457 .pal_burst = false,
79e53945
JB		 458
459 .composite_levels = &ntsc_m_levels_composite,
460 .composite_color = &ntsc_m_csc_composite,
461 .svideo_levels = &ntsc_m_levels_svideo,
462 .svideo_color = &ntsc_m_csc_svideo,
463
464 .filter_table = filter_table,
465 },
466 {
467 .name = "NTSC-J",
ba01079c 468 .clock = 108000,
23bd15ec 469 .refresh = 59940,
4f503798 470 .oversample = 8,
56f62308 471 .component_only = false,
79e53945
JB		 472
473 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
474 .hsync_end = 64, .hblank_end = 124,
475 .hblank_start = 836, .htotal = 857,
476
477 .progressive = false, .trilevel_sync = false,
478
479 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
480 .vsync_len = 6,
481
0206e353 482 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 483 .veq_start_f2 = 1, .veq_len = 18,
484
485 .vi_end_f1 = 20, .vi_end_f2 = 21,
486 .nbr_end = 240,
487
488 .burst_ena = true,
489 .hburst_start = 72, .hburst_len = 34,
490 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
491 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
492 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
493 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
494
495 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 496 .dda1_inc = 135,
497 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 498 .dda3_inc = 0, .dda3_size = 0,
499 .sc_reset = TV_SC_RESET_EVERY_4,
500 .pal_burst = false,
501
502 .composite_levels = &ntsc_j_levels_composite,
503 .composite_color = &ntsc_j_csc_composite,
504 .svideo_levels = &ntsc_j_levels_svideo,
505 .svideo_color = &ntsc_j_csc_svideo,
506
507 .filter_table = filter_table,
508 },
509 {
510 .name = "PAL-M",
ba01079c 511 .clock = 108000,
23bd15ec 512 .refresh = 59940,
4f503798 513 .oversample = 8,
56f62308 514 .component_only = false,
79e53945
JB		 515
516 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
517 .hsync_end = 64, .hblank_end = 124,
518 .hblank_start = 836, .htotal = 857,
519
520 .progressive = false, .trilevel_sync = false,
521
522 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
523 .vsync_len = 6,
524
0206e353 525 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 526 .veq_start_f2 = 1, .veq_len = 18,
527
528 .vi_end_f1 = 20, .vi_end_f2 = 21,
529 .nbr_end = 240,
530
531 .burst_ena = true,
532 .hburst_start = 72, .hburst_len = 34,
533 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
534 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
535 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
536 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
537
538 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 539 .dda1_inc = 135,
540 .dda2_inc = 16704, .dda2_size = 27456,
79e53945 541 .dda3_inc = 0, .dda3_size = 0,
ba01079c
ZW		 542 .sc_reset = TV_SC_RESET_EVERY_8,
543 .pal_burst = true,
79e53945
JB		 544
545 .composite_levels = &pal_m_levels_composite,
546 .composite_color = &pal_m_csc_composite,
547 .svideo_levels = &pal_m_levels_svideo,
548 .svideo_color = &pal_m_csc_svideo,
549
550 .filter_table = filter_table,
551 },
552 {
553 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
554 .name = "PAL-N",
ba01079c 555 .clock = 108000,
23bd15ec 556 .refresh = 50000,
4f503798 557 .oversample = 8,
56f62308 558 .component_only = false,
79e53945
JB		 559
560 .hsync_end = 64, .hblank_end = 128,
561 .hblank_start = 844, .htotal = 863,
562
563 .progressive = false, .trilevel_sync = false,
564
565
566 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
567 .vsync_len = 6,
568
0206e353 569 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 570 .veq_start_f2 = 1, .veq_len = 18,
571
572 .vi_end_f1 = 24, .vi_end_f2 = 25,
573 .nbr_end = 286,
574
575 .burst_ena = true,
0206e353 576 .hburst_start = 73, .hburst_len = 34,
79e53945
JB		 577 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
578 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
579 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
580 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
581
582
583 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
ba01079c
ZW		 584 .dda1_inc = 135,
585 .dda2_inc = 23578, .dda2_size = 27648,
586 .dda3_inc = 134, .dda3_size = 625,
79e53945
JB		 587 .sc_reset = TV_SC_RESET_EVERY_8,
588 .pal_burst = true,
589
590 .composite_levels = &pal_n_levels_composite,
591 .composite_color = &pal_n_csc_composite,
592 .svideo_levels = &pal_n_levels_svideo,
593 .svideo_color = &pal_n_csc_svideo,
594
595 .filter_table = filter_table,
596 },
597 {
598 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
599 .name = "PAL",
ba01079c 600 .clock = 108000,
23bd15ec 601 .refresh = 50000,
4f503798 602 .oversample = 8,
56f62308 603 .component_only = false,
79e53945 604
ba01079c 605 .hsync_end = 64, .hblank_end = 142,
79e53945
JB		 606 .hblank_start = 844, .htotal = 863,
607
608 .progressive = false, .trilevel_sync = false,
609
610 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
611 .vsync_len = 5,
612
0206e353 613 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 614 .veq_start_f2 = 1, .veq_len = 15,
615
616 .vi_end_f1 = 24, .vi_end_f2 = 25,
617 .nbr_end = 286,
618
619 .burst_ena = true,
620 .hburst_start = 73, .hburst_len = 32,
621 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
622 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
623 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
624 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
625
626 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
627 .dda1_inc = 168,
ba01079c
ZW		 628 .dda2_inc = 4122, .dda2_size = 27648,
629 .dda3_inc = 67, .dda3_size = 625,
79e53945
JB		 630 .sc_reset = TV_SC_RESET_EVERY_8,
631 .pal_burst = true,
632
633 .composite_levels = &pal_levels_composite,
634 .composite_color = &pal_csc_composite,
635 .svideo_levels = &pal_levels_svideo,
636 .svideo_color = &pal_csc_svideo,
637
638 .filter_table = filter_table,
639 },
9589919f
RV		 640 {
641 .name = "480p",
d5152823 642 .clock = 108000,
9589919f 643 .refresh = 59940,
4f503798 644 .oversample = 4,
56f62308 645 .component_only = true,
9589919f
RV		 646
647 .hsync_end = 64, .hblank_end = 122,
648 .hblank_start = 842, .htotal = 857,
649
650 .progressive = true, .trilevel_sync = false,
651
652 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
653 .vsync_len = 12,
654
655 .veq_ena = false,
656
657 .vi_end_f1 = 44, .vi_end_f2 = 44,
658 .nbr_end = 479,
659
660 .burst_ena = false,
661
662 .filter_table = filter_table,
663 },
664 {
665 .name = "576p",
d5152823 666 .clock = 108000,
9589919f 667 .refresh = 50000,
4f503798 668 .oversample = 4,
56f62308 669 .component_only = true,
9589919f
RV		 670
671 .hsync_end = 64, .hblank_end = 139,
672 .hblank_start = 859, .htotal = 863,
673
674 .progressive = true, .trilevel_sync = false,
675
676 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
677 .vsync_len = 10,
678
679 .veq_ena = false,
680
681 .vi_end_f1 = 48, .vi_end_f2 = 48,
682 .nbr_end = 575,
683
684 .burst_ena = false,
685
686 .filter_table = filter_table,
687 },
79e53945
JB		 688 {
689 .name = "720p@60Hz",
d5152823 690 .clock = 148500,
79e53945 691 .refresh = 60000,
4f503798 692 .oversample = 2,
56f62308 693 .component_only = true,
79e53945
JB		 694
695 .hsync_end = 80, .hblank_end = 300,
696 .hblank_start = 1580, .htotal = 1649,
697
0206e353 698 .progressive = true, .trilevel_sync = true,
79e53945
JB		 699
700 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
701 .vsync_len = 10,
702
703 .veq_ena = false,
704
705 .vi_end_f1 = 29, .vi_end_f2 = 29,
706 .nbr_end = 719,
707
708 .burst_ena = false,
709
710 .filter_table = filter_table,
711 },
79e53945
JB		 712 {
713 .name = "720p@50Hz",
d5152823 714 .clock = 148500,
79e53945 715 .refresh = 50000,
4f503798 716 .oversample = 2,
56f62308 717 .component_only = true,
79e53945
JB		 718
719 .hsync_end = 80, .hblank_end = 300,
720 .hblank_start = 1580, .htotal = 1979,
721
0206e353 722 .progressive = true, .trilevel_sync = true,
79e53945
JB		 723
724 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
725 .vsync_len = 10,
726
727 .veq_ena = false,
728
729 .vi_end_f1 = 29, .vi_end_f2 = 29,
730 .nbr_end = 719,
731
732 .burst_ena = false,
733
734 .filter_table = filter_table,
79e53945
JB		 735 },
736 {
737 .name = "1080i@50Hz",
d5152823 738 .clock = 148500,
23bd15ec 739 .refresh = 50000,
4f503798 740 .oversample = 2,
56f62308 741 .component_only = true,
79e53945
JB		 742
743 .hsync_end = 88, .hblank_end = 235,
744 .hblank_start = 2155, .htotal = 2639,
745
0206e353 746 .progressive = false, .trilevel_sync = true,
79e53945
JB		 747
748 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
749 .vsync_len = 10,
750
0206e353 751 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 752 .veq_start_f2 = 4, .veq_len = 10,
753
754
755 .vi_end_f1 = 21, .vi_end_f2 = 22,
756 .nbr_end = 539,
757
758 .burst_ena = false,
759
760 .filter_table = filter_table,
761 },
762 {
763 .name = "1080i@60Hz",
d5152823 764 .clock = 148500,
23bd15ec 765 .refresh = 60000,
4f503798 766 .oversample = 2,
56f62308 767 .component_only = true,
79e53945
JB		 768
769 .hsync_end = 88, .hblank_end = 235,
770 .hblank_start = 2155, .htotal = 2199,
771
0206e353 772 .progressive = false, .trilevel_sync = true,
79e53945
JB		 773
774 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
775 .vsync_len = 10,
776
0206e353 777 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 778 .veq_start_f2 = 4, .veq_len = 10,
779
780
781 .vi_end_f1 = 21, .vi_end_f2 = 22,
782 .nbr_end = 539,
783
784 .burst_ena = false,
785
79e53945
JB		 786 .filter_table = filter_table,
787 },
a0ff6779
VS		 788
789 {
790 .name = "1080p@30Hz",
791 .clock = 148500,
792 .refresh = 30000,
793 .oversample = 2,
794 .component_only = true,
795
796 .hsync_end = 88, .hblank_end = 235,
797 .hblank_start = 2155, .htotal = 2199,
798
799 .progressive = true, .trilevel_sync = true,
800
801 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
802 .vsync_len = 10,
803
804 .veq_ena = false, .veq_start_f1 = 0,
805 .veq_start_f2 = 0, .veq_len = 0,
806
807 .vi_end_f1 = 44, .vi_end_f2 = 44,
808 .nbr_end = 1079,
809
810 .burst_ena = false,
811
812 .filter_table = filter_table,
813 },
814
815 {
816 .name = "1080p@50Hz",
817 .clock = 148500,
818 .refresh = 50000,
819 .oversample = 1,
820 .component_only = true,
821
822 .hsync_end = 88, .hblank_end = 235,
823 .hblank_start = 2155, .htotal = 2639,
824
825 .progressive = true, .trilevel_sync = true,
826
827 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
828 .vsync_len = 10,
829
830 .veq_ena = false, .veq_start_f1 = 0,
831 .veq_start_f2 = 0, .veq_len = 0,
832
833 .vi_end_f1 = 44, .vi_end_f2 = 44,
834 .nbr_end = 1079,
835
836 .burst_ena = false,
837
838 .filter_table = filter_table,
839 },
840
841 {
842 .name = "1080p@60Hz",
843 .clock = 148500,
844 .refresh = 60000,
845 .oversample = 1,
846 .component_only = true,
847
848 .hsync_end = 88, .hblank_end = 235,
849 .hblank_start = 2155, .htotal = 2199,
850
851 .progressive = true, .trilevel_sync = true,
852
853 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
854 .vsync_len = 10,
855
856 .veq_ena = false, .veq_start_f1 = 0,
857 .veq_start_f2 = 0, .veq_len = 0,
858
859 .vi_end_f1 = 44, .vi_end_f2 = 44,
860 .nbr_end = 1079,
861
862 .burst_ena = false,
863
864 .filter_table = filter_table,
865 },
79e53945
JB		 866};
867
690157f0
VS		 868struct intel_tv_connector_state {
869 struct drm_connector_state base;
870
871 /*
872 * May need to override the user margins for
873 * gen3 >1024 wide source vertical centering.
874 */
875 struct {
876 u16 top, bottom;
877 } margins;
878
879 bool bypass_vfilter;
880};
881
882#define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base)
883
884static struct drm_connector_state *
885intel_tv_connector_duplicate_state(struct drm_connector *connector)
886{
887 struct intel_tv_connector_state *state;
888
889 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
890 if (!state)
891 return NULL;
892
893 __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
894 return &state->base;
895}
896
cd91ef23 897static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
ea5b213a 898{
cd91ef23 899 return container_of(encoder, struct intel_tv, base);
ea5b213a
CW		 900}
901
43a6d19c 902static struct intel_tv *intel_attached_tv(struct intel_connector *connector)
df0e9248 903{
cd91ef23 904 return enc_to_tv(intel_attached_encoder(connector));
df0e9248
CW		 905}
906
9a8ee983
DV		 907static bool
908intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
909{
4add0f6b 910 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
988ff27b 911 u32 tmp = intel_de_read(dev_priv, TV_CTL);
9a8ee983 912
4add0f6b 913 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
9a8ee983 914
4add0f6b 915 return tmp & TV_ENC_ENABLE;
9a8ee983
DV		 916}
917
79e53945 918static void
ede9771d
VS		 919intel_enable_tv(struct intel_atomic_state *state,
920 struct intel_encoder *encoder,
5f88a9c6
VS		 921 const struct intel_crtc_state *pipe_config,
922 const struct drm_connector_state *conn_state)
79e53945 923{
6b5756a0 924 struct drm_device *dev = encoder->base.dev;
fac5e23e 925 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 926
7a98948f 927 /* Prevents vblank waits from timing out in intel_tv_detect_type() */
7b06894b 928 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
7a98948f 929
988ff27b
JN		 930 intel_de_write(dev_priv, TV_CTL,
931 intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE);
6b5756a0
DV		 932}
933
934static void
ede9771d
VS		 935intel_disable_tv(struct intel_atomic_state *state,
936 struct intel_encoder *encoder,
5f88a9c6
VS		 937 const struct intel_crtc_state *old_crtc_state,
938 const struct drm_connector_state *old_conn_state)
6b5756a0
DV		 939{
940 struct drm_device *dev = encoder->base.dev;
fac5e23e 941 struct drm_i915_private *dev_priv = to_i915(dev);
6b5756a0 942
988ff27b
JN		 943 intel_de_write(dev_priv, TV_CTL,
944 intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE);
79e53945
JB		 945}
946
5f88a9c6 947static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
79e53945 948{
0e891b3f 949 int format = conn_state->tv.mode;
79e53945 950
0e891b3f 951 return &tv_modes[format];
79e53945
JB		 952}
953
954static enum drm_mode_status
763a4a01
CW		 955intel_tv_mode_valid(struct drm_connector *connector,
956 struct drm_display_mode *mode)
79e53945 957{
0e891b3f 958 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
54c032b3
MK		 959 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
960
e4dd27aa
VS		 961 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
962 return MODE_NO_DBLESCAN;
963
54c032b3
MK		 964 if (mode->clock > max_dotclk)
965 return MODE_CLOCK_HIGH;
79e53945
JB		 966
967 /* Ensure TV refresh is close to desired refresh */
15de0889
VS		 968 if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000)
969 return MODE_CLOCK_RANGE;
763a4a01 970
15de0889 971 return MODE_OK;
79e53945
JB		 972}
973
65ddf7f9
VS		 974static int
975intel_tv_mode_vdisplay(const struct tv_mode *tv_mode)
976{
977 if (tv_mode->progressive)
978 return tv_mode->nbr_end + 1;
979 else
980 return 2 * (tv_mode->nbr_end + 1);
981}
79e53945 982
e3bb355c
VS		 983static void
984intel_tv_mode_to_mode(struct drm_display_mode *mode,
985 const struct tv_mode *tv_mode)
986{
987 mode->clock = tv_mode->clock /
988 (tv_mode->oversample >> !tv_mode->progressive);
989
990 /*
991 * tv_mode horizontal timings:
992 *
993 * hsync_end
994 * | hblank_end
995 * | | hblank_start
996 * | | | htotal
997 * | _______ |
998 * ____/ \___
999 * \__/ \
1000 */
1001 mode->hdisplay =
1002 tv_mode->hblank_start - tv_mode->hblank_end;
1003 mode->hsync_start = mode->hdisplay +
1004 tv_mode->htotal - tv_mode->hblank_start;
1005 mode->hsync_end = mode->hsync_start +
1006 tv_mode->hsync_end;
1007 mode->htotal = tv_mode->htotal + 1;
1008
1009 /*
1010 * tv_mode vertical timings:
1011 *
1012 * vsync_start
1013 * | vsync_end
1014 * | | vi_end nbr_end
1015 * | | | |
1016 * | | _______
1017 * \__ ____/ \
1018 * \__/
1019 */
1020 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode);
1021 if (tv_mode->progressive) {
1022 mode->vsync_start = mode->vdisplay +
1023 tv_mode->vsync_start_f1 + 1;
1024 mode->vsync_end = mode->vsync_start +
1025 tv_mode->vsync_len;
1026 mode->vtotal = mode->vdisplay +
1027 tv_mode->vi_end_f1 + 1;
1028 } else {
1029 mode->vsync_start = mode->vdisplay +
1030 tv_mode->vsync_start_f1 + 1 +
1031 tv_mode->vsync_start_f2 + 1;
1032 mode->vsync_end = mode->vsync_start +
1033 2 * tv_mode->vsync_len;
1034 mode->vtotal = mode->vdisplay +
1035 tv_mode->vi_end_f1 + 1 +
1036 tv_mode->vi_end_f2 + 1;
1037 }
1038
1039 /* TV has it's own notion of sync and other mode flags, so clear them. */
1040 mode->flags = 0;
1041
e3bb355c
VS		 1042 snprintf(mode->name, sizeof(mode->name),
1043 "%dx%d%c (%s)",
1044 mode->hdisplay, mode->vdisplay,
1045 tv_mode->progressive ? 'p' : 'i',
1046 tv_mode->name);
1047}
1048
1049static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode,
1050 int hdisplay, int left_margin,
1051 int right_margin)
1052{
1053 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin;
1054 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin;
1055 int new_htotal = mode->htotal * hdisplay /
1056 (mode->hdisplay - left_margin - right_margin);
1057
1058 mode->clock = mode->clock * new_htotal / mode->htotal;
1059
1060 mode->hdisplay = hdisplay;
1061 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal;
1062 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal;
1063 mode->htotal = new_htotal;
1064}
1065
1066static void intel_tv_scale_mode_vert(struct drm_display_mode *mode,
1067 int vdisplay, int top_margin,
1068 int bottom_margin)
1069{
1070 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin;
1071 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin;
1072 int new_vtotal = mode->vtotal * vdisplay /
1073 (mode->vdisplay - top_margin - bottom_margin);
1074
1075 mode->clock = mode->clock * new_vtotal / mode->vtotal;
1076
1077 mode->vdisplay = vdisplay;
1078 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal;
1079 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal;
1080 mode->vtotal = new_vtotal;
1081}
1082
7a495cfd
DV		 1083static void
1084intel_tv_get_config(struct intel_encoder *encoder,
5cec258b 1085 struct intel_crtc_state *pipe_config)
7a495cfd 1086{
e3bb355c
VS		 1087 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1088 struct drm_display_mode *adjusted_mode =
1326a92c 1089 &pipe_config->hw.adjusted_mode;
e3bb355c
VS		 1090 struct drm_display_mode mode = {};
1091 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
1092 struct tv_mode tv_mode = {};
1093 int hdisplay = adjusted_mode->crtc_hdisplay;
1094 int vdisplay = adjusted_mode->crtc_vdisplay;
1095 int xsize, ysize, xpos, ypos;
1096
e1214b95
VS		 1097 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
1098
988ff27b
JN		 1099 tv_ctl = intel_de_read(dev_priv, TV_CTL);
1100 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
1101 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
1102 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
1103 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
e3bb355c
VS		 1104
1105 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
1106 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
1107
1108 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT;
1109 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT;
1110
1111 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT;
1112 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT;
1113 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT;
1114
1115 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT;
1116 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT;
1117 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT;
1118
1119 tv_mode.clock = pipe_config->port_clock;
1120
1121 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE;
1122
1123 switch (tv_ctl & TV_OVERSAMPLE_MASK) {
1124 case TV_OVERSAMPLE_8X:
1125 tv_mode.oversample = 8;
1126 break;
1127 case TV_OVERSAMPLE_4X:
1128 tv_mode.oversample = 4;
1129 break;
1130 case TV_OVERSAMPLE_2X:
1131 tv_mode.oversample = 2;
1132 break;
1133 default:
1134 tv_mode.oversample = 1;
1135 break;
1136 }
1137
988ff27b 1138 tmp = intel_de_read(dev_priv, TV_WIN_POS);
e3bb355c
VS		 1139 xpos = tmp >> 16;
1140 ypos = tmp & 0xffff;
1141
988ff27b 1142 tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
e3bb355c
VS		 1143 xsize = tmp >> 16;
1144 ysize = tmp & 0xffff;
1145
1146 intel_tv_mode_to_mode(&mode, &tv_mode);
1147
025c2e19 1148 drm_dbg_kms(&dev_priv->drm, "TV mode:\n");
e3bb355c
VS		 1149 drm_mode_debug_printmodeline(&mode);
1150
1151 intel_tv_scale_mode_horiz(&mode, hdisplay,
1152 xpos, mode.hdisplay - xsize - xpos);
1153 intel_tv_scale_mode_vert(&mode, vdisplay,
1154 ypos, mode.vdisplay - ysize - ypos);
1155
1156 adjusted_mode->crtc_clock = mode.clock;
addc80f0
VS		 1157 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1158 adjusted_mode->crtc_clock /= 2;
8a920e24
VS		 1159
1160 /* pixel counter doesn't work on i965gm TV output */
1161 if (IS_I965GM(dev_priv))
af157b76 1162 pipe_config->mode_flags |=
8a920e24 1163 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
7a495cfd
DV		 1164}
1165
68e94f62
VS		 1166static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
1167 int hdisplay)
1168{
93e7e61e 1169 return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
68e94f62
VS		 1170}
1171
1172static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
1173 const struct drm_connector_state *conn_state,
1174 int vdisplay)
1175{
1176 return tv_mode->crtc_vdisplay -
1177 conn_state->tv.margins.top -
1178 conn_state->tv.margins.bottom !=
1179 vdisplay;
1180}
1181
204474a6 1182static int
5d2d38dd 1183intel_tv_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1184 struct intel_crtc_state *pipe_config,
1185 struct drm_connector_state *conn_state)
79e53945 1186{
690157f0
VS		 1187 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1188 struct intel_tv_connector_state *tv_conn_state =
1189 to_intel_tv_connector_state(conn_state);
0e891b3f 1190 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
e4dd27aa 1191 struct drm_display_mode *adjusted_mode =
1326a92c 1192 &pipe_config->hw.adjusted_mode;
e3bb355c
VS		 1193 int hdisplay = adjusted_mode->crtc_hdisplay;
1194 int vdisplay = adjusted_mode->crtc_vdisplay;
79e53945
JB		 1195
1196 if (!tv_mode)
204474a6 1197 return -EINVAL;
79e53945 1198
e4dd27aa 1199 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
204474a6 1200 return -EINVAL;
e4dd27aa 1201
d9facae6 1202 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
e3bb355c 1203
025c2e19 1204 drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
5d2d38dd
DV		 1205 pipe_config->pipe_bpp = 8*3;
1206
e3bb355c
VS		 1207 pipe_config->port_clock = tv_mode->clock;
1208
1209 intel_tv_mode_to_mode(adjusted_mode, tv_mode);
690157f0
VS		 1210 drm_mode_set_crtcinfo(adjusted_mode, 0);
1211
68e94f62
VS		 1212 if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
1213 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
690157f0
VS		 1214 int extra, top, bottom;
1215
1216 extra = adjusted_mode->crtc_vdisplay - vdisplay;
1217
1218 if (extra < 0) {
025c2e19
WK		 1219 drm_dbg_kms(&dev_priv->drm,
1220 "No vertical scaling for >1024 pixel wide modes\n");
6a2a9404 1221 return -EINVAL;
690157f0
VS		 1222 }
1223
1224 /* Need to turn off the vertical filter and center the image */
1225
1226 /* Attempt to maintain the relative sizes of the margins */
1227 top = conn_state->tv.margins.top;
1228 bottom = conn_state->tv.margins.bottom;
1229
1230 if (top + bottom)
1231 top = extra * top / (top + bottom);
1232 else
1233 top = extra / 2;
1234 bottom = extra - top;
1235
1236 tv_conn_state->margins.top = top;
1237 tv_conn_state->margins.bottom = bottom;
1238
1239 tv_conn_state->bypass_vfilter = true;
1240
addc80f0
VS		 1241 if (!tv_mode->progressive) {
1242 adjusted_mode->clock /= 2;
1243 adjusted_mode->crtc_clock /= 2;
690157f0 1244 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
addc80f0 1245 }
690157f0
VS		 1246 } else {
1247 tv_conn_state->margins.top = conn_state->tv.margins.top;
1248 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom;
1249
1250 tv_conn_state->bypass_vfilter = false;
1251 }
e3bb355c 1252
025c2e19 1253 drm_dbg_kms(&dev_priv->drm, "TV mode:\n");
e3bb355c 1254 drm_mode_debug_printmodeline(adjusted_mode);
1062b815
DV		 1255
1256 /*
e3bb355c
VS		 1257 * The pipe scanline counter behaviour looks as follows when
1258 * using the TV encoder:
1259 *
1260 * time ->
1261 *
1262 * dsl=vtotal-1 | |
1263 * || ||
1264 * ___| | ___| |
1265 * / | / |
1266 * / | / |
1267 * dsl=0 ___/ |_____/ |
1268 * | | | | | |
1269 * ^ ^ ^ ^ ^
1270 * | | | | pipe vblank/first part of tv vblank
1271 * | | | bottom margin
1272 * | | active
1273 * | top margin
1274 * remainder of tv vblank
1275 *
1276 * When the TV encoder is used the pipe wants to run faster
1277 * than expected rate. During the active portion the TV
1278 * encoder stalls the pipe every few lines to keep it in
1279 * check. When the TV encoder reaches the bottom margin the
1280 * pipe simply stops. Once we reach the TV vblank the pipe is
1281 * no longer stalled and it runs at the max rate (apparently
1282 * oversample clock on gen3, cdclk on gen4). Once the pipe
1283 * reaches the pipe vtotal the pipe stops for the remainder
1284 * of the TV vblank/top margin. The pipe starts up again when
1285 * the TV encoder exits the top margin.
1286 *
1287 * To avoid huge hassles for vblank timestamping we scale
1288 * the pipe timings as if the pipe always runs at the average
1289 * rate it maintains during the active period. This also
1290 * gives us a reasonable guesstimate as to the pixel rate.
1291 * Due to the variation in the actual pipe speed the scanline
1292 * counter will give us slightly erroneous results during the
1293 * TV vblank/margins. But since vtotal was selected such that
1294 * it matches the average rate of the pipe during the active
1295 * portion the error shouldn't cause any serious grief to
1296 * vblank timestamps.
1297 *
1298 * For posterity here is the empirically derived formula
1299 * that gives us the maximum length of the pipe vblank
1300 * we can use without causing display corruption. Following
1301 * this would allow us to have a ticking scanline counter
1302 * everywhere except during the bottom margin (there the
1303 * pipe always stops). Ie. this would eliminate the second
1304 * flat portion of the above graph. However this would also
1305 * complicate vblank timestamping as the pipe vtotal would
1306 * no longer match the average rate the pipe runs at during
1307 * the active portion. Hence following this formula seems
1308 * more trouble that it's worth.
1309 *
07960a4c 1310 * if (GRAPHICS_VER(dev_priv) == 4) {
e3bb355c
VS		 1311 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
1312 * den = tv_mode->clock;
1313 * } else {
1314 * num = tv_mode->oversample >> !tv_mode->progressive;
1315 * den = 1;
1316 * }
1317 * max_pipe_vblank_len ~=
1318 * (num * tv_htotal * (tv_vblank_len + top_margin)) /
1319 * (den * pipe_htotal);
1062b815 1320 */
e3bb355c
VS		 1321 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay,
1322 conn_state->tv.margins.left,
1323 conn_state->tv.margins.right);
1324 intel_tv_scale_mode_vert(adjusted_mode, vdisplay,
690157f0
VS		 1325 tv_conn_state->margins.top,
1326 tv_conn_state->margins.bottom);
e3bb355c
VS		 1327 drm_mode_set_crtcinfo(adjusted_mode, 0);
1328 adjusted_mode->name[0] = '\0';
1062b815 1329
8a920e24
VS		 1330 /* pixel counter doesn't work on i965gm TV output */
1331 if (IS_I965GM(dev_priv))
af157b76 1332 pipe_config->mode_flags |=
8a920e24
VS		 1333 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1334
204474a6 1335 return 0;
79e53945
JB		 1336}
1337
8cb92203
DV		 1338static void
1339set_tv_mode_timings(struct drm_i915_private *dev_priv,
1340 const struct tv_mode *tv_mode,
1341 bool burst_ena)
1342{
1343 u32 hctl1, hctl2, hctl3;
1344 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
1345
1346 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
1347 (tv_mode->htotal << TV_HTOTAL_SHIFT);
1348
1349 hctl2 = (tv_mode->hburst_start << 16) |
1350 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
1351
1352 if (burst_ena)
1353 hctl2 |= TV_BURST_ENA;
1354
1355 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
1356 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
1357
1358 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
1359 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
1360 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
1361
1362 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
1363 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
1364 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
1365
1366 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
1367 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1368 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1369
1370 if (tv_mode->veq_ena)
1371 vctl3 |= TV_EQUAL_ENA;
1372
1373 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1374 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1375
1376 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1377 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1378
1379 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1380 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1381
1382 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1383 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1384
988ff27b
JN		 1385 intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
1386 intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
1387 intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
1388 intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
1389 intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
1390 intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
1391 intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
1392 intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
1393 intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
1394 intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
8cb92203
DV		 1395}
1396
b8866ef8
DV		 1397static void set_color_conversion(struct drm_i915_private *dev_priv,
1398 const struct color_conversion *color_conversion)
1399{
1400 if (!color_conversion)
1401 return;
1402
988ff27b
JN		 1403 intel_de_write(dev_priv, TV_CSC_Y,
1404 (color_conversion->ry << 16) | color_conversion->gy);
1405 intel_de_write(dev_priv, TV_CSC_Y2,
1406 (color_conversion->by << 16) | color_conversion->ay);
1407 intel_de_write(dev_priv, TV_CSC_U,
1408 (color_conversion->ru << 16) | color_conversion->gu);
1409 intel_de_write(dev_priv, TV_CSC_U2,
1410 (color_conversion->bu << 16) | color_conversion->au);
1411 intel_de_write(dev_priv, TV_CSC_V,
1412 (color_conversion->rv << 16) | color_conversion->gv);
1413 intel_de_write(dev_priv, TV_CSC_V2,
1414 (color_conversion->bv << 16) | color_conversion->av);
b8866ef8
DV		 1415}
1416
ede9771d
VS		 1417static void intel_tv_pre_enable(struct intel_atomic_state *state,
1418 struct intel_encoder *encoder,
5f88a9c6
VS		 1419 const struct intel_crtc_state *pipe_config,
1420 const struct drm_connector_state *conn_state)
79e53945 1421{
66478475 1422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f15f01a7 1423 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
cd91ef23 1424 struct intel_tv *intel_tv = enc_to_tv(encoder);
690157f0
VS		 1425 const struct intel_tv_connector_state *tv_conn_state =
1426 to_intel_tv_connector_state(conn_state);
0e891b3f 1427 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
690157f0 1428 u32 tv_ctl, tv_filter_ctl;
79e53945
JB		 1429 u32 scctl1, scctl2, scctl3;
1430 int i, j;
1431 const struct video_levels *video_levels;
1432 const struct color_conversion *color_conversion;
1433 bool burst_ena;
bda5f532 1434 int xpos, ypos;
3fa2dd14 1435 unsigned int xsize, ysize;
79e53945
JB		 1436
1437 if (!tv_mode)
1438 return; /* can't happen (mode_prepare prevents this) */
1439
988ff27b 1440 tv_ctl = intel_de_read(dev_priv, TV_CTL);
d2d9f232 1441 tv_ctl &= TV_CTL_SAVE;
79e53945 1442
ea5b213a 1443 switch (intel_tv->type) {
79e53945
JB		 1444 default:
1445 case DRM_MODE_CONNECTOR_Unknown:
1446 case DRM_MODE_CONNECTOR_Composite:
1447 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1448 video_levels = tv_mode->composite_levels;
1449 color_conversion = tv_mode->composite_color;
1450 burst_ena = tv_mode->burst_ena;
1451 break;
1452 case DRM_MODE_CONNECTOR_Component:
1453 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1454 video_levels = &component_levels;
1455 if (tv_mode->burst_ena)
1456 color_conversion = &sdtv_csc_yprpb;
1457 else
1458 color_conversion = &hdtv_csc_yprpb;
1459 burst_ena = false;
1460 break;
1461 case DRM_MODE_CONNECTOR_SVIDEO:
1462 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1463 video_levels = tv_mode->svideo_levels;
1464 color_conversion = tv_mode->svideo_color;
1465 burst_ena = tv_mode->burst_ena;
1466 break;
1467 }
79e53945 1468
f15f01a7 1469 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
4f503798
VS		 1470
1471 switch (tv_mode->oversample) {
1472 case 8:
1473 tv_ctl |= TV_OVERSAMPLE_8X;
1474 break;
1475 case 4:
1476 tv_ctl |= TV_OVERSAMPLE_4X;
1477 break;
1478 case 2:
1479 tv_ctl |= TV_OVERSAMPLE_2X;
1480 break;
1481 default:
1482 tv_ctl |= TV_OVERSAMPLE_NONE;
1483 break;
1484 }
79e53945
JB		 1485
1486 if (tv_mode->progressive)
1487 tv_ctl |= TV_PROGRESSIVE;
1488 if (tv_mode->trilevel_sync)
1489 tv_ctl |= TV_TRILEVEL_SYNC;
1490 if (tv_mode->pal_burst)
1491 tv_ctl |= TV_PAL_BURST;
d271817b 1492
79e53945 1493 scctl1 = 0;
d271817b 1494 if (tv_mode->dda1_inc)
79e53945 1495 scctl1 |= TV_SC_DDA1_EN;
79e53945
JB		 1496 if (tv_mode->dda2_inc)
1497 scctl1 |= TV_SC_DDA2_EN;
79e53945
JB		 1498 if (tv_mode->dda3_inc)
1499 scctl1 |= TV_SC_DDA3_EN;
79e53945 1500 scctl1 |= tv_mode->sc_reset;
d271817b
CW		 1501 if (video_levels)
1502 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
79e53945
JB		 1503 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1504
1505 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1506 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1507
1508 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1509 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1510
1511 /* Enable two fixes for the chips that need them. */
50a0bc90 1512 if (IS_I915GM(dev_priv))
79e53945
JB		 1513 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1514
8cb92203
DV		 1515 set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
1516
988ff27b
JN		 1517 intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
1518 intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
1519 intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
79e53945 1520
b8866ef8 1521 set_color_conversion(dev_priv, color_conversion);
79e53945 1522
005e9537 1523 if (DISPLAY_VER(dev_priv) >= 4)
988ff27b 1524 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
d2d9f232 1525 else
988ff27b 1526 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
d2d9f232 1527
79e53945 1528 if (video_levels)
988ff27b
JN		 1529 intel_de_write(dev_priv, TV_CLR_LEVEL,
1530 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
3fa2dd14 1531
8c66081b 1532 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
3fa2dd14
DV		 1533
1534 /* Filter ctl must be set before TV_WIN_SIZE */
690157f0
VS		 1535 tv_filter_ctl = TV_AUTO_SCALE;
1536 if (tv_conn_state->bypass_vfilter)
1537 tv_filter_ctl |= TV_V_FILTER_BYPASS;
988ff27b 1538 intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
690157f0 1539
3fa2dd14 1540 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
65ddf7f9 1541 ysize = intel_tv_mode_vdisplay(tv_mode);
3fa2dd14 1542
bda5f532 1543 xpos = conn_state->tv.margins.left;
690157f0 1544 ypos = tv_conn_state->margins.top;
0e891b3f
ML		 1545 xsize -= (conn_state->tv.margins.left +
1546 conn_state->tv.margins.right);
690157f0
VS		 1547 ysize -= (tv_conn_state->margins.top +
1548 tv_conn_state->margins.bottom);
988ff27b
JN		 1549 intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
1550 intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
79e53945
JB		 1551
1552 j = 0;
1553 for (i = 0; i < 60; i++)
988ff27b
JN		 1554 intel_de_write(dev_priv, TV_H_LUMA(i),
1555 tv_mode->filter_table[j++]);
79e53945 1556 for (i = 0; i < 60; i++)
988ff27b
JN		 1557 intel_de_write(dev_priv, TV_H_CHROMA(i),
1558 tv_mode->filter_table[j++]);
79e53945 1559 for (i = 0; i < 43; i++)
988ff27b
JN		 1560 intel_de_write(dev_priv, TV_V_LUMA(i),
1561 tv_mode->filter_table[j++]);
79e53945 1562 for (i = 0; i < 43; i++)
988ff27b
JN		 1563 intel_de_write(dev_priv, TV_V_CHROMA(i),
1564 tv_mode->filter_table[j++]);
1565 intel_de_write(dev_priv, TV_DAC,
1566 intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
1567 intel_de_write(dev_priv, TV_CTL, tv_ctl);
79e53945
JB		 1568}
1569
79e53945 1570static int
0206e353 1571intel_tv_detect_type(struct intel_tv *intel_tv,
8102e126 1572 struct drm_connector *connector)
79e53945 1573{
f15f01a7 1574 struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc);
0eadc624 1575 struct drm_device *dev = connector->dev;
fac5e23e 1576 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 1577 u32 tv_ctl, save_tv_ctl;
1578 u32 tv_dac, save_tv_dac;
974b9331 1579 int type;
79e53945
JB		 1580
1581 /* Disable TV interrupts around load detect or we'll recurse */
8102e126 1582 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1583 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1584 i915_disable_pipestat(dev_priv, 0,
755e9019
ID		 1585 PIPE_HOTPLUG_INTERRUPT_STATUS |
1586 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1587 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1588 }
79e53945 1589
988ff27b
JN		 1590 save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
1591 save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
974b9331
CW		 1592
1593 /* Poll for TV detection */
4add0f6b 1594 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
8ed9a5bc 1595 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
f15f01a7 1596 tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
974b9331
CW		 1597
1598 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
8ed9a5bc 1599 tv_dac |= (TVDAC_STATE_CHG_EN |
1600 TVDAC_A_SENSE_CTL |
1601 TVDAC_B_SENSE_CTL |
1602 TVDAC_C_SENSE_CTL |
1603 DAC_CTL_OVERRIDE |
1604 DAC_A_0_7_V |
1605 DAC_B_0_7_V |
1606 DAC_C_0_7_V);
974b9331 1607
d42c9e2c
DV		 1608
1609 /*
1610 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1611 * the TV is misdetected. This is hardware requirement.
1612 */
50a0bc90 1613 if (IS_GM45(dev_priv))
d42c9e2c
DV		 1614 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1615 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1616
988ff27b
JN		 1617 intel_de_write(dev_priv, TV_CTL, tv_ctl);
1618 intel_de_write(dev_priv, TV_DAC, tv_dac);
1619 intel_de_posting_read(dev_priv, TV_DAC);
4f233eff 1620
7b06894b 1621 intel_crtc_wait_for_next_vblank(crtc);
29e1316a 1622
974b9331 1623 type = -1;
988ff27b 1624 tv_dac = intel_de_read(dev_priv, TV_DAC);
025c2e19 1625 drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
2bf71160
KP		 1626 /*
1627 * A B C
1628 * 0 1 1 Composite
1629 * 1 0 X svideo
1630 * 0 0 0 Component
1631 */
1632 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
025c2e19
WK		 1633 drm_dbg_kms(&dev_priv->drm,
1634 "Detected Composite TV connection\n");
2bf71160
KP		 1635 type = DRM_MODE_CONNECTOR_Composite;
1636 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
025c2e19
WK		 1637 drm_dbg_kms(&dev_priv->drm,
1638 "Detected S-Video TV connection\n");
2bf71160
KP		 1639 type = DRM_MODE_CONNECTOR_SVIDEO;
1640 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
025c2e19
WK		 1641 drm_dbg_kms(&dev_priv->drm,
1642 "Detected Component TV connection\n");
2bf71160
KP		 1643 type = DRM_MODE_CONNECTOR_Component;
1644 } else {
025c2e19 1645 drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n");
2bf71160 1646 type = -1;
79e53945
JB		 1647 }
1648
988ff27b
JN		 1649 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1650 intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
1651 intel_de_posting_read(dev_priv, TV_CTL);
bf2125e2
DV		 1652
1653 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
7b06894b 1654 intel_crtc_wait_for_next_vblank(crtc);
974b9331 1655
79e53945 1656 /* Restore interrupt config */
8102e126 1657 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1658 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1659 i915_enable_pipestat(dev_priv, 0,
755e9019
ID		 1660 PIPE_HOTPLUG_INTERRUPT_STATUS |
1661 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1662 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1663 }
79e53945
JB		 1664
1665 return type;
1666}
1667
213c2e64
ML		 1668/*
1669 * Here we set accurate tv format according to connector type
1670 * i.e Component TV should not be assigned by NTSC or PAL
1671 */
1672static void intel_tv_find_better_format(struct drm_connector *connector)
1673{
43a6d19c 1674 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
0e891b3f 1675 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
213c2e64
ML		 1676 int i;
1677
e94390aa
VS		 1678 /* Component supports everything so we can keep the current mode */
1679 if (intel_tv->type == DRM_MODE_CONNECTOR_Component)
213c2e64
ML		 1680 return;
1681
e94390aa
VS		 1682 /* If the current mode is fine don't change it */
1683 if (!tv_mode->component_only)
1684 return;
213c2e64 1685
53abb679 1686 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
e94390aa 1687 tv_mode = &tv_modes[i];
213c2e64 1688
e94390aa 1689 if (!tv_mode->component_only)
213c2e64
ML		 1690 break;
1691 }
1692
0e891b3f 1693 connector->state->tv.mode = i;
213c2e64
ML		 1694}
1695
6c5ed5ae
ML		 1696static int
1697intel_tv_detect(struct drm_connector *connector,
1698 struct drm_modeset_acquire_ctx *ctx,
1699 bool force)
79e53945 1700{
7bee031d 1701 struct drm_i915_private *i915 = to_i915(connector->dev);
43a6d19c 1702 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
bbfb44e8 1703 enum drm_connector_status status;
ea5b213a 1704 int type;
79e53945 1705
7bee031d
JN		 1706 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n",
1707 connector->base.id, connector->name, force);
164c8598 1708
b81dddb9
VS		 1709 if (!INTEL_DISPLAY_ENABLED(i915))
1710 return connector_status_disconnected;
1711
38de45c5 1712 if (force) {
8261b191 1713 struct intel_load_detect_pipe tmp;
6c5ed5ae 1714 int ret;
ea5b213a 1715
25f89954 1716 ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
6c5ed5ae
ML		 1717 if (ret < 0)
1718 return ret;
208bf9fd 1719
6c5ed5ae 1720 if (ret > 0) {
8102e126 1721 type = intel_tv_detect_type(intel_tv, connector);
6c5ed5ae 1722 intel_release_load_detect_pipe(connector, &tmp, ctx);
bbfb44e8
VS		 1723 status = type < 0 ?
1724 connector_status_disconnected :
1725 connector_status_connected;
79e53945 1726 } else
bbfb44e8 1727 status = connector_status_unknown;
bf5a269a 1728
0e891b3f
ML		 1729 if (status == connector_status_connected) {
1730 intel_tv->type = type;
1731 intel_tv_find_better_format(connector);
1732 }
d5627663 1733
0e891b3f
ML		 1734 return status;
1735 } else
1736 return connector->status;
79e53945
JB		 1737}
1738
763a4a01 1739static const struct input_res {
5023520f 1740 u16 w, h;
763a4a01 1741} input_res_table[] = {
5023520f
VS		 1742 { 640, 480 },
1743 { 800, 600 },
1744 { 1024, 768 },
1745 { 1280, 1024 },
1746 { 848, 480 },
1747 { 1280, 720 },
1748 { 1920, 1080 },
79e53945
JB		 1749};
1750
65ddf7f9
VS		 1751/* Choose preferred mode according to line number of TV format */
1752static bool
1753intel_tv_is_preferred_mode(const struct drm_display_mode *mode,
1754 const struct tv_mode *tv_mode)
1755{
1756 int vdisplay = intel_tv_mode_vdisplay(tv_mode);
1757
1758 /* prefer 480 line modes for all SD TV modes */
1759 if (vdisplay <= 576)
1760 vdisplay = 480;
1761
1762 return vdisplay == mode->vdisplay;
1763}
1764
bcae2ca8 1765static void
65ddf7f9
VS		 1766intel_tv_set_mode_type(struct drm_display_mode *mode,
1767 const struct tv_mode *tv_mode)
bcae2ca8 1768{
65ddf7f9
VS		 1769 mode->type = DRM_MODE_TYPE_DRIVER;
1770
1771 if (intel_tv_is_preferred_mode(mode, tv_mode))
1772 mode->type |= DRM_MODE_TYPE_PREFERRED;
bcae2ca8 1773}
1774
79e53945
JB		 1775static int
1776intel_tv_get_modes(struct drm_connector *connector)
1777{
0bb1ffe4 1778 struct drm_i915_private *dev_priv = to_i915(connector->dev);
0e891b3f 1779 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
e3bb355c 1780 int i, count = 0;
79e53945 1781
e3bb355c
VS		 1782 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) {
1783 const struct input_res *input = &input_res_table[i];
1784 struct drm_display_mode *mode;
79e53945 1785
e3bb355c
VS		 1786 if (input->w > 1024 &&
1787 !tv_mode->progressive &&
1788 !tv_mode->component_only)
79e53945
JB		 1789 continue;
1790
0bb1ffe4 1791 /* no vertical scaling with wide sources on gen3 */
93e7e61e 1792 if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
0bb1ffe4
VS		 1793 input->h > intel_tv_mode_vdisplay(tv_mode))
1794 continue;
1795
e3bb355c
VS		 1796 mode = drm_mode_create(connector->dev);
1797 if (!mode)
02c5dd98 1798 continue;
79e53945 1799
e3bb355c
VS		 1800 /*
1801 * We take the TV mode and scale it to look
1802 * like it had the expected h/vdisplay. This
1803 * provides the most information to userspace
1804 * about the actual timings of the mode. We
1805 * do ignore the margins though.
1806 */
1807 intel_tv_mode_to_mode(mode, tv_mode);
1808 if (count == 0) {
025c2e19 1809 drm_dbg_kms(&dev_priv->drm, "TV mode:\n");
e3bb355c
VS		 1810 drm_mode_debug_printmodeline(mode);
1811 }
1812 intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
1813 intel_tv_scale_mode_vert(mode, input->h, 0, 0);
1814 intel_tv_set_mode_type(mode, tv_mode);
5023520f 1815
e3bb355c 1816 drm_mode_set_name(mode);
5023520f 1817
e3bb355c 1818 drm_mode_probed_add(connector, mode);
02c5dd98 1819 count++;
79e53945
JB		 1820 }
1821
02c5dd98 1822 return count;
79e53945
JB		 1823}
1824
79e53945 1825static const struct drm_connector_funcs intel_tv_connector_funcs = {
1ebaa0b9 1826 .late_register = intel_connector_register,
c191eca1 1827 .early_unregister = intel_connector_unregister,
d4b26e4f 1828 .destroy = intel_connector_destroy,
79e53945 1829 .fill_modes = drm_helper_probe_single_connector_modes,
c6f95f27 1830 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
690157f0 1831 .atomic_duplicate_state = intel_tv_connector_duplicate_state,
79e53945
JB		 1832};
1833
0e891b3f 1834static int intel_tv_atomic_check(struct drm_connector *connector,
6f3b6278 1835 struct drm_atomic_state *state)
0e891b3f 1836{
6f3b6278 1837 struct drm_connector_state *new_state;
0e891b3f
ML		 1838 struct drm_crtc_state *new_crtc_state;
1839 struct drm_connector_state *old_state;
1840
6f3b6278 1841 new_state = drm_atomic_get_new_connector_state(state, connector);
0e891b3f
ML		 1842 if (!new_state->crtc)
1843 return 0;
1844
6f3b6278
SP		 1845 old_state = drm_atomic_get_old_connector_state(state, connector);
1846 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
0e891b3f
ML		 1847
1848 if (old_state->tv.mode != new_state->tv.mode ||
1849 old_state->tv.margins.left != new_state->tv.margins.left ||
1850 old_state->tv.margins.right != new_state->tv.margins.right ||
1851 old_state->tv.margins.top != new_state->tv.margins.top ||
1852 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
1853 /* Force a modeset. */
1854
1855 new_crtc_state->connectors_changed = true;
1856 }
1857
1858 return 0;
1859}
1860
79e53945 1861static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
6c5ed5ae 1862 .detect_ctx = intel_tv_detect,
79e53945
JB		 1863 .mode_valid = intel_tv_mode_valid,
1864 .get_modes = intel_tv_get_modes,
0e891b3f 1865 .atomic_check = intel_tv_atomic_check,
79e53945
JB		 1866};
1867
79e53945 1868static const struct drm_encoder_funcs intel_tv_enc_funcs = {
ea5b213a 1869 .destroy = intel_encoder_destroy,
79e53945
JB		 1870};
1871
79e53945 1872void
c39055b0 1873intel_tv_init(struct drm_i915_private *dev_priv)
79e53945 1874{
c39055b0 1875 struct drm_device *dev = &dev_priv->drm;
79e53945 1876 struct drm_connector *connector;
ea5b213a 1877 struct intel_tv *intel_tv;
21d40d37 1878 struct intel_encoder *intel_encoder;
0c41ee2b 1879 struct intel_connector *intel_connector;
79e53945 1880 u32 tv_dac_on, tv_dac_off, save_tv_dac;
b7c914b3 1881 const char *tv_format_names[ARRAY_SIZE(tv_modes)];
79e53945 1882 int i, initial_mode = 0;
0e891b3f 1883 struct drm_connector_state *state;
79e53945 1884
988ff27b 1885 if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
79e53945
JB		 1886 return;
1887
3bdd14d5 1888 if (!intel_bios_is_tv_present(dev_priv)) {
025c2e19 1889 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
c3561438
ZY		 1890 return;
1891 }
79e53945
JB		 1892
1893 /*
1894 * Sanity check the TV output by checking to see if the
1895 * DAC register holds a value
1896 */
988ff27b 1897 save_tv_dac = intel_de_read(dev_priv, TV_DAC);
79e53945 1898
988ff27b
JN		 1899 intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1900 tv_dac_on = intel_de_read(dev_priv, TV_DAC);
79e53945 1901
988ff27b
JN		 1902 intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1903 tv_dac_off = intel_de_read(dev_priv, TV_DAC);
79e53945 1904
988ff27b 1905 intel_de_write(dev_priv, TV_DAC, save_tv_dac);
79e53945
JB		 1906
1907 /*
1908 * If the register does not hold the state change enable
1909 * bit, (either as a 0 or a 1), assume it doesn't really
1910 * exist
1911 */
1912 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1913 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1914 return;
1915
b14c5679 1916 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
ea5b213a 1917 if (!intel_tv) {
79e53945
JB		 1918 return;
1919 }
f8aed700 1920
08d9bc92 1921 intel_connector = intel_connector_alloc();
0c41ee2b 1922 if (!intel_connector) {
ea5b213a 1923 kfree(intel_tv);
0c41ee2b
ZW		 1924 return;
1925 }
1926
ea5b213a 1927 intel_encoder = &intel_tv->base;
0c41ee2b 1928 connector = &intel_connector->base;
0e891b3f 1929 state = connector->state;
79e53945 1930
3930f18a
CW		 1931 /*
1932 * The documentation, for the older chipsets at least, recommend
8102e126
CW		 1933 * using a polling method rather than hotplug detection for TVs.
1934 * This is because in order to perform the hotplug detection, the PLLs
1935 * for the TV must be kept alive increasing power drain and starving
1936 * bandwidth from other encoders. Notably for instance, it causes
1937 * pipe underruns on Crestline when this encoder is supposedly idle.
1938 *
1939 * More recent chipsets favour HDMI rather than integrated S-Video.
1940 */
821450c6 1941 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
8102e126 1942
79e53945
JB		 1943 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1944 DRM_MODE_CONNECTOR_SVIDEO);
1945
4ef69c7a 1946 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
580d8ed5 1947 DRM_MODE_ENCODER_TVDAC, "TV");
79e53945 1948
5d2d38dd 1949 intel_encoder->compute_config = intel_tv_compute_config;
7a495cfd 1950 intel_encoder->get_config = intel_tv_get_config;
809a2a8b 1951 intel_encoder->pre_enable = intel_tv_pre_enable;
6b5756a0
DV		 1952 intel_encoder->enable = intel_enable_tv;
1953 intel_encoder->disable = intel_disable_tv;
9a8ee983
DV		 1954 intel_encoder->get_hw_state = intel_tv_get_hw_state;
1955 intel_connector->get_hw_state = intel_connector_get_hw_state;
6b5756a0 1956
df0e9248 1957 intel_connector_attach_encoder(intel_connector, intel_encoder);
03cdc1d4 1958
21d40d37 1959 intel_encoder->type = INTEL_OUTPUT_TVOUT;
79f255a0 1960 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 1961 intel_encoder->port = PORT_NONE;
34053ee1 1962 intel_encoder->pipe_mask = ~0;
bc079e8b 1963 intel_encoder->cloneable = 0;
ea5b213a 1964 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
79e53945
JB		 1965
1966 /* BIOS margin values */
0e891b3f
ML		 1967 state->tv.margins.left = 54;
1968 state->tv.margins.top = 36;
1969 state->tv.margins.right = 46;
1970 state->tv.margins.bottom = 37;
79e53945 1971
0e891b3f 1972 state->tv.mode = initial_mode;
79e53945 1973
79e53945
JB		 1974 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1975 connector->interlace_allowed = false;
1976 connector->doublescan_allowed = false;
1977
1978 /* Create TV properties then attach current values */
a0ff6779
VS		 1979 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1980 /* 1080p50/1080p60 not supported on gen3 */
93e7e61e 1981 if (DISPLAY_VER(dev_priv) == 3 &&
a0ff6779
VS		 1982 tv_modes[i].oversample == 1)
1983 break;
1984
b7c914b3 1985 tv_format_names[i] = tv_modes[i].name;
a0ff6779
VS		 1986 }
1987 drm_mode_create_tv_properties(dev, i, tv_format_names);
79e53945 1988
662595df 1989 drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property,
0e891b3f 1990 state->tv.mode);
662595df 1991 drm_object_attach_property(&connector->base,
79e53945 1992 dev->mode_config.tv_left_margin_property,
0e891b3f 1993 state->tv.margins.left);
662595df 1994 drm_object_attach_property(&connector->base,
79e53945 1995 dev->mode_config.tv_top_margin_property,
0e891b3f 1996 state->tv.margins.top);
662595df 1997 drm_object_attach_property(&connector->base,
79e53945 1998 dev->mode_config.tv_right_margin_property,
0e891b3f 1999 state->tv.margins.right);
662595df 2000 drm_object_attach_property(&connector->base,
79e53945 2001 dev->mode_config.tv_bottom_margin_property,
0e891b3f 2002 state->tv.margins.bottom);
79e53945 2003}
Linux 6.x block layer and io_uring tree(s)