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b7fa22d8 ACO |
1 | /* |
2 | * Copyright © 2014-2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
5e258fa5 | 24 | #include "bxt_dpio_phy_regs.h" |
801543b2 | 25 | #include "i915_reg.h" |
5f5ada0b VS |
26 | #include "intel_ddi.h" |
27 | #include "intel_ddi_buf_trans.h" | |
7785ae0b | 28 | #include "intel_de.h" |
2cef3595 | 29 | #include "intel_display_power_well.h" |
1d455f8d | 30 | #include "intel_display_types.h" |
1eecf31e | 31 | #include "intel_dp.h" |
b1ad4c39 | 32 | #include "intel_dpio_phy.h" |
6f1923f5 | 33 | #include "vlv_dpio_phy_regs.h" |
1eecf31e | 34 | #include "vlv_sideband.h" |
b7fa22d8 | 35 | |
f38861b8 ACO |
36 | /** |
37 | * DOC: DPIO | |
38 | * | |
39 | * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI | |
40 | * ports. DPIO is the name given to such a display PHY. These PHYs | |
41 | * don't follow the standard programming model using direct MMIO | |
42 | * registers, and instead their registers must be accessed trough IOSF | |
43 | * sideband. VLV has one such PHY for driving ports B and C, and CHV | |
44 | * adds another PHY for driving port D. Each PHY responds to specific | |
45 | * IOSF-SB port. | |
46 | * | |
47 | * Each display PHY is made up of one or two channels. Each channel | |
48 | * houses a common lane part which contains the PLL and other common | |
49 | * logic. CH0 common lane also contains the IOSF-SB logic for the | |
50 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock | |
51 | * must be running when any DPIO registers are accessed. | |
52 | * | |
53 | * In addition to having their own registers, the PHYs are also | |
54 | * controlled through some dedicated signals from the display | |
55 | * controller. These include PLL reference clock enable, PLL enable, | |
56 | * and CRI clock selection, for example. | |
57 | * | |
58 | * Eeach channel also has two splines (also called data lanes), and | |
59 | * each spline is made up of one Physical Access Coding Sub-Layer | |
60 | * (PCS) block and two TX lanes. So each channel has two PCS blocks | |
61 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS | |
62 | * data/clock pairs depending on the output type. | |
63 | * | |
64 | * Additionally the PHY also contains an AUX lane with AUX blocks | |
65 | * for each channel. This is used for DP AUX communication, but | |
66 | * this fact isn't really relevant for the driver since AUX is | |
67 | * controlled from the display controller side. No DPIO registers | |
68 | * need to be accessed during AUX communication, | |
69 | * | |
70 | * Generally on VLV/CHV the common lane corresponds to the pipe and | |
71 | * the spline (PCS/TX) corresponds to the port. | |
72 | * | |
73 | * For dual channel PHY (VLV/CHV): | |
74 | * | |
75 | * pipe A == CMN/PLL/REF CH0 | |
76 | * | |
77 | * pipe B == CMN/PLL/REF CH1 | |
78 | * | |
79 | * port B == PCS/TX CH0 | |
80 | * | |
81 | * port C == PCS/TX CH1 | |
82 | * | |
83 | * This is especially important when we cross the streams | |
84 | * ie. drive port B with pipe B, or port C with pipe A. | |
85 | * | |
86 | * For single channel PHY (CHV): | |
87 | * | |
88 | * pipe C == CMN/PLL/REF CH0 | |
89 | * | |
90 | * port D == PCS/TX CH0 | |
91 | * | |
92 | * On BXT the entire PHY channel corresponds to the port. That means | |
93 | * the PLL is also now associated with the port rather than the pipe, | |
94 | * and so the clock needs to be routed to the appropriate transcoder. | |
95 | * Port A PLL is directly connected to transcoder EDP and port B/C | |
96 | * PLLs can be routed to any transcoder A/B/C. | |
97 | * | |
98 | * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is | |
99 | * digital port D (CHV) or port A (BXT). :: | |
100 | * | |
101 | * | |
102 | * Dual channel PHY (VLV/CHV/BXT) | |
103 | * --------------------------------- | |
104 | * | CH0 | CH1 | | |
105 | * | CMN/PLL/REF | CMN/PLL/REF | | |
106 | * |---------------|---------------| Display PHY | |
107 | * | PCS01 | PCS23 | PCS01 | PCS23 | | |
108 | * |-------|-------|-------|-------| | |
109 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| | |
110 | * --------------------------------- | |
111 | * | DDI0 | DDI1 | DP/HDMI ports | |
112 | * --------------------------------- | |
113 | * | |
114 | * Single channel PHY (CHV/BXT) | |
115 | * ----------------- | |
116 | * | CH0 | | |
117 | * | CMN/PLL/REF | | |
118 | * |---------------| Display PHY | |
119 | * | PCS01 | PCS23 | | |
120 | * |-------|-------| | |
121 | * |TX0|TX1|TX2|TX3| | |
122 | * ----------------- | |
123 | * | DDI2 | DP/HDMI port | |
124 | * ----------------- | |
125 | */ | |
126 | ||
842d4166 | 127 | /** |
ba07c3ed | 128 | * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy |
842d4166 | 129 | */ |
ba07c3ed | 130 | struct bxt_dpio_phy_info { |
842d4166 ACO |
131 | /** |
132 | * @dual_channel: true if this phy has a second channel. | |
133 | */ | |
134 | bool dual_channel; | |
135 | ||
e7583f7b ACO |
136 | /** |
137 | * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. | |
138 | * Otherwise the GRC value will be copied from the phy indicated by | |
139 | * this field. | |
140 | */ | |
141 | enum dpio_phy rcomp_phy; | |
142 | ||
0a116ce8 ACO |
143 | /** |
144 | * @reset_delay: delay in us to wait before setting the common reset | |
145 | * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy. | |
146 | */ | |
147 | int reset_delay; | |
148 | ||
149 | /** | |
150 | * @pwron_mask: Mask with the appropriate bit set that would cause the | |
151 | * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON. | |
152 | */ | |
153 | u32 pwron_mask; | |
154 | ||
842d4166 ACO |
155 | /** |
156 | * @channel: struct containing per channel information. | |
157 | */ | |
158 | struct { | |
159 | /** | |
41e1bd56 | 160 | * @channel.port: which port maps to this channel. |
842d4166 ACO |
161 | */ |
162 | enum port port; | |
163 | } channel[2]; | |
164 | }; | |
165 | ||
ba07c3ed | 166 | static const struct bxt_dpio_phy_info bxt_dpio_phy_info[] = { |
842d4166 ACO |
167 | [DPIO_PHY0] = { |
168 | .dual_channel = true, | |
e7583f7b | 169 | .rcomp_phy = DPIO_PHY1, |
0a116ce8 | 170 | .pwron_mask = BIT(0), |
842d4166 ACO |
171 | |
172 | .channel = { | |
173 | [DPIO_CH0] = { .port = PORT_B }, | |
174 | [DPIO_CH1] = { .port = PORT_C }, | |
175 | } | |
176 | }, | |
177 | [DPIO_PHY1] = { | |
178 | .dual_channel = false, | |
e7583f7b | 179 | .rcomp_phy = -1, |
0a116ce8 | 180 | .pwron_mask = BIT(1), |
842d4166 ACO |
181 | |
182 | .channel = { | |
183 | [DPIO_CH0] = { .port = PORT_A }, | |
184 | } | |
185 | }, | |
186 | }; | |
187 | ||
ba07c3ed | 188 | static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = { |
0a116ce8 ACO |
189 | [DPIO_PHY0] = { |
190 | .dual_channel = false, | |
191 | .rcomp_phy = DPIO_PHY1, | |
192 | .pwron_mask = BIT(0), | |
193 | .reset_delay = 20, | |
194 | ||
195 | .channel = { | |
196 | [DPIO_CH0] = { .port = PORT_B }, | |
197 | } | |
198 | }, | |
199 | [DPIO_PHY1] = { | |
200 | .dual_channel = false, | |
201 | .rcomp_phy = -1, | |
202 | .pwron_mask = BIT(3), | |
203 | .reset_delay = 20, | |
204 | ||
205 | .channel = { | |
206 | [DPIO_CH0] = { .port = PORT_A }, | |
207 | } | |
208 | }, | |
209 | [DPIO_PHY2] = { | |
210 | .dual_channel = false, | |
211 | .rcomp_phy = DPIO_PHY1, | |
212 | .pwron_mask = BIT(1), | |
213 | .reset_delay = 20, | |
214 | ||
215 | .channel = { | |
216 | [DPIO_CH0] = { .port = PORT_C }, | |
217 | } | |
218 | }, | |
219 | }; | |
220 | ||
ba07c3ed | 221 | static const struct bxt_dpio_phy_info * |
0a116ce8 ACO |
222 | bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) |
223 | { | |
224 | if (IS_GEMINILAKE(dev_priv)) { | |
ba07c3ed VS |
225 | *count = ARRAY_SIZE(glk_dpio_phy_info); |
226 | return glk_dpio_phy_info; | |
0a116ce8 | 227 | } else { |
ba07c3ed VS |
228 | *count = ARRAY_SIZE(bxt_dpio_phy_info); |
229 | return bxt_dpio_phy_info; | |
0a116ce8 ACO |
230 | } |
231 | } | |
232 | ||
ba07c3ed | 233 | static const struct bxt_dpio_phy_info * |
0a116ce8 ACO |
234 | bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
235 | { | |
236 | int count; | |
ba07c3ed | 237 | const struct bxt_dpio_phy_info *phy_list = |
0a116ce8 ACO |
238 | bxt_get_phy_list(dev_priv, &count); |
239 | ||
240 | return &phy_list[phy]; | |
241 | } | |
242 | ||
243 | void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, | |
ed37892e ACO |
244 | enum dpio_phy *phy, enum dpio_channel *ch) |
245 | { | |
ba07c3ed | 246 | const struct bxt_dpio_phy_info *phy_info, *phys; |
0a116ce8 ACO |
247 | int i, count; |
248 | ||
249 | phys = bxt_get_phy_list(dev_priv, &count); | |
ed37892e | 250 | |
0a116ce8 ACO |
251 | for (i = 0; i < count; i++) { |
252 | phy_info = &phys[i]; | |
ed37892e ACO |
253 | |
254 | if (port == phy_info->channel[DPIO_CH0].port) { | |
255 | *phy = i; | |
256 | *ch = DPIO_CH0; | |
257 | return; | |
258 | } | |
259 | ||
260 | if (phy_info->dual_channel && | |
261 | port == phy_info->channel[DPIO_CH1].port) { | |
262 | *phy = i; | |
263 | *ch = DPIO_CH1; | |
264 | return; | |
265 | } | |
266 | } | |
267 | ||
f4224a4c PB |
268 | drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", |
269 | port_name(port)); | |
ed37892e ACO |
270 | *phy = DPIO_PHY0; |
271 | *ch = DPIO_CH0; | |
272 | } | |
273 | ||
95428406 VS |
274 | /* |
275 | * Like intel_de_rmw() but reads from a single per-lane register and | |
276 | * writes to the group register to write the same value to all the lanes. | |
277 | */ | |
ba07c3ed VS |
278 | static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915, |
279 | i915_reg_t reg_single, | |
280 | i915_reg_t reg_group, | |
281 | u32 clear, u32 set) | |
95428406 VS |
282 | { |
283 | u32 old, val; | |
284 | ||
285 | old = intel_de_read(i915, reg_single); | |
286 | val = (old & ~clear) | set; | |
287 | intel_de_write(i915, reg_group, val); | |
288 | ||
289 | return old; | |
290 | } | |
291 | ||
ba07c3ed VS |
292 | void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder, |
293 | const struct intel_crtc_state *crtc_state) | |
b6e08203 | 294 | { |
5f5ada0b | 295 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f5ada0b | 296 | const struct intel_ddi_buf_trans *trans; |
ed37892e | 297 | enum dpio_channel ch; |
5f5ada0b | 298 | enum dpio_phy phy; |
aeda5f4e | 299 | int lane, n_entries; |
5f5ada0b VS |
300 | |
301 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); | |
302 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) | |
303 | return; | |
ed37892e | 304 | |
5f5ada0b | 305 | bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); |
b6e08203 ACO |
306 | |
307 | /* | |
308 | * While we write to the group register to program all lanes at once we | |
309 | * can read only lane registers and we pick lanes 0/1 for that. | |
310 | */ | |
ba07c3ed VS |
311 | bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch), |
312 | BXT_PORT_PCS_DW10_GRP(phy, ch), | |
313 | TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0); | |
314 | ||
aeda5f4e VS |
315 | for (lane = 0; lane < crtc_state->lane_count; lane++) { |
316 | int level = intel_ddi_level(encoder, crtc_state, lane); | |
317 | ||
318 | intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane), | |
ba07c3ed VS |
319 | MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK, |
320 | MARGIN_000(trans->entries[level].bxt.margin) | | |
321 | UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale)); | |
aeda5f4e VS |
322 | } |
323 | ||
324 | for (lane = 0; lane < crtc_state->lane_count; lane++) { | |
325 | int level = intel_ddi_level(encoder, crtc_state, lane); | |
326 | u32 val; | |
ba07c3ed | 327 | |
aeda5f4e | 328 | intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane), |
ba07c3ed VS |
329 | SCALE_DCOMP_METHOD, |
330 | trans->entries[level].bxt.enable ? | |
331 | SCALE_DCOMP_METHOD : 0); | |
b6e08203 | 332 | |
aeda5f4e VS |
333 | val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane)); |
334 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) | |
335 | drm_err(&dev_priv->drm, | |
336 | "Disabled scaling while ouniqetrangenmethod was set"); | |
337 | } | |
338 | ||
339 | for (lane = 0; lane < crtc_state->lane_count; lane++) { | |
340 | int level = intel_ddi_level(encoder, crtc_state, lane); | |
b6e08203 | 341 | |
aeda5f4e VS |
342 | intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane), |
343 | DE_EMPHASIS_MASK, | |
ba07c3ed | 344 | DE_EMPHASIS(trans->entries[level].bxt.deemphasis)); |
aeda5f4e | 345 | } |
b6e08203 | 346 | |
ba07c3ed VS |
347 | bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch), |
348 | BXT_PORT_PCS_DW10_GRP(phy, ch), | |
349 | 0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); | |
b6e08203 ACO |
350 | } |
351 | ||
ba07c3ed VS |
352 | bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv, |
353 | enum dpio_phy phy) | |
47a6bc61 | 354 | { |
ba07c3ed | 355 | const struct bxt_dpio_phy_info *phy_info; |
47a6bc61 | 356 | |
0a116ce8 ACO |
357 | phy_info = bxt_get_phy_info(dev_priv, phy); |
358 | ||
ee8845a2 | 359 | if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) |
47a6bc61 ACO |
360 | return false; |
361 | ||
ee8845a2 | 362 | if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & |
47a6bc61 | 363 | (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { |
2fbfc595 WK |
364 | drm_dbg(&dev_priv->drm, |
365 | "DDI PHY %d powered, but power hasn't settled\n", phy); | |
47a6bc61 ACO |
366 | |
367 | return false; | |
368 | } | |
369 | ||
ee8845a2 | 370 | if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { |
2fbfc595 WK |
371 | drm_dbg(&dev_priv->drm, |
372 | "DDI PHY %d powered, but still in reset\n", phy); | |
47a6bc61 ACO |
373 | |
374 | return false; | |
375 | } | |
376 | ||
47a6bc61 ACO |
377 | return true; |
378 | } | |
379 | ||
380 | static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
381 | { | |
ee8845a2 | 382 | u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); |
47a6bc61 | 383 | |
8221a622 | 384 | return REG_FIELD_GET(GRC_CODE_MASK, val); |
47a6bc61 ACO |
385 | } |
386 | ||
387 | static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, | |
388 | enum dpio_phy phy) | |
389 | { | |
4cb3b44d DCS |
390 | if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy), |
391 | GRC_DONE, 10)) | |
2fbfc595 WK |
392 | drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", |
393 | phy); | |
47a6bc61 ACO |
394 | } |
395 | ||
ba07c3ed VS |
396 | static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv, |
397 | enum dpio_phy phy) | |
47a6bc61 | 398 | { |
ba07c3ed | 399 | const struct bxt_dpio_phy_info *phy_info; |
47a6bc61 ACO |
400 | u32 val; |
401 | ||
0a116ce8 ACO |
402 | phy_info = bxt_get_phy_info(dev_priv, phy); |
403 | ||
ba07c3ed | 404 | if (bxt_dpio_phy_is_enabled(dev_priv, phy)) { |
47a6bc61 | 405 | /* Still read out the GRC value for state verification */ |
e7583f7b | 406 | if (phy_info->rcomp_phy != -1) |
e2855f8e | 407 | dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy); |
47a6bc61 | 408 | |
ba07c3ed | 409 | if (bxt_dpio_phy_verify_state(dev_priv, phy)) { |
2fbfc595 WK |
410 | drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " |
411 | "won't reprogram it\n", phy); | |
47a6bc61 ACO |
412 | return; |
413 | } | |
414 | ||
2fbfc595 WK |
415 | drm_dbg(&dev_priv->drm, |
416 | "DDI PHY %d enabled with invalid state, " | |
417 | "force reprogramming it\n", phy); | |
47a6bc61 ACO |
418 | } |
419 | ||
bdfee324 | 420 | intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); |
47a6bc61 ACO |
421 | |
422 | /* | |
423 | * The PHY registers start out inaccessible and respond to reads with | |
424 | * all 1s. Eventually they become accessible as they power up, then | |
425 | * the reserved bit will give the default 0. Poll on the reserved bit | |
426 | * becoming 0 to find when the PHY is accessible. | |
1b85147b ID |
427 | * The flag should get set in 100us according to the HW team, but |
428 | * use 1ms due to occasional timeouts observed with that. | |
47a6bc61 | 429 | */ |
1a886482 JN |
430 | if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy), |
431 | PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1)) | |
2fbfc595 WK |
432 | drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", |
433 | phy); | |
47a6bc61 ACO |
434 | |
435 | /* Program PLL Rcomp code offset */ | |
8221a622 VS |
436 | intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), |
437 | IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4)); | |
47a6bc61 | 438 | |
8221a622 VS |
439 | intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), |
440 | IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4)); | |
47a6bc61 ACO |
441 | |
442 | /* Program power gating */ | |
bdfee324 AH |
443 | intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0, |
444 | OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG); | |
445 | ||
446 | if (phy_info->dual_channel) | |
447 | intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0, | |
448 | DW6_OLDO_DYN_PWR_DOWN_EN); | |
47a6bc61 | 449 | |
e7583f7b | 450 | if (phy_info->rcomp_phy != -1) { |
739f3abd | 451 | u32 grc_code; |
01a55197 RV |
452 | |
453 | bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); | |
454 | ||
47a6bc61 ACO |
455 | /* |
456 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
457 | * the corresponding calibrated value from PHY1, and disable | |
458 | * the automatic calibration on PHY0. | |
459 | */ | |
e2855f8e JN |
460 | val = bxt_get_grc(dev_priv, phy_info->rcomp_phy); |
461 | dev_priv->display.state.bxt_phy_grc = val; | |
462 | ||
8221a622 VS |
463 | grc_code = GRC_CODE_FAST(val) | |
464 | GRC_CODE_SLOW(val) | | |
465 | GRC_CODE_NOM(val); | |
ee8845a2 | 466 | intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code); |
bdfee324 AH |
467 | intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy), |
468 | 0, GRC_DIS | GRC_RDY_OVRD); | |
47a6bc61 ACO |
469 | } |
470 | ||
0a116ce8 ACO |
471 | if (phy_info->reset_delay) |
472 | udelay(phy_info->reset_delay); | |
473 | ||
bdfee324 | 474 | intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); |
47a6bc61 ACO |
475 | } |
476 | ||
ba07c3ed | 477 | void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
47a6bc61 | 478 | { |
ba07c3ed | 479 | const struct bxt_dpio_phy_info *phy_info; |
47a6bc61 | 480 | |
0a116ce8 ACO |
481 | phy_info = bxt_get_phy_info(dev_priv, phy); |
482 | ||
bdfee324 | 483 | intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0); |
47a6bc61 | 484 | |
bdfee324 | 485 | intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0); |
47a6bc61 ACO |
486 | } |
487 | ||
ba07c3ed | 488 | void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
e7583f7b | 489 | { |
ba07c3ed | 490 | const struct bxt_dpio_phy_info *phy_info = |
0a116ce8 | 491 | bxt_get_phy_info(dev_priv, phy); |
e7583f7b ACO |
492 | enum dpio_phy rcomp_phy = phy_info->rcomp_phy; |
493 | bool was_enabled; | |
494 | ||
e3e8148f | 495 | lockdep_assert_held(&dev_priv->display.power.domains.lock); |
e7583f7b | 496 | |
0e870bf8 CW |
497 | was_enabled = true; |
498 | if (rcomp_phy != -1) | |
ba07c3ed | 499 | was_enabled = bxt_dpio_phy_is_enabled(dev_priv, rcomp_phy); |
e7583f7b | 500 | |
0e870bf8 CW |
501 | /* |
502 | * We need to copy the GRC calibration value from rcomp_phy, | |
503 | * so make sure it's powered up. | |
504 | */ | |
505 | if (!was_enabled) | |
ba07c3ed | 506 | _bxt_dpio_phy_init(dev_priv, rcomp_phy); |
e7583f7b | 507 | |
ba07c3ed | 508 | _bxt_dpio_phy_init(dev_priv, phy); |
e7583f7b | 509 | |
0e870bf8 | 510 | if (!was_enabled) |
ba07c3ed | 511 | bxt_dpio_phy_uninit(dev_priv, rcomp_phy); |
e7583f7b ACO |
512 | } |
513 | ||
47a6bc61 ACO |
514 | static bool __printf(6, 7) |
515 | __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, | |
516 | i915_reg_t reg, u32 mask, u32 expected, | |
517 | const char *reg_fmt, ...) | |
518 | { | |
519 | struct va_format vaf; | |
520 | va_list args; | |
521 | u32 val; | |
522 | ||
ee8845a2 | 523 | val = intel_de_read(dev_priv, reg); |
47a6bc61 ACO |
524 | if ((val & mask) == expected) |
525 | return true; | |
526 | ||
527 | va_start(args, reg_fmt); | |
528 | vaf.fmt = reg_fmt; | |
529 | vaf.va = &args; | |
530 | ||
2fbfc595 | 531 | drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " |
47a6bc61 ACO |
532 | "current %08x, expected %08x (mask %08x)\n", |
533 | phy, &vaf, reg.reg, val, (val & ~mask) | expected, | |
534 | mask); | |
535 | ||
536 | va_end(args); | |
537 | ||
538 | return false; | |
539 | } | |
540 | ||
ba07c3ed VS |
541 | bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv, |
542 | enum dpio_phy phy) | |
47a6bc61 | 543 | { |
ba07c3ed | 544 | const struct bxt_dpio_phy_info *phy_info; |
739f3abd | 545 | u32 mask; |
47a6bc61 ACO |
546 | bool ok; |
547 | ||
0a116ce8 ACO |
548 | phy_info = bxt_get_phy_info(dev_priv, phy); |
549 | ||
47a6bc61 ACO |
550 | #define _CHK(reg, mask, exp, fmt, ...) \ |
551 | __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ | |
552 | ## __VA_ARGS__) | |
553 | ||
ba07c3ed | 554 | if (!bxt_dpio_phy_is_enabled(dev_priv, phy)) |
47a6bc61 ACO |
555 | return false; |
556 | ||
557 | ok = true; | |
558 | ||
559 | /* PLL Rcomp code offset */ | |
560 | ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), | |
8221a622 VS |
561 | IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xe4), |
562 | "BXT_PORT_CL1CM_DW9(%d)", phy); | |
47a6bc61 | 563 | ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), |
8221a622 VS |
564 | IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xe4), |
565 | "BXT_PORT_CL1CM_DW10(%d)", phy); | |
47a6bc61 ACO |
566 | |
567 | /* Power gating */ | |
568 | mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; | |
569 | ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, | |
8221a622 | 570 | "BXT_PORT_CL1CM_DW28(%d)", phy); |
47a6bc61 | 571 | |
842d4166 ACO |
572 | if (phy_info->dual_channel) |
573 | ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), | |
47a6bc61 | 574 | DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, |
842d4166 | 575 | "BXT_PORT_CL2CM_DW6(%d)", phy); |
47a6bc61 | 576 | |
e7583f7b | 577 | if (phy_info->rcomp_phy != -1) { |
e2855f8e | 578 | u32 grc_code = dev_priv->display.state.bxt_phy_grc; |
47a6bc61 | 579 | |
8221a622 VS |
580 | grc_code = GRC_CODE_FAST(grc_code) | |
581 | GRC_CODE_SLOW(grc_code) | | |
582 | GRC_CODE_NOM(grc_code); | |
47a6bc61 ACO |
583 | mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | |
584 | GRC_CODE_NOM_MASK; | |
e7583f7b | 585 | ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, |
ed37892e | 586 | "BXT_PORT_REF_DW6(%d)", phy); |
47a6bc61 ACO |
587 | |
588 | mask = GRC_DIS | GRC_RDY_OVRD; | |
e7583f7b | 589 | ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, |
8221a622 | 590 | "BXT_PORT_REF_DW8(%d)", phy); |
47a6bc61 ACO |
591 | } |
592 | ||
593 | return ok; | |
594 | #undef _CHK | |
595 | } | |
596 | ||
739f3abd | 597 | u8 |
ba07c3ed | 598 | bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) |
47a6bc61 ACO |
599 | { |
600 | switch (lane_count) { | |
601 | case 1: | |
602 | return 0; | |
603 | case 2: | |
604 | return BIT(2) | BIT(0); | |
605 | case 4: | |
606 | return BIT(3) | BIT(2) | BIT(0); | |
607 | default: | |
608 | MISSING_CASE(lane_count); | |
609 | ||
610 | return 0; | |
611 | } | |
612 | } | |
613 | ||
ba07c3ed VS |
614 | void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder, |
615 | u8 lane_lat_optim_mask) | |
47a6bc61 | 616 | { |
8f4f2797 VS |
617 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
618 | enum port port = encoder->port; | |
ed37892e ACO |
619 | enum dpio_phy phy; |
620 | enum dpio_channel ch; | |
47a6bc61 ACO |
621 | int lane; |
622 | ||
0a116ce8 | 623 | bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); |
ed37892e | 624 | |
47a6bc61 | 625 | for (lane = 0; lane < 4; lane++) { |
47a6bc61 ACO |
626 | /* |
627 | * Note that on CHV this flag is called UPAR, but has | |
628 | * the same function. | |
629 | */ | |
b575007d VS |
630 | intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), |
631 | LATENCY_OPTIM, | |
632 | lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0); | |
47a6bc61 ACO |
633 | } |
634 | } | |
635 | ||
739f3abd | 636 | u8 |
ba07c3ed | 637 | bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) |
47a6bc61 | 638 | { |
8f4f2797 VS |
639 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
640 | enum port port = encoder->port; | |
ed37892e ACO |
641 | enum dpio_phy phy; |
642 | enum dpio_channel ch; | |
47a6bc61 | 643 | int lane; |
739f3abd | 644 | u8 mask; |
47a6bc61 | 645 | |
0a116ce8 | 646 | bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); |
ed37892e | 647 | |
47a6bc61 ACO |
648 | mask = 0; |
649 | for (lane = 0; lane < 4; lane++) { | |
ee8845a2 JN |
650 | u32 val = intel_de_read(dev_priv, |
651 | BXT_PORT_TX_DW14_LN(phy, ch, lane)); | |
47a6bc61 ACO |
652 | |
653 | if (val & LATENCY_OPTIM) | |
654 | mask |= BIT(lane); | |
655 | } | |
656 | ||
657 | return mask; | |
658 | } | |
659 | ||
2461bdb3 JN |
660 | enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port) |
661 | { | |
662 | switch (dig_port->base.port) { | |
663 | default: | |
664 | MISSING_CASE(dig_port->base.port); | |
665 | fallthrough; | |
666 | case PORT_B: | |
667 | case PORT_D: | |
668 | return DPIO_CH0; | |
669 | case PORT_C: | |
670 | return DPIO_CH1; | |
671 | } | |
672 | } | |
673 | ||
674 | enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port) | |
675 | { | |
676 | switch (dig_port->base.port) { | |
677 | default: | |
678 | MISSING_CASE(dig_port->base.port); | |
679 | fallthrough; | |
680 | case PORT_B: | |
681 | case PORT_C: | |
682 | return DPIO_PHY0; | |
683 | case PORT_D: | |
684 | return DPIO_PHY1; | |
685 | } | |
686 | } | |
687 | ||
9fda18c2 JN |
688 | enum dpio_phy vlv_pipe_to_phy(enum pipe pipe) |
689 | { | |
690 | switch (pipe) { | |
691 | default: | |
692 | MISSING_CASE(pipe); | |
693 | fallthrough; | |
694 | case PIPE_A: | |
695 | case PIPE_B: | |
696 | return DPIO_PHY0; | |
697 | case PIPE_C: | |
698 | return DPIO_PHY1; | |
699 | } | |
700 | } | |
701 | ||
2461bdb3 JN |
702 | enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) |
703 | { | |
704 | switch (pipe) { | |
705 | default: | |
706 | MISSING_CASE(pipe); | |
707 | fallthrough; | |
708 | case PIPE_A: | |
709 | case PIPE_C: | |
710 | return DPIO_CH0; | |
711 | case PIPE_B: | |
712 | return DPIO_CH1; | |
713 | } | |
714 | } | |
715 | ||
b7fa22d8 | 716 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
a621860a | 717 | const struct intel_crtc_state *crtc_state, |
b7fa22d8 ACO |
718 | u32 deemph_reg_value, u32 margin_reg_value, |
719 | bool uniq_trans_scale) | |
720 | { | |
721 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
7801f3b7 | 722 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
7801f3b7 | 723 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); |
b798431c | 724 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); |
b7fa22d8 ACO |
725 | u32 val; |
726 | int i; | |
727 | ||
221c7862 | 728 | vlv_dpio_get(dev_priv); |
b7fa22d8 ACO |
729 | |
730 | /* Clear calc init */ | |
f70a68bc | 731 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); |
b7fa22d8 ACO |
732 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
733 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
734 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
f70a68bc | 735 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val); |
b7fa22d8 | 736 | |
a621860a | 737 | if (crtc_state->lane_count > 2) { |
f70a68bc | 738 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); |
b7fa22d8 ACO |
739 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); |
740 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
741 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
f70a68bc | 742 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val); |
b7fa22d8 ACO |
743 | } |
744 | ||
f70a68bc | 745 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch)); |
b7fa22d8 ACO |
746 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
747 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
f70a68bc | 748 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val); |
b7fa22d8 | 749 | |
a621860a | 750 | if (crtc_state->lane_count > 2) { |
f70a68bc | 751 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch)); |
b7fa22d8 ACO |
752 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); |
753 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
f70a68bc | 754 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val); |
b7fa22d8 ACO |
755 | } |
756 | ||
757 | /* Program swing deemph */ | |
a621860a | 758 | for (i = 0; i < crtc_state->lane_count; i++) { |
f70a68bc | 759 | val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i)); |
b7fa22d8 | 760 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
b0efc428 | 761 | val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value); |
f70a68bc | 762 | vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val); |
b7fa22d8 ACO |
763 | } |
764 | ||
765 | /* Program swing margin */ | |
a621860a | 766 | for (i = 0; i < crtc_state->lane_count; i++) { |
f70a68bc | 767 | val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i)); |
b7fa22d8 ACO |
768 | |
769 | val &= ~DPIO_SWING_MARGIN000_MASK; | |
b0efc428 | 770 | val |= DPIO_SWING_MARGIN000(margin_reg_value); |
b7fa22d8 ACO |
771 | |
772 | /* | |
773 | * Supposedly this value shouldn't matter when unique transition | |
774 | * scale is disabled, but in fact it does matter. Let's just | |
775 | * always program the same value and hope it's OK. | |
776 | */ | |
b0efc428 VS |
777 | val &= ~DPIO_UNIQ_TRANS_SCALE_MASK; |
778 | val |= DPIO_UNIQ_TRANS_SCALE(0x9a); | |
b7fa22d8 | 779 | |
f70a68bc | 780 | vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val); |
b7fa22d8 ACO |
781 | } |
782 | ||
783 | /* | |
784 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
785 | * for ch1. Might be a typo in the doc. | |
786 | * For now, for this unique transition scale selection, set bit | |
787 | * 27 for ch0 and ch1. | |
788 | */ | |
a621860a | 789 | for (i = 0; i < crtc_state->lane_count; i++) { |
f70a68bc | 790 | val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i)); |
b7fa22d8 ACO |
791 | if (uniq_trans_scale) |
792 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
793 | else | |
794 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
f70a68bc | 795 | vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val); |
b7fa22d8 ACO |
796 | } |
797 | ||
798 | /* Start swing calculation */ | |
f70a68bc | 799 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); |
b7fa22d8 | 800 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
f70a68bc | 801 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val); |
b7fa22d8 | 802 | |
a621860a | 803 | if (crtc_state->lane_count > 2) { |
f70a68bc | 804 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); |
b7fa22d8 | 805 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; |
f70a68bc | 806 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val); |
b7fa22d8 ACO |
807 | } |
808 | ||
221c7862 | 809 | vlv_dpio_put(dev_priv); |
b7fa22d8 ACO |
810 | } |
811 | ||
844b2f9a | 812 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2e1029c6 | 813 | const struct intel_crtc_state *crtc_state, |
844b2f9a ACO |
814 | bool reset) |
815 | { | |
816 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b798431c VS |
817 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
818 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); | |
819 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); | |
739f3abd | 820 | u32 val; |
844b2f9a | 821 | |
f70a68bc | 822 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch)); |
844b2f9a ACO |
823 | if (reset) |
824 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
825 | else | |
826 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
f70a68bc | 827 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val); |
844b2f9a | 828 | |
958bb452 | 829 | if (crtc_state->lane_count > 2) { |
f70a68bc | 830 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch)); |
844b2f9a ACO |
831 | if (reset) |
832 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
833 | else | |
834 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
f70a68bc | 835 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val); |
844b2f9a ACO |
836 | } |
837 | ||
f70a68bc | 838 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch)); |
844b2f9a ACO |
839 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
840 | if (reset) | |
841 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
842 | else | |
843 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
f70a68bc | 844 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val); |
844b2f9a | 845 | |
958bb452 | 846 | if (crtc_state->lane_count > 2) { |
f70a68bc | 847 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch)); |
844b2f9a ACO |
848 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
849 | if (reset) | |
850 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
851 | else | |
852 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
f70a68bc | 853 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val); |
844b2f9a ACO |
854 | } |
855 | } | |
419b1b7a | 856 | |
2e1029c6 VS |
857 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder, |
858 | const struct intel_crtc_state *crtc_state) | |
419b1b7a | 859 | { |
7801f3b7 | 860 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2e1029c6 | 861 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 862 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7801f3b7 | 863 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); |
b798431c | 864 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); |
2e1029c6 | 865 | enum pipe pipe = crtc->pipe; |
419b1b7a | 866 | unsigned int lane_mask = |
2e1029c6 | 867 | intel_dp_unused_lane_mask(crtc_state->lane_count); |
419b1b7a ACO |
868 | u32 val; |
869 | ||
870 | /* | |
871 | * Must trick the second common lane into life. | |
872 | * Otherwise we can't even access the PLL. | |
873 | */ | |
874 | if (ch == DPIO_CH0 && pipe == PIPE_B) | |
7801f3b7 | 875 | dig_port->release_cl2_override = |
419b1b7a ACO |
876 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); |
877 | ||
878 | chv_phy_powergate_lanes(encoder, true, lane_mask); | |
879 | ||
221c7862 | 880 | vlv_dpio_get(dev_priv); |
419b1b7a ACO |
881 | |
882 | /* Assert data lane reset */ | |
2e1029c6 | 883 | chv_data_lane_soft_reset(encoder, crtc_state, true); |
419b1b7a ACO |
884 | |
885 | /* program left/right clock distribution */ | |
886 | if (pipe != PIPE_B) { | |
61f73e8c | 887 | val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); |
419b1b7a ACO |
888 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
889 | if (ch == DPIO_CH0) | |
890 | val |= CHV_BUFLEFTENA1_FORCE; | |
891 | if (ch == DPIO_CH1) | |
892 | val |= CHV_BUFRIGHTENA1_FORCE; | |
61f73e8c | 893 | vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); |
419b1b7a | 894 | } else { |
61f73e8c | 895 | val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); |
419b1b7a ACO |
896 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
897 | if (ch == DPIO_CH0) | |
898 | val |= CHV_BUFLEFTENA2_FORCE; | |
899 | if (ch == DPIO_CH1) | |
900 | val |= CHV_BUFRIGHTENA2_FORCE; | |
61f73e8c | 901 | vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); |
419b1b7a ACO |
902 | } |
903 | ||
904 | /* program clock channel usage */ | |
f70a68bc | 905 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch)); |
b0efc428 VS |
906 | val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; |
907 | if (pipe == PIPE_B) | |
908 | val |= DPIO_PCS_USEDCLKCHANNEL; | |
419b1b7a | 909 | else |
b0efc428 | 910 | val &= ~DPIO_PCS_USEDCLKCHANNEL; |
f70a68bc | 911 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val); |
419b1b7a | 912 | |
2e1029c6 | 913 | if (crtc_state->lane_count > 2) { |
f70a68bc | 914 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch)); |
b0efc428 VS |
915 | val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; |
916 | if (pipe == PIPE_B) | |
917 | val |= DPIO_PCS_USEDCLKCHANNEL; | |
419b1b7a | 918 | else |
b0efc428 | 919 | val &= ~DPIO_PCS_USEDCLKCHANNEL; |
f70a68bc | 920 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val); |
419b1b7a ACO |
921 | } |
922 | ||
923 | /* | |
924 | * This a a bit weird since generally CL | |
925 | * matches the pipe, but here we need to | |
926 | * pick the CL based on the port. | |
927 | */ | |
f70a68bc | 928 | val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch)); |
b0efc428 | 929 | if (pipe == PIPE_B) |
419b1b7a | 930 | val |= CHV_CMN_USEDCLKCHANNEL; |
b0efc428 VS |
931 | else |
932 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
f70a68bc | 933 | vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val); |
419b1b7a | 934 | |
221c7862 | 935 | vlv_dpio_put(dev_priv); |
419b1b7a | 936 | } |
e7d2a717 | 937 | |
2e1029c6 VS |
938 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, |
939 | const struct intel_crtc_state *crtc_state) | |
e7d2a717 | 940 | { |
b7d02c3a | 941 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7801f3b7 | 942 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2e1029c6 | 943 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
7801f3b7 | 944 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); |
b798431c | 945 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); |
e7d2a717 ACO |
946 | int data, i, stagger; |
947 | u32 val; | |
948 | ||
221c7862 | 949 | vlv_dpio_get(dev_priv); |
e7d2a717 ACO |
950 | |
951 | /* allow hardware to manage TX FIFO reset source */ | |
f70a68bc | 952 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch)); |
e7d2a717 | 953 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
f70a68bc | 954 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val); |
e7d2a717 | 955 | |
2e1029c6 | 956 | if (crtc_state->lane_count > 2) { |
f70a68bc | 957 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch)); |
e7d2a717 | 958 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; |
f70a68bc | 959 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val); |
e7d2a717 ACO |
960 | } |
961 | ||
962 | /* Program Tx lane latency optimal setting*/ | |
2e1029c6 | 963 | for (i = 0; i < crtc_state->lane_count; i++) { |
e7d2a717 | 964 | /* Set the upar bit */ |
2e1029c6 | 965 | if (crtc_state->lane_count == 1) |
b0efc428 | 966 | data = 0; |
e7d2a717 | 967 | else |
b0efc428 VS |
968 | data = (i == 1) ? 0 : DPIO_UPAR; |
969 | vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data); | |
e7d2a717 ACO |
970 | } |
971 | ||
972 | /* Data lane stagger programming */ | |
2e1029c6 | 973 | if (crtc_state->port_clock > 270000) |
e7d2a717 | 974 | stagger = 0x18; |
2e1029c6 | 975 | else if (crtc_state->port_clock > 135000) |
e7d2a717 | 976 | stagger = 0xd; |
2e1029c6 | 977 | else if (crtc_state->port_clock > 67500) |
e7d2a717 | 978 | stagger = 0x7; |
2e1029c6 | 979 | else if (crtc_state->port_clock > 33750) |
e7d2a717 ACO |
980 | stagger = 0x4; |
981 | else | |
982 | stagger = 0x2; | |
983 | ||
f70a68bc | 984 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch)); |
e7d2a717 | 985 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
f70a68bc | 986 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val); |
e7d2a717 | 987 | |
2e1029c6 | 988 | if (crtc_state->lane_count > 2) { |
f70a68bc | 989 | val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch)); |
e7d2a717 | 990 | val |= DPIO_TX2_STAGGER_MASK(0x1f); |
f70a68bc | 991 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val); |
e7d2a717 ACO |
992 | } |
993 | ||
f70a68bc | 994 | vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch), |
e7d2a717 ACO |
995 | DPIO_LANESTAGGER_STRAP(stagger) | |
996 | DPIO_LANESTAGGER_STRAP_OVRD | | |
997 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
998 | DPIO_TX1_STAGGER_MULT(6) | | |
999 | DPIO_TX2_STAGGER_MULT(0)); | |
1000 | ||
2e1029c6 | 1001 | if (crtc_state->lane_count > 2) { |
f70a68bc | 1002 | vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch), |
e7d2a717 ACO |
1003 | DPIO_LANESTAGGER_STRAP(stagger) | |
1004 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1005 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1006 | DPIO_TX1_STAGGER_MULT(7) | | |
1007 | DPIO_TX2_STAGGER_MULT(5)); | |
1008 | } | |
1009 | ||
1010 | /* Deassert data lane reset */ | |
2e1029c6 | 1011 | chv_data_lane_soft_reset(encoder, crtc_state, false); |
e7d2a717 | 1012 | |
221c7862 | 1013 | vlv_dpio_put(dev_priv); |
e7d2a717 ACO |
1014 | } |
1015 | ||
1016 | void chv_phy_release_cl2_override(struct intel_encoder *encoder) | |
1017 | { | |
7801f3b7 | 1018 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
e7d2a717 ACO |
1019 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1020 | ||
7801f3b7 | 1021 | if (dig_port->release_cl2_override) { |
e7d2a717 | 1022 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); |
7801f3b7 | 1023 | dig_port->release_cl2_override = false; |
e7d2a717 ACO |
1024 | } |
1025 | } | |
204970b5 | 1026 | |
2e1029c6 VS |
1027 | void chv_phy_post_pll_disable(struct intel_encoder *encoder, |
1028 | const struct intel_crtc_state *old_crtc_state) | |
204970b5 ACO |
1029 | { |
1030 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b798431c | 1031 | enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); |
2225f3c6 | 1032 | enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; |
204970b5 ACO |
1033 | u32 val; |
1034 | ||
221c7862 | 1035 | vlv_dpio_get(dev_priv); |
204970b5 ACO |
1036 | |
1037 | /* disable left/right clock distribution */ | |
1038 | if (pipe != PIPE_B) { | |
61f73e8c | 1039 | val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); |
204970b5 | 1040 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); |
61f73e8c | 1041 | vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); |
204970b5 | 1042 | } else { |
61f73e8c | 1043 | val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); |
204970b5 | 1044 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); |
61f73e8c | 1045 | vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); |
204970b5 ACO |
1046 | } |
1047 | ||
221c7862 | 1048 | vlv_dpio_put(dev_priv); |
204970b5 ACO |
1049 | |
1050 | /* | |
1051 | * Leave the power down bit cleared for at least one | |
1052 | * lane so that chv_powergate_phy_ch() will power | |
1053 | * on something when the channel is otherwise unused. | |
1054 | * When the port is off and the override is removed | |
1055 | * the lanes power down anyway, so otherwise it doesn't | |
1056 | * really matter what the state of power down bits is | |
1057 | * after this. | |
1058 | */ | |
1059 | chv_phy_powergate_lanes(encoder, false, 0x0); | |
1060 | } | |
53d98725 ACO |
1061 | |
1062 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, | |
a621860a | 1063 | const struct intel_crtc_state *crtc_state, |
53d98725 ACO |
1064 | u32 demph_reg_value, u32 preemph_reg_value, |
1065 | u32 uniqtranscale_reg_value, u32 tx3_demph) | |
1066 | { | |
1067 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
7801f3b7 | 1068 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
7533c713 | 1069 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); |
b798431c | 1070 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); |
53d98725 | 1071 | |
221c7862 CW |
1072 | vlv_dpio_get(dev_priv); |
1073 | ||
263ed349 VS |
1074 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000); |
1075 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); | |
1076 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch), | |
53d98725 | 1077 | uniqtranscale_reg_value); |
263ed349 | 1078 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); |
53d98725 ACO |
1079 | |
1080 | if (tx3_demph) | |
32373aaf | 1081 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph); |
53d98725 | 1082 | |
263ed349 VS |
1083 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); |
1084 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); | |
1085 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); | |
221c7862 CW |
1086 | |
1087 | vlv_dpio_put(dev_priv); | |
53d98725 | 1088 | } |
6da2e616 | 1089 | |
2e1029c6 VS |
1090 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, |
1091 | const struct intel_crtc_state *crtc_state) | |
6da2e616 | 1092 | { |
7801f3b7 | 1093 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2e1029c6 | 1094 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
7533c713 | 1095 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); |
b798431c | 1096 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); |
6da2e616 ACO |
1097 | |
1098 | /* Program Tx lane resets to default */ | |
221c7862 CW |
1099 | vlv_dpio_get(dev_priv); |
1100 | ||
263ed349 | 1101 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), |
b0efc428 VS |
1102 | DPIO_PCS_TX_LANE2_RESET | |
1103 | DPIO_PCS_TX_LANE1_RESET); | |
263ed349 | 1104 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), |
b0efc428 VS |
1105 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1106 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1107 | DPIO_PCS_CLK_DATAWIDTH_8_10 | | |
1108 | DPIO_PCS_CLK_SOFT_RESET); | |
6da2e616 ACO |
1109 | |
1110 | /* Fix up inter-pair skew failure */ | |
263ed349 VS |
1111 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); |
1112 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500); | |
1113 | vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000); | |
221c7862 CW |
1114 | |
1115 | vlv_dpio_put(dev_priv); | |
6da2e616 | 1116 | } |
5f68c275 | 1117 | |
2e1029c6 VS |
1118 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, |
1119 | const struct intel_crtc_state *crtc_state) | |
5f68c275 | 1120 | { |
b7d02c3a | 1121 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7801f3b7 | 1122 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2e1029c6 | 1123 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 1124 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
7533c713 | 1125 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); |
b798431c | 1126 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); |
2e1029c6 | 1127 | enum pipe pipe = crtc->pipe; |
5f68c275 ACO |
1128 | u32 val; |
1129 | ||
221c7862 | 1130 | vlv_dpio_get(dev_priv); |
5f68c275 ACO |
1131 | |
1132 | /* Enable clock channels for this port */ | |
b0efc428 VS |
1133 | val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; |
1134 | if (pipe == PIPE_B) | |
1135 | val |= DPIO_PCS_USEDCLKCHANNEL; | |
1136 | val |= 0xc4; | |
263ed349 | 1137 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val); |
5f68c275 ACO |
1138 | |
1139 | /* Program lane clock */ | |
263ed349 VS |
1140 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); |
1141 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); | |
5f68c275 | 1142 | |
221c7862 | 1143 | vlv_dpio_put(dev_priv); |
5f68c275 | 1144 | } |
0f572ebe | 1145 | |
2e1029c6 VS |
1146 | void vlv_phy_reset_lanes(struct intel_encoder *encoder, |
1147 | const struct intel_crtc_state *old_crtc_state) | |
0f572ebe | 1148 | { |
7801f3b7 | 1149 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
fac5e23e | 1150 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
7533c713 | 1151 | enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); |
b798431c | 1152 | enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); |
0f572ebe | 1153 | |
221c7862 | 1154 | vlv_dpio_get(dev_priv); |
263ed349 VS |
1155 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); |
1156 | vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); | |
221c7862 | 1157 | vlv_dpio_put(dev_priv); |
0f572ebe | 1158 | } |