Commit | Line | Data |
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0e32b39c DA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * 2014 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
eca22edb | 26 | #include <drm/drm_atomic.h> |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
0e32b39c | 28 | #include <drm/drm_edid.h> |
fcd70cd3 | 29 | #include <drm/drm_probe_helper.h> |
0e32b39c | 30 | |
331c201a | 31 | #include "i915_drv.h" |
12392a74 | 32 | #include "intel_atomic.h" |
331c201a | 33 | #include "intel_audio.h" |
ec7f29ff | 34 | #include "intel_connector.h" |
7c53e628 | 35 | #include "intel_crtc.h" |
fdc24cf3 | 36 | #include "intel_ddi.h" |
7785ae0b | 37 | #include "intel_de.h" |
1d455f8d | 38 | #include "intel_display_types.h" |
27fec1f9 | 39 | #include "intel_dp.h" |
b23109c5 | 40 | #include "intel_dp_hdcp.h" |
46f2066e | 41 | #include "intel_dp_mst.h" |
b1ad4c39 | 42 | #include "intel_dpio_phy.h" |
1fa01409 | 43 | #include "intel_hdcp.h" |
b23109c5 | 44 | #include "intel_hotplug.h" |
714b1cdb | 45 | #include "skl_scaler.h" |
331c201a | 46 | |
f1477219 VS |
47 | static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, |
48 | struct intel_crtc_state *crtc_state, | |
49 | struct drm_connector_state *conn_state, | |
50 | struct link_config_limits *limits) | |
51 | { | |
2225f3c6 | 52 | struct drm_atomic_state *state = crtc_state->uapi.state; |
b7d02c3a | 53 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
f1477219 VS |
54 | struct intel_dp *intel_dp = &intel_mst->primary->dp; |
55 | struct intel_connector *connector = | |
56 | to_intel_connector(conn_state->connector); | |
ca4aae6d | 57 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
f1477219 | 58 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 59 | &crtc_state->hw.adjusted_mode; |
7c553f8b | 60 | bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N); |
f1477219 VS |
61 | int bpp, slots = -EINVAL; |
62 | ||
63 | crtc_state->lane_count = limits->max_lane_count; | |
f5b21c2e | 64 | crtc_state->port_clock = limits->max_rate; |
f1477219 VS |
65 | |
66 | for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { | |
67 | crtc_state->pipe_bpp = bpp; | |
68 | ||
69 | crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, | |
dc48529f DF |
70 | crtc_state->pipe_bpp, |
71 | false); | |
f1477219 VS |
72 | |
73 | slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, | |
743acd11 | 74 | connector->port, |
b59c27ca | 75 | crtc_state->pbn, |
c869c5f8 LP |
76 | drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, |
77 | crtc_state->port_clock, | |
b59c27ca | 78 | crtc_state->lane_count)); |
f1477219 VS |
79 | if (slots == -EDEADLK) |
80 | return slots; | |
81 | if (slots >= 0) | |
82 | break; | |
83 | } | |
84 | ||
85 | if (slots < 0) { | |
ca4aae6d JN |
86 | drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", |
87 | slots); | |
f1477219 VS |
88 | return slots; |
89 | } | |
90 | ||
91 | intel_link_compute_m_n(crtc_state->pipe_bpp, | |
92 | crtc_state->lane_count, | |
93 | adjusted_mode->crtc_clock, | |
94 | crtc_state->port_clock, | |
95 | &crtc_state->dp_m_n, | |
ed06efb8 | 96 | constant_n, crtc_state->fec_enable); |
f1477219 VS |
97 | crtc_state->dp_m_n.tu = slots; |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
420f63cb JN |
102 | static int intel_dp_mst_update_slots(struct intel_encoder *encoder, |
103 | struct intel_crtc_state *crtc_state, | |
104 | struct drm_connector_state *conn_state) | |
105 | { | |
106 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
107 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
108 | struct intel_dp *intel_dp = &intel_mst->primary->dp; | |
109 | struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; | |
110 | struct drm_dp_mst_topology_state *topology_state; | |
111 | u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? | |
112 | DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; | |
113 | ||
114 | topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr); | |
115 | if (IS_ERR(topology_state)) { | |
116 | drm_dbg_kms(&i915->drm, "slot update failed\n"); | |
117 | return PTR_ERR(topology_state); | |
118 | } | |
119 | ||
120 | drm_dp_mst_update_slots(topology_state, link_coding_cap); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
96550555 LP |
125 | static int intel_dp_mst_compute_config(struct intel_encoder *encoder, |
126 | struct intel_crtc_state *pipe_config, | |
127 | struct drm_connector_state *conn_state) | |
0e32b39c | 128 | { |
53e9bf5e | 129 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 130 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
f1477219 VS |
131 | struct intel_dp *intel_dp = &intel_mst->primary->dp; |
132 | struct intel_connector *connector = | |
133 | to_intel_connector(conn_state->connector); | |
765bdb0b VS |
134 | struct intel_digital_connector_state *intel_conn_state = |
135 | to_intel_digital_connector_state(conn_state); | |
f1477219 | 136 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 137 | &pipe_config->hw.adjusted_mode; |
f1477219 VS |
138 | struct link_config_limits limits; |
139 | int ret; | |
0e32b39c | 140 | |
e4dd27aa | 141 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
96550555 | 142 | return -EINVAL; |
e4dd27aa | 143 | |
d9facae6 | 144 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
0e32b39c | 145 | pipe_config->has_pch_encoder = false; |
765bdb0b VS |
146 | |
147 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
20c22ad3 | 148 | pipe_config->has_audio = connector->port->has_audio; |
765bdb0b VS |
149 | else |
150 | pipe_config->has_audio = | |
151 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
152 | ||
0e32b39c DA |
153 | /* |
154 | * for MST we always configure max link bw - the spec doesn't | |
155 | * seem to suggest we should do otherwise. | |
156 | */ | |
f5b21c2e JN |
157 | limits.min_rate = |
158 | limits.max_rate = intel_dp_max_link_rate(intel_dp); | |
ed4e9c1d | 159 | |
f1477219 VS |
160 | limits.min_lane_count = |
161 | limits.max_lane_count = intel_dp_max_lane_count(intel_dp); | |
0e32b39c | 162 | |
f1bce832 | 163 | limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); |
75427b2a VS |
164 | /* |
165 | * FIXME: If all the streams can't fit into the link with | |
166 | * their current pipe_bpp we should reduce pipe_bpp across | |
167 | * the board until things start to fit. Until then we | |
168 | * limit to <= 8bpc since that's what was hardcoded for all | |
169 | * MST streams previously. This hack should be removed once | |
170 | * we have the proper retry logic in place. | |
171 | */ | |
172 | limits.max_bpp = min(pipe_config->pipe_bpp, 24); | |
0e32b39c | 173 | |
f1477219 VS |
174 | intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |
175 | ||
176 | ret = intel_dp_mst_compute_link_config(encoder, pipe_config, | |
177 | conn_state, &limits); | |
178 | if (ret) | |
179 | return ret; | |
e75f4771 | 180 | |
420f63cb JN |
181 | ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state); |
182 | if (ret) | |
183 | return ret; | |
184 | ||
37aa52bf VS |
185 | pipe_config->limited_color_range = |
186 | intel_dp_limited_color_range(pipe_config, conn_state); | |
187 | ||
70bfb307 | 188 | if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) |
5161d058 VS |
189 | pipe_config->lane_lat_optim_mask = |
190 | bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); | |
191 | ||
53e9bf5e VS |
192 | intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); |
193 | ||
3a035ea4 VS |
194 | return 0; |
195 | } | |
196 | ||
197 | /* | |
198 | * Iterate over all connectors and return a mask of | |
199 | * all CPU transcoders streaming over the same DP link. | |
200 | */ | |
201 | static unsigned int | |
202 | intel_dp_mst_transcoder_mask(struct intel_atomic_state *state, | |
203 | struct intel_dp *mst_port) | |
204 | { | |
205 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
206 | const struct intel_digital_connector_state *conn_state; | |
207 | struct intel_connector *connector; | |
208 | u8 transcoders = 0; | |
209 | int i; | |
210 | ||
005e9537 | 211 | if (DISPLAY_VER(dev_priv) < 12) |
3a035ea4 VS |
212 | return 0; |
213 | ||
214 | for_each_new_intel_connector_in_state(state, connector, conn_state, i) { | |
215 | const struct intel_crtc_state *crtc_state; | |
216 | struct intel_crtc *crtc; | |
217 | ||
218 | if (connector->mst_port != mst_port || !conn_state->base.crtc) | |
219 | continue; | |
220 | ||
221 | crtc = to_intel_crtc(conn_state->base.crtc); | |
222 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); | |
223 | ||
224 | if (!crtc_state->hw.active) | |
225 | continue; | |
226 | ||
227 | transcoders |= BIT(crtc_state->cpu_transcoder); | |
228 | } | |
229 | ||
230 | return transcoders; | |
231 | } | |
232 | ||
233 | static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder, | |
234 | struct intel_crtc_state *crtc_state, | |
235 | struct drm_connector_state *conn_state) | |
236 | { | |
237 | struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); | |
238 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
239 | struct intel_dp *intel_dp = &intel_mst->primary->dp; | |
240 | ||
241 | /* lowest numbered transcoder will be designated master */ | |
242 | crtc_state->mst_master_transcoder = | |
243 | ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1; | |
6671c367 JRS |
244 | |
245 | return 0; | |
246 | } | |
247 | ||
248 | /* | |
249 | * If one of the connectors in a MST stream needs a modeset, mark all CRTCs | |
250 | * that shares the same MST stream as mode changed, | |
251 | * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do | |
252 | * a fastset when possible. | |
253 | */ | |
254 | static int | |
255 | intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector, | |
256 | struct intel_atomic_state *state) | |
257 | { | |
258 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
259 | struct drm_connector_list_iter connector_list_iter; | |
260 | struct intel_connector *connector_iter; | |
c4ae82a0 | 261 | int ret = 0; |
6671c367 | 262 | |
005e9537 | 263 | if (DISPLAY_VER(dev_priv) < 12) |
6671c367 JRS |
264 | return 0; |
265 | ||
266 | if (!intel_connector_needs_modeset(state, &connector->base)) | |
267 | return 0; | |
268 | ||
269 | drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter); | |
270 | for_each_intel_connector_iter(connector_iter, &connector_list_iter) { | |
271 | struct intel_digital_connector_state *conn_iter_state; | |
272 | struct intel_crtc_state *crtc_state; | |
273 | struct intel_crtc *crtc; | |
6671c367 JRS |
274 | |
275 | if (connector_iter->mst_port != connector->mst_port || | |
276 | connector_iter == connector) | |
277 | continue; | |
278 | ||
279 | conn_iter_state = intel_atomic_get_digital_connector_state(state, | |
280 | connector_iter); | |
281 | if (IS_ERR(conn_iter_state)) { | |
c4ae82a0 HY |
282 | ret = PTR_ERR(conn_iter_state); |
283 | break; | |
6671c367 JRS |
284 | } |
285 | ||
286 | if (!conn_iter_state->base.crtc) | |
287 | continue; | |
288 | ||
289 | crtc = to_intel_crtc(conn_iter_state->base.crtc); | |
290 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
291 | if (IS_ERR(crtc_state)) { | |
c4ae82a0 HY |
292 | ret = PTR_ERR(crtc_state); |
293 | break; | |
6671c367 JRS |
294 | } |
295 | ||
296 | ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); | |
c4ae82a0 HY |
297 | if (ret) |
298 | break; | |
6671c367 JRS |
299 | crtc_state->uapi.mode_changed = true; |
300 | } | |
301 | drm_connector_list_iter_end(&connector_list_iter); | |
302 | ||
c4ae82a0 | 303 | return ret; |
f424f55e | 304 | } |
0e32b39c | 305 | |
eceae147 LP |
306 | static int |
307 | intel_dp_mst_atomic_check(struct drm_connector *connector, | |
6671c367 | 308 | struct drm_atomic_state *_state) |
f424f55e | 309 | { |
6671c367 | 310 | struct intel_atomic_state *state = to_intel_atomic_state(_state); |
6f3b6278 | 311 | struct drm_connector_state *new_conn_state = |
6671c367 | 312 | drm_atomic_get_new_connector_state(&state->base, connector); |
eceae147 | 313 | struct drm_connector_state *old_conn_state = |
6671c367 | 314 | drm_atomic_get_old_connector_state(&state->base, connector); |
eceae147 LP |
315 | struct intel_connector *intel_connector = |
316 | to_intel_connector(connector); | |
317 | struct drm_crtc *new_crtc = new_conn_state->crtc; | |
eceae147 | 318 | struct drm_dp_mst_topology_mgr *mgr; |
37aa52bf VS |
319 | int ret; |
320 | ||
6671c367 JRS |
321 | ret = intel_digital_connector_atomic_check(connector, &state->base); |
322 | if (ret) | |
323 | return ret; | |
324 | ||
325 | ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state); | |
37aa52bf VS |
326 | if (ret) |
327 | return ret; | |
eceae147 LP |
328 | |
329 | if (!old_conn_state->crtc) | |
330 | return 0; | |
331 | ||
332 | /* We only want to free VCPI if this state disables the CRTC on this | |
333 | * connector | |
334 | */ | |
335 | if (new_crtc) { | |
f15f01a7 | 336 | struct intel_crtc *crtc = to_intel_crtc(new_crtc); |
3558cafc | 337 | struct intel_crtc_state *crtc_state = |
f15f01a7 | 338 | intel_atomic_get_new_crtc_state(state, crtc); |
eceae147 LP |
339 | |
340 | if (!crtc_state || | |
2225f3c6 | 341 | !drm_atomic_crtc_needs_modeset(&crtc_state->uapi) || |
c50bb4dd | 342 | crtc_state->uapi.enable) |
eceae147 | 343 | return 0; |
f424f55e | 344 | } |
eceae147 | 345 | |
b7d02c3a | 346 | mgr = &enc_to_mst(to_intel_encoder(old_conn_state->best_encoder))->primary->dp.mst_mgr; |
6671c367 | 347 | ret = drm_dp_atomic_release_vcpi_slots(&state->base, mgr, |
eceae147 LP |
348 | intel_connector->port); |
349 | ||
f424f55e | 350 | return ret; |
0e32b39c DA |
351 | } |
352 | ||
ef79fafe VS |
353 | static void clear_act_sent(struct intel_encoder *encoder, |
354 | const struct intel_crtc_state *crtc_state) | |
e60b8672 | 355 | { |
ef79fafe | 356 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
e60b8672 | 357 | |
ef79fafe | 358 | intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state), |
3d289d25 | 359 | DP_TP_STATUS_ACT_SENT); |
e60b8672 ID |
360 | } |
361 | ||
ef79fafe VS |
362 | static void wait_for_act_sent(struct intel_encoder *encoder, |
363 | const struct intel_crtc_state *crtc_state) | |
e60b8672 | 364 | { |
ef79fafe VS |
365 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
366 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
367 | struct intel_dp *intel_dp = &intel_mst->primary->dp; | |
e60b8672 | 368 | |
ef79fafe | 369 | if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), |
e60b8672 ID |
370 | DP_TP_STATUS_ACT_SENT, 1)) |
371 | drm_err(&i915->drm, "Timed out waiting for ACT sent\n"); | |
372 | ||
373 | drm_dp_check_act_status(&intel_dp->mst_mgr); | |
374 | } | |
375 | ||
ede9771d VS |
376 | static void intel_mst_disable_dp(struct intel_atomic_state *state, |
377 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
378 | const struct intel_crtc_state *old_crtc_state, |
379 | const struct drm_connector_state *old_conn_state) | |
0e32b39c | 380 | { |
b7d02c3a | 381 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
7801f3b7 LDM |
382 | struct intel_digital_port *dig_port = intel_mst->primary; |
383 | struct intel_dp *intel_dp = &dig_port->dp; | |
1e7bfa0b ML |
384 | struct intel_connector *connector = |
385 | to_intel_connector(old_conn_state->connector); | |
ca4aae6d | 386 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
420f63cb | 387 | int start_slot = intel_dp_is_uhbr(old_crtc_state) ? 0 : 1; |
0e32b39c DA |
388 | int ret; |
389 | ||
ca4aae6d JN |
390 | drm_dbg_kms(&i915->drm, "active links %d\n", |
391 | intel_dp->active_mst_links); | |
0e32b39c | 392 | |
1fa01409 SP |
393 | intel_hdcp_disable(intel_mst->connector); |
394 | ||
1e7bfa0b | 395 | drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port); |
0e32b39c | 396 | |
420f63cb | 397 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, start_slot); |
0e32b39c | 398 | if (ret) { |
ca4aae6d | 399 | drm_dbg_kms(&i915->drm, "failed to update payload %d\n", ret); |
0e32b39c | 400 | } |
179db7c1 JN |
401 | |
402 | intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); | |
0e32b39c DA |
403 | } |
404 | ||
ede9771d VS |
405 | static void intel_mst_post_disable_dp(struct intel_atomic_state *state, |
406 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
407 | const struct intel_crtc_state *old_crtc_state, |
408 | const struct drm_connector_state *old_conn_state) | |
0e32b39c | 409 | { |
b7d02c3a | 410 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
7801f3b7 LDM |
411 | struct intel_digital_port *dig_port = intel_mst->primary; |
412 | struct intel_dp *intel_dp = &dig_port->dp; | |
1e7bfa0b ML |
413 | struct intel_connector *connector = |
414 | to_intel_connector(old_conn_state->connector); | |
3ca8f191 JRS |
415 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
416 | bool last_mst_stream; | |
0e32b39c | 417 | |
3ca8f191 JRS |
418 | intel_dp->active_mst_links--; |
419 | last_mst_stream = intel_dp->active_mst_links == 0; | |
f4224a4c | 420 | drm_WARN_ON(&dev_priv->drm, |
005e9537 | 421 | DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && |
f4224a4c | 422 | !intel_dp_mst_is_master_trans(old_crtc_state)); |
3ca8f191 | 423 | |
773b4b54 VS |
424 | intel_crtc_vblank_off(old_crtc_state); |
425 | ||
8c66081b | 426 | intel_disable_transcoder(old_crtc_state); |
773b4b54 | 427 | |
c59053dc JRS |
428 | drm_dp_update_payload_part2(&intel_dp->mst_mgr); |
429 | ||
ef79fafe | 430 | clear_act_sent(encoder, old_crtc_state); |
90d4f99a | 431 | |
5918241f JN |
432 | intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), |
433 | TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); | |
c59053dc | 434 | |
ef79fafe | 435 | wait_for_act_sent(encoder, old_crtc_state); |
c59053dc JRS |
436 | |
437 | drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); | |
438 | ||
773b4b54 VS |
439 | intel_ddi_disable_transcoder_func(old_crtc_state); |
440 | ||
005e9537 | 441 | if (DISPLAY_VER(dev_priv) >= 9) |
f6df4d46 | 442 | skl_scaler_disable(old_crtc_state); |
773b4b54 | 443 | else |
9eae5e27 | 444 | ilk_pfit_disable(old_crtc_state); |
773b4b54 | 445 | |
c59053dc JRS |
446 | /* |
447 | * Power down mst path before disabling the port, otherwise we end | |
448 | * up getting interrupts from the sink upon detecting link loss. | |
449 | */ | |
450 | drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, | |
451 | false); | |
c980216d ID |
452 | |
453 | /* | |
454 | * BSpec 4287: disable DIP after the transcoder is disabled and before | |
455 | * the transcoder clock select is set to none. | |
456 | */ | |
457 | if (last_mst_stream) | |
7801f3b7 | 458 | intel_dp_set_infoframes(&dig_port->base, false, |
c980216d | 459 | old_crtc_state, NULL); |
3ca8f191 JRS |
460 | /* |
461 | * From TGL spec: "If multi-stream slave transcoder: Configure | |
462 | * Transcoder Clock Select to direct no clock to the transcoder" | |
463 | * | |
464 | * From older GENs spec: "Configure Transcoder Clock Select to direct | |
465 | * no clock to the transcoder" | |
466 | */ | |
005e9537 | 467 | if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) |
3ca8f191 | 468 | intel_ddi_disable_pipe_clock(old_crtc_state); |
2b5cf4ef | 469 | |
5ea2355a | 470 | |
0552f765 | 471 | intel_mst->connector = NULL; |
3ca8f191 | 472 | if (last_mst_stream) |
7801f3b7 | 473 | dig_port->base.post_disable(state, &dig_port->base, |
1939ba51 VS |
474 | old_crtc_state, NULL); |
475 | ||
ca4aae6d JN |
476 | drm_dbg_kms(&dev_priv->drm, "active links %d\n", |
477 | intel_dp->active_mst_links); | |
0e32b39c DA |
478 | } |
479 | ||
ede9771d VS |
480 | static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, |
481 | struct intel_encoder *encoder, | |
5161d058 VS |
482 | const struct intel_crtc_state *pipe_config, |
483 | const struct drm_connector_state *conn_state) | |
484 | { | |
b7d02c3a | 485 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
7801f3b7 LDM |
486 | struct intel_digital_port *dig_port = intel_mst->primary; |
487 | struct intel_dp *intel_dp = &dig_port->dp; | |
5161d058 | 488 | |
ca401e96 | 489 | if (intel_dp->active_mst_links == 0) |
7801f3b7 | 490 | dig_port->base.pre_pll_enable(state, &dig_port->base, |
5161d058 VS |
491 | pipe_config, NULL); |
492 | } | |
493 | ||
ede9771d VS |
494 | static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, |
495 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
496 | const struct intel_crtc_state *pipe_config, |
497 | const struct drm_connector_state *conn_state) | |
0e32b39c | 498 | { |
b7d02c3a | 499 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
7801f3b7 LDM |
500 | struct intel_digital_port *dig_port = intel_mst->primary; |
501 | struct intel_dp *intel_dp = &dig_port->dp; | |
1e7bfa0b | 502 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1e7bfa0b ML |
503 | struct intel_connector *connector = |
504 | to_intel_connector(conn_state->connector); | |
420f63cb | 505 | int start_slot = intel_dp_is_uhbr(pipe_config) ? 0 : 1; |
0e32b39c | 506 | int ret; |
a687b4ef | 507 | bool first_mst_stream; |
0e32b39c | 508 | |
e85376cb ML |
509 | /* MST encoders are bound to a crtc, not to a connector, |
510 | * force the mapping here for get_hw_state. | |
511 | */ | |
1e7bfa0b ML |
512 | connector->encoder = encoder; |
513 | intel_mst->connector = connector; | |
a687b4ef | 514 | first_mst_stream = intel_dp->active_mst_links == 0; |
f4224a4c | 515 | drm_WARN_ON(&dev_priv->drm, |
005e9537 | 516 | DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && |
f4224a4c | 517 | !intel_dp_mst_is_master_trans(pipe_config)); |
e85376cb | 518 | |
ca4aae6d JN |
519 | drm_dbg_kms(&dev_priv->drm, "active links %d\n", |
520 | intel_dp->active_mst_links); | |
0552f765 | 521 | |
a687b4ef | 522 | if (first_mst_stream) |
0e634efd | 523 | intel_dp_set_power(intel_dp, DP_SET_POWER_D0); |
be1c63c8 | 524 | |
5ea2355a | 525 | drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); |
be1c63c8 | 526 | |
a687b4ef | 527 | if (first_mst_stream) |
7801f3b7 | 528 | dig_port->base.pre_enable(state, &dig_port->base, |
e081c846 | 529 | pipe_config, NULL); |
0e32b39c DA |
530 | |
531 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | |
1e7bfa0b | 532 | connector->port, |
1e797f55 PD |
533 | pipe_config->pbn, |
534 | pipe_config->dp_m_n.tu); | |
65172699 | 535 | if (!ret) |
ca4aae6d | 536 | drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); |
0e32b39c | 537 | |
19e0b4ca | 538 | intel_dp->active_mst_links++; |
0e32b39c | 539 | |
420f63cb | 540 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, start_slot); |
2b5cf4ef | 541 | |
a687b4ef LDM |
542 | /* |
543 | * Before Gen 12 this is not done as part of | |
7801f3b7 | 544 | * dig_port->base.pre_enable() and should be done here. For |
a687b4ef LDM |
545 | * Gen 12+ the step in which this should be done is different for the |
546 | * first MST stream, so it's done on the DDI for the first stream and | |
547 | * here for the following ones. | |
548 | */ | |
005e9537 | 549 | if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) |
02a715c3 | 550 | intel_ddi_enable_pipe_clock(encoder, pipe_config); |
bd8c9cca GM |
551 | |
552 | intel_ddi_set_dp_msa(pipe_config, conn_state); | |
0e32b39c DA |
553 | } |
554 | ||
ede9771d VS |
555 | static void intel_mst_enable_dp(struct intel_atomic_state *state, |
556 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
557 | const struct intel_crtc_state *pipe_config, |
558 | const struct drm_connector_state *conn_state) | |
0e32b39c | 559 | { |
b7d02c3a | 560 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
7801f3b7 LDM |
561 | struct intel_digital_port *dig_port = intel_mst->primary; |
562 | struct intel_dp *intel_dp = &dig_port->dp; | |
1e7bfa0b | 563 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3c73553f | 564 | enum transcoder trans = pipe_config->cpu_transcoder; |
0e32b39c | 565 | |
27495962 JN |
566 | drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); |
567 | ||
ef79fafe | 568 | clear_act_sent(encoder, pipe_config); |
e60b8672 | 569 | |
e01163e8 JN |
570 | if (intel_dp_is_uhbr(pipe_config)) { |
571 | const struct drm_display_mode *adjusted_mode = | |
572 | &pipe_config->hw.adjusted_mode; | |
573 | u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); | |
574 | ||
575 | intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), | |
576 | TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); | |
577 | intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), | |
578 | TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); | |
579 | } | |
580 | ||
eed22a46 | 581 | intel_ddi_enable_transcoder_func(encoder, pipe_config); |
7c2fedd7 | 582 | |
3c73553f MR |
583 | intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, |
584 | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); | |
580fbdc5 | 585 | |
ca4aae6d JN |
586 | drm_dbg_kms(&dev_priv->drm, "active links %d\n", |
587 | intel_dp->active_mst_links); | |
0e32b39c | 588 | |
ef79fafe | 589 | wait_for_act_sent(encoder, pipe_config); |
0e32b39c | 590 | |
6bd31b37 | 591 | drm_dp_update_payload_part2(&intel_dp->mst_mgr); |
90c49a09 | 592 | |
3c73553f MR |
593 | if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) |
594 | intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, | |
595 | FECSTALL_DIS_DPTSTREAM_DPTTG); | |
596 | ||
8c66081b | 597 | intel_enable_transcoder(pipe_config); |
90c49a09 VS |
598 | |
599 | intel_crtc_vblank_on(pipe_config); | |
600 | ||
179db7c1 | 601 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
1fa01409 SP |
602 | |
603 | /* Enable hdcp if it's desired */ | |
604 | if (conn_state->content_protection == | |
605 | DRM_MODE_CONTENT_PROTECTION_DESIRED) | |
606 | intel_hdcp_enable(to_intel_connector(conn_state->connector), | |
fc6097d4 | 607 | pipe_config, |
1fa01409 | 608 | (u8)conn_state->hdcp_content_type); |
0e32b39c DA |
609 | } |
610 | ||
611 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, | |
612 | enum pipe *pipe) | |
613 | { | |
b7d02c3a | 614 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
0e32b39c | 615 | *pipe = intel_mst->pipe; |
0552f765 | 616 | if (intel_mst->connector) |
0e32b39c DA |
617 | return true; |
618 | return false; | |
619 | } | |
620 | ||
621 | static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, | |
5cec258b | 622 | struct intel_crtc_state *pipe_config) |
0e32b39c | 623 | { |
b7d02c3a | 624 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); |
7801f3b7 | 625 | struct intel_digital_port *dig_port = intel_mst->primary; |
53e9bf5e | 626 | |
356ce0ea | 627 | dig_port->base.get_config(&dig_port->base, pipe_config); |
0e32b39c DA |
628 | } |
629 | ||
b671d6ef ID |
630 | static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder, |
631 | struct intel_crtc_state *crtc_state) | |
632 | { | |
633 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
634 | struct intel_digital_port *dig_port = intel_mst->primary; | |
635 | ||
636 | return intel_dp_initial_fastset_check(&dig_port->base, crtc_state); | |
637 | } | |
638 | ||
0e32b39c DA |
639 | static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) |
640 | { | |
641 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
642 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
643 | struct edid *edid; | |
644 | int ret; | |
645 | ||
39b50c60 | 646 | if (drm_connector_is_unregistered(connector)) |
0552f765 | 647 | return intel_connector_update_modes(connector, NULL); |
0e32b39c | 648 | |
0552f765 | 649 | edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
650 | ret = intel_connector_update_modes(connector, edid); |
651 | kfree(edid); | |
652 | ||
653 | return ret; | |
654 | } | |
655 | ||
f972b495 LP |
656 | static int |
657 | intel_dp_mst_connector_late_register(struct drm_connector *connector) | |
658 | { | |
659 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
660 | int ret; | |
661 | ||
662 | ret = drm_dp_mst_connector_late_register(connector, | |
663 | intel_connector->port); | |
664 | if (ret < 0) | |
665 | return ret; | |
666 | ||
667 | ret = intel_connector_register(connector); | |
668 | if (ret < 0) | |
669 | drm_dp_mst_connector_early_unregister(connector, | |
670 | intel_connector->port); | |
671 | ||
672 | return ret; | |
673 | } | |
674 | ||
675 | static void | |
676 | intel_dp_mst_connector_early_unregister(struct drm_connector *connector) | |
677 | { | |
678 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
679 | ||
680 | intel_connector_unregister(connector); | |
681 | drm_dp_mst_connector_early_unregister(connector, | |
682 | intel_connector->port); | |
683 | } | |
684 | ||
0e32b39c | 685 | static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { |
0e32b39c | 686 | .fill_modes = drm_helper_probe_single_connector_modes, |
37aa52bf VS |
687 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
688 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
f972b495 LP |
689 | .late_register = intel_dp_mst_connector_late_register, |
690 | .early_unregister = intel_dp_mst_connector_early_unregister, | |
d4b26e4f | 691 | .destroy = intel_connector_destroy, |
c6f95f27 | 692 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
37aa52bf | 693 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
0e32b39c DA |
694 | }; |
695 | ||
696 | static int intel_dp_mst_get_modes(struct drm_connector *connector) | |
697 | { | |
698 | return intel_dp_mst_get_ddc_modes(connector); | |
699 | } | |
700 | ||
e398d7c1 LS |
701 | static int |
702 | intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, | |
703 | struct drm_display_mode *mode, | |
704 | struct drm_modeset_acquire_ctx *ctx, | |
705 | enum drm_mode_status *status) | |
0e32b39c | 706 | { |
74f1d789 | 707 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
22a2c8e0 DP |
708 | struct intel_connector *intel_connector = to_intel_connector(connector); |
709 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
e398d7c1 LS |
710 | struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; |
711 | struct drm_dp_mst_port *port = intel_connector->port; | |
712 | const int min_bpp = 18; | |
832d5bfd | 713 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
22a2c8e0 | 714 | int max_rate, mode_rate, max_lanes, max_link_clock; |
e398d7c1 | 715 | int ret; |
22a2c8e0 | 716 | |
e398d7c1 LS |
717 | if (drm_connector_is_unregistered(connector)) { |
718 | *status = MODE_ERROR; | |
719 | return 0; | |
720 | } | |
06bfe5b0 | 721 | |
e398d7c1 LS |
722 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
723 | *status = MODE_NO_DBLESCAN; | |
724 | return 0; | |
725 | } | |
e4dd27aa | 726 | |
22a2c8e0 | 727 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
3d65a735 | 728 | max_lanes = intel_dp_max_lane_count(intel_dp); |
22a2c8e0 DP |
729 | |
730 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
e398d7c1 | 731 | mode_rate = intel_dp_link_required(mode->clock, min_bpp); |
832d5bfd | 732 | |
e398d7c1 LS |
733 | ret = drm_modeset_lock(&mgr->base.lock, ctx); |
734 | if (ret) | |
735 | return ret; | |
0e32b39c | 736 | |
e398d7c1 LS |
737 | if (mode_rate > max_rate || mode->clock > max_dotclk || |
738 | drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) { | |
739 | *status = MODE_CLOCK_HIGH; | |
740 | return 0; | |
741 | } | |
742 | ||
743 | if (mode->clock < 10000) { | |
744 | *status = MODE_CLOCK_LOW; | |
745 | return 0; | |
746 | } | |
0e32b39c | 747 | |
e398d7c1 LS |
748 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) { |
749 | *status = MODE_H_ILLEGAL; | |
750 | return 0; | |
751 | } | |
832d5bfd | 752 | |
63dc014e | 753 | *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); |
e398d7c1 | 754 | return 0; |
0e32b39c DA |
755 | } |
756 | ||
459485ad | 757 | static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, |
eca22edb | 758 | struct drm_atomic_state *state) |
459485ad | 759 | { |
eca22edb MR |
760 | struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, |
761 | connector); | |
459485ad DV |
762 | struct intel_connector *intel_connector = to_intel_connector(connector); |
763 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
eca22edb | 764 | struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc); |
459485ad DV |
765 | |
766 | return &intel_dp->mst_encoders[crtc->pipe]->base.base; | |
767 | } | |
768 | ||
3f9b3f02 LP |
769 | static int |
770 | intel_dp_mst_detect(struct drm_connector *connector, | |
771 | struct drm_modeset_acquire_ctx *ctx, bool force) | |
772 | { | |
b81dddb9 | 773 | struct drm_i915_private *i915 = to_i915(connector->dev); |
3f9b3f02 LP |
774 | struct intel_connector *intel_connector = to_intel_connector(connector); |
775 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
776 | ||
b81dddb9 VS |
777 | if (!INTEL_DISPLAY_ENABLED(i915)) |
778 | return connector_status_disconnected; | |
779 | ||
3f9b3f02 LP |
780 | if (drm_connector_is_unregistered(connector)) |
781 | return connector_status_disconnected; | |
782 | ||
783 | return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr, | |
784 | intel_connector->port); | |
785 | } | |
786 | ||
0e32b39c DA |
787 | static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { |
788 | .get_modes = intel_dp_mst_get_modes, | |
e398d7c1 | 789 | .mode_valid_ctx = intel_dp_mst_mode_valid_ctx, |
459485ad | 790 | .atomic_best_encoder = intel_mst_atomic_best_encoder, |
f424f55e | 791 | .atomic_check = intel_dp_mst_atomic_check, |
3f9b3f02 | 792 | .detect_ctx = intel_dp_mst_detect, |
0e32b39c DA |
793 | }; |
794 | ||
795 | static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) | |
796 | { | |
b7d02c3a | 797 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder)); |
0e32b39c DA |
798 | |
799 | drm_encoder_cleanup(encoder); | |
800 | kfree(intel_mst); | |
801 | } | |
802 | ||
803 | static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { | |
804 | .destroy = intel_dp_mst_encoder_destroy, | |
805 | }; | |
806 | ||
807 | static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) | |
808 | { | |
fa7edcd2 | 809 | if (intel_attached_encoder(connector) && connector->base.state->crtc) { |
0e32b39c | 810 | enum pipe pipe; |
fa7edcd2 | 811 | if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe)) |
0e32b39c DA |
812 | return false; |
813 | return true; | |
814 | } | |
815 | return false; | |
816 | } | |
817 | ||
12e6cecd | 818 | static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) |
0e32b39c DA |
819 | { |
820 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
7801f3b7 LDM |
821 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
822 | struct drm_device *dev = dig_port->base.base.dev; | |
4d58443d | 823 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
824 | struct intel_connector *intel_connector; |
825 | struct drm_connector *connector; | |
4d58443d | 826 | enum pipe pipe; |
091a4f91 | 827 | int ret; |
0e32b39c | 828 | |
9bdbd0b9 | 829 | intel_connector = intel_connector_alloc(); |
0e32b39c DA |
830 | if (!intel_connector) |
831 | return NULL; | |
832 | ||
66a5ab10 LP |
833 | intel_connector->get_hw_state = intel_dp_mst_get_hw_state; |
834 | intel_connector->mst_port = intel_dp; | |
835 | intel_connector->port = port; | |
79a47cd3 | 836 | drm_dp_mst_get_port_malloc(port); |
66a5ab10 | 837 | |
0e32b39c | 838 | connector = &intel_connector->base; |
091a4f91 JA |
839 | ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, |
840 | DRM_MODE_CONNECTOR_DisplayPort); | |
841 | if (ret) { | |
85144df9 | 842 | drm_dp_mst_put_port_malloc(port); |
091a4f91 JA |
843 | intel_connector_free(intel_connector); |
844 | return NULL; | |
845 | } | |
846 | ||
0e32b39c DA |
847 | drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); |
848 | ||
4d58443d | 849 | for_each_pipe(dev_priv, pipe) { |
091a4f91 JA |
850 | struct drm_encoder *enc = |
851 | &intel_dp->mst_encoders[pipe]->base.base; | |
852 | ||
cde4c44d | 853 | ret = drm_connector_attach_encoder(&intel_connector->base, enc); |
091a4f91 JA |
854 | if (ret) |
855 | goto err; | |
0e32b39c | 856 | } |
0e32b39c DA |
857 | |
858 | drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); | |
6f134d7b DA |
859 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
860 | ||
97e14fbe | 861 | ret = drm_connector_set_path_property(connector, pathprop); |
091a4f91 JA |
862 | if (ret) |
863 | goto err; | |
864 | ||
765bdb0b | 865 | intel_attach_force_audio_property(connector); |
37aa52bf | 866 | intel_attach_broadcast_rgb_property(connector); |
1b9bd096 | 867 | |
9c13c8ff AG |
868 | ret = intel_dp_hdcp_init(dig_port, intel_connector); |
869 | if (ret) | |
870 | drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n", | |
871 | connector->name, connector->base.id); | |
1b9bd096 VS |
872 | /* |
873 | * Reuse the prop from the SST connector because we're | |
874 | * not allowed to create new props after device registration. | |
875 | */ | |
876 | connector->max_bpc_property = | |
877 | intel_dp->attached_connector->base.max_bpc_property; | |
878 | if (connector->max_bpc_property) | |
879 | drm_connector_attach_max_bpc_property(connector, 6, 12); | |
37aa52bf | 880 | |
d9515c5e | 881 | return connector; |
091a4f91 JA |
882 | |
883 | err: | |
884 | drm_connector_cleanup(connector); | |
885 | return NULL; | |
d9515c5e DA |
886 | } |
887 | ||
471bdd0d ID |
888 | static void |
889 | intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) | |
890 | { | |
891 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
892 | ||
893 | intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); | |
894 | } | |
895 | ||
69a0f89c | 896 | static const struct drm_dp_mst_topology_cbs mst_cbs = { |
0e32b39c | 897 | .add_connector = intel_dp_add_mst_connector, |
471bdd0d | 898 | .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, |
0e32b39c DA |
899 | }; |
900 | ||
901 | static struct intel_dp_mst_encoder * | |
7801f3b7 | 902 | intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) |
0e32b39c DA |
903 | { |
904 | struct intel_dp_mst_encoder *intel_mst; | |
905 | struct intel_encoder *intel_encoder; | |
7801f3b7 | 906 | struct drm_device *dev = dig_port->base.base.dev; |
0e32b39c DA |
907 | |
908 | intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); | |
909 | ||
910 | if (!intel_mst) | |
911 | return NULL; | |
912 | ||
913 | intel_mst->pipe = pipe; | |
914 | intel_encoder = &intel_mst->base; | |
7801f3b7 | 915 | intel_mst->primary = dig_port; |
0e32b39c DA |
916 | |
917 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, | |
580d8ed5 | 918 | DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); |
0e32b39c DA |
919 | |
920 | intel_encoder->type = INTEL_OUTPUT_DP_MST; | |
7801f3b7 LDM |
921 | intel_encoder->power_domain = dig_port->base.power_domain; |
922 | intel_encoder->port = dig_port->base.port; | |
0e32b39c | 923 | intel_encoder->cloneable = 0; |
29b27657 VS |
924 | /* |
925 | * This is wrong, but broken userspace uses the intersection | |
926 | * of possible_crtcs of all the encoders of a given connector | |
927 | * to figure out which crtcs can drive said connector. What | |
928 | * should be used instead is the union of possible_crtcs. | |
929 | * To keep such userspace functioning we must misconfigure | |
930 | * this to make sure the intersection is not empty :( | |
931 | */ | |
34053ee1 | 932 | intel_encoder->pipe_mask = ~0; |
0e32b39c DA |
933 | |
934 | intel_encoder->compute_config = intel_dp_mst_compute_config; | |
3a035ea4 | 935 | intel_encoder->compute_config_late = intel_dp_mst_compute_config_late; |
0e32b39c DA |
936 | intel_encoder->disable = intel_mst_disable_dp; |
937 | intel_encoder->post_disable = intel_mst_post_disable_dp; | |
f1c7a36b | 938 | intel_encoder->update_pipe = intel_ddi_update_pipe; |
5161d058 | 939 | intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp; |
0e32b39c DA |
940 | intel_encoder->pre_enable = intel_mst_pre_enable_dp; |
941 | intel_encoder->enable = intel_mst_enable_dp; | |
942 | intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; | |
943 | intel_encoder->get_config = intel_dp_mst_enc_get_config; | |
b671d6ef | 944 | intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check; |
0e32b39c DA |
945 | |
946 | return intel_mst; | |
947 | ||
948 | } | |
949 | ||
950 | static bool | |
7801f3b7 | 951 | intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) |
0e32b39c | 952 | { |
7801f3b7 LDM |
953 | struct intel_dp *intel_dp = &dig_port->dp; |
954 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
4d58443d | 955 | enum pipe pipe; |
0e32b39c | 956 | |
4d58443d | 957 | for_each_pipe(dev_priv, pipe) |
7801f3b7 | 958 | intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); |
0e32b39c DA |
959 | return true; |
960 | } | |
961 | ||
e15fd1be | 962 | int |
7801f3b7 | 963 | intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) |
e15fd1be | 964 | { |
7801f3b7 | 965 | return dig_port->dp.active_mst_links; |
e15fd1be JN |
966 | } |
967 | ||
0e32b39c | 968 | int |
7801f3b7 | 969 | intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) |
0e32b39c | 970 | { |
7801f3b7 LDM |
971 | struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); |
972 | struct intel_dp *intel_dp = &dig_port->dp; | |
973 | enum port port = dig_port->base.port; | |
0e32b39c | 974 | int ret; |
41283596 NC |
975 | int max_source_rate = |
976 | intel_dp->source_rates[intel_dp->num_source_rates - 1]; | |
0e32b39c | 977 | |
10d987fd LDM |
978 | if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) |
979 | return 0; | |
980 | ||
005e9537 | 981 | if (DISPLAY_VER(i915) < 12 && port == PORT_A) |
10d987fd LDM |
982 | return 0; |
983 | ||
005e9537 | 984 | if (DISPLAY_VER(i915) < 11 && port == PORT_E) |
10d987fd LDM |
985 | return 0; |
986 | ||
0e32b39c DA |
987 | intel_dp->mst_mgr.cbs = &mst_cbs; |
988 | ||
989 | /* create encoders */ | |
7801f3b7 | 990 | intel_dp_create_fake_mst_encoders(dig_port); |
10d987fd | 991 | ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, |
98025a62 | 992 | &intel_dp->aux, 16, 3, |
71b970c8 NC |
993 | dig_port->max_lanes, |
994 | max_source_rate, | |
41283596 | 995 | conn_base_id); |
a94a6d76 JN |
996 | if (ret) { |
997 | intel_dp->mst_mgr.cbs = NULL; | |
0e32b39c | 998 | return ret; |
a94a6d76 | 999 | } |
10d987fd | 1000 | |
0e32b39c DA |
1001 | return 0; |
1002 | } | |
1003 | ||
a94a6d76 JN |
1004 | bool intel_dp_mst_source_support(struct intel_dp *intel_dp) |
1005 | { | |
1006 | return intel_dp->mst_mgr.cbs; | |
1007 | } | |
1008 | ||
0e32b39c | 1009 | void |
7801f3b7 | 1010 | intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) |
0e32b39c | 1011 | { |
7801f3b7 | 1012 | struct intel_dp *intel_dp = &dig_port->dp; |
0e32b39c | 1013 | |
a94a6d76 | 1014 | if (!intel_dp_mst_source_support(intel_dp)) |
0e32b39c DA |
1015 | return; |
1016 | ||
1017 | drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); | |
1018 | /* encoders will get killed by normal cleanup */ | |
a94a6d76 JN |
1019 | |
1020 | intel_dp->mst_mgr.cbs = NULL; | |
0e32b39c | 1021 | } |
6671c367 JRS |
1022 | |
1023 | bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state) | |
1024 | { | |
1025 | return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder; | |
1026 | } | |
1027 | ||
1028 | bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state) | |
1029 | { | |
1030 | return crtc_state->mst_master_transcoder != INVALID_TRANSCODER && | |
1031 | crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder; | |
1032 | } |