[linux-block.git] / drivers / gpu / drm / i915 / display / intel_dp_hdcp.c

/* SPDX-License-Identifier: MIT */
/*
 * Copyright (C) 2020 Google, Inc.
 *
 * Authors:
 * Sean Paul <seanpaul@chromium.org>
 */

#include <drm/drm_dp_helper.h>
#include <drm/drm_dp_mst_helper.h>
#include <drm/drm_hdcp.h>
#include <drm/drm_print.h>

#include "intel_display_types.h"
#include "intel_ddi.h"
#include "intel_dp.h"
#include "intel_hdcp.h"

static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
{
	long ret;

#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
	ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
					       msecs_to_jiffies(timeout));

	if (!ret)
		DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
}

static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
				u8 *an)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	u8 aksv[DRM_HDCP_KSV_LEN] = {};
	ssize_t dpcd_ret;

	/* Output An first, that's easy */
	dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
				     an, DRM_HDCP_AN_LEN);
	if (dpcd_ret != DRM_HDCP_AN_LEN) {
		drm_dbg_kms(&i915->drm,
			    "Failed to write An over DP/AUX (%zd)\n",
			    dpcd_ret);
		return dpcd_ret >= 0 ? -EIO : dpcd_ret;
	}

	/*
	 * Since Aksv is Oh-So-Secret, we can't access it in software. So we
	 * send an empty buffer of the correct length through the DP helpers. On
	 * the other side, in the transfer hook, we'll generate a flag based on
	 * the destination address which will tickle the hardware to output the
	 * Aksv on our behalf after the header is sent.
	 */
	dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
				     aksv, DRM_HDCP_KSV_LEN);
	if (dpcd_ret != DRM_HDCP_KSV_LEN) {
		drm_dbg_kms(&i915->drm,
			    "Failed to write Aksv over DP/AUX (%zd)\n",
			    dpcd_ret);
		return dpcd_ret >= 0 ? -EIO : dpcd_ret;
	}
	return 0;
}

static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
				   u8 *bksv)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
			       DRM_HDCP_KSV_LEN);
	if (ret != DRM_HDCP_KSV_LEN) {
		drm_dbg_kms(&i915->drm,
			    "Read Bksv from DP/AUX failed (%zd)\n", ret);
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
				      u8 *bstatus)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;

	/*
	 * For some reason the HDMI and DP HDCP specs call this register
	 * definition by different names. In the HDMI spec, it's called BSTATUS,
	 * but in DP it's called BINFO.
	 */
	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
			       bstatus, DRM_HDCP_BSTATUS_LEN);
	if (ret != DRM_HDCP_BSTATUS_LEN) {
		drm_dbg_kms(&i915->drm,
			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static
int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
			     u8 *bcaps)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
			       bcaps, 1);
	if (ret != 1) {
		drm_dbg_kms(&i915->drm,
			    "Read bcaps from DP/AUX failed (%zd)\n", ret);
		return ret >= 0 ? -EIO : ret;
	}

	return 0;
}

static
int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
				   bool *repeater_present)
{
	ssize_t ret;
	u8 bcaps;

	ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
	if (ret)
		return ret;

	*repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
	return 0;
}

static
int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
				u8 *ri_prime)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
			       ri_prime, DRM_HDCP_RI_LEN);
	if (ret != DRM_HDCP_RI_LEN) {
		drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
			    ret);
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static
int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
				 bool *ksv_ready)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;
	u8 bstatus;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
			       &bstatus, 1);
	if (ret != 1) {
		drm_dbg_kms(&i915->drm,
			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
		return ret >= 0 ? -EIO : ret;
	}
	*ksv_ready = bstatus & DP_BSTATUS_READY;
	return 0;
}

static
int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
				int num_downstream, u8 *ksv_fifo)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;
	int i;

	/* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
	for (i = 0; i < num_downstream; i += 3) {
		size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
		ret = drm_dp_dpcd_read(&dig_port->dp.aux,
				       DP_AUX_HDCP_KSV_FIFO,
				       ksv_fifo + i * DRM_HDCP_KSV_LEN,
				       len);
		if (ret != len) {
			drm_dbg_kms(&i915->drm,
				    "Read ksv[%d] from DP/AUX failed (%zd)\n",
				    i, ret);
			return ret >= 0 ? -EIO : ret;
		}
	}
	return 0;
}

static
int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
				    int i, u32 *part)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;

	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
		return -EINVAL;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
			       DP_AUX_HDCP_V_PRIME(i), part,
			       DRM_HDCP_V_PRIME_PART_LEN);
	if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
		drm_dbg_kms(&i915->drm,
			    "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
		return ret >= 0 ? -EIO : ret;
	}
	return 0;
}

static
int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
				    enum transcoder cpu_transcoder,
				    bool enable)
{
	/* Not used for single stream DisplayPort setups */
	return 0;
}

static
bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
			      struct intel_connector *connector)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;
	u8 bstatus;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
			       &bstatus, 1);
	if (ret != 1) {
		drm_dbg_kms(&i915->drm,
			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
		return false;
	}

	return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
}

static
int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
			  bool *hdcp_capable)
{
	ssize_t ret;
	u8 bcaps;

	ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
	if (ret)
		return ret;

	*hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
	return 0;
}

struct hdcp2_dp_errata_stream_type {
	u8	msg_id;
	u8	stream_type;
} __packed;

struct hdcp2_dp_msg_data {
	u8 msg_id;
	u32 offset;
	bool msg_detectable;
	u32 timeout;
	u32 timeout2; /* Added for non_paired situation */
};

static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
	{ HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
	{ HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
	  false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
	{ HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
	  false, 0, 0 },
	{ HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
	  false, 0, 0 },
	{ HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
	  true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
	  HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
	{ HDCP_2_2_AKE_SEND_PAIRING_INFO,
	  DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
	  HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
	{ HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
	{ HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
	  false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
	{ HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
	  0, 0 },
	{ HDCP_2_2_REP_SEND_RECVID_LIST,
	  DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
	  HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
	{ HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
	  0, 0 },
	{ HDCP_2_2_REP_STREAM_MANAGE,
	  DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
	  0, 0 },
	{ HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
	  false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
/* local define to shovel this through the write_2_2 interface */
#define HDCP_2_2_ERRATA_DP_STREAM_TYPE	50
	{ HDCP_2_2_ERRATA_DP_STREAM_TYPE,
	  DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
	  0, 0 },
};

static int
intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
			      u8 *rx_status)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	ssize_t ret;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
			       DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
			       HDCP_2_2_DP_RXSTATUS_LEN);
	if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
		drm_dbg_kms(&i915->drm,
			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
		return ret >= 0 ? -EIO : ret;
	}

	return 0;
}

static
int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
				  u8 msg_id, bool *msg_ready)
{
	u8 rx_status;
	int ret;

	*msg_ready = false;
	ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
	if (ret < 0)
		return ret;

	switch (msg_id) {
	case HDCP_2_2_AKE_SEND_HPRIME:
		if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
			*msg_ready = true;
		break;
	case HDCP_2_2_AKE_SEND_PAIRING_INFO:
		if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
			*msg_ready = true;
		break;
	case HDCP_2_2_REP_SEND_RECVID_LIST:
		if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
			*msg_ready = true;
		break;
	default:
		DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
		return -EINVAL;
	}

	return 0;
}

static ssize_t
intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
			    const struct hdcp2_dp_msg_data *hdcp2_msg_data)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_dp *dp = &dig_port->dp;
	struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
	u8 msg_id = hdcp2_msg_data->msg_id;
	int ret, timeout;
	bool msg_ready = false;

	if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
		timeout = hdcp2_msg_data->timeout2;
	else
		timeout = hdcp2_msg_data->timeout;

	/*
	 * There is no way to detect the CERT, LPRIME and STREAM_READY
	 * availability. So Wait for timeout and read the msg.
	 */
	if (!hdcp2_msg_data->msg_detectable) {
		mdelay(timeout);
		ret = 0;
	} else {
		/*
		 * As we want to check the msg availability at timeout, Ignoring
		 * the timeout at wait for CP_IRQ.
		 */
		intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
		ret = hdcp2_detect_msg_availability(dig_port,
						    msg_id, &msg_ready);
		if (!msg_ready)
			ret = -ETIMEDOUT;
	}

	if (ret)
		drm_dbg_kms(&i915->drm,
			    "msg_id %d, ret %d, timeout(mSec): %d\n",
			    hdcp2_msg_data->msg_id, ret, timeout);

	return ret;
}

static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
		if (hdcp2_dp_msg_data[i].msg_id == msg_id)
			return &hdcp2_dp_msg_data[i];

	return NULL;
}

static
int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
			     void *buf, size_t size)
{
	struct intel_dp *dp = &dig_port->dp;
	struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
	unsigned int offset;
	u8 *byte = buf;
	ssize_t ret, bytes_to_write, len;
	const struct hdcp2_dp_msg_data *hdcp2_msg_data;

	hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
	if (!hdcp2_msg_data)
		return -EINVAL;

	offset = hdcp2_msg_data->offset;

	/* No msg_id in DP HDCP2.2 msgs */
	bytes_to_write = size - 1;
	byte++;

	hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);

	while (bytes_to_write) {
		len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
				DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;

		ret = drm_dp_dpcd_write(&dig_port->dp.aux,
					offset, (void *)byte, len);
		if (ret < 0)
			return ret;

		bytes_to_write -= ret;
		byte += ret;
		offset += ret;
	}

	return size;
}

static
ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port)
{
	u8 rx_info[HDCP_2_2_RXINFO_LEN];
	u32 dev_cnt;
	ssize_t ret;

	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
			       DP_HDCP_2_2_REG_RXINFO_OFFSET,
			       (void *)rx_info, HDCP_2_2_RXINFO_LEN);
	if (ret != HDCP_2_2_RXINFO_LEN)
		return ret >= 0 ? -EIO : ret;

	dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
		   HDCP_2_2_DEV_COUNT_LO(rx_info[1]));

	if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
		dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;

	ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
		HDCP_2_2_RECEIVER_IDS_MAX_LEN +
		(dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);

	return ret;
}

static
int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
			    u8 msg_id, void *buf, size_t size)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	unsigned int offset;
	u8 *byte = buf;
	ssize_t ret, bytes_to_recv, len;
	const struct hdcp2_dp_msg_data *hdcp2_msg_data;

	hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
	if (!hdcp2_msg_data)
		return -EINVAL;
	offset = hdcp2_msg_data->offset;

	ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
	if (ret < 0)
		return ret;

	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
		ret = get_receiver_id_list_size(dig_port);
		if (ret < 0)
			return ret;

		size = ret;
	}
	bytes_to_recv = size - 1;

	/* DP adaptation msgs has no msg_id */
	byte++;

	while (bytes_to_recv) {
		len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
		      DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;

		ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
				       (void *)byte, len);
		if (ret < 0) {
			drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
				    msg_id, ret);
			return ret;
		}

		bytes_to_recv -= ret;
		byte += ret;
		offset += ret;
	}
	byte = buf;
	*byte = msg_id;

	return size;
}

static
int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
				      bool is_repeater, u8 content_type)
{
	int ret;
	struct hdcp2_dp_errata_stream_type stream_type_msg;

	if (is_repeater)
		return 0;

	/*
	 * Errata for DP: As Stream type is used for encryption, Receiver
	 * should be communicated with stream type for the decryption of the
	 * content.
	 * Repeater will be communicated with stream type as a part of it's
	 * auth later in time.
	 */
	stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
	stream_type_msg.stream_type = content_type;

	ret =  intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
					sizeof(stream_type_msg));

	return ret < 0 ? ret : 0;

}

static
int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
{
	u8 rx_status;
	int ret;

	ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
	if (ret)
		return ret;

	if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
		ret = HDCP_REAUTH_REQUEST;
	else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
		ret = HDCP_LINK_INTEGRITY_FAILURE;
	else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
		ret = HDCP_TOPOLOGY_CHANGE;

	return ret;
}

static
int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
			   bool *capable)
{
	u8 rx_caps[3];
	int ret;

	*capable = false;
	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
			       DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
			       rx_caps, HDCP_2_2_RXCAPS_LEN);
	if (ret != HDCP_2_2_RXCAPS_LEN)
		return ret >= 0 ? -EIO : ret;

	if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
	    HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
		*capable = true;

	return 0;
}

static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
	.read_bksv = intel_dp_hdcp_read_bksv,
	.read_bstatus = intel_dp_hdcp_read_bstatus,
	.repeater_present = intel_dp_hdcp_repeater_present,
	.read_ri_prime = intel_dp_hdcp_read_ri_prime,
	.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
	.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
	.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
	.toggle_signalling = intel_dp_hdcp_toggle_signalling,
	.check_link = intel_dp_hdcp_check_link,
	.hdcp_capable = intel_dp_hdcp_capable,
	.write_2_2_msg = intel_dp_hdcp2_write_msg,
	.read_2_2_msg = intel_dp_hdcp2_read_msg,
	.config_stream_type = intel_dp_hdcp2_config_stream_type,
	.check_2_2_link = intel_dp_hdcp2_check_link,
	.hdcp_2_2_capable = intel_dp_hdcp2_capable,
	.protocol = HDCP_PROTOCOL_DP,
};

static int
intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
				    enum transcoder cpu_transcoder,
				    bool enable)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	int ret;

	if (!enable)
		usleep_range(6, 60); /* Bspec says >= 6us */

	ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
					       cpu_transcoder, enable);
	if (ret)
		drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
			      enable ? "Enable" : "Disable", ret);
	return ret;
}

static
bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
				  struct intel_connector *connector)
{
	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	struct intel_dp *intel_dp = &dig_port->dp;
	struct drm_dp_query_stream_enc_status_ack_reply reply;
	int ret;

	if (!intel_dp_hdcp_check_link(dig_port, connector))
		return false;

	ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
						  connector->port, &reply);
	if (ret) {
		drm_dbg_kms(&i915->drm,
			    "[CONNECTOR:%d:%s] failed QSES ret=%d\n",
			    connector->base.base.id, connector->base.name, ret);
		return false;
	}

	return reply.auth_completed && reply.encryption_enabled;
}

static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
	.read_bksv = intel_dp_hdcp_read_bksv,
	.read_bstatus = intel_dp_hdcp_read_bstatus,
	.repeater_present = intel_dp_hdcp_repeater_present,
	.read_ri_prime = intel_dp_hdcp_read_ri_prime,
	.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
	.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
	.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
	.toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
	.check_link = intel_dp_mst_hdcp_check_link,
	.hdcp_capable = intel_dp_hdcp_capable,

	.protocol = HDCP_PROTOCOL_DP,
};

int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
		       struct intel_connector *intel_connector)
{
	struct drm_device *dev = intel_connector->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_encoder *intel_encoder = &dig_port->base;
	enum port port = intel_encoder->port;
	struct intel_dp *intel_dp = &dig_port->dp;

	if (!is_hdcp_supported(dev_priv, port))
		return 0;

	if (intel_connector->mst_port)
		return intel_hdcp_init(intel_connector, port,
				       &intel_dp_mst_hdcp_shim);
	else if (!intel_dp_is_edp(intel_dp))
		return intel_hdcp_init(intel_connector, port,
				       &intel_dp_hdcp_shim);

	return 0;
}
Commit	Line	Data
d079b7e4 SP	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright (C) 2020 Google, Inc.
	4	*
	5	* Authors:
	6	* Sean Paul <seanpaul@chromium.org>
	7	*/
	8
	9	#include <drm/drm_dp_helper.h>
1fa01409	10	#include <drm/drm_dp_mst_helper.h>
d079b7e4 SP	11	#include <drm/drm_hdcp.h>
	12	#include <drm/drm_print.h>
	13
	14	#include "intel_display_types.h"
1fa01409	15	#include "intel_ddi.h"
d079b7e4 SP	16	#include "intel_dp.h"
	17	#include "intel_hdcp.h"
	18
	19	static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
	20	{
	21	long ret;
	22
	23	#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
	24	ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
	25	msecs_to_jiffies(timeout));
	26
	27	if (!ret)
	28	DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
	29	}
	30
	31	static
	32	int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
	33	u8 *an)
	34	{
	35	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	36	u8 aksv[DRM_HDCP_KSV_LEN] = {};
	37	ssize_t dpcd_ret;
	38
	39	/* Output An first, that's easy */
	40	dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
	41	an, DRM_HDCP_AN_LEN);
	42	if (dpcd_ret != DRM_HDCP_AN_LEN) {
	43	drm_dbg_kms(&i915->drm,
	44	"Failed to write An over DP/AUX (%zd)\n",
	45	dpcd_ret);
	46	return dpcd_ret >= 0 ? -EIO : dpcd_ret;
	47	}
	48
	49	/*
	50	* Since Aksv is Oh-So-Secret, we can't access it in software. So we
	51	* send an empty buffer of the correct length through the DP helpers. On
	52	* the other side, in the transfer hook, we'll generate a flag based on
	53	* the destination address which will tickle the hardware to output the
	54	* Aksv on our behalf after the header is sent.
	55	*/
	56	dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
	57	aksv, DRM_HDCP_KSV_LEN);
	58	if (dpcd_ret != DRM_HDCP_KSV_LEN) {
	59	drm_dbg_kms(&i915->drm,
	60	"Failed to write Aksv over DP/AUX (%zd)\n",
	61	dpcd_ret);
	62	return dpcd_ret >= 0 ? -EIO : dpcd_ret;
	63	}
	64	return 0;
	65	}
	66
	67	static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
	68	u8 *bksv)
	69	{
	70	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	71	ssize_t ret;
	72
	73	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
	74	DRM_HDCP_KSV_LEN);
	75	if (ret != DRM_HDCP_KSV_LEN) {
	76	drm_dbg_kms(&i915->drm,
	77	"Read Bksv from DP/AUX failed (%zd)\n", ret);
	78	return ret >= 0 ? -EIO : ret;
	79	}
80	return 0;
81	}
82
83	static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
84	u8 *bstatus)
85	{
86	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
87	ssize_t ret;
88
89	/*
90	* For some reason the HDMI and DP HDCP specs call this register
91	* definition by different names. In the HDMI spec, it's called BSTATUS,
92	* but in DP it's called BINFO.
93	*/
94	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
95	bstatus, DRM_HDCP_BSTATUS_LEN);
96	if (ret != DRM_HDCP_BSTATUS_LEN) {
97	drm_dbg_kms(&i915->drm,
98	"Read bstatus from DP/AUX failed (%zd)\n", ret);
99	return ret >= 0 ? -EIO : ret;
100	}
101	return 0;
102	}
103
104	static
105	int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
106	u8 *bcaps)
107	{
108	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
109	ssize_t ret;
110
111	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
112	bcaps, 1);
113	if (ret != 1) {
114	drm_dbg_kms(&i915->drm,
115	"Read bcaps from DP/AUX failed (%zd)\n", ret);
116	return ret >= 0 ? -EIO : ret;
117	}
118
119	return 0;
120	}
121
122	static
123	int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
124	bool *repeater_present)
125	{
126	ssize_t ret;
127	u8 bcaps;
128
129	ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
130	if (ret)
131	return ret;
132
133	*repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
134	return 0;
135	}
136
137	static
138	int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
139	u8 *ri_prime)
140	{
141	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
142	ssize_t ret;
143
144	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
145	ri_prime, DRM_HDCP_RI_LEN);
146	if (ret != DRM_HDCP_RI_LEN) {
147	drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
148	ret);
149	return ret >= 0 ? -EIO : ret;
150	}
151	return 0;
152	}
153
154	static
155	int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
156	bool *ksv_ready)
157	{
158	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
159	ssize_t ret;
160	u8 bstatus;
161
162	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
163	&bstatus, 1);
164	if (ret != 1) {
165	drm_dbg_kms(&i915->drm,
166	"Read bstatus from DP/AUX failed (%zd)\n", ret);
167	return ret >= 0 ? -EIO : ret;
168	}
169	*ksv_ready = bstatus & DP_BSTATUS_READY;
170	return 0;
171	}
172
173	static
174	int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
175	int num_downstream, u8 *ksv_fifo)
176	{
177	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
178	ssize_t ret;
179	int i;
180
181	/* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
182	for (i = 0; i < num_downstream; i += 3) {
183	size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
184	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
185	DP_AUX_HDCP_KSV_FIFO,
186	ksv_fifo + i * DRM_HDCP_KSV_LEN,
187	len);
188	if (ret != len) {
189	drm_dbg_kms(&i915->drm,
190	"Read ksv[%d] from DP/AUX failed (%zd)\n",
191	i, ret);
192	return ret >= 0 ? -EIO : ret;
193	}
194	}
195	return 0;
196	}
197
198	static
199	int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
200	int i, u32 *part)
201	{
202	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
203	ssize_t ret;
204
205	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
206	return -EINVAL;
207
208	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
209	DP_AUX_HDCP_V_PRIME(i), part,
210	DRM_HDCP_V_PRIME_PART_LEN);
211	if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
212	drm_dbg_kms(&i915->drm,
213	"Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
214	return ret >= 0 ? -EIO : ret;
215	}
216	return 0;
217	}
218
219	static
220	int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
221	enum transcoder cpu_transcoder,
222	bool enable)
223	{
224	/* Not used for single stream DisplayPort setups */
225	return 0;
226	}
227
228	static
038bac89 SP	229	bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
038bac89 SP	230	struct intel_connector *connector)
d079b7e4 SP	231	{
	232	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	233	ssize_t ret;
	234	u8 bstatus;
	235
	236	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
	237	&bstatus, 1);
	238	if (ret != 1) {
	239	drm_dbg_kms(&i915->drm,
	240	"Read bstatus from DP/AUX failed (%zd)\n", ret);
	241	return false;
	242	}
	243
	244	return !(bstatus & (DP_BSTATUS_LINK_FAILURE \| DP_BSTATUS_REAUTH_REQ));
	245	}
	246
	247	static
	248	int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
	249	bool *hdcp_capable)
	250	{
	251	ssize_t ret;
	252	u8 bcaps;
	253
	254	ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
	255	if (ret)
	256	return ret;
	257
	258	*hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
	259	return 0;
	260	}
	261
	262	struct hdcp2_dp_errata_stream_type {
	263	u8 msg_id;
	264	u8 stream_type;
	265	} __packed;
	266
	267	struct hdcp2_dp_msg_data {
	268	u8 msg_id;
	269	u32 offset;
	270	bool msg_detectable;
	271	u32 timeout;
	272	u32 timeout2; /* Added for non_paired situation */
	273	};
	274
	275	static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
	276	{ HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
	277	{ HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
	278	false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
	279	{ HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
	280	false, 0, 0 },
	281	{ HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
	282	false, 0, 0 },
	283	{ HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
	284	true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
	285	HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
	286	{ HDCP_2_2_AKE_SEND_PAIRING_INFO,
	287	DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
	288	HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
	289	{ HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
	290	{ HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
	291	false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
	292	{ HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
	293	0, 0 },
	294	{ HDCP_2_2_REP_SEND_RECVID_LIST,
295	DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
296	HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
297	{ HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
298	0, 0 },
299	{ HDCP_2_2_REP_STREAM_MANAGE,
300	DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
301	0, 0 },
302	{ HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
303	false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
304	/* local define to shovel this through the write_2_2 interface */
305	#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
306	{ HDCP_2_2_ERRATA_DP_STREAM_TYPE,
307	DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
308	0, 0 },
309	};
310
311	static int
312	intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
313	u8 *rx_status)
314	{
315	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
316	ssize_t ret;
317
318	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
319	DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
320	HDCP_2_2_DP_RXSTATUS_LEN);
321	if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
322	drm_dbg_kms(&i915->drm,
323	"Read bstatus from DP/AUX failed (%zd)\n", ret);
324	return ret >= 0 ? -EIO : ret;
325	}
326
327	return 0;
328	}
329
330	static
331	int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
332	u8 msg_id, bool *msg_ready)
333	{
334	u8 rx_status;
335	int ret;
336
337	*msg_ready = false;
338	ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
339	if (ret < 0)
340	return ret;
341
342	switch (msg_id) {
343	case HDCP_2_2_AKE_SEND_HPRIME:
344	if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
345	*msg_ready = true;
346	break;
347	case HDCP_2_2_AKE_SEND_PAIRING_INFO:
348	if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
349	*msg_ready = true;
350	break;
351	case HDCP_2_2_REP_SEND_RECVID_LIST:
352	if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
353	*msg_ready = true;
354	break;
355	default:
356	DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
357	return -EINVAL;
358	}
359
360	return 0;
361	}
362
363	static ssize_t
364	intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
365	const struct hdcp2_dp_msg_data *hdcp2_msg_data)
366	{
367	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
368	struct intel_dp *dp = &dig_port->dp;
369	struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
370	u8 msg_id = hdcp2_msg_data->msg_id;
371	int ret, timeout;
372	bool msg_ready = false;
373
374	if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
375	timeout = hdcp2_msg_data->timeout2;
376	else
377	timeout = hdcp2_msg_data->timeout;
378
379	/*
380	* There is no way to detect the CERT, LPRIME and STREAM_READY
381	* availability. So Wait for timeout and read the msg.
382	*/
383	if (!hdcp2_msg_data->msg_detectable) {
384	mdelay(timeout);
385	ret = 0;
386	} else {
387	/*
388	* As we want to check the msg availability at timeout, Ignoring
389	* the timeout at wait for CP_IRQ.
390	*/
391	intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
392	ret = hdcp2_detect_msg_availability(dig_port,
393	msg_id, &msg_ready);
394	if (!msg_ready)
395	ret = -ETIMEDOUT;
396	}
397
398	if (ret)
399	drm_dbg_kms(&i915->drm,
400	"msg_id %d, ret %d, timeout(mSec): %d\n",
401	hdcp2_msg_data->msg_id, ret, timeout);
402
403	return ret;
404	}
405
406	static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
407	{
408	int i;
409
410	for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
411	if (hdcp2_dp_msg_data[i].msg_id == msg_id)
412	return &hdcp2_dp_msg_data[i];
413
414	return NULL;
415	}
416
417	static
418	int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
419	void *buf, size_t size)
420	{
421	struct intel_dp *dp = &dig_port->dp;
422	struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
423	unsigned int offset;
424	u8 *byte = buf;
425	ssize_t ret, bytes_to_write, len;
426	const struct hdcp2_dp_msg_data *hdcp2_msg_data;
427
428	hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
429	if (!hdcp2_msg_data)
430	return -EINVAL;
431
432	offset = hdcp2_msg_data->offset;
433
434	/* No msg_id in DP HDCP2.2 msgs */
435	bytes_to_write = size - 1;
436	byte++;
437
438	hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
439
440	while (bytes_to_write) {
441	len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
442	DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
443
444	ret = drm_dp_dpcd_write(&dig_port->dp.aux,
445	offset, (void *)byte, len);
446	if (ret < 0)
447	return ret;
448
449	bytes_to_write -= ret;
450	byte += ret;
451	offset += ret;
452	}
453
454	return size;
455	}
456
457	static
458	ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port)
459	{
460	u8 rx_info[HDCP_2_2_RXINFO_LEN];
461	u32 dev_cnt;
462	ssize_t ret;
463
464	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
465	DP_HDCP_2_2_REG_RXINFO_OFFSET,
466	(void *)rx_info, HDCP_2_2_RXINFO_LEN);
467	if (ret != HDCP_2_2_RXINFO_LEN)
468	return ret >= 0 ? -EIO : ret;
469
470	dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 \|
471	HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
472
473	if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
474	dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
475
476	ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
477	HDCP_2_2_RECEIVER_IDS_MAX_LEN +
478	(dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
479
480	return ret;
481	}
482
483	static
484	int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
485	u8 msg_id, void *buf, size_t size)
486	{
487	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
488	unsigned int offset;
489	u8 *byte = buf;
490	ssize_t ret, bytes_to_recv, len;
491	const struct hdcp2_dp_msg_data *hdcp2_msg_data;
492
493	hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
494	if (!hdcp2_msg_data)
495	return -EINVAL;
496	offset = hdcp2_msg_data->offset;
497
498	ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
499	if (ret < 0)
500	return ret;
501
502	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
503	ret = get_receiver_id_list_size(dig_port);
504	if (ret < 0)
505	return ret;
506
507	size = ret;
508	}
509	bytes_to_recv = size - 1;
510
511	/* DP adaptation msgs has no msg_id */
512	byte++;
513
514	while (bytes_to_recv) {
515	len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
516	DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
517
518	ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
519	(void *)byte, len);
520	if (ret < 0) {
521	drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
522	msg_id, ret);
523	return ret;
524	}
525
526	bytes_to_recv -= ret;
527	byte += ret;
528	offset += ret;
529	}
530	byte = buf;
531	*byte = msg_id;
532
533	return size;
534	}
535
536	static
537	int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
538	bool is_repeater, u8 content_type)
539	{
540	int ret;
541	struct hdcp2_dp_errata_stream_type stream_type_msg;
542
543	if (is_repeater)
544	return 0;
545
546	/*
547	* Errata for DP: As Stream type is used for encryption, Receiver
548	* should be communicated with stream type for the decryption of the
549	* content.
550	* Repeater will be communicated with stream type as a part of it's
551	* auth later in time.
552	*/
553	stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
554	stream_type_msg.stream_type = content_type;
555
556	ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
557	sizeof(stream_type_msg));
558
559	return ret < 0 ? ret : 0;
560
561	}
562
563	static
564	int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
565	{
566	u8 rx_status;
567	int ret;
568
569	ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
570	if (ret)
571	return ret;
572
573	if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
574	ret = HDCP_REAUTH_REQUEST;
575	else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
576	ret = HDCP_LINK_INTEGRITY_FAILURE;
577	else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
578	ret = HDCP_TOPOLOGY_CHANGE;
579
580	return ret;
581	}
582
583	static
584	int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
585	bool *capable)
586	{
587	u8 rx_caps[3];
588	int ret;
589
590	*capable = false;
591	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
592	DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
593	rx_caps, HDCP_2_2_RXCAPS_LEN);
594	if (ret != HDCP_2_2_RXCAPS_LEN)
595	return ret >= 0 ? -EIO : ret;
596
597	if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
598	HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
599	*capable = true;
600
601	return 0;
602	}
603
604	static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
605	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
606	.read_bksv = intel_dp_hdcp_read_bksv,
607	.read_bstatus = intel_dp_hdcp_read_bstatus,
608	.repeater_present = intel_dp_hdcp_repeater_present,
609	.read_ri_prime = intel_dp_hdcp_read_ri_prime,
610	.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
611	.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
612	.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
613	.toggle_signalling = intel_dp_hdcp_toggle_signalling,
614	.check_link = intel_dp_hdcp_check_link,
615	.hdcp_capable = intel_dp_hdcp_capable,
616	.write_2_2_msg = intel_dp_hdcp2_write_msg,
617	.read_2_2_msg = intel_dp_hdcp2_read_msg,
618	.config_stream_type = intel_dp_hdcp2_config_stream_type,
619	.check_2_2_link = intel_dp_hdcp2_check_link,
620	.hdcp_2_2_capable = intel_dp_hdcp2_capable,
621	.protocol = HDCP_PROTOCOL_DP,
622	};
623
1fa01409 SP	624	static int
	625	intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
	626	enum transcoder cpu_transcoder,
	627	bool enable)
	628	{
	629	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	630	int ret;
	631
	632	if (!enable)
	633	usleep_range(6, 60); /* Bspec says >= 6us */
	634
	635	ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
	636	cpu_transcoder, enable);
	637	if (ret)
	638	drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
	639	enable ? "Enable" : "Disable", ret);
	640	return ret;
	641	}
	642
	643	static
	644	bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
	645	struct intel_connector *connector)
	646	{
	647	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	648	struct intel_dp *intel_dp = &dig_port->dp;
	649	struct drm_dp_query_stream_enc_status_ack_reply reply;
	650	int ret;
	651
	652	if (!intel_dp_hdcp_check_link(dig_port, connector))
	653	return false;
	654
	655	ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
	656	connector->port, &reply);
	657	if (ret) {
	658	drm_dbg_kms(&i915->drm,
	659	"[CONNECTOR:%d:%s] failed QSES ret=%d\n",
	660	connector->base.base.id, connector->base.name, ret);
	661	return false;
	662	}
	663
	664	return reply.auth_completed && reply.encryption_enabled;
	665	}
	666
	667	static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
	668	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
	669	.read_bksv = intel_dp_hdcp_read_bksv,
	670	.read_bstatus = intel_dp_hdcp_read_bstatus,
	671	.repeater_present = intel_dp_hdcp_repeater_present,
	672	.read_ri_prime = intel_dp_hdcp_read_ri_prime,
	673	.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
	674	.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
	675	.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
	676	.toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
	677	.check_link = intel_dp_mst_hdcp_check_link,
	678	.hdcp_capable = intel_dp_hdcp_capable,
	679
	680	.protocol = HDCP_PROTOCOL_DP,
	681	};
	682
d079b7e4 SP	683	int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
	684	struct intel_connector *intel_connector)
	685	{
	686	struct drm_device *dev = intel_connector->base.dev;
	687	struct drm_i915_private *dev_priv = to_i915(dev);
	688	struct intel_encoder *intel_encoder = &dig_port->base;
	689	enum port port = intel_encoder->port;
	690	struct intel_dp *intel_dp = &dig_port->dp;
	691
	692	if (!is_hdcp_supported(dev_priv, port))
	693	return 0;
	694
1fa01409 SP	695	if (intel_connector->mst_port)
	696	return intel_hdcp_init(intel_connector, port,
	697	&intel_dp_mst_hdcp_shim);
	698	else if (!intel_dp_is_edp(intel_dp))
bf3657da SP	699	return intel_hdcp_init(intel_connector, port,
bf3657da SP	700	&intel_dp_hdcp_shim);
d079b7e4 SP	701
	702	return 0;
	703	}