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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
2d1a8a48 | 28 | #include <linux/export.h> |
331c201a | 29 | #include <linux/i2c.h> |
01527b31 CT |
30 | #include <linux/notifier.h> |
31 | #include <linux/reboot.h> | |
331c201a JN |
32 | #include <linux/slab.h> |
33 | #include <linux/types.h> | |
56c5098f | 34 | |
611032bf | 35 | #include <asm/byteorder.h> |
331c201a | 36 | |
c6f95f27 | 37 | #include <drm/drm_atomic_helper.h> |
760285e7 | 38 | #include <drm/drm_crtc.h> |
20f24d77 | 39 | #include <drm/drm_dp_helper.h> |
760285e7 | 40 | #include <drm/drm_edid.h> |
20f24d77 | 41 | #include <drm/drm_hdcp.h> |
fcd70cd3 | 42 | #include <drm/drm_probe_helper.h> |
760285e7 | 43 | #include <drm/i915_drm.h> |
331c201a | 44 | |
2126d3e9 | 45 | #include "i915_debugfs.h" |
a4fc5ed6 | 46 | #include "i915_drv.h" |
a09d9a80 | 47 | #include "i915_trace.h" |
12392a74 | 48 | #include "intel_atomic.h" |
331c201a | 49 | #include "intel_audio.h" |
ec7f29ff | 50 | #include "intel_connector.h" |
fdc24cf3 | 51 | #include "intel_ddi.h" |
1d455f8d | 52 | #include "intel_display_types.h" |
27fec1f9 | 53 | #include "intel_dp.h" |
e075094f | 54 | #include "intel_dp_link_training.h" |
46f2066e | 55 | #include "intel_dp_mst.h" |
b1ad4c39 | 56 | #include "intel_dpio_phy.h" |
8834e365 | 57 | #include "intel_fifo_underrun.h" |
408bd917 | 58 | #include "intel_hdcp.h" |
0550691d | 59 | #include "intel_hdmi.h" |
dbeb38d9 | 60 | #include "intel_hotplug.h" |
f3e18947 | 61 | #include "intel_lspcon.h" |
42406fdc | 62 | #include "intel_lvds.h" |
44c1220a | 63 | #include "intel_panel.h" |
55367a27 | 64 | #include "intel_psr.h" |
56c5098f | 65 | #include "intel_sideband.h" |
bc85328f | 66 | #include "intel_tc.h" |
b375d0ef | 67 | #include "intel_vdsc.h" |
a4fc5ed6 | 68 | |
e8b2577c | 69 | #define DP_DPRX_ESI_LEN 14 |
a4fc5ed6 | 70 | |
d9218c8f MN |
71 | /* DP DSC throughput values used for slice count calculations KPixels/s */ |
72 | #define DP_DSC_PEAK_PIXEL_RATE 2720000 | |
73 | #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 | |
74 | #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 | |
75 | ||
ed06efb8 ML |
76 | /* DP DSC FEC Overhead factor = 1/(0.972261) */ |
77 | #define DP_DSC_FEC_OVERHEAD_FACTOR 972261 | |
d9218c8f | 78 | |
559be30c TP |
79 | /* Compliance test status bits */ |
80 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
81 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
82 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
83 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
84 | ||
9dd4ffdf | 85 | struct dp_link_dpll { |
840b32b7 | 86 | int clock; |
9dd4ffdf CML |
87 | struct dpll dpll; |
88 | }; | |
89 | ||
45101e93 | 90 | static const struct dp_link_dpll g4x_dpll[] = { |
840b32b7 | 91 | { 162000, |
9dd4ffdf | 92 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 93 | { 270000, |
9dd4ffdf CML |
94 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
95 | }; | |
96 | ||
97 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 98 | { 162000, |
9dd4ffdf | 99 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 100 | { 270000, |
9dd4ffdf CML |
101 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
102 | }; | |
103 | ||
65ce4bf5 | 104 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 105 | { 162000, |
58f6e632 | 106 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 107 | { 270000, |
65ce4bf5 CML |
108 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
109 | }; | |
110 | ||
ef9348c8 CML |
111 | /* |
112 | * CHV supports eDP 1.4 that have more link rates. | |
113 | * Below only provides the fixed rate but exclude variable rate. | |
114 | */ | |
115 | static const struct dp_link_dpll chv_dpll[] = { | |
116 | /* | |
117 | * CHV requires to program fractional division for m2. | |
118 | * m2 is stored in fixed point format using formula below | |
119 | * (m2_int << 22) | m2_fraction | |
120 | */ | |
840b32b7 | 121 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 122 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 123 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 124 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
ef9348c8 | 125 | }; |
637a9c63 | 126 | |
d9218c8f MN |
127 | /* Constants for DP DSC configurations */ |
128 | static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; | |
129 | ||
130 | /* With Single pipe configuration, HW is capable of supporting maximum | |
131 | * of 4 slices per line. | |
132 | */ | |
133 | static const u8 valid_dsc_slicecount[] = {1, 2, 4}; | |
134 | ||
cfcb0fc9 | 135 | /** |
1853a9da | 136 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
cfcb0fc9 JB |
137 | * @intel_dp: DP struct |
138 | * | |
139 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
140 | * will return true, and false otherwise. | |
141 | */ | |
1853a9da | 142 | bool intel_dp_is_edp(struct intel_dp *intel_dp) |
cfcb0fc9 | 143 | { |
da63a9f2 PZ |
144 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
145 | ||
146 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
147 | } |
148 | ||
43a6d19c | 149 | static struct intel_dp *intel_attached_dp(struct intel_connector *connector) |
df0e9248 | 150 | { |
b7d02c3a | 151 | return enc_to_intel_dp(intel_attached_encoder(connector)); |
df0e9248 CW |
152 | } |
153 | ||
adc10304 VS |
154 | static void intel_dp_link_down(struct intel_encoder *encoder, |
155 | const struct intel_crtc_state *old_crtc_state); | |
1e0560e0 | 156 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 157 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
adc10304 VS |
158 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
159 | const struct intel_crtc_state *crtc_state); | |
46bd8383 | 160 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a8c3344e | 161 | enum pipe pipe); |
f21a2198 | 162 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 163 | |
68f357cb JN |
164 | /* update sink rates from dpcd */ |
165 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) | |
166 | { | |
229675d5 | 167 | static const int dp_rates[] = { |
c71b53cc | 168 | 162000, 270000, 540000, 810000 |
229675d5 | 169 | }; |
a8a08886 | 170 | int i, max_rate; |
68f357cb | 171 | |
a8a08886 | 172 | max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); |
68f357cb | 173 | |
229675d5 JN |
174 | for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { |
175 | if (dp_rates[i] > max_rate) | |
a8a08886 | 176 | break; |
229675d5 | 177 | intel_dp->sink_rates[i] = dp_rates[i]; |
a8a08886 | 178 | } |
68f357cb | 179 | |
a8a08886 | 180 | intel_dp->num_sink_rates = i; |
68f357cb JN |
181 | } |
182 | ||
10ebb736 JN |
183 | /* Get length of rates array potentially limited by max_rate. */ |
184 | static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) | |
185 | { | |
186 | int i; | |
187 | ||
188 | /* Limit results by potentially reduced max rate */ | |
189 | for (i = 0; i < len; i++) { | |
190 | if (rates[len - i - 1] <= max_rate) | |
191 | return len - i; | |
192 | } | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /* Get length of common rates array potentially limited by max_rate. */ | |
198 | static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, | |
199 | int max_rate) | |
200 | { | |
201 | return intel_dp_rate_limit_len(intel_dp->common_rates, | |
202 | intel_dp->num_common_rates, max_rate); | |
203 | } | |
204 | ||
540b0b7f JN |
205 | /* Theoretical max between source and sink */ |
206 | static int intel_dp_max_common_rate(struct intel_dp *intel_dp) | |
a4fc5ed6 | 207 | { |
540b0b7f | 208 | return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
a4fc5ed6 KP |
209 | } |
210 | ||
540b0b7f JN |
211 | /* Theoretical max between source and sink */ |
212 | static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) | |
eeb6324d PZ |
213 | { |
214 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
540b0b7f JN |
215 | int source_max = intel_dig_port->max_lanes; |
216 | int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | |
bc85328f | 217 | int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port); |
eeb6324d | 218 | |
db7295c2 | 219 | return min3(source_max, sink_max, fia_max); |
eeb6324d PZ |
220 | } |
221 | ||
3d65a735 | 222 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
540b0b7f JN |
223 | { |
224 | return intel_dp->max_link_lane_count; | |
225 | } | |
226 | ||
22a2c8e0 | 227 | int |
c898261c | 228 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 229 | { |
fd81c44e DP |
230 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
231 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
232 | } |
233 | ||
22a2c8e0 | 234 | int |
fe27d53e DA |
235 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
236 | { | |
fd81c44e DP |
237 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
238 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
239 | * is transmitted every LS_Clk per lane, there is no need to account for | |
240 | * the channel encoding that is done in the PHY layer here. | |
241 | */ | |
242 | ||
243 | return max_link_clock * max_lanes; | |
fe27d53e DA |
244 | } |
245 | ||
70ec0645 MK |
246 | static int |
247 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
248 | { | |
249 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
250 | struct intel_encoder *encoder = &intel_dig_port->base; | |
251 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
252 | int max_dotclk = dev_priv->max_dotclk_freq; | |
253 | int ds_max_dotclk; | |
254 | ||
255 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
256 | ||
257 | if (type != DP_DS_PORT_TYPE_VGA) | |
258 | return max_dotclk; | |
259 | ||
260 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
261 | intel_dp->downstream_ports); | |
262 | ||
263 | if (ds_max_dotclk != 0) | |
264 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
265 | ||
266 | return max_dotclk; | |
267 | } | |
268 | ||
4ba285d4 | 269 | static int cnl_max_source_rate(struct intel_dp *intel_dp) |
53ddb3cd RV |
270 | { |
271 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
272 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
273 | enum port port = dig_port->base.port; | |
274 | ||
275 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
276 | ||
277 | /* Low voltage SKUs are limited to max of 5.4G */ | |
278 | if (voltage == VOLTAGE_INFO_0_85V) | |
4ba285d4 | 279 | return 540000; |
53ddb3cd RV |
280 | |
281 | /* For this SKU 8.1G is supported in all ports */ | |
282 | if (IS_CNL_WITH_PORT_F(dev_priv)) | |
4ba285d4 | 283 | return 810000; |
53ddb3cd | 284 | |
3758d968 | 285 | /* For other SKUs, max rate on ports A and D is 5.4G */ |
53ddb3cd | 286 | if (port == PORT_A || port == PORT_D) |
4ba285d4 | 287 | return 540000; |
53ddb3cd | 288 | |
4ba285d4 | 289 | return 810000; |
53ddb3cd RV |
290 | } |
291 | ||
46b527d1 MN |
292 | static int icl_max_source_rate(struct intel_dp *intel_dp) |
293 | { | |
294 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
b265a2a6 | 295 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
d8fe2ab6 | 296 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
46b527d1 | 297 | |
d8fe2ab6 | 298 | if (intel_phy_is_combo(dev_priv, phy) && |
b7143860 | 299 | !IS_ELKHARTLAKE(dev_priv) && |
b265a2a6 | 300 | !intel_dp_is_edp(intel_dp)) |
46b527d1 MN |
301 | return 540000; |
302 | ||
303 | return 810000; | |
304 | } | |
305 | ||
55cfc580 JN |
306 | static void |
307 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 | 308 | { |
229675d5 JN |
309 | /* The values must be in increasing order */ |
310 | static const int cnl_rates[] = { | |
311 | 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 | |
312 | }; | |
313 | static const int bxt_rates[] = { | |
314 | 162000, 216000, 243000, 270000, 324000, 432000, 540000 | |
315 | }; | |
316 | static const int skl_rates[] = { | |
317 | 162000, 216000, 270000, 324000, 432000, 540000 | |
318 | }; | |
319 | static const int hsw_rates[] = { | |
320 | 162000, 270000, 540000 | |
321 | }; | |
322 | static const int g4x_rates[] = { | |
323 | 162000, 270000 | |
324 | }; | |
40dba341 NM |
325 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
326 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
99b91bda JN |
327 | const struct ddi_vbt_port_info *info = |
328 | &dev_priv->vbt.ddi_port_info[dig_port->base.port]; | |
55cfc580 | 329 | const int *source_rates; |
99b91bda | 330 | int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate; |
40dba341 | 331 | |
55cfc580 JN |
332 | /* This should only be done once */ |
333 | WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); | |
334 | ||
46b527d1 | 335 | if (INTEL_GEN(dev_priv) >= 10) { |
d907b665 | 336 | source_rates = cnl_rates; |
4ba285d4 | 337 | size = ARRAY_SIZE(cnl_rates); |
cf819eff | 338 | if (IS_GEN(dev_priv, 10)) |
46b527d1 MN |
339 | max_rate = cnl_max_source_rate(intel_dp); |
340 | else | |
341 | max_rate = icl_max_source_rate(intel_dp); | |
ba1c06a5 MN |
342 | } else if (IS_GEN9_LP(dev_priv)) { |
343 | source_rates = bxt_rates; | |
344 | size = ARRAY_SIZE(bxt_rates); | |
b976dc53 | 345 | } else if (IS_GEN9_BC(dev_priv)) { |
55cfc580 | 346 | source_rates = skl_rates; |
40dba341 | 347 | size = ARRAY_SIZE(skl_rates); |
fc603ca7 JN |
348 | } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
349 | IS_BROADWELL(dev_priv)) { | |
229675d5 JN |
350 | source_rates = hsw_rates; |
351 | size = ARRAY_SIZE(hsw_rates); | |
fc603ca7 | 352 | } else { |
229675d5 JN |
353 | source_rates = g4x_rates; |
354 | size = ARRAY_SIZE(g4x_rates); | |
40dba341 NM |
355 | } |
356 | ||
99b91bda JN |
357 | if (max_rate && vbt_max_rate) |
358 | max_rate = min(max_rate, vbt_max_rate); | |
359 | else if (vbt_max_rate) | |
360 | max_rate = vbt_max_rate; | |
361 | ||
4ba285d4 JN |
362 | if (max_rate) |
363 | size = intel_dp_rate_limit_len(source_rates, size, max_rate); | |
364 | ||
55cfc580 JN |
365 | intel_dp->source_rates = source_rates; |
366 | intel_dp->num_source_rates = size; | |
40dba341 NM |
367 | } |
368 | ||
369 | static int intersect_rates(const int *source_rates, int source_len, | |
370 | const int *sink_rates, int sink_len, | |
371 | int *common_rates) | |
372 | { | |
373 | int i = 0, j = 0, k = 0; | |
374 | ||
375 | while (i < source_len && j < sink_len) { | |
376 | if (source_rates[i] == sink_rates[j]) { | |
377 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
378 | return k; | |
379 | common_rates[k] = source_rates[i]; | |
380 | ++k; | |
381 | ++i; | |
382 | ++j; | |
383 | } else if (source_rates[i] < sink_rates[j]) { | |
384 | ++i; | |
385 | } else { | |
386 | ++j; | |
387 | } | |
388 | } | |
389 | return k; | |
390 | } | |
391 | ||
8001b754 JN |
392 | /* return index of rate in rates array, or -1 if not found */ |
393 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
394 | { | |
395 | int i; | |
396 | ||
397 | for (i = 0; i < len; i++) | |
398 | if (rate == rates[i]) | |
399 | return i; | |
400 | ||
401 | return -1; | |
402 | } | |
403 | ||
975ee5fc | 404 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 405 | { |
975ee5fc | 406 | WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); |
40dba341 | 407 | |
975ee5fc JN |
408 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
409 | intel_dp->num_source_rates, | |
410 | intel_dp->sink_rates, | |
411 | intel_dp->num_sink_rates, | |
412 | intel_dp->common_rates); | |
413 | ||
414 | /* Paranoia, there should always be something in common. */ | |
415 | if (WARN_ON(intel_dp->num_common_rates == 0)) { | |
229675d5 | 416 | intel_dp->common_rates[0] = 162000; |
975ee5fc JN |
417 | intel_dp->num_common_rates = 1; |
418 | } | |
419 | } | |
420 | ||
1a92c70e | 421 | static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
830de422 | 422 | u8 lane_count) |
14c562c0 MN |
423 | { |
424 | /* | |
425 | * FIXME: we need to synchronize the current link parameters with | |
426 | * hardware readout. Currently fast link training doesn't work on | |
427 | * boot-up. | |
428 | */ | |
1a92c70e MN |
429 | if (link_rate == 0 || |
430 | link_rate > intel_dp->max_link_rate) | |
14c562c0 MN |
431 | return false; |
432 | ||
1a92c70e MN |
433 | if (lane_count == 0 || |
434 | lane_count > intel_dp_max_lane_count(intel_dp)) | |
14c562c0 MN |
435 | return false; |
436 | ||
437 | return true; | |
438 | } | |
439 | ||
1e712535 MN |
440 | static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, |
441 | int link_rate, | |
830de422 | 442 | u8 lane_count) |
1e712535 MN |
443 | { |
444 | const struct drm_display_mode *fixed_mode = | |
445 | intel_dp->attached_connector->panel.fixed_mode; | |
446 | int mode_rate, max_rate; | |
447 | ||
448 | mode_rate = intel_dp_link_required(fixed_mode->clock, 18); | |
449 | max_rate = intel_dp_max_data_rate(link_rate, lane_count); | |
450 | if (mode_rate > max_rate) | |
451 | return false; | |
452 | ||
453 | return true; | |
454 | } | |
455 | ||
fdb14d33 | 456 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
830de422 | 457 | int link_rate, u8 lane_count) |
fdb14d33 | 458 | { |
b1810a74 | 459 | int index; |
fdb14d33 | 460 | |
b1810a74 JN |
461 | index = intel_dp_rate_index(intel_dp->common_rates, |
462 | intel_dp->num_common_rates, | |
463 | link_rate); | |
464 | if (index > 0) { | |
1e712535 MN |
465 | if (intel_dp_is_edp(intel_dp) && |
466 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
467 | intel_dp->common_rates[index - 1], | |
468 | lane_count)) { | |
469 | DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); | |
470 | return 0; | |
471 | } | |
e6c0c64a JN |
472 | intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
473 | intel_dp->max_link_lane_count = lane_count; | |
fdb14d33 | 474 | } else if (lane_count > 1) { |
1e712535 MN |
475 | if (intel_dp_is_edp(intel_dp) && |
476 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
477 | intel_dp_max_common_rate(intel_dp), | |
478 | lane_count >> 1)) { | |
479 | DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); | |
480 | return 0; | |
481 | } | |
540b0b7f | 482 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
e6c0c64a | 483 | intel_dp->max_link_lane_count = lane_count >> 1; |
fdb14d33 MN |
484 | } else { |
485 | DRM_ERROR("Link Training Unsuccessful\n"); | |
486 | return -1; | |
487 | } | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
ed06efb8 ML |
492 | u32 intel_dp_mode_to_fec_clock(u32 mode_clock) |
493 | { | |
494 | return div_u64(mul_u32_u32(mode_clock, 1000000U), | |
495 | DP_DSC_FEC_OVERHEAD_FACTOR); | |
496 | } | |
497 | ||
45d3c5cd MR |
498 | static int |
499 | small_joiner_ram_size_bits(struct drm_i915_private *i915) | |
500 | { | |
501 | if (INTEL_GEN(i915) >= 11) | |
502 | return 7680 * 8; | |
503 | else | |
504 | return 6144 * 8; | |
505 | } | |
506 | ||
507 | static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, | |
508 | u32 link_clock, u32 lane_count, | |
ed06efb8 ML |
509 | u32 mode_clock, u32 mode_hdisplay) |
510 | { | |
511 | u32 bits_per_pixel, max_bpp_small_joiner_ram; | |
512 | int i; | |
513 | ||
514 | /* | |
515 | * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* | |
516 | * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) | |
517 | * for SST -> TimeSlotsPerMTP is 1, | |
518 | * for MST -> TimeSlotsPerMTP has to be calculated | |
519 | */ | |
520 | bits_per_pixel = (link_clock * lane_count * 8) / | |
521 | intel_dp_mode_to_fec_clock(mode_clock); | |
522 | DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel); | |
523 | ||
524 | /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ | |
45d3c5cd MR |
525 | max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / |
526 | mode_hdisplay; | |
ed06efb8 ML |
527 | DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram); |
528 | ||
529 | /* | |
530 | * Greatest allowed DSC BPP = MIN (output BPP from available Link BW | |
531 | * check, output bpp from small joiner RAM check) | |
532 | */ | |
533 | bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); | |
534 | ||
535 | /* Error out if the max bpp is less than smallest allowed valid bpp */ | |
536 | if (bits_per_pixel < valid_dsc_bpp[0]) { | |
537 | DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n", | |
538 | bits_per_pixel, valid_dsc_bpp[0]); | |
539 | return 0; | |
540 | } | |
541 | ||
542 | /* Find the nearest match in the array of known BPPs from VESA */ | |
543 | for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { | |
544 | if (bits_per_pixel < valid_dsc_bpp[i + 1]) | |
545 | break; | |
546 | } | |
547 | bits_per_pixel = valid_dsc_bpp[i]; | |
548 | ||
549 | /* | |
550 | * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, | |
551 | * fractional part is 0 | |
552 | */ | |
553 | return bits_per_pixel << 4; | |
554 | } | |
555 | ||
556 | static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, | |
557 | int mode_clock, int mode_hdisplay) | |
558 | { | |
559 | u8 min_slice_count, i; | |
560 | int max_slice_width; | |
561 | ||
562 | if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) | |
563 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
564 | DP_DSC_MAX_ENC_THROUGHPUT_0); | |
565 | else | |
566 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
567 | DP_DSC_MAX_ENC_THROUGHPUT_1); | |
568 | ||
569 | max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); | |
570 | if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { | |
571 | DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n", | |
572 | max_slice_width); | |
573 | return 0; | |
574 | } | |
575 | /* Also take into account max slice width */ | |
576 | min_slice_count = min_t(u8, min_slice_count, | |
577 | DIV_ROUND_UP(mode_hdisplay, | |
578 | max_slice_width)); | |
579 | ||
580 | /* Find the closest match to the valid slice count values */ | |
581 | for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { | |
582 | if (valid_dsc_slicecount[i] > | |
583 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, | |
584 | false)) | |
585 | break; | |
586 | if (min_slice_count <= valid_dsc_slicecount[i]) | |
587 | return valid_dsc_slicecount[i]; | |
588 | } | |
589 | ||
590 | DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count); | |
591 | return 0; | |
592 | } | |
593 | ||
98c93394 VS |
594 | static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, |
595 | int hdisplay) | |
596 | { | |
597 | /* | |
598 | * Older platforms don't like hdisplay==4096 with DP. | |
599 | * | |
600 | * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline | |
601 | * and frame counter increment), but we don't get vblank interrupts, | |
602 | * and the pipe underruns immediately. The link also doesn't seem | |
603 | * to get trained properly. | |
604 | * | |
605 | * On CHV the vblank interrupts don't seem to disappear but | |
606 | * otherwise the symptoms are similar. | |
607 | * | |
608 | * TODO: confirm the behaviour on HSW+ | |
609 | */ | |
610 | return hdisplay == 4096 && !HAS_DDI(dev_priv); | |
611 | } | |
612 | ||
c19de8eb | 613 | static enum drm_mode_status |
a4fc5ed6 KP |
614 | intel_dp_mode_valid(struct drm_connector *connector, |
615 | struct drm_display_mode *mode) | |
616 | { | |
43a6d19c | 617 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
dd06f90e JN |
618 | struct intel_connector *intel_connector = to_intel_connector(connector); |
619 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
6cfd04b0 | 620 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
36008365 DV |
621 | int target_clock = mode->clock; |
622 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 | 623 | int max_dotclk; |
6cfd04b0 MN |
624 | u16 dsc_max_output_bpp = 0; |
625 | u8 dsc_slice_count = 0; | |
70ec0645 | 626 | |
e4dd27aa VS |
627 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
628 | return MODE_NO_DBLESCAN; | |
629 | ||
70ec0645 | 630 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); |
a4fc5ed6 | 631 | |
1853a9da | 632 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
dd06f90e | 633 | if (mode->hdisplay > fixed_mode->hdisplay) |
7de56f43 ZY |
634 | return MODE_PANEL; |
635 | ||
dd06f90e | 636 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 637 | return MODE_PANEL; |
03afc4a2 DV |
638 | |
639 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
640 | } |
641 | ||
50fec21a | 642 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 643 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
644 | |
645 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
646 | mode_rate = intel_dp_link_required(target_clock, 18); | |
647 | ||
98c93394 VS |
648 | if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) |
649 | return MODE_H_ILLEGAL; | |
650 | ||
6cfd04b0 MN |
651 | /* |
652 | * Output bpp is stored in 6.4 format so right shift by 4 to get the | |
653 | * integer value since we support only integer values of bpp. | |
654 | */ | |
655 | if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && | |
656 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { | |
657 | if (intel_dp_is_edp(intel_dp)) { | |
658 | dsc_max_output_bpp = | |
659 | drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; | |
660 | dsc_slice_count = | |
661 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, | |
662 | true); | |
240999cf | 663 | } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { |
6cfd04b0 | 664 | dsc_max_output_bpp = |
45d3c5cd MR |
665 | intel_dp_dsc_get_output_bpp(dev_priv, |
666 | max_link_clock, | |
6cfd04b0 MN |
667 | max_lanes, |
668 | target_clock, | |
669 | mode->hdisplay) >> 4; | |
670 | dsc_slice_count = | |
671 | intel_dp_dsc_get_slice_count(intel_dp, | |
672 | target_clock, | |
673 | mode->hdisplay); | |
674 | } | |
675 | } | |
676 | ||
677 | if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || | |
678 | target_clock > max_dotclk) | |
c4867936 | 679 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
680 | |
681 | if (mode->clock < 10000) | |
682 | return MODE_CLOCK_LOW; | |
683 | ||
0af78a2b DV |
684 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
685 | return MODE_H_ILLEGAL; | |
686 | ||
2d20411e | 687 | return intel_mode_valid_max_plane_size(dev_priv, mode); |
a4fc5ed6 KP |
688 | } |
689 | ||
830de422 | 690 | u32 intel_dp_pack_aux(const u8 *src, int src_bytes) |
a4fc5ed6 | 691 | { |
830de422 JN |
692 | int i; |
693 | u32 v = 0; | |
a4fc5ed6 KP |
694 | |
695 | if (src_bytes > 4) | |
696 | src_bytes = 4; | |
697 | for (i = 0; i < src_bytes; i++) | |
830de422 | 698 | v |= ((u32)src[i]) << ((3 - i) * 8); |
a4fc5ed6 KP |
699 | return v; |
700 | } | |
701 | ||
830de422 | 702 | static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) |
a4fc5ed6 KP |
703 | { |
704 | int i; | |
705 | if (dst_bytes > 4) | |
706 | dst_bytes = 4; | |
707 | for (i = 0; i < dst_bytes; i++) | |
708 | dst[i] = src >> ((3-i) * 8); | |
709 | } | |
710 | ||
bf13e81b | 711 | static void |
46bd8383 | 712 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); |
bf13e81b | 713 | static void |
46bd8383 | 714 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 715 | bool force_disable_vdd); |
335f752b | 716 | static void |
46bd8383 | 717 | intel_dp_pps_init(struct intel_dp *intel_dp); |
bf13e81b | 718 | |
69d93820 CW |
719 | static intel_wakeref_t |
720 | pps_lock(struct intel_dp *intel_dp) | |
773538e8 | 721 | { |
de25eb7f | 722 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 723 | intel_wakeref_t wakeref; |
773538e8 VS |
724 | |
725 | /* | |
40c7ae45 | 726 | * See intel_power_sequencer_reset() why we need |
773538e8 VS |
727 | * a power domain reference here. |
728 | */ | |
69d93820 CW |
729 | wakeref = intel_display_power_get(dev_priv, |
730 | intel_aux_power_domain(dp_to_dig_port(intel_dp))); | |
773538e8 VS |
731 | |
732 | mutex_lock(&dev_priv->pps_mutex); | |
69d93820 CW |
733 | |
734 | return wakeref; | |
773538e8 VS |
735 | } |
736 | ||
69d93820 CW |
737 | static intel_wakeref_t |
738 | pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) | |
773538e8 | 739 | { |
de25eb7f | 740 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
773538e8 VS |
741 | |
742 | mutex_unlock(&dev_priv->pps_mutex); | |
69d93820 CW |
743 | intel_display_power_put(dev_priv, |
744 | intel_aux_power_domain(dp_to_dig_port(intel_dp)), | |
745 | wakeref); | |
746 | return 0; | |
773538e8 VS |
747 | } |
748 | ||
69d93820 CW |
749 | #define with_pps_lock(dp, wf) \ |
750 | for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) | |
751 | ||
961a0db0 VS |
752 | static void |
753 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
754 | { | |
de25eb7f | 755 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
961a0db0 | 756 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
961a0db0 | 757 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
758 | bool pll_enabled, release_cl_override = false; |
759 | enum dpio_phy phy = DPIO_PHY(pipe); | |
760 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
830de422 | 761 | u32 DP; |
961a0db0 VS |
762 | |
763 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
66a990dd VS |
764 | "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", |
765 | pipe_name(pipe), intel_dig_port->base.base.base.id, | |
766 | intel_dig_port->base.base.name)) | |
961a0db0 VS |
767 | return; |
768 | ||
66a990dd VS |
769 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", |
770 | pipe_name(pipe), intel_dig_port->base.base.base.id, | |
771 | intel_dig_port->base.base.name); | |
961a0db0 VS |
772 | |
773 | /* Preserve the BIOS-computed detected bit. This is | |
774 | * supposed to be read-only. | |
775 | */ | |
776 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
777 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
778 | DP |= DP_PORT_WIDTH(1); | |
779 | DP |= DP_LINK_TRAIN_PAT_1; | |
780 | ||
920a14b2 | 781 | if (IS_CHERRYVIEW(dev_priv)) |
59b74c49 VS |
782 | DP |= DP_PIPE_SEL_CHV(pipe); |
783 | else | |
784 | DP |= DP_PIPE_SEL(pipe); | |
961a0db0 | 785 | |
d288f65f VS |
786 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
787 | ||
788 | /* | |
789 | * The DPLL for the pipe must be enabled for this to work. | |
790 | * So enable temporarily it if it's not already enabled. | |
791 | */ | |
0047eedc | 792 | if (!pll_enabled) { |
920a14b2 | 793 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
794 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
795 | ||
30ad9814 | 796 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
797 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
798 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
799 | pipe_name(pipe)); | |
800 | return; | |
801 | } | |
0047eedc | 802 | } |
d288f65f | 803 | |
961a0db0 VS |
804 | /* |
805 | * Similar magic as in intel_dp_enable_port(). | |
806 | * We _must_ do this port enable + disable trick | |
e7f2af78 | 807 | * to make this power sequencer lock onto the port. |
961a0db0 VS |
808 | * Otherwise even VDD force bit won't work. |
809 | */ | |
810 | I915_WRITE(intel_dp->output_reg, DP); | |
811 | POSTING_READ(intel_dp->output_reg); | |
812 | ||
813 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
814 | POSTING_READ(intel_dp->output_reg); | |
815 | ||
816 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
817 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 818 | |
0047eedc | 819 | if (!pll_enabled) { |
30ad9814 | 820 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
821 | |
822 | if (release_cl_override) | |
823 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
824 | } | |
961a0db0 VS |
825 | } |
826 | ||
9f2bdb00 VS |
827 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
828 | { | |
829 | struct intel_encoder *encoder; | |
830 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
831 | ||
832 | /* | |
833 | * We don't have power sequencer currently. | |
834 | * Pick one that's not used by other ports. | |
835 | */ | |
14aa521c | 836 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 837 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
9f2bdb00 VS |
838 | |
839 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
840 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && | |
841 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
842 | ||
843 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
844 | pipes &= ~(1 << intel_dp->pps_pipe); | |
845 | } else { | |
846 | WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); | |
847 | ||
848 | if (intel_dp->active_pipe != INVALID_PIPE) | |
849 | pipes &= ~(1 << intel_dp->active_pipe); | |
850 | } | |
851 | } | |
852 | ||
853 | if (pipes == 0) | |
854 | return INVALID_PIPE; | |
855 | ||
856 | return ffs(pipes) - 1; | |
857 | } | |
858 | ||
bf13e81b JN |
859 | static enum pipe |
860 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
861 | { | |
de25eb7f | 862 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
bf13e81b | 863 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
a8c3344e | 864 | enum pipe pipe; |
bf13e81b | 865 | |
e39b999a | 866 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 867 | |
a8c3344e | 868 | /* We should never land here with regular DP ports */ |
1853a9da | 869 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
a8c3344e | 870 | |
9f2bdb00 VS |
871 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
872 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
873 | ||
a4a5d2f8 VS |
874 | if (intel_dp->pps_pipe != INVALID_PIPE) |
875 | return intel_dp->pps_pipe; | |
876 | ||
9f2bdb00 | 877 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
878 | |
879 | /* | |
880 | * Didn't find one. This should not happen since there | |
881 | * are two power sequencers and up to two eDP ports. | |
882 | */ | |
9f2bdb00 | 883 | if (WARN_ON(pipe == INVALID_PIPE)) |
a8c3344e | 884 | pipe = PIPE_A; |
a4a5d2f8 | 885 | |
46bd8383 | 886 | vlv_steal_power_sequencer(dev_priv, pipe); |
a8c3344e | 887 | intel_dp->pps_pipe = pipe; |
a4a5d2f8 | 888 | |
66a990dd | 889 | DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n", |
a4a5d2f8 | 890 | pipe_name(intel_dp->pps_pipe), |
66a990dd VS |
891 | intel_dig_port->base.base.base.id, |
892 | intel_dig_port->base.base.name); | |
a4a5d2f8 VS |
893 | |
894 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
895 | intel_dp_init_panel_power_sequencer(intel_dp); |
896 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 | 897 | |
961a0db0 VS |
898 | /* |
899 | * Even vdd force doesn't work until we've made | |
900 | * the power sequencer lock in on the port. | |
901 | */ | |
902 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
903 | |
904 | return intel_dp->pps_pipe; | |
905 | } | |
906 | ||
78597996 ID |
907 | static int |
908 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
909 | { | |
de25eb7f | 910 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
73c0fcac | 911 | int backlight_controller = dev_priv->vbt.backlight.controller; |
78597996 ID |
912 | |
913 | lockdep_assert_held(&dev_priv->pps_mutex); | |
914 | ||
915 | /* We should never land here with regular DP ports */ | |
1853a9da | 916 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
78597996 | 917 | |
78597996 | 918 | if (!intel_dp->pps_reset) |
73c0fcac | 919 | return backlight_controller; |
78597996 ID |
920 | |
921 | intel_dp->pps_reset = false; | |
922 | ||
923 | /* | |
924 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
925 | * has been setup during connector init. | |
926 | */ | |
46bd8383 | 927 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); |
78597996 | 928 | |
73c0fcac | 929 | return backlight_controller; |
78597996 ID |
930 | } |
931 | ||
6491ab27 VS |
932 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
933 | enum pipe pipe); | |
934 | ||
935 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
936 | enum pipe pipe) | |
937 | { | |
44cb734c | 938 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
939 | } |
940 | ||
941 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
942 | enum pipe pipe) | |
943 | { | |
44cb734c | 944 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
945 | } |
946 | ||
947 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
948 | enum pipe pipe) | |
949 | { | |
950 | return true; | |
951 | } | |
bf13e81b | 952 | |
a4a5d2f8 | 953 | static enum pipe |
6491ab27 VS |
954 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
955 | enum port port, | |
956 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
957 | { |
958 | enum pipe pipe; | |
bf13e81b | 959 | |
bf13e81b | 960 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 961 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 962 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
963 | |
964 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
965 | continue; | |
966 | ||
6491ab27 VS |
967 | if (!pipe_check(dev_priv, pipe)) |
968 | continue; | |
969 | ||
a4a5d2f8 | 970 | return pipe; |
bf13e81b JN |
971 | } |
972 | ||
a4a5d2f8 VS |
973 | return INVALID_PIPE; |
974 | } | |
975 | ||
976 | static void | |
977 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
978 | { | |
de25eb7f | 979 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a4a5d2f8 | 980 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 981 | enum port port = intel_dig_port->base.port; |
a4a5d2f8 VS |
982 | |
983 | lockdep_assert_held(&dev_priv->pps_mutex); | |
984 | ||
985 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
986 | /* first pick one where the panel is on */ |
987 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
988 | vlv_pipe_has_pp_on); | |
989 | /* didn't find one? pick one where vdd is on */ | |
990 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
991 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
992 | vlv_pipe_has_vdd_on); | |
993 | /* didn't find one? pick one with just the correct port */ | |
994 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
995 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
996 | vlv_pipe_any); | |
a4a5d2f8 VS |
997 | |
998 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
999 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
66a990dd VS |
1000 | DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n", |
1001 | intel_dig_port->base.base.base.id, | |
1002 | intel_dig_port->base.base.name); | |
a4a5d2f8 | 1003 | return; |
bf13e81b JN |
1004 | } |
1005 | ||
66a990dd VS |
1006 | DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", |
1007 | intel_dig_port->base.base.base.id, | |
1008 | intel_dig_port->base.base.name, | |
1009 | pipe_name(intel_dp->pps_pipe)); | |
a4a5d2f8 | 1010 | |
46bd8383 VS |
1011 | intel_dp_init_panel_power_sequencer(intel_dp); |
1012 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
bf13e81b JN |
1013 | } |
1014 | ||
78597996 | 1015 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 1016 | { |
773538e8 VS |
1017 | struct intel_encoder *encoder; |
1018 | ||
920a14b2 | 1019 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 1020 | !IS_GEN9_LP(dev_priv))) |
773538e8 VS |
1021 | return; |
1022 | ||
1023 | /* | |
1024 | * We can't grab pps_mutex here due to deadlock with power_domain | |
1025 | * mutex when power_domain functions are called while holding pps_mutex. | |
1026 | * That also means that in order to use pps_pipe the code needs to | |
1027 | * hold both a power domain reference and pps_mutex, and the power domain | |
1028 | * reference get/put must be done while _not_ holding pps_mutex. | |
1029 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
1030 | * should use them always. | |
1031 | */ | |
1032 | ||
14aa521c | 1033 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 1034 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7e732cac | 1035 | |
9f2bdb00 VS |
1036 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
1037 | ||
1038 | if (encoder->type != INTEL_OUTPUT_EDP) | |
1039 | continue; | |
1040 | ||
cc3f90f0 | 1041 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
1042 | intel_dp->pps_reset = true; |
1043 | else | |
1044 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 1045 | } |
bf13e81b JN |
1046 | } |
1047 | ||
8e8232d5 ID |
1048 | struct pps_registers { |
1049 | i915_reg_t pp_ctrl; | |
1050 | i915_reg_t pp_stat; | |
1051 | i915_reg_t pp_on; | |
1052 | i915_reg_t pp_off; | |
1053 | i915_reg_t pp_div; | |
1054 | }; | |
1055 | ||
46bd8383 | 1056 | static void intel_pps_get_registers(struct intel_dp *intel_dp, |
8e8232d5 ID |
1057 | struct pps_registers *regs) |
1058 | { | |
de25eb7f | 1059 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
44cb734c ID |
1060 | int pps_idx = 0; |
1061 | ||
8e8232d5 ID |
1062 | memset(regs, 0, sizeof(*regs)); |
1063 | ||
cc3f90f0 | 1064 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
1065 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
1066 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1067 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 1068 | |
44cb734c ID |
1069 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
1070 | regs->pp_stat = PP_STATUS(pps_idx); | |
1071 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
1072 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
ab3517c1 JN |
1073 | |
1074 | /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ | |
c6c30b91 | 1075 | if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) |
ab3517c1 JN |
1076 | regs->pp_div = INVALID_MMIO_REG; |
1077 | else | |
44cb734c | 1078 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
1079 | } |
1080 | ||
f0f59a00 VS |
1081 | static i915_reg_t |
1082 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 1083 | { |
8e8232d5 | 1084 | struct pps_registers regs; |
bf13e81b | 1085 | |
46bd8383 | 1086 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
1087 | |
1088 | return regs.pp_ctrl; | |
bf13e81b JN |
1089 | } |
1090 | ||
f0f59a00 VS |
1091 | static i915_reg_t |
1092 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 1093 | { |
8e8232d5 | 1094 | struct pps_registers regs; |
bf13e81b | 1095 | |
46bd8383 | 1096 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
1097 | |
1098 | return regs.pp_stat; | |
bf13e81b JN |
1099 | } |
1100 | ||
01527b31 CT |
1101 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
1102 | This function only applicable when panel PM state is not to be tracked */ | |
1103 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
1104 | void *unused) | |
1105 | { | |
1106 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
1107 | edp_notifier); | |
de25eb7f | 1108 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 1109 | intel_wakeref_t wakeref; |
01527b31 | 1110 | |
1853a9da | 1111 | if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) |
01527b31 CT |
1112 | return 0; |
1113 | ||
69d93820 CW |
1114 | with_pps_lock(intel_dp, wakeref) { |
1115 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
1116 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); | |
1117 | i915_reg_t pp_ctrl_reg, pp_div_reg; | |
1118 | u32 pp_div; | |
1119 | ||
1120 | pp_ctrl_reg = PP_CONTROL(pipe); | |
1121 | pp_div_reg = PP_DIVISOR(pipe); | |
1122 | pp_div = I915_READ(pp_div_reg); | |
1123 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
1124 | ||
1125 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
1126 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
bfb0a2cb | 1127 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS); |
69d93820 CW |
1128 | msleep(intel_dp->panel_power_cycle_delay); |
1129 | } | |
01527b31 CT |
1130 | } |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
4be73780 | 1135 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 1136 | { |
de25eb7f | 1137 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1138 | |
e39b999a VS |
1139 | lockdep_assert_held(&dev_priv->pps_mutex); |
1140 | ||
920a14b2 | 1141 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
1142 | intel_dp->pps_pipe == INVALID_PIPE) |
1143 | return false; | |
1144 | ||
bf13e81b | 1145 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
1146 | } |
1147 | ||
4be73780 | 1148 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 1149 | { |
de25eb7f | 1150 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1151 | |
e39b999a VS |
1152 | lockdep_assert_held(&dev_priv->pps_mutex); |
1153 | ||
920a14b2 | 1154 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
1155 | intel_dp->pps_pipe == INVALID_PIPE) |
1156 | return false; | |
1157 | ||
773538e8 | 1158 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
1159 | } |
1160 | ||
9b984dae KP |
1161 | static void |
1162 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
1163 | { | |
de25eb7f | 1164 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1165 | |
1853a9da | 1166 | if (!intel_dp_is_edp(intel_dp)) |
9b984dae | 1167 | return; |
453c5420 | 1168 | |
4be73780 | 1169 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
1170 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
1171 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
1172 | I915_READ(_pp_stat_reg(intel_dp)), |
1173 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
1174 | } |
1175 | } | |
1176 | ||
830de422 | 1177 | static u32 |
8a29c778 | 1178 | intel_dp_aux_wait_done(struct intel_dp *intel_dp) |
9ee32fea | 1179 | { |
5a31d30b | 1180 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
4904fa66 | 1181 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
54516464 | 1182 | const unsigned int timeout_ms = 10; |
830de422 | 1183 | u32 status; |
9ee32fea DV |
1184 | bool done; |
1185 | ||
5a31d30b TU |
1186 | #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1187 | done = wait_event_timeout(i915->gmbus_wait_queue, C, | |
54516464 | 1188 | msecs_to_jiffies_timeout(timeout_ms)); |
39806c3f VS |
1189 | |
1190 | /* just trace the final value */ | |
1191 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); | |
1192 | ||
9ee32fea | 1193 | if (!done) |
54516464 MR |
1194 | DRM_ERROR("%s did not complete or timeout within %ums (status 0x%08x)\n", |
1195 | intel_dp->aux.name, timeout_ms, status); | |
9ee32fea DV |
1196 | #undef C |
1197 | ||
1198 | return status; | |
1199 | } | |
1200 | ||
830de422 | 1201 | static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 1202 | { |
de25eb7f | 1203 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
9ee32fea | 1204 | |
a457f54b VS |
1205 | if (index) |
1206 | return 0; | |
1207 | ||
ec5b01dd DL |
1208 | /* |
1209 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 1210 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 1211 | */ |
a457f54b | 1212 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
1213 | } |
1214 | ||
830de422 | 1215 | static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
ec5b01dd | 1216 | { |
de25eb7f | 1217 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 | 1218 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
ec5b01dd DL |
1219 | |
1220 | if (index) | |
1221 | return 0; | |
1222 | ||
a457f54b VS |
1223 | /* |
1224 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
1225 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
1226 | * divide by 2000 and use that | |
1227 | */ | |
563d22a0 | 1228 | if (dig_port->aux_ch == AUX_CH_A) |
49cd97a3 | 1229 | return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); |
e7dc33f3 VS |
1230 | else |
1231 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
1232 | } |
1233 | ||
830de422 | 1234 | static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
ec5b01dd | 1235 | { |
de25eb7f | 1236 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 | 1237 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
ec5b01dd | 1238 | |
563d22a0 | 1239 | if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 1240 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
1241 | switch (index) { |
1242 | case 0: return 63; | |
1243 | case 1: return 72; | |
1244 | default: return 0; | |
1245 | } | |
2c55c336 | 1246 | } |
a457f54b VS |
1247 | |
1248 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
1249 | } |
1250 | ||
830de422 | 1251 | static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
b6b5e383 DL |
1252 | { |
1253 | /* | |
1254 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
1255 | * derive the clock from CDCLK automatically). We still implement the | |
1256 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
1257 | */ | |
1258 | return index ? 0 : 1; | |
1259 | } | |
1260 | ||
830de422 JN |
1261 | static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
1262 | int send_bytes, | |
1263 | u32 aux_clock_divider) | |
5ed12a19 DL |
1264 | { |
1265 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
1266 | struct drm_i915_private *dev_priv = |
1267 | to_i915(intel_dig_port->base.base.dev); | |
830de422 | 1268 | u32 precharge, timeout; |
5ed12a19 | 1269 | |
cf819eff | 1270 | if (IS_GEN(dev_priv, 6)) |
5ed12a19 DL |
1271 | precharge = 3; |
1272 | else | |
1273 | precharge = 5; | |
1274 | ||
8f5f63d5 | 1275 | if (IS_BROADWELL(dev_priv)) |
5ed12a19 DL |
1276 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
1277 | else | |
1278 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
1279 | ||
1280 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 1281 | DP_AUX_CH_CTL_DONE | |
8a29c778 | 1282 | DP_AUX_CH_CTL_INTERRUPT | |
788d4433 | 1283 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 1284 | timeout | |
788d4433 | 1285 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
1286 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1287 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 1288 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
1289 | } |
1290 | ||
830de422 JN |
1291 | static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
1292 | int send_bytes, | |
1293 | u32 unused) | |
b9ca5fad | 1294 | { |
6f211ed4 | 1295 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
49748264 JRS |
1296 | struct drm_i915_private *i915 = |
1297 | to_i915(intel_dig_port->base.base.dev); | |
1298 | enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); | |
830de422 | 1299 | u32 ret; |
6f211ed4 AS |
1300 | |
1301 | ret = DP_AUX_CH_CTL_SEND_BUSY | | |
1302 | DP_AUX_CH_CTL_DONE | | |
1303 | DP_AUX_CH_CTL_INTERRUPT | | |
1304 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1305 | DP_AUX_CH_CTL_TIME_OUT_MAX | | |
1306 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
1307 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1308 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | | |
1309 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); | |
1310 | ||
49748264 JRS |
1311 | if (intel_phy_is_tc(i915, phy) && |
1312 | intel_dig_port->tc_mode == TC_PORT_TBT_ALT) | |
6f211ed4 AS |
1313 | ret |= DP_AUX_CH_CTL_TBT_IO; |
1314 | ||
1315 | return ret; | |
b9ca5fad DL |
1316 | } |
1317 | ||
b84a1cf8 | 1318 | static int |
f7606265 | 1319 | intel_dp_aux_xfer(struct intel_dp *intel_dp, |
830de422 JN |
1320 | const u8 *send, int send_bytes, |
1321 | u8 *recv, int recv_size, | |
8159c796 | 1322 | u32 aux_send_ctl_flags) |
b84a1cf8 RV |
1323 | { |
1324 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5a31d30b | 1325 | struct drm_i915_private *i915 = |
0031fb96 | 1326 | to_i915(intel_dig_port->base.base.dev); |
5a31d30b | 1327 | struct intel_uncore *uncore = &i915->uncore; |
d8fe2ab6 MR |
1328 | enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); |
1329 | bool is_tc_port = intel_phy_is_tc(i915, phy); | |
4904fa66 | 1330 | i915_reg_t ch_ctl, ch_data[5]; |
830de422 | 1331 | u32 aux_clock_divider; |
f39194a7 ID |
1332 | enum intel_display_power_domain aux_domain = |
1333 | intel_aux_power_domain(intel_dig_port); | |
1334 | intel_wakeref_t aux_wakeref; | |
1335 | intel_wakeref_t pps_wakeref; | |
b84a1cf8 | 1336 | int i, ret, recv_bytes; |
5ed12a19 | 1337 | int try, clock = 0; |
830de422 | 1338 | u32 status; |
884f19e9 JN |
1339 | bool vdd; |
1340 | ||
4904fa66 VS |
1341 | ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
1342 | for (i = 0; i < ARRAY_SIZE(ch_data); i++) | |
1343 | ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); | |
1344 | ||
8c10e226 ID |
1345 | if (is_tc_port) |
1346 | intel_tc_port_lock(intel_dig_port); | |
1347 | ||
5a31d30b | 1348 | aux_wakeref = intel_display_power_get(i915, aux_domain); |
f39194a7 | 1349 | pps_wakeref = pps_lock(intel_dp); |
e39b999a | 1350 | |
72c3500a VS |
1351 | /* |
1352 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1353 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1354 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1355 | * ourselves. | |
1356 | */ | |
1e0560e0 | 1357 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1358 | |
1359 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1360 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1361 | * deep sleep states. | |
1362 | */ | |
4d4dda48 | 1363 | cpu_latency_qos_update_request(&i915->pm_qos, 0); |
b84a1cf8 RV |
1364 | |
1365 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1366 | |
11bee43e JB |
1367 | /* Try to wait for any previous AUX channel activity */ |
1368 | for (try = 0; try < 3; try++) { | |
5a31d30b | 1369 | status = intel_uncore_read_notrace(uncore, ch_ctl); |
11bee43e JB |
1370 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1371 | break; | |
1372 | msleep(1); | |
1373 | } | |
39806c3f VS |
1374 | /* just trace the final value */ |
1375 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); | |
11bee43e JB |
1376 | |
1377 | if (try == 3) { | |
5a31d30b | 1378 | const u32 status = intel_uncore_read(uncore, ch_ctl); |
02196c77 | 1379 | |
81cdeca4 | 1380 | if (status != intel_dp->aux_busy_last_status) { |
02196c77 MK |
1381 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
1382 | status); | |
81cdeca4 | 1383 | intel_dp->aux_busy_last_status = status; |
02196c77 MK |
1384 | } |
1385 | ||
9ee32fea DV |
1386 | ret = -EBUSY; |
1387 | goto out; | |
4f7f7b7e CW |
1388 | } |
1389 | ||
46a5ae9f PZ |
1390 | /* Only 5 data registers! */ |
1391 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
1392 | ret = -E2BIG; | |
1393 | goto out; | |
1394 | } | |
1395 | ||
ec5b01dd | 1396 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
8159c796 | 1397 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
8159c796 VS |
1398 | send_bytes, |
1399 | aux_clock_divider); | |
1400 | ||
1401 | send_ctl |= aux_send_ctl_flags; | |
5ed12a19 | 1402 | |
bc86625a CW |
1403 | /* Must try at least 3 times according to DP spec */ |
1404 | for (try = 0; try < 5; try++) { | |
1405 | /* Load the send data into the aux channel data registers */ | |
1406 | for (i = 0; i < send_bytes; i += 4) | |
5a31d30b TU |
1407 | intel_uncore_write(uncore, |
1408 | ch_data[i >> 2], | |
1409 | intel_dp_pack_aux(send + i, | |
1410 | send_bytes - i)); | |
bc86625a CW |
1411 | |
1412 | /* Send the command and wait for it to complete */ | |
5a31d30b | 1413 | intel_uncore_write(uncore, ch_ctl, send_ctl); |
bc86625a | 1414 | |
8a29c778 | 1415 | status = intel_dp_aux_wait_done(intel_dp); |
bc86625a CW |
1416 | |
1417 | /* Clear done status and any errors */ | |
5a31d30b TU |
1418 | intel_uncore_write(uncore, |
1419 | ch_ctl, | |
1420 | status | | |
1421 | DP_AUX_CH_CTL_DONE | | |
1422 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1423 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
bc86625a | 1424 | |
74ebf294 TP |
1425 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
1426 | * 400us delay required for errors and timeouts | |
1427 | * Timeout errors from the HW already meet this | |
1428 | * requirement so skip to next iteration | |
1429 | */ | |
3975f0aa DP |
1430 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
1431 | continue; | |
1432 | ||
74ebf294 TP |
1433 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1434 | usleep_range(400, 500); | |
bc86625a | 1435 | continue; |
74ebf294 | 1436 | } |
bc86625a | 1437 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1438 | goto done; |
bc86625a | 1439 | } |
a4fc5ed6 KP |
1440 | } |
1441 | ||
a4fc5ed6 | 1442 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1443 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1444 | ret = -EBUSY; |
1445 | goto out; | |
a4fc5ed6 KP |
1446 | } |
1447 | ||
e058c945 | 1448 | done: |
a4fc5ed6 KP |
1449 | /* Check for timeout or receive error. |
1450 | * Timeouts occur when the sink is not connected | |
1451 | */ | |
a5b3da54 | 1452 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1453 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1454 | ret = -EIO; |
1455 | goto out; | |
a5b3da54 | 1456 | } |
1ae8c0a5 KP |
1457 | |
1458 | /* Timeouts occur when the device isn't connected, so they're | |
1459 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1460 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
a5570fe5 | 1461 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1462 | ret = -ETIMEDOUT; |
1463 | goto out; | |
a4fc5ed6 KP |
1464 | } |
1465 | ||
1466 | /* Unload any bytes sent back from the other side */ | |
1467 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1468 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1469 | |
1470 | /* | |
1471 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1472 | * We have no idea of what happened so we return -EBUSY so | |
1473 | * drm layer takes care for the necessary retries. | |
1474 | */ | |
1475 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1476 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1477 | recv_bytes); | |
14e01889 RV |
1478 | ret = -EBUSY; |
1479 | goto out; | |
1480 | } | |
1481 | ||
a4fc5ed6 KP |
1482 | if (recv_bytes > recv_size) |
1483 | recv_bytes = recv_size; | |
0206e353 | 1484 | |
4f7f7b7e | 1485 | for (i = 0; i < recv_bytes; i += 4) |
5a31d30b | 1486 | intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), |
a4f1289e | 1487 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1488 | |
9ee32fea DV |
1489 | ret = recv_bytes; |
1490 | out: | |
4d4dda48 | 1491 | cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 1492 | |
884f19e9 JN |
1493 | if (vdd) |
1494 | edp_panel_vdd_off(intel_dp, false); | |
1495 | ||
f39194a7 | 1496 | pps_unlock(intel_dp, pps_wakeref); |
5a31d30b | 1497 | intel_display_power_put_async(i915, aux_domain, aux_wakeref); |
e39b999a | 1498 | |
8c10e226 ID |
1499 | if (is_tc_port) |
1500 | intel_tc_port_unlock(intel_dig_port); | |
1501 | ||
9ee32fea | 1502 | return ret; |
a4fc5ed6 KP |
1503 | } |
1504 | ||
a6c8aff0 JN |
1505 | #define BARE_ADDRESS_SIZE 3 |
1506 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
32078b72 VS |
1507 | |
1508 | static void | |
1509 | intel_dp_aux_header(u8 txbuf[HEADER_SIZE], | |
1510 | const struct drm_dp_aux_msg *msg) | |
1511 | { | |
1512 | txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); | |
1513 | txbuf[1] = (msg->address >> 8) & 0xff; | |
1514 | txbuf[2] = msg->address & 0xff; | |
1515 | txbuf[3] = msg->size - 1; | |
1516 | } | |
1517 | ||
9d1a1031 JN |
1518 | static ssize_t |
1519 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1520 | { |
9d1a1031 | 1521 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
830de422 | 1522 | u8 txbuf[20], rxbuf[20]; |
9d1a1031 | 1523 | size_t txsize, rxsize; |
a4fc5ed6 | 1524 | int ret; |
a4fc5ed6 | 1525 | |
32078b72 | 1526 | intel_dp_aux_header(txbuf, msg); |
46a5ae9f | 1527 | |
9d1a1031 JN |
1528 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1529 | case DP_AUX_NATIVE_WRITE: | |
1530 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1531 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1532 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1533 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1534 | |
9d1a1031 JN |
1535 | if (WARN_ON(txsize > 20)) |
1536 | return -E2BIG; | |
a4fc5ed6 | 1537 | |
dd788090 VS |
1538 | WARN_ON(!msg->buffer != !msg->size); |
1539 | ||
d81a67cc ID |
1540 | if (msg->buffer) |
1541 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1542 | |
f7606265 | 1543 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
8159c796 | 1544 | rxbuf, rxsize, 0); |
9d1a1031 JN |
1545 | if (ret > 0) { |
1546 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1547 | |
a1ddefd8 JN |
1548 | if (ret > 1) { |
1549 | /* Number of bytes written in a short write. */ | |
1550 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1551 | } else { | |
1552 | /* Return payload size. */ | |
1553 | ret = msg->size; | |
1554 | } | |
9d1a1031 JN |
1555 | } |
1556 | break; | |
46a5ae9f | 1557 | |
9d1a1031 JN |
1558 | case DP_AUX_NATIVE_READ: |
1559 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1560 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1561 | rxsize = msg->size + 1; |
a4fc5ed6 | 1562 | |
9d1a1031 JN |
1563 | if (WARN_ON(rxsize > 20)) |
1564 | return -E2BIG; | |
a4fc5ed6 | 1565 | |
f7606265 | 1566 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
8159c796 | 1567 | rxbuf, rxsize, 0); |
9d1a1031 JN |
1568 | if (ret > 0) { |
1569 | msg->reply = rxbuf[0] >> 4; | |
1570 | /* | |
1571 | * Assume happy day, and copy the data. The caller is | |
1572 | * expected to check msg->reply before touching it. | |
1573 | * | |
1574 | * Return payload size. | |
1575 | */ | |
1576 | ret--; | |
1577 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1578 | } |
9d1a1031 JN |
1579 | break; |
1580 | ||
1581 | default: | |
1582 | ret = -EINVAL; | |
1583 | break; | |
a4fc5ed6 | 1584 | } |
f51a44b9 | 1585 | |
9d1a1031 | 1586 | return ret; |
a4fc5ed6 KP |
1587 | } |
1588 | ||
8f7ce038 | 1589 | |
4904fa66 | 1590 | static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) |
da00bdcf | 1591 | { |
de25eb7f | 1592 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1593 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1594 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1595 | |
bdabdb63 VS |
1596 | switch (aux_ch) { |
1597 | case AUX_CH_B: | |
1598 | case AUX_CH_C: | |
1599 | case AUX_CH_D: | |
1600 | return DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1601 | default: |
bdabdb63 VS |
1602 | MISSING_CASE(aux_ch); |
1603 | return DP_AUX_CH_CTL(AUX_CH_B); | |
da00bdcf VS |
1604 | } |
1605 | } | |
1606 | ||
4904fa66 | 1607 | static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) |
330e20ec | 1608 | { |
de25eb7f | 1609 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1610 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1611 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1612 | |
bdabdb63 VS |
1613 | switch (aux_ch) { |
1614 | case AUX_CH_B: | |
1615 | case AUX_CH_C: | |
1616 | case AUX_CH_D: | |
1617 | return DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1618 | default: |
bdabdb63 VS |
1619 | MISSING_CASE(aux_ch); |
1620 | return DP_AUX_CH_DATA(AUX_CH_B, index); | |
330e20ec VS |
1621 | } |
1622 | } | |
1623 | ||
4904fa66 | 1624 | static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1625 | { |
de25eb7f | 1626 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1627 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1628 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1629 | |
bdabdb63 VS |
1630 | switch (aux_ch) { |
1631 | case AUX_CH_A: | |
1632 | return DP_AUX_CH_CTL(aux_ch); | |
1633 | case AUX_CH_B: | |
1634 | case AUX_CH_C: | |
1635 | case AUX_CH_D: | |
1636 | return PCH_DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1637 | default: |
bdabdb63 VS |
1638 | MISSING_CASE(aux_ch); |
1639 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1640 | } |
1641 | } | |
1642 | ||
4904fa66 | 1643 | static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1644 | { |
de25eb7f | 1645 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1646 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1647 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1648 | |
bdabdb63 VS |
1649 | switch (aux_ch) { |
1650 | case AUX_CH_A: | |
1651 | return DP_AUX_CH_DATA(aux_ch, index); | |
1652 | case AUX_CH_B: | |
1653 | case AUX_CH_C: | |
1654 | case AUX_CH_D: | |
1655 | return PCH_DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1656 | default: |
bdabdb63 VS |
1657 | MISSING_CASE(aux_ch); |
1658 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1659 | } |
1660 | } | |
1661 | ||
4904fa66 | 1662 | static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1663 | { |
de25eb7f | 1664 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1665 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1666 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1667 | |
bdabdb63 VS |
1668 | switch (aux_ch) { |
1669 | case AUX_CH_A: | |
1670 | case AUX_CH_B: | |
1671 | case AUX_CH_C: | |
1672 | case AUX_CH_D: | |
bb187e93 | 1673 | case AUX_CH_E: |
bdabdb63 | 1674 | case AUX_CH_F: |
eb8de23c | 1675 | case AUX_CH_G: |
bdabdb63 | 1676 | return DP_AUX_CH_CTL(aux_ch); |
da00bdcf | 1677 | default: |
bdabdb63 VS |
1678 | MISSING_CASE(aux_ch); |
1679 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1680 | } |
1681 | } | |
1682 | ||
4904fa66 | 1683 | static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1684 | { |
de25eb7f | 1685 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1686 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1687 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1688 | |
bdabdb63 VS |
1689 | switch (aux_ch) { |
1690 | case AUX_CH_A: | |
1691 | case AUX_CH_B: | |
1692 | case AUX_CH_C: | |
1693 | case AUX_CH_D: | |
bb187e93 | 1694 | case AUX_CH_E: |
bdabdb63 | 1695 | case AUX_CH_F: |
eb8de23c | 1696 | case AUX_CH_G: |
bdabdb63 | 1697 | return DP_AUX_CH_DATA(aux_ch, index); |
330e20ec | 1698 | default: |
bdabdb63 VS |
1699 | MISSING_CASE(aux_ch); |
1700 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1701 | } |
1702 | } | |
1703 | ||
91e939ae VS |
1704 | static void |
1705 | intel_dp_aux_fini(struct intel_dp *intel_dp) | |
1706 | { | |
1707 | kfree(intel_dp->aux.name); | |
1708 | } | |
1709 | ||
1710 | static void | |
1711 | intel_dp_aux_init(struct intel_dp *intel_dp) | |
330e20ec | 1712 | { |
de25eb7f | 1713 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1714 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1715 | struct intel_encoder *encoder = &dig_port->base; | |
91e939ae | 1716 | |
4904fa66 VS |
1717 | if (INTEL_GEN(dev_priv) >= 9) { |
1718 | intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; | |
1719 | intel_dp->aux_ch_data_reg = skl_aux_data_reg; | |
1720 | } else if (HAS_PCH_SPLIT(dev_priv)) { | |
1721 | intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; | |
1722 | intel_dp->aux_ch_data_reg = ilk_aux_data_reg; | |
1723 | } else { | |
1724 | intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; | |
1725 | intel_dp->aux_ch_data_reg = g4x_aux_data_reg; | |
1726 | } | |
330e20ec | 1727 | |
91e939ae VS |
1728 | if (INTEL_GEN(dev_priv) >= 9) |
1729 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
1730 | else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
1731 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
1732 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1733 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
1734 | else | |
1735 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; | |
bdabdb63 | 1736 | |
91e939ae VS |
1737 | if (INTEL_GEN(dev_priv) >= 9) |
1738 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
1739 | else | |
1740 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; | |
ab2c0672 | 1741 | |
7a418e34 | 1742 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1743 | |
7a418e34 | 1744 | /* Failure to allocate our preferred name is not critical */ |
bdabdb63 VS |
1745 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", |
1746 | port_name(encoder->port)); | |
9d1a1031 | 1747 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1748 | } |
1749 | ||
e588fa18 | 1750 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1751 | { |
fc603ca7 | 1752 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
e588fa18 | 1753 | |
fc603ca7 | 1754 | return max_rate >= 540000; |
ed63baaf TS |
1755 | } |
1756 | ||
2edd5327 MN |
1757 | bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) |
1758 | { | |
1759 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; | |
1760 | ||
1761 | return max_rate >= 810000; | |
1762 | } | |
1763 | ||
c6bb3538 DV |
1764 | static void |
1765 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1766 | struct intel_crtc_state *pipe_config) |
c6bb3538 | 1767 | { |
2f773477 | 1768 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9dd4ffdf CML |
1769 | const struct dp_link_dpll *divisor = NULL; |
1770 | int i, count = 0; | |
c6bb3538 | 1771 | |
9beb5fea | 1772 | if (IS_G4X(dev_priv)) { |
45101e93 VS |
1773 | divisor = g4x_dpll; |
1774 | count = ARRAY_SIZE(g4x_dpll); | |
6e266956 | 1775 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1776 | divisor = pch_dpll; |
1777 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1778 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1779 | divisor = chv_dpll; |
1780 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1781 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1782 | divisor = vlv_dpll; |
1783 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1784 | } |
9dd4ffdf CML |
1785 | |
1786 | if (divisor && count) { | |
1787 | for (i = 0; i < count; i++) { | |
840b32b7 | 1788 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1789 | pipe_config->dpll = divisor[i].dpll; |
1790 | pipe_config->clock_set = true; | |
1791 | break; | |
1792 | } | |
1793 | } | |
c6bb3538 DV |
1794 | } |
1795 | } | |
1796 | ||
0336400e VS |
1797 | static void snprintf_int_array(char *str, size_t len, |
1798 | const int *array, int nelem) | |
1799 | { | |
1800 | int i; | |
1801 | ||
1802 | str[0] = '\0'; | |
1803 | ||
1804 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1805 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1806 | if (r >= len) |
1807 | return; | |
1808 | str += r; | |
1809 | len -= r; | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1814 | { | |
0336400e VS |
1815 | char str[128]; /* FIXME: too big for stack? */ |
1816 | ||
bdbf43d7 | 1817 | if (!drm_debug_enabled(DRM_UT_KMS)) |
0336400e VS |
1818 | return; |
1819 | ||
55cfc580 JN |
1820 | snprintf_int_array(str, sizeof(str), |
1821 | intel_dp->source_rates, intel_dp->num_source_rates); | |
0336400e VS |
1822 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1823 | ||
68f357cb JN |
1824 | snprintf_int_array(str, sizeof(str), |
1825 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
0336400e VS |
1826 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1827 | ||
975ee5fc JN |
1828 | snprintf_int_array(str, sizeof(str), |
1829 | intel_dp->common_rates, intel_dp->num_common_rates); | |
94ca719e | 1830 | DRM_DEBUG_KMS("common rates: %s\n", str); |
0336400e VS |
1831 | } |
1832 | ||
50fec21a VS |
1833 | int |
1834 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1835 | { | |
50fec21a VS |
1836 | int len; |
1837 | ||
e6c0c64a | 1838 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
50fec21a VS |
1839 | if (WARN_ON(len <= 0)) |
1840 | return 162000; | |
1841 | ||
975ee5fc | 1842 | return intel_dp->common_rates[len - 1]; |
50fec21a VS |
1843 | } |
1844 | ||
ed4e9c1d VS |
1845 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1846 | { | |
8001b754 JN |
1847 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1848 | intel_dp->num_sink_rates, rate); | |
b5c72b20 JN |
1849 | |
1850 | if (WARN_ON(i < 0)) | |
1851 | i = 0; | |
1852 | ||
1853 | return i; | |
ed4e9c1d VS |
1854 | } |
1855 | ||
94223d04 | 1856 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
830de422 | 1857 | u8 *link_bw, u8 *rate_select) |
04a60f9f | 1858 | { |
68f357cb JN |
1859 | /* eDP 1.4 rate select method. */ |
1860 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1861 | *link_bw = 0; |
1862 | *rate_select = | |
1863 | intel_dp_rate_select(intel_dp, port_clock); | |
1864 | } else { | |
1865 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1866 | *rate_select = 0; | |
1867 | } | |
1868 | } | |
1869 | ||
240999cf | 1870 | static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, |
a4a15777 MN |
1871 | const struct intel_crtc_state *pipe_config) |
1872 | { | |
1873 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1874 | ||
9770f220 MTP |
1875 | /* On TGL, FEC is supported on all Pipes */ |
1876 | if (INTEL_GEN(dev_priv) >= 12) | |
1877 | return true; | |
1878 | ||
1879 | if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) | |
1880 | return true; | |
1881 | ||
1882 | return false; | |
240999cf AS |
1883 | } |
1884 | ||
1885 | static bool intel_dp_supports_fec(struct intel_dp *intel_dp, | |
1886 | const struct intel_crtc_state *pipe_config) | |
1887 | { | |
1888 | return intel_dp_source_supports_fec(intel_dp, pipe_config) && | |
1889 | drm_dp_sink_supports_fec(intel_dp->fec_capable); | |
1890 | } | |
1891 | ||
a4a15777 | 1892 | static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, |
deaaff49 | 1893 | const struct intel_crtc_state *crtc_state) |
a4a15777 | 1894 | { |
deaaff49 JN |
1895 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
1896 | ||
1897 | if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable) | |
240999cf AS |
1898 | return false; |
1899 | ||
deaaff49 | 1900 | return intel_dsc_source_support(encoder, crtc_state) && |
a4a15777 MN |
1901 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); |
1902 | } | |
1903 | ||
f580bea9 JN |
1904 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1905 | struct intel_crtc_state *pipe_config) | |
f9bb705e | 1906 | { |
de25eb7f | 1907 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ef32659a | 1908 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
f9bb705e MK |
1909 | int bpp, bpc; |
1910 | ||
1911 | bpp = pipe_config->pipe_bpp; | |
1912 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1913 | ||
1914 | if (bpc > 0) | |
1915 | bpp = min(bpp, 3*bpc); | |
1916 | ||
ef32659a JN |
1917 | if (intel_dp_is_edp(intel_dp)) { |
1918 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1919 | if (intel_connector->base.display_info.bpc == 0 && | |
1920 | dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { | |
1921 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", | |
1922 | dev_priv->vbt.edp.bpp); | |
1923 | bpp = dev_priv->vbt.edp.bpp; | |
1924 | } | |
1925 | } | |
1926 | ||
f9bb705e MK |
1927 | return bpp; |
1928 | } | |
1929 | ||
a4971453 | 1930 | /* Adjust link config limits based on compliance test requests. */ |
f1477219 | 1931 | void |
a4971453 JN |
1932 | intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, |
1933 | struct intel_crtc_state *pipe_config, | |
1934 | struct link_config_limits *limits) | |
1935 | { | |
1936 | /* For DP Compliance we override the computed bpp for the pipe */ | |
1937 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1938 | int bpp = 3 * intel_dp->compliance.test_data.bpc; | |
1939 | ||
1940 | limits->min_bpp = limits->max_bpp = bpp; | |
1941 | pipe_config->dither_force_disable = bpp == 6 * 3; | |
1942 | ||
1943 | DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp); | |
1944 | } | |
1945 | ||
1946 | /* Use values requested by Compliance Test Request */ | |
1947 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
1948 | int index; | |
1949 | ||
1950 | /* Validate the compliance test data since max values | |
1951 | * might have changed due to link train fallback. | |
1952 | */ | |
1953 | if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, | |
1954 | intel_dp->compliance.test_lane_count)) { | |
1955 | index = intel_dp_rate_index(intel_dp->common_rates, | |
1956 | intel_dp->num_common_rates, | |
1957 | intel_dp->compliance.test_link_rate); | |
1958 | if (index >= 0) | |
1959 | limits->min_clock = limits->max_clock = index; | |
1960 | limits->min_lane_count = limits->max_lane_count = | |
1961 | intel_dp->compliance.test_lane_count; | |
1962 | } | |
1963 | } | |
1964 | } | |
1965 | ||
16668f48 GM |
1966 | static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp) |
1967 | { | |
1968 | /* | |
1969 | * bpp value was assumed to RGB format. And YCbCr 4:2:0 output | |
1970 | * format of the number of bytes per pixel will be half the number | |
1971 | * of bytes of RGB pixel. | |
1972 | */ | |
1973 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
1974 | bpp /= 2; | |
1975 | ||
1976 | return bpp; | |
1977 | } | |
1978 | ||
3acd115d | 1979 | /* Optimize link config in order: max bpp, min clock, min lanes */ |
204474a6 | 1980 | static int |
3acd115d JN |
1981 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, |
1982 | struct intel_crtc_state *pipe_config, | |
1983 | const struct link_config_limits *limits) | |
1984 | { | |
1326a92c | 1985 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
3acd115d JN |
1986 | int bpp, clock, lane_count; |
1987 | int mode_rate, link_clock, link_avail; | |
1988 | ||
1989 | for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { | |
ddb3d12a VS |
1990 | int output_bpp = intel_dp_output_bpp(pipe_config, bpp); |
1991 | ||
3acd115d | 1992 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
ddb3d12a | 1993 | output_bpp); |
3acd115d JN |
1994 | |
1995 | for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { | |
1996 | for (lane_count = limits->min_lane_count; | |
1997 | lane_count <= limits->max_lane_count; | |
1998 | lane_count <<= 1) { | |
1999 | link_clock = intel_dp->common_rates[clock]; | |
2000 | link_avail = intel_dp_max_data_rate(link_clock, | |
2001 | lane_count); | |
2002 | ||
2003 | if (mode_rate <= link_avail) { | |
2004 | pipe_config->lane_count = lane_count; | |
2005 | pipe_config->pipe_bpp = bpp; | |
2006 | pipe_config->port_clock = link_clock; | |
2007 | ||
204474a6 | 2008 | return 0; |
3acd115d JN |
2009 | } |
2010 | } | |
2011 | } | |
2012 | } | |
2013 | ||
204474a6 | 2014 | return -EINVAL; |
3acd115d JN |
2015 | } |
2016 | ||
a4a15777 MN |
2017 | static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) |
2018 | { | |
2019 | int i, num_bpc; | |
2020 | u8 dsc_bpc[3] = {0}; | |
2021 | ||
2022 | num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, | |
2023 | dsc_bpc); | |
2024 | for (i = 0; i < num_bpc; i++) { | |
2025 | if (dsc_max_bpc >= dsc_bpc[i]) | |
2026 | return dsc_bpc[i] * 3; | |
2027 | } | |
2028 | ||
2029 | return 0; | |
2030 | } | |
2031 | ||
7a7b5be9 JN |
2032 | #define DSC_SUPPORTED_VERSION_MIN 1 |
2033 | ||
2034 | static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, | |
2035 | struct intel_crtc_state *crtc_state) | |
2036 | { | |
b7d02c3a | 2037 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7a7b5be9 JN |
2038 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; |
2039 | u8 line_buf_depth; | |
2040 | int ret; | |
2041 | ||
2042 | ret = intel_dsc_compute_params(encoder, crtc_state); | |
2043 | if (ret) | |
2044 | return ret; | |
2045 | ||
c42c38ec JN |
2046 | /* |
2047 | * Slice Height of 8 works for all currently available panels. So start | |
2048 | * with that if pic_height is an integral multiple of 8. Eventually add | |
2049 | * logic to try multiple slice heights. | |
2050 | */ | |
2051 | if (vdsc_cfg->pic_height % 8 == 0) | |
2052 | vdsc_cfg->slice_height = 8; | |
2053 | else if (vdsc_cfg->pic_height % 4 == 0) | |
2054 | vdsc_cfg->slice_height = 4; | |
2055 | else | |
2056 | vdsc_cfg->slice_height = 2; | |
2057 | ||
7a7b5be9 JN |
2058 | vdsc_cfg->dsc_version_major = |
2059 | (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & | |
2060 | DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; | |
2061 | vdsc_cfg->dsc_version_minor = | |
2062 | min(DSC_SUPPORTED_VERSION_MIN, | |
2063 | (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & | |
2064 | DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); | |
2065 | ||
2066 | vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & | |
2067 | DP_DSC_RGB; | |
2068 | ||
2069 | line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); | |
2070 | if (!line_buf_depth) { | |
2071 | DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n"); | |
2072 | return -EINVAL; | |
2073 | } | |
2074 | ||
2075 | if (vdsc_cfg->dsc_version_minor == 2) | |
2076 | vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? | |
2077 | DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; | |
2078 | else | |
2079 | vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? | |
2080 | DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; | |
2081 | ||
2082 | vdsc_cfg->block_pred_enable = | |
2083 | intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & | |
2084 | DP_DSC_BLK_PREDICTION_IS_SUPPORTED; | |
2085 | ||
2086 | return drm_dsc_compute_rc_parameters(vdsc_cfg); | |
2087 | } | |
2088 | ||
204474a6 LP |
2089 | static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
2090 | struct intel_crtc_state *pipe_config, | |
2091 | struct drm_connector_state *conn_state, | |
2092 | struct link_config_limits *limits) | |
a4a15777 MN |
2093 | { |
2094 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2095 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
1326a92c | 2096 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
a4a15777 MN |
2097 | u8 dsc_max_bpc; |
2098 | int pipe_bpp; | |
204474a6 | 2099 | int ret; |
a4a15777 | 2100 | |
6fd3134a VS |
2101 | pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && |
2102 | intel_dp_supports_fec(intel_dp, pipe_config); | |
2103 | ||
a4a15777 | 2104 | if (!intel_dp_supports_dsc(intel_dp, pipe_config)) |
204474a6 | 2105 | return -EINVAL; |
a4a15777 | 2106 | |
cee508a0 AS |
2107 | /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ |
2108 | if (INTEL_GEN(dev_priv) >= 12) | |
2109 | dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); | |
2110 | else | |
2111 | dsc_max_bpc = min_t(u8, 10, | |
2112 | conn_state->max_requested_bpc); | |
a4a15777 MN |
2113 | |
2114 | pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); | |
cee508a0 AS |
2115 | |
2116 | /* Min Input BPC for ICL+ is 8 */ | |
2117 | if (pipe_bpp < 8 * 3) { | |
a4a15777 | 2118 | DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); |
204474a6 | 2119 | return -EINVAL; |
a4a15777 MN |
2120 | } |
2121 | ||
2122 | /* | |
2123 | * For now enable DSC for max bpp, max link rate, max lane count. | |
2124 | * Optimize this later for the minimum possible link rate/lane count | |
2125 | * with DSC enabled for the requested mode. | |
2126 | */ | |
2127 | pipe_config->pipe_bpp = pipe_bpp; | |
2128 | pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; | |
2129 | pipe_config->lane_count = limits->max_lane_count; | |
2130 | ||
2131 | if (intel_dp_is_edp(intel_dp)) { | |
010663a6 | 2132 | pipe_config->dsc.compressed_bpp = |
a4a15777 MN |
2133 | min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, |
2134 | pipe_config->pipe_bpp); | |
010663a6 | 2135 | pipe_config->dsc.slice_count = |
a4a15777 MN |
2136 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
2137 | true); | |
2138 | } else { | |
2139 | u16 dsc_max_output_bpp; | |
2140 | u8 dsc_dp_slice_count; | |
2141 | ||
2142 | dsc_max_output_bpp = | |
45d3c5cd MR |
2143 | intel_dp_dsc_get_output_bpp(dev_priv, |
2144 | pipe_config->port_clock, | |
a4a15777 MN |
2145 | pipe_config->lane_count, |
2146 | adjusted_mode->crtc_clock, | |
2147 | adjusted_mode->crtc_hdisplay); | |
2148 | dsc_dp_slice_count = | |
2149 | intel_dp_dsc_get_slice_count(intel_dp, | |
2150 | adjusted_mode->crtc_clock, | |
2151 | adjusted_mode->crtc_hdisplay); | |
2152 | if (!dsc_max_output_bpp || !dsc_dp_slice_count) { | |
2153 | DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); | |
204474a6 | 2154 | return -EINVAL; |
a4a15777 | 2155 | } |
010663a6 | 2156 | pipe_config->dsc.compressed_bpp = min_t(u16, |
a4a15777 MN |
2157 | dsc_max_output_bpp >> 4, |
2158 | pipe_config->pipe_bpp); | |
010663a6 | 2159 | pipe_config->dsc.slice_count = dsc_dp_slice_count; |
a4a15777 MN |
2160 | } |
2161 | /* | |
2162 | * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate | |
2163 | * is greater than the maximum Cdclock and if slice count is even | |
2164 | * then we need to use 2 VDSC instances. | |
2165 | */ | |
2166 | if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { | |
010663a6 JN |
2167 | if (pipe_config->dsc.slice_count > 1) { |
2168 | pipe_config->dsc.dsc_split = true; | |
a4a15777 MN |
2169 | } else { |
2170 | DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); | |
204474a6 | 2171 | return -EINVAL; |
a4a15777 MN |
2172 | } |
2173 | } | |
204474a6 | 2174 | |
7a7b5be9 | 2175 | ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); |
204474a6 | 2176 | if (ret < 0) { |
168243c1 GS |
2177 | DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " |
2178 | "Compressed BPP = %d\n", | |
2179 | pipe_config->pipe_bpp, | |
010663a6 | 2180 | pipe_config->dsc.compressed_bpp); |
204474a6 | 2181 | return ret; |
168243c1 | 2182 | } |
204474a6 | 2183 | |
010663a6 | 2184 | pipe_config->dsc.compression_enable = true; |
a4a15777 MN |
2185 | DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " |
2186 | "Compressed Bpp = %d Slice Count = %d\n", | |
2187 | pipe_config->pipe_bpp, | |
010663a6 JN |
2188 | pipe_config->dsc.compressed_bpp, |
2189 | pipe_config->dsc.slice_count); | |
a4a15777 | 2190 | |
204474a6 | 2191 | return 0; |
a4a15777 MN |
2192 | } |
2193 | ||
4e2056e0 VS |
2194 | int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state) |
2195 | { | |
2196 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) | |
2197 | return 6 * 3; | |
2198 | else | |
2199 | return 8 * 3; | |
2200 | } | |
2201 | ||
204474a6 | 2202 | static int |
981a63eb | 2203 | intel_dp_compute_link_config(struct intel_encoder *encoder, |
a4a15777 MN |
2204 | struct intel_crtc_state *pipe_config, |
2205 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 2206 | { |
1326a92c | 2207 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
b7d02c3a | 2208 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7c2781e4 | 2209 | struct link_config_limits limits; |
94ca719e | 2210 | int common_len; |
204474a6 | 2211 | int ret; |
7c2781e4 | 2212 | |
975ee5fc | 2213 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
e6c0c64a | 2214 | intel_dp->max_link_rate); |
a8f3ef61 SJ |
2215 | |
2216 | /* No common link rates between source and sink */ | |
94ca719e | 2217 | WARN_ON(common_len <= 0); |
a8f3ef61 | 2218 | |
7c2781e4 JN |
2219 | limits.min_clock = 0; |
2220 | limits.max_clock = common_len - 1; | |
2221 | ||
2222 | limits.min_lane_count = 1; | |
2223 | limits.max_lane_count = intel_dp_max_lane_count(intel_dp); | |
2224 | ||
4e2056e0 | 2225 | limits.min_bpp = intel_dp_min_bpp(pipe_config); |
7c2781e4 | 2226 | limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
a4fc5ed6 | 2227 | |
f11cb1c1 | 2228 | if (intel_dp_is_edp(intel_dp)) { |
344c5bbc JN |
2229 | /* |
2230 | * Use the maximum clock and number of lanes the eDP panel | |
f11cb1c1 JN |
2231 | * advertizes being capable of. The panels are generally |
2232 | * designed to support only a single clock and lane | |
2233 | * configuration, and typically these values correspond to the | |
2234 | * native resolution of the panel. | |
344c5bbc | 2235 | */ |
7c2781e4 JN |
2236 | limits.min_lane_count = limits.max_lane_count; |
2237 | limits.min_clock = limits.max_clock; | |
7984211e | 2238 | } |
657445fe | 2239 | |
a4971453 JN |
2240 | intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |
2241 | ||
7c2781e4 JN |
2242 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
2243 | "max rate %d max bpp %d pixel clock %iKHz\n", | |
2244 | limits.max_lane_count, | |
2245 | intel_dp->common_rates[limits.max_clock], | |
2246 | limits.max_bpp, adjusted_mode->crtc_clock); | |
2247 | ||
f11cb1c1 JN |
2248 | /* |
2249 | * Optimize for slow and wide. This is the place to add alternative | |
2250 | * optimization policy. | |
2251 | */ | |
2252 | ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); | |
a4a15777 MN |
2253 | |
2254 | /* enable compression if the mode doesn't fit available BW */ | |
e845f099 | 2255 | DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en); |
204474a6 LP |
2256 | if (ret || intel_dp->force_dsc_en) { |
2257 | ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, | |
2258 | conn_state, &limits); | |
2259 | if (ret < 0) | |
2260 | return ret; | |
7769db58 | 2261 | } |
981a63eb | 2262 | |
010663a6 | 2263 | if (pipe_config->dsc.compression_enable) { |
a4a15777 MN |
2264 | DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", |
2265 | pipe_config->lane_count, pipe_config->port_clock, | |
2266 | pipe_config->pipe_bpp, | |
010663a6 | 2267 | pipe_config->dsc.compressed_bpp); |
a4a15777 MN |
2268 | |
2269 | DRM_DEBUG_KMS("DP link rate required %i available %i\n", | |
2270 | intel_dp_link_required(adjusted_mode->crtc_clock, | |
010663a6 | 2271 | pipe_config->dsc.compressed_bpp), |
a4a15777 MN |
2272 | intel_dp_max_data_rate(pipe_config->port_clock, |
2273 | pipe_config->lane_count)); | |
2274 | } else { | |
2275 | DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", | |
2276 | pipe_config->lane_count, pipe_config->port_clock, | |
2277 | pipe_config->pipe_bpp); | |
2278 | ||
2279 | DRM_DEBUG_KMS("DP link rate required %i available %i\n", | |
2280 | intel_dp_link_required(adjusted_mode->crtc_clock, | |
2281 | pipe_config->pipe_bpp), | |
2282 | intel_dp_max_data_rate(pipe_config->port_clock, | |
2283 | pipe_config->lane_count)); | |
2284 | } | |
204474a6 | 2285 | return 0; |
981a63eb JN |
2286 | } |
2287 | ||
8e9d645c GM |
2288 | static int |
2289 | intel_dp_ycbcr420_config(struct intel_dp *intel_dp, | |
2290 | struct drm_connector *connector, | |
2291 | struct intel_crtc_state *crtc_state) | |
2292 | { | |
2293 | const struct drm_display_info *info = &connector->display_info; | |
2294 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 2295 | &crtc_state->hw.adjusted_mode; |
2225f3c6 | 2296 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
8e9d645c GM |
2297 | int ret; |
2298 | ||
2299 | if (!drm_mode_is_420_only(info, adjusted_mode) || | |
2300 | !intel_dp_get_colorimetry_status(intel_dp) || | |
2301 | !connector->ycbcr_420_allowed) | |
2302 | return 0; | |
2303 | ||
2304 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; | |
2305 | ||
2306 | /* YCBCR 420 output conversion needs a scaler */ | |
2307 | ret = skl_update_scaler_crtc(crtc_state); | |
2308 | if (ret) { | |
2309 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
2310 | return ret; | |
2311 | } | |
2312 | ||
2313 | intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN); | |
2314 | ||
2315 | return 0; | |
2316 | } | |
2317 | ||
37aa52bf VS |
2318 | bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
2319 | const struct drm_connector_state *conn_state) | |
2320 | { | |
2321 | const struct intel_digital_connector_state *intel_conn_state = | |
2322 | to_intel_digital_connector_state(conn_state); | |
2323 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 2324 | &crtc_state->hw.adjusted_mode; |
37aa52bf | 2325 | |
cae154fc VS |
2326 | /* |
2327 | * Our YCbCr output is always limited range. | |
2328 | * crtc_state->limited_color_range only applies to RGB, | |
2329 | * and it must never be set for YCbCr or we risk setting | |
2330 | * some conflicting bits in PIPECONF which will mess up | |
2331 | * the colors on the monitor. | |
2332 | */ | |
2333 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
2334 | return false; | |
2335 | ||
37aa52bf VS |
2336 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
2337 | /* | |
2338 | * See: | |
2339 | * CEA-861-E - 5.1 Default Encoding Parameters | |
2340 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
2341 | */ | |
2342 | return crtc_state->pipe_bpp != 18 && | |
2343 | drm_default_rgb_quant_range(adjusted_mode) == | |
2344 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
2345 | } else { | |
2346 | return intel_conn_state->broadcast_rgb == | |
2347 | INTEL_BROADCAST_RGB_LIMITED; | |
2348 | } | |
2349 | } | |
2350 | ||
07130981 KV |
2351 | static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, |
2352 | enum port port) | |
2353 | { | |
2354 | if (IS_G4X(dev_priv)) | |
2355 | return false; | |
2356 | if (INTEL_GEN(dev_priv) < 12 && port == PORT_A) | |
2357 | return false; | |
2358 | ||
2359 | return true; | |
2360 | } | |
2361 | ||
204474a6 | 2362 | int |
981a63eb JN |
2363 | intel_dp_compute_config(struct intel_encoder *encoder, |
2364 | struct intel_crtc_state *pipe_config, | |
2365 | struct drm_connector_state *conn_state) | |
2366 | { | |
2367 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1326a92c | 2368 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
b7d02c3a VS |
2369 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2370 | struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); | |
981a63eb | 2371 | enum port port = encoder->port; |
2225f3c6 | 2372 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); |
981a63eb JN |
2373 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
2374 | struct intel_digital_connector_state *intel_conn_state = | |
2375 | to_intel_digital_connector_state(conn_state); | |
53ca2edc LS |
2376 | bool constant_n = drm_dp_has_quirk(&intel_dp->desc, |
2377 | DP_DPCD_QUIRK_CONSTANT_N); | |
8e9d645c | 2378 | int ret = 0, output_bpp; |
981a63eb JN |
2379 | |
2380 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) | |
2381 | pipe_config->has_pch_encoder = true; | |
2382 | ||
d9facae6 | 2383 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
0c06fa15 | 2384 | |
668b6c17 SS |
2385 | if (lspcon->active) |
2386 | lspcon_ycbcr420_config(&intel_connector->base, pipe_config); | |
8e9d645c GM |
2387 | else |
2388 | ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base, | |
2389 | pipe_config); | |
2390 | ||
2391 | if (ret) | |
2392 | return ret; | |
668b6c17 | 2393 | |
981a63eb | 2394 | pipe_config->has_drrs = false; |
07130981 | 2395 | if (!intel_dp_port_has_audio(dev_priv, port)) |
981a63eb JN |
2396 | pipe_config->has_audio = false; |
2397 | else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2398 | pipe_config->has_audio = intel_dp->has_audio; | |
2399 | else | |
2400 | pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2401 | ||
2402 | if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { | |
d93fa1b4 JN |
2403 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
2404 | adjusted_mode); | |
981a63eb JN |
2405 | |
2406 | if (INTEL_GEN(dev_priv) >= 9) { | |
981a63eb JN |
2407 | ret = skl_update_scaler_crtc(pipe_config); |
2408 | if (ret) | |
2409 | return ret; | |
2410 | } | |
2411 | ||
b2ae318a | 2412 | if (HAS_GMCH(dev_priv)) |
981a63eb JN |
2413 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
2414 | conn_state->scaling_mode); | |
2415 | else | |
2416 | intel_pch_panel_fitting(intel_crtc, pipe_config, | |
2417 | conn_state->scaling_mode); | |
2418 | } | |
2419 | ||
e4dd27aa | 2420 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2421 | return -EINVAL; |
e4dd27aa | 2422 | |
b2ae318a | 2423 | if (HAS_GMCH(dev_priv) && |
981a63eb | 2424 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
204474a6 | 2425 | return -EINVAL; |
981a63eb JN |
2426 | |
2427 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
204474a6 | 2428 | return -EINVAL; |
981a63eb | 2429 | |
98c93394 VS |
2430 | if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) |
2431 | return -EINVAL; | |
2432 | ||
204474a6 LP |
2433 | ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); |
2434 | if (ret < 0) | |
2435 | return ret; | |
981a63eb | 2436 | |
37aa52bf VS |
2437 | pipe_config->limited_color_range = |
2438 | intel_dp_limited_color_range(pipe_config, conn_state); | |
55bc60db | 2439 | |
010663a6 JN |
2440 | if (pipe_config->dsc.compression_enable) |
2441 | output_bpp = pipe_config->dsc.compressed_bpp; | |
a4a15777 | 2442 | else |
16668f48 | 2443 | output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); |
aefa95ba VS |
2444 | |
2445 | intel_link_compute_m_n(output_bpp, | |
2446 | pipe_config->lane_count, | |
2447 | adjusted_mode->crtc_clock, | |
2448 | pipe_config->port_clock, | |
2449 | &pipe_config->dp_m_n, | |
ed06efb8 | 2450 | constant_n, pipe_config->fec_enable); |
9d1a455b | 2451 | |
439d7ac0 | 2452 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 2453 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 2454 | pipe_config->has_drrs = true; |
aefa95ba | 2455 | intel_link_compute_m_n(output_bpp, |
981a63eb JN |
2456 | pipe_config->lane_count, |
2457 | intel_connector->panel.downclock_mode->clock, | |
2458 | pipe_config->port_clock, | |
2459 | &pipe_config->dp_m2_n2, | |
ed06efb8 | 2460 | constant_n, pipe_config->fec_enable); |
439d7ac0 PB |
2461 | } |
2462 | ||
4f8036a2 | 2463 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 2464 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 2465 | |
4d90f2d5 VS |
2466 | intel_psr_compute_config(intel_dp, pipe_config); |
2467 | ||
204474a6 | 2468 | return 0; |
a4fc5ed6 KP |
2469 | } |
2470 | ||
901c2daf | 2471 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
830de422 | 2472 | int link_rate, u8 lane_count, |
dfa10480 | 2473 | bool link_mst) |
901c2daf | 2474 | { |
edb2e530 | 2475 | intel_dp->link_trained = false; |
dfa10480 ACO |
2476 | intel_dp->link_rate = link_rate; |
2477 | intel_dp->lane_count = lane_count; | |
2478 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
2479 | } |
2480 | ||
85cb48a1 | 2481 | static void intel_dp_prepare(struct intel_encoder *encoder, |
5f88a9c6 | 2482 | const struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 2483 | { |
2f773477 | 2484 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 2485 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
8f4f2797 | 2486 | enum port port = encoder->port; |
2225f3c6 | 2487 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
1326a92c | 2488 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
a4fc5ed6 | 2489 | |
dfa10480 ACO |
2490 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
2491 | pipe_config->lane_count, | |
2492 | intel_crtc_has_type(pipe_config, | |
2493 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 2494 | |
4444df6e LDM |
2495 | intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port); |
2496 | intel_dp->regs.dp_tp_status = DP_TP_STATUS(port); | |
2497 | ||
417e822d | 2498 | /* |
1a2eb460 | 2499 | * There are four kinds of DP registers: |
417e822d KP |
2500 | * |
2501 | * IBX PCH | |
1a2eb460 KP |
2502 | * SNB CPU |
2503 | * IVB CPU | |
417e822d KP |
2504 | * CPT PCH |
2505 | * | |
2506 | * IBX PCH and CPU are the same for almost everything, | |
2507 | * except that the CPU DP PLL is configured in this | |
2508 | * register | |
2509 | * | |
2510 | * CPT PCH is quite different, having many bits moved | |
2511 | * to the TRANS_DP_CTL register instead. That | |
9eae5e27 | 2512 | * configuration happens (oddly) in ilk_pch_enable |
417e822d | 2513 | */ |
9c9e7927 | 2514 | |
417e822d KP |
2515 | /* Preserve the BIOS-computed detected bit. This is |
2516 | * supposed to be read-only. | |
2517 | */ | |
2518 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 2519 | |
417e822d | 2520 | /* Handle DP bits in common between all three register formats */ |
417e822d | 2521 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 2522 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 2523 | |
417e822d | 2524 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 2525 | |
b752e995 | 2526 | if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
2527 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
2528 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
2529 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
2530 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
2531 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
2532 | ||
6aba5b6c | 2533 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
2534 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2535 | ||
59b74c49 | 2536 | intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); |
6e266956 | 2537 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
2538 | u32 trans_dp; |
2539 | ||
39e5fa88 | 2540 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
2541 | |
2542 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
2543 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2544 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
2545 | else | |
2546 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
2547 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 2548 | } else { |
c99f53f7 | 2549 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 2550 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
2551 | |
2552 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
2553 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
2554 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
2555 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
2556 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
2557 | ||
6aba5b6c | 2558 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
2559 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2560 | ||
920a14b2 | 2561 | if (IS_CHERRYVIEW(dev_priv)) |
59b74c49 VS |
2562 | intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); |
2563 | else | |
2564 | intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); | |
32f9d658 | 2565 | } |
a4fc5ed6 KP |
2566 | } |
2567 | ||
ffd6749d PZ |
2568 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
2569 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 2570 | |
1a5ef5b7 PZ |
2571 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
2572 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 2573 | |
ffd6749d PZ |
2574 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
2575 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 2576 | |
46bd8383 | 2577 | static void intel_pps_verify_state(struct intel_dp *intel_dp); |
de9c1b6b | 2578 | |
4be73780 | 2579 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
2580 | u32 mask, |
2581 | u32 value) | |
bd943159 | 2582 | { |
de25eb7f | 2583 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
f0f59a00 | 2584 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 2585 | |
e39b999a VS |
2586 | lockdep_assert_held(&dev_priv->pps_mutex); |
2587 | ||
46bd8383 | 2588 | intel_pps_verify_state(intel_dp); |
de9c1b6b | 2589 | |
bf13e81b JN |
2590 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2591 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 2592 | |
99ea7127 | 2593 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
2594 | mask, value, |
2595 | I915_READ(pp_stat_reg), | |
2596 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 2597 | |
4cb3b44d DCS |
2598 | if (intel_de_wait_for_register(dev_priv, pp_stat_reg, |
2599 | mask, value, 5000)) | |
99ea7127 | 2600 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
2601 | I915_READ(pp_stat_reg), |
2602 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
2603 | |
2604 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 2605 | } |
32ce697c | 2606 | |
4be73780 | 2607 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
2608 | { |
2609 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 2610 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
2611 | } |
2612 | ||
4be73780 | 2613 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
2614 | { |
2615 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 2616 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
2617 | } |
2618 | ||
4be73780 | 2619 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 2620 | { |
d28d4731 AK |
2621 | ktime_t panel_power_on_time; |
2622 | s64 panel_power_off_duration; | |
2623 | ||
99ea7127 | 2624 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 2625 | |
d28d4731 AK |
2626 | /* take the difference of currrent time and panel power off time |
2627 | * and then make panel wait for t11_t12 if needed. */ | |
2628 | panel_power_on_time = ktime_get_boottime(); | |
2629 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
2630 | ||
dce56b3c PZ |
2631 | /* When we disable the VDD override bit last we have to do the manual |
2632 | * wait. */ | |
d28d4731 AK |
2633 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
2634 | wait_remaining_ms_from_jiffies(jiffies, | |
2635 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 2636 | |
4be73780 | 2637 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
2638 | } |
2639 | ||
4be73780 | 2640 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
2641 | { |
2642 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
2643 | intel_dp->backlight_on_delay); | |
2644 | } | |
2645 | ||
4be73780 | 2646 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
2647 | { |
2648 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
2649 | intel_dp->backlight_off_delay); | |
2650 | } | |
99ea7127 | 2651 | |
832dd3c1 KP |
2652 | /* Read the current pp_control value, unlocking the register if it |
2653 | * is locked | |
2654 | */ | |
2655 | ||
9eae5e27 | 2656 | static u32 ilk_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 2657 | { |
de25eb7f | 2658 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
453c5420 | 2659 | u32 control; |
832dd3c1 | 2660 | |
e39b999a VS |
2661 | lockdep_assert_held(&dev_priv->pps_mutex); |
2662 | ||
bf13e81b | 2663 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
2664 | if (WARN_ON(!HAS_DDI(dev_priv) && |
2665 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
2666 | control &= ~PANEL_UNLOCK_MASK; |
2667 | control |= PANEL_UNLOCK_REGS; | |
2668 | } | |
832dd3c1 | 2669 | return control; |
bd943159 KP |
2670 | } |
2671 | ||
951468f3 VS |
2672 | /* |
2673 | * Must be paired with edp_panel_vdd_off(). | |
2674 | * Must hold pps_mutex around the whole on/off sequence. | |
2675 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2676 | */ | |
1e0560e0 | 2677 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2678 | { |
de25eb7f | 2679 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4e6e1a54 | 2680 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5d613501 | 2681 | u32 pp; |
f0f59a00 | 2682 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2683 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2684 | |
e39b999a VS |
2685 | lockdep_assert_held(&dev_priv->pps_mutex); |
2686 | ||
1853a9da | 2687 | if (!intel_dp_is_edp(intel_dp)) |
adddaaf4 | 2688 | return false; |
bd943159 | 2689 | |
2c623c11 | 2690 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2691 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2692 | |
4be73780 | 2693 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2694 | return need_to_disable; |
b0665d57 | 2695 | |
337837ac ID |
2696 | intel_display_power_get(dev_priv, |
2697 | intel_aux_power_domain(intel_dig_port)); | |
e9cb81a2 | 2698 | |
66a990dd VS |
2699 | DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n", |
2700 | intel_dig_port->base.base.base.id, | |
2701 | intel_dig_port->base.base.name); | |
bd943159 | 2702 | |
4be73780 DV |
2703 | if (!edp_have_panel_power(intel_dp)) |
2704 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 2705 | |
9eae5e27 | 2706 | pp = ilk_get_pp_control(intel_dp); |
5d613501 | 2707 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 2708 | |
bf13e81b JN |
2709 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2710 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
2711 | |
2712 | I915_WRITE(pp_ctrl_reg, pp); | |
2713 | POSTING_READ(pp_ctrl_reg); | |
2714 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2715 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
2716 | /* |
2717 | * If the panel wasn't on, delay before accessing aux channel | |
2718 | */ | |
4be73780 | 2719 | if (!edp_have_panel_power(intel_dp)) { |
66a990dd VS |
2720 | DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n", |
2721 | intel_dig_port->base.base.base.id, | |
2722 | intel_dig_port->base.base.name); | |
f01eca2e | 2723 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2724 | } |
adddaaf4 JN |
2725 | |
2726 | return need_to_disable; | |
2727 | } | |
2728 | ||
951468f3 VS |
2729 | /* |
2730 | * Must be paired with intel_edp_panel_vdd_off() or | |
2731 | * intel_edp_panel_off(). | |
2732 | * Nested calls to these functions are not allowed since | |
2733 | * we drop the lock. Caller must use some higher level | |
2734 | * locking to prevent nested calls from other threads. | |
2735 | */ | |
b80d6c78 | 2736 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2737 | { |
69d93820 | 2738 | intel_wakeref_t wakeref; |
c695b6b6 | 2739 | bool vdd; |
adddaaf4 | 2740 | |
1853a9da | 2741 | if (!intel_dp_is_edp(intel_dp)) |
c695b6b6 VS |
2742 | return; |
2743 | ||
69d93820 CW |
2744 | vdd = false; |
2745 | with_pps_lock(intel_dp, wakeref) | |
2746 | vdd = edp_panel_vdd_on(intel_dp); | |
66a990dd VS |
2747 | I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n", |
2748 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
2749 | dp_to_dig_port(intel_dp)->base.base.name); | |
5d613501 JB |
2750 | } |
2751 | ||
4be73780 | 2752 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2753 | { |
de25eb7f | 2754 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
be2c9196 VS |
2755 | struct intel_digital_port *intel_dig_port = |
2756 | dp_to_dig_port(intel_dp); | |
5d613501 | 2757 | u32 pp; |
f0f59a00 | 2758 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2759 | |
e39b999a | 2760 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2761 | |
15e899a0 | 2762 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2763 | |
15e899a0 | 2764 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2765 | return; |
b0665d57 | 2766 | |
66a990dd VS |
2767 | DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n", |
2768 | intel_dig_port->base.base.base.id, | |
2769 | intel_dig_port->base.base.name); | |
bd943159 | 2770 | |
9eae5e27 | 2771 | pp = ilk_get_pp_control(intel_dp); |
be2c9196 | 2772 | pp &= ~EDP_FORCE_VDD; |
453c5420 | 2773 | |
be2c9196 VS |
2774 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2775 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2776 | |
be2c9196 VS |
2777 | I915_WRITE(pp_ctrl_reg, pp); |
2778 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2779 | |
be2c9196 VS |
2780 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2781 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2782 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2783 | |
5a162e22 | 2784 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2785 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2786 | |
0e6e0be4 CW |
2787 | intel_display_power_put_unchecked(dev_priv, |
2788 | intel_aux_power_domain(intel_dig_port)); | |
bd943159 | 2789 | } |
5d613501 | 2790 | |
4be73780 | 2791 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 | 2792 | { |
69d93820 CW |
2793 | struct intel_dp *intel_dp = |
2794 | container_of(to_delayed_work(__work), | |
2795 | struct intel_dp, panel_vdd_work); | |
2796 | intel_wakeref_t wakeref; | |
bd943159 | 2797 | |
69d93820 CW |
2798 | with_pps_lock(intel_dp, wakeref) { |
2799 | if (!intel_dp->want_panel_vdd) | |
2800 | edp_panel_vdd_off_sync(intel_dp); | |
2801 | } | |
bd943159 KP |
2802 | } |
2803 | ||
aba86890 ID |
2804 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2805 | { | |
2806 | unsigned long delay; | |
2807 | ||
2808 | /* | |
2809 | * Queue the timer to fire a long time from now (relative to the power | |
2810 | * down delay) to keep the panel power up across a sequence of | |
2811 | * operations. | |
2812 | */ | |
2813 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2814 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2815 | } | |
2816 | ||
951468f3 VS |
2817 | /* |
2818 | * Must be paired with edp_panel_vdd_on(). | |
2819 | * Must hold pps_mutex around the whole on/off sequence. | |
2820 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2821 | */ | |
4be73780 | 2822 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2823 | { |
de25eb7f | 2824 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e39b999a VS |
2825 | |
2826 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2827 | ||
1853a9da | 2828 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2829 | return; |
5d613501 | 2830 | |
66a990dd VS |
2831 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on", |
2832 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
2833 | dp_to_dig_port(intel_dp)->base.base.name); | |
f2e8b18a | 2834 | |
bd943159 KP |
2835 | intel_dp->want_panel_vdd = false; |
2836 | ||
aba86890 | 2837 | if (sync) |
4be73780 | 2838 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2839 | else |
2840 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2841 | } |
2842 | ||
9f0fb5be | 2843 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2844 | { |
de25eb7f | 2845 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
99ea7127 | 2846 | u32 pp; |
f0f59a00 | 2847 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2848 | |
9f0fb5be VS |
2849 | lockdep_assert_held(&dev_priv->pps_mutex); |
2850 | ||
1853a9da | 2851 | if (!intel_dp_is_edp(intel_dp)) |
bd943159 | 2852 | return; |
99ea7127 | 2853 | |
66a990dd VS |
2854 | DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n", |
2855 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
2856 | dp_to_dig_port(intel_dp)->base.base.name); | |
e39b999a | 2857 | |
e7a89ace | 2858 | if (WARN(edp_have_panel_power(intel_dp), |
66a990dd VS |
2859 | "[ENCODER:%d:%s] panel power already on\n", |
2860 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
2861 | dp_to_dig_port(intel_dp)->base.base.name)) | |
9f0fb5be | 2862 | return; |
9934c132 | 2863 | |
4be73780 | 2864 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2865 | |
bf13e81b | 2866 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
9eae5e27 | 2867 | pp = ilk_get_pp_control(intel_dp); |
cf819eff | 2868 | if (IS_GEN(dev_priv, 5)) { |
05ce1a49 KP |
2869 | /* ILK workaround: disable reset around power sequence */ |
2870 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2871 | I915_WRITE(pp_ctrl_reg, pp); |
2872 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2873 | } |
37c6c9b0 | 2874 | |
5a162e22 | 2875 | pp |= PANEL_POWER_ON; |
cf819eff | 2876 | if (!IS_GEN(dev_priv, 5)) |
99ea7127 KP |
2877 | pp |= PANEL_POWER_RESET; |
2878 | ||
453c5420 JB |
2879 | I915_WRITE(pp_ctrl_reg, pp); |
2880 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2881 | |
4be73780 | 2882 | wait_panel_on(intel_dp); |
dce56b3c | 2883 | intel_dp->last_power_on = jiffies; |
9934c132 | 2884 | |
cf819eff | 2885 | if (IS_GEN(dev_priv, 5)) { |
05ce1a49 | 2886 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2887 | I915_WRITE(pp_ctrl_reg, pp); |
2888 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2889 | } |
9f0fb5be | 2890 | } |
e39b999a | 2891 | |
9f0fb5be VS |
2892 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2893 | { | |
69d93820 CW |
2894 | intel_wakeref_t wakeref; |
2895 | ||
1853a9da | 2896 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be VS |
2897 | return; |
2898 | ||
69d93820 CW |
2899 | with_pps_lock(intel_dp, wakeref) |
2900 | edp_panel_on(intel_dp); | |
9934c132 JB |
2901 | } |
2902 | ||
9f0fb5be VS |
2903 | |
2904 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2905 | { |
de25eb7f | 2906 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
337837ac | 2907 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
99ea7127 | 2908 | u32 pp; |
f0f59a00 | 2909 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2910 | |
9f0fb5be VS |
2911 | lockdep_assert_held(&dev_priv->pps_mutex); |
2912 | ||
1853a9da | 2913 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2914 | return; |
37c6c9b0 | 2915 | |
66a990dd VS |
2916 | DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n", |
2917 | dig_port->base.base.base.id, dig_port->base.base.name); | |
37c6c9b0 | 2918 | |
66a990dd VS |
2919 | WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n", |
2920 | dig_port->base.base.base.id, dig_port->base.base.name); | |
24f3e092 | 2921 | |
9eae5e27 | 2922 | pp = ilk_get_pp_control(intel_dp); |
35a38556 DV |
2923 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2924 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2925 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2926 | EDP_BLC_ENABLE); |
453c5420 | 2927 | |
bf13e81b | 2928 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2929 | |
849e39f5 PZ |
2930 | intel_dp->want_panel_vdd = false; |
2931 | ||
453c5420 JB |
2932 | I915_WRITE(pp_ctrl_reg, pp); |
2933 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2934 | |
4be73780 | 2935 | wait_panel_off(intel_dp); |
d7ba25bd | 2936 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
849e39f5 PZ |
2937 | |
2938 | /* We got a reference when we enabled the VDD. */ | |
0e6e0be4 | 2939 | intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port)); |
9f0fb5be | 2940 | } |
e39b999a | 2941 | |
9f0fb5be VS |
2942 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2943 | { | |
69d93820 CW |
2944 | intel_wakeref_t wakeref; |
2945 | ||
1853a9da | 2946 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be | 2947 | return; |
e39b999a | 2948 | |
69d93820 CW |
2949 | with_pps_lock(intel_dp, wakeref) |
2950 | edp_panel_off(intel_dp); | |
9934c132 JB |
2951 | } |
2952 | ||
1250d107 JN |
2953 | /* Enable backlight in the panel power control. */ |
2954 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2955 | { |
de25eb7f | 2956 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 2957 | intel_wakeref_t wakeref; |
32f9d658 | 2958 | |
01cb9ea6 JB |
2959 | /* |
2960 | * If we enable the backlight right away following a panel power | |
2961 | * on, we may see slight flicker as the panel syncs with the eDP | |
2962 | * link. So delay a bit to make sure the image is solid before | |
2963 | * allowing it to appear. | |
2964 | */ | |
4be73780 | 2965 | wait_backlight_on(intel_dp); |
e39b999a | 2966 | |
69d93820 CW |
2967 | with_pps_lock(intel_dp, wakeref) { |
2968 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
2969 | u32 pp; | |
453c5420 | 2970 | |
9eae5e27 | 2971 | pp = ilk_get_pp_control(intel_dp); |
69d93820 | 2972 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2973 | |
69d93820 CW |
2974 | I915_WRITE(pp_ctrl_reg, pp); |
2975 | POSTING_READ(pp_ctrl_reg); | |
2976 | } | |
32f9d658 ZW |
2977 | } |
2978 | ||
1250d107 | 2979 | /* Enable backlight PWM and backlight PP control. */ |
b037d58f ML |
2980 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
2981 | const struct drm_connector_state *conn_state) | |
1250d107 | 2982 | { |
b7d02c3a | 2983 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); |
b037d58f | 2984 | |
1853a9da | 2985 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2986 | return; |
2987 | ||
2988 | DRM_DEBUG_KMS("\n"); | |
2989 | ||
b037d58f | 2990 | intel_panel_enable_backlight(crtc_state, conn_state); |
1250d107 JN |
2991 | _intel_edp_backlight_on(intel_dp); |
2992 | } | |
2993 | ||
2994 | /* Disable backlight in the panel power control. */ | |
2995 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2996 | { |
de25eb7f | 2997 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 2998 | intel_wakeref_t wakeref; |
32f9d658 | 2999 | |
1853a9da | 3000 | if (!intel_dp_is_edp(intel_dp)) |
f01eca2e KP |
3001 | return; |
3002 | ||
69d93820 CW |
3003 | with_pps_lock(intel_dp, wakeref) { |
3004 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
3005 | u32 pp; | |
e39b999a | 3006 | |
9eae5e27 | 3007 | pp = ilk_get_pp_control(intel_dp); |
69d93820 | 3008 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 3009 | |
69d93820 CW |
3010 | I915_WRITE(pp_ctrl_reg, pp); |
3011 | POSTING_READ(pp_ctrl_reg); | |
3012 | } | |
e39b999a VS |
3013 | |
3014 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 3015 | edp_wait_backlight_off(intel_dp); |
1250d107 | 3016 | } |
f7d2323c | 3017 | |
1250d107 | 3018 | /* Disable backlight PP control and backlight PWM. */ |
b037d58f | 3019 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
1250d107 | 3020 | { |
b7d02c3a | 3021 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); |
b037d58f | 3022 | |
1853a9da | 3023 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
3024 | return; |
3025 | ||
3026 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 3027 | |
1250d107 | 3028 | _intel_edp_backlight_off(intel_dp); |
b037d58f | 3029 | intel_panel_disable_backlight(old_conn_state); |
32f9d658 | 3030 | } |
a4fc5ed6 | 3031 | |
73580fb7 JN |
3032 | /* |
3033 | * Hook for controlling the panel power control backlight through the bl_power | |
3034 | * sysfs attribute. Take care to handle multiple calls. | |
3035 | */ | |
3036 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
3037 | bool enable) | |
3038 | { | |
43a6d19c | 3039 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
69d93820 | 3040 | intel_wakeref_t wakeref; |
e39b999a VS |
3041 | bool is_enabled; |
3042 | ||
69d93820 CW |
3043 | is_enabled = false; |
3044 | with_pps_lock(intel_dp, wakeref) | |
9eae5e27 | 3045 | is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
73580fb7 JN |
3046 | if (is_enabled == enable) |
3047 | return; | |
3048 | ||
23ba9373 JN |
3049 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
3050 | enable ? "enable" : "disable"); | |
73580fb7 JN |
3051 | |
3052 | if (enable) | |
3053 | _intel_edp_backlight_on(intel_dp); | |
3054 | else | |
3055 | _intel_edp_backlight_off(intel_dp); | |
3056 | } | |
3057 | ||
64e1077a VS |
3058 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
3059 | { | |
3060 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
3061 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
3062 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
3063 | ||
3064 | I915_STATE_WARN(cur_state != state, | |
66a990dd VS |
3065 | "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", |
3066 | dig_port->base.base.base.id, dig_port->base.base.name, | |
87ad3212 | 3067 | onoff(state), onoff(cur_state)); |
64e1077a VS |
3068 | } |
3069 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
3070 | ||
3071 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
3072 | { | |
3073 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
3074 | ||
3075 | I915_STATE_WARN(cur_state != state, | |
3076 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 3077 | onoff(state), onoff(cur_state)); |
64e1077a VS |
3078 | } |
3079 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
3080 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
3081 | ||
9eae5e27 LDM |
3082 | static void ilk_edp_pll_on(struct intel_dp *intel_dp, |
3083 | const struct intel_crtc_state *pipe_config) | |
d240f20f | 3084 | { |
2225f3c6 | 3085 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
64e1077a | 3086 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 3087 | |
5c34ba27 | 3088 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); |
64e1077a VS |
3089 | assert_dp_port_disabled(intel_dp); |
3090 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 3091 | |
abfce949 | 3092 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 3093 | pipe_config->port_clock); |
abfce949 VS |
3094 | |
3095 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
3096 | ||
85cb48a1 | 3097 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
3098 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
3099 | else | |
3100 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
3101 | ||
3102 | I915_WRITE(DP_A, intel_dp->DP); | |
3103 | POSTING_READ(DP_A); | |
3104 | udelay(500); | |
3105 | ||
6b23f3e8 VS |
3106 | /* |
3107 | * [DevILK] Work around required when enabling DP PLL | |
3108 | * while a pipe is enabled going to FDI: | |
3109 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
3110 | * 2. Program DP PLL enable | |
3111 | */ | |
cf819eff | 3112 | if (IS_GEN(dev_priv, 5)) |
0f0f74bc | 3113 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 3114 | |
0767935e | 3115 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 3116 | |
0767935e | 3117 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
3118 | POSTING_READ(DP_A); |
3119 | udelay(200); | |
d240f20f JB |
3120 | } |
3121 | ||
9eae5e27 LDM |
3122 | static void ilk_edp_pll_off(struct intel_dp *intel_dp, |
3123 | const struct intel_crtc_state *old_crtc_state) | |
d240f20f | 3124 | { |
2225f3c6 | 3125 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
64e1077a | 3126 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 3127 | |
5c34ba27 | 3128 | assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); |
64e1077a VS |
3129 | assert_dp_port_disabled(intel_dp); |
3130 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 3131 | |
abfce949 VS |
3132 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
3133 | ||
6fec7662 | 3134 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 3135 | |
6fec7662 | 3136 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 3137 | POSTING_READ(DP_A); |
d240f20f JB |
3138 | udelay(200); |
3139 | } | |
3140 | ||
857c416e VS |
3141 | static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) |
3142 | { | |
3143 | /* | |
3144 | * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus | |
3145 | * be capable of signalling downstream hpd with a long pulse. | |
3146 | * Whether or not that means D3 is safe to use is not clear, | |
3147 | * but let's assume so until proven otherwise. | |
3148 | * | |
3149 | * FIXME should really check all downstream ports... | |
3150 | */ | |
3151 | return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && | |
3152 | intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && | |
3153 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; | |
3154 | } | |
3155 | ||
2279298d GS |
3156 | void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, |
3157 | const struct intel_crtc_state *crtc_state, | |
3158 | bool enable) | |
3159 | { | |
3160 | int ret; | |
3161 | ||
010663a6 | 3162 | if (!crtc_state->dsc.compression_enable) |
2279298d GS |
3163 | return; |
3164 | ||
3165 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, | |
3166 | enable ? DP_DECOMPRESSION_EN : 0); | |
3167 | if (ret < 0) | |
3168 | DRM_DEBUG_KMS("Failed to %s sink decompression state\n", | |
3169 | enable ? "enable" : "disable"); | |
3170 | } | |
3171 | ||
c7ad3810 | 3172 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 3173 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
3174 | { |
3175 | int ret, i; | |
3176 | ||
3177 | /* Should have a valid DPCD by this point */ | |
3178 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
3179 | return; | |
3180 | ||
3181 | if (mode != DRM_MODE_DPMS_ON) { | |
857c416e VS |
3182 | if (downstream_hpd_needs_d0(intel_dp)) |
3183 | return; | |
3184 | ||
9d1a1031 JN |
3185 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
3186 | DP_SET_POWER_D3); | |
c7ad3810 | 3187 | } else { |
357c0ae9 ID |
3188 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
3189 | ||
c7ad3810 JB |
3190 | /* |
3191 | * When turning on, we need to retry for 1ms to give the sink | |
3192 | * time to wake up. | |
3193 | */ | |
3194 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
3195 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
3196 | DP_SET_POWER_D0); | |
c7ad3810 JB |
3197 | if (ret == 1) |
3198 | break; | |
3199 | msleep(1); | |
3200 | } | |
357c0ae9 ID |
3201 | |
3202 | if (ret == 1 && lspcon->active) | |
3203 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 3204 | } |
f9cac721 JN |
3205 | |
3206 | if (ret != 1) | |
3207 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
3208 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
3209 | } |
3210 | ||
59b74c49 VS |
3211 | static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, |
3212 | enum port port, enum pipe *pipe) | |
3213 | { | |
3214 | enum pipe p; | |
3215 | ||
3216 | for_each_pipe(dev_priv, p) { | |
3217 | u32 val = I915_READ(TRANS_DP_CTL(p)); | |
3218 | ||
3219 | if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { | |
3220 | *pipe = p; | |
3221 | return true; | |
3222 | } | |
3223 | } | |
3224 | ||
3225 | DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port)); | |
3226 | ||
3227 | /* must initialize pipe to something for the asserts */ | |
3228 | *pipe = PIPE_A; | |
3229 | ||
3230 | return false; | |
3231 | } | |
3232 | ||
3233 | bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, | |
3234 | i915_reg_t dp_reg, enum port port, | |
3235 | enum pipe *pipe) | |
3236 | { | |
3237 | bool ret; | |
3238 | u32 val; | |
3239 | ||
3240 | val = I915_READ(dp_reg); | |
3241 | ||
3242 | ret = val & DP_PORT_EN; | |
3243 | ||
3244 | /* asserts want to know the pipe even if the port is disabled */ | |
3245 | if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) | |
3246 | *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; | |
3247 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) | |
3248 | ret &= cpt_dp_port_selected(dev_priv, port, pipe); | |
3249 | else if (IS_CHERRYVIEW(dev_priv)) | |
3250 | *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; | |
3251 | else | |
3252 | *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; | |
3253 | ||
3254 | return ret; | |
3255 | } | |
3256 | ||
19d8fe15 DV |
3257 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
3258 | enum pipe *pipe) | |
d240f20f | 3259 | { |
2f773477 | 3260 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3261 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
0e6e0be4 | 3262 | intel_wakeref_t wakeref; |
6fa9a5ec | 3263 | bool ret; |
6d129bea | 3264 | |
0e6e0be4 CW |
3265 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
3266 | encoder->power_domain); | |
3267 | if (!wakeref) | |
6d129bea ID |
3268 | return false; |
3269 | ||
59b74c49 VS |
3270 | ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, |
3271 | encoder->port, pipe); | |
6fa9a5ec | 3272 | |
0e6e0be4 | 3273 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
6fa9a5ec ID |
3274 | |
3275 | return ret; | |
19d8fe15 | 3276 | } |
d240f20f | 3277 | |
045ac3b5 | 3278 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 3279 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 3280 | { |
2f773477 | 3281 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3282 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
045ac3b5 | 3283 | u32 tmp, flags = 0; |
8f4f2797 | 3284 | enum port port = encoder->port; |
2225f3c6 | 3285 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
045ac3b5 | 3286 | |
e1214b95 VS |
3287 | if (encoder->type == INTEL_OUTPUT_EDP) |
3288 | pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); | |
3289 | else | |
3290 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); | |
045ac3b5 | 3291 | |
9ed109a7 | 3292 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
3293 | |
3294 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 3295 | |
6e266956 | 3296 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
3297 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
3298 | ||
3299 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
3300 | flags |= DRM_MODE_FLAG_PHSYNC; |
3301 | else | |
3302 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 3303 | |
b81e34c2 | 3304 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
3305 | flags |= DRM_MODE_FLAG_PVSYNC; |
3306 | else | |
3307 | flags |= DRM_MODE_FLAG_NVSYNC; | |
3308 | } else { | |
39e5fa88 | 3309 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
3310 | flags |= DRM_MODE_FLAG_PHSYNC; |
3311 | else | |
3312 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 3313 | |
39e5fa88 | 3314 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
3315 | flags |= DRM_MODE_FLAG_PVSYNC; |
3316 | else | |
3317 | flags |= DRM_MODE_FLAG_NVSYNC; | |
3318 | } | |
045ac3b5 | 3319 | |
1326a92c | 3320 | pipe_config->hw.adjusted_mode.flags |= flags; |
f1f644dc | 3321 | |
c99f53f7 | 3322 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
3323 | pipe_config->limited_color_range = true; |
3324 | ||
90a6b7b0 VS |
3325 | pipe_config->lane_count = |
3326 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
3327 | ||
eb14cb74 VS |
3328 | intel_dp_get_m_n(crtc, pipe_config); |
3329 | ||
18442d08 | 3330 | if (port == PORT_A) { |
b377e0df | 3331 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
3332 | pipe_config->port_clock = 162000; |
3333 | else | |
3334 | pipe_config->port_clock = 270000; | |
3335 | } | |
18442d08 | 3336 | |
1326a92c | 3337 | pipe_config->hw.adjusted_mode.crtc_clock = |
e3b247da VS |
3338 | intel_dotclock_calculate(pipe_config->port_clock, |
3339 | &pipe_config->dp_m_n); | |
7f16e5c1 | 3340 | |
1853a9da | 3341 | if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
6aa23e65 | 3342 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
c6cd2ee2 JN |
3343 | /* |
3344 | * This is a big fat ugly hack. | |
3345 | * | |
3346 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
3347 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
3348 | * unknown we fail to light up. Yet the same BIOS boots up with | |
3349 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
3350 | * max, not what it tells us to use. | |
3351 | * | |
3352 | * Note: This will still be broken if the eDP panel is not lit | |
3353 | * up by the BIOS, and thus we can't get the mode at module | |
3354 | * load. | |
3355 | */ | |
3356 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
3357 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
3358 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 3359 | } |
045ac3b5 JB |
3360 | } |
3361 | ||
fd6bbda9 | 3362 | static void intel_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3363 | const struct intel_crtc_state *old_crtc_state, |
3364 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 3365 | { |
b7d02c3a | 3366 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
495a5bb8 | 3367 | |
edb2e530 VS |
3368 | intel_dp->link_trained = false; |
3369 | ||
85cb48a1 | 3370 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
3371 | intel_audio_codec_disable(encoder, |
3372 | old_crtc_state, old_conn_state); | |
6cb49835 DV |
3373 | |
3374 | /* Make sure the panel is off before trying to change the mode. But also | |
3375 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 3376 | intel_edp_panel_vdd_on(intel_dp); |
b037d58f | 3377 | intel_edp_backlight_off(old_conn_state); |
fdbc3b1f | 3378 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 3379 | intel_edp_panel_off(intel_dp); |
1a8ff607 VS |
3380 | } |
3381 | ||
3382 | static void g4x_disable_dp(struct intel_encoder *encoder, | |
3383 | const struct intel_crtc_state *old_crtc_state, | |
3384 | const struct drm_connector_state *old_conn_state) | |
1a8ff607 VS |
3385 | { |
3386 | intel_disable_dp(encoder, old_crtc_state, old_conn_state); | |
3387 | } | |
3388 | ||
3389 | static void vlv_disable_dp(struct intel_encoder *encoder, | |
3390 | const struct intel_crtc_state *old_crtc_state, | |
3391 | const struct drm_connector_state *old_conn_state) | |
3392 | { | |
1a8ff607 | 3393 | intel_disable_dp(encoder, old_crtc_state, old_conn_state); |
d240f20f JB |
3394 | } |
3395 | ||
51a9f6df | 3396 | static void g4x_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3397 | const struct intel_crtc_state *old_crtc_state, |
3398 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 3399 | { |
b7d02c3a | 3400 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
adc10304 | 3401 | enum port port = encoder->port; |
2bd2ad64 | 3402 | |
51a9f6df VS |
3403 | /* |
3404 | * Bspec does not list a specific disable sequence for g4x DP. | |
3405 | * Follow the ilk+ sequence (disable pipe before the port) for | |
3406 | * g4x DP as it does not suffer from underruns like the normal | |
3407 | * g4x modeset sequence (disable pipe after the port). | |
3408 | */ | |
adc10304 | 3409 | intel_dp_link_down(encoder, old_crtc_state); |
abfce949 VS |
3410 | |
3411 | /* Only ilk+ has port A */ | |
08aff3fe | 3412 | if (port == PORT_A) |
9eae5e27 | 3413 | ilk_edp_pll_off(intel_dp, old_crtc_state); |
49277c31 VS |
3414 | } |
3415 | ||
fd6bbda9 | 3416 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3417 | const struct intel_crtc_state *old_crtc_state, |
3418 | const struct drm_connector_state *old_conn_state) | |
49277c31 | 3419 | { |
adc10304 | 3420 | intel_dp_link_down(encoder, old_crtc_state); |
2bd2ad64 DV |
3421 | } |
3422 | ||
fd6bbda9 | 3423 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3424 | const struct intel_crtc_state *old_crtc_state, |
3425 | const struct drm_connector_state *old_conn_state) | |
a8f327fb | 3426 | { |
adc10304 | 3427 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
97fd4d5c | 3428 | |
adc10304 | 3429 | intel_dp_link_down(encoder, old_crtc_state); |
a8f327fb | 3430 | |
221c7862 | 3431 | vlv_dpio_get(dev_priv); |
a8f327fb VS |
3432 | |
3433 | /* Assert data lane reset */ | |
2e1029c6 | 3434 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 3435 | |
221c7862 | 3436 | vlv_dpio_put(dev_priv); |
580d3811 VS |
3437 | } |
3438 | ||
7b13b58a VS |
3439 | static void |
3440 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
830de422 JN |
3441 | u32 *DP, |
3442 | u8 dp_train_pat) | |
7b13b58a | 3443 | { |
de25eb7f | 3444 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7b13b58a | 3445 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 3446 | enum port port = intel_dig_port->base.port; |
830de422 | 3447 | u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); |
7b13b58a | 3448 | |
2edd5327 | 3449 | if (dp_train_pat & train_pat_mask) |
8b0878a0 | 3450 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", |
2edd5327 | 3451 | dp_train_pat & train_pat_mask); |
8b0878a0 | 3452 | |
4f8036a2 | 3453 | if (HAS_DDI(dev_priv)) { |
4444df6e | 3454 | u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl); |
7b13b58a VS |
3455 | |
3456 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
3457 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
3458 | else | |
3459 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
3460 | ||
3461 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2edd5327 | 3462 | switch (dp_train_pat & train_pat_mask) { |
7b13b58a VS |
3463 | case DP_TRAINING_PATTERN_DISABLE: |
3464 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
3465 | ||
3466 | break; | |
3467 | case DP_TRAINING_PATTERN_1: | |
3468 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
3469 | break; | |
3470 | case DP_TRAINING_PATTERN_2: | |
3471 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
3472 | break; | |
3473 | case DP_TRAINING_PATTERN_3: | |
3474 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
3475 | break; | |
2edd5327 MN |
3476 | case DP_TRAINING_PATTERN_4: |
3477 | temp |= DP_TP_CTL_LINK_TRAIN_PAT4; | |
3478 | break; | |
7b13b58a | 3479 | } |
4444df6e | 3480 | I915_WRITE(intel_dp->regs.dp_tp_ctl, temp); |
7b13b58a | 3481 | |
b752e995 | 3482 | } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || |
6e266956 | 3483 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
3484 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3485 | ||
3486 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
3487 | case DP_TRAINING_PATTERN_DISABLE: | |
3488 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
3489 | break; | |
3490 | case DP_TRAINING_PATTERN_1: | |
3491 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
3492 | break; | |
3493 | case DP_TRAINING_PATTERN_2: | |
3494 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
3495 | break; | |
3496 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 3497 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
3498 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
3499 | break; | |
3500 | } | |
3501 | ||
3502 | } else { | |
3b358cda | 3503 | *DP &= ~DP_LINK_TRAIN_MASK; |
7b13b58a VS |
3504 | |
3505 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
3506 | case DP_TRAINING_PATTERN_DISABLE: | |
3507 | *DP |= DP_LINK_TRAIN_OFF; | |
3508 | break; | |
3509 | case DP_TRAINING_PATTERN_1: | |
3510 | *DP |= DP_LINK_TRAIN_PAT_1; | |
3511 | break; | |
3512 | case DP_TRAINING_PATTERN_2: | |
3513 | *DP |= DP_LINK_TRAIN_PAT_2; | |
3514 | break; | |
3515 | case DP_TRAINING_PATTERN_3: | |
3b358cda VS |
3516 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
3517 | *DP |= DP_LINK_TRAIN_PAT_2; | |
7b13b58a VS |
3518 | break; |
3519 | } | |
3520 | } | |
3521 | } | |
3522 | ||
85cb48a1 | 3523 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
5f88a9c6 | 3524 | const struct intel_crtc_state *old_crtc_state) |
7b13b58a | 3525 | { |
de25eb7f | 3526 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7b13b58a | 3527 | |
7b13b58a | 3528 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 3529 | |
8b0878a0 | 3530 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
3531 | |
3532 | /* | |
3533 | * Magic for VLV/CHV. We _must_ first set up the register | |
3534 | * without actually enabling the port, and then do another | |
3535 | * write to enable the port. Otherwise link training will | |
3536 | * fail when the power sequencer is freshly used for this port. | |
3537 | */ | |
3538 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 3539 | if (old_crtc_state->has_audio) |
6fec7662 | 3540 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
3541 | |
3542 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3543 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
3544 | } |
3545 | ||
85cb48a1 | 3546 | static void intel_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3547 | const struct intel_crtc_state *pipe_config, |
3548 | const struct drm_connector_state *conn_state) | |
d240f20f | 3549 | { |
2f773477 | 3550 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3551 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 3552 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
830de422 | 3553 | u32 dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 3554 | enum pipe pipe = crtc->pipe; |
69d93820 | 3555 | intel_wakeref_t wakeref; |
5d613501 | 3556 | |
0c33d8d7 DV |
3557 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
3558 | return; | |
5d613501 | 3559 | |
69d93820 CW |
3560 | with_pps_lock(intel_dp, wakeref) { |
3561 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
3562 | vlv_init_panel_power_sequencer(encoder, pipe_config); | |
093e3f13 | 3563 | |
69d93820 | 3564 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 | 3565 | |
69d93820 CW |
3566 | edp_panel_vdd_on(intel_dp); |
3567 | edp_panel_on(intel_dp); | |
3568 | edp_panel_vdd_off(intel_dp, true); | |
3569 | } | |
093e3f13 | 3570 | |
920a14b2 | 3571 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
3572 | unsigned int lane_mask = 0x0; |
3573 | ||
920a14b2 | 3574 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 3575 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 3576 | |
9b6de0a1 VS |
3577 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
3578 | lane_mask); | |
e0fce78f | 3579 | } |
61234fa5 | 3580 | |
f01eca2e | 3581 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 3582 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 3583 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 3584 | |
85cb48a1 | 3585 | if (pipe_config->has_audio) { |
c1dec79a | 3586 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 3587 | pipe_name(pipe)); |
bbf35e9d | 3588 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 3589 | } |
ab1f90f9 | 3590 | } |
89b667f8 | 3591 | |
fd6bbda9 | 3592 | static void g4x_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3593 | const struct intel_crtc_state *pipe_config, |
3594 | const struct drm_connector_state *conn_state) | |
ecff4f3b | 3595 | { |
bbf35e9d | 3596 | intel_enable_dp(encoder, pipe_config, conn_state); |
b037d58f | 3597 | intel_edp_backlight_on(pipe_config, conn_state); |
ab1f90f9 | 3598 | } |
89b667f8 | 3599 | |
fd6bbda9 | 3600 | static void vlv_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3601 | const struct intel_crtc_state *pipe_config, |
3602 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 3603 | { |
b037d58f | 3604 | intel_edp_backlight_on(pipe_config, conn_state); |
d240f20f JB |
3605 | } |
3606 | ||
fd6bbda9 | 3607 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3608 | const struct intel_crtc_state *pipe_config, |
3609 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 3610 | { |
b7d02c3a | 3611 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
8f4f2797 | 3612 | enum port port = encoder->port; |
ab1f90f9 | 3613 | |
85cb48a1 | 3614 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3615 | |
d41f1efb | 3616 | /* Only ilk+ has port A */ |
abfce949 | 3617 | if (port == PORT_A) |
9eae5e27 | 3618 | ilk_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
3619 | } |
3620 | ||
83b84597 VS |
3621 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
3622 | { | |
3623 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 3624 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 3625 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 3626 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 3627 | |
9f2bdb00 VS |
3628 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
3629 | ||
d158694f VS |
3630 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
3631 | return; | |
3632 | ||
83b84597 VS |
3633 | edp_panel_vdd_off_sync(intel_dp); |
3634 | ||
3635 | /* | |
e7f2af78 | 3636 | * VLV seems to get confused when multiple power sequencers |
83b84597 VS |
3637 | * have the same port selected (even if only one has power/vdd |
3638 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
3639 | * CHV on the other hand doesn't seem to mind having the same port | |
e7f2af78 | 3640 | * selected in multiple power sequencers, but let's clear the |
83b84597 VS |
3641 | * port select always when logically disconnecting a power sequencer |
3642 | * from a port. | |
3643 | */ | |
66a990dd VS |
3644 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", |
3645 | pipe_name(pipe), intel_dig_port->base.base.base.id, | |
3646 | intel_dig_port->base.base.name); | |
83b84597 VS |
3647 | I915_WRITE(pp_on_reg, 0); |
3648 | POSTING_READ(pp_on_reg); | |
3649 | ||
3650 | intel_dp->pps_pipe = INVALID_PIPE; | |
3651 | } | |
3652 | ||
46bd8383 | 3653 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a4a5d2f8 VS |
3654 | enum pipe pipe) |
3655 | { | |
a4a5d2f8 VS |
3656 | struct intel_encoder *encoder; |
3657 | ||
3658 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3659 | ||
14aa521c | 3660 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 3661 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4a5d2f8 | 3662 | |
9f2bdb00 | 3663 | WARN(intel_dp->active_pipe == pipe, |
66a990dd VS |
3664 | "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", |
3665 | pipe_name(pipe), encoder->base.base.id, | |
3666 | encoder->base.name); | |
9f2bdb00 | 3667 | |
a4a5d2f8 VS |
3668 | if (intel_dp->pps_pipe != pipe) |
3669 | continue; | |
3670 | ||
66a990dd VS |
3671 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", |
3672 | pipe_name(pipe), encoder->base.base.id, | |
3673 | encoder->base.name); | |
a4a5d2f8 VS |
3674 | |
3675 | /* make sure vdd is off before we steal it */ | |
83b84597 | 3676 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
3677 | } |
3678 | } | |
3679 | ||
adc10304 VS |
3680 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
3681 | const struct intel_crtc_state *crtc_state) | |
a4a5d2f8 | 3682 | { |
46bd8383 | 3683 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3684 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 3685 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
a4a5d2f8 VS |
3686 | |
3687 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3688 | ||
9f2bdb00 | 3689 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 3690 | |
9f2bdb00 VS |
3691 | if (intel_dp->pps_pipe != INVALID_PIPE && |
3692 | intel_dp->pps_pipe != crtc->pipe) { | |
3693 | /* | |
3694 | * If another power sequencer was being used on this | |
3695 | * port previously make sure to turn off vdd there while | |
3696 | * we still have control of it. | |
3697 | */ | |
83b84597 | 3698 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 3699 | } |
a4a5d2f8 VS |
3700 | |
3701 | /* | |
3702 | * We may be stealing the power | |
3703 | * sequencer from another port. | |
3704 | */ | |
46bd8383 | 3705 | vlv_steal_power_sequencer(dev_priv, crtc->pipe); |
a4a5d2f8 | 3706 | |
9f2bdb00 VS |
3707 | intel_dp->active_pipe = crtc->pipe; |
3708 | ||
1853a9da | 3709 | if (!intel_dp_is_edp(intel_dp)) |
9f2bdb00 VS |
3710 | return; |
3711 | ||
a4a5d2f8 VS |
3712 | /* now it's all ours */ |
3713 | intel_dp->pps_pipe = crtc->pipe; | |
3714 | ||
66a990dd VS |
3715 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", |
3716 | pipe_name(intel_dp->pps_pipe), encoder->base.base.id, | |
3717 | encoder->base.name); | |
a4a5d2f8 VS |
3718 | |
3719 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
3720 | intel_dp_init_panel_power_sequencer(intel_dp); |
3721 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 VS |
3722 | } |
3723 | ||
fd6bbda9 | 3724 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3725 | const struct intel_crtc_state *pipe_config, |
3726 | const struct drm_connector_state *conn_state) | |
a4fc5ed6 | 3727 | { |
2e1029c6 | 3728 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
ab1f90f9 | 3729 | |
bbf35e9d | 3730 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
3731 | } |
3732 | ||
fd6bbda9 | 3733 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3734 | const struct intel_crtc_state *pipe_config, |
3735 | const struct drm_connector_state *conn_state) | |
89b667f8 | 3736 | { |
85cb48a1 | 3737 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3738 | |
2e1029c6 | 3739 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
a4fc5ed6 KP |
3740 | } |
3741 | ||
fd6bbda9 | 3742 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3743 | const struct intel_crtc_state *pipe_config, |
3744 | const struct drm_connector_state *conn_state) | |
e4a1d846 | 3745 | { |
2e1029c6 | 3746 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
e4a1d846 | 3747 | |
bbf35e9d | 3748 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
3749 | |
3750 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 3751 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
3752 | } |
3753 | ||
fd6bbda9 | 3754 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3755 | const struct intel_crtc_state *pipe_config, |
3756 | const struct drm_connector_state *conn_state) | |
9197c88b | 3757 | { |
85cb48a1 | 3758 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 3759 | |
2e1029c6 | 3760 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
3761 | } |
3762 | ||
fd6bbda9 | 3763 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
2e1029c6 VS |
3764 | const struct intel_crtc_state *old_crtc_state, |
3765 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 3766 | { |
2e1029c6 | 3767 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
3768 | } |
3769 | ||
a4fc5ed6 KP |
3770 | /* |
3771 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3772 | * link status information | |
3773 | */ | |
94223d04 | 3774 | bool |
830de422 | 3775 | intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3776 | { |
9f085ebb L |
3777 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3778 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3779 | } |
3780 | ||
1100244e | 3781 | /* These are source-specific values. */ |
830de422 | 3782 | u8 |
1a2eb460 | 3783 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3784 | { |
de25eb7f | 3785 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a393e964 VS |
3786 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3787 | enum port port = encoder->port; | |
1a2eb460 | 3788 | |
a393e964 | 3789 | if (HAS_DDI(dev_priv)) |
ffe5111e | 3790 | return intel_ddi_dp_voltage_max(encoder); |
a393e964 | 3791 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3792 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
b752e995 | 3793 | else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) |
bd60018a | 3794 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3795 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3796 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3797 | else |
bd60018a | 3798 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3799 | } |
3800 | ||
830de422 JN |
3801 | u8 |
3802 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing) | |
1a2eb460 | 3803 | { |
de25eb7f | 3804 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4718a365 VS |
3805 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3806 | enum port port = encoder->port; | |
1a2eb460 | 3807 | |
4718a365 VS |
3808 | if (HAS_DDI(dev_priv)) { |
3809 | return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing); | |
8652744b | 3810 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3811 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3812 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3813 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3814 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3815 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3816 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3817 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3818 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3819 | default: |
bd60018a | 3820 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3821 | } |
b752e995 | 3822 | } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
1a2eb460 | 3823 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3824 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3825 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3826 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3827 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3828 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3829 | default: |
bd60018a | 3830 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3831 | } |
3832 | } else { | |
3833 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3834 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3835 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3836 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3837 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3838 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3839 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3840 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3841 | default: |
bd60018a | 3842 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3843 | } |
a4fc5ed6 KP |
3844 | } |
3845 | } | |
3846 | ||
830de422 | 3847 | static u32 vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3848 | { |
53d98725 | 3849 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3850 | unsigned long demph_reg_value, preemph_reg_value, |
3851 | uniqtranscale_reg_value; | |
830de422 | 3852 | u8 train_set = intel_dp->train_set[0]; |
e2fa6fba P |
3853 | |
3854 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3855 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3856 | preemph_reg_value = 0x0004000; |
3857 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3858 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3859 | demph_reg_value = 0x2B405555; |
3860 | uniqtranscale_reg_value = 0x552AB83A; | |
3861 | break; | |
bd60018a | 3862 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3863 | demph_reg_value = 0x2B404040; |
3864 | uniqtranscale_reg_value = 0x5548B83A; | |
3865 | break; | |
bd60018a | 3866 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3867 | demph_reg_value = 0x2B245555; |
3868 | uniqtranscale_reg_value = 0x5560B83A; | |
3869 | break; | |
bd60018a | 3870 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3871 | demph_reg_value = 0x2B405555; |
3872 | uniqtranscale_reg_value = 0x5598DA3A; | |
3873 | break; | |
3874 | default: | |
3875 | return 0; | |
3876 | } | |
3877 | break; | |
bd60018a | 3878 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3879 | preemph_reg_value = 0x0002000; |
3880 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3881 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3882 | demph_reg_value = 0x2B404040; |
3883 | uniqtranscale_reg_value = 0x5552B83A; | |
3884 | break; | |
bd60018a | 3885 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3886 | demph_reg_value = 0x2B404848; |
3887 | uniqtranscale_reg_value = 0x5580B83A; | |
3888 | break; | |
bd60018a | 3889 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3890 | demph_reg_value = 0x2B404040; |
3891 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3892 | break; | |
3893 | default: | |
3894 | return 0; | |
3895 | } | |
3896 | break; | |
bd60018a | 3897 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3898 | preemph_reg_value = 0x0000000; |
3899 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3900 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3901 | demph_reg_value = 0x2B305555; |
3902 | uniqtranscale_reg_value = 0x5570B83A; | |
3903 | break; | |
bd60018a | 3904 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3905 | demph_reg_value = 0x2B2B4040; |
3906 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3907 | break; | |
3908 | default: | |
3909 | return 0; | |
3910 | } | |
3911 | break; | |
bd60018a | 3912 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3913 | preemph_reg_value = 0x0006000; |
3914 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3915 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3916 | demph_reg_value = 0x1B405555; |
3917 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3918 | break; | |
3919 | default: | |
3920 | return 0; | |
3921 | } | |
3922 | break; | |
3923 | default: | |
3924 | return 0; | |
3925 | } | |
3926 | ||
53d98725 ACO |
3927 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3928 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3929 | |
3930 | return 0; | |
3931 | } | |
3932 | ||
830de422 | 3933 | static u32 chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3934 | { |
b7fa22d8 ACO |
3935 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3936 | u32 deemph_reg_value, margin_reg_value; | |
3937 | bool uniq_trans_scale = false; | |
830de422 | 3938 | u8 train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3939 | |
3940 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3941 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3942 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3943 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3944 | deemph_reg_value = 128; |
3945 | margin_reg_value = 52; | |
3946 | break; | |
bd60018a | 3947 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3948 | deemph_reg_value = 128; |
3949 | margin_reg_value = 77; | |
3950 | break; | |
bd60018a | 3951 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3952 | deemph_reg_value = 128; |
3953 | margin_reg_value = 102; | |
3954 | break; | |
bd60018a | 3955 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3956 | deemph_reg_value = 128; |
3957 | margin_reg_value = 154; | |
b7fa22d8 | 3958 | uniq_trans_scale = true; |
e4a1d846 CML |
3959 | break; |
3960 | default: | |
3961 | return 0; | |
3962 | } | |
3963 | break; | |
bd60018a | 3964 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3965 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3966 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3967 | deemph_reg_value = 85; |
3968 | margin_reg_value = 78; | |
3969 | break; | |
bd60018a | 3970 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3971 | deemph_reg_value = 85; |
3972 | margin_reg_value = 116; | |
3973 | break; | |
bd60018a | 3974 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3975 | deemph_reg_value = 85; |
3976 | margin_reg_value = 154; | |
3977 | break; | |
3978 | default: | |
3979 | return 0; | |
3980 | } | |
3981 | break; | |
bd60018a | 3982 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3983 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3984 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3985 | deemph_reg_value = 64; |
3986 | margin_reg_value = 104; | |
3987 | break; | |
bd60018a | 3988 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3989 | deemph_reg_value = 64; |
3990 | margin_reg_value = 154; | |
3991 | break; | |
3992 | default: | |
3993 | return 0; | |
3994 | } | |
3995 | break; | |
bd60018a | 3996 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3997 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3998 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3999 | deemph_reg_value = 43; |
4000 | margin_reg_value = 154; | |
4001 | break; | |
4002 | default: | |
4003 | return 0; | |
4004 | } | |
4005 | break; | |
4006 | default: | |
4007 | return 0; | |
4008 | } | |
4009 | ||
b7fa22d8 ACO |
4010 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
4011 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
4012 | |
4013 | return 0; | |
4014 | } | |
4015 | ||
830de422 JN |
4016 | static u32 |
4017 | g4x_signal_levels(u8 train_set) | |
a4fc5ed6 | 4018 | { |
830de422 | 4019 | u32 signal_levels = 0; |
a4fc5ed6 | 4020 | |
3cf2efb1 | 4021 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4022 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
4023 | default: |
4024 | signal_levels |= DP_VOLTAGE_0_4; | |
4025 | break; | |
bd60018a | 4026 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
4027 | signal_levels |= DP_VOLTAGE_0_6; |
4028 | break; | |
bd60018a | 4029 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
4030 | signal_levels |= DP_VOLTAGE_0_8; |
4031 | break; | |
bd60018a | 4032 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
4033 | signal_levels |= DP_VOLTAGE_1_2; |
4034 | break; | |
4035 | } | |
3cf2efb1 | 4036 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 4037 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
4038 | default: |
4039 | signal_levels |= DP_PRE_EMPHASIS_0; | |
4040 | break; | |
bd60018a | 4041 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
4042 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
4043 | break; | |
bd60018a | 4044 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
4045 | signal_levels |= DP_PRE_EMPHASIS_6; |
4046 | break; | |
bd60018a | 4047 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
4048 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
4049 | break; | |
4050 | } | |
4051 | return signal_levels; | |
4052 | } | |
4053 | ||
4d82c2b5 | 4054 | /* SNB CPU eDP voltage swing and pre-emphasis control */ |
830de422 JN |
4055 | static u32 |
4056 | snb_cpu_edp_signal_levels(u8 train_set) | |
e3421a18 | 4057 | { |
3c5a62b5 YL |
4058 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
4059 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
4060 | switch (signal_levels) { | |
bd60018a SJ |
4061 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
4062 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 4063 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 4064 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 4065 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
4066 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
4067 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 4068 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
4069 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
4070 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 4071 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
4072 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
4073 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 4074 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 4075 | default: |
3c5a62b5 YL |
4076 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
4077 | "0x%x\n", signal_levels); | |
4078 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
4079 | } |
4080 | } | |
4081 | ||
4d82c2b5 | 4082 | /* IVB CPU eDP voltage swing and pre-emphasis control */ |
830de422 JN |
4083 | static u32 |
4084 | ivb_cpu_edp_signal_levels(u8 train_set) | |
1a2eb460 KP |
4085 | { |
4086 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
4087 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
4088 | switch (signal_levels) { | |
bd60018a | 4089 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4090 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 4091 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 4092 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 4093 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
4094 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
4095 | ||
bd60018a | 4096 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4097 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 4098 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
4099 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
4100 | ||
bd60018a | 4101 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4102 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 4103 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
4104 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
4105 | ||
4106 | default: | |
4107 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
4108 | "0x%x\n", signal_levels); | |
4109 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
4110 | } | |
4111 | } | |
4112 | ||
94223d04 | 4113 | void |
f4eb692e | 4114 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e | 4115 | { |
de25eb7f | 4116 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
f0a3424e | 4117 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 4118 | enum port port = intel_dig_port->base.port; |
830de422 JN |
4119 | u32 signal_levels, mask = 0; |
4120 | u8 train_set = intel_dp->train_set[0]; | |
f0a3424e | 4121 | |
61cdfb9e | 4122 | if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { |
d509af6c RV |
4123 | signal_levels = bxt_signal_levels(intel_dp); |
4124 | } else if (HAS_DDI(dev_priv)) { | |
f8896f5d | 4125 | signal_levels = ddi_signal_levels(intel_dp); |
d509af6c | 4126 | mask = DDI_BUF_EMP_MASK; |
920a14b2 | 4127 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 4128 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 4129 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 4130 | signal_levels = vlv_signal_levels(intel_dp); |
b752e995 | 4131 | } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
4d82c2b5 | 4132 | signal_levels = ivb_cpu_edp_signal_levels(train_set); |
f0a3424e | 4133 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
cf819eff | 4134 | } else if (IS_GEN(dev_priv, 6) && port == PORT_A) { |
4d82c2b5 | 4135 | signal_levels = snb_cpu_edp_signal_levels(train_set); |
f0a3424e PZ |
4136 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
4137 | } else { | |
45101e93 | 4138 | signal_levels = g4x_signal_levels(train_set); |
f0a3424e PZ |
4139 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
4140 | } | |
4141 | ||
96fb9f9b VK |
4142 | if (mask) |
4143 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
4144 | ||
4145 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
4146 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
4147 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
4148 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
4149 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 4150 | |
f4eb692e | 4151 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
4152 | |
4153 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
4154 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
4155 | } |
4156 | ||
94223d04 | 4157 | void |
e9c176d5 | 4158 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
830de422 | 4159 | u8 dp_train_pat) |
a4fc5ed6 | 4160 | { |
174edf1f | 4161 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
4162 | struct drm_i915_private *dev_priv = |
4163 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 4164 | |
f4eb692e | 4165 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 4166 | |
f4eb692e | 4167 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 4168 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
4169 | } |
4170 | ||
94223d04 | 4171 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 | 4172 | { |
de25eb7f | 4173 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
3ab9c637 | 4174 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 4175 | enum port port = intel_dig_port->base.port; |
830de422 | 4176 | u32 val; |
3ab9c637 | 4177 | |
4f8036a2 | 4178 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
4179 | return; |
4180 | ||
4444df6e | 4181 | val = I915_READ(intel_dp->regs.dp_tp_ctl); |
3ab9c637 ID |
4182 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
4183 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
4444df6e | 4184 | I915_WRITE(intel_dp->regs.dp_tp_ctl, val); |
3ab9c637 ID |
4185 | |
4186 | /* | |
99389390 JRS |
4187 | * Until TGL on PORT_A we can have only eDP in SST mode. There the only |
4188 | * reason we need to set idle transmission mode is to work around a HW | |
4189 | * issue where we enable the pipe while not in idle link-training mode. | |
3ab9c637 ID |
4190 | * In this case there is requirement to wait for a minimum number of |
4191 | * idle patterns to be sent. | |
4192 | */ | |
99389390 | 4193 | if (port == PORT_A && INTEL_GEN(dev_priv) < 12) |
3ab9c637 ID |
4194 | return; |
4195 | ||
4444df6e | 4196 | if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, |
4cb3b44d | 4197 | DP_TP_STATUS_IDLE_DONE, 1)) |
3ab9c637 ID |
4198 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
4199 | } | |
4200 | ||
a4fc5ed6 | 4201 | static void |
adc10304 VS |
4202 | intel_dp_link_down(struct intel_encoder *encoder, |
4203 | const struct intel_crtc_state *old_crtc_state) | |
a4fc5ed6 | 4204 | { |
adc10304 | 4205 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 4206 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 4207 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
adc10304 | 4208 | enum port port = encoder->port; |
830de422 | 4209 | u32 DP = intel_dp->DP; |
a4fc5ed6 | 4210 | |
0c33d8d7 | 4211 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
4212 | return; |
4213 | ||
28c97730 | 4214 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 4215 | |
b752e995 | 4216 | if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || |
6e266956 | 4217 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 4218 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 4219 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 4220 | } else { |
3b358cda | 4221 | DP &= ~DP_LINK_TRAIN_MASK; |
1612c8bd | 4222 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 4223 | } |
1612c8bd | 4224 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 4225 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 4226 | |
1612c8bd VS |
4227 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
4228 | I915_WRITE(intel_dp->output_reg, DP); | |
4229 | POSTING_READ(intel_dp->output_reg); | |
4230 | ||
4231 | /* | |
4232 | * HW workaround for IBX, we need to move the port | |
4233 | * to transcoder A after disabling it to allow the | |
4234 | * matching HDMI port to be enabled on transcoder A. | |
4235 | */ | |
6e266956 | 4236 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
4237 | /* |
4238 | * We get CPU/PCH FIFO underruns on the other pipe when | |
4239 | * doing the workaround. Sweep them under the rug. | |
4240 | */ | |
4241 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
4242 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
4243 | ||
1612c8bd | 4244 | /* always enable with pattern 1 (as per spec) */ |
59b74c49 VS |
4245 | DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); |
4246 | DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | | |
4247 | DP_LINK_TRAIN_PAT_1; | |
1612c8bd VS |
4248 | I915_WRITE(intel_dp->output_reg, DP); |
4249 | POSTING_READ(intel_dp->output_reg); | |
4250 | ||
4251 | DP &= ~DP_PORT_EN; | |
5bddd17f | 4252 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 4253 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 4254 | |
0f0f74bc | 4255 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
4256 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
4257 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
4258 | } |
4259 | ||
f01eca2e | 4260 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
4261 | |
4262 | intel_dp->DP = DP; | |
9f2bdb00 VS |
4263 | |
4264 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
69d93820 CW |
4265 | intel_wakeref_t wakeref; |
4266 | ||
4267 | with_pps_lock(intel_dp, wakeref) | |
4268 | intel_dp->active_pipe = INVALID_PIPE; | |
9f2bdb00 | 4269 | } |
a4fc5ed6 KP |
4270 | } |
4271 | ||
a1d92652 MA |
4272 | static void |
4273 | intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp) | |
4274 | { | |
4275 | u8 dpcd_ext[6]; | |
4276 | ||
4277 | /* | |
4278 | * Prior to DP1.3 the bit represented by | |
4279 | * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. | |
4280 | * if it is set DP_DPCD_REV at 0000h could be at a value less than | |
4281 | * the true capability of the panel. The only way to check is to | |
4282 | * then compare 0000h and 2200h. | |
4283 | */ | |
4284 | if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] & | |
4285 | DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) | |
4286 | return; | |
4287 | ||
4288 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV, | |
4289 | &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) { | |
4290 | DRM_ERROR("DPCD failed read at extended capabilities\n"); | |
4291 | return; | |
4292 | } | |
4293 | ||
4294 | if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { | |
4295 | DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n"); | |
4296 | return; | |
4297 | } | |
4298 | ||
4299 | if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext))) | |
4300 | return; | |
4301 | ||
4302 | DRM_DEBUG_KMS("Base DPCD: %*ph\n", | |
4303 | (int)sizeof(intel_dp->dpcd), intel_dp->dpcd); | |
4304 | ||
4305 | memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)); | |
4306 | } | |
4307 | ||
24e807e7 | 4308 | bool |
fe5a66f9 | 4309 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 4310 | { |
9f085ebb L |
4311 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
4312 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 4313 | return false; /* aux transfer failed */ |
92fd8fd1 | 4314 | |
a1d92652 MA |
4315 | intel_dp_extended_receiver_capabilities(intel_dp); |
4316 | ||
a8e98153 | 4317 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 4318 | |
fe5a66f9 VS |
4319 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
4320 | } | |
edb39244 | 4321 | |
8e9d645c GM |
4322 | bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
4323 | { | |
4324 | u8 dprx = 0; | |
4325 | ||
4326 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
4327 | &dprx) != 1) | |
4328 | return false; | |
4329 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
4330 | } | |
4331 | ||
93ac092f MN |
4332 | static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) |
4333 | { | |
4334 | /* | |
4335 | * Clear the cached register set to avoid using stale values | |
4336 | * for the sinks that do not support DSC. | |
4337 | */ | |
4338 | memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); | |
4339 | ||
08cadae8 AS |
4340 | /* Clear fec_capable to avoid using stale values */ |
4341 | intel_dp->fec_capable = 0; | |
4342 | ||
93ac092f MN |
4343 | /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ |
4344 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || | |
4345 | intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
4346 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, | |
4347 | intel_dp->dsc_dpcd, | |
4348 | sizeof(intel_dp->dsc_dpcd)) < 0) | |
4349 | DRM_ERROR("Failed to read DPCD register 0x%x\n", | |
4350 | DP_DSC_SUPPORT); | |
4351 | ||
4352 | DRM_DEBUG_KMS("DSC DPCD: %*ph\n", | |
4353 | (int)sizeof(intel_dp->dsc_dpcd), | |
4354 | intel_dp->dsc_dpcd); | |
0ce611c9 | 4355 | |
08cadae8 | 4356 | /* FEC is supported only on DP 1.4 */ |
0ce611c9 CW |
4357 | if (!intel_dp_is_edp(intel_dp) && |
4358 | drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, | |
4359 | &intel_dp->fec_capable) < 0) | |
4360 | DRM_ERROR("Failed to read FEC DPCD register\n"); | |
08cadae8 | 4361 | |
0ce611c9 | 4362 | DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable); |
93ac092f MN |
4363 | } |
4364 | } | |
4365 | ||
fe5a66f9 VS |
4366 | static bool |
4367 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
4368 | { | |
4369 | struct drm_i915_private *dev_priv = | |
4370 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 4371 | |
fe5a66f9 VS |
4372 | /* this function is meant to be called only once */ |
4373 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 4374 | |
fe5a66f9 | 4375 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
4376 | return false; |
4377 | ||
84c36753 JN |
4378 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4379 | drm_dp_is_branch(intel_dp->dpcd)); | |
12a47a42 | 4380 | |
7c838e2a JN |
4381 | /* |
4382 | * Read the eDP display control registers. | |
4383 | * | |
4384 | * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in | |
4385 | * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it | |
4386 | * set, but require eDP 1.4+ detection (e.g. for supported link rates | |
4387 | * method). The display control registers should read zero if they're | |
4388 | * not supported anyway. | |
4389 | */ | |
4390 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
4391 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
4392 | sizeof(intel_dp->edp_dpcd)) | |
e6ed2a1b | 4393 | DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
fe5a66f9 | 4394 | intel_dp->edp_dpcd); |
06ea66b6 | 4395 | |
84bb2916 DP |
4396 | /* |
4397 | * This has to be called after intel_dp->edp_dpcd is filled, PSR checks | |
4398 | * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] | |
4399 | */ | |
4400 | intel_psr_init_dpcd(intel_dp); | |
4401 | ||
e6ed2a1b JN |
4402 | /* Read the eDP 1.4+ supported link rates. */ |
4403 | if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
94ca719e | 4404 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
4405 | int i; |
4406 | ||
9f085ebb L |
4407 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
4408 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 4409 | |
94ca719e VS |
4410 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
4411 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
4412 | |
4413 | if (val == 0) | |
4414 | break; | |
4415 | ||
fd81c44e DP |
4416 | /* Value read multiplied by 200kHz gives the per-lane |
4417 | * link rate in kHz. The source rates are, however, | |
4418 | * stored in terms of LS_Clk kHz. The full conversion | |
4419 | * back to symbols is | |
4420 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
4421 | */ | |
af77b974 | 4422 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 4423 | } |
94ca719e | 4424 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 4425 | } |
0336400e | 4426 | |
e6ed2a1b JN |
4427 | /* |
4428 | * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, | |
4429 | * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. | |
4430 | */ | |
68f357cb JN |
4431 | if (intel_dp->num_sink_rates) |
4432 | intel_dp->use_rate_select = true; | |
4433 | else | |
4434 | intel_dp_set_sink_rates(intel_dp); | |
4435 | ||
975ee5fc JN |
4436 | intel_dp_set_common_rates(intel_dp); |
4437 | ||
93ac092f MN |
4438 | /* Read the eDP DSC DPCD registers */ |
4439 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
4440 | intel_dp_get_dsc_sink_cap(intel_dp); | |
4441 | ||
fe5a66f9 VS |
4442 | return true; |
4443 | } | |
4444 | ||
4445 | ||
4446 | static bool | |
4447 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
4448 | { | |
4449 | if (!intel_dp_read_dpcd(intel_dp)) | |
4450 | return false; | |
4451 | ||
eaa2b31b VS |
4452 | /* |
4453 | * Don't clobber cached eDP rates. Also skip re-reading | |
4454 | * the OUI/ID since we know it won't change. | |
4455 | */ | |
1853a9da | 4456 | if (!intel_dp_is_edp(intel_dp)) { |
eaa2b31b VS |
4457 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4458 | drm_dp_is_branch(intel_dp->dpcd)); | |
4459 | ||
68f357cb | 4460 | intel_dp_set_sink_rates(intel_dp); |
975ee5fc JN |
4461 | intel_dp_set_common_rates(intel_dp); |
4462 | } | |
68f357cb | 4463 | |
fe5a66f9 | 4464 | /* |
2bb06265 JRS |
4465 | * Some eDP panels do not set a valid value for sink count, that is why |
4466 | * it don't care about read it here and in intel_edp_init_dpcd(). | |
fe5a66f9 | 4467 | */ |
eaa2b31b VS |
4468 | if (!intel_dp_is_edp(intel_dp) && |
4469 | !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) { | |
2bb06265 JRS |
4470 | u8 count; |
4471 | ssize_t r; | |
fe5a66f9 | 4472 | |
2bb06265 JRS |
4473 | r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count); |
4474 | if (r < 1) | |
4475 | return false; | |
4476 | ||
4477 | /* | |
4478 | * Sink count can change between short pulse hpd hence | |
4479 | * a member variable in intel_dp will track any changes | |
4480 | * between short pulse interrupts. | |
4481 | */ | |
4482 | intel_dp->sink_count = DP_GET_SINK_COUNT(count); | |
4483 | ||
4484 | /* | |
4485 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
4486 | * a dongle is present but no display. Unless we require to know | |
4487 | * if a dongle is present or not, we don't need to update | |
4488 | * downstream port information. So, an early return here saves | |
4489 | * time from performing other operations which are not required. | |
4490 | */ | |
4491 | if (!intel_dp->sink_count) | |
4492 | return false; | |
4493 | } | |
0336400e | 4494 | |
c726ad01 | 4495 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
4496 | return true; /* native DP sink */ |
4497 | ||
4498 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
4499 | return true; /* no per-port downstream info */ | |
4500 | ||
9f085ebb L |
4501 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
4502 | intel_dp->downstream_ports, | |
4503 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
4504 | return false; /* downstream port status fetch failed */ |
4505 | ||
4506 | return true; | |
92fd8fd1 KP |
4507 | } |
4508 | ||
0e32b39c | 4509 | static bool |
9dbf5a4e | 4510 | intel_dp_sink_can_mst(struct intel_dp *intel_dp) |
0e32b39c | 4511 | { |
010b9b39 | 4512 | u8 mstm_cap; |
0e32b39c | 4513 | |
0e32b39c DA |
4514 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
4515 | return false; | |
4516 | ||
010b9b39 | 4517 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1) |
c4e3170a | 4518 | return false; |
0e32b39c | 4519 | |
010b9b39 | 4520 | return mstm_cap & DP_MST_CAP; |
c4e3170a VS |
4521 | } |
4522 | ||
9dbf5a4e VS |
4523 | static bool |
4524 | intel_dp_can_mst(struct intel_dp *intel_dp) | |
4525 | { | |
4526 | return i915_modparams.enable_dp_mst && | |
4527 | intel_dp->can_mst && | |
4528 | intel_dp_sink_can_mst(intel_dp); | |
4529 | } | |
4530 | ||
c4e3170a VS |
4531 | static void |
4532 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
4533 | { | |
9dbf5a4e VS |
4534 | struct intel_encoder *encoder = |
4535 | &dp_to_dig_port(intel_dp)->base; | |
4536 | bool sink_can_mst = intel_dp_sink_can_mst(intel_dp); | |
4537 | ||
7acf6c94 | 4538 | DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", |
66a990dd VS |
4539 | encoder->base.base.id, encoder->base.name, |
4540 | yesno(intel_dp->can_mst), yesno(sink_can_mst), | |
4541 | yesno(i915_modparams.enable_dp_mst)); | |
c4e3170a VS |
4542 | |
4543 | if (!intel_dp->can_mst) | |
4544 | return; | |
4545 | ||
9dbf5a4e VS |
4546 | intel_dp->is_mst = sink_can_mst && |
4547 | i915_modparams.enable_dp_mst; | |
c4e3170a VS |
4548 | |
4549 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4550 | intel_dp->is_mst); | |
0e32b39c DA |
4551 | } |
4552 | ||
0e32b39c DA |
4553 | static bool |
4554 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4555 | { | |
e8b2577c PD |
4556 | return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, |
4557 | sink_irq_vector, DP_DPRX_ESI_LEN) == | |
4558 | DP_DPRX_ESI_LEN; | |
0e32b39c DA |
4559 | } |
4560 | ||
0c06fa15 GM |
4561 | bool |
4562 | intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, | |
4563 | const struct drm_connector_state *conn_state) | |
4564 | { | |
4565 | /* | |
4566 | * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication | |
4567 | * of Color Encoding Format and Content Color Gamut], in order to | |
4568 | * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. | |
4569 | */ | |
4570 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
4571 | return true; | |
4572 | ||
4573 | switch (conn_state->colorspace) { | |
4574 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
4575 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
4576 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
4577 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
4578 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
4579 | return true; | |
4580 | default: | |
4581 | break; | |
4582 | } | |
4583 | ||
4584 | return false; | |
4585 | } | |
4586 | ||
3c053a96 | 4587 | static void |
bb71fb00 GM |
4588 | intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp, |
4589 | const struct intel_crtc_state *crtc_state, | |
4590 | const struct drm_connector_state *conn_state) | |
3c053a96 GM |
4591 | { |
4592 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4593 | struct dp_sdp vsc_sdp = {}; | |
4594 | ||
4595 | /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */ | |
4596 | vsc_sdp.sdp_header.HB0 = 0; | |
4597 | vsc_sdp.sdp_header.HB1 = 0x7; | |
4598 | ||
4599 | /* | |
4600 | * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ | |
4601 | * Colorimetry Format indication. | |
4602 | */ | |
4603 | vsc_sdp.sdp_header.HB2 = 0x5; | |
4604 | ||
4605 | /* | |
4606 | * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/ | |
4607 | * Colorimetry Format indication (HB2 = 05h). | |
4608 | */ | |
4609 | vsc_sdp.sdp_header.HB3 = 0x13; | |
4610 | ||
bb71fb00 GM |
4611 | /* DP 1.4a spec, Table 2-120 */ |
4612 | switch (crtc_state->output_format) { | |
4613 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
4614 | vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */ | |
4615 | break; | |
4616 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
4617 | vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */ | |
4618 | break; | |
4619 | case INTEL_OUTPUT_FORMAT_RGB: | |
4620 | default: | |
4621 | /* RGB: DB16[7:4] = 0h */ | |
4622 | break; | |
4623 | } | |
4624 | ||
4625 | switch (conn_state->colorspace) { | |
4626 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
4627 | vsc_sdp.db[16] |= 0x1; | |
4628 | break; | |
4629 | case DRM_MODE_COLORIMETRY_XVYCC_601: | |
4630 | vsc_sdp.db[16] |= 0x2; | |
4631 | break; | |
4632 | case DRM_MODE_COLORIMETRY_XVYCC_709: | |
4633 | vsc_sdp.db[16] |= 0x3; | |
4634 | break; | |
4635 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
4636 | vsc_sdp.db[16] |= 0x4; | |
4637 | break; | |
4638 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
4639 | vsc_sdp.db[16] |= 0x5; | |
4640 | break; | |
4641 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
4642 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
4643 | vsc_sdp.db[16] |= 0x6; | |
4644 | break; | |
4645 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
4646 | vsc_sdp.db[16] |= 0x7; | |
4647 | break; | |
4648 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: | |
4649 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: | |
4650 | vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */ | |
4651 | break; | |
4652 | default: | |
4653 | /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */ | |
4654 | ||
4655 | /* RGB->YCBCR color conversion uses the BT.709 color space. */ | |
4656 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
4657 | vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */ | |
4658 | break; | |
4659 | } | |
3c053a96 GM |
4660 | |
4661 | /* | |
4662 | * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only, | |
4663 | * the following Component Bit Depth values are defined: | |
4664 | * 001b = 8bpc. | |
4665 | * 010b = 10bpc. | |
4666 | * 011b = 12bpc. | |
4667 | * 100b = 16bpc. | |
4668 | */ | |
4669 | switch (crtc_state->pipe_bpp) { | |
4670 | case 24: /* 8bpc */ | |
4671 | vsc_sdp.db[17] = 0x1; | |
4672 | break; | |
4673 | case 30: /* 10bpc */ | |
4674 | vsc_sdp.db[17] = 0x2; | |
4675 | break; | |
4676 | case 36: /* 12bpc */ | |
4677 | vsc_sdp.db[17] = 0x3; | |
4678 | break; | |
4679 | case 48: /* 16bpc */ | |
4680 | vsc_sdp.db[17] = 0x4; | |
4681 | break; | |
4682 | default: | |
4683 | MISSING_CASE(crtc_state->pipe_bpp); | |
4684 | break; | |
4685 | } | |
4686 | ||
4687 | /* | |
4688 | * Dynamic Range (Bit 7) | |
4689 | * 0 = VESA range, 1 = CTA range. | |
4690 | * all YCbCr are always limited range | |
4691 | */ | |
4692 | vsc_sdp.db[17] |= 0x80; | |
4693 | ||
4694 | /* | |
4695 | * Content Type (Bits 2:0) | |
4696 | * 000b = Not defined. | |
4697 | * 001b = Graphics. | |
4698 | * 010b = Photo. | |
4699 | * 011b = Video. | |
4700 | * 100b = Game | |
4701 | * All other values are RESERVED. | |
4702 | * Note: See CTA-861-G for the definition and expected | |
4703 | * processing by a stream sink for the above contect types. | |
4704 | */ | |
4705 | vsc_sdp.db[18] = 0; | |
4706 | ||
4707 | intel_dig_port->write_infoframe(&intel_dig_port->base, | |
4708 | crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp)); | |
4709 | } | |
4710 | ||
b246cf21 GM |
4711 | static void |
4712 | intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, | |
4713 | const struct intel_crtc_state *crtc_state, | |
4714 | const struct drm_connector_state *conn_state) | |
4715 | { | |
4716 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4717 | struct dp_sdp infoframe_sdp = {}; | |
4718 | struct hdmi_drm_infoframe drm_infoframe = {}; | |
4719 | const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; | |
4720 | unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; | |
4721 | ssize_t len; | |
4722 | int ret; | |
4723 | ||
4724 | ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state); | |
4725 | if (ret) { | |
4726 | DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); | |
4727 | return; | |
4728 | } | |
4729 | ||
4730 | len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf)); | |
4731 | if (len < 0) { | |
4732 | DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n"); | |
4733 | return; | |
4734 | } | |
4735 | ||
4736 | if (len != infoframe_size) { | |
4737 | DRM_DEBUG_KMS("wrong static hdr metadata size\n"); | |
4738 | return; | |
4739 | } | |
4740 | ||
4741 | /* | |
4742 | * Set up the infoframe sdp packet for HDR static metadata. | |
4743 | * Prepare VSC Header for SU as per DP 1.4a spec, | |
4744 | * Table 2-100 and Table 2-101 | |
4745 | */ | |
4746 | ||
4747 | /* Packet ID, 00h for non-Audio INFOFRAME */ | |
4748 | infoframe_sdp.sdp_header.HB0 = 0; | |
4749 | /* | |
4750 | * Packet Type 80h + Non-audio INFOFRAME Type value | |
4751 | * HDMI_INFOFRAME_TYPE_DRM: 0x87, | |
4752 | */ | |
4753 | infoframe_sdp.sdp_header.HB1 = drm_infoframe.type; | |
4754 | /* | |
4755 | * Least Significant Eight Bits of (Data Byte Count – 1) | |
4756 | * infoframe_size - 1, | |
4757 | */ | |
4758 | infoframe_sdp.sdp_header.HB2 = 0x1D; | |
4759 | /* INFOFRAME SDP Version Number */ | |
4760 | infoframe_sdp.sdp_header.HB3 = (0x13 << 2); | |
4761 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ | |
4762 | infoframe_sdp.db[0] = drm_infoframe.version; | |
4763 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ | |
4764 | infoframe_sdp.db[1] = drm_infoframe.length; | |
4765 | /* | |
4766 | * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after | |
4767 | * HDMI_INFOFRAME_HEADER_SIZE | |
4768 | */ | |
4769 | BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2); | |
4770 | memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], | |
4771 | HDMI_DRM_INFOFRAME_SIZE); | |
4772 | ||
4773 | /* | |
4774 | * Size of DP infoframe sdp packet for HDR static metadata is consist of | |
4775 | * - DP SDP Header(struct dp_sdp_header): 4 bytes | |
4776 | * - Two Data Blocks: 2 bytes | |
4777 | * CTA Header Byte2 (INFOFRAME Version Number) | |
4778 | * CTA Header Byte3 (Length of INFOFRAME) | |
4779 | * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes | |
4780 | * | |
4781 | * Prior to GEN11's GMP register size is identical to DP HDR static metadata | |
4782 | * infoframe size. But GEN11+ has larger than that size, write_infoframe | |
4783 | * will pad rest of the size. | |
4784 | */ | |
4785 | intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state, | |
4786 | HDMI_PACKET_TYPE_GAMUT_METADATA, | |
4787 | &infoframe_sdp, | |
4788 | sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE); | |
4789 | } | |
4790 | ||
bb71fb00 GM |
4791 | void intel_dp_vsc_enable(struct intel_dp *intel_dp, |
4792 | const struct intel_crtc_state *crtc_state, | |
4793 | const struct drm_connector_state *conn_state) | |
3c053a96 | 4794 | { |
0c06fa15 | 4795 | if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) |
3c053a96 GM |
4796 | return; |
4797 | ||
bb71fb00 | 4798 | intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state); |
3c053a96 GM |
4799 | } |
4800 | ||
b246cf21 GM |
4801 | void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp, |
4802 | const struct intel_crtc_state *crtc_state, | |
4803 | const struct drm_connector_state *conn_state) | |
4804 | { | |
4805 | if (!conn_state->hdr_output_metadata) | |
4806 | return; | |
4807 | ||
4808 | intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp, | |
4809 | crtc_state, | |
4810 | conn_state); | |
4811 | } | |
4812 | ||
830de422 | 4813 | static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
c5d5ab7a | 4814 | { |
da15f7cb | 4815 | int status = 0; |
140ef138 | 4816 | int test_link_rate; |
830de422 | 4817 | u8 test_lane_count, test_link_bw; |
da15f7cb MN |
4818 | /* (DP CTS 1.2) |
4819 | * 4.3.1.11 | |
4820 | */ | |
4821 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
4822 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
4823 | &test_lane_count); | |
4824 | ||
4825 | if (status <= 0) { | |
4826 | DRM_DEBUG_KMS("Lane count read failed\n"); | |
4827 | return DP_TEST_NAK; | |
4828 | } | |
4829 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
da15f7cb MN |
4830 | |
4831 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
4832 | &test_link_bw); | |
4833 | if (status <= 0) { | |
4834 | DRM_DEBUG_KMS("Link Rate read failed\n"); | |
4835 | return DP_TEST_NAK; | |
4836 | } | |
da15f7cb | 4837 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); |
140ef138 MN |
4838 | |
4839 | /* Validate the requested link rate and lane count */ | |
4840 | if (!intel_dp_link_params_valid(intel_dp, test_link_rate, | |
4841 | test_lane_count)) | |
da15f7cb MN |
4842 | return DP_TEST_NAK; |
4843 | ||
4844 | intel_dp->compliance.test_lane_count = test_lane_count; | |
4845 | intel_dp->compliance.test_link_rate = test_link_rate; | |
4846 | ||
4847 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4848 | } |
4849 | ||
830de422 | 4850 | static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
c5d5ab7a | 4851 | { |
830de422 JN |
4852 | u8 test_pattern; |
4853 | u8 test_misc; | |
611032bf MN |
4854 | __be16 h_width, v_height; |
4855 | int status = 0; | |
4856 | ||
4857 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
010b9b39 JN |
4858 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, |
4859 | &test_pattern); | |
611032bf MN |
4860 | if (status <= 0) { |
4861 | DRM_DEBUG_KMS("Test pattern read failed\n"); | |
4862 | return DP_TEST_NAK; | |
4863 | } | |
4864 | if (test_pattern != DP_COLOR_RAMP) | |
4865 | return DP_TEST_NAK; | |
4866 | ||
4867 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
4868 | &h_width, 2); | |
4869 | if (status <= 0) { | |
4870 | DRM_DEBUG_KMS("H Width read failed\n"); | |
4871 | return DP_TEST_NAK; | |
4872 | } | |
4873 | ||
4874 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
4875 | &v_height, 2); | |
4876 | if (status <= 0) { | |
4877 | DRM_DEBUG_KMS("V Height read failed\n"); | |
4878 | return DP_TEST_NAK; | |
4879 | } | |
4880 | ||
010b9b39 JN |
4881 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, |
4882 | &test_misc); | |
611032bf MN |
4883 | if (status <= 0) { |
4884 | DRM_DEBUG_KMS("TEST MISC read failed\n"); | |
4885 | return DP_TEST_NAK; | |
4886 | } | |
4887 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
4888 | return DP_TEST_NAK; | |
4889 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
4890 | return DP_TEST_NAK; | |
4891 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
4892 | case DP_TEST_BIT_DEPTH_6: | |
4893 | intel_dp->compliance.test_data.bpc = 6; | |
4894 | break; | |
4895 | case DP_TEST_BIT_DEPTH_8: | |
4896 | intel_dp->compliance.test_data.bpc = 8; | |
4897 | break; | |
4898 | default: | |
4899 | return DP_TEST_NAK; | |
4900 | } | |
4901 | ||
4902 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
4903 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
4904 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
4905 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 4906 | intel_dp->compliance.test_active = true; |
611032bf MN |
4907 | |
4908 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4909 | } |
4910 | ||
830de422 | 4911 | static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) |
a60f0e38 | 4912 | { |
830de422 | 4913 | u8 test_result = DP_TEST_ACK; |
559be30c TP |
4914 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4915 | struct drm_connector *connector = &intel_connector->base; | |
4916 | ||
4917 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4918 | connector->edid_corrupt || |
559be30c TP |
4919 | intel_dp->aux.i2c_defer_count > 6) { |
4920 | /* Check EDID read for NACKs, DEFERs and corruption | |
4921 | * (DP CTS 1.2 Core r1.1) | |
4922 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4923 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4924 | * 4.2.2.6 : EDID corruption detected | |
4925 | * Use failsafe mode for all cases | |
4926 | */ | |
4927 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4928 | intel_dp->aux.i2c_defer_count > 0) | |
4929 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
4930 | intel_dp->aux.i2c_nack_count, | |
4931 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 4932 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 4933 | } else { |
f79b468e TS |
4934 | struct edid *block = intel_connector->detect_edid; |
4935 | ||
4936 | /* We have to write the checksum | |
4937 | * of the last block read | |
4938 | */ | |
4939 | block += intel_connector->detect_edid->extensions; | |
4940 | ||
010b9b39 JN |
4941 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, |
4942 | block->checksum) <= 0) | |
559be30c TP |
4943 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4944 | ||
4945 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 4946 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
4947 | } |
4948 | ||
4949 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 4950 | intel_dp->compliance.test_active = true; |
559be30c | 4951 | |
c5d5ab7a TP |
4952 | return test_result; |
4953 | } | |
4954 | ||
830de422 | 4955 | static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
a60f0e38 | 4956 | { |
830de422 | 4957 | u8 test_result = DP_TEST_NAK; |
c5d5ab7a TP |
4958 | return test_result; |
4959 | } | |
4960 | ||
4961 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4962 | { | |
830de422 JN |
4963 | u8 response = DP_TEST_NAK; |
4964 | u8 request = 0; | |
5ec63bbd | 4965 | int status; |
c5d5ab7a | 4966 | |
5ec63bbd | 4967 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a TP |
4968 | if (status <= 0) { |
4969 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
4970 | goto update_status; | |
4971 | } | |
4972 | ||
5ec63bbd | 4973 | switch (request) { |
c5d5ab7a TP |
4974 | case DP_TEST_LINK_TRAINING: |
4975 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
c5d5ab7a TP |
4976 | response = intel_dp_autotest_link_training(intel_dp); |
4977 | break; | |
4978 | case DP_TEST_LINK_VIDEO_PATTERN: | |
4979 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
c5d5ab7a TP |
4980 | response = intel_dp_autotest_video_pattern(intel_dp); |
4981 | break; | |
4982 | case DP_TEST_LINK_EDID_READ: | |
4983 | DRM_DEBUG_KMS("EDID test requested\n"); | |
c5d5ab7a TP |
4984 | response = intel_dp_autotest_edid(intel_dp); |
4985 | break; | |
4986 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
4987 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
c5d5ab7a TP |
4988 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4989 | break; | |
4990 | default: | |
5ec63bbd | 4991 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); |
c5d5ab7a TP |
4992 | break; |
4993 | } | |
4994 | ||
5ec63bbd JN |
4995 | if (response & DP_TEST_ACK) |
4996 | intel_dp->compliance.test_type = request; | |
4997 | ||
c5d5ab7a | 4998 | update_status: |
5ec63bbd | 4999 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a TP |
5000 | if (status <= 0) |
5001 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
5002 | } |
5003 | ||
0e32b39c DA |
5004 | static int |
5005 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
5006 | { | |
5007 | bool bret; | |
5008 | ||
5009 | if (intel_dp->is_mst) { | |
e8b2577c | 5010 | u8 esi[DP_DPRX_ESI_LEN] = { 0 }; |
0e32b39c DA |
5011 | int ret = 0; |
5012 | int retry; | |
5013 | bool handled; | |
45ef40aa DP |
5014 | |
5015 | WARN_ON_ONCE(intel_dp->active_mst_links < 0); | |
0e32b39c DA |
5016 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
5017 | go_again: | |
5018 | if (bret == true) { | |
5019 | ||
5020 | /* check link status - esi[10] = 0x200c */ | |
45ef40aa | 5021 | if (intel_dp->active_mst_links > 0 && |
901c2daf | 5022 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
5023 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
5024 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
5025 | intel_dp_stop_link_train(intel_dp); |
5026 | } | |
5027 | ||
6f34cc39 | 5028 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
5029 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
5030 | ||
5031 | if (handled) { | |
5032 | for (retry = 0; retry < 3; retry++) { | |
5033 | int wret; | |
5034 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
5035 | DP_SINK_COUNT_ESI+1, | |
5036 | &esi[1], 3); | |
5037 | if (wret == 3) { | |
5038 | break; | |
5039 | } | |
5040 | } | |
5041 | ||
5042 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
5043 | if (bret == true) { | |
6f34cc39 | 5044 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
5045 | goto go_again; |
5046 | } | |
5047 | } else | |
5048 | ret = 0; | |
5049 | ||
5050 | return ret; | |
5051 | } else { | |
0e32b39c DA |
5052 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); |
5053 | intel_dp->is_mst = false; | |
6cbb55c0 LP |
5054 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
5055 | intel_dp->is_mst); | |
0e32b39c DA |
5056 | } |
5057 | } | |
5058 | return -EINVAL; | |
5059 | } | |
5060 | ||
c85d200e VS |
5061 | static bool |
5062 | intel_dp_needs_link_retrain(struct intel_dp *intel_dp) | |
5063 | { | |
5064 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
5065 | ||
edb2e530 | 5066 | if (!intel_dp->link_trained) |
2f8e7ea9 JRS |
5067 | return false; |
5068 | ||
5069 | /* | |
5070 | * While PSR source HW is enabled, it will control main-link sending | |
5071 | * frames, enabling and disabling it so trying to do a retrain will fail | |
5072 | * as the link would or not be on or it could mix training patterns | |
5073 | * and frame data at the same time causing retrain to fail. | |
5074 | * Also when exiting PSR, HW will retrain the link anyways fixing | |
5075 | * any link status error. | |
5076 | */ | |
5077 | if (intel_psr_enabled(intel_dp)) | |
edb2e530 VS |
5078 | return false; |
5079 | ||
5080 | if (!intel_dp_get_link_status(intel_dp, link_status)) | |
c85d200e | 5081 | return false; |
c85d200e VS |
5082 | |
5083 | /* | |
5084 | * Validate the cached values of intel_dp->link_rate and | |
5085 | * intel_dp->lane_count before attempting to retrain. | |
5086 | */ | |
5087 | if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, | |
5088 | intel_dp->lane_count)) | |
5089 | return false; | |
5090 | ||
5091 | /* Retrain if Channel EQ or CR not ok */ | |
5092 | return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); | |
5093 | } | |
5094 | ||
c85d200e VS |
5095 | int intel_dp_retrain_link(struct intel_encoder *encoder, |
5096 | struct drm_modeset_acquire_ctx *ctx) | |
bfd02b3c | 5097 | { |
bfd02b3c | 5098 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 5099 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
c85d200e VS |
5100 | struct intel_connector *connector = intel_dp->attached_connector; |
5101 | struct drm_connector_state *conn_state; | |
5102 | struct intel_crtc_state *crtc_state; | |
5103 | struct intel_crtc *crtc; | |
5104 | int ret; | |
5105 | ||
5106 | /* FIXME handle the MST connectors as well */ | |
5107 | ||
5108 | if (!connector || connector->base.status != connector_status_connected) | |
5109 | return 0; | |
5110 | ||
5111 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
5112 | ctx); | |
5113 | if (ret) | |
5114 | return ret; | |
5115 | ||
5116 | conn_state = connector->base.state; | |
5117 | ||
5118 | crtc = to_intel_crtc(conn_state->crtc); | |
5119 | if (!crtc) | |
5120 | return 0; | |
5121 | ||
5122 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
5123 | if (ret) | |
5124 | return ret; | |
5125 | ||
5126 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
5127 | ||
5128 | WARN_ON(!intel_crtc_has_dp_encoder(crtc_state)); | |
5129 | ||
1326a92c | 5130 | if (!crtc_state->hw.active) |
c85d200e VS |
5131 | return 0; |
5132 | ||
5133 | if (conn_state->commit && | |
5134 | !try_wait_for_completion(&conn_state->commit->hw_done)) | |
5135 | return 0; | |
5136 | ||
5137 | if (!intel_dp_needs_link_retrain(intel_dp)) | |
5138 | return 0; | |
bfd02b3c VS |
5139 | |
5140 | /* Suppress underruns caused by re-training */ | |
5141 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
f56f6648 | 5142 | if (crtc_state->has_pch_encoder) |
bfd02b3c VS |
5143 | intel_set_pch_fifo_underrun_reporting(dev_priv, |
5144 | intel_crtc_pch_transcoder(crtc), false); | |
5145 | ||
5146 | intel_dp_start_link_train(intel_dp); | |
5147 | intel_dp_stop_link_train(intel_dp); | |
5148 | ||
5149 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 5150 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
5151 | |
5152 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
f56f6648 | 5153 | if (crtc_state->has_pch_encoder) |
bfd02b3c VS |
5154 | intel_set_pch_fifo_underrun_reporting(dev_priv, |
5155 | intel_crtc_pch_transcoder(crtc), true); | |
c85d200e VS |
5156 | |
5157 | return 0; | |
bfd02b3c VS |
5158 | } |
5159 | ||
c85d200e VS |
5160 | /* |
5161 | * If display is now connected check links status, | |
5162 | * there has been known issues of link loss triggering | |
5163 | * long pulse. | |
5164 | * | |
5165 | * Some sinks (eg. ASUS PB287Q) seem to perform some | |
5166 | * weird HPD ping pong during modesets. So we can apparently | |
5167 | * end up with HPD going low during a modeset, and then | |
5168 | * going back up soon after. And once that happens we must | |
5169 | * retrain the link to get a picture. That's in case no | |
5170 | * userspace component reacted to intermittent HPD dip. | |
5171 | */ | |
3944709d ID |
5172 | static enum intel_hotplug_state |
5173 | intel_dp_hotplug(struct intel_encoder *encoder, | |
5174 | struct intel_connector *connector, | |
5175 | bool irq_received) | |
5c9114d0 | 5176 | { |
c85d200e | 5177 | struct drm_modeset_acquire_ctx ctx; |
3944709d | 5178 | enum intel_hotplug_state state; |
c85d200e | 5179 | int ret; |
5c9114d0 | 5180 | |
3944709d | 5181 | state = intel_encoder_hotplug(encoder, connector, irq_received); |
5c9114d0 | 5182 | |
c85d200e | 5183 | drm_modeset_acquire_init(&ctx, 0); |
42e5e657 | 5184 | |
c85d200e VS |
5185 | for (;;) { |
5186 | ret = intel_dp_retrain_link(encoder, &ctx); | |
5c9114d0 | 5187 | |
c85d200e VS |
5188 | if (ret == -EDEADLK) { |
5189 | drm_modeset_backoff(&ctx); | |
5190 | continue; | |
5191 | } | |
5c9114d0 | 5192 | |
c85d200e VS |
5193 | break; |
5194 | } | |
d4cb3fd9 | 5195 | |
c85d200e VS |
5196 | drm_modeset_drop_locks(&ctx); |
5197 | drm_modeset_acquire_fini(&ctx); | |
5198 | WARN(ret, "Acquiring modeset locks failed with %i\n", ret); | |
bfd02b3c | 5199 | |
bb80c925 JRS |
5200 | /* |
5201 | * Keeping it consistent with intel_ddi_hotplug() and | |
5202 | * intel_hdmi_hotplug(). | |
5203 | */ | |
5204 | if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) | |
5205 | state = INTEL_HOTPLUG_RETRY; | |
5206 | ||
3944709d | 5207 | return state; |
5c9114d0 SS |
5208 | } |
5209 | ||
9844bc87 DP |
5210 | static void intel_dp_check_service_irq(struct intel_dp *intel_dp) |
5211 | { | |
5212 | u8 val; | |
5213 | ||
5214 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
5215 | return; | |
5216 | ||
5217 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
5218 | DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) | |
5219 | return; | |
5220 | ||
5221 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); | |
5222 | ||
5223 | if (val & DP_AUTOMATED_TEST_REQUEST) | |
5224 | intel_dp_handle_test_request(intel_dp); | |
5225 | ||
342ac601 | 5226 | if (val & DP_CP_IRQ) |
09d56393 | 5227 | intel_hdcp_handle_cp_irq(intel_dp->attached_connector); |
342ac601 R |
5228 | |
5229 | if (val & DP_SINK_SPECIFIC_IRQ) | |
5230 | DRM_DEBUG_DRIVER("Sink specific irq unhandled\n"); | |
9844bc87 DP |
5231 | } |
5232 | ||
a4fc5ed6 KP |
5233 | /* |
5234 | * According to DP spec | |
5235 | * 5.1.2: | |
5236 | * 1. Read DPCD | |
5237 | * 2. Configure link according to Receiver Capabilities | |
5238 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
5239 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
5240 | * |
5241 | * intel_dp_short_pulse - handles short pulse interrupts | |
5242 | * when full detection is not required. | |
5243 | * Returns %true if short pulse is handled and full detection | |
5244 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 5245 | */ |
39ff747b | 5246 | static bool |
5c9114d0 | 5247 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 5248 | { |
de25eb7f | 5249 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
39ff747b SS |
5250 | u8 old_sink_count = intel_dp->sink_count; |
5251 | bool ret; | |
5b215bcf | 5252 | |
4df6960e SS |
5253 | /* |
5254 | * Clearing compliance test variables to allow capturing | |
5255 | * of values for next automated test request. | |
5256 | */ | |
c1617abc | 5257 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 5258 | |
39ff747b SS |
5259 | /* |
5260 | * Now read the DPCD to see if it's actually running | |
5261 | * If the current value of sink count doesn't match with | |
5262 | * the value that was stored earlier or dpcd read failed | |
5263 | * we need to do full detection | |
5264 | */ | |
5265 | ret = intel_dp_get_dpcd(intel_dp); | |
5266 | ||
5267 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
5268 | /* No need to proceed if we are going to do full detect */ | |
5269 | return false; | |
59cd09e1 JB |
5270 | } |
5271 | ||
9844bc87 | 5272 | intel_dp_check_service_irq(intel_dp); |
a60f0e38 | 5273 | |
82e00d11 HV |
5274 | /* Handle CEC interrupts, if any */ |
5275 | drm_dp_cec_irq(&intel_dp->aux); | |
5276 | ||
c85d200e VS |
5277 | /* defer to the hotplug work for link retraining if needed */ |
5278 | if (intel_dp_needs_link_retrain(intel_dp)) | |
5279 | return false; | |
42e5e657 | 5280 | |
cc3054ff JRS |
5281 | intel_psr_short_pulse(intel_dp); |
5282 | ||
da15f7cb MN |
5283 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
5284 | DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); | |
5285 | /* Send a Hotplug Uevent to userspace to start modeset */ | |
2f773477 | 5286 | drm_kms_helper_hotplug_event(&dev_priv->drm); |
da15f7cb | 5287 | } |
39ff747b SS |
5288 | |
5289 | return true; | |
a4fc5ed6 | 5290 | } |
a4fc5ed6 | 5291 | |
caf9ab24 | 5292 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 5293 | static enum drm_connector_status |
26d61aad | 5294 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 5295 | { |
e393d0d6 | 5296 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
830de422 JN |
5297 | u8 *dpcd = intel_dp->dpcd; |
5298 | u8 type; | |
caf9ab24 | 5299 | |
ad5125d6 ID |
5300 | if (WARN_ON(intel_dp_is_edp(intel_dp))) |
5301 | return connector_status_connected; | |
5302 | ||
e393d0d6 ID |
5303 | if (lspcon->active) |
5304 | lspcon_resume(lspcon); | |
5305 | ||
caf9ab24 AJ |
5306 | if (!intel_dp_get_dpcd(intel_dp)) |
5307 | return connector_status_disconnected; | |
5308 | ||
5309 | /* if there's no downstream port, we're done */ | |
c726ad01 | 5310 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 5311 | return connector_status_connected; |
caf9ab24 AJ |
5312 | |
5313 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
5314 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
5315 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 5316 | |
30d9aa42 SS |
5317 | return intel_dp->sink_count ? |
5318 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
5319 | } |
5320 | ||
c4e3170a VS |
5321 | if (intel_dp_can_mst(intel_dp)) |
5322 | return connector_status_connected; | |
5323 | ||
caf9ab24 | 5324 | /* If no HPD, poke DDC gently */ |
0b99836f | 5325 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 5326 | return connector_status_connected; |
caf9ab24 AJ |
5327 | |
5328 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
5329 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
5330 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
5331 | if (type == DP_DS_PORT_TYPE_VGA || | |
5332 | type == DP_DS_PORT_TYPE_NON_EDID) | |
5333 | return connector_status_unknown; | |
5334 | } else { | |
5335 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
5336 | DP_DWN_STRM_PORT_TYPE_MASK; | |
5337 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
5338 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
5339 | return connector_status_unknown; | |
5340 | } | |
caf9ab24 AJ |
5341 | |
5342 | /* Anything else is out of spec, warn and ignore */ | |
5343 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 5344 | return connector_status_disconnected; |
71ba9000 AJ |
5345 | } |
5346 | ||
d410b56d CW |
5347 | static enum drm_connector_status |
5348 | edp_detect(struct intel_dp *intel_dp) | |
5349 | { | |
b93b41af | 5350 | return connector_status_connected; |
d410b56d CW |
5351 | } |
5352 | ||
7533eb4f | 5353 | static bool ibx_digital_port_connected(struct intel_encoder *encoder) |
5eb08b69 | 5354 | { |
7533eb4f | 5355 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b93433cc | 5356 | u32 bit; |
01cb9ea6 | 5357 | |
7533eb4f RV |
5358 | switch (encoder->hpd_pin) { |
5359 | case HPD_PORT_B: | |
0df53b77 JN |
5360 | bit = SDE_PORTB_HOTPLUG; |
5361 | break; | |
7533eb4f | 5362 | case HPD_PORT_C: |
0df53b77 JN |
5363 | bit = SDE_PORTC_HOTPLUG; |
5364 | break; | |
7533eb4f | 5365 | case HPD_PORT_D: |
0df53b77 JN |
5366 | bit = SDE_PORTD_HOTPLUG; |
5367 | break; | |
5368 | default: | |
7533eb4f | 5369 | MISSING_CASE(encoder->hpd_pin); |
0df53b77 JN |
5370 | return false; |
5371 | } | |
5372 | ||
5373 | return I915_READ(SDEISR) & bit; | |
5374 | } | |
5375 | ||
7533eb4f | 5376 | static bool cpt_digital_port_connected(struct intel_encoder *encoder) |
0df53b77 | 5377 | { |
7533eb4f | 5378 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0df53b77 JN |
5379 | u32 bit; |
5380 | ||
7533eb4f RV |
5381 | switch (encoder->hpd_pin) { |
5382 | case HPD_PORT_B: | |
0df53b77 JN |
5383 | bit = SDE_PORTB_HOTPLUG_CPT; |
5384 | break; | |
7533eb4f | 5385 | case HPD_PORT_C: |
0df53b77 JN |
5386 | bit = SDE_PORTC_HOTPLUG_CPT; |
5387 | break; | |
7533eb4f | 5388 | case HPD_PORT_D: |
0df53b77 JN |
5389 | bit = SDE_PORTD_HOTPLUG_CPT; |
5390 | break; | |
93e5f0b6 | 5391 | default: |
7533eb4f | 5392 | MISSING_CASE(encoder->hpd_pin); |
93e5f0b6 VS |
5393 | return false; |
5394 | } | |
5395 | ||
5396 | return I915_READ(SDEISR) & bit; | |
5397 | } | |
5398 | ||
7533eb4f | 5399 | static bool spt_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 5400 | { |
7533eb4f | 5401 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
93e5f0b6 VS |
5402 | u32 bit; |
5403 | ||
7533eb4f RV |
5404 | switch (encoder->hpd_pin) { |
5405 | case HPD_PORT_A: | |
93e5f0b6 VS |
5406 | bit = SDE_PORTA_HOTPLUG_SPT; |
5407 | break; | |
7533eb4f | 5408 | case HPD_PORT_E: |
a78695d3 JN |
5409 | bit = SDE_PORTE_HOTPLUG_SPT; |
5410 | break; | |
0df53b77 | 5411 | default: |
7533eb4f | 5412 | return cpt_digital_port_connected(encoder); |
b93433cc | 5413 | } |
1b469639 | 5414 | |
b93433cc | 5415 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
5416 | } |
5417 | ||
7533eb4f | 5418 | static bool g4x_digital_port_connected(struct intel_encoder *encoder) |
a4fc5ed6 | 5419 | { |
7533eb4f | 5420 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c | 5421 | u32 bit; |
5eb08b69 | 5422 | |
7533eb4f RV |
5423 | switch (encoder->hpd_pin) { |
5424 | case HPD_PORT_B: | |
9642c81c JN |
5425 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
5426 | break; | |
7533eb4f | 5427 | case HPD_PORT_C: |
9642c81c JN |
5428 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
5429 | break; | |
7533eb4f | 5430 | case HPD_PORT_D: |
9642c81c JN |
5431 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
5432 | break; | |
5433 | default: | |
7533eb4f | 5434 | MISSING_CASE(encoder->hpd_pin); |
9642c81c JN |
5435 | return false; |
5436 | } | |
5437 | ||
5438 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
5439 | } | |
5440 | ||
7533eb4f | 5441 | static bool gm45_digital_port_connected(struct intel_encoder *encoder) |
9642c81c | 5442 | { |
7533eb4f | 5443 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c JN |
5444 | u32 bit; |
5445 | ||
7533eb4f RV |
5446 | switch (encoder->hpd_pin) { |
5447 | case HPD_PORT_B: | |
0780cd36 | 5448 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 5449 | break; |
7533eb4f | 5450 | case HPD_PORT_C: |
0780cd36 | 5451 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 5452 | break; |
7533eb4f | 5453 | case HPD_PORT_D: |
0780cd36 | 5454 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
5455 | break; |
5456 | default: | |
7533eb4f | 5457 | MISSING_CASE(encoder->hpd_pin); |
9642c81c | 5458 | return false; |
a4fc5ed6 KP |
5459 | } |
5460 | ||
1d245987 | 5461 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
5462 | } |
5463 | ||
7533eb4f | 5464 | static bool ilk_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 5465 | { |
7533eb4f RV |
5466 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5467 | ||
5468 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
5469 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG; |
5470 | else | |
7533eb4f | 5471 | return ibx_digital_port_connected(encoder); |
93e5f0b6 VS |
5472 | } |
5473 | ||
7533eb4f | 5474 | static bool snb_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 5475 | { |
7533eb4f RV |
5476 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5477 | ||
5478 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
5479 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG; |
5480 | else | |
7533eb4f | 5481 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
5482 | } |
5483 | ||
7533eb4f | 5484 | static bool ivb_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 5485 | { |
7533eb4f RV |
5486 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5487 | ||
5488 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
5489 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB; |
5490 | else | |
7533eb4f | 5491 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
5492 | } |
5493 | ||
7533eb4f | 5494 | static bool bdw_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 5495 | { |
7533eb4f RV |
5496 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5497 | ||
5498 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
5499 | return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; |
5500 | else | |
7533eb4f | 5501 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
5502 | } |
5503 | ||
7533eb4f | 5504 | static bool bxt_digital_port_connected(struct intel_encoder *encoder) |
e464bfde | 5505 | { |
7533eb4f | 5506 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e464bfde JN |
5507 | u32 bit; |
5508 | ||
7533eb4f RV |
5509 | switch (encoder->hpd_pin) { |
5510 | case HPD_PORT_A: | |
e464bfde JN |
5511 | bit = BXT_DE_PORT_HP_DDIA; |
5512 | break; | |
7533eb4f | 5513 | case HPD_PORT_B: |
e464bfde JN |
5514 | bit = BXT_DE_PORT_HP_DDIB; |
5515 | break; | |
7533eb4f | 5516 | case HPD_PORT_C: |
e464bfde JN |
5517 | bit = BXT_DE_PORT_HP_DDIC; |
5518 | break; | |
5519 | default: | |
7533eb4f | 5520 | MISSING_CASE(encoder->hpd_pin); |
e464bfde JN |
5521 | return false; |
5522 | } | |
5523 | ||
5524 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
5525 | } | |
5526 | ||
3d1e388d MR |
5527 | static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv, |
5528 | enum phy phy) | |
b9fcddab | 5529 | { |
3d1e388d | 5530 | if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) |
53448aed VK |
5531 | return I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); |
5532 | ||
3d1e388d | 5533 | return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(phy); |
b9fcddab PZ |
5534 | } |
5535 | ||
9695cde6 | 5536 | static bool icp_digital_port_connected(struct intel_encoder *encoder) |
b9fcddab PZ |
5537 | { |
5538 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 5539 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
d8fe2ab6 | 5540 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
b9fcddab | 5541 | |
d8fe2ab6 | 5542 | if (intel_phy_is_combo(dev_priv, phy)) |
3d1e388d | 5543 | return intel_combo_phy_connected(dev_priv, phy); |
d8fe2ab6 | 5544 | else if (intel_phy_is_tc(dev_priv, phy)) |
bc85328f | 5545 | return intel_tc_port_connected(dig_port); |
c0aa8344 | 5546 | else |
b9fcddab | 5547 | MISSING_CASE(encoder->hpd_pin); |
c0aa8344 MK |
5548 | |
5549 | return false; | |
b9fcddab PZ |
5550 | } |
5551 | ||
7e66bcf2 JN |
5552 | /* |
5553 | * intel_digital_port_connected - is the specified port connected? | |
7533eb4f | 5554 | * @encoder: intel_encoder |
7e66bcf2 | 5555 | * |
39d1e234 PZ |
5556 | * In cases where there's a connector physically connected but it can't be used |
5557 | * by our hardware we also return false, since the rest of the driver should | |
5558 | * pretty much treat the port as disconnected. This is relevant for type-C | |
5559 | * (starting on ICL) where there's ownership involved. | |
5560 | * | |
7533eb4f | 5561 | * Return %true if port is connected, %false otherwise. |
7e66bcf2 | 5562 | */ |
6cfe7ec0 | 5563 | static bool __intel_digital_port_connected(struct intel_encoder *encoder) |
7e66bcf2 | 5564 | { |
7533eb4f RV |
5565 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5566 | ||
b2ae318a | 5567 | if (HAS_GMCH(dev_priv)) { |
93e5f0b6 | 5568 | if (IS_GM45(dev_priv)) |
7533eb4f | 5569 | return gm45_digital_port_connected(encoder); |
93e5f0b6 | 5570 | else |
7533eb4f | 5571 | return g4x_digital_port_connected(encoder); |
93e5f0b6 VS |
5572 | } |
5573 | ||
9695cde6 MR |
5574 | if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) |
5575 | return icp_digital_port_connected(encoder); | |
5576 | else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) | |
210126bd | 5577 | return spt_digital_port_connected(encoder); |
cc3f90f0 | 5578 | else if (IS_GEN9_LP(dev_priv)) |
7533eb4f | 5579 | return bxt_digital_port_connected(encoder); |
cf819eff | 5580 | else if (IS_GEN(dev_priv, 8)) |
210126bd | 5581 | return bdw_digital_port_connected(encoder); |
cf819eff | 5582 | else if (IS_GEN(dev_priv, 7)) |
210126bd | 5583 | return ivb_digital_port_connected(encoder); |
cf819eff | 5584 | else if (IS_GEN(dev_priv, 6)) |
210126bd | 5585 | return snb_digital_port_connected(encoder); |
cf819eff | 5586 | else if (IS_GEN(dev_priv, 5)) |
210126bd RV |
5587 | return ilk_digital_port_connected(encoder); |
5588 | ||
5589 | MISSING_CASE(INTEL_GEN(dev_priv)); | |
5590 | return false; | |
7e66bcf2 JN |
5591 | } |
5592 | ||
6cfe7ec0 ID |
5593 | bool intel_digital_port_connected(struct intel_encoder *encoder) |
5594 | { | |
5595 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
96ac0813 | 5596 | bool is_connected = false; |
6cfe7ec0 | 5597 | intel_wakeref_t wakeref; |
6cfe7ec0 ID |
5598 | |
5599 | with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) | |
5600 | is_connected = __intel_digital_port_connected(encoder); | |
5601 | ||
5602 | return is_connected; | |
5603 | } | |
5604 | ||
8c241fef | 5605 | static struct edid * |
beb60608 | 5606 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 5607 | { |
beb60608 | 5608 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 5609 | |
9cd300e0 JN |
5610 | /* use cached edid if we have one */ |
5611 | if (intel_connector->edid) { | |
9cd300e0 JN |
5612 | /* invalid edid */ |
5613 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
5614 | return NULL; |
5615 | ||
55e9edeb | 5616 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
5617 | } else |
5618 | return drm_get_edid(&intel_connector->base, | |
5619 | &intel_dp->aux.ddc); | |
5620 | } | |
8c241fef | 5621 | |
beb60608 CW |
5622 | static void |
5623 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
5624 | { | |
5625 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
5626 | struct edid *edid; | |
8c241fef | 5627 | |
f21a2198 | 5628 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
5629 | edid = intel_dp_get_edid(intel_dp); |
5630 | intel_connector->detect_edid = edid; | |
5631 | ||
e6b72c94 | 5632 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
82e00d11 | 5633 | drm_dp_cec_set_edid(&intel_dp->aux, edid); |
8c241fef KP |
5634 | } |
5635 | ||
beb60608 CW |
5636 | static void |
5637 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 5638 | { |
beb60608 | 5639 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 5640 | |
82e00d11 | 5641 | drm_dp_cec_unset_edid(&intel_dp->aux); |
beb60608 CW |
5642 | kfree(intel_connector->detect_edid); |
5643 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 5644 | |
beb60608 CW |
5645 | intel_dp->has_audio = false; |
5646 | } | |
d6f24d0f | 5647 | |
6c5ed5ae | 5648 | static int |
cbfa8ac8 DP |
5649 | intel_dp_detect(struct drm_connector *connector, |
5650 | struct drm_modeset_acquire_ctx *ctx, | |
5651 | bool force) | |
a9756bb5 | 5652 | { |
cbfa8ac8 | 5653 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
43a6d19c | 5654 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
337837ac ID |
5655 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5656 | struct intel_encoder *encoder = &dig_port->base; | |
a9756bb5 | 5657 | enum drm_connector_status status; |
a9756bb5 | 5658 | |
cbfa8ac8 DP |
5659 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5660 | connector->base.id, connector->name); | |
2f773477 | 5661 | WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); |
6c5ed5ae | 5662 | |
b93b41af | 5663 | /* Can't disconnect eDP */ |
1853a9da | 5664 | if (intel_dp_is_edp(intel_dp)) |
d410b56d | 5665 | status = edp_detect(intel_dp); |
d5acd97f | 5666 | else if (intel_digital_port_connected(encoder)) |
c555a81d | 5667 | status = intel_dp_detect_dpcd(intel_dp); |
a9756bb5 | 5668 | else |
c555a81d ACO |
5669 | status = connector_status_disconnected; |
5670 | ||
5cb651a7 | 5671 | if (status == connector_status_disconnected) { |
c1617abc | 5672 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
93ac092f | 5673 | memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); |
4df6960e | 5674 | |
0e505a08 | 5675 | if (intel_dp->is_mst) { |
5676 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
5677 | intel_dp->is_mst, | |
5678 | intel_dp->mst_mgr.mst_state); | |
5679 | intel_dp->is_mst = false; | |
5680 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
5681 | intel_dp->is_mst); | |
5682 | } | |
5683 | ||
c8c8fb33 | 5684 | goto out; |
4df6960e | 5685 | } |
a9756bb5 | 5686 | |
d7e8ef02 | 5687 | if (intel_dp->reset_link_params) { |
540b0b7f JN |
5688 | /* Initial max link lane count */ |
5689 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
f482984a | 5690 | |
540b0b7f JN |
5691 | /* Initial max link rate */ |
5692 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
d7e8ef02 MN |
5693 | |
5694 | intel_dp->reset_link_params = false; | |
5695 | } | |
f482984a | 5696 | |
fe5a66f9 VS |
5697 | intel_dp_print_rates(intel_dp); |
5698 | ||
93ac092f MN |
5699 | /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ |
5700 | if (INTEL_GEN(dev_priv) >= 11) | |
5701 | intel_dp_get_dsc_sink_cap(intel_dp); | |
5702 | ||
c4e3170a VS |
5703 | intel_dp_configure_mst(intel_dp); |
5704 | ||
5705 | if (intel_dp->is_mst) { | |
f21a2198 SS |
5706 | /* |
5707 | * If we are in MST mode then this connector | |
5708 | * won't appear connected or have anything | |
5709 | * with EDID on it | |
5710 | */ | |
0e32b39c DA |
5711 | status = connector_status_disconnected; |
5712 | goto out; | |
f24f6eb9 DP |
5713 | } |
5714 | ||
5715 | /* | |
5716 | * Some external monitors do not signal loss of link synchronization | |
5717 | * with an IRQ_HPD, so force a link status check. | |
5718 | */ | |
47658556 DP |
5719 | if (!intel_dp_is_edp(intel_dp)) { |
5720 | int ret; | |
5721 | ||
5722 | ret = intel_dp_retrain_link(encoder, ctx); | |
6cfe7ec0 | 5723 | if (ret) |
47658556 | 5724 | return ret; |
47658556 | 5725 | } |
0e32b39c | 5726 | |
4df6960e SS |
5727 | /* |
5728 | * Clearing NACK and defer counts to get their exact values | |
5729 | * while reading EDID which are required by Compliance tests | |
5730 | * 4.2.2.4 and 4.2.2.5 | |
5731 | */ | |
5732 | intel_dp->aux.i2c_nack_count = 0; | |
5733 | intel_dp->aux.i2c_defer_count = 0; | |
5734 | ||
beb60608 | 5735 | intel_dp_set_edid(intel_dp); |
cbfa8ac8 DP |
5736 | if (intel_dp_is_edp(intel_dp) || |
5737 | to_intel_connector(connector)->detect_edid) | |
5cb651a7 | 5738 | status = connector_status_connected; |
c8c8fb33 | 5739 | |
9844bc87 | 5740 | intel_dp_check_service_irq(intel_dp); |
09b1eb13 | 5741 | |
c8c8fb33 | 5742 | out: |
5cb651a7 | 5743 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 5744 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 5745 | |
a8ddac7c ID |
5746 | /* |
5747 | * Make sure the refs for power wells enabled during detect are | |
5748 | * dropped to avoid a new detect cycle triggered by HPD polling. | |
5749 | */ | |
5750 | intel_display_power_flush_work(dev_priv); | |
5751 | ||
5cb651a7 | 5752 | return status; |
f21a2198 SS |
5753 | } |
5754 | ||
beb60608 CW |
5755 | static void |
5756 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 5757 | { |
43a6d19c | 5758 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
337837ac ID |
5759 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5760 | struct intel_encoder *intel_encoder = &dig_port->base; | |
25f78f58 | 5761 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
337837ac ID |
5762 | enum intel_display_power_domain aux_domain = |
5763 | intel_aux_power_domain(dig_port); | |
0e6e0be4 | 5764 | intel_wakeref_t wakeref; |
a4fc5ed6 | 5765 | |
beb60608 CW |
5766 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
5767 | connector->base.id, connector->name); | |
5768 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 5769 | |
beb60608 CW |
5770 | if (connector->status != connector_status_connected) |
5771 | return; | |
671dedd2 | 5772 | |
0e6e0be4 | 5773 | wakeref = intel_display_power_get(dev_priv, aux_domain); |
beb60608 CW |
5774 | |
5775 | intel_dp_set_edid(intel_dp); | |
5776 | ||
0e6e0be4 | 5777 | intel_display_power_put(dev_priv, aux_domain, wakeref); |
beb60608 CW |
5778 | } |
5779 | ||
5780 | static int intel_dp_get_modes(struct drm_connector *connector) | |
5781 | { | |
5782 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
5783 | struct edid *edid; | |
5784 | ||
5785 | edid = intel_connector->detect_edid; | |
5786 | if (edid) { | |
5787 | int ret = intel_connector_update_modes(connector, edid); | |
5788 | if (ret) | |
5789 | return ret; | |
5790 | } | |
32f9d658 | 5791 | |
f8779fda | 5792 | /* if eDP has no EDID, fall back to fixed mode */ |
43a6d19c | 5793 | if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) && |
beb60608 | 5794 | intel_connector->panel.fixed_mode) { |
f8779fda | 5795 | struct drm_display_mode *mode; |
beb60608 CW |
5796 | |
5797 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 5798 | intel_connector->panel.fixed_mode); |
f8779fda | 5799 | if (mode) { |
32f9d658 ZW |
5800 | drm_mode_probed_add(connector, mode); |
5801 | return 1; | |
5802 | } | |
5803 | } | |
beb60608 | 5804 | |
32f9d658 | 5805 | return 0; |
a4fc5ed6 KP |
5806 | } |
5807 | ||
7a418e34 CW |
5808 | static int |
5809 | intel_dp_connector_register(struct drm_connector *connector) | |
5810 | { | |
43a6d19c | 5811 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
1ebaa0b9 CW |
5812 | int ret; |
5813 | ||
5814 | ret = intel_connector_register(connector); | |
5815 | if (ret) | |
5816 | return ret; | |
7a418e34 CW |
5817 | |
5818 | i915_debugfs_connector_add(connector); | |
5819 | ||
5820 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
5821 | intel_dp->aux.name, connector->kdev->kobj.name); | |
5822 | ||
5823 | intel_dp->aux.dev = connector->kdev; | |
82e00d11 HV |
5824 | ret = drm_dp_aux_register(&intel_dp->aux); |
5825 | if (!ret) | |
ae85b0df | 5826 | drm_dp_cec_register_connector(&intel_dp->aux, connector); |
82e00d11 | 5827 | return ret; |
7a418e34 CW |
5828 | } |
5829 | ||
c191eca1 CW |
5830 | static void |
5831 | intel_dp_connector_unregister(struct drm_connector *connector) | |
5832 | { | |
43a6d19c | 5833 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
82e00d11 HV |
5834 | |
5835 | drm_dp_cec_unregister_connector(&intel_dp->aux); | |
5836 | drm_dp_aux_unregister(&intel_dp->aux); | |
c191eca1 CW |
5837 | intel_connector_unregister(connector); |
5838 | } | |
5839 | ||
f6bff60e | 5840 | void intel_dp_encoder_flush_work(struct drm_encoder *encoder) |
24d05927 | 5841 | { |
b7d02c3a | 5842 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder)); |
da63a9f2 | 5843 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
24d05927 | 5844 | |
0e32b39c | 5845 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
1853a9da | 5846 | if (intel_dp_is_edp(intel_dp)) { |
69d93820 CW |
5847 | intel_wakeref_t wakeref; |
5848 | ||
bd943159 | 5849 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
951468f3 VS |
5850 | /* |
5851 | * vdd might still be enabled do to the delayed vdd off. | |
5852 | * Make sure vdd is actually turned off here. | |
5853 | */ | |
69d93820 CW |
5854 | with_pps_lock(intel_dp, wakeref) |
5855 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 5856 | |
01527b31 CT |
5857 | if (intel_dp->edp_notifier.notifier_call) { |
5858 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
5859 | intel_dp->edp_notifier.notifier_call = NULL; | |
5860 | } | |
bd943159 | 5861 | } |
99681886 CW |
5862 | |
5863 | intel_dp_aux_fini(intel_dp); | |
f6bff60e ID |
5864 | } |
5865 | ||
5866 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) | |
5867 | { | |
5868 | intel_dp_encoder_flush_work(encoder); | |
99681886 | 5869 | |
c8bd0e49 | 5870 | drm_encoder_cleanup(encoder); |
b7d02c3a | 5871 | kfree(enc_to_dig_port(to_intel_encoder(encoder))); |
24d05927 DV |
5872 | } |
5873 | ||
bf93ba67 | 5874 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b | 5875 | { |
b7d02c3a | 5876 | struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); |
69d93820 | 5877 | intel_wakeref_t wakeref; |
07f9cd0b | 5878 | |
1853a9da | 5879 | if (!intel_dp_is_edp(intel_dp)) |
07f9cd0b ID |
5880 | return; |
5881 | ||
951468f3 VS |
5882 | /* |
5883 | * vdd might still be enabled do to the delayed vdd off. | |
5884 | * Make sure vdd is actually turned off here. | |
5885 | */ | |
afa4e53a | 5886 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
69d93820 CW |
5887 | with_pps_lock(intel_dp, wakeref) |
5888 | edp_panel_vdd_off_sync(intel_dp); | |
07f9cd0b ID |
5889 | } |
5890 | ||
cf9cb35f R |
5891 | static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) |
5892 | { | |
5893 | long ret; | |
5894 | ||
5895 | #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) | |
5896 | ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, | |
5897 | msecs_to_jiffies(timeout)); | |
5898 | ||
5899 | if (!ret) | |
5900 | DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); | |
5901 | } | |
5902 | ||
20f24d77 SP |
5903 | static |
5904 | int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
5905 | u8 *an) | |
5906 | { | |
b7d02c3a | 5907 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base)); |
32078b72 VS |
5908 | static const struct drm_dp_aux_msg msg = { |
5909 | .request = DP_AUX_NATIVE_WRITE, | |
5910 | .address = DP_AUX_HDCP_AKSV, | |
5911 | .size = DRM_HDCP_KSV_LEN, | |
5912 | }; | |
830de422 | 5913 | u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0; |
20f24d77 SP |
5914 | ssize_t dpcd_ret; |
5915 | int ret; | |
5916 | ||
5917 | /* Output An first, that's easy */ | |
5918 | dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, | |
5919 | an, DRM_HDCP_AN_LEN); | |
5920 | if (dpcd_ret != DRM_HDCP_AN_LEN) { | |
3aae21fc R |
5921 | DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n", |
5922 | dpcd_ret); | |
20f24d77 SP |
5923 | return dpcd_ret >= 0 ? -EIO : dpcd_ret; |
5924 | } | |
5925 | ||
5926 | /* | |
5927 | * Since Aksv is Oh-So-Secret, we can't access it in software. So in | |
5928 | * order to get it on the wire, we need to create the AUX header as if | |
5929 | * we were writing the data, and then tickle the hardware to output the | |
5930 | * data once the header is sent out. | |
5931 | */ | |
32078b72 | 5932 | intel_dp_aux_header(txbuf, &msg); |
20f24d77 | 5933 | |
32078b72 | 5934 | ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size, |
8159c796 VS |
5935 | rxbuf, sizeof(rxbuf), |
5936 | DP_AUX_CH_CTL_AUX_AKSV_SELECT); | |
20f24d77 | 5937 | if (ret < 0) { |
3aae21fc | 5938 | DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret); |
20f24d77 SP |
5939 | return ret; |
5940 | } else if (ret == 0) { | |
3aae21fc | 5941 | DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n"); |
20f24d77 SP |
5942 | return -EIO; |
5943 | } | |
5944 | ||
5945 | reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK; | |
4cf74aaf R |
5946 | if (reply != DP_AUX_NATIVE_REPLY_ACK) { |
5947 | DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n", | |
5948 | reply); | |
5949 | return -EIO; | |
5950 | } | |
5951 | return 0; | |
20f24d77 SP |
5952 | } |
5953 | ||
5954 | static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
5955 | u8 *bksv) | |
5956 | { | |
5957 | ssize_t ret; | |
5958 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, | |
5959 | DRM_HDCP_KSV_LEN); | |
5960 | if (ret != DRM_HDCP_KSV_LEN) { | |
3aae21fc | 5961 | DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret); |
20f24d77 SP |
5962 | return ret >= 0 ? -EIO : ret; |
5963 | } | |
5964 | return 0; | |
5965 | } | |
5966 | ||
5967 | static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
5968 | u8 *bstatus) | |
5969 | { | |
5970 | ssize_t ret; | |
5971 | /* | |
5972 | * For some reason the HDMI and DP HDCP specs call this register | |
5973 | * definition by different names. In the HDMI spec, it's called BSTATUS, | |
5974 | * but in DP it's called BINFO. | |
5975 | */ | |
5976 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, | |
5977 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
5978 | if (ret != DRM_HDCP_BSTATUS_LEN) { | |
3aae21fc | 5979 | DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); |
20f24d77 SP |
5980 | return ret >= 0 ? -EIO : ret; |
5981 | } | |
5982 | return 0; | |
5983 | } | |
5984 | ||
5985 | static | |
791a98dd R |
5986 | int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, |
5987 | u8 *bcaps) | |
20f24d77 SP |
5988 | { |
5989 | ssize_t ret; | |
791a98dd | 5990 | |
20f24d77 | 5991 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, |
791a98dd | 5992 | bcaps, 1); |
20f24d77 | 5993 | if (ret != 1) { |
3aae21fc | 5994 | DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret); |
20f24d77 SP |
5995 | return ret >= 0 ? -EIO : ret; |
5996 | } | |
791a98dd R |
5997 | |
5998 | return 0; | |
5999 | } | |
6000 | ||
6001 | static | |
6002 | int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
6003 | bool *repeater_present) | |
6004 | { | |
6005 | ssize_t ret; | |
6006 | u8 bcaps; | |
6007 | ||
6008 | ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); | |
6009 | if (ret) | |
6010 | return ret; | |
6011 | ||
20f24d77 SP |
6012 | *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; |
6013 | return 0; | |
6014 | } | |
6015 | ||
6016 | static | |
6017 | int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
6018 | u8 *ri_prime) | |
6019 | { | |
6020 | ssize_t ret; | |
6021 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, | |
6022 | ri_prime, DRM_HDCP_RI_LEN); | |
6023 | if (ret != DRM_HDCP_RI_LEN) { | |
3aae21fc | 6024 | DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret); |
20f24d77 SP |
6025 | return ret >= 0 ? -EIO : ret; |
6026 | } | |
6027 | return 0; | |
6028 | } | |
6029 | ||
6030 | static | |
6031 | int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
6032 | bool *ksv_ready) | |
6033 | { | |
6034 | ssize_t ret; | |
6035 | u8 bstatus; | |
6036 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, | |
6037 | &bstatus, 1); | |
6038 | if (ret != 1) { | |
3aae21fc | 6039 | DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); |
20f24d77 SP |
6040 | return ret >= 0 ? -EIO : ret; |
6041 | } | |
6042 | *ksv_ready = bstatus & DP_BSTATUS_READY; | |
6043 | return 0; | |
6044 | } | |
6045 | ||
6046 | static | |
6047 | int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
6048 | int num_downstream, u8 *ksv_fifo) | |
6049 | { | |
6050 | ssize_t ret; | |
6051 | int i; | |
6052 | ||
6053 | /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ | |
6054 | for (i = 0; i < num_downstream; i += 3) { | |
6055 | size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; | |
6056 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6057 | DP_AUX_HDCP_KSV_FIFO, | |
6058 | ksv_fifo + i * DRM_HDCP_KSV_LEN, | |
6059 | len); | |
6060 | if (ret != len) { | |
3aae21fc R |
6061 | DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n", |
6062 | i, ret); | |
20f24d77 SP |
6063 | return ret >= 0 ? -EIO : ret; |
6064 | } | |
6065 | } | |
6066 | return 0; | |
6067 | } | |
6068 | ||
6069 | static | |
6070 | int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
6071 | int i, u32 *part) | |
6072 | { | |
6073 | ssize_t ret; | |
6074 | ||
6075 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
6076 | return -EINVAL; | |
6077 | ||
6078 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6079 | DP_AUX_HDCP_V_PRIME(i), part, | |
6080 | DRM_HDCP_V_PRIME_PART_LEN); | |
6081 | if (ret != DRM_HDCP_V_PRIME_PART_LEN) { | |
3aae21fc | 6082 | DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); |
20f24d77 SP |
6083 | return ret >= 0 ? -EIO : ret; |
6084 | } | |
6085 | return 0; | |
6086 | } | |
6087 | ||
6088 | static | |
6089 | int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
6090 | bool enable) | |
6091 | { | |
6092 | /* Not used for single stream DisplayPort setups */ | |
6093 | return 0; | |
6094 | } | |
6095 | ||
6096 | static | |
6097 | bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
6098 | { | |
6099 | ssize_t ret; | |
6100 | u8 bstatus; | |
b7fc1a9b | 6101 | |
20f24d77 SP |
6102 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, |
6103 | &bstatus, 1); | |
6104 | if (ret != 1) { | |
3aae21fc | 6105 | DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); |
b7fc1a9b | 6106 | return false; |
20f24d77 | 6107 | } |
b7fc1a9b | 6108 | |
20f24d77 SP |
6109 | return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); |
6110 | } | |
6111 | ||
791a98dd R |
6112 | static |
6113 | int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, | |
6114 | bool *hdcp_capable) | |
6115 | { | |
6116 | ssize_t ret; | |
6117 | u8 bcaps; | |
6118 | ||
6119 | ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); | |
6120 | if (ret) | |
6121 | return ret; | |
6122 | ||
6123 | *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; | |
6124 | return 0; | |
6125 | } | |
6126 | ||
238d3a9e R |
6127 | struct hdcp2_dp_errata_stream_type { |
6128 | u8 msg_id; | |
6129 | u8 stream_type; | |
6130 | } __packed; | |
6131 | ||
57bf7f43 | 6132 | struct hdcp2_dp_msg_data { |
238d3a9e R |
6133 | u8 msg_id; |
6134 | u32 offset; | |
6135 | bool msg_detectable; | |
6136 | u32 timeout; | |
6137 | u32 timeout2; /* Added for non_paired situation */ | |
57bf7f43 JN |
6138 | }; |
6139 | ||
e8465e1c | 6140 | static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { |
57bf7f43 JN |
6141 | { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 }, |
6142 | { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, | |
6143 | false, HDCP_2_2_CERT_TIMEOUT_MS, 0 }, | |
6144 | { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, | |
6145 | false, 0, 0 }, | |
6146 | { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, | |
6147 | false, 0, 0 }, | |
6148 | { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, | |
6149 | true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, | |
6150 | HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS }, | |
6151 | { HDCP_2_2_AKE_SEND_PAIRING_INFO, | |
6152 | DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, | |
6153 | HDCP_2_2_PAIRING_TIMEOUT_MS, 0 }, | |
6154 | { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 }, | |
6155 | { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, | |
6156 | false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 }, | |
6157 | { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, | |
6158 | 0, 0 }, | |
6159 | { HDCP_2_2_REP_SEND_RECVID_LIST, | |
6160 | DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, | |
6161 | HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 }, | |
6162 | { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, | |
6163 | 0, 0 }, | |
6164 | { HDCP_2_2_REP_STREAM_MANAGE, | |
6165 | DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, | |
6166 | 0, 0 }, | |
6167 | { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, | |
6168 | false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 }, | |
238d3a9e R |
6169 | /* local define to shovel this through the write_2_2 interface */ |
6170 | #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 | |
57bf7f43 JN |
6171 | { HDCP_2_2_ERRATA_DP_STREAM_TYPE, |
6172 | DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, | |
6173 | 0, 0 }, | |
6174 | }; | |
238d3a9e R |
6175 | |
6176 | static inline | |
6177 | int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, | |
6178 | u8 *rx_status) | |
6179 | { | |
6180 | ssize_t ret; | |
6181 | ||
6182 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6183 | DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, | |
6184 | HDCP_2_2_DP_RXSTATUS_LEN); | |
6185 | if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { | |
6186 | DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); | |
6187 | return ret >= 0 ? -EIO : ret; | |
6188 | } | |
6189 | ||
6190 | return 0; | |
6191 | } | |
6192 | ||
6193 | static | |
6194 | int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, | |
6195 | u8 msg_id, bool *msg_ready) | |
6196 | { | |
6197 | u8 rx_status; | |
6198 | int ret; | |
6199 | ||
6200 | *msg_ready = false; | |
6201 | ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); | |
6202 | if (ret < 0) | |
6203 | return ret; | |
6204 | ||
6205 | switch (msg_id) { | |
6206 | case HDCP_2_2_AKE_SEND_HPRIME: | |
6207 | if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) | |
6208 | *msg_ready = true; | |
6209 | break; | |
6210 | case HDCP_2_2_AKE_SEND_PAIRING_INFO: | |
6211 | if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) | |
6212 | *msg_ready = true; | |
6213 | break; | |
6214 | case HDCP_2_2_REP_SEND_RECVID_LIST: | |
6215 | if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) | |
6216 | *msg_ready = true; | |
6217 | break; | |
6218 | default: | |
6219 | DRM_ERROR("Unidentified msg_id: %d\n", msg_id); | |
6220 | return -EINVAL; | |
6221 | } | |
6222 | ||
6223 | return 0; | |
6224 | } | |
6225 | ||
6226 | static ssize_t | |
6227 | intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, | |
e8465e1c | 6228 | const struct hdcp2_dp_msg_data *hdcp2_msg_data) |
238d3a9e R |
6229 | { |
6230 | struct intel_dp *dp = &intel_dig_port->dp; | |
6231 | struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; | |
6232 | u8 msg_id = hdcp2_msg_data->msg_id; | |
6233 | int ret, timeout; | |
6234 | bool msg_ready = false; | |
6235 | ||
6236 | if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) | |
6237 | timeout = hdcp2_msg_data->timeout2; | |
6238 | else | |
6239 | timeout = hdcp2_msg_data->timeout; | |
6240 | ||
6241 | /* | |
6242 | * There is no way to detect the CERT, LPRIME and STREAM_READY | |
6243 | * availability. So Wait for timeout and read the msg. | |
6244 | */ | |
6245 | if (!hdcp2_msg_data->msg_detectable) { | |
6246 | mdelay(timeout); | |
6247 | ret = 0; | |
6248 | } else { | |
cf9cb35f R |
6249 | /* |
6250 | * As we want to check the msg availability at timeout, Ignoring | |
6251 | * the timeout at wait for CP_IRQ. | |
6252 | */ | |
6253 | intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); | |
6254 | ret = hdcp2_detect_msg_availability(intel_dig_port, | |
6255 | msg_id, &msg_ready); | |
238d3a9e R |
6256 | if (!msg_ready) |
6257 | ret = -ETIMEDOUT; | |
6258 | } | |
6259 | ||
6260 | if (ret) | |
6261 | DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n", | |
6262 | hdcp2_msg_data->msg_id, ret, timeout); | |
6263 | ||
6264 | return ret; | |
6265 | } | |
6266 | ||
e8465e1c | 6267 | static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) |
238d3a9e R |
6268 | { |
6269 | int i; | |
6270 | ||
3be3a877 JN |
6271 | for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) |
6272 | if (hdcp2_dp_msg_data[i].msg_id == msg_id) | |
6273 | return &hdcp2_dp_msg_data[i]; | |
238d3a9e R |
6274 | |
6275 | return NULL; | |
6276 | } | |
6277 | ||
6278 | static | |
6279 | int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, | |
6280 | void *buf, size_t size) | |
6281 | { | |
cf9cb35f R |
6282 | struct intel_dp *dp = &intel_dig_port->dp; |
6283 | struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; | |
238d3a9e R |
6284 | unsigned int offset; |
6285 | u8 *byte = buf; | |
6286 | ssize_t ret, bytes_to_write, len; | |
e8465e1c | 6287 | const struct hdcp2_dp_msg_data *hdcp2_msg_data; |
238d3a9e R |
6288 | |
6289 | hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); | |
6290 | if (!hdcp2_msg_data) | |
6291 | return -EINVAL; | |
6292 | ||
6293 | offset = hdcp2_msg_data->offset; | |
6294 | ||
6295 | /* No msg_id in DP HDCP2.2 msgs */ | |
6296 | bytes_to_write = size - 1; | |
6297 | byte++; | |
6298 | ||
cf9cb35f R |
6299 | hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); |
6300 | ||
238d3a9e R |
6301 | while (bytes_to_write) { |
6302 | len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? | |
6303 | DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; | |
6304 | ||
6305 | ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, | |
6306 | offset, (void *)byte, len); | |
6307 | if (ret < 0) | |
6308 | return ret; | |
6309 | ||
6310 | bytes_to_write -= ret; | |
6311 | byte += ret; | |
6312 | offset += ret; | |
6313 | } | |
6314 | ||
6315 | return size; | |
6316 | } | |
6317 | ||
6318 | static | |
6319 | ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) | |
6320 | { | |
6321 | u8 rx_info[HDCP_2_2_RXINFO_LEN]; | |
6322 | u32 dev_cnt; | |
6323 | ssize_t ret; | |
6324 | ||
6325 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6326 | DP_HDCP_2_2_REG_RXINFO_OFFSET, | |
6327 | (void *)rx_info, HDCP_2_2_RXINFO_LEN); | |
6328 | if (ret != HDCP_2_2_RXINFO_LEN) | |
6329 | return ret >= 0 ? -EIO : ret; | |
6330 | ||
6331 | dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | | |
6332 | HDCP_2_2_DEV_COUNT_LO(rx_info[1])); | |
6333 | ||
6334 | if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) | |
6335 | dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; | |
6336 | ||
6337 | ret = sizeof(struct hdcp2_rep_send_receiverid_list) - | |
6338 | HDCP_2_2_RECEIVER_IDS_MAX_LEN + | |
6339 | (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); | |
6340 | ||
6341 | return ret; | |
6342 | } | |
6343 | ||
6344 | static | |
6345 | int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, | |
6346 | u8 msg_id, void *buf, size_t size) | |
6347 | { | |
6348 | unsigned int offset; | |
6349 | u8 *byte = buf; | |
6350 | ssize_t ret, bytes_to_recv, len; | |
e8465e1c | 6351 | const struct hdcp2_dp_msg_data *hdcp2_msg_data; |
238d3a9e R |
6352 | |
6353 | hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); | |
6354 | if (!hdcp2_msg_data) | |
6355 | return -EINVAL; | |
6356 | offset = hdcp2_msg_data->offset; | |
6357 | ||
6358 | ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); | |
6359 | if (ret < 0) | |
6360 | return ret; | |
6361 | ||
6362 | if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { | |
6363 | ret = get_receiver_id_list_size(intel_dig_port); | |
6364 | if (ret < 0) | |
6365 | return ret; | |
6366 | ||
6367 | size = ret; | |
6368 | } | |
6369 | bytes_to_recv = size - 1; | |
6370 | ||
6371 | /* DP adaptation msgs has no msg_id */ | |
6372 | byte++; | |
6373 | ||
6374 | while (bytes_to_recv) { | |
6375 | len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? | |
6376 | DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; | |
6377 | ||
6378 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, | |
6379 | (void *)byte, len); | |
6380 | if (ret < 0) { | |
6381 | DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret); | |
6382 | return ret; | |
6383 | } | |
6384 | ||
6385 | bytes_to_recv -= ret; | |
6386 | byte += ret; | |
6387 | offset += ret; | |
6388 | } | |
6389 | byte = buf; | |
6390 | *byte = msg_id; | |
6391 | ||
6392 | return size; | |
6393 | } | |
6394 | ||
6395 | static | |
6396 | int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, | |
6397 | bool is_repeater, u8 content_type) | |
6398 | { | |
6399 | struct hdcp2_dp_errata_stream_type stream_type_msg; | |
6400 | ||
6401 | if (is_repeater) | |
6402 | return 0; | |
6403 | ||
6404 | /* | |
6405 | * Errata for DP: As Stream type is used for encryption, Receiver | |
6406 | * should be communicated with stream type for the decryption of the | |
6407 | * content. | |
6408 | * Repeater will be communicated with stream type as a part of it's | |
6409 | * auth later in time. | |
6410 | */ | |
6411 | stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; | |
6412 | stream_type_msg.stream_type = content_type; | |
6413 | ||
6414 | return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, | |
6415 | sizeof(stream_type_msg)); | |
6416 | } | |
6417 | ||
6418 | static | |
6419 | int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) | |
6420 | { | |
6421 | u8 rx_status; | |
6422 | int ret; | |
6423 | ||
6424 | ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); | |
6425 | if (ret) | |
6426 | return ret; | |
6427 | ||
6428 | if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) | |
6429 | ret = HDCP_REAUTH_REQUEST; | |
6430 | else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) | |
6431 | ret = HDCP_LINK_INTEGRITY_FAILURE; | |
6432 | else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) | |
6433 | ret = HDCP_TOPOLOGY_CHANGE; | |
6434 | ||
6435 | return ret; | |
6436 | } | |
6437 | ||
6438 | static | |
6439 | int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, | |
6440 | bool *capable) | |
6441 | { | |
6442 | u8 rx_caps[3]; | |
6443 | int ret; | |
6444 | ||
6445 | *capable = false; | |
6446 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6447 | DP_HDCP_2_2_REG_RX_CAPS_OFFSET, | |
6448 | rx_caps, HDCP_2_2_RXCAPS_LEN); | |
6449 | if (ret != HDCP_2_2_RXCAPS_LEN) | |
6450 | return ret >= 0 ? -EIO : ret; | |
6451 | ||
6452 | if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && | |
6453 | HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) | |
6454 | *capable = true; | |
6455 | ||
6456 | return 0; | |
6457 | } | |
6458 | ||
20f24d77 SP |
6459 | static const struct intel_hdcp_shim intel_dp_hdcp_shim = { |
6460 | .write_an_aksv = intel_dp_hdcp_write_an_aksv, | |
6461 | .read_bksv = intel_dp_hdcp_read_bksv, | |
6462 | .read_bstatus = intel_dp_hdcp_read_bstatus, | |
6463 | .repeater_present = intel_dp_hdcp_repeater_present, | |
6464 | .read_ri_prime = intel_dp_hdcp_read_ri_prime, | |
6465 | .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, | |
6466 | .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, | |
6467 | .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, | |
6468 | .toggle_signalling = intel_dp_hdcp_toggle_signalling, | |
6469 | .check_link = intel_dp_hdcp_check_link, | |
791a98dd | 6470 | .hdcp_capable = intel_dp_hdcp_capable, |
238d3a9e R |
6471 | .write_2_2_msg = intel_dp_hdcp2_write_msg, |
6472 | .read_2_2_msg = intel_dp_hdcp2_read_msg, | |
6473 | .config_stream_type = intel_dp_hdcp2_config_stream_type, | |
6474 | .check_2_2_link = intel_dp_hdcp2_check_link, | |
6475 | .hdcp_2_2_capable = intel_dp_hdcp2_capable, | |
6476 | .protocol = HDCP_PROTOCOL_DP, | |
20f24d77 SP |
6477 | }; |
6478 | ||
49e6bc51 VS |
6479 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
6480 | { | |
de25eb7f | 6481 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
337837ac | 6482 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
49e6bc51 VS |
6483 | |
6484 | lockdep_assert_held(&dev_priv->pps_mutex); | |
6485 | ||
6486 | if (!edp_have_panel_vdd(intel_dp)) | |
6487 | return; | |
6488 | ||
6489 | /* | |
6490 | * The VDD bit needs a power domain reference, so if the bit is | |
6491 | * already enabled when we boot or resume, grab this reference and | |
6492 | * schedule a vdd off, so we don't hold on to the reference | |
6493 | * indefinitely. | |
6494 | */ | |
6495 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
337837ac | 6496 | intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); |
49e6bc51 VS |
6497 | |
6498 | edp_panel_vdd_schedule_off(intel_dp); | |
6499 | } | |
6500 | ||
9f2bdb00 VS |
6501 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
6502 | { | |
de25eb7f | 6503 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
59b74c49 VS |
6504 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
6505 | enum pipe pipe; | |
9f2bdb00 | 6506 | |
59b74c49 VS |
6507 | if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg, |
6508 | encoder->port, &pipe)) | |
6509 | return pipe; | |
9f2bdb00 | 6510 | |
59b74c49 | 6511 | return INVALID_PIPE; |
9f2bdb00 VS |
6512 | } |
6513 | ||
bf93ba67 | 6514 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 6515 | { |
64989ca4 | 6516 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
b7d02c3a | 6517 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); |
dd75f6dd | 6518 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
69d93820 | 6519 | intel_wakeref_t wakeref; |
64989ca4 VS |
6520 | |
6521 | if (!HAS_DDI(dev_priv)) | |
6522 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 6523 | |
dd75f6dd | 6524 | if (lspcon->active) |
910530c0 SS |
6525 | lspcon_resume(lspcon); |
6526 | ||
d7e8ef02 MN |
6527 | intel_dp->reset_link_params = true; |
6528 | ||
b4c7ea63 ID |
6529 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6530 | !intel_dp_is_edp(intel_dp)) | |
6531 | return; | |
6532 | ||
69d93820 CW |
6533 | with_pps_lock(intel_dp, wakeref) { |
6534 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
6535 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
49e6bc51 | 6536 | |
69d93820 CW |
6537 | if (intel_dp_is_edp(intel_dp)) { |
6538 | /* | |
6539 | * Reinit the power sequencer, in case BIOS did | |
6540 | * something nasty with it. | |
6541 | */ | |
6542 | intel_dp_pps_init(intel_dp); | |
6543 | intel_edp_panel_vdd_sanitize(intel_dp); | |
6544 | } | |
9f2bdb00 | 6545 | } |
6d93c0c4 ID |
6546 | } |
6547 | ||
a4fc5ed6 | 6548 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
beb60608 | 6549 | .force = intel_dp_force, |
a4fc5ed6 | 6550 | .fill_modes = drm_helper_probe_single_connector_modes, |
8f647a01 ML |
6551 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
6552 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
7a418e34 | 6553 | .late_register = intel_dp_connector_register, |
c191eca1 | 6554 | .early_unregister = intel_dp_connector_unregister, |
d4b26e4f | 6555 | .destroy = intel_connector_destroy, |
c6f95f27 | 6556 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
8f647a01 | 6557 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
a4fc5ed6 KP |
6558 | }; |
6559 | ||
6560 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
6c5ed5ae | 6561 | .detect_ctx = intel_dp_detect, |
a4fc5ed6 KP |
6562 | .get_modes = intel_dp_get_modes, |
6563 | .mode_valid = intel_dp_mode_valid, | |
8f647a01 | 6564 | .atomic_check = intel_digital_connector_atomic_check, |
a4fc5ed6 KP |
6565 | }; |
6566 | ||
a4fc5ed6 | 6567 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 6568 | .reset = intel_dp_encoder_reset, |
24d05927 | 6569 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
6570 | }; |
6571 | ||
b2c5c181 | 6572 | enum irqreturn |
13cf5504 DA |
6573 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
6574 | { | |
6575 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 6576 | |
7a7f84cc VS |
6577 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
6578 | /* | |
6579 | * vdd off can generate a long pulse on eDP which | |
6580 | * would require vdd on to handle it, and thus we | |
6581 | * would end up in an endless cycle of | |
6582 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
6583 | */ | |
66a990dd VS |
6584 | DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n", |
6585 | intel_dig_port->base.base.base.id, | |
6586 | intel_dig_port->base.base.name); | |
a8b3d52f | 6587 | return IRQ_HANDLED; |
7a7f84cc VS |
6588 | } |
6589 | ||
66a990dd VS |
6590 | DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n", |
6591 | intel_dig_port->base.base.base.id, | |
6592 | intel_dig_port->base.base.name, | |
0e32b39c | 6593 | long_hpd ? "long" : "short"); |
13cf5504 | 6594 | |
27d4efc5 | 6595 | if (long_hpd) { |
d7e8ef02 | 6596 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
6597 | return IRQ_NONE; |
6598 | } | |
6599 | ||
27d4efc5 VS |
6600 | if (intel_dp->is_mst) { |
6601 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
6602 | /* | |
6603 | * If we were in MST mode, and device is not | |
6604 | * there, get out of MST mode | |
6605 | */ | |
6606 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
6607 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
6608 | intel_dp->is_mst = false; | |
6609 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
6610 | intel_dp->is_mst); | |
6f08ebe7 ID |
6611 | |
6612 | return IRQ_NONE; | |
0e32b39c | 6613 | } |
27d4efc5 | 6614 | } |
0e32b39c | 6615 | |
27d4efc5 | 6616 | if (!intel_dp->is_mst) { |
c85d200e | 6617 | bool handled; |
42e5e657 DV |
6618 | |
6619 | handled = intel_dp_short_pulse(intel_dp); | |
6620 | ||
cbfa8ac8 | 6621 | if (!handled) |
6f08ebe7 | 6622 | return IRQ_NONE; |
0e32b39c | 6623 | } |
b2c5c181 | 6624 | |
6f08ebe7 | 6625 | return IRQ_HANDLED; |
13cf5504 DA |
6626 | } |
6627 | ||
477ec328 | 6628 | /* check the VBT to see whether the eDP is on another port */ |
7b91bf7f | 6629 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 6630 | { |
53ce81a7 VS |
6631 | /* |
6632 | * eDP not supported on g4x. so bail out early just | |
6633 | * for a bit extra safety in case the VBT is bonkers. | |
6634 | */ | |
dd11bc10 | 6635 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
6636 | return false; |
6637 | ||
a98d9c1d | 6638 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
6639 | return true; |
6640 | ||
951d9efe | 6641 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
6642 | } |
6643 | ||
200819ab | 6644 | static void |
f684960e CW |
6645 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
6646 | { | |
8b45330a | 6647 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
68ec0736 VS |
6648 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
6649 | ||
6650 | if (!IS_G4X(dev_priv) && port != PORT_A) | |
6651 | intel_attach_force_audio_property(connector); | |
8b45330a | 6652 | |
e953fd7b | 6653 | intel_attach_broadcast_rgb_property(connector); |
b2ae318a | 6654 | if (HAS_GMCH(dev_priv)) |
f1a12172 RS |
6655 | drm_connector_attach_max_bpc_property(connector, 6, 10); |
6656 | else if (INTEL_GEN(dev_priv) >= 5) | |
6657 | drm_connector_attach_max_bpc_property(connector, 6, 12); | |
53b41837 | 6658 | |
9d1bb6f0 GM |
6659 | intel_attach_colorspace_property(connector); |
6660 | ||
0299dfa7 GM |
6661 | if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11) |
6662 | drm_object_attach_property(&connector->base, | |
6663 | connector->dev->mode_config.hdr_output_metadata_property, | |
6664 | 0); | |
6665 | ||
1853a9da | 6666 | if (intel_dp_is_edp(intel_dp)) { |
8b45330a ML |
6667 | u32 allowed_scalers; |
6668 | ||
6669 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
b2ae318a | 6670 | if (!HAS_GMCH(dev_priv)) |
8b45330a ML |
6671 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); |
6672 | ||
6673 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
6674 | ||
eead06df | 6675 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
8b45330a | 6676 | |
53b41837 | 6677 | } |
f684960e CW |
6678 | } |
6679 | ||
dada1a9f ID |
6680 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
6681 | { | |
d28d4731 | 6682 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
6683 | intel_dp->last_power_on = jiffies; |
6684 | intel_dp->last_backlight_off = jiffies; | |
6685 | } | |
6686 | ||
67a54566 | 6687 | static void |
46bd8383 | 6688 | intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) |
67a54566 | 6689 | { |
de25eb7f | 6690 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ab3517c1 | 6691 | u32 pp_on, pp_off, pp_ctl; |
8e8232d5 | 6692 | struct pps_registers regs; |
453c5420 | 6693 | |
46bd8383 | 6694 | intel_pps_get_registers(intel_dp, ®s); |
67a54566 | 6695 | |
9eae5e27 | 6696 | pp_ctl = ilk_get_pp_control(intel_dp); |
67a54566 | 6697 | |
1b61c4a3 JN |
6698 | /* Ensure PPS is unlocked */ |
6699 | if (!HAS_DDI(dev_priv)) | |
6700 | I915_WRITE(regs.pp_ctrl, pp_ctl); | |
6701 | ||
8e8232d5 ID |
6702 | pp_on = I915_READ(regs.pp_on); |
6703 | pp_off = I915_READ(regs.pp_off); | |
67a54566 DV |
6704 | |
6705 | /* Pull timing values out of registers */ | |
78b36b10 JN |
6706 | seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); |
6707 | seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); | |
6708 | seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); | |
6709 | seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); | |
67a54566 | 6710 | |
ab3517c1 JN |
6711 | if (i915_mmio_reg_valid(regs.pp_div)) { |
6712 | u32 pp_div; | |
6713 | ||
6714 | pp_div = I915_READ(regs.pp_div); | |
6715 | ||
78b36b10 | 6716 | seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; |
ab3517c1 | 6717 | } else { |
78b36b10 | 6718 | seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; |
b0a08bec | 6719 | } |
54648618 ID |
6720 | } |
6721 | ||
de9c1b6b ID |
6722 | static void |
6723 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
6724 | { | |
6725 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
6726 | state_name, | |
6727 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
6728 | } | |
6729 | ||
6730 | static void | |
46bd8383 | 6731 | intel_pps_verify_state(struct intel_dp *intel_dp) |
de9c1b6b ID |
6732 | { |
6733 | struct edp_power_seq hw; | |
6734 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
6735 | ||
46bd8383 | 6736 | intel_pps_readout_hw_state(intel_dp, &hw); |
de9c1b6b ID |
6737 | |
6738 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
6739 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
6740 | DRM_ERROR("PPS state mismatch\n"); | |
6741 | intel_pps_dump_state("sw", sw); | |
6742 | intel_pps_dump_state("hw", &hw); | |
6743 | } | |
6744 | } | |
6745 | ||
54648618 | 6746 | static void |
46bd8383 | 6747 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) |
54648618 | 6748 | { |
de25eb7f | 6749 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
54648618 ID |
6750 | struct edp_power_seq cur, vbt, spec, |
6751 | *final = &intel_dp->pps_delays; | |
6752 | ||
6753 | lockdep_assert_held(&dev_priv->pps_mutex); | |
6754 | ||
6755 | /* already initialized? */ | |
6756 | if (final->t11_t12 != 0) | |
6757 | return; | |
6758 | ||
46bd8383 | 6759 | intel_pps_readout_hw_state(intel_dp, &cur); |
67a54566 | 6760 | |
de9c1b6b | 6761 | intel_pps_dump_state("cur", &cur); |
67a54566 | 6762 | |
6aa23e65 | 6763 | vbt = dev_priv->vbt.edp.pps; |
c99a259b MN |
6764 | /* On Toshiba Satellite P50-C-18C system the VBT T12 delay |
6765 | * of 500ms appears to be too short. Ocassionally the panel | |
6766 | * just fails to power back on. Increasing the delay to 800ms | |
6767 | * seems sufficient to avoid this problem. | |
6768 | */ | |
6769 | if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { | |
7313f5a9 | 6770 | vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); |
c99a259b MN |
6771 | DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n", |
6772 | vbt.t11_t12); | |
6773 | } | |
770a17a5 MN |
6774 | /* T11_T12 delay is special and actually in units of 100ms, but zero |
6775 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
6776 | * table multiplies it with 1000 to make it in units of 100usec, | |
6777 | * too. */ | |
6778 | vbt.t11_t12 += 100 * 10; | |
67a54566 DV |
6779 | |
6780 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
6781 | * our hw here, which are all in 100usec. */ | |
6782 | spec.t1_t3 = 210 * 10; | |
6783 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
6784 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
6785 | spec.t10 = 500 * 10; | |
6786 | /* This one is special and actually in units of 100ms, but zero | |
6787 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
6788 | * table multiplies it with 1000 to make it in units of 100usec, | |
6789 | * too. */ | |
6790 | spec.t11_t12 = (510 + 100) * 10; | |
6791 | ||
de9c1b6b | 6792 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
6793 | |
6794 | /* Use the max of the register settings and vbt. If both are | |
6795 | * unset, fall back to the spec limits. */ | |
36b5f425 | 6796 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
6797 | spec.field : \ |
6798 | max(cur.field, vbt.field)) | |
6799 | assign_final(t1_t3); | |
6800 | assign_final(t8); | |
6801 | assign_final(t9); | |
6802 | assign_final(t10); | |
6803 | assign_final(t11_t12); | |
6804 | #undef assign_final | |
6805 | ||
36b5f425 | 6806 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
6807 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
6808 | intel_dp->backlight_on_delay = get_delay(t8); | |
6809 | intel_dp->backlight_off_delay = get_delay(t9); | |
6810 | intel_dp->panel_power_down_delay = get_delay(t10); | |
6811 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
6812 | #undef get_delay | |
6813 | ||
f30d26e4 JN |
6814 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
6815 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
6816 | intel_dp->panel_power_cycle_delay); | |
6817 | ||
6818 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
6819 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
6820 | |
6821 | /* | |
6822 | * We override the HW backlight delays to 1 because we do manual waits | |
6823 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
6824 | * don't do this, we'll end up waiting for the backlight off delay | |
6825 | * twice: once when we do the manual sleep, and once when we disable | |
6826 | * the panel and wait for the PP_STATUS bit to become zero. | |
6827 | */ | |
6828 | final->t8 = 1; | |
6829 | final->t9 = 1; | |
5643205c ID |
6830 | |
6831 | /* | |
6832 | * HW has only a 100msec granularity for t11_t12 so round it up | |
6833 | * accordingly. | |
6834 | */ | |
6835 | final->t11_t12 = roundup(final->t11_t12, 100 * 10); | |
f30d26e4 JN |
6836 | } |
6837 | ||
6838 | static void | |
46bd8383 | 6839 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 6840 | bool force_disable_vdd) |
f30d26e4 | 6841 | { |
de25eb7f | 6842 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ab3517c1 | 6843 | u32 pp_on, pp_off, port_sel = 0; |
e7dc33f3 | 6844 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 6845 | struct pps_registers regs; |
8f4f2797 | 6846 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
36b5f425 | 6847 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 6848 | |
e39b999a | 6849 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 6850 | |
46bd8383 | 6851 | intel_pps_get_registers(intel_dp, ®s); |
453c5420 | 6852 | |
5d5ab2d2 VS |
6853 | /* |
6854 | * On some VLV machines the BIOS can leave the VDD | |
e7f2af78 | 6855 | * enabled even on power sequencers which aren't |
5d5ab2d2 VS |
6856 | * hooked up to any port. This would mess up the |
6857 | * power domain tracking the first time we pick | |
6858 | * one of these power sequencers for use since | |
6859 | * edp_panel_vdd_on() would notice that the VDD was | |
6860 | * already on and therefore wouldn't grab the power | |
6861 | * domain reference. Disable VDD first to avoid this. | |
6862 | * This also avoids spuriously turning the VDD on as | |
e7f2af78 | 6863 | * soon as the new power sequencer gets initialized. |
5d5ab2d2 VS |
6864 | */ |
6865 | if (force_disable_vdd) { | |
9eae5e27 | 6866 | u32 pp = ilk_get_pp_control(intel_dp); |
5d5ab2d2 VS |
6867 | |
6868 | WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); | |
6869 | ||
6870 | if (pp & EDP_FORCE_VDD) | |
6871 | DRM_DEBUG_KMS("VDD already on, disabling first\n"); | |
6872 | ||
6873 | pp &= ~EDP_FORCE_VDD; | |
6874 | ||
6875 | I915_WRITE(regs.pp_ctrl, pp); | |
6876 | } | |
6877 | ||
78b36b10 JN |
6878 | pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | |
6879 | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); | |
6880 | pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | | |
6881 | REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); | |
67a54566 DV |
6882 | |
6883 | /* Haswell doesn't have any port selection bits for the panel | |
6884 | * power sequencer any more. */ | |
920a14b2 | 6885 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 6886 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 6887 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
05bf51d3 VS |
6888 | switch (port) { |
6889 | case PORT_A: | |
a24c144c | 6890 | port_sel = PANEL_PORT_SELECT_DPA; |
05bf51d3 VS |
6891 | break; |
6892 | case PORT_C: | |
6893 | port_sel = PANEL_PORT_SELECT_DPC; | |
6894 | break; | |
6895 | case PORT_D: | |
a24c144c | 6896 | port_sel = PANEL_PORT_SELECT_DPD; |
05bf51d3 VS |
6897 | break; |
6898 | default: | |
6899 | MISSING_CASE(port); | |
6900 | break; | |
6901 | } | |
67a54566 DV |
6902 | } |
6903 | ||
453c5420 JB |
6904 | pp_on |= port_sel; |
6905 | ||
8e8232d5 ID |
6906 | I915_WRITE(regs.pp_on, pp_on); |
6907 | I915_WRITE(regs.pp_off, pp_off); | |
ab3517c1 JN |
6908 | |
6909 | /* | |
6910 | * Compute the divisor for the pp clock, simply match the Bspec formula. | |
6911 | */ | |
6912 | if (i915_mmio_reg_valid(regs.pp_div)) { | |
78b36b10 JN |
6913 | I915_WRITE(regs.pp_div, |
6914 | REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | | |
6915 | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); | |
ab3517c1 JN |
6916 | } else { |
6917 | u32 pp_ctl; | |
6918 | ||
6919 | pp_ctl = I915_READ(regs.pp_ctrl); | |
6920 | pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; | |
78b36b10 | 6921 | pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); |
ab3517c1 JN |
6922 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
6923 | } | |
67a54566 | 6924 | |
67a54566 | 6925 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
6926 | I915_READ(regs.pp_on), |
6927 | I915_READ(regs.pp_off), | |
ab3517c1 JN |
6928 | i915_mmio_reg_valid(regs.pp_div) ? |
6929 | I915_READ(regs.pp_div) : | |
6930 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); | |
f684960e CW |
6931 | } |
6932 | ||
46bd8383 | 6933 | static void intel_dp_pps_init(struct intel_dp *intel_dp) |
335f752b | 6934 | { |
de25eb7f | 6935 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
920a14b2 TU |
6936 | |
6937 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
6938 | vlv_initial_power_sequencer_setup(intel_dp); |
6939 | } else { | |
46bd8383 VS |
6940 | intel_dp_init_panel_power_sequencer(intel_dp); |
6941 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
335f752b ID |
6942 | } |
6943 | } | |
6944 | ||
b33a2815 VK |
6945 | /** |
6946 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 6947 | * @dev_priv: i915 device |
e896402c | 6948 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
6949 | * @refresh_rate: RR to be programmed |
6950 | * | |
6951 | * This function gets called when refresh rate (RR) has to be changed from | |
6952 | * one frequency to another. Switches can be between high and low RR | |
6953 | * supported by the panel or to any other RR based on media playback (in | |
6954 | * this case, RR value needs to be passed from user space). | |
6955 | * | |
6956 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
6957 | */ | |
85cb48a1 | 6958 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5f88a9c6 | 6959 | const struct intel_crtc_state *crtc_state, |
85cb48a1 | 6960 | int refresh_rate) |
439d7ac0 | 6961 | { |
96178eeb | 6962 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
2225f3c6 | 6963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
96178eeb | 6964 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
6965 | |
6966 | if (refresh_rate <= 0) { | |
6967 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
6968 | return; | |
6969 | } | |
6970 | ||
96178eeb VK |
6971 | if (intel_dp == NULL) { |
6972 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
6973 | return; |
6974 | } | |
6975 | ||
439d7ac0 PB |
6976 | if (!intel_crtc) { |
6977 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
6978 | return; | |
6979 | } | |
6980 | ||
96178eeb | 6981 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
6982 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
6983 | return; | |
6984 | } | |
6985 | ||
96178eeb VK |
6986 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
6987 | refresh_rate) | |
439d7ac0 PB |
6988 | index = DRRS_LOW_RR; |
6989 | ||
96178eeb | 6990 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
6991 | DRM_DEBUG_KMS( |
6992 | "DRRS requested for previously set RR...ignoring\n"); | |
6993 | return; | |
6994 | } | |
6995 | ||
1326a92c | 6996 | if (!crtc_state->hw.active) { |
439d7ac0 PB |
6997 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
6998 | return; | |
6999 | } | |
7000 | ||
85cb48a1 | 7001 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
7002 | switch (index) { |
7003 | case DRRS_HIGH_RR: | |
4c354754 | 7004 | intel_dp_set_m_n(crtc_state, M1_N1); |
a4c30b1d VK |
7005 | break; |
7006 | case DRRS_LOW_RR: | |
4c354754 | 7007 | intel_dp_set_m_n(crtc_state, M2_N2); |
a4c30b1d VK |
7008 | break; |
7009 | case DRRS_MAX_RR: | |
7010 | default: | |
7011 | DRM_ERROR("Unsupported refreshrate type\n"); | |
7012 | } | |
85cb48a1 ML |
7013 | } else if (INTEL_GEN(dev_priv) > 6) { |
7014 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 7015 | u32 val; |
a4c30b1d | 7016 | |
649636ef | 7017 | val = I915_READ(reg); |
439d7ac0 | 7018 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 7019 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
7020 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
7021 | else | |
7022 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 7023 | } else { |
85cb48a1 | 7024 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
7025 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
7026 | else | |
7027 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
7028 | } |
7029 | I915_WRITE(reg, val); | |
7030 | } | |
7031 | ||
4e9ac947 VK |
7032 | dev_priv->drrs.refresh_rate_type = index; |
7033 | ||
7034 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
7035 | } | |
7036 | ||
b33a2815 VK |
7037 | /** |
7038 | * intel_edp_drrs_enable - init drrs struct if supported | |
7039 | * @intel_dp: DP struct | |
5423adf1 | 7040 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
7041 | * |
7042 | * Initializes frontbuffer_bits and drrs.dp | |
7043 | */ | |
85cb48a1 | 7044 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 7045 | const struct intel_crtc_state *crtc_state) |
c395578e | 7046 | { |
de25eb7f | 7047 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c395578e | 7048 | |
85cb48a1 | 7049 | if (!crtc_state->has_drrs) { |
c395578e VK |
7050 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
7051 | return; | |
7052 | } | |
7053 | ||
da83ef85 RS |
7054 | if (dev_priv->psr.enabled) { |
7055 | DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n"); | |
7056 | return; | |
7057 | } | |
7058 | ||
c395578e | 7059 | mutex_lock(&dev_priv->drrs.mutex); |
f69a0d71 HG |
7060 | if (dev_priv->drrs.dp) { |
7061 | DRM_DEBUG_KMS("DRRS already enabled\n"); | |
c395578e VK |
7062 | goto unlock; |
7063 | } | |
7064 | ||
7065 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
7066 | ||
7067 | dev_priv->drrs.dp = intel_dp; | |
7068 | ||
7069 | unlock: | |
7070 | mutex_unlock(&dev_priv->drrs.mutex); | |
7071 | } | |
7072 | ||
b33a2815 VK |
7073 | /** |
7074 | * intel_edp_drrs_disable - Disable DRRS | |
7075 | * @intel_dp: DP struct | |
5423adf1 | 7076 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
7077 | * |
7078 | */ | |
85cb48a1 | 7079 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 7080 | const struct intel_crtc_state *old_crtc_state) |
c395578e | 7081 | { |
de25eb7f | 7082 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c395578e | 7083 | |
85cb48a1 | 7084 | if (!old_crtc_state->has_drrs) |
c395578e VK |
7085 | return; |
7086 | ||
7087 | mutex_lock(&dev_priv->drrs.mutex); | |
7088 | if (!dev_priv->drrs.dp) { | |
7089 | mutex_unlock(&dev_priv->drrs.mutex); | |
7090 | return; | |
7091 | } | |
7092 | ||
7093 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
7094 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
7095 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
7096 | |
7097 | dev_priv->drrs.dp = NULL; | |
7098 | mutex_unlock(&dev_priv->drrs.mutex); | |
7099 | ||
7100 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
7101 | } | |
7102 | ||
4e9ac947 VK |
7103 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
7104 | { | |
7105 | struct drm_i915_private *dev_priv = | |
7106 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
7107 | struct intel_dp *intel_dp; | |
7108 | ||
7109 | mutex_lock(&dev_priv->drrs.mutex); | |
7110 | ||
7111 | intel_dp = dev_priv->drrs.dp; | |
7112 | ||
7113 | if (!intel_dp) | |
7114 | goto unlock; | |
7115 | ||
439d7ac0 | 7116 | /* |
4e9ac947 VK |
7117 | * The delayed work can race with an invalidate hence we need to |
7118 | * recheck. | |
439d7ac0 PB |
7119 | */ |
7120 | ||
4e9ac947 VK |
7121 | if (dev_priv->drrs.busy_frontbuffer_bits) |
7122 | goto unlock; | |
439d7ac0 | 7123 | |
85cb48a1 ML |
7124 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
7125 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
7126 | ||
7127 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
7128 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
7129 | } | |
439d7ac0 | 7130 | |
4e9ac947 | 7131 | unlock: |
4e9ac947 | 7132 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
7133 | } |
7134 | ||
b33a2815 | 7135 | /** |
0ddfd203 | 7136 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 7137 | * @dev_priv: i915 device |
b33a2815 VK |
7138 | * @frontbuffer_bits: frontbuffer plane tracking bits |
7139 | * | |
0ddfd203 R |
7140 | * This function gets called everytime rendering on the given planes start. |
7141 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
7142 | * |
7143 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
7144 | */ | |
5748b6a1 CW |
7145 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
7146 | unsigned int frontbuffer_bits) | |
a93fad0f | 7147 | { |
a93fad0f VK |
7148 | struct drm_crtc *crtc; |
7149 | enum pipe pipe; | |
7150 | ||
9da7d693 | 7151 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
7152 | return; |
7153 | ||
88f933a8 | 7154 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 7155 | |
a93fad0f | 7156 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
7157 | if (!dev_priv->drrs.dp) { |
7158 | mutex_unlock(&dev_priv->drrs.mutex); | |
7159 | return; | |
7160 | } | |
7161 | ||
a93fad0f VK |
7162 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
7163 | pipe = to_intel_crtc(crtc)->pipe; | |
7164 | ||
c1d038c6 DV |
7165 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
7166 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
7167 | ||
0ddfd203 | 7168 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 7169 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
7170 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
7171 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 7172 | |
a93fad0f VK |
7173 | mutex_unlock(&dev_priv->drrs.mutex); |
7174 | } | |
7175 | ||
b33a2815 | 7176 | /** |
0ddfd203 | 7177 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 7178 | * @dev_priv: i915 device |
b33a2815 VK |
7179 | * @frontbuffer_bits: frontbuffer plane tracking bits |
7180 | * | |
0ddfd203 R |
7181 | * This function gets called every time rendering on the given planes has |
7182 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
7183 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
7184 | * if no other planes are dirty. | |
b33a2815 VK |
7185 | * |
7186 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
7187 | */ | |
5748b6a1 CW |
7188 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
7189 | unsigned int frontbuffer_bits) | |
a93fad0f | 7190 | { |
a93fad0f VK |
7191 | struct drm_crtc *crtc; |
7192 | enum pipe pipe; | |
7193 | ||
9da7d693 | 7194 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
7195 | return; |
7196 | ||
88f933a8 | 7197 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 7198 | |
a93fad0f | 7199 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
7200 | if (!dev_priv->drrs.dp) { |
7201 | mutex_unlock(&dev_priv->drrs.mutex); | |
7202 | return; | |
7203 | } | |
7204 | ||
a93fad0f VK |
7205 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
7206 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
7207 | |
7208 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
7209 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
7210 | ||
0ddfd203 | 7211 | /* flush means busy screen hence upclock */ |
c1d038c6 | 7212 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
7213 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
7214 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
7215 | |
7216 | /* | |
7217 | * flush also means no more activity hence schedule downclock, if all | |
7218 | * other fbs are quiescent too | |
7219 | */ | |
7220 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
7221 | schedule_delayed_work(&dev_priv->drrs.work, |
7222 | msecs_to_jiffies(1000)); | |
7223 | mutex_unlock(&dev_priv->drrs.mutex); | |
7224 | } | |
7225 | ||
b33a2815 VK |
7226 | /** |
7227 | * DOC: Display Refresh Rate Switching (DRRS) | |
7228 | * | |
7229 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
7230 | * which enables swtching between low and high refresh rates, | |
7231 | * dynamically, based on the usage scenario. This feature is applicable | |
7232 | * for internal panels. | |
7233 | * | |
7234 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
7235 | * would list multiple refresh rates for one resolution. | |
7236 | * | |
7237 | * DRRS is of 2 types - static and seamless. | |
7238 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
7239 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
7240 | * Seamless DRRS involves changing RR without any visual effect to the user | |
7241 | * and can be used during normal system usage. This is done by programming | |
7242 | * certain registers. | |
7243 | * | |
7244 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
7245 | * inputs from the panel spec. | |
7246 | * | |
7247 | * DRRS saves power by switching to low RR based on usage scenarios. | |
7248 | * | |
2e7a5701 DV |
7249 | * The implementation is based on frontbuffer tracking implementation. When |
7250 | * there is a disturbance on the screen triggered by user activity or a periodic | |
7251 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
7252 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
7253 | * made. | |
7254 | * | |
7255 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
7256 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
7257 | * |
7258 | * DRRS can be further extended to support other internal panels and also | |
7259 | * the scenario of video playback wherein RR is set based on the rate | |
7260 | * requested by userspace. | |
7261 | */ | |
7262 | ||
7263 | /** | |
7264 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
2f773477 | 7265 | * @connector: eDP connector |
b33a2815 VK |
7266 | * @fixed_mode: preferred mode of panel |
7267 | * | |
7268 | * This function is called only once at driver load to initialize basic | |
7269 | * DRRS stuff. | |
7270 | * | |
7271 | * Returns: | |
7272 | * Downclock mode if panel supports it, else return NULL. | |
7273 | * DRRS support is determined by the presence of downclock mode (apart | |
7274 | * from VBT setting). | |
7275 | */ | |
4f9db5b5 | 7276 | static struct drm_display_mode * |
2f773477 VS |
7277 | intel_dp_drrs_init(struct intel_connector *connector, |
7278 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 | 7279 | { |
2f773477 | 7280 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
4f9db5b5 PB |
7281 | struct drm_display_mode *downclock_mode = NULL; |
7282 | ||
9da7d693 DV |
7283 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
7284 | mutex_init(&dev_priv->drrs.mutex); | |
7285 | ||
dd11bc10 | 7286 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
7287 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
7288 | return NULL; | |
7289 | } | |
7290 | ||
7291 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 7292 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
7293 | return NULL; |
7294 | } | |
7295 | ||
abf1aae8 | 7296 | downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); |
4f9db5b5 | 7297 | if (!downclock_mode) { |
a1d26342 | 7298 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
7299 | return NULL; |
7300 | } | |
7301 | ||
96178eeb | 7302 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 7303 | |
96178eeb | 7304 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 7305 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
7306 | return downclock_mode; |
7307 | } | |
7308 | ||
ed92f0b2 | 7309 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 7310 | struct intel_connector *intel_connector) |
ed92f0b2 | 7311 | { |
de25eb7f RV |
7312 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7313 | struct drm_device *dev = &dev_priv->drm; | |
2f773477 | 7314 | struct drm_connector *connector = &intel_connector->base; |
ed92f0b2 | 7315 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 7316 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 | 7317 | bool has_dpcd; |
6517d273 | 7318 | enum pipe pipe = INVALID_PIPE; |
69d93820 CW |
7319 | intel_wakeref_t wakeref; |
7320 | struct edid *edid; | |
ed92f0b2 | 7321 | |
1853a9da | 7322 | if (!intel_dp_is_edp(intel_dp)) |
ed92f0b2 PZ |
7323 | return true; |
7324 | ||
36b80aa3 JRS |
7325 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work); |
7326 | ||
97a824e1 ID |
7327 | /* |
7328 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
7329 | * driver uses the only internal power sequencer available for both | |
7330 | * eDP and LVDS bail out early in this case to prevent interfering | |
7331 | * with an already powered-on LVDS power sequencer. | |
7332 | */ | |
17be4942 | 7333 | if (intel_get_lvds_encoder(dev_priv)) { |
97a824e1 ID |
7334 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); |
7335 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
7336 | ||
7337 | return false; | |
7338 | } | |
7339 | ||
69d93820 CW |
7340 | with_pps_lock(intel_dp, wakeref) { |
7341 | intel_dp_init_panel_power_timestamps(intel_dp); | |
7342 | intel_dp_pps_init(intel_dp); | |
7343 | intel_edp_panel_vdd_sanitize(intel_dp); | |
7344 | } | |
63635217 | 7345 | |
ed92f0b2 | 7346 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 7347 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 7348 | |
fe5a66f9 | 7349 | if (!has_dpcd) { |
ed92f0b2 PZ |
7350 | /* if this fails, presume the device is a ghost */ |
7351 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 7352 | goto out_vdd_off; |
ed92f0b2 PZ |
7353 | } |
7354 | ||
060c8778 | 7355 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 7356 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
7357 | if (edid) { |
7358 | if (drm_add_edid_modes(connector, edid)) { | |
c555f023 | 7359 | drm_connector_update_edid_property(connector, |
ed92f0b2 | 7360 | edid); |
ed92f0b2 PZ |
7361 | } else { |
7362 | kfree(edid); | |
7363 | edid = ERR_PTR(-EINVAL); | |
7364 | } | |
7365 | } else { | |
7366 | edid = ERR_PTR(-ENOENT); | |
7367 | } | |
7368 | intel_connector->edid = edid; | |
7369 | ||
0dc927eb VS |
7370 | fixed_mode = intel_panel_edid_fixed_mode(intel_connector); |
7371 | if (fixed_mode) | |
7372 | downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode); | |
ed92f0b2 PZ |
7373 | |
7374 | /* fallback to VBT if available for eDP */ | |
325710d3 VS |
7375 | if (!fixed_mode) |
7376 | fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); | |
060c8778 | 7377 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 7378 | |
920a14b2 | 7379 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
7380 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
7381 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
7382 | |
7383 | /* | |
7384 | * Figure out the current pipe for the initial backlight setup. | |
7385 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
7386 | * fails just assume pipe A. | |
7387 | */ | |
9f2bdb00 | 7388 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
7389 | |
7390 | if (pipe != PIPE_A && pipe != PIPE_B) | |
7391 | pipe = intel_dp->pps_pipe; | |
7392 | ||
7393 | if (pipe != PIPE_A && pipe != PIPE_B) | |
7394 | pipe = PIPE_A; | |
7395 | ||
7396 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
7397 | pipe_name(pipe)); | |
01527b31 CT |
7398 | } |
7399 | ||
d93fa1b4 | 7400 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 7401 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 7402 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 | 7403 | |
9531221d HG |
7404 | if (fixed_mode) |
7405 | drm_connector_init_panel_orientation_property( | |
7406 | connector, fixed_mode->hdisplay, fixed_mode->vdisplay); | |
7407 | ||
ed92f0b2 | 7408 | return true; |
b4d06ede ID |
7409 | |
7410 | out_vdd_off: | |
7411 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
7412 | /* | |
7413 | * vdd might still be enabled do to the delayed vdd off. | |
7414 | * Make sure vdd is actually turned off here. | |
7415 | */ | |
69d93820 CW |
7416 | with_pps_lock(intel_dp, wakeref) |
7417 | edp_panel_vdd_off_sync(intel_dp); | |
b4d06ede ID |
7418 | |
7419 | return false; | |
ed92f0b2 PZ |
7420 | } |
7421 | ||
9301397a MN |
7422 | static void intel_dp_modeset_retry_work_fn(struct work_struct *work) |
7423 | { | |
7424 | struct intel_connector *intel_connector; | |
7425 | struct drm_connector *connector; | |
7426 | ||
7427 | intel_connector = container_of(work, typeof(*intel_connector), | |
7428 | modeset_retry_work); | |
7429 | connector = &intel_connector->base; | |
7430 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, | |
7431 | connector->name); | |
7432 | ||
7433 | /* Grab the locks before changing connector property*/ | |
7434 | mutex_lock(&connector->dev->mode_config.mutex); | |
7435 | /* Set connector link status to BAD and send a Uevent to notify | |
7436 | * userspace to do a modeset. | |
7437 | */ | |
97e14fbe DV |
7438 | drm_connector_set_link_status_property(connector, |
7439 | DRM_MODE_LINK_STATUS_BAD); | |
9301397a MN |
7440 | mutex_unlock(&connector->dev->mode_config.mutex); |
7441 | /* Send Hotplug uevent so userspace can reprobe */ | |
7442 | drm_kms_helper_hotplug_event(connector->dev); | |
7443 | } | |
7444 | ||
16c25533 | 7445 | bool |
f0fec3f2 PZ |
7446 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
7447 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 7448 | { |
f0fec3f2 PZ |
7449 | struct drm_connector *connector = &intel_connector->base; |
7450 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
7451 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
7452 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 7453 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 7454 | enum port port = intel_encoder->port; |
d8fe2ab6 | 7455 | enum phy phy = intel_port_to_phy(dev_priv, port); |
7a418e34 | 7456 | int type; |
a4fc5ed6 | 7457 | |
9301397a MN |
7458 | /* Initialize the work for modeset in case of link train failure */ |
7459 | INIT_WORK(&intel_connector->modeset_retry_work, | |
7460 | intel_dp_modeset_retry_work_fn); | |
7461 | ||
ccb1a831 | 7462 | if (WARN(intel_dig_port->max_lanes < 1, |
66a990dd VS |
7463 | "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", |
7464 | intel_dig_port->max_lanes, intel_encoder->base.base.id, | |
7465 | intel_encoder->base.name)) | |
ccb1a831 VS |
7466 | return false; |
7467 | ||
55cfc580 JN |
7468 | intel_dp_set_source_rates(intel_dp); |
7469 | ||
d7e8ef02 | 7470 | intel_dp->reset_link_params = true; |
a4a5d2f8 | 7471 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 7472 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 7473 | |
0767935e DV |
7474 | /* Preserve the current hw state. */ |
7475 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 7476 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 7477 | |
4e309baf ID |
7478 | if (intel_dp_is_port_edp(dev_priv, port)) { |
7479 | /* | |
7480 | * Currently we don't support eDP on TypeC ports, although in | |
7481 | * theory it could work on TypeC legacy ports. | |
7482 | */ | |
d8fe2ab6 | 7483 | WARN_ON(intel_phy_is_tc(dev_priv, phy)); |
b329530c | 7484 | type = DRM_MODE_CONNECTOR_eDP; |
4e309baf | 7485 | } else { |
3b32a35b | 7486 | type = DRM_MODE_CONNECTOR_DisplayPort; |
4e309baf | 7487 | } |
b329530c | 7488 | |
9f2bdb00 VS |
7489 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
7490 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
7491 | ||
f7d24902 ID |
7492 | /* |
7493 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
7494 | * for DP the encoder type can be set by the caller to | |
7495 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
7496 | */ | |
7497 | if (type == DRM_MODE_CONNECTOR_eDP) | |
7498 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
7499 | ||
c17ed5b5 | 7500 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 7501 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1853a9da JN |
7502 | intel_dp_is_edp(intel_dp) && |
7503 | port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
7504 | return false; |
7505 | ||
66a990dd VS |
7506 | DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n", |
7507 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
7508 | intel_encoder->base.base.id, intel_encoder->base.name); | |
e7281eab | 7509 | |
b329530c | 7510 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
7511 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
7512 | ||
b2ae318a | 7513 | if (!HAS_GMCH(dev_priv)) |
05021389 | 7514 | connector->interlace_allowed = true; |
a4fc5ed6 KP |
7515 | connector->doublescan_allowed = 0; |
7516 | ||
47d0ccec GM |
7517 | if (INTEL_GEN(dev_priv) >= 11) |
7518 | connector->ycbcr_420_allowed = true; | |
7519 | ||
bdabdb63 | 7520 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
5432fcaf | 7521 | |
b6339585 | 7522 | intel_dp_aux_init(intel_dp); |
7a418e34 | 7523 | |
df0e9248 | 7524 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 7525 | |
4f8036a2 | 7526 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
7527 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
7528 | else | |
7529 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
7530 | ||
0e32b39c | 7531 | /* init MST on ports that can support it */ |
10d987fd LDM |
7532 | intel_dp_mst_encoder_init(intel_dig_port, |
7533 | intel_connector->base.base.id); | |
0e32b39c | 7534 | |
36b5f425 | 7535 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
7536 | intel_dp_aux_fini(intel_dp); |
7537 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
7538 | goto fail; | |
b2f246a8 | 7539 | } |
32f9d658 | 7540 | |
f684960e | 7541 | intel_dp_add_properties(intel_dp, connector); |
20f24d77 | 7542 | |
fdddd08c | 7543 | if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { |
20f24d77 SP |
7544 | int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); |
7545 | if (ret) | |
7546 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
7547 | } | |
f684960e | 7548 | |
a4fc5ed6 KP |
7549 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
7550 | * 0xd. Failure to do so will result in spurious interrupts being | |
7551 | * generated on the port when a cable is not attached. | |
7552 | */ | |
1c0f1b3d | 7553 | if (IS_G45(dev_priv)) { |
a4fc5ed6 KP |
7554 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
7555 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
7556 | } | |
16c25533 PZ |
7557 | |
7558 | return true; | |
a121f4e5 VS |
7559 | |
7560 | fail: | |
a121f4e5 VS |
7561 | drm_connector_cleanup(connector); |
7562 | ||
7563 | return false; | |
a4fc5ed6 | 7564 | } |
f0fec3f2 | 7565 | |
c39055b0 | 7566 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
7567 | i915_reg_t output_reg, |
7568 | enum port port) | |
f0fec3f2 PZ |
7569 | { |
7570 | struct intel_digital_port *intel_dig_port; | |
7571 | struct intel_encoder *intel_encoder; | |
7572 | struct drm_encoder *encoder; | |
7573 | struct intel_connector *intel_connector; | |
7574 | ||
b14c5679 | 7575 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 7576 | if (!intel_dig_port) |
457c52d8 | 7577 | return false; |
f0fec3f2 | 7578 | |
08d9bc92 | 7579 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
7580 | if (!intel_connector) |
7581 | goto err_connector_alloc; | |
f0fec3f2 PZ |
7582 | |
7583 | intel_encoder = &intel_dig_port->base; | |
7584 | encoder = &intel_encoder->base; | |
7585 | ||
c39055b0 ACO |
7586 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
7587 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
7588 | "DP %c", port_name(port))) | |
893da0c9 | 7589 | goto err_encoder_init; |
f0fec3f2 | 7590 | |
c85d200e | 7591 | intel_encoder->hotplug = intel_dp_hotplug; |
5bfe2ac0 | 7592 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 7593 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 7594 | intel_encoder->get_config = intel_dp_get_config; |
63a23d24 | 7595 | intel_encoder->update_pipe = intel_panel_update_backlight; |
07f9cd0b | 7596 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 7597 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 7598 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
7599 | intel_encoder->pre_enable = chv_pre_enable_dp; |
7600 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 7601 | intel_encoder->disable = vlv_disable_dp; |
580d3811 | 7602 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 7603 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 7604 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 7605 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
7606 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
7607 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 7608 | intel_encoder->disable = vlv_disable_dp; |
49277c31 | 7609 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 7610 | } else { |
ecff4f3b JN |
7611 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
7612 | intel_encoder->enable = g4x_enable_dp; | |
1a8ff607 | 7613 | intel_encoder->disable = g4x_disable_dp; |
51a9f6df | 7614 | intel_encoder->post_disable = g4x_post_disable_dp; |
ab1f90f9 | 7615 | } |
f0fec3f2 | 7616 | |
f0fec3f2 | 7617 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 7618 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 7619 | |
cca0502b | 7620 | intel_encoder->type = INTEL_OUTPUT_DP; |
79f255a0 | 7621 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
920a14b2 | 7622 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 | 7623 | if (port == PORT_D) |
981329ce | 7624 | intel_encoder->pipe_mask = BIT(PIPE_C); |
882ec384 | 7625 | else |
981329ce | 7626 | intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); |
882ec384 | 7627 | } else { |
34053ee1 | 7628 | intel_encoder->pipe_mask = ~0; |
882ec384 | 7629 | } |
bc079e8b | 7630 | intel_encoder->cloneable = 0; |
03cdc1d4 | 7631 | intel_encoder->port = port; |
f0fec3f2 | 7632 | |
13cf5504 | 7633 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
13cf5504 | 7634 | |
385e4de0 VS |
7635 | if (port != PORT_A) |
7636 | intel_infoframe_init(intel_dig_port); | |
7637 | ||
39053089 | 7638 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
11aee0f6 SM |
7639 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
7640 | goto err_init_connector; | |
7641 | ||
457c52d8 | 7642 | return true; |
11aee0f6 SM |
7643 | |
7644 | err_init_connector: | |
7645 | drm_encoder_cleanup(encoder); | |
893da0c9 | 7646 | err_encoder_init: |
11aee0f6 SM |
7647 | kfree(intel_connector); |
7648 | err_connector_alloc: | |
7649 | kfree(intel_dig_port); | |
457c52d8 | 7650 | return false; |
f0fec3f2 | 7651 | } |
0e32b39c | 7652 | |
1a4313d1 | 7653 | void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) |
0e32b39c | 7654 | { |
1a4313d1 VS |
7655 | struct intel_encoder *encoder; |
7656 | ||
7657 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
7658 | struct intel_dp *intel_dp; | |
0e32b39c | 7659 | |
1a4313d1 VS |
7660 | if (encoder->type != INTEL_OUTPUT_DDI) |
7661 | continue; | |
5aa56969 | 7662 | |
b7d02c3a | 7663 | intel_dp = enc_to_intel_dp(encoder); |
5aa56969 | 7664 | |
1a4313d1 | 7665 | if (!intel_dp->can_mst) |
0e32b39c DA |
7666 | continue; |
7667 | ||
1a4313d1 VS |
7668 | if (intel_dp->is_mst) |
7669 | drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); | |
0e32b39c DA |
7670 | } |
7671 | } | |
7672 | ||
1a4313d1 | 7673 | void intel_dp_mst_resume(struct drm_i915_private *dev_priv) |
0e32b39c | 7674 | { |
1a4313d1 | 7675 | struct intel_encoder *encoder; |
0e32b39c | 7676 | |
1a4313d1 VS |
7677 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
7678 | struct intel_dp *intel_dp; | |
5aa56969 | 7679 | int ret; |
0e32b39c | 7680 | |
1a4313d1 VS |
7681 | if (encoder->type != INTEL_OUTPUT_DDI) |
7682 | continue; | |
7683 | ||
b7d02c3a | 7684 | intel_dp = enc_to_intel_dp(encoder); |
1a4313d1 VS |
7685 | |
7686 | if (!intel_dp->can_mst) | |
5aa56969 | 7687 | continue; |
0e32b39c | 7688 | |
6f85f738 LP |
7689 | ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, |
7690 | true); | |
6be1cf96 LP |
7691 | if (ret) { |
7692 | intel_dp->is_mst = false; | |
7693 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
7694 | false); | |
7695 | } | |
0e32b39c DA |
7696 | } |
7697 | } |