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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
2d1a8a48 | 28 | #include <linux/export.h> |
331c201a | 29 | #include <linux/i2c.h> |
01527b31 CT |
30 | #include <linux/notifier.h> |
31 | #include <linux/reboot.h> | |
331c201a JN |
32 | #include <linux/slab.h> |
33 | #include <linux/types.h> | |
56c5098f | 34 | |
611032bf | 35 | #include <asm/byteorder.h> |
331c201a | 36 | |
c6f95f27 | 37 | #include <drm/drm_atomic_helper.h> |
760285e7 | 38 | #include <drm/drm_crtc.h> |
20f24d77 | 39 | #include <drm/drm_dp_helper.h> |
760285e7 | 40 | #include <drm/drm_edid.h> |
20f24d77 | 41 | #include <drm/drm_hdcp.h> |
fcd70cd3 | 42 | #include <drm/drm_probe_helper.h> |
331c201a | 43 | |
2126d3e9 | 44 | #include "i915_debugfs.h" |
a4fc5ed6 | 45 | #include "i915_drv.h" |
a09d9a80 | 46 | #include "i915_trace.h" |
12392a74 | 47 | #include "intel_atomic.h" |
331c201a | 48 | #include "intel_audio.h" |
ec7f29ff | 49 | #include "intel_connector.h" |
fdc24cf3 | 50 | #include "intel_ddi.h" |
1d455f8d | 51 | #include "intel_display_types.h" |
27fec1f9 | 52 | #include "intel_dp.h" |
e075094f | 53 | #include "intel_dp_link_training.h" |
46f2066e | 54 | #include "intel_dp_mst.h" |
b1ad4c39 | 55 | #include "intel_dpio_phy.h" |
8834e365 | 56 | #include "intel_fifo_underrun.h" |
408bd917 | 57 | #include "intel_hdcp.h" |
0550691d | 58 | #include "intel_hdmi.h" |
dbeb38d9 | 59 | #include "intel_hotplug.h" |
f3e18947 | 60 | #include "intel_lspcon.h" |
42406fdc | 61 | #include "intel_lvds.h" |
44c1220a | 62 | #include "intel_panel.h" |
55367a27 | 63 | #include "intel_psr.h" |
56c5098f | 64 | #include "intel_sideband.h" |
bc85328f | 65 | #include "intel_tc.h" |
b375d0ef | 66 | #include "intel_vdsc.h" |
a4fc5ed6 | 67 | |
e8b2577c | 68 | #define DP_DPRX_ESI_LEN 14 |
a4fc5ed6 | 69 | |
d9218c8f MN |
70 | /* DP DSC throughput values used for slice count calculations KPixels/s */ |
71 | #define DP_DSC_PEAK_PIXEL_RATE 2720000 | |
72 | #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 | |
73 | #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 | |
74 | ||
ed06efb8 ML |
75 | /* DP DSC FEC Overhead factor = 1/(0.972261) */ |
76 | #define DP_DSC_FEC_OVERHEAD_FACTOR 972261 | |
d9218c8f | 77 | |
559be30c TP |
78 | /* Compliance test status bits */ |
79 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
80 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
81 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
82 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
83 | ||
9dd4ffdf | 84 | struct dp_link_dpll { |
840b32b7 | 85 | int clock; |
9dd4ffdf CML |
86 | struct dpll dpll; |
87 | }; | |
88 | ||
45101e93 | 89 | static const struct dp_link_dpll g4x_dpll[] = { |
840b32b7 | 90 | { 162000, |
9dd4ffdf | 91 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 92 | { 270000, |
9dd4ffdf CML |
93 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
94 | }; | |
95 | ||
96 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 97 | { 162000, |
9dd4ffdf | 98 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 99 | { 270000, |
9dd4ffdf CML |
100 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
101 | }; | |
102 | ||
65ce4bf5 | 103 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 104 | { 162000, |
58f6e632 | 105 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 106 | { 270000, |
65ce4bf5 CML |
107 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
108 | }; | |
109 | ||
ef9348c8 CML |
110 | /* |
111 | * CHV supports eDP 1.4 that have more link rates. | |
112 | * Below only provides the fixed rate but exclude variable rate. | |
113 | */ | |
114 | static const struct dp_link_dpll chv_dpll[] = { | |
115 | /* | |
116 | * CHV requires to program fractional division for m2. | |
117 | * m2 is stored in fixed point format using formula below | |
118 | * (m2_int << 22) | m2_fraction | |
119 | */ | |
840b32b7 | 120 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 121 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 122 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 123 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
ef9348c8 | 124 | }; |
637a9c63 | 125 | |
d9218c8f MN |
126 | /* Constants for DP DSC configurations */ |
127 | static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; | |
128 | ||
129 | /* With Single pipe configuration, HW is capable of supporting maximum | |
130 | * of 4 slices per line. | |
131 | */ | |
132 | static const u8 valid_dsc_slicecount[] = {1, 2, 4}; | |
133 | ||
cfcb0fc9 | 134 | /** |
1853a9da | 135 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
cfcb0fc9 JB |
136 | * @intel_dp: DP struct |
137 | * | |
138 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
139 | * will return true, and false otherwise. | |
140 | */ | |
1853a9da | 141 | bool intel_dp_is_edp(struct intel_dp *intel_dp) |
cfcb0fc9 | 142 | { |
da63a9f2 PZ |
143 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
144 | ||
145 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
146 | } |
147 | ||
adc10304 VS |
148 | static void intel_dp_link_down(struct intel_encoder *encoder, |
149 | const struct intel_crtc_state *old_crtc_state); | |
1e0560e0 | 150 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 151 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
adc10304 VS |
152 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
153 | const struct intel_crtc_state *crtc_state); | |
46bd8383 | 154 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a8c3344e | 155 | enum pipe pipe); |
f21a2198 | 156 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 157 | |
68f357cb JN |
158 | /* update sink rates from dpcd */ |
159 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) | |
160 | { | |
229675d5 | 161 | static const int dp_rates[] = { |
c71b53cc | 162 | 162000, 270000, 540000, 810000 |
229675d5 | 163 | }; |
a8a08886 | 164 | int i, max_rate; |
68f357cb | 165 | |
639e0db2 MK |
166 | if (drm_dp_has_quirk(&intel_dp->desc, 0, |
167 | DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { | |
168 | /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ | |
169 | static const int quirk_rates[] = { 162000, 270000, 324000 }; | |
170 | ||
171 | memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); | |
172 | intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); | |
173 | ||
174 | return; | |
175 | } | |
176 | ||
a8a08886 | 177 | max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); |
68f357cb | 178 | |
229675d5 JN |
179 | for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { |
180 | if (dp_rates[i] > max_rate) | |
a8a08886 | 181 | break; |
229675d5 | 182 | intel_dp->sink_rates[i] = dp_rates[i]; |
a8a08886 | 183 | } |
68f357cb | 184 | |
a8a08886 | 185 | intel_dp->num_sink_rates = i; |
68f357cb JN |
186 | } |
187 | ||
10ebb736 JN |
188 | /* Get length of rates array potentially limited by max_rate. */ |
189 | static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) | |
190 | { | |
191 | int i; | |
192 | ||
193 | /* Limit results by potentially reduced max rate */ | |
194 | for (i = 0; i < len; i++) { | |
195 | if (rates[len - i - 1] <= max_rate) | |
196 | return len - i; | |
197 | } | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | /* Get length of common rates array potentially limited by max_rate. */ | |
203 | static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, | |
204 | int max_rate) | |
205 | { | |
206 | return intel_dp_rate_limit_len(intel_dp->common_rates, | |
207 | intel_dp->num_common_rates, max_rate); | |
208 | } | |
209 | ||
540b0b7f JN |
210 | /* Theoretical max between source and sink */ |
211 | static int intel_dp_max_common_rate(struct intel_dp *intel_dp) | |
a4fc5ed6 | 212 | { |
540b0b7f | 213 | return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
a4fc5ed6 KP |
214 | } |
215 | ||
540b0b7f JN |
216 | /* Theoretical max between source and sink */ |
217 | static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) | |
eeb6324d PZ |
218 | { |
219 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
540b0b7f JN |
220 | int source_max = intel_dig_port->max_lanes; |
221 | int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | |
bc85328f | 222 | int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port); |
eeb6324d | 223 | |
db7295c2 | 224 | return min3(source_max, sink_max, fia_max); |
eeb6324d PZ |
225 | } |
226 | ||
3d65a735 | 227 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
540b0b7f JN |
228 | { |
229 | return intel_dp->max_link_lane_count; | |
230 | } | |
231 | ||
22a2c8e0 | 232 | int |
c898261c | 233 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 234 | { |
fd81c44e DP |
235 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
236 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
237 | } |
238 | ||
22a2c8e0 | 239 | int |
fe27d53e DA |
240 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
241 | { | |
fd81c44e DP |
242 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
243 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
244 | * is transmitted every LS_Clk per lane, there is no need to account for | |
245 | * the channel encoding that is done in the PHY layer here. | |
246 | */ | |
247 | ||
248 | return max_link_clock * max_lanes; | |
fe27d53e DA |
249 | } |
250 | ||
70ec0645 MK |
251 | static int |
252 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
253 | { | |
254 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
255 | struct intel_encoder *encoder = &intel_dig_port->base; | |
256 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
257 | int max_dotclk = dev_priv->max_dotclk_freq; | |
258 | int ds_max_dotclk; | |
259 | ||
260 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
261 | ||
262 | if (type != DP_DS_PORT_TYPE_VGA) | |
263 | return max_dotclk; | |
264 | ||
265 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
266 | intel_dp->downstream_ports); | |
267 | ||
268 | if (ds_max_dotclk != 0) | |
269 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
270 | ||
271 | return max_dotclk; | |
272 | } | |
273 | ||
4ba285d4 | 274 | static int cnl_max_source_rate(struct intel_dp *intel_dp) |
53ddb3cd RV |
275 | { |
276 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
277 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
278 | enum port port = dig_port->base.port; | |
279 | ||
b4e33881 | 280 | u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; |
53ddb3cd RV |
281 | |
282 | /* Low voltage SKUs are limited to max of 5.4G */ | |
283 | if (voltage == VOLTAGE_INFO_0_85V) | |
4ba285d4 | 284 | return 540000; |
53ddb3cd RV |
285 | |
286 | /* For this SKU 8.1G is supported in all ports */ | |
287 | if (IS_CNL_WITH_PORT_F(dev_priv)) | |
4ba285d4 | 288 | return 810000; |
53ddb3cd | 289 | |
3758d968 | 290 | /* For other SKUs, max rate on ports A and D is 5.4G */ |
53ddb3cd | 291 | if (port == PORT_A || port == PORT_D) |
4ba285d4 | 292 | return 540000; |
53ddb3cd | 293 | |
4ba285d4 | 294 | return 810000; |
53ddb3cd RV |
295 | } |
296 | ||
46b527d1 MN |
297 | static int icl_max_source_rate(struct intel_dp *intel_dp) |
298 | { | |
299 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
b265a2a6 | 300 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
d8fe2ab6 | 301 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
46b527d1 | 302 | |
d8fe2ab6 | 303 | if (intel_phy_is_combo(dev_priv, phy) && |
b7143860 | 304 | !IS_ELKHARTLAKE(dev_priv) && |
b265a2a6 | 305 | !intel_dp_is_edp(intel_dp)) |
46b527d1 MN |
306 | return 540000; |
307 | ||
308 | return 810000; | |
309 | } | |
310 | ||
55cfc580 JN |
311 | static void |
312 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 | 313 | { |
229675d5 JN |
314 | /* The values must be in increasing order */ |
315 | static const int cnl_rates[] = { | |
316 | 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 | |
317 | }; | |
318 | static const int bxt_rates[] = { | |
319 | 162000, 216000, 243000, 270000, 324000, 432000, 540000 | |
320 | }; | |
321 | static const int skl_rates[] = { | |
322 | 162000, 216000, 270000, 324000, 432000, 540000 | |
323 | }; | |
324 | static const int hsw_rates[] = { | |
325 | 162000, 270000, 540000 | |
326 | }; | |
327 | static const int g4x_rates[] = { | |
328 | 162000, 270000 | |
329 | }; | |
40dba341 | 330 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
f83acdab | 331 | struct intel_encoder *encoder = &dig_port->base; |
40dba341 | 332 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
55cfc580 | 333 | const int *source_rates; |
f83acdab | 334 | int size, max_rate = 0, vbt_max_rate; |
40dba341 | 335 | |
55cfc580 | 336 | /* This should only be done once */ |
eb020ca3 PB |
337 | drm_WARN_ON(&dev_priv->drm, |
338 | intel_dp->source_rates || intel_dp->num_source_rates); | |
55cfc580 | 339 | |
46b527d1 | 340 | if (INTEL_GEN(dev_priv) >= 10) { |
d907b665 | 341 | source_rates = cnl_rates; |
4ba285d4 | 342 | size = ARRAY_SIZE(cnl_rates); |
cf819eff | 343 | if (IS_GEN(dev_priv, 10)) |
46b527d1 MN |
344 | max_rate = cnl_max_source_rate(intel_dp); |
345 | else | |
346 | max_rate = icl_max_source_rate(intel_dp); | |
ba1c06a5 MN |
347 | } else if (IS_GEN9_LP(dev_priv)) { |
348 | source_rates = bxt_rates; | |
349 | size = ARRAY_SIZE(bxt_rates); | |
b976dc53 | 350 | } else if (IS_GEN9_BC(dev_priv)) { |
55cfc580 | 351 | source_rates = skl_rates; |
40dba341 | 352 | size = ARRAY_SIZE(skl_rates); |
fc603ca7 JN |
353 | } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
354 | IS_BROADWELL(dev_priv)) { | |
229675d5 JN |
355 | source_rates = hsw_rates; |
356 | size = ARRAY_SIZE(hsw_rates); | |
fc603ca7 | 357 | } else { |
229675d5 JN |
358 | source_rates = g4x_rates; |
359 | size = ARRAY_SIZE(g4x_rates); | |
40dba341 NM |
360 | } |
361 | ||
f83acdab | 362 | vbt_max_rate = intel_bios_dp_max_link_rate(encoder); |
99b91bda JN |
363 | if (max_rate && vbt_max_rate) |
364 | max_rate = min(max_rate, vbt_max_rate); | |
365 | else if (vbt_max_rate) | |
366 | max_rate = vbt_max_rate; | |
367 | ||
4ba285d4 JN |
368 | if (max_rate) |
369 | size = intel_dp_rate_limit_len(source_rates, size, max_rate); | |
370 | ||
55cfc580 JN |
371 | intel_dp->source_rates = source_rates; |
372 | intel_dp->num_source_rates = size; | |
40dba341 NM |
373 | } |
374 | ||
375 | static int intersect_rates(const int *source_rates, int source_len, | |
376 | const int *sink_rates, int sink_len, | |
377 | int *common_rates) | |
378 | { | |
379 | int i = 0, j = 0, k = 0; | |
380 | ||
381 | while (i < source_len && j < sink_len) { | |
382 | if (source_rates[i] == sink_rates[j]) { | |
383 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
384 | return k; | |
385 | common_rates[k] = source_rates[i]; | |
386 | ++k; | |
387 | ++i; | |
388 | ++j; | |
389 | } else if (source_rates[i] < sink_rates[j]) { | |
390 | ++i; | |
391 | } else { | |
392 | ++j; | |
393 | } | |
394 | } | |
395 | return k; | |
396 | } | |
397 | ||
8001b754 JN |
398 | /* return index of rate in rates array, or -1 if not found */ |
399 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
400 | { | |
401 | int i; | |
402 | ||
403 | for (i = 0; i < len; i++) | |
404 | if (rate == rates[i]) | |
405 | return i; | |
406 | ||
407 | return -1; | |
408 | } | |
409 | ||
975ee5fc | 410 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 411 | { |
975ee5fc | 412 | WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); |
40dba341 | 413 | |
975ee5fc JN |
414 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
415 | intel_dp->num_source_rates, | |
416 | intel_dp->sink_rates, | |
417 | intel_dp->num_sink_rates, | |
418 | intel_dp->common_rates); | |
419 | ||
420 | /* Paranoia, there should always be something in common. */ | |
421 | if (WARN_ON(intel_dp->num_common_rates == 0)) { | |
229675d5 | 422 | intel_dp->common_rates[0] = 162000; |
975ee5fc JN |
423 | intel_dp->num_common_rates = 1; |
424 | } | |
425 | } | |
426 | ||
1a92c70e | 427 | static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
830de422 | 428 | u8 lane_count) |
14c562c0 MN |
429 | { |
430 | /* | |
431 | * FIXME: we need to synchronize the current link parameters with | |
432 | * hardware readout. Currently fast link training doesn't work on | |
433 | * boot-up. | |
434 | */ | |
1a92c70e MN |
435 | if (link_rate == 0 || |
436 | link_rate > intel_dp->max_link_rate) | |
14c562c0 MN |
437 | return false; |
438 | ||
1a92c70e MN |
439 | if (lane_count == 0 || |
440 | lane_count > intel_dp_max_lane_count(intel_dp)) | |
14c562c0 MN |
441 | return false; |
442 | ||
443 | return true; | |
444 | } | |
445 | ||
1e712535 MN |
446 | static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, |
447 | int link_rate, | |
830de422 | 448 | u8 lane_count) |
1e712535 MN |
449 | { |
450 | const struct drm_display_mode *fixed_mode = | |
451 | intel_dp->attached_connector->panel.fixed_mode; | |
452 | int mode_rate, max_rate; | |
453 | ||
454 | mode_rate = intel_dp_link_required(fixed_mode->clock, 18); | |
455 | max_rate = intel_dp_max_data_rate(link_rate, lane_count); | |
456 | if (mode_rate > max_rate) | |
457 | return false; | |
458 | ||
459 | return true; | |
460 | } | |
461 | ||
fdb14d33 | 462 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
830de422 | 463 | int link_rate, u8 lane_count) |
fdb14d33 | 464 | { |
af67009c | 465 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b1810a74 | 466 | int index; |
fdb14d33 | 467 | |
b1810a74 JN |
468 | index = intel_dp_rate_index(intel_dp->common_rates, |
469 | intel_dp->num_common_rates, | |
470 | link_rate); | |
471 | if (index > 0) { | |
1e712535 MN |
472 | if (intel_dp_is_edp(intel_dp) && |
473 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
474 | intel_dp->common_rates[index - 1], | |
475 | lane_count)) { | |
af67009c JN |
476 | drm_dbg_kms(&i915->drm, |
477 | "Retrying Link training for eDP with same parameters\n"); | |
1e712535 MN |
478 | return 0; |
479 | } | |
e6c0c64a JN |
480 | intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
481 | intel_dp->max_link_lane_count = lane_count; | |
fdb14d33 | 482 | } else if (lane_count > 1) { |
1e712535 MN |
483 | if (intel_dp_is_edp(intel_dp) && |
484 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
485 | intel_dp_max_common_rate(intel_dp), | |
486 | lane_count >> 1)) { | |
af67009c JN |
487 | drm_dbg_kms(&i915->drm, |
488 | "Retrying Link training for eDP with same parameters\n"); | |
1e712535 MN |
489 | return 0; |
490 | } | |
540b0b7f | 491 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
e6c0c64a | 492 | intel_dp->max_link_lane_count = lane_count >> 1; |
fdb14d33 | 493 | } else { |
af67009c | 494 | drm_err(&i915->drm, "Link Training Unsuccessful\n"); |
fdb14d33 MN |
495 | return -1; |
496 | } | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
ed06efb8 ML |
501 | u32 intel_dp_mode_to_fec_clock(u32 mode_clock) |
502 | { | |
503 | return div_u64(mul_u32_u32(mode_clock, 1000000U), | |
504 | DP_DSC_FEC_OVERHEAD_FACTOR); | |
505 | } | |
506 | ||
45d3c5cd MR |
507 | static int |
508 | small_joiner_ram_size_bits(struct drm_i915_private *i915) | |
509 | { | |
510 | if (INTEL_GEN(i915) >= 11) | |
511 | return 7680 * 8; | |
512 | else | |
513 | return 6144 * 8; | |
514 | } | |
515 | ||
516 | static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, | |
517 | u32 link_clock, u32 lane_count, | |
ed06efb8 ML |
518 | u32 mode_clock, u32 mode_hdisplay) |
519 | { | |
520 | u32 bits_per_pixel, max_bpp_small_joiner_ram; | |
521 | int i; | |
522 | ||
523 | /* | |
524 | * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* | |
525 | * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) | |
526 | * for SST -> TimeSlotsPerMTP is 1, | |
527 | * for MST -> TimeSlotsPerMTP has to be calculated | |
528 | */ | |
529 | bits_per_pixel = (link_clock * lane_count * 8) / | |
530 | intel_dp_mode_to_fec_clock(mode_clock); | |
bdc6114e | 531 | drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); |
ed06efb8 ML |
532 | |
533 | /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ | |
45d3c5cd MR |
534 | max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / |
535 | mode_hdisplay; | |
bdc6114e WK |
536 | drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n", |
537 | max_bpp_small_joiner_ram); | |
ed06efb8 ML |
538 | |
539 | /* | |
540 | * Greatest allowed DSC BPP = MIN (output BPP from available Link BW | |
541 | * check, output bpp from small joiner RAM check) | |
542 | */ | |
543 | bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); | |
544 | ||
545 | /* Error out if the max bpp is less than smallest allowed valid bpp */ | |
546 | if (bits_per_pixel < valid_dsc_bpp[0]) { | |
bdc6114e WK |
547 | drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", |
548 | bits_per_pixel, valid_dsc_bpp[0]); | |
ed06efb8 ML |
549 | return 0; |
550 | } | |
551 | ||
552 | /* Find the nearest match in the array of known BPPs from VESA */ | |
553 | for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { | |
554 | if (bits_per_pixel < valid_dsc_bpp[i + 1]) | |
555 | break; | |
556 | } | |
557 | bits_per_pixel = valid_dsc_bpp[i]; | |
558 | ||
559 | /* | |
560 | * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, | |
561 | * fractional part is 0 | |
562 | */ | |
563 | return bits_per_pixel << 4; | |
564 | } | |
565 | ||
566 | static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, | |
567 | int mode_clock, int mode_hdisplay) | |
568 | { | |
af67009c | 569 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
ed06efb8 ML |
570 | u8 min_slice_count, i; |
571 | int max_slice_width; | |
572 | ||
573 | if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) | |
574 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
575 | DP_DSC_MAX_ENC_THROUGHPUT_0); | |
576 | else | |
577 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
578 | DP_DSC_MAX_ENC_THROUGHPUT_1); | |
579 | ||
580 | max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); | |
581 | if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { | |
af67009c JN |
582 | drm_dbg_kms(&i915->drm, |
583 | "Unsupported slice width %d by DP DSC Sink device\n", | |
584 | max_slice_width); | |
ed06efb8 ML |
585 | return 0; |
586 | } | |
587 | /* Also take into account max slice width */ | |
588 | min_slice_count = min_t(u8, min_slice_count, | |
589 | DIV_ROUND_UP(mode_hdisplay, | |
590 | max_slice_width)); | |
591 | ||
592 | /* Find the closest match to the valid slice count values */ | |
593 | for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { | |
594 | if (valid_dsc_slicecount[i] > | |
595 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, | |
596 | false)) | |
597 | break; | |
598 | if (min_slice_count <= valid_dsc_slicecount[i]) | |
599 | return valid_dsc_slicecount[i]; | |
600 | } | |
601 | ||
af67009c JN |
602 | drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", |
603 | min_slice_count); | |
ed06efb8 ML |
604 | return 0; |
605 | } | |
606 | ||
98c93394 VS |
607 | static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, |
608 | int hdisplay) | |
609 | { | |
610 | /* | |
611 | * Older platforms don't like hdisplay==4096 with DP. | |
612 | * | |
613 | * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline | |
614 | * and frame counter increment), but we don't get vblank interrupts, | |
615 | * and the pipe underruns immediately. The link also doesn't seem | |
616 | * to get trained properly. | |
617 | * | |
618 | * On CHV the vblank interrupts don't seem to disappear but | |
619 | * otherwise the symptoms are similar. | |
620 | * | |
621 | * TODO: confirm the behaviour on HSW+ | |
622 | */ | |
623 | return hdisplay == 4096 && !HAS_DDI(dev_priv); | |
624 | } | |
625 | ||
c19de8eb | 626 | static enum drm_mode_status |
a4fc5ed6 KP |
627 | intel_dp_mode_valid(struct drm_connector *connector, |
628 | struct drm_display_mode *mode) | |
629 | { | |
43a6d19c | 630 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
dd06f90e JN |
631 | struct intel_connector *intel_connector = to_intel_connector(connector); |
632 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
6cfd04b0 | 633 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
36008365 DV |
634 | int target_clock = mode->clock; |
635 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 | 636 | int max_dotclk; |
6cfd04b0 MN |
637 | u16 dsc_max_output_bpp = 0; |
638 | u8 dsc_slice_count = 0; | |
70ec0645 | 639 | |
e4dd27aa VS |
640 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
641 | return MODE_NO_DBLESCAN; | |
642 | ||
70ec0645 | 643 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); |
a4fc5ed6 | 644 | |
1853a9da | 645 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
dd06f90e | 646 | if (mode->hdisplay > fixed_mode->hdisplay) |
7de56f43 ZY |
647 | return MODE_PANEL; |
648 | ||
dd06f90e | 649 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 650 | return MODE_PANEL; |
03afc4a2 DV |
651 | |
652 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
653 | } |
654 | ||
50fec21a | 655 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 656 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
657 | |
658 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
659 | mode_rate = intel_dp_link_required(target_clock, 18); | |
660 | ||
98c93394 VS |
661 | if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) |
662 | return MODE_H_ILLEGAL; | |
663 | ||
6cfd04b0 MN |
664 | /* |
665 | * Output bpp is stored in 6.4 format so right shift by 4 to get the | |
666 | * integer value since we support only integer values of bpp. | |
667 | */ | |
668 | if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && | |
669 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { | |
670 | if (intel_dp_is_edp(intel_dp)) { | |
671 | dsc_max_output_bpp = | |
672 | drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; | |
673 | dsc_slice_count = | |
674 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, | |
675 | true); | |
240999cf | 676 | } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { |
6cfd04b0 | 677 | dsc_max_output_bpp = |
45d3c5cd MR |
678 | intel_dp_dsc_get_output_bpp(dev_priv, |
679 | max_link_clock, | |
6cfd04b0 MN |
680 | max_lanes, |
681 | target_clock, | |
682 | mode->hdisplay) >> 4; | |
683 | dsc_slice_count = | |
684 | intel_dp_dsc_get_slice_count(intel_dp, | |
685 | target_clock, | |
686 | mode->hdisplay); | |
687 | } | |
688 | } | |
689 | ||
690 | if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || | |
691 | target_clock > max_dotclk) | |
c4867936 | 692 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
693 | |
694 | if (mode->clock < 10000) | |
695 | return MODE_CLOCK_LOW; | |
696 | ||
0af78a2b DV |
697 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
698 | return MODE_H_ILLEGAL; | |
699 | ||
2d20411e | 700 | return intel_mode_valid_max_plane_size(dev_priv, mode); |
a4fc5ed6 KP |
701 | } |
702 | ||
830de422 | 703 | u32 intel_dp_pack_aux(const u8 *src, int src_bytes) |
a4fc5ed6 | 704 | { |
830de422 JN |
705 | int i; |
706 | u32 v = 0; | |
a4fc5ed6 KP |
707 | |
708 | if (src_bytes > 4) | |
709 | src_bytes = 4; | |
710 | for (i = 0; i < src_bytes; i++) | |
830de422 | 711 | v |= ((u32)src[i]) << ((3 - i) * 8); |
a4fc5ed6 KP |
712 | return v; |
713 | } | |
714 | ||
830de422 | 715 | static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) |
a4fc5ed6 KP |
716 | { |
717 | int i; | |
718 | if (dst_bytes > 4) | |
719 | dst_bytes = 4; | |
720 | for (i = 0; i < dst_bytes; i++) | |
721 | dst[i] = src >> ((3-i) * 8); | |
722 | } | |
723 | ||
bf13e81b | 724 | static void |
46bd8383 | 725 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); |
bf13e81b | 726 | static void |
46bd8383 | 727 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 728 | bool force_disable_vdd); |
335f752b | 729 | static void |
46bd8383 | 730 | intel_dp_pps_init(struct intel_dp *intel_dp); |
bf13e81b | 731 | |
69d93820 CW |
732 | static intel_wakeref_t |
733 | pps_lock(struct intel_dp *intel_dp) | |
773538e8 | 734 | { |
de25eb7f | 735 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 736 | intel_wakeref_t wakeref; |
773538e8 VS |
737 | |
738 | /* | |
40c7ae45 | 739 | * See intel_power_sequencer_reset() why we need |
773538e8 VS |
740 | * a power domain reference here. |
741 | */ | |
69d93820 CW |
742 | wakeref = intel_display_power_get(dev_priv, |
743 | intel_aux_power_domain(dp_to_dig_port(intel_dp))); | |
773538e8 VS |
744 | |
745 | mutex_lock(&dev_priv->pps_mutex); | |
69d93820 CW |
746 | |
747 | return wakeref; | |
773538e8 VS |
748 | } |
749 | ||
69d93820 CW |
750 | static intel_wakeref_t |
751 | pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) | |
773538e8 | 752 | { |
de25eb7f | 753 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
773538e8 VS |
754 | |
755 | mutex_unlock(&dev_priv->pps_mutex); | |
69d93820 CW |
756 | intel_display_power_put(dev_priv, |
757 | intel_aux_power_domain(dp_to_dig_port(intel_dp)), | |
758 | wakeref); | |
759 | return 0; | |
773538e8 VS |
760 | } |
761 | ||
69d93820 CW |
762 | #define with_pps_lock(dp, wf) \ |
763 | for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) | |
764 | ||
961a0db0 VS |
765 | static void |
766 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
767 | { | |
de25eb7f | 768 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
961a0db0 | 769 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
961a0db0 | 770 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
771 | bool pll_enabled, release_cl_override = false; |
772 | enum dpio_phy phy = DPIO_PHY(pipe); | |
773 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
830de422 | 774 | u32 DP; |
961a0db0 | 775 | |
eb020ca3 PB |
776 | if (drm_WARN(&dev_priv->drm, |
777 | intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, | |
778 | "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", | |
779 | pipe_name(pipe), intel_dig_port->base.base.base.id, | |
780 | intel_dig_port->base.base.name)) | |
961a0db0 VS |
781 | return; |
782 | ||
bdc6114e WK |
783 | drm_dbg_kms(&dev_priv->drm, |
784 | "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", | |
785 | pipe_name(pipe), intel_dig_port->base.base.base.id, | |
786 | intel_dig_port->base.base.name); | |
961a0db0 VS |
787 | |
788 | /* Preserve the BIOS-computed detected bit. This is | |
789 | * supposed to be read-only. | |
790 | */ | |
b4e33881 | 791 | DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; |
961a0db0 VS |
792 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
793 | DP |= DP_PORT_WIDTH(1); | |
794 | DP |= DP_LINK_TRAIN_PAT_1; | |
795 | ||
920a14b2 | 796 | if (IS_CHERRYVIEW(dev_priv)) |
59b74c49 VS |
797 | DP |= DP_PIPE_SEL_CHV(pipe); |
798 | else | |
799 | DP |= DP_PIPE_SEL(pipe); | |
961a0db0 | 800 | |
b4e33881 | 801 | pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; |
d288f65f VS |
802 | |
803 | /* | |
804 | * The DPLL for the pipe must be enabled for this to work. | |
805 | * So enable temporarily it if it's not already enabled. | |
806 | */ | |
0047eedc | 807 | if (!pll_enabled) { |
920a14b2 | 808 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
809 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
810 | ||
30ad9814 | 811 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 | 812 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
bdc6114e WK |
813 | drm_err(&dev_priv->drm, |
814 | "Failed to force on pll for pipe %c!\n", | |
815 | pipe_name(pipe)); | |
3f36b937 TU |
816 | return; |
817 | } | |
0047eedc | 818 | } |
d288f65f | 819 | |
961a0db0 VS |
820 | /* |
821 | * Similar magic as in intel_dp_enable_port(). | |
822 | * We _must_ do this port enable + disable trick | |
e7f2af78 | 823 | * to make this power sequencer lock onto the port. |
961a0db0 VS |
824 | * Otherwise even VDD force bit won't work. |
825 | */ | |
b4e33881 JN |
826 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
827 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
961a0db0 | 828 | |
b4e33881 JN |
829 | intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); |
830 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
961a0db0 | 831 | |
b4e33881 JN |
832 | intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); |
833 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
d288f65f | 834 | |
0047eedc | 835 | if (!pll_enabled) { |
30ad9814 | 836 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
837 | |
838 | if (release_cl_override) | |
839 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
840 | } | |
961a0db0 VS |
841 | } |
842 | ||
9f2bdb00 VS |
843 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
844 | { | |
845 | struct intel_encoder *encoder; | |
846 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
847 | ||
848 | /* | |
849 | * We don't have power sequencer currently. | |
850 | * Pick one that's not used by other ports. | |
851 | */ | |
14aa521c | 852 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 853 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
9f2bdb00 VS |
854 | |
855 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
eb020ca3 PB |
856 | drm_WARN_ON(&dev_priv->drm, |
857 | intel_dp->active_pipe != INVALID_PIPE && | |
858 | intel_dp->active_pipe != | |
859 | intel_dp->pps_pipe); | |
9f2bdb00 VS |
860 | |
861 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
862 | pipes &= ~(1 << intel_dp->pps_pipe); | |
863 | } else { | |
eb020ca3 PB |
864 | drm_WARN_ON(&dev_priv->drm, |
865 | intel_dp->pps_pipe != INVALID_PIPE); | |
9f2bdb00 VS |
866 | |
867 | if (intel_dp->active_pipe != INVALID_PIPE) | |
868 | pipes &= ~(1 << intel_dp->active_pipe); | |
869 | } | |
870 | } | |
871 | ||
872 | if (pipes == 0) | |
873 | return INVALID_PIPE; | |
874 | ||
875 | return ffs(pipes) - 1; | |
876 | } | |
877 | ||
bf13e81b JN |
878 | static enum pipe |
879 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
880 | { | |
de25eb7f | 881 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
bf13e81b | 882 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
a8c3344e | 883 | enum pipe pipe; |
bf13e81b | 884 | |
e39b999a | 885 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 886 | |
a8c3344e | 887 | /* We should never land here with regular DP ports */ |
eb020ca3 | 888 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); |
a8c3344e | 889 | |
eb020ca3 PB |
890 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE && |
891 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
9f2bdb00 | 892 | |
a4a5d2f8 VS |
893 | if (intel_dp->pps_pipe != INVALID_PIPE) |
894 | return intel_dp->pps_pipe; | |
895 | ||
9f2bdb00 | 896 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
897 | |
898 | /* | |
899 | * Didn't find one. This should not happen since there | |
900 | * are two power sequencers and up to two eDP ports. | |
901 | */ | |
eb020ca3 | 902 | if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)) |
a8c3344e | 903 | pipe = PIPE_A; |
a4a5d2f8 | 904 | |
46bd8383 | 905 | vlv_steal_power_sequencer(dev_priv, pipe); |
a8c3344e | 906 | intel_dp->pps_pipe = pipe; |
a4a5d2f8 | 907 | |
bdc6114e WK |
908 | drm_dbg_kms(&dev_priv->drm, |
909 | "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", | |
910 | pipe_name(intel_dp->pps_pipe), | |
911 | intel_dig_port->base.base.base.id, | |
912 | intel_dig_port->base.base.name); | |
a4a5d2f8 VS |
913 | |
914 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
915 | intel_dp_init_panel_power_sequencer(intel_dp); |
916 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 | 917 | |
961a0db0 VS |
918 | /* |
919 | * Even vdd force doesn't work until we've made | |
920 | * the power sequencer lock in on the port. | |
921 | */ | |
922 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
923 | |
924 | return intel_dp->pps_pipe; | |
925 | } | |
926 | ||
78597996 ID |
927 | static int |
928 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
929 | { | |
de25eb7f | 930 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
73c0fcac | 931 | int backlight_controller = dev_priv->vbt.backlight.controller; |
78597996 ID |
932 | |
933 | lockdep_assert_held(&dev_priv->pps_mutex); | |
934 | ||
935 | /* We should never land here with regular DP ports */ | |
eb020ca3 | 936 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); |
78597996 | 937 | |
78597996 | 938 | if (!intel_dp->pps_reset) |
73c0fcac | 939 | return backlight_controller; |
78597996 ID |
940 | |
941 | intel_dp->pps_reset = false; | |
942 | ||
943 | /* | |
944 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
945 | * has been setup during connector init. | |
946 | */ | |
46bd8383 | 947 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); |
78597996 | 948 | |
73c0fcac | 949 | return backlight_controller; |
78597996 ID |
950 | } |
951 | ||
6491ab27 VS |
952 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
953 | enum pipe pipe); | |
954 | ||
955 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
956 | enum pipe pipe) | |
957 | { | |
b4e33881 | 958 | return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
959 | } |
960 | ||
961 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
962 | enum pipe pipe) | |
963 | { | |
b4e33881 | 964 | return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
965 | } |
966 | ||
967 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
968 | enum pipe pipe) | |
969 | { | |
970 | return true; | |
971 | } | |
bf13e81b | 972 | |
a4a5d2f8 | 973 | static enum pipe |
6491ab27 VS |
974 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
975 | enum port port, | |
976 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
977 | { |
978 | enum pipe pipe; | |
bf13e81b | 979 | |
bf13e81b | 980 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
b4e33881 | 981 | u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & |
bf13e81b | 982 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
983 | |
984 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
985 | continue; | |
986 | ||
6491ab27 VS |
987 | if (!pipe_check(dev_priv, pipe)) |
988 | continue; | |
989 | ||
a4a5d2f8 | 990 | return pipe; |
bf13e81b JN |
991 | } |
992 | ||
a4a5d2f8 VS |
993 | return INVALID_PIPE; |
994 | } | |
995 | ||
996 | static void | |
997 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
998 | { | |
de25eb7f | 999 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a4a5d2f8 | 1000 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 1001 | enum port port = intel_dig_port->base.port; |
a4a5d2f8 VS |
1002 | |
1003 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1004 | ||
1005 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
1006 | /* first pick one where the panel is on */ |
1007 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
1008 | vlv_pipe_has_pp_on); | |
1009 | /* didn't find one? pick one where vdd is on */ | |
1010 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
1011 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
1012 | vlv_pipe_has_vdd_on); | |
1013 | /* didn't find one? pick one with just the correct port */ | |
1014 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
1015 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
1016 | vlv_pipe_any); | |
a4a5d2f8 VS |
1017 | |
1018 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
1019 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
bdc6114e WK |
1020 | drm_dbg_kms(&dev_priv->drm, |
1021 | "no initial power sequencer for [ENCODER:%d:%s]\n", | |
1022 | intel_dig_port->base.base.base.id, | |
1023 | intel_dig_port->base.base.name); | |
a4a5d2f8 | 1024 | return; |
bf13e81b JN |
1025 | } |
1026 | ||
bdc6114e WK |
1027 | drm_dbg_kms(&dev_priv->drm, |
1028 | "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", | |
1029 | intel_dig_port->base.base.base.id, | |
1030 | intel_dig_port->base.base.name, | |
1031 | pipe_name(intel_dp->pps_pipe)); | |
a4a5d2f8 | 1032 | |
46bd8383 VS |
1033 | intel_dp_init_panel_power_sequencer(intel_dp); |
1034 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
bf13e81b JN |
1035 | } |
1036 | ||
78597996 | 1037 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 1038 | { |
773538e8 VS |
1039 | struct intel_encoder *encoder; |
1040 | ||
a2ab4ab6 CW |
1041 | if (drm_WARN_ON(&dev_priv->drm, |
1042 | !(IS_VALLEYVIEW(dev_priv) || | |
1043 | IS_CHERRYVIEW(dev_priv) || | |
1044 | IS_GEN9_LP(dev_priv)))) | |
773538e8 VS |
1045 | return; |
1046 | ||
1047 | /* | |
1048 | * We can't grab pps_mutex here due to deadlock with power_domain | |
1049 | * mutex when power_domain functions are called while holding pps_mutex. | |
1050 | * That also means that in order to use pps_pipe the code needs to | |
1051 | * hold both a power domain reference and pps_mutex, and the power domain | |
1052 | * reference get/put must be done while _not_ holding pps_mutex. | |
1053 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
1054 | * should use them always. | |
1055 | */ | |
1056 | ||
14aa521c | 1057 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 1058 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7e732cac | 1059 | |
eb020ca3 PB |
1060 | drm_WARN_ON(&dev_priv->drm, |
1061 | intel_dp->active_pipe != INVALID_PIPE); | |
9f2bdb00 VS |
1062 | |
1063 | if (encoder->type != INTEL_OUTPUT_EDP) | |
1064 | continue; | |
1065 | ||
cc3f90f0 | 1066 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
1067 | intel_dp->pps_reset = true; |
1068 | else | |
1069 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 1070 | } |
bf13e81b JN |
1071 | } |
1072 | ||
8e8232d5 ID |
1073 | struct pps_registers { |
1074 | i915_reg_t pp_ctrl; | |
1075 | i915_reg_t pp_stat; | |
1076 | i915_reg_t pp_on; | |
1077 | i915_reg_t pp_off; | |
1078 | i915_reg_t pp_div; | |
1079 | }; | |
1080 | ||
46bd8383 | 1081 | static void intel_pps_get_registers(struct intel_dp *intel_dp, |
8e8232d5 ID |
1082 | struct pps_registers *regs) |
1083 | { | |
de25eb7f | 1084 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
44cb734c ID |
1085 | int pps_idx = 0; |
1086 | ||
8e8232d5 ID |
1087 | memset(regs, 0, sizeof(*regs)); |
1088 | ||
cc3f90f0 | 1089 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
1090 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
1091 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1092 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 1093 | |
44cb734c ID |
1094 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
1095 | regs->pp_stat = PP_STATUS(pps_idx); | |
1096 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
1097 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
ab3517c1 JN |
1098 | |
1099 | /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ | |
c6c30b91 | 1100 | if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) |
ab3517c1 JN |
1101 | regs->pp_div = INVALID_MMIO_REG; |
1102 | else | |
44cb734c | 1103 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
1104 | } |
1105 | ||
f0f59a00 VS |
1106 | static i915_reg_t |
1107 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 1108 | { |
8e8232d5 | 1109 | struct pps_registers regs; |
bf13e81b | 1110 | |
46bd8383 | 1111 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
1112 | |
1113 | return regs.pp_ctrl; | |
bf13e81b JN |
1114 | } |
1115 | ||
f0f59a00 VS |
1116 | static i915_reg_t |
1117 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 1118 | { |
8e8232d5 | 1119 | struct pps_registers regs; |
bf13e81b | 1120 | |
46bd8383 | 1121 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
1122 | |
1123 | return regs.pp_stat; | |
bf13e81b JN |
1124 | } |
1125 | ||
01527b31 CT |
1126 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
1127 | This function only applicable when panel PM state is not to be tracked */ | |
1128 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
1129 | void *unused) | |
1130 | { | |
1131 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
1132 | edp_notifier); | |
de25eb7f | 1133 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 1134 | intel_wakeref_t wakeref; |
01527b31 | 1135 | |
1853a9da | 1136 | if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) |
01527b31 CT |
1137 | return 0; |
1138 | ||
69d93820 CW |
1139 | with_pps_lock(intel_dp, wakeref) { |
1140 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
1141 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); | |
1142 | i915_reg_t pp_ctrl_reg, pp_div_reg; | |
1143 | u32 pp_div; | |
1144 | ||
1145 | pp_ctrl_reg = PP_CONTROL(pipe); | |
1146 | pp_div_reg = PP_DIVISOR(pipe); | |
b4e33881 | 1147 | pp_div = intel_de_read(dev_priv, pp_div_reg); |
69d93820 CW |
1148 | pp_div &= PP_REFERENCE_DIVIDER_MASK; |
1149 | ||
1150 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
b4e33881 JN |
1151 | intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F); |
1152 | intel_de_write(dev_priv, pp_ctrl_reg, | |
1153 | PANEL_UNLOCK_REGS); | |
69d93820 CW |
1154 | msleep(intel_dp->panel_power_cycle_delay); |
1155 | } | |
01527b31 CT |
1156 | } |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
4be73780 | 1161 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 1162 | { |
de25eb7f | 1163 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1164 | |
e39b999a VS |
1165 | lockdep_assert_held(&dev_priv->pps_mutex); |
1166 | ||
920a14b2 | 1167 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
1168 | intel_dp->pps_pipe == INVALID_PIPE) |
1169 | return false; | |
1170 | ||
b4e33881 | 1171 | return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
1172 | } |
1173 | ||
4be73780 | 1174 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 1175 | { |
de25eb7f | 1176 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1177 | |
e39b999a VS |
1178 | lockdep_assert_held(&dev_priv->pps_mutex); |
1179 | ||
920a14b2 | 1180 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
1181 | intel_dp->pps_pipe == INVALID_PIPE) |
1182 | return false; | |
1183 | ||
b4e33881 | 1184 | return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
1185 | } |
1186 | ||
9b984dae KP |
1187 | static void |
1188 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
1189 | { | |
de25eb7f | 1190 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1191 | |
1853a9da | 1192 | if (!intel_dp_is_edp(intel_dp)) |
9b984dae | 1193 | return; |
453c5420 | 1194 | |
4be73780 | 1195 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
eb020ca3 PB |
1196 | drm_WARN(&dev_priv->drm, 1, |
1197 | "eDP powered off while attempting aux channel communication.\n"); | |
bdc6114e | 1198 | drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", |
b4e33881 JN |
1199 | intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), |
1200 | intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
1201 | } |
1202 | } | |
1203 | ||
830de422 | 1204 | static u32 |
8a29c778 | 1205 | intel_dp_aux_wait_done(struct intel_dp *intel_dp) |
9ee32fea | 1206 | { |
5a31d30b | 1207 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
4904fa66 | 1208 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
54516464 | 1209 | const unsigned int timeout_ms = 10; |
830de422 | 1210 | u32 status; |
9ee32fea DV |
1211 | bool done; |
1212 | ||
5a31d30b TU |
1213 | #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1214 | done = wait_event_timeout(i915->gmbus_wait_queue, C, | |
54516464 | 1215 | msecs_to_jiffies_timeout(timeout_ms)); |
39806c3f VS |
1216 | |
1217 | /* just trace the final value */ | |
1218 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); | |
1219 | ||
9ee32fea | 1220 | if (!done) |
bdc6114e | 1221 | drm_err(&i915->drm, |
264c0247 | 1222 | "%s: did not complete or timeout within %ums (status 0x%08x)\n", |
bdc6114e | 1223 | intel_dp->aux.name, timeout_ms, status); |
9ee32fea DV |
1224 | #undef C |
1225 | ||
1226 | return status; | |
1227 | } | |
1228 | ||
830de422 | 1229 | static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 1230 | { |
de25eb7f | 1231 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
9ee32fea | 1232 | |
a457f54b VS |
1233 | if (index) |
1234 | return 0; | |
1235 | ||
ec5b01dd DL |
1236 | /* |
1237 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 1238 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 1239 | */ |
b04002f4 | 1240 | return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); |
ec5b01dd DL |
1241 | } |
1242 | ||
830de422 | 1243 | static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
ec5b01dd | 1244 | { |
de25eb7f | 1245 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 | 1246 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
b04002f4 | 1247 | u32 freq; |
ec5b01dd DL |
1248 | |
1249 | if (index) | |
1250 | return 0; | |
1251 | ||
a457f54b VS |
1252 | /* |
1253 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
1254 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
1255 | * divide by 2000 and use that | |
1256 | */ | |
563d22a0 | 1257 | if (dig_port->aux_ch == AUX_CH_A) |
b04002f4 | 1258 | freq = dev_priv->cdclk.hw.cdclk; |
e7dc33f3 | 1259 | else |
b04002f4 CW |
1260 | freq = RUNTIME_INFO(dev_priv)->rawclk_freq; |
1261 | return DIV_ROUND_CLOSEST(freq, 2000); | |
ec5b01dd DL |
1262 | } |
1263 | ||
830de422 | 1264 | static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
ec5b01dd | 1265 | { |
de25eb7f | 1266 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 | 1267 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
ec5b01dd | 1268 | |
563d22a0 | 1269 | if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 1270 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
1271 | switch (index) { |
1272 | case 0: return 63; | |
1273 | case 1: return 72; | |
1274 | default: return 0; | |
1275 | } | |
2c55c336 | 1276 | } |
a457f54b VS |
1277 | |
1278 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
1279 | } |
1280 | ||
830de422 | 1281 | static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
b6b5e383 DL |
1282 | { |
1283 | /* | |
1284 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
1285 | * derive the clock from CDCLK automatically). We still implement the | |
1286 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
1287 | */ | |
1288 | return index ? 0 : 1; | |
1289 | } | |
1290 | ||
830de422 JN |
1291 | static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
1292 | int send_bytes, | |
1293 | u32 aux_clock_divider) | |
5ed12a19 DL |
1294 | { |
1295 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
1296 | struct drm_i915_private *dev_priv = |
1297 | to_i915(intel_dig_port->base.base.dev); | |
830de422 | 1298 | u32 precharge, timeout; |
5ed12a19 | 1299 | |
cf819eff | 1300 | if (IS_GEN(dev_priv, 6)) |
5ed12a19 DL |
1301 | precharge = 3; |
1302 | else | |
1303 | precharge = 5; | |
1304 | ||
8f5f63d5 | 1305 | if (IS_BROADWELL(dev_priv)) |
5ed12a19 DL |
1306 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
1307 | else | |
1308 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
1309 | ||
1310 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 1311 | DP_AUX_CH_CTL_DONE | |
8a29c778 | 1312 | DP_AUX_CH_CTL_INTERRUPT | |
788d4433 | 1313 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 1314 | timeout | |
788d4433 | 1315 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
1316 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1317 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 1318 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
1319 | } |
1320 | ||
830de422 JN |
1321 | static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
1322 | int send_bytes, | |
1323 | u32 unused) | |
b9ca5fad | 1324 | { |
6f211ed4 | 1325 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
49748264 JRS |
1326 | struct drm_i915_private *i915 = |
1327 | to_i915(intel_dig_port->base.base.dev); | |
1328 | enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); | |
830de422 | 1329 | u32 ret; |
6f211ed4 AS |
1330 | |
1331 | ret = DP_AUX_CH_CTL_SEND_BUSY | | |
1332 | DP_AUX_CH_CTL_DONE | | |
1333 | DP_AUX_CH_CTL_INTERRUPT | | |
1334 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1335 | DP_AUX_CH_CTL_TIME_OUT_MAX | | |
1336 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
1337 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1338 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | | |
1339 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); | |
1340 | ||
49748264 JRS |
1341 | if (intel_phy_is_tc(i915, phy) && |
1342 | intel_dig_port->tc_mode == TC_PORT_TBT_ALT) | |
6f211ed4 AS |
1343 | ret |= DP_AUX_CH_CTL_TBT_IO; |
1344 | ||
1345 | return ret; | |
b9ca5fad DL |
1346 | } |
1347 | ||
b84a1cf8 | 1348 | static int |
f7606265 | 1349 | intel_dp_aux_xfer(struct intel_dp *intel_dp, |
830de422 JN |
1350 | const u8 *send, int send_bytes, |
1351 | u8 *recv, int recv_size, | |
8159c796 | 1352 | u32 aux_send_ctl_flags) |
b84a1cf8 RV |
1353 | { |
1354 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5a31d30b | 1355 | struct drm_i915_private *i915 = |
0031fb96 | 1356 | to_i915(intel_dig_port->base.base.dev); |
5a31d30b | 1357 | struct intel_uncore *uncore = &i915->uncore; |
d8fe2ab6 MR |
1358 | enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); |
1359 | bool is_tc_port = intel_phy_is_tc(i915, phy); | |
4904fa66 | 1360 | i915_reg_t ch_ctl, ch_data[5]; |
830de422 | 1361 | u32 aux_clock_divider; |
f39194a7 ID |
1362 | enum intel_display_power_domain aux_domain = |
1363 | intel_aux_power_domain(intel_dig_port); | |
1364 | intel_wakeref_t aux_wakeref; | |
1365 | intel_wakeref_t pps_wakeref; | |
b84a1cf8 | 1366 | int i, ret, recv_bytes; |
5ed12a19 | 1367 | int try, clock = 0; |
830de422 | 1368 | u32 status; |
884f19e9 JN |
1369 | bool vdd; |
1370 | ||
4904fa66 VS |
1371 | ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
1372 | for (i = 0; i < ARRAY_SIZE(ch_data); i++) | |
1373 | ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); | |
1374 | ||
8c10e226 ID |
1375 | if (is_tc_port) |
1376 | intel_tc_port_lock(intel_dig_port); | |
1377 | ||
5a31d30b | 1378 | aux_wakeref = intel_display_power_get(i915, aux_domain); |
f39194a7 | 1379 | pps_wakeref = pps_lock(intel_dp); |
e39b999a | 1380 | |
72c3500a VS |
1381 | /* |
1382 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1383 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1384 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1385 | * ourselves. | |
1386 | */ | |
1e0560e0 | 1387 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1388 | |
1389 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1390 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1391 | * deep sleep states. | |
1392 | */ | |
4d4dda48 | 1393 | cpu_latency_qos_update_request(&i915->pm_qos, 0); |
b84a1cf8 RV |
1394 | |
1395 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1396 | |
11bee43e JB |
1397 | /* Try to wait for any previous AUX channel activity */ |
1398 | for (try = 0; try < 3; try++) { | |
5a31d30b | 1399 | status = intel_uncore_read_notrace(uncore, ch_ctl); |
11bee43e JB |
1400 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1401 | break; | |
1402 | msleep(1); | |
1403 | } | |
39806c3f VS |
1404 | /* just trace the final value */ |
1405 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); | |
11bee43e JB |
1406 | |
1407 | if (try == 3) { | |
5a31d30b | 1408 | const u32 status = intel_uncore_read(uncore, ch_ctl); |
02196c77 | 1409 | |
81cdeca4 | 1410 | if (status != intel_dp->aux_busy_last_status) { |
eb020ca3 PB |
1411 | drm_WARN(&i915->drm, 1, |
1412 | "%s: not started (status 0x%08x)\n", | |
1413 | intel_dp->aux.name, status); | |
81cdeca4 | 1414 | intel_dp->aux_busy_last_status = status; |
02196c77 MK |
1415 | } |
1416 | ||
9ee32fea DV |
1417 | ret = -EBUSY; |
1418 | goto out; | |
4f7f7b7e CW |
1419 | } |
1420 | ||
46a5ae9f | 1421 | /* Only 5 data registers! */ |
eb020ca3 | 1422 | if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { |
46a5ae9f PZ |
1423 | ret = -E2BIG; |
1424 | goto out; | |
1425 | } | |
1426 | ||
ec5b01dd | 1427 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
8159c796 | 1428 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
8159c796 VS |
1429 | send_bytes, |
1430 | aux_clock_divider); | |
1431 | ||
1432 | send_ctl |= aux_send_ctl_flags; | |
5ed12a19 | 1433 | |
bc86625a CW |
1434 | /* Must try at least 3 times according to DP spec */ |
1435 | for (try = 0; try < 5; try++) { | |
1436 | /* Load the send data into the aux channel data registers */ | |
1437 | for (i = 0; i < send_bytes; i += 4) | |
5a31d30b TU |
1438 | intel_uncore_write(uncore, |
1439 | ch_data[i >> 2], | |
1440 | intel_dp_pack_aux(send + i, | |
1441 | send_bytes - i)); | |
bc86625a CW |
1442 | |
1443 | /* Send the command and wait for it to complete */ | |
5a31d30b | 1444 | intel_uncore_write(uncore, ch_ctl, send_ctl); |
bc86625a | 1445 | |
8a29c778 | 1446 | status = intel_dp_aux_wait_done(intel_dp); |
bc86625a CW |
1447 | |
1448 | /* Clear done status and any errors */ | |
5a31d30b TU |
1449 | intel_uncore_write(uncore, |
1450 | ch_ctl, | |
1451 | status | | |
1452 | DP_AUX_CH_CTL_DONE | | |
1453 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1454 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
bc86625a | 1455 | |
74ebf294 TP |
1456 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
1457 | * 400us delay required for errors and timeouts | |
1458 | * Timeout errors from the HW already meet this | |
1459 | * requirement so skip to next iteration | |
1460 | */ | |
3975f0aa DP |
1461 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
1462 | continue; | |
1463 | ||
74ebf294 TP |
1464 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1465 | usleep_range(400, 500); | |
bc86625a | 1466 | continue; |
74ebf294 | 1467 | } |
bc86625a | 1468 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1469 | goto done; |
bc86625a | 1470 | } |
a4fc5ed6 KP |
1471 | } |
1472 | ||
a4fc5ed6 | 1473 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
264c0247 VS |
1474 | drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", |
1475 | intel_dp->aux.name, status); | |
9ee32fea DV |
1476 | ret = -EBUSY; |
1477 | goto out; | |
a4fc5ed6 KP |
1478 | } |
1479 | ||
e058c945 | 1480 | done: |
a4fc5ed6 KP |
1481 | /* Check for timeout or receive error. |
1482 | * Timeouts occur when the sink is not connected | |
1483 | */ | |
a5b3da54 | 1484 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
264c0247 VS |
1485 | drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", |
1486 | intel_dp->aux.name, status); | |
9ee32fea DV |
1487 | ret = -EIO; |
1488 | goto out; | |
a5b3da54 | 1489 | } |
1ae8c0a5 KP |
1490 | |
1491 | /* Timeouts occur when the device isn't connected, so they're | |
1492 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1493 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
264c0247 VS |
1494 | drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", |
1495 | intel_dp->aux.name, status); | |
9ee32fea DV |
1496 | ret = -ETIMEDOUT; |
1497 | goto out; | |
a4fc5ed6 KP |
1498 | } |
1499 | ||
1500 | /* Unload any bytes sent back from the other side */ | |
1501 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1502 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1503 | |
1504 | /* | |
1505 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1506 | * We have no idea of what happened so we return -EBUSY so | |
1507 | * drm layer takes care for the necessary retries. | |
1508 | */ | |
1509 | if (recv_bytes == 0 || recv_bytes > 20) { | |
bdc6114e | 1510 | drm_dbg_kms(&i915->drm, |
264c0247 VS |
1511 | "%s: Forbidden recv_bytes = %d on aux transaction\n", |
1512 | intel_dp->aux.name, recv_bytes); | |
14e01889 RV |
1513 | ret = -EBUSY; |
1514 | goto out; | |
1515 | } | |
1516 | ||
a4fc5ed6 KP |
1517 | if (recv_bytes > recv_size) |
1518 | recv_bytes = recv_size; | |
0206e353 | 1519 | |
4f7f7b7e | 1520 | for (i = 0; i < recv_bytes; i += 4) |
5a31d30b | 1521 | intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), |
a4f1289e | 1522 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1523 | |
9ee32fea DV |
1524 | ret = recv_bytes; |
1525 | out: | |
4d4dda48 | 1526 | cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 1527 | |
884f19e9 JN |
1528 | if (vdd) |
1529 | edp_panel_vdd_off(intel_dp, false); | |
1530 | ||
f39194a7 | 1531 | pps_unlock(intel_dp, pps_wakeref); |
5a31d30b | 1532 | intel_display_power_put_async(i915, aux_domain, aux_wakeref); |
e39b999a | 1533 | |
8c10e226 ID |
1534 | if (is_tc_port) |
1535 | intel_tc_port_unlock(intel_dig_port); | |
1536 | ||
9ee32fea | 1537 | return ret; |
a4fc5ed6 KP |
1538 | } |
1539 | ||
a6c8aff0 JN |
1540 | #define BARE_ADDRESS_SIZE 3 |
1541 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
32078b72 VS |
1542 | |
1543 | static void | |
1544 | intel_dp_aux_header(u8 txbuf[HEADER_SIZE], | |
1545 | const struct drm_dp_aux_msg *msg) | |
1546 | { | |
1547 | txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); | |
1548 | txbuf[1] = (msg->address >> 8) & 0xff; | |
1549 | txbuf[2] = msg->address & 0xff; | |
1550 | txbuf[3] = msg->size - 1; | |
1551 | } | |
1552 | ||
9d1a1031 JN |
1553 | static ssize_t |
1554 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1555 | { |
9d1a1031 | 1556 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
830de422 | 1557 | u8 txbuf[20], rxbuf[20]; |
9d1a1031 | 1558 | size_t txsize, rxsize; |
a4fc5ed6 | 1559 | int ret; |
a4fc5ed6 | 1560 | |
32078b72 | 1561 | intel_dp_aux_header(txbuf, msg); |
46a5ae9f | 1562 | |
9d1a1031 JN |
1563 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1564 | case DP_AUX_NATIVE_WRITE: | |
1565 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1566 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1567 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1568 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1569 | |
9d1a1031 JN |
1570 | if (WARN_ON(txsize > 20)) |
1571 | return -E2BIG; | |
a4fc5ed6 | 1572 | |
dd788090 VS |
1573 | WARN_ON(!msg->buffer != !msg->size); |
1574 | ||
d81a67cc ID |
1575 | if (msg->buffer) |
1576 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1577 | |
f7606265 | 1578 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
8159c796 | 1579 | rxbuf, rxsize, 0); |
9d1a1031 JN |
1580 | if (ret > 0) { |
1581 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1582 | |
a1ddefd8 JN |
1583 | if (ret > 1) { |
1584 | /* Number of bytes written in a short write. */ | |
1585 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1586 | } else { | |
1587 | /* Return payload size. */ | |
1588 | ret = msg->size; | |
1589 | } | |
9d1a1031 JN |
1590 | } |
1591 | break; | |
46a5ae9f | 1592 | |
9d1a1031 JN |
1593 | case DP_AUX_NATIVE_READ: |
1594 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1595 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1596 | rxsize = msg->size + 1; |
a4fc5ed6 | 1597 | |
9d1a1031 JN |
1598 | if (WARN_ON(rxsize > 20)) |
1599 | return -E2BIG; | |
a4fc5ed6 | 1600 | |
f7606265 | 1601 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
8159c796 | 1602 | rxbuf, rxsize, 0); |
9d1a1031 JN |
1603 | if (ret > 0) { |
1604 | msg->reply = rxbuf[0] >> 4; | |
1605 | /* | |
1606 | * Assume happy day, and copy the data. The caller is | |
1607 | * expected to check msg->reply before touching it. | |
1608 | * | |
1609 | * Return payload size. | |
1610 | */ | |
1611 | ret--; | |
1612 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1613 | } |
9d1a1031 JN |
1614 | break; |
1615 | ||
1616 | default: | |
1617 | ret = -EINVAL; | |
1618 | break; | |
a4fc5ed6 | 1619 | } |
f51a44b9 | 1620 | |
9d1a1031 | 1621 | return ret; |
a4fc5ed6 KP |
1622 | } |
1623 | ||
8f7ce038 | 1624 | |
4904fa66 | 1625 | static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) |
da00bdcf | 1626 | { |
de25eb7f | 1627 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1628 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1629 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1630 | |
bdabdb63 VS |
1631 | switch (aux_ch) { |
1632 | case AUX_CH_B: | |
1633 | case AUX_CH_C: | |
1634 | case AUX_CH_D: | |
1635 | return DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1636 | default: |
bdabdb63 VS |
1637 | MISSING_CASE(aux_ch); |
1638 | return DP_AUX_CH_CTL(AUX_CH_B); | |
da00bdcf VS |
1639 | } |
1640 | } | |
1641 | ||
4904fa66 | 1642 | static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) |
330e20ec | 1643 | { |
de25eb7f | 1644 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1645 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1646 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1647 | |
bdabdb63 VS |
1648 | switch (aux_ch) { |
1649 | case AUX_CH_B: | |
1650 | case AUX_CH_C: | |
1651 | case AUX_CH_D: | |
1652 | return DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1653 | default: |
bdabdb63 VS |
1654 | MISSING_CASE(aux_ch); |
1655 | return DP_AUX_CH_DATA(AUX_CH_B, index); | |
330e20ec VS |
1656 | } |
1657 | } | |
1658 | ||
4904fa66 | 1659 | static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1660 | { |
de25eb7f | 1661 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1662 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1663 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1664 | |
bdabdb63 VS |
1665 | switch (aux_ch) { |
1666 | case AUX_CH_A: | |
1667 | return DP_AUX_CH_CTL(aux_ch); | |
1668 | case AUX_CH_B: | |
1669 | case AUX_CH_C: | |
1670 | case AUX_CH_D: | |
1671 | return PCH_DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1672 | default: |
bdabdb63 VS |
1673 | MISSING_CASE(aux_ch); |
1674 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1675 | } |
1676 | } | |
1677 | ||
4904fa66 | 1678 | static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1679 | { |
de25eb7f | 1680 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1681 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1682 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1683 | |
bdabdb63 VS |
1684 | switch (aux_ch) { |
1685 | case AUX_CH_A: | |
1686 | return DP_AUX_CH_DATA(aux_ch, index); | |
1687 | case AUX_CH_B: | |
1688 | case AUX_CH_C: | |
1689 | case AUX_CH_D: | |
1690 | return PCH_DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1691 | default: |
bdabdb63 VS |
1692 | MISSING_CASE(aux_ch); |
1693 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1694 | } |
1695 | } | |
1696 | ||
4904fa66 | 1697 | static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1698 | { |
de25eb7f | 1699 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1700 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1701 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1702 | |
bdabdb63 VS |
1703 | switch (aux_ch) { |
1704 | case AUX_CH_A: | |
1705 | case AUX_CH_B: | |
1706 | case AUX_CH_C: | |
1707 | case AUX_CH_D: | |
bb187e93 | 1708 | case AUX_CH_E: |
bdabdb63 | 1709 | case AUX_CH_F: |
eb8de23c | 1710 | case AUX_CH_G: |
bdabdb63 | 1711 | return DP_AUX_CH_CTL(aux_ch); |
da00bdcf | 1712 | default: |
bdabdb63 VS |
1713 | MISSING_CASE(aux_ch); |
1714 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1715 | } |
1716 | } | |
1717 | ||
4904fa66 | 1718 | static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1719 | { |
de25eb7f | 1720 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1721 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1722 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1723 | |
bdabdb63 VS |
1724 | switch (aux_ch) { |
1725 | case AUX_CH_A: | |
1726 | case AUX_CH_B: | |
1727 | case AUX_CH_C: | |
1728 | case AUX_CH_D: | |
bb187e93 | 1729 | case AUX_CH_E: |
bdabdb63 | 1730 | case AUX_CH_F: |
eb8de23c | 1731 | case AUX_CH_G: |
bdabdb63 | 1732 | return DP_AUX_CH_DATA(aux_ch, index); |
330e20ec | 1733 | default: |
bdabdb63 VS |
1734 | MISSING_CASE(aux_ch); |
1735 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1736 | } |
1737 | } | |
1738 | ||
91e939ae VS |
1739 | static void |
1740 | intel_dp_aux_fini(struct intel_dp *intel_dp) | |
1741 | { | |
1742 | kfree(intel_dp->aux.name); | |
1743 | } | |
1744 | ||
1745 | static void | |
1746 | intel_dp_aux_init(struct intel_dp *intel_dp) | |
330e20ec | 1747 | { |
de25eb7f | 1748 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1749 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1750 | struct intel_encoder *encoder = &dig_port->base; | |
91e939ae | 1751 | |
4904fa66 VS |
1752 | if (INTEL_GEN(dev_priv) >= 9) { |
1753 | intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; | |
1754 | intel_dp->aux_ch_data_reg = skl_aux_data_reg; | |
1755 | } else if (HAS_PCH_SPLIT(dev_priv)) { | |
1756 | intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; | |
1757 | intel_dp->aux_ch_data_reg = ilk_aux_data_reg; | |
1758 | } else { | |
1759 | intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; | |
1760 | intel_dp->aux_ch_data_reg = g4x_aux_data_reg; | |
1761 | } | |
330e20ec | 1762 | |
91e939ae VS |
1763 | if (INTEL_GEN(dev_priv) >= 9) |
1764 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
1765 | else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
1766 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
1767 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1768 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
1769 | else | |
1770 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; | |
bdabdb63 | 1771 | |
91e939ae VS |
1772 | if (INTEL_GEN(dev_priv) >= 9) |
1773 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
1774 | else | |
1775 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; | |
ab2c0672 | 1776 | |
7a418e34 | 1777 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1778 | |
7a418e34 | 1779 | /* Failure to allocate our preferred name is not critical */ |
a87e692a VS |
1780 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c", |
1781 | aux_ch_name(dig_port->aux_ch), | |
bdabdb63 | 1782 | port_name(encoder->port)); |
9d1a1031 | 1783 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1784 | } |
1785 | ||
e588fa18 | 1786 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1787 | { |
fc603ca7 | 1788 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
e588fa18 | 1789 | |
fc603ca7 | 1790 | return max_rate >= 540000; |
ed63baaf TS |
1791 | } |
1792 | ||
2edd5327 MN |
1793 | bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) |
1794 | { | |
1795 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; | |
1796 | ||
1797 | return max_rate >= 810000; | |
1798 | } | |
1799 | ||
c6bb3538 DV |
1800 | static void |
1801 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1802 | struct intel_crtc_state *pipe_config) |
c6bb3538 | 1803 | { |
2f773477 | 1804 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9dd4ffdf CML |
1805 | const struct dp_link_dpll *divisor = NULL; |
1806 | int i, count = 0; | |
c6bb3538 | 1807 | |
9beb5fea | 1808 | if (IS_G4X(dev_priv)) { |
45101e93 VS |
1809 | divisor = g4x_dpll; |
1810 | count = ARRAY_SIZE(g4x_dpll); | |
6e266956 | 1811 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1812 | divisor = pch_dpll; |
1813 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1814 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1815 | divisor = chv_dpll; |
1816 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1817 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1818 | divisor = vlv_dpll; |
1819 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1820 | } |
9dd4ffdf CML |
1821 | |
1822 | if (divisor && count) { | |
1823 | for (i = 0; i < count; i++) { | |
840b32b7 | 1824 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1825 | pipe_config->dpll = divisor[i].dpll; |
1826 | pipe_config->clock_set = true; | |
1827 | break; | |
1828 | } | |
1829 | } | |
c6bb3538 DV |
1830 | } |
1831 | } | |
1832 | ||
0336400e VS |
1833 | static void snprintf_int_array(char *str, size_t len, |
1834 | const int *array, int nelem) | |
1835 | { | |
1836 | int i; | |
1837 | ||
1838 | str[0] = '\0'; | |
1839 | ||
1840 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1841 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1842 | if (r >= len) |
1843 | return; | |
1844 | str += r; | |
1845 | len -= r; | |
1846 | } | |
1847 | } | |
1848 | ||
1849 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1850 | { | |
af67009c | 1851 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
0336400e VS |
1852 | char str[128]; /* FIXME: too big for stack? */ |
1853 | ||
bdbf43d7 | 1854 | if (!drm_debug_enabled(DRM_UT_KMS)) |
0336400e VS |
1855 | return; |
1856 | ||
55cfc580 JN |
1857 | snprintf_int_array(str, sizeof(str), |
1858 | intel_dp->source_rates, intel_dp->num_source_rates); | |
af67009c | 1859 | drm_dbg_kms(&i915->drm, "source rates: %s\n", str); |
0336400e | 1860 | |
68f357cb JN |
1861 | snprintf_int_array(str, sizeof(str), |
1862 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
af67009c | 1863 | drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); |
0336400e | 1864 | |
975ee5fc JN |
1865 | snprintf_int_array(str, sizeof(str), |
1866 | intel_dp->common_rates, intel_dp->num_common_rates); | |
af67009c | 1867 | drm_dbg_kms(&i915->drm, "common rates: %s\n", str); |
0336400e VS |
1868 | } |
1869 | ||
50fec21a VS |
1870 | int |
1871 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1872 | { | |
50fec21a VS |
1873 | int len; |
1874 | ||
e6c0c64a | 1875 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
50fec21a VS |
1876 | if (WARN_ON(len <= 0)) |
1877 | return 162000; | |
1878 | ||
975ee5fc | 1879 | return intel_dp->common_rates[len - 1]; |
50fec21a VS |
1880 | } |
1881 | ||
ed4e9c1d VS |
1882 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1883 | { | |
8001b754 JN |
1884 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1885 | intel_dp->num_sink_rates, rate); | |
b5c72b20 JN |
1886 | |
1887 | if (WARN_ON(i < 0)) | |
1888 | i = 0; | |
1889 | ||
1890 | return i; | |
ed4e9c1d VS |
1891 | } |
1892 | ||
94223d04 | 1893 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
830de422 | 1894 | u8 *link_bw, u8 *rate_select) |
04a60f9f | 1895 | { |
68f357cb JN |
1896 | /* eDP 1.4 rate select method. */ |
1897 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1898 | *link_bw = 0; |
1899 | *rate_select = | |
1900 | intel_dp_rate_select(intel_dp, port_clock); | |
1901 | } else { | |
1902 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1903 | *rate_select = 0; | |
1904 | } | |
1905 | } | |
1906 | ||
240999cf | 1907 | static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, |
a4a15777 MN |
1908 | const struct intel_crtc_state *pipe_config) |
1909 | { | |
1910 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1911 | ||
9770f220 MTP |
1912 | /* On TGL, FEC is supported on all Pipes */ |
1913 | if (INTEL_GEN(dev_priv) >= 12) | |
1914 | return true; | |
1915 | ||
1916 | if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) | |
1917 | return true; | |
1918 | ||
1919 | return false; | |
240999cf AS |
1920 | } |
1921 | ||
1922 | static bool intel_dp_supports_fec(struct intel_dp *intel_dp, | |
1923 | const struct intel_crtc_state *pipe_config) | |
1924 | { | |
1925 | return intel_dp_source_supports_fec(intel_dp, pipe_config) && | |
1926 | drm_dp_sink_supports_fec(intel_dp->fec_capable); | |
1927 | } | |
1928 | ||
a4a15777 | 1929 | static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, |
deaaff49 | 1930 | const struct intel_crtc_state *crtc_state) |
a4a15777 | 1931 | { |
deaaff49 JN |
1932 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
1933 | ||
1934 | if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable) | |
240999cf AS |
1935 | return false; |
1936 | ||
deaaff49 | 1937 | return intel_dsc_source_support(encoder, crtc_state) && |
a4a15777 MN |
1938 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); |
1939 | } | |
1940 | ||
f580bea9 JN |
1941 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1942 | struct intel_crtc_state *pipe_config) | |
f9bb705e | 1943 | { |
de25eb7f | 1944 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ef32659a | 1945 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
f9bb705e MK |
1946 | int bpp, bpc; |
1947 | ||
1948 | bpp = pipe_config->pipe_bpp; | |
1949 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1950 | ||
1951 | if (bpc > 0) | |
1952 | bpp = min(bpp, 3*bpc); | |
1953 | ||
ef32659a JN |
1954 | if (intel_dp_is_edp(intel_dp)) { |
1955 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1956 | if (intel_connector->base.display_info.bpc == 0 && | |
1957 | dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { | |
bdc6114e WK |
1958 | drm_dbg_kms(&dev_priv->drm, |
1959 | "clamping bpp for eDP panel to BIOS-provided %i\n", | |
1960 | dev_priv->vbt.edp.bpp); | |
ef32659a JN |
1961 | bpp = dev_priv->vbt.edp.bpp; |
1962 | } | |
1963 | } | |
1964 | ||
f9bb705e MK |
1965 | return bpp; |
1966 | } | |
1967 | ||
a4971453 | 1968 | /* Adjust link config limits based on compliance test requests. */ |
f1477219 | 1969 | void |
a4971453 JN |
1970 | intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, |
1971 | struct intel_crtc_state *pipe_config, | |
1972 | struct link_config_limits *limits) | |
1973 | { | |
af67009c JN |
1974 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
1975 | ||
a4971453 JN |
1976 | /* For DP Compliance we override the computed bpp for the pipe */ |
1977 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1978 | int bpp = 3 * intel_dp->compliance.test_data.bpc; | |
1979 | ||
1980 | limits->min_bpp = limits->max_bpp = bpp; | |
1981 | pipe_config->dither_force_disable = bpp == 6 * 3; | |
1982 | ||
af67009c | 1983 | drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); |
a4971453 JN |
1984 | } |
1985 | ||
1986 | /* Use values requested by Compliance Test Request */ | |
1987 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
1988 | int index; | |
1989 | ||
1990 | /* Validate the compliance test data since max values | |
1991 | * might have changed due to link train fallback. | |
1992 | */ | |
1993 | if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, | |
1994 | intel_dp->compliance.test_lane_count)) { | |
1995 | index = intel_dp_rate_index(intel_dp->common_rates, | |
1996 | intel_dp->num_common_rates, | |
1997 | intel_dp->compliance.test_link_rate); | |
1998 | if (index >= 0) | |
1999 | limits->min_clock = limits->max_clock = index; | |
2000 | limits->min_lane_count = limits->max_lane_count = | |
2001 | intel_dp->compliance.test_lane_count; | |
2002 | } | |
2003 | } | |
2004 | } | |
2005 | ||
16668f48 GM |
2006 | static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp) |
2007 | { | |
2008 | /* | |
2009 | * bpp value was assumed to RGB format. And YCbCr 4:2:0 output | |
2010 | * format of the number of bytes per pixel will be half the number | |
2011 | * of bytes of RGB pixel. | |
2012 | */ | |
2013 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
2014 | bpp /= 2; | |
2015 | ||
2016 | return bpp; | |
2017 | } | |
2018 | ||
3acd115d | 2019 | /* Optimize link config in order: max bpp, min clock, min lanes */ |
204474a6 | 2020 | static int |
3acd115d JN |
2021 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, |
2022 | struct intel_crtc_state *pipe_config, | |
2023 | const struct link_config_limits *limits) | |
2024 | { | |
1326a92c | 2025 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
3acd115d JN |
2026 | int bpp, clock, lane_count; |
2027 | int mode_rate, link_clock, link_avail; | |
2028 | ||
2029 | for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { | |
ddb3d12a VS |
2030 | int output_bpp = intel_dp_output_bpp(pipe_config, bpp); |
2031 | ||
3acd115d | 2032 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
ddb3d12a | 2033 | output_bpp); |
3acd115d JN |
2034 | |
2035 | for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { | |
2036 | for (lane_count = limits->min_lane_count; | |
2037 | lane_count <= limits->max_lane_count; | |
2038 | lane_count <<= 1) { | |
2039 | link_clock = intel_dp->common_rates[clock]; | |
2040 | link_avail = intel_dp_max_data_rate(link_clock, | |
2041 | lane_count); | |
2042 | ||
2043 | if (mode_rate <= link_avail) { | |
2044 | pipe_config->lane_count = lane_count; | |
2045 | pipe_config->pipe_bpp = bpp; | |
2046 | pipe_config->port_clock = link_clock; | |
2047 | ||
204474a6 | 2048 | return 0; |
3acd115d JN |
2049 | } |
2050 | } | |
2051 | } | |
2052 | } | |
2053 | ||
204474a6 | 2054 | return -EINVAL; |
3acd115d JN |
2055 | } |
2056 | ||
a4a15777 MN |
2057 | static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) |
2058 | { | |
2059 | int i, num_bpc; | |
2060 | u8 dsc_bpc[3] = {0}; | |
2061 | ||
2062 | num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, | |
2063 | dsc_bpc); | |
2064 | for (i = 0; i < num_bpc; i++) { | |
2065 | if (dsc_max_bpc >= dsc_bpc[i]) | |
2066 | return dsc_bpc[i] * 3; | |
2067 | } | |
2068 | ||
2069 | return 0; | |
2070 | } | |
2071 | ||
7a7b5be9 JN |
2072 | #define DSC_SUPPORTED_VERSION_MIN 1 |
2073 | ||
2074 | static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, | |
2075 | struct intel_crtc_state *crtc_state) | |
2076 | { | |
af67009c | 2077 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
b7d02c3a | 2078 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7a7b5be9 JN |
2079 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; |
2080 | u8 line_buf_depth; | |
2081 | int ret; | |
2082 | ||
2083 | ret = intel_dsc_compute_params(encoder, crtc_state); | |
2084 | if (ret) | |
2085 | return ret; | |
2086 | ||
c42c38ec JN |
2087 | /* |
2088 | * Slice Height of 8 works for all currently available panels. So start | |
2089 | * with that if pic_height is an integral multiple of 8. Eventually add | |
2090 | * logic to try multiple slice heights. | |
2091 | */ | |
2092 | if (vdsc_cfg->pic_height % 8 == 0) | |
2093 | vdsc_cfg->slice_height = 8; | |
2094 | else if (vdsc_cfg->pic_height % 4 == 0) | |
2095 | vdsc_cfg->slice_height = 4; | |
2096 | else | |
2097 | vdsc_cfg->slice_height = 2; | |
2098 | ||
7a7b5be9 JN |
2099 | vdsc_cfg->dsc_version_major = |
2100 | (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & | |
2101 | DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; | |
2102 | vdsc_cfg->dsc_version_minor = | |
2103 | min(DSC_SUPPORTED_VERSION_MIN, | |
2104 | (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & | |
2105 | DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); | |
2106 | ||
2107 | vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & | |
2108 | DP_DSC_RGB; | |
2109 | ||
2110 | line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); | |
2111 | if (!line_buf_depth) { | |
af67009c JN |
2112 | drm_dbg_kms(&i915->drm, |
2113 | "DSC Sink Line Buffer Depth invalid\n"); | |
7a7b5be9 JN |
2114 | return -EINVAL; |
2115 | } | |
2116 | ||
2117 | if (vdsc_cfg->dsc_version_minor == 2) | |
2118 | vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? | |
2119 | DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; | |
2120 | else | |
2121 | vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? | |
2122 | DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; | |
2123 | ||
2124 | vdsc_cfg->block_pred_enable = | |
2125 | intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & | |
2126 | DP_DSC_BLK_PREDICTION_IS_SUPPORTED; | |
2127 | ||
2128 | return drm_dsc_compute_rc_parameters(vdsc_cfg); | |
2129 | } | |
2130 | ||
204474a6 LP |
2131 | static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
2132 | struct intel_crtc_state *pipe_config, | |
2133 | struct drm_connector_state *conn_state, | |
2134 | struct link_config_limits *limits) | |
a4a15777 MN |
2135 | { |
2136 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2137 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
0c1abaa7 VS |
2138 | const struct drm_display_mode *adjusted_mode = |
2139 | &pipe_config->hw.adjusted_mode; | |
a4a15777 MN |
2140 | u8 dsc_max_bpc; |
2141 | int pipe_bpp; | |
204474a6 | 2142 | int ret; |
a4a15777 | 2143 | |
6fd3134a VS |
2144 | pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && |
2145 | intel_dp_supports_fec(intel_dp, pipe_config); | |
2146 | ||
a4a15777 | 2147 | if (!intel_dp_supports_dsc(intel_dp, pipe_config)) |
204474a6 | 2148 | return -EINVAL; |
a4a15777 | 2149 | |
cee508a0 AS |
2150 | /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ |
2151 | if (INTEL_GEN(dev_priv) >= 12) | |
2152 | dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); | |
2153 | else | |
2154 | dsc_max_bpc = min_t(u8, 10, | |
2155 | conn_state->max_requested_bpc); | |
a4a15777 MN |
2156 | |
2157 | pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); | |
cee508a0 AS |
2158 | |
2159 | /* Min Input BPC for ICL+ is 8 */ | |
2160 | if (pipe_bpp < 8 * 3) { | |
bdc6114e WK |
2161 | drm_dbg_kms(&dev_priv->drm, |
2162 | "No DSC support for less than 8bpc\n"); | |
204474a6 | 2163 | return -EINVAL; |
a4a15777 MN |
2164 | } |
2165 | ||
2166 | /* | |
2167 | * For now enable DSC for max bpp, max link rate, max lane count. | |
2168 | * Optimize this later for the minimum possible link rate/lane count | |
2169 | * with DSC enabled for the requested mode. | |
2170 | */ | |
2171 | pipe_config->pipe_bpp = pipe_bpp; | |
2172 | pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; | |
2173 | pipe_config->lane_count = limits->max_lane_count; | |
2174 | ||
2175 | if (intel_dp_is_edp(intel_dp)) { | |
010663a6 | 2176 | pipe_config->dsc.compressed_bpp = |
a4a15777 MN |
2177 | min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, |
2178 | pipe_config->pipe_bpp); | |
010663a6 | 2179 | pipe_config->dsc.slice_count = |
a4a15777 MN |
2180 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
2181 | true); | |
2182 | } else { | |
2183 | u16 dsc_max_output_bpp; | |
2184 | u8 dsc_dp_slice_count; | |
2185 | ||
2186 | dsc_max_output_bpp = | |
45d3c5cd MR |
2187 | intel_dp_dsc_get_output_bpp(dev_priv, |
2188 | pipe_config->port_clock, | |
a4a15777 MN |
2189 | pipe_config->lane_count, |
2190 | adjusted_mode->crtc_clock, | |
2191 | adjusted_mode->crtc_hdisplay); | |
2192 | dsc_dp_slice_count = | |
2193 | intel_dp_dsc_get_slice_count(intel_dp, | |
2194 | adjusted_mode->crtc_clock, | |
2195 | adjusted_mode->crtc_hdisplay); | |
2196 | if (!dsc_max_output_bpp || !dsc_dp_slice_count) { | |
bdc6114e WK |
2197 | drm_dbg_kms(&dev_priv->drm, |
2198 | "Compressed BPP/Slice Count not supported\n"); | |
204474a6 | 2199 | return -EINVAL; |
a4a15777 | 2200 | } |
010663a6 | 2201 | pipe_config->dsc.compressed_bpp = min_t(u16, |
a4a15777 MN |
2202 | dsc_max_output_bpp >> 4, |
2203 | pipe_config->pipe_bpp); | |
010663a6 | 2204 | pipe_config->dsc.slice_count = dsc_dp_slice_count; |
a4a15777 MN |
2205 | } |
2206 | /* | |
2207 | * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate | |
2208 | * is greater than the maximum Cdclock and if slice count is even | |
2209 | * then we need to use 2 VDSC instances. | |
2210 | */ | |
2211 | if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { | |
010663a6 JN |
2212 | if (pipe_config->dsc.slice_count > 1) { |
2213 | pipe_config->dsc.dsc_split = true; | |
a4a15777 | 2214 | } else { |
bdc6114e WK |
2215 | drm_dbg_kms(&dev_priv->drm, |
2216 | "Cannot split stream to use 2 VDSC instances\n"); | |
204474a6 | 2217 | return -EINVAL; |
a4a15777 MN |
2218 | } |
2219 | } | |
204474a6 | 2220 | |
7a7b5be9 | 2221 | ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); |
204474a6 | 2222 | if (ret < 0) { |
bdc6114e WK |
2223 | drm_dbg_kms(&dev_priv->drm, |
2224 | "Cannot compute valid DSC parameters for Input Bpp = %d " | |
2225 | "Compressed BPP = %d\n", | |
2226 | pipe_config->pipe_bpp, | |
2227 | pipe_config->dsc.compressed_bpp); | |
204474a6 | 2228 | return ret; |
168243c1 | 2229 | } |
204474a6 | 2230 | |
010663a6 | 2231 | pipe_config->dsc.compression_enable = true; |
bdc6114e WK |
2232 | drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " |
2233 | "Compressed Bpp = %d Slice Count = %d\n", | |
2234 | pipe_config->pipe_bpp, | |
2235 | pipe_config->dsc.compressed_bpp, | |
2236 | pipe_config->dsc.slice_count); | |
a4a15777 | 2237 | |
204474a6 | 2238 | return 0; |
a4a15777 MN |
2239 | } |
2240 | ||
4e2056e0 VS |
2241 | int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state) |
2242 | { | |
2243 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) | |
2244 | return 6 * 3; | |
2245 | else | |
2246 | return 8 * 3; | |
2247 | } | |
2248 | ||
204474a6 | 2249 | static int |
981a63eb | 2250 | intel_dp_compute_link_config(struct intel_encoder *encoder, |
a4a15777 MN |
2251 | struct intel_crtc_state *pipe_config, |
2252 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 2253 | { |
af67009c | 2254 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
0c1abaa7 VS |
2255 | const struct drm_display_mode *adjusted_mode = |
2256 | &pipe_config->hw.adjusted_mode; | |
b7d02c3a | 2257 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7c2781e4 | 2258 | struct link_config_limits limits; |
94ca719e | 2259 | int common_len; |
204474a6 | 2260 | int ret; |
7c2781e4 | 2261 | |
975ee5fc | 2262 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
e6c0c64a | 2263 | intel_dp->max_link_rate); |
a8f3ef61 SJ |
2264 | |
2265 | /* No common link rates between source and sink */ | |
3a47ae20 | 2266 | drm_WARN_ON(encoder->base.dev, common_len <= 0); |
a8f3ef61 | 2267 | |
7c2781e4 JN |
2268 | limits.min_clock = 0; |
2269 | limits.max_clock = common_len - 1; | |
2270 | ||
2271 | limits.min_lane_count = 1; | |
2272 | limits.max_lane_count = intel_dp_max_lane_count(intel_dp); | |
2273 | ||
4e2056e0 | 2274 | limits.min_bpp = intel_dp_min_bpp(pipe_config); |
7c2781e4 | 2275 | limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
a4fc5ed6 | 2276 | |
f11cb1c1 | 2277 | if (intel_dp_is_edp(intel_dp)) { |
344c5bbc JN |
2278 | /* |
2279 | * Use the maximum clock and number of lanes the eDP panel | |
f11cb1c1 JN |
2280 | * advertizes being capable of. The panels are generally |
2281 | * designed to support only a single clock and lane | |
2282 | * configuration, and typically these values correspond to the | |
2283 | * native resolution of the panel. | |
344c5bbc | 2284 | */ |
7c2781e4 JN |
2285 | limits.min_lane_count = limits.max_lane_count; |
2286 | limits.min_clock = limits.max_clock; | |
7984211e | 2287 | } |
657445fe | 2288 | |
a4971453 JN |
2289 | intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |
2290 | ||
af67009c JN |
2291 | drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " |
2292 | "max rate %d max bpp %d pixel clock %iKHz\n", | |
2293 | limits.max_lane_count, | |
2294 | intel_dp->common_rates[limits.max_clock], | |
2295 | limits.max_bpp, adjusted_mode->crtc_clock); | |
7c2781e4 | 2296 | |
f11cb1c1 JN |
2297 | /* |
2298 | * Optimize for slow and wide. This is the place to add alternative | |
2299 | * optimization policy. | |
2300 | */ | |
2301 | ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); | |
a4a15777 MN |
2302 | |
2303 | /* enable compression if the mode doesn't fit available BW */ | |
af67009c | 2304 | drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); |
204474a6 LP |
2305 | if (ret || intel_dp->force_dsc_en) { |
2306 | ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, | |
2307 | conn_state, &limits); | |
2308 | if (ret < 0) | |
2309 | return ret; | |
7769db58 | 2310 | } |
981a63eb | 2311 | |
010663a6 | 2312 | if (pipe_config->dsc.compression_enable) { |
af67009c JN |
2313 | drm_dbg_kms(&i915->drm, |
2314 | "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", | |
2315 | pipe_config->lane_count, pipe_config->port_clock, | |
2316 | pipe_config->pipe_bpp, | |
2317 | pipe_config->dsc.compressed_bpp); | |
2318 | ||
2319 | drm_dbg_kms(&i915->drm, | |
2320 | "DP link rate required %i available %i\n", | |
2321 | intel_dp_link_required(adjusted_mode->crtc_clock, | |
2322 | pipe_config->dsc.compressed_bpp), | |
2323 | intel_dp_max_data_rate(pipe_config->port_clock, | |
2324 | pipe_config->lane_count)); | |
a4a15777 | 2325 | } else { |
af67009c JN |
2326 | drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", |
2327 | pipe_config->lane_count, pipe_config->port_clock, | |
2328 | pipe_config->pipe_bpp); | |
a4a15777 | 2329 | |
af67009c JN |
2330 | drm_dbg_kms(&i915->drm, |
2331 | "DP link rate required %i available %i\n", | |
2332 | intel_dp_link_required(adjusted_mode->crtc_clock, | |
2333 | pipe_config->pipe_bpp), | |
2334 | intel_dp_max_data_rate(pipe_config->port_clock, | |
2335 | pipe_config->lane_count)); | |
a4a15777 | 2336 | } |
204474a6 | 2337 | return 0; |
981a63eb JN |
2338 | } |
2339 | ||
8e9d645c GM |
2340 | static int |
2341 | intel_dp_ycbcr420_config(struct intel_dp *intel_dp, | |
4cecc7c0 VS |
2342 | struct intel_crtc_state *crtc_state, |
2343 | const struct drm_connector_state *conn_state) | |
8e9d645c | 2344 | { |
4cecc7c0 | 2345 | struct drm_connector *connector = conn_state->connector; |
8e9d645c GM |
2346 | const struct drm_display_info *info = &connector->display_info; |
2347 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 2348 | &crtc_state->hw.adjusted_mode; |
8e9d645c GM |
2349 | |
2350 | if (!drm_mode_is_420_only(info, adjusted_mode) || | |
2351 | !intel_dp_get_colorimetry_status(intel_dp) || | |
2352 | !connector->ycbcr_420_allowed) | |
2353 | return 0; | |
2354 | ||
2355 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; | |
2356 | ||
d7ff281c | 2357 | return intel_pch_panel_fitting(crtc_state, conn_state); |
8e9d645c GM |
2358 | } |
2359 | ||
37aa52bf VS |
2360 | bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
2361 | const struct drm_connector_state *conn_state) | |
2362 | { | |
2363 | const struct intel_digital_connector_state *intel_conn_state = | |
2364 | to_intel_digital_connector_state(conn_state); | |
2365 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 2366 | &crtc_state->hw.adjusted_mode; |
37aa52bf | 2367 | |
cae154fc VS |
2368 | /* |
2369 | * Our YCbCr output is always limited range. | |
2370 | * crtc_state->limited_color_range only applies to RGB, | |
2371 | * and it must never be set for YCbCr or we risk setting | |
2372 | * some conflicting bits in PIPECONF which will mess up | |
2373 | * the colors on the monitor. | |
2374 | */ | |
2375 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
2376 | return false; | |
2377 | ||
37aa52bf VS |
2378 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
2379 | /* | |
2380 | * See: | |
2381 | * CEA-861-E - 5.1 Default Encoding Parameters | |
2382 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
2383 | */ | |
2384 | return crtc_state->pipe_bpp != 18 && | |
2385 | drm_default_rgb_quant_range(adjusted_mode) == | |
2386 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
2387 | } else { | |
2388 | return intel_conn_state->broadcast_rgb == | |
2389 | INTEL_BROADCAST_RGB_LIMITED; | |
2390 | } | |
2391 | } | |
2392 | ||
07130981 KV |
2393 | static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, |
2394 | enum port port) | |
2395 | { | |
2396 | if (IS_G4X(dev_priv)) | |
2397 | return false; | |
2398 | if (INTEL_GEN(dev_priv) < 12 && port == PORT_A) | |
2399 | return false; | |
2400 | ||
2401 | return true; | |
2402 | } | |
2403 | ||
9799c4c3 GM |
2404 | static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, |
2405 | const struct drm_connector_state *conn_state, | |
2406 | struct drm_dp_vsc_sdp *vsc) | |
2407 | { | |
2408 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
2409 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
2410 | ||
2411 | /* | |
2412 | * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 | |
2413 | * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ | |
2414 | * Colorimetry Format indication. | |
2415 | */ | |
2416 | vsc->revision = 0x5; | |
2417 | vsc->length = 0x13; | |
2418 | ||
2419 | /* DP 1.4a spec, Table 2-120 */ | |
2420 | switch (crtc_state->output_format) { | |
2421 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
2422 | vsc->pixelformat = DP_PIXELFORMAT_YUV444; | |
2423 | break; | |
2424 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
2425 | vsc->pixelformat = DP_PIXELFORMAT_YUV420; | |
2426 | break; | |
2427 | case INTEL_OUTPUT_FORMAT_RGB: | |
2428 | default: | |
2429 | vsc->pixelformat = DP_PIXELFORMAT_RGB; | |
2430 | } | |
2431 | ||
2432 | switch (conn_state->colorspace) { | |
2433 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
2434 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; | |
2435 | break; | |
2436 | case DRM_MODE_COLORIMETRY_XVYCC_601: | |
2437 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; | |
2438 | break; | |
2439 | case DRM_MODE_COLORIMETRY_XVYCC_709: | |
2440 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; | |
2441 | break; | |
2442 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
2443 | vsc->colorimetry = DP_COLORIMETRY_SYCC_601; | |
2444 | break; | |
2445 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
2446 | vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; | |
2447 | break; | |
2448 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
2449 | vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; | |
2450 | break; | |
2451 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
2452 | vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; | |
2453 | break; | |
2454 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
2455 | vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; | |
2456 | break; | |
2457 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: | |
2458 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: | |
2459 | vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; | |
2460 | break; | |
2461 | default: | |
2462 | /* | |
2463 | * RGB->YCBCR color conversion uses the BT.709 | |
2464 | * color space. | |
2465 | */ | |
2466 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
2467 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; | |
2468 | else | |
2469 | vsc->colorimetry = DP_COLORIMETRY_DEFAULT; | |
2470 | break; | |
2471 | } | |
2472 | ||
2473 | vsc->bpc = crtc_state->pipe_bpp / 3; | |
2474 | ||
2475 | /* only RGB pixelformat supports 6 bpc */ | |
2476 | drm_WARN_ON(&dev_priv->drm, | |
2477 | vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); | |
2478 | ||
2479 | /* all YCbCr are always limited range */ | |
2480 | vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; | |
2481 | vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; | |
2482 | } | |
2483 | ||
2484 | static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, | |
2485 | struct intel_crtc_state *crtc_state, | |
2486 | const struct drm_connector_state *conn_state) | |
2487 | { | |
2488 | struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; | |
2489 | ||
2490 | /* When PSR is enabled, VSC SDP is handled by PSR routine */ | |
2491 | if (intel_psr_enabled(intel_dp)) | |
2492 | return; | |
2493 | ||
2494 | if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) | |
2495 | return; | |
2496 | ||
2497 | crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); | |
2498 | vsc->sdp_type = DP_SDP_VSC; | |
2499 | intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, | |
2500 | &crtc_state->infoframes.vsc); | |
2501 | } | |
2502 | ||
d1eed96d GM |
2503 | static void |
2504 | intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, | |
2505 | struct intel_crtc_state *crtc_state, | |
2506 | const struct drm_connector_state *conn_state) | |
2507 | { | |
2508 | int ret; | |
2509 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
2510 | struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; | |
2511 | ||
2512 | if (!conn_state->hdr_output_metadata) | |
2513 | return; | |
2514 | ||
2515 | ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); | |
2516 | ||
2517 | if (ret) { | |
2518 | drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); | |
2519 | return; | |
2520 | } | |
2521 | ||
2522 | crtc_state->infoframes.enable |= | |
2523 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); | |
2524 | } | |
2525 | ||
204474a6 | 2526 | int |
981a63eb JN |
2527 | intel_dp_compute_config(struct intel_encoder *encoder, |
2528 | struct intel_crtc_state *pipe_config, | |
2529 | struct drm_connector_state *conn_state) | |
2530 | { | |
2531 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1326a92c | 2532 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
b7d02c3a VS |
2533 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2534 | struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); | |
981a63eb | 2535 | enum port port = encoder->port; |
981a63eb JN |
2536 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
2537 | struct intel_digital_connector_state *intel_conn_state = | |
2538 | to_intel_digital_connector_state(conn_state); | |
0883ce81 | 2539 | bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, |
53ca2edc | 2540 | DP_DPCD_QUIRK_CONSTANT_N); |
8e9d645c | 2541 | int ret = 0, output_bpp; |
981a63eb JN |
2542 | |
2543 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) | |
2544 | pipe_config->has_pch_encoder = true; | |
2545 | ||
d9facae6 | 2546 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
0c06fa15 | 2547 | |
668b6c17 SS |
2548 | if (lspcon->active) |
2549 | lspcon_ycbcr420_config(&intel_connector->base, pipe_config); | |
8e9d645c | 2550 | else |
4cecc7c0 VS |
2551 | ret = intel_dp_ycbcr420_config(intel_dp, pipe_config, |
2552 | conn_state); | |
8e9d645c GM |
2553 | if (ret) |
2554 | return ret; | |
668b6c17 | 2555 | |
981a63eb | 2556 | pipe_config->has_drrs = false; |
07130981 | 2557 | if (!intel_dp_port_has_audio(dev_priv, port)) |
981a63eb JN |
2558 | pipe_config->has_audio = false; |
2559 | else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2560 | pipe_config->has_audio = intel_dp->has_audio; | |
2561 | else | |
2562 | pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2563 | ||
2564 | if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { | |
d93fa1b4 JN |
2565 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
2566 | adjusted_mode); | |
981a63eb | 2567 | |
b2ae318a | 2568 | if (HAS_GMCH(dev_priv)) |
d7ff281c | 2569 | ret = intel_gmch_panel_fitting(pipe_config, conn_state); |
981a63eb | 2570 | else |
d7ff281c VS |
2571 | ret = intel_pch_panel_fitting(pipe_config, conn_state); |
2572 | if (ret) | |
2573 | return ret; | |
981a63eb JN |
2574 | } |
2575 | ||
e4dd27aa | 2576 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2577 | return -EINVAL; |
e4dd27aa | 2578 | |
b2ae318a | 2579 | if (HAS_GMCH(dev_priv) && |
981a63eb | 2580 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
204474a6 | 2581 | return -EINVAL; |
981a63eb JN |
2582 | |
2583 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
204474a6 | 2584 | return -EINVAL; |
981a63eb | 2585 | |
98c93394 VS |
2586 | if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) |
2587 | return -EINVAL; | |
2588 | ||
204474a6 LP |
2589 | ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); |
2590 | if (ret < 0) | |
2591 | return ret; | |
981a63eb | 2592 | |
37aa52bf VS |
2593 | pipe_config->limited_color_range = |
2594 | intel_dp_limited_color_range(pipe_config, conn_state); | |
55bc60db | 2595 | |
010663a6 JN |
2596 | if (pipe_config->dsc.compression_enable) |
2597 | output_bpp = pipe_config->dsc.compressed_bpp; | |
a4a15777 | 2598 | else |
16668f48 | 2599 | output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); |
aefa95ba VS |
2600 | |
2601 | intel_link_compute_m_n(output_bpp, | |
2602 | pipe_config->lane_count, | |
2603 | adjusted_mode->crtc_clock, | |
2604 | pipe_config->port_clock, | |
2605 | &pipe_config->dp_m_n, | |
ed06efb8 | 2606 | constant_n, pipe_config->fec_enable); |
9d1a455b | 2607 | |
439d7ac0 | 2608 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 2609 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 2610 | pipe_config->has_drrs = true; |
aefa95ba | 2611 | intel_link_compute_m_n(output_bpp, |
981a63eb JN |
2612 | pipe_config->lane_count, |
2613 | intel_connector->panel.downclock_mode->clock, | |
2614 | pipe_config->port_clock, | |
2615 | &pipe_config->dp_m2_n2, | |
ed06efb8 | 2616 | constant_n, pipe_config->fec_enable); |
439d7ac0 PB |
2617 | } |
2618 | ||
4f8036a2 | 2619 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 2620 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 2621 | |
4d90f2d5 | 2622 | intel_psr_compute_config(intel_dp, pipe_config); |
9799c4c3 | 2623 | intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); |
d1eed96d | 2624 | intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); |
4d90f2d5 | 2625 | |
204474a6 | 2626 | return 0; |
a4fc5ed6 KP |
2627 | } |
2628 | ||
901c2daf | 2629 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
830de422 | 2630 | int link_rate, u8 lane_count, |
dfa10480 | 2631 | bool link_mst) |
901c2daf | 2632 | { |
edb2e530 | 2633 | intel_dp->link_trained = false; |
dfa10480 ACO |
2634 | intel_dp->link_rate = link_rate; |
2635 | intel_dp->lane_count = lane_count; | |
2636 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
2637 | } |
2638 | ||
85cb48a1 | 2639 | static void intel_dp_prepare(struct intel_encoder *encoder, |
5f88a9c6 | 2640 | const struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 2641 | { |
2f773477 | 2642 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 2643 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
8f4f2797 | 2644 | enum port port = encoder->port; |
2225f3c6 | 2645 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
1326a92c | 2646 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
a4fc5ed6 | 2647 | |
dfa10480 ACO |
2648 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
2649 | pipe_config->lane_count, | |
2650 | intel_crtc_has_type(pipe_config, | |
2651 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 2652 | |
417e822d | 2653 | /* |
1a2eb460 | 2654 | * There are four kinds of DP registers: |
417e822d KP |
2655 | * |
2656 | * IBX PCH | |
1a2eb460 KP |
2657 | * SNB CPU |
2658 | * IVB CPU | |
417e822d KP |
2659 | * CPT PCH |
2660 | * | |
2661 | * IBX PCH and CPU are the same for almost everything, | |
2662 | * except that the CPU DP PLL is configured in this | |
2663 | * register | |
2664 | * | |
2665 | * CPT PCH is quite different, having many bits moved | |
2666 | * to the TRANS_DP_CTL register instead. That | |
9eae5e27 | 2667 | * configuration happens (oddly) in ilk_pch_enable |
417e822d | 2668 | */ |
9c9e7927 | 2669 | |
417e822d KP |
2670 | /* Preserve the BIOS-computed detected bit. This is |
2671 | * supposed to be read-only. | |
2672 | */ | |
b4e33881 | 2673 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; |
a4fc5ed6 | 2674 | |
417e822d | 2675 | /* Handle DP bits in common between all three register formats */ |
417e822d | 2676 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 2677 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 2678 | |
417e822d | 2679 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 2680 | |
b752e995 | 2681 | if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
2682 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
2683 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
2684 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
2685 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
2686 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
2687 | ||
6aba5b6c | 2688 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
2689 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2690 | ||
59b74c49 | 2691 | intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); |
6e266956 | 2692 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
2693 | u32 trans_dp; |
2694 | ||
39e5fa88 | 2695 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 | 2696 | |
b4e33881 | 2697 | trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); |
e3ef4479 VS |
2698 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
2699 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
2700 | else | |
2701 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
b4e33881 | 2702 | intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); |
39e5fa88 | 2703 | } else { |
c99f53f7 | 2704 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 2705 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
2706 | |
2707 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
2708 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
2709 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
2710 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
2711 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
2712 | ||
6aba5b6c | 2713 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
2714 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2715 | ||
920a14b2 | 2716 | if (IS_CHERRYVIEW(dev_priv)) |
59b74c49 VS |
2717 | intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); |
2718 | else | |
2719 | intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); | |
32f9d658 | 2720 | } |
a4fc5ed6 KP |
2721 | } |
2722 | ||
ffd6749d PZ |
2723 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
2724 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 2725 | |
1a5ef5b7 PZ |
2726 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
2727 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 2728 | |
ffd6749d PZ |
2729 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
2730 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 2731 | |
46bd8383 | 2732 | static void intel_pps_verify_state(struct intel_dp *intel_dp); |
de9c1b6b | 2733 | |
4be73780 | 2734 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
2735 | u32 mask, |
2736 | u32 value) | |
bd943159 | 2737 | { |
de25eb7f | 2738 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
f0f59a00 | 2739 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 2740 | |
e39b999a VS |
2741 | lockdep_assert_held(&dev_priv->pps_mutex); |
2742 | ||
46bd8383 | 2743 | intel_pps_verify_state(intel_dp); |
de9c1b6b | 2744 | |
bf13e81b JN |
2745 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2746 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 2747 | |
bdc6114e WK |
2748 | drm_dbg_kms(&dev_priv->drm, |
2749 | "mask %08x value %08x status %08x control %08x\n", | |
2750 | mask, value, | |
b4e33881 JN |
2751 | intel_de_read(dev_priv, pp_stat_reg), |
2752 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
32ce697c | 2753 | |
4cb3b44d DCS |
2754 | if (intel_de_wait_for_register(dev_priv, pp_stat_reg, |
2755 | mask, value, 5000)) | |
bdc6114e WK |
2756 | drm_err(&dev_priv->drm, |
2757 | "Panel status timeout: status %08x control %08x\n", | |
b4e33881 JN |
2758 | intel_de_read(dev_priv, pp_stat_reg), |
2759 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
54c136d4 | 2760 | |
bdc6114e | 2761 | drm_dbg_kms(&dev_priv->drm, "Wait complete\n"); |
99ea7127 | 2762 | } |
32ce697c | 2763 | |
4be73780 | 2764 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 | 2765 | { |
af67009c JN |
2766 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
2767 | ||
2768 | drm_dbg_kms(&i915->drm, "Wait for panel power on\n"); | |
4be73780 | 2769 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
2770 | } |
2771 | ||
4be73780 | 2772 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 | 2773 | { |
af67009c JN |
2774 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
2775 | ||
2776 | drm_dbg_kms(&i915->drm, "Wait for panel power off time\n"); | |
4be73780 | 2777 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
2778 | } |
2779 | ||
4be73780 | 2780 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 2781 | { |
af67009c | 2782 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
d28d4731 AK |
2783 | ktime_t panel_power_on_time; |
2784 | s64 panel_power_off_duration; | |
2785 | ||
af67009c | 2786 | drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n"); |
dce56b3c | 2787 | |
d28d4731 AK |
2788 | /* take the difference of currrent time and panel power off time |
2789 | * and then make panel wait for t11_t12 if needed. */ | |
2790 | panel_power_on_time = ktime_get_boottime(); | |
2791 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
2792 | ||
dce56b3c PZ |
2793 | /* When we disable the VDD override bit last we have to do the manual |
2794 | * wait. */ | |
d28d4731 AK |
2795 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
2796 | wait_remaining_ms_from_jiffies(jiffies, | |
2797 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 2798 | |
4be73780 | 2799 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
2800 | } |
2801 | ||
4be73780 | 2802 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
2803 | { |
2804 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
2805 | intel_dp->backlight_on_delay); | |
2806 | } | |
2807 | ||
4be73780 | 2808 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
2809 | { |
2810 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
2811 | intel_dp->backlight_off_delay); | |
2812 | } | |
99ea7127 | 2813 | |
832dd3c1 KP |
2814 | /* Read the current pp_control value, unlocking the register if it |
2815 | * is locked | |
2816 | */ | |
2817 | ||
9eae5e27 | 2818 | static u32 ilk_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 2819 | { |
de25eb7f | 2820 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
453c5420 | 2821 | u32 control; |
832dd3c1 | 2822 | |
e39b999a VS |
2823 | lockdep_assert_held(&dev_priv->pps_mutex); |
2824 | ||
b4e33881 | 2825 | control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)); |
eb020ca3 PB |
2826 | if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) && |
2827 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
2828 | control &= ~PANEL_UNLOCK_MASK; |
2829 | control |= PANEL_UNLOCK_REGS; | |
2830 | } | |
832dd3c1 | 2831 | return control; |
bd943159 KP |
2832 | } |
2833 | ||
951468f3 VS |
2834 | /* |
2835 | * Must be paired with edp_panel_vdd_off(). | |
2836 | * Must hold pps_mutex around the whole on/off sequence. | |
2837 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2838 | */ | |
1e0560e0 | 2839 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2840 | { |
de25eb7f | 2841 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4e6e1a54 | 2842 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5d613501 | 2843 | u32 pp; |
f0f59a00 | 2844 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2845 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2846 | |
e39b999a VS |
2847 | lockdep_assert_held(&dev_priv->pps_mutex); |
2848 | ||
1853a9da | 2849 | if (!intel_dp_is_edp(intel_dp)) |
adddaaf4 | 2850 | return false; |
bd943159 | 2851 | |
2c623c11 | 2852 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2853 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2854 | |
4be73780 | 2855 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2856 | return need_to_disable; |
b0665d57 | 2857 | |
337837ac ID |
2858 | intel_display_power_get(dev_priv, |
2859 | intel_aux_power_domain(intel_dig_port)); | |
e9cb81a2 | 2860 | |
bdc6114e WK |
2861 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", |
2862 | intel_dig_port->base.base.base.id, | |
2863 | intel_dig_port->base.base.name); | |
bd943159 | 2864 | |
4be73780 DV |
2865 | if (!edp_have_panel_power(intel_dp)) |
2866 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 2867 | |
9eae5e27 | 2868 | pp = ilk_get_pp_control(intel_dp); |
5d613501 | 2869 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 2870 | |
bf13e81b JN |
2871 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2872 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 | 2873 | |
b4e33881 JN |
2874 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
2875 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
bdc6114e | 2876 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
b4e33881 JN |
2877 | intel_de_read(dev_priv, pp_stat_reg), |
2878 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
ebf33b18 KP |
2879 | /* |
2880 | * If the panel wasn't on, delay before accessing aux channel | |
2881 | */ | |
4be73780 | 2882 | if (!edp_have_panel_power(intel_dp)) { |
bdc6114e WK |
2883 | drm_dbg_kms(&dev_priv->drm, |
2884 | "[ENCODER:%d:%s] panel power wasn't enabled\n", | |
2885 | intel_dig_port->base.base.base.id, | |
2886 | intel_dig_port->base.base.name); | |
f01eca2e | 2887 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2888 | } |
adddaaf4 JN |
2889 | |
2890 | return need_to_disable; | |
2891 | } | |
2892 | ||
951468f3 VS |
2893 | /* |
2894 | * Must be paired with intel_edp_panel_vdd_off() or | |
2895 | * intel_edp_panel_off(). | |
2896 | * Nested calls to these functions are not allowed since | |
2897 | * we drop the lock. Caller must use some higher level | |
2898 | * locking to prevent nested calls from other threads. | |
2899 | */ | |
b80d6c78 | 2900 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2901 | { |
69d93820 | 2902 | intel_wakeref_t wakeref; |
c695b6b6 | 2903 | bool vdd; |
adddaaf4 | 2904 | |
1853a9da | 2905 | if (!intel_dp_is_edp(intel_dp)) |
c695b6b6 VS |
2906 | return; |
2907 | ||
69d93820 CW |
2908 | vdd = false; |
2909 | with_pps_lock(intel_dp, wakeref) | |
2910 | vdd = edp_panel_vdd_on(intel_dp); | |
66a990dd VS |
2911 | I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n", |
2912 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
2913 | dp_to_dig_port(intel_dp)->base.base.name); | |
5d613501 JB |
2914 | } |
2915 | ||
4be73780 | 2916 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2917 | { |
de25eb7f | 2918 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
be2c9196 VS |
2919 | struct intel_digital_port *intel_dig_port = |
2920 | dp_to_dig_port(intel_dp); | |
5d613501 | 2921 | u32 pp; |
f0f59a00 | 2922 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2923 | |
e39b999a | 2924 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2925 | |
eb020ca3 | 2926 | drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd); |
4e6e1a54 | 2927 | |
15e899a0 | 2928 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2929 | return; |
b0665d57 | 2930 | |
bdc6114e WK |
2931 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", |
2932 | intel_dig_port->base.base.base.id, | |
2933 | intel_dig_port->base.base.name); | |
bd943159 | 2934 | |
9eae5e27 | 2935 | pp = ilk_get_pp_control(intel_dp); |
be2c9196 | 2936 | pp &= ~EDP_FORCE_VDD; |
453c5420 | 2937 | |
be2c9196 VS |
2938 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2939 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2940 | |
b4e33881 JN |
2941 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
2942 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
90791a5c | 2943 | |
be2c9196 | 2944 | /* Make sure sequencer is idle before allowing subsequent activity */ |
bdc6114e | 2945 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
b4e33881 JN |
2946 | intel_de_read(dev_priv, pp_stat_reg), |
2947 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
e9cb81a2 | 2948 | |
5a162e22 | 2949 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2950 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2951 | |
0e6e0be4 CW |
2952 | intel_display_power_put_unchecked(dev_priv, |
2953 | intel_aux_power_domain(intel_dig_port)); | |
bd943159 | 2954 | } |
5d613501 | 2955 | |
4be73780 | 2956 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 | 2957 | { |
69d93820 CW |
2958 | struct intel_dp *intel_dp = |
2959 | container_of(to_delayed_work(__work), | |
2960 | struct intel_dp, panel_vdd_work); | |
2961 | intel_wakeref_t wakeref; | |
bd943159 | 2962 | |
69d93820 CW |
2963 | with_pps_lock(intel_dp, wakeref) { |
2964 | if (!intel_dp->want_panel_vdd) | |
2965 | edp_panel_vdd_off_sync(intel_dp); | |
2966 | } | |
bd943159 KP |
2967 | } |
2968 | ||
aba86890 ID |
2969 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2970 | { | |
2971 | unsigned long delay; | |
2972 | ||
2973 | /* | |
2974 | * Queue the timer to fire a long time from now (relative to the power | |
2975 | * down delay) to keep the panel power up across a sequence of | |
2976 | * operations. | |
2977 | */ | |
2978 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2979 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2980 | } | |
2981 | ||
951468f3 VS |
2982 | /* |
2983 | * Must be paired with edp_panel_vdd_on(). | |
2984 | * Must hold pps_mutex around the whole on/off sequence. | |
2985 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2986 | */ | |
4be73780 | 2987 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2988 | { |
de25eb7f | 2989 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e39b999a VS |
2990 | |
2991 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2992 | ||
1853a9da | 2993 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2994 | return; |
5d613501 | 2995 | |
66a990dd VS |
2996 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on", |
2997 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
2998 | dp_to_dig_port(intel_dp)->base.base.name); | |
f2e8b18a | 2999 | |
bd943159 KP |
3000 | intel_dp->want_panel_vdd = false; |
3001 | ||
aba86890 | 3002 | if (sync) |
4be73780 | 3003 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
3004 | else |
3005 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
3006 | } |
3007 | ||
9f0fb5be | 3008 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 3009 | { |
de25eb7f | 3010 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
99ea7127 | 3011 | u32 pp; |
f0f59a00 | 3012 | i915_reg_t pp_ctrl_reg; |
9934c132 | 3013 | |
9f0fb5be VS |
3014 | lockdep_assert_held(&dev_priv->pps_mutex); |
3015 | ||
1853a9da | 3016 | if (!intel_dp_is_edp(intel_dp)) |
bd943159 | 3017 | return; |
99ea7127 | 3018 | |
bdc6114e WK |
3019 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n", |
3020 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
3021 | dp_to_dig_port(intel_dp)->base.base.name); | |
e39b999a | 3022 | |
eb020ca3 PB |
3023 | if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), |
3024 | "[ENCODER:%d:%s] panel power already on\n", | |
3025 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
3026 | dp_to_dig_port(intel_dp)->base.base.name)) | |
9f0fb5be | 3027 | return; |
9934c132 | 3028 | |
4be73780 | 3029 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 3030 | |
bf13e81b | 3031 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
9eae5e27 | 3032 | pp = ilk_get_pp_control(intel_dp); |
cf819eff | 3033 | if (IS_GEN(dev_priv, 5)) { |
05ce1a49 KP |
3034 | /* ILK workaround: disable reset around power sequence */ |
3035 | pp &= ~PANEL_POWER_RESET; | |
b4e33881 JN |
3036 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3037 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
05ce1a49 | 3038 | } |
37c6c9b0 | 3039 | |
5a162e22 | 3040 | pp |= PANEL_POWER_ON; |
cf819eff | 3041 | if (!IS_GEN(dev_priv, 5)) |
99ea7127 KP |
3042 | pp |= PANEL_POWER_RESET; |
3043 | ||
b4e33881 JN |
3044 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3045 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
9934c132 | 3046 | |
4be73780 | 3047 | wait_panel_on(intel_dp); |
dce56b3c | 3048 | intel_dp->last_power_on = jiffies; |
9934c132 | 3049 | |
cf819eff | 3050 | if (IS_GEN(dev_priv, 5)) { |
05ce1a49 | 3051 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
b4e33881 JN |
3052 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3053 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
05ce1a49 | 3054 | } |
9f0fb5be | 3055 | } |
e39b999a | 3056 | |
9f0fb5be VS |
3057 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
3058 | { | |
69d93820 CW |
3059 | intel_wakeref_t wakeref; |
3060 | ||
1853a9da | 3061 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be VS |
3062 | return; |
3063 | ||
69d93820 CW |
3064 | with_pps_lock(intel_dp, wakeref) |
3065 | edp_panel_on(intel_dp); | |
9934c132 JB |
3066 | } |
3067 | ||
9f0fb5be VS |
3068 | |
3069 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 3070 | { |
de25eb7f | 3071 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
337837ac | 3072 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
99ea7127 | 3073 | u32 pp; |
f0f59a00 | 3074 | i915_reg_t pp_ctrl_reg; |
9934c132 | 3075 | |
9f0fb5be VS |
3076 | lockdep_assert_held(&dev_priv->pps_mutex); |
3077 | ||
1853a9da | 3078 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 3079 | return; |
37c6c9b0 | 3080 | |
bdc6114e WK |
3081 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n", |
3082 | dig_port->base.base.base.id, dig_port->base.base.name); | |
37c6c9b0 | 3083 | |
eb020ca3 PB |
3084 | drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd, |
3085 | "Need [ENCODER:%d:%s] VDD to turn off panel\n", | |
3086 | dig_port->base.base.base.id, dig_port->base.base.name); | |
24f3e092 | 3087 | |
9eae5e27 | 3088 | pp = ilk_get_pp_control(intel_dp); |
35a38556 DV |
3089 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
3090 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 3091 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 3092 | EDP_BLC_ENABLE); |
453c5420 | 3093 | |
bf13e81b | 3094 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 3095 | |
849e39f5 PZ |
3096 | intel_dp->want_panel_vdd = false; |
3097 | ||
b4e33881 JN |
3098 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3099 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
9934c132 | 3100 | |
4be73780 | 3101 | wait_panel_off(intel_dp); |
d7ba25bd | 3102 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
849e39f5 PZ |
3103 | |
3104 | /* We got a reference when we enabled the VDD. */ | |
0e6e0be4 | 3105 | intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port)); |
9f0fb5be | 3106 | } |
e39b999a | 3107 | |
9f0fb5be VS |
3108 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
3109 | { | |
69d93820 CW |
3110 | intel_wakeref_t wakeref; |
3111 | ||
1853a9da | 3112 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be | 3113 | return; |
e39b999a | 3114 | |
69d93820 CW |
3115 | with_pps_lock(intel_dp, wakeref) |
3116 | edp_panel_off(intel_dp); | |
9934c132 JB |
3117 | } |
3118 | ||
1250d107 JN |
3119 | /* Enable backlight in the panel power control. */ |
3120 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 3121 | { |
de25eb7f | 3122 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 3123 | intel_wakeref_t wakeref; |
32f9d658 | 3124 | |
01cb9ea6 JB |
3125 | /* |
3126 | * If we enable the backlight right away following a panel power | |
3127 | * on, we may see slight flicker as the panel syncs with the eDP | |
3128 | * link. So delay a bit to make sure the image is solid before | |
3129 | * allowing it to appear. | |
3130 | */ | |
4be73780 | 3131 | wait_backlight_on(intel_dp); |
e39b999a | 3132 | |
69d93820 CW |
3133 | with_pps_lock(intel_dp, wakeref) { |
3134 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
3135 | u32 pp; | |
453c5420 | 3136 | |
9eae5e27 | 3137 | pp = ilk_get_pp_control(intel_dp); |
69d93820 | 3138 | pp |= EDP_BLC_ENABLE; |
453c5420 | 3139 | |
b4e33881 JN |
3140 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3141 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
69d93820 | 3142 | } |
32f9d658 ZW |
3143 | } |
3144 | ||
1250d107 | 3145 | /* Enable backlight PWM and backlight PP control. */ |
b037d58f ML |
3146 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
3147 | const struct drm_connector_state *conn_state) | |
1250d107 | 3148 | { |
b7d02c3a | 3149 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); |
af67009c | 3150 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b037d58f | 3151 | |
1853a9da | 3152 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
3153 | return; |
3154 | ||
af67009c | 3155 | drm_dbg_kms(&i915->drm, "\n"); |
1250d107 | 3156 | |
b037d58f | 3157 | intel_panel_enable_backlight(crtc_state, conn_state); |
1250d107 JN |
3158 | _intel_edp_backlight_on(intel_dp); |
3159 | } | |
3160 | ||
3161 | /* Disable backlight in the panel power control. */ | |
3162 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 3163 | { |
de25eb7f | 3164 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 3165 | intel_wakeref_t wakeref; |
32f9d658 | 3166 | |
1853a9da | 3167 | if (!intel_dp_is_edp(intel_dp)) |
f01eca2e KP |
3168 | return; |
3169 | ||
69d93820 CW |
3170 | with_pps_lock(intel_dp, wakeref) { |
3171 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
3172 | u32 pp; | |
e39b999a | 3173 | |
9eae5e27 | 3174 | pp = ilk_get_pp_control(intel_dp); |
69d93820 | 3175 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 3176 | |
b4e33881 JN |
3177 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3178 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
69d93820 | 3179 | } |
e39b999a VS |
3180 | |
3181 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 3182 | edp_wait_backlight_off(intel_dp); |
1250d107 | 3183 | } |
f7d2323c | 3184 | |
1250d107 | 3185 | /* Disable backlight PP control and backlight PWM. */ |
b037d58f | 3186 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
1250d107 | 3187 | { |
b7d02c3a | 3188 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); |
af67009c | 3189 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b037d58f | 3190 | |
1853a9da | 3191 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
3192 | return; |
3193 | ||
af67009c | 3194 | drm_dbg_kms(&i915->drm, "\n"); |
f7d2323c | 3195 | |
1250d107 | 3196 | _intel_edp_backlight_off(intel_dp); |
b037d58f | 3197 | intel_panel_disable_backlight(old_conn_state); |
32f9d658 | 3198 | } |
a4fc5ed6 | 3199 | |
73580fb7 JN |
3200 | /* |
3201 | * Hook for controlling the panel power control backlight through the bl_power | |
3202 | * sysfs attribute. Take care to handle multiple calls. | |
3203 | */ | |
3204 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
3205 | bool enable) | |
3206 | { | |
af67009c | 3207 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
43a6d19c | 3208 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
69d93820 | 3209 | intel_wakeref_t wakeref; |
e39b999a VS |
3210 | bool is_enabled; |
3211 | ||
69d93820 CW |
3212 | is_enabled = false; |
3213 | with_pps_lock(intel_dp, wakeref) | |
9eae5e27 | 3214 | is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
73580fb7 JN |
3215 | if (is_enabled == enable) |
3216 | return; | |
3217 | ||
af67009c JN |
3218 | drm_dbg_kms(&i915->drm, "panel power control backlight %s\n", |
3219 | enable ? "enable" : "disable"); | |
73580fb7 JN |
3220 | |
3221 | if (enable) | |
3222 | _intel_edp_backlight_on(intel_dp); | |
3223 | else | |
3224 | _intel_edp_backlight_off(intel_dp); | |
3225 | } | |
3226 | ||
64e1077a VS |
3227 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
3228 | { | |
3229 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
3230 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
b4e33881 | 3231 | bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; |
64e1077a VS |
3232 | |
3233 | I915_STATE_WARN(cur_state != state, | |
66a990dd VS |
3234 | "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", |
3235 | dig_port->base.base.base.id, dig_port->base.base.name, | |
87ad3212 | 3236 | onoff(state), onoff(cur_state)); |
64e1077a VS |
3237 | } |
3238 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
3239 | ||
3240 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
3241 | { | |
b4e33881 | 3242 | bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; |
64e1077a VS |
3243 | |
3244 | I915_STATE_WARN(cur_state != state, | |
3245 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 3246 | onoff(state), onoff(cur_state)); |
64e1077a VS |
3247 | } |
3248 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
3249 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
3250 | ||
9eae5e27 LDM |
3251 | static void ilk_edp_pll_on(struct intel_dp *intel_dp, |
3252 | const struct intel_crtc_state *pipe_config) | |
d240f20f | 3253 | { |
2225f3c6 | 3254 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
64e1077a | 3255 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 3256 | |
5c34ba27 | 3257 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); |
64e1077a VS |
3258 | assert_dp_port_disabled(intel_dp); |
3259 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 3260 | |
bdc6114e WK |
3261 | drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", |
3262 | pipe_config->port_clock); | |
abfce949 VS |
3263 | |
3264 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
3265 | ||
85cb48a1 | 3266 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
3267 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
3268 | else | |
3269 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
3270 | ||
b4e33881 JN |
3271 | intel_de_write(dev_priv, DP_A, intel_dp->DP); |
3272 | intel_de_posting_read(dev_priv, DP_A); | |
abfce949 VS |
3273 | udelay(500); |
3274 | ||
6b23f3e8 VS |
3275 | /* |
3276 | * [DevILK] Work around required when enabling DP PLL | |
3277 | * while a pipe is enabled going to FDI: | |
3278 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
3279 | * 2. Program DP PLL enable | |
3280 | */ | |
cf819eff | 3281 | if (IS_GEN(dev_priv, 5)) |
0f0f74bc | 3282 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 3283 | |
0767935e | 3284 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 3285 | |
b4e33881 JN |
3286 | intel_de_write(dev_priv, DP_A, intel_dp->DP); |
3287 | intel_de_posting_read(dev_priv, DP_A); | |
298b0b39 | 3288 | udelay(200); |
d240f20f JB |
3289 | } |
3290 | ||
9eae5e27 LDM |
3291 | static void ilk_edp_pll_off(struct intel_dp *intel_dp, |
3292 | const struct intel_crtc_state *old_crtc_state) | |
d240f20f | 3293 | { |
2225f3c6 | 3294 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
64e1077a | 3295 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 3296 | |
5c34ba27 | 3297 | assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); |
64e1077a VS |
3298 | assert_dp_port_disabled(intel_dp); |
3299 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 3300 | |
bdc6114e | 3301 | drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); |
abfce949 | 3302 | |
6fec7662 | 3303 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 3304 | |
b4e33881 JN |
3305 | intel_de_write(dev_priv, DP_A, intel_dp->DP); |
3306 | intel_de_posting_read(dev_priv, DP_A); | |
d240f20f JB |
3307 | udelay(200); |
3308 | } | |
3309 | ||
857c416e VS |
3310 | static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) |
3311 | { | |
3312 | /* | |
3313 | * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus | |
3314 | * be capable of signalling downstream hpd with a long pulse. | |
3315 | * Whether or not that means D3 is safe to use is not clear, | |
3316 | * but let's assume so until proven otherwise. | |
3317 | * | |
3318 | * FIXME should really check all downstream ports... | |
3319 | */ | |
3320 | return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && | |
b4c32073 | 3321 | drm_dp_is_branch(intel_dp->dpcd) && |
857c416e VS |
3322 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; |
3323 | } | |
3324 | ||
2279298d GS |
3325 | void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, |
3326 | const struct intel_crtc_state *crtc_state, | |
3327 | bool enable) | |
3328 | { | |
af67009c | 3329 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
2279298d GS |
3330 | int ret; |
3331 | ||
010663a6 | 3332 | if (!crtc_state->dsc.compression_enable) |
2279298d GS |
3333 | return; |
3334 | ||
3335 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, | |
3336 | enable ? DP_DECOMPRESSION_EN : 0); | |
3337 | if (ret < 0) | |
af67009c JN |
3338 | drm_dbg_kms(&i915->drm, |
3339 | "Failed to %s sink decompression state\n", | |
3340 | enable ? "enable" : "disable"); | |
2279298d GS |
3341 | } |
3342 | ||
c7ad3810 | 3343 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 3344 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 | 3345 | { |
af67009c | 3346 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
c7ad3810 JB |
3347 | int ret, i; |
3348 | ||
3349 | /* Should have a valid DPCD by this point */ | |
3350 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
3351 | return; | |
3352 | ||
3353 | if (mode != DRM_MODE_DPMS_ON) { | |
857c416e VS |
3354 | if (downstream_hpd_needs_d0(intel_dp)) |
3355 | return; | |
3356 | ||
9d1a1031 JN |
3357 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
3358 | DP_SET_POWER_D3); | |
c7ad3810 | 3359 | } else { |
357c0ae9 ID |
3360 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
3361 | ||
c7ad3810 JB |
3362 | /* |
3363 | * When turning on, we need to retry for 1ms to give the sink | |
3364 | * time to wake up. | |
3365 | */ | |
3366 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
3367 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
3368 | DP_SET_POWER_D0); | |
c7ad3810 JB |
3369 | if (ret == 1) |
3370 | break; | |
3371 | msleep(1); | |
3372 | } | |
357c0ae9 ID |
3373 | |
3374 | if (ret == 1 && lspcon->active) | |
3375 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 3376 | } |
f9cac721 JN |
3377 | |
3378 | if (ret != 1) | |
af67009c JN |
3379 | drm_dbg_kms(&i915->drm, "failed to %s sink power state\n", |
3380 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
3381 | } |
3382 | ||
59b74c49 VS |
3383 | static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, |
3384 | enum port port, enum pipe *pipe) | |
3385 | { | |
3386 | enum pipe p; | |
3387 | ||
3388 | for_each_pipe(dev_priv, p) { | |
b4e33881 | 3389 | u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); |
59b74c49 VS |
3390 | |
3391 | if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { | |
3392 | *pipe = p; | |
3393 | return true; | |
3394 | } | |
3395 | } | |
3396 | ||
bdc6114e WK |
3397 | drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", |
3398 | port_name(port)); | |
59b74c49 VS |
3399 | |
3400 | /* must initialize pipe to something for the asserts */ | |
3401 | *pipe = PIPE_A; | |
3402 | ||
3403 | return false; | |
3404 | } | |
3405 | ||
3406 | bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, | |
3407 | i915_reg_t dp_reg, enum port port, | |
3408 | enum pipe *pipe) | |
3409 | { | |
3410 | bool ret; | |
3411 | u32 val; | |
3412 | ||
b4e33881 | 3413 | val = intel_de_read(dev_priv, dp_reg); |
59b74c49 VS |
3414 | |
3415 | ret = val & DP_PORT_EN; | |
3416 | ||
3417 | /* asserts want to know the pipe even if the port is disabled */ | |
3418 | if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) | |
3419 | *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; | |
3420 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) | |
3421 | ret &= cpt_dp_port_selected(dev_priv, port, pipe); | |
3422 | else if (IS_CHERRYVIEW(dev_priv)) | |
3423 | *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; | |
3424 | else | |
3425 | *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; | |
3426 | ||
3427 | return ret; | |
3428 | } | |
3429 | ||
19d8fe15 DV |
3430 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
3431 | enum pipe *pipe) | |
d240f20f | 3432 | { |
2f773477 | 3433 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3434 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
0e6e0be4 | 3435 | intel_wakeref_t wakeref; |
6fa9a5ec | 3436 | bool ret; |
6d129bea | 3437 | |
0e6e0be4 CW |
3438 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
3439 | encoder->power_domain); | |
3440 | if (!wakeref) | |
6d129bea ID |
3441 | return false; |
3442 | ||
59b74c49 VS |
3443 | ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, |
3444 | encoder->port, pipe); | |
6fa9a5ec | 3445 | |
0e6e0be4 | 3446 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
6fa9a5ec ID |
3447 | |
3448 | return ret; | |
19d8fe15 | 3449 | } |
d240f20f | 3450 | |
045ac3b5 | 3451 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 3452 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 3453 | { |
2f773477 | 3454 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3455 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
045ac3b5 | 3456 | u32 tmp, flags = 0; |
8f4f2797 | 3457 | enum port port = encoder->port; |
2225f3c6 | 3458 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
045ac3b5 | 3459 | |
e1214b95 VS |
3460 | if (encoder->type == INTEL_OUTPUT_EDP) |
3461 | pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); | |
3462 | else | |
3463 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); | |
045ac3b5 | 3464 | |
b4e33881 | 3465 | tmp = intel_de_read(dev_priv, intel_dp->output_reg); |
9fcb1704 JN |
3466 | |
3467 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 3468 | |
6e266956 | 3469 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b4e33881 JN |
3470 | u32 trans_dp = intel_de_read(dev_priv, |
3471 | TRANS_DP_CTL(crtc->pipe)); | |
b81e34c2 VS |
3472 | |
3473 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
3474 | flags |= DRM_MODE_FLAG_PHSYNC; |
3475 | else | |
3476 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 3477 | |
b81e34c2 | 3478 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
3479 | flags |= DRM_MODE_FLAG_PVSYNC; |
3480 | else | |
3481 | flags |= DRM_MODE_FLAG_NVSYNC; | |
3482 | } else { | |
39e5fa88 | 3483 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
3484 | flags |= DRM_MODE_FLAG_PHSYNC; |
3485 | else | |
3486 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 3487 | |
39e5fa88 | 3488 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
3489 | flags |= DRM_MODE_FLAG_PVSYNC; |
3490 | else | |
3491 | flags |= DRM_MODE_FLAG_NVSYNC; | |
3492 | } | |
045ac3b5 | 3493 | |
1326a92c | 3494 | pipe_config->hw.adjusted_mode.flags |= flags; |
f1f644dc | 3495 | |
c99f53f7 | 3496 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
3497 | pipe_config->limited_color_range = true; |
3498 | ||
90a6b7b0 VS |
3499 | pipe_config->lane_count = |
3500 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
3501 | ||
eb14cb74 VS |
3502 | intel_dp_get_m_n(crtc, pipe_config); |
3503 | ||
18442d08 | 3504 | if (port == PORT_A) { |
b4e33881 | 3505 | if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
3506 | pipe_config->port_clock = 162000; |
3507 | else | |
3508 | pipe_config->port_clock = 270000; | |
3509 | } | |
18442d08 | 3510 | |
1326a92c | 3511 | pipe_config->hw.adjusted_mode.crtc_clock = |
e3b247da VS |
3512 | intel_dotclock_calculate(pipe_config->port_clock, |
3513 | &pipe_config->dp_m_n); | |
7f16e5c1 | 3514 | |
1853a9da | 3515 | if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
6aa23e65 | 3516 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
c6cd2ee2 JN |
3517 | /* |
3518 | * This is a big fat ugly hack. | |
3519 | * | |
3520 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
3521 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
3522 | * unknown we fail to light up. Yet the same BIOS boots up with | |
3523 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
3524 | * max, not what it tells us to use. | |
3525 | * | |
3526 | * Note: This will still be broken if the eDP panel is not lit | |
3527 | * up by the BIOS, and thus we can't get the mode at module | |
3528 | * load. | |
3529 | */ | |
bdc6114e WK |
3530 | drm_dbg_kms(&dev_priv->drm, |
3531 | "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
3532 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); | |
6aa23e65 | 3533 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
c6cd2ee2 | 3534 | } |
045ac3b5 JB |
3535 | } |
3536 | ||
ede9771d VS |
3537 | static void intel_disable_dp(struct intel_atomic_state *state, |
3538 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3539 | const struct intel_crtc_state *old_crtc_state, |
3540 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 3541 | { |
b7d02c3a | 3542 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
495a5bb8 | 3543 | |
edb2e530 VS |
3544 | intel_dp->link_trained = false; |
3545 | ||
85cb48a1 | 3546 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
3547 | intel_audio_codec_disable(encoder, |
3548 | old_crtc_state, old_conn_state); | |
6cb49835 DV |
3549 | |
3550 | /* Make sure the panel is off before trying to change the mode. But also | |
3551 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 3552 | intel_edp_panel_vdd_on(intel_dp); |
b037d58f | 3553 | intel_edp_backlight_off(old_conn_state); |
fdbc3b1f | 3554 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 3555 | intel_edp_panel_off(intel_dp); |
1a8ff607 VS |
3556 | } |
3557 | ||
ede9771d VS |
3558 | static void g4x_disable_dp(struct intel_atomic_state *state, |
3559 | struct intel_encoder *encoder, | |
1a8ff607 VS |
3560 | const struct intel_crtc_state *old_crtc_state, |
3561 | const struct drm_connector_state *old_conn_state) | |
1a8ff607 | 3562 | { |
ede9771d | 3563 | intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); |
1a8ff607 VS |
3564 | } |
3565 | ||
ede9771d VS |
3566 | static void vlv_disable_dp(struct intel_atomic_state *state, |
3567 | struct intel_encoder *encoder, | |
1a8ff607 VS |
3568 | const struct intel_crtc_state *old_crtc_state, |
3569 | const struct drm_connector_state *old_conn_state) | |
3570 | { | |
ede9771d | 3571 | intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); |
d240f20f JB |
3572 | } |
3573 | ||
ede9771d VS |
3574 | static void g4x_post_disable_dp(struct intel_atomic_state *state, |
3575 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3576 | const struct intel_crtc_state *old_crtc_state, |
3577 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 3578 | { |
b7d02c3a | 3579 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
adc10304 | 3580 | enum port port = encoder->port; |
2bd2ad64 | 3581 | |
51a9f6df VS |
3582 | /* |
3583 | * Bspec does not list a specific disable sequence for g4x DP. | |
3584 | * Follow the ilk+ sequence (disable pipe before the port) for | |
3585 | * g4x DP as it does not suffer from underruns like the normal | |
3586 | * g4x modeset sequence (disable pipe after the port). | |
3587 | */ | |
adc10304 | 3588 | intel_dp_link_down(encoder, old_crtc_state); |
abfce949 VS |
3589 | |
3590 | /* Only ilk+ has port A */ | |
08aff3fe | 3591 | if (port == PORT_A) |
9eae5e27 | 3592 | ilk_edp_pll_off(intel_dp, old_crtc_state); |
49277c31 VS |
3593 | } |
3594 | ||
ede9771d VS |
3595 | static void vlv_post_disable_dp(struct intel_atomic_state *state, |
3596 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3597 | const struct intel_crtc_state *old_crtc_state, |
3598 | const struct drm_connector_state *old_conn_state) | |
49277c31 | 3599 | { |
adc10304 | 3600 | intel_dp_link_down(encoder, old_crtc_state); |
2bd2ad64 DV |
3601 | } |
3602 | ||
ede9771d VS |
3603 | static void chv_post_disable_dp(struct intel_atomic_state *state, |
3604 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3605 | const struct intel_crtc_state *old_crtc_state, |
3606 | const struct drm_connector_state *old_conn_state) | |
a8f327fb | 3607 | { |
adc10304 | 3608 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
97fd4d5c | 3609 | |
adc10304 | 3610 | intel_dp_link_down(encoder, old_crtc_state); |
a8f327fb | 3611 | |
221c7862 | 3612 | vlv_dpio_get(dev_priv); |
a8f327fb VS |
3613 | |
3614 | /* Assert data lane reset */ | |
2e1029c6 | 3615 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 3616 | |
221c7862 | 3617 | vlv_dpio_put(dev_priv); |
580d3811 VS |
3618 | } |
3619 | ||
7b13b58a VS |
3620 | static void |
3621 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
830de422 JN |
3622 | u32 *DP, |
3623 | u8 dp_train_pat) | |
7b13b58a | 3624 | { |
de25eb7f | 3625 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7b13b58a | 3626 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 3627 | enum port port = intel_dig_port->base.port; |
830de422 | 3628 | u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); |
7b13b58a | 3629 | |
2edd5327 | 3630 | if (dp_train_pat & train_pat_mask) |
bdc6114e WK |
3631 | drm_dbg_kms(&dev_priv->drm, |
3632 | "Using DP training pattern TPS%d\n", | |
3633 | dp_train_pat & train_pat_mask); | |
8b0878a0 | 3634 | |
4f8036a2 | 3635 | if (HAS_DDI(dev_priv)) { |
b4e33881 | 3636 | u32 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); |
7b13b58a VS |
3637 | |
3638 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
3639 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
3640 | else | |
3641 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
3642 | ||
3643 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2edd5327 | 3644 | switch (dp_train_pat & train_pat_mask) { |
7b13b58a VS |
3645 | case DP_TRAINING_PATTERN_DISABLE: |
3646 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
3647 | ||
3648 | break; | |
3649 | case DP_TRAINING_PATTERN_1: | |
3650 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
3651 | break; | |
3652 | case DP_TRAINING_PATTERN_2: | |
3653 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
3654 | break; | |
3655 | case DP_TRAINING_PATTERN_3: | |
3656 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
3657 | break; | |
2edd5327 MN |
3658 | case DP_TRAINING_PATTERN_4: |
3659 | temp |= DP_TP_CTL_LINK_TRAIN_PAT4; | |
3660 | break; | |
7b13b58a | 3661 | } |
b4e33881 | 3662 | intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); |
7b13b58a | 3663 | |
b752e995 | 3664 | } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || |
6e266956 | 3665 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
3666 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
3667 | ||
3668 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
3669 | case DP_TRAINING_PATTERN_DISABLE: | |
3670 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
3671 | break; | |
3672 | case DP_TRAINING_PATTERN_1: | |
3673 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
3674 | break; | |
3675 | case DP_TRAINING_PATTERN_2: | |
3676 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
3677 | break; | |
3678 | case DP_TRAINING_PATTERN_3: | |
bdc6114e WK |
3679 | drm_dbg_kms(&dev_priv->drm, |
3680 | "TPS3 not supported, using TPS2 instead\n"); | |
7b13b58a VS |
3681 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
3682 | break; | |
3683 | } | |
3684 | ||
3685 | } else { | |
3b358cda | 3686 | *DP &= ~DP_LINK_TRAIN_MASK; |
7b13b58a VS |
3687 | |
3688 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
3689 | case DP_TRAINING_PATTERN_DISABLE: | |
3690 | *DP |= DP_LINK_TRAIN_OFF; | |
3691 | break; | |
3692 | case DP_TRAINING_PATTERN_1: | |
3693 | *DP |= DP_LINK_TRAIN_PAT_1; | |
3694 | break; | |
3695 | case DP_TRAINING_PATTERN_2: | |
3696 | *DP |= DP_LINK_TRAIN_PAT_2; | |
3697 | break; | |
3698 | case DP_TRAINING_PATTERN_3: | |
bdc6114e WK |
3699 | drm_dbg_kms(&dev_priv->drm, |
3700 | "TPS3 not supported, using TPS2 instead\n"); | |
3b358cda | 3701 | *DP |= DP_LINK_TRAIN_PAT_2; |
7b13b58a VS |
3702 | break; |
3703 | } | |
3704 | } | |
3705 | } | |
3706 | ||
85cb48a1 | 3707 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
5f88a9c6 | 3708 | const struct intel_crtc_state *old_crtc_state) |
7b13b58a | 3709 | { |
de25eb7f | 3710 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7b13b58a | 3711 | |
7b13b58a | 3712 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 3713 | |
8b0878a0 | 3714 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
3715 | |
3716 | /* | |
3717 | * Magic for VLV/CHV. We _must_ first set up the register | |
3718 | * without actually enabling the port, and then do another | |
3719 | * write to enable the port. Otherwise link training will | |
3720 | * fail when the power sequencer is freshly used for this port. | |
3721 | */ | |
3722 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 3723 | if (old_crtc_state->has_audio) |
6fec7662 | 3724 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 | 3725 | |
b4e33881 JN |
3726 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
3727 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
580d3811 VS |
3728 | } |
3729 | ||
ede9771d VS |
3730 | static void intel_enable_dp(struct intel_atomic_state *state, |
3731 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3732 | const struct intel_crtc_state *pipe_config, |
3733 | const struct drm_connector_state *conn_state) | |
d240f20f | 3734 | { |
2f773477 | 3735 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3736 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 3737 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
b4e33881 | 3738 | u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); |
d6fbdd15 | 3739 | enum pipe pipe = crtc->pipe; |
69d93820 | 3740 | intel_wakeref_t wakeref; |
5d613501 | 3741 | |
eb020ca3 | 3742 | if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) |
0c33d8d7 | 3743 | return; |
5d613501 | 3744 | |
69d93820 CW |
3745 | with_pps_lock(intel_dp, wakeref) { |
3746 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
3747 | vlv_init_panel_power_sequencer(encoder, pipe_config); | |
093e3f13 | 3748 | |
69d93820 | 3749 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 | 3750 | |
69d93820 CW |
3751 | edp_panel_vdd_on(intel_dp); |
3752 | edp_panel_on(intel_dp); | |
3753 | edp_panel_vdd_off(intel_dp, true); | |
3754 | } | |
093e3f13 | 3755 | |
920a14b2 | 3756 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
3757 | unsigned int lane_mask = 0x0; |
3758 | ||
920a14b2 | 3759 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 3760 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 3761 | |
9b6de0a1 VS |
3762 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
3763 | lane_mask); | |
e0fce78f | 3764 | } |
61234fa5 | 3765 | |
f01eca2e | 3766 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 3767 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 3768 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 3769 | |
85cb48a1 | 3770 | if (pipe_config->has_audio) { |
bdc6114e WK |
3771 | drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n", |
3772 | pipe_name(pipe)); | |
bbf35e9d | 3773 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 3774 | } |
ab1f90f9 | 3775 | } |
89b667f8 | 3776 | |
ede9771d VS |
3777 | static void g4x_enable_dp(struct intel_atomic_state *state, |
3778 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3779 | const struct intel_crtc_state *pipe_config, |
3780 | const struct drm_connector_state *conn_state) | |
ecff4f3b | 3781 | { |
ede9771d | 3782 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
b037d58f | 3783 | intel_edp_backlight_on(pipe_config, conn_state); |
ab1f90f9 | 3784 | } |
89b667f8 | 3785 | |
ede9771d VS |
3786 | static void vlv_enable_dp(struct intel_atomic_state *state, |
3787 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3788 | const struct intel_crtc_state *pipe_config, |
3789 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 3790 | { |
b037d58f | 3791 | intel_edp_backlight_on(pipe_config, conn_state); |
d240f20f JB |
3792 | } |
3793 | ||
ede9771d VS |
3794 | static void g4x_pre_enable_dp(struct intel_atomic_state *state, |
3795 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3796 | const struct intel_crtc_state *pipe_config, |
3797 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 3798 | { |
b7d02c3a | 3799 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
8f4f2797 | 3800 | enum port port = encoder->port; |
ab1f90f9 | 3801 | |
85cb48a1 | 3802 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3803 | |
d41f1efb | 3804 | /* Only ilk+ has port A */ |
abfce949 | 3805 | if (port == PORT_A) |
9eae5e27 | 3806 | ilk_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
3807 | } |
3808 | ||
83b84597 VS |
3809 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
3810 | { | |
3811 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 3812 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 3813 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 3814 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 3815 | |
eb020ca3 | 3816 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); |
9f2bdb00 | 3817 | |
eb020ca3 | 3818 | if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) |
d158694f VS |
3819 | return; |
3820 | ||
83b84597 VS |
3821 | edp_panel_vdd_off_sync(intel_dp); |
3822 | ||
3823 | /* | |
e7f2af78 | 3824 | * VLV seems to get confused when multiple power sequencers |
83b84597 VS |
3825 | * have the same port selected (even if only one has power/vdd |
3826 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
3827 | * CHV on the other hand doesn't seem to mind having the same port | |
e7f2af78 | 3828 | * selected in multiple power sequencers, but let's clear the |
83b84597 VS |
3829 | * port select always when logically disconnecting a power sequencer |
3830 | * from a port. | |
3831 | */ | |
bdc6114e WK |
3832 | drm_dbg_kms(&dev_priv->drm, |
3833 | "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", | |
3834 | pipe_name(pipe), intel_dig_port->base.base.base.id, | |
3835 | intel_dig_port->base.base.name); | |
b4e33881 JN |
3836 | intel_de_write(dev_priv, pp_on_reg, 0); |
3837 | intel_de_posting_read(dev_priv, pp_on_reg); | |
83b84597 VS |
3838 | |
3839 | intel_dp->pps_pipe = INVALID_PIPE; | |
3840 | } | |
3841 | ||
46bd8383 | 3842 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a4a5d2f8 VS |
3843 | enum pipe pipe) |
3844 | { | |
a4a5d2f8 VS |
3845 | struct intel_encoder *encoder; |
3846 | ||
3847 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3848 | ||
14aa521c | 3849 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 3850 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4a5d2f8 | 3851 | |
eb020ca3 PB |
3852 | drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe, |
3853 | "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", | |
3854 | pipe_name(pipe), encoder->base.base.id, | |
3855 | encoder->base.name); | |
9f2bdb00 | 3856 | |
a4a5d2f8 VS |
3857 | if (intel_dp->pps_pipe != pipe) |
3858 | continue; | |
3859 | ||
bdc6114e WK |
3860 | drm_dbg_kms(&dev_priv->drm, |
3861 | "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", | |
3862 | pipe_name(pipe), encoder->base.base.id, | |
3863 | encoder->base.name); | |
a4a5d2f8 VS |
3864 | |
3865 | /* make sure vdd is off before we steal it */ | |
83b84597 | 3866 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
3867 | } |
3868 | } | |
3869 | ||
adc10304 VS |
3870 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
3871 | const struct intel_crtc_state *crtc_state) | |
a4a5d2f8 | 3872 | { |
46bd8383 | 3873 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3874 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 3875 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
a4a5d2f8 VS |
3876 | |
3877 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3878 | ||
eb020ca3 | 3879 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 3880 | |
9f2bdb00 VS |
3881 | if (intel_dp->pps_pipe != INVALID_PIPE && |
3882 | intel_dp->pps_pipe != crtc->pipe) { | |
3883 | /* | |
3884 | * If another power sequencer was being used on this | |
3885 | * port previously make sure to turn off vdd there while | |
3886 | * we still have control of it. | |
3887 | */ | |
83b84597 | 3888 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 3889 | } |
a4a5d2f8 VS |
3890 | |
3891 | /* | |
3892 | * We may be stealing the power | |
3893 | * sequencer from another port. | |
3894 | */ | |
46bd8383 | 3895 | vlv_steal_power_sequencer(dev_priv, crtc->pipe); |
a4a5d2f8 | 3896 | |
9f2bdb00 VS |
3897 | intel_dp->active_pipe = crtc->pipe; |
3898 | ||
1853a9da | 3899 | if (!intel_dp_is_edp(intel_dp)) |
9f2bdb00 VS |
3900 | return; |
3901 | ||
a4a5d2f8 VS |
3902 | /* now it's all ours */ |
3903 | intel_dp->pps_pipe = crtc->pipe; | |
3904 | ||
bdc6114e WK |
3905 | drm_dbg_kms(&dev_priv->drm, |
3906 | "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", | |
3907 | pipe_name(intel_dp->pps_pipe), encoder->base.base.id, | |
3908 | encoder->base.name); | |
a4a5d2f8 VS |
3909 | |
3910 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
3911 | intel_dp_init_panel_power_sequencer(intel_dp); |
3912 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 VS |
3913 | } |
3914 | ||
ede9771d VS |
3915 | static void vlv_pre_enable_dp(struct intel_atomic_state *state, |
3916 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3917 | const struct intel_crtc_state *pipe_config, |
3918 | const struct drm_connector_state *conn_state) | |
a4fc5ed6 | 3919 | { |
2e1029c6 | 3920 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
ab1f90f9 | 3921 | |
ede9771d | 3922 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
89b667f8 JB |
3923 | } |
3924 | ||
ede9771d VS |
3925 | static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, |
3926 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3927 | const struct intel_crtc_state *pipe_config, |
3928 | const struct drm_connector_state *conn_state) | |
89b667f8 | 3929 | { |
85cb48a1 | 3930 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3931 | |
2e1029c6 | 3932 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
a4fc5ed6 KP |
3933 | } |
3934 | ||
ede9771d VS |
3935 | static void chv_pre_enable_dp(struct intel_atomic_state *state, |
3936 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3937 | const struct intel_crtc_state *pipe_config, |
3938 | const struct drm_connector_state *conn_state) | |
e4a1d846 | 3939 | { |
2e1029c6 | 3940 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
e4a1d846 | 3941 | |
ede9771d | 3942 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
b0b33846 VS |
3943 | |
3944 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 3945 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
3946 | } |
3947 | ||
ede9771d VS |
3948 | static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, |
3949 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3950 | const struct intel_crtc_state *pipe_config, |
3951 | const struct drm_connector_state *conn_state) | |
9197c88b | 3952 | { |
85cb48a1 | 3953 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 3954 | |
2e1029c6 | 3955 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
3956 | } |
3957 | ||
ede9771d VS |
3958 | static void chv_dp_post_pll_disable(struct intel_atomic_state *state, |
3959 | struct intel_encoder *encoder, | |
2e1029c6 VS |
3960 | const struct intel_crtc_state *old_crtc_state, |
3961 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 3962 | { |
2e1029c6 | 3963 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
3964 | } |
3965 | ||
a4fc5ed6 KP |
3966 | /* |
3967 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3968 | * link status information | |
3969 | */ | |
94223d04 | 3970 | bool |
830de422 | 3971 | intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3972 | { |
9f085ebb L |
3973 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3974 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3975 | } |
3976 | ||
1100244e | 3977 | /* These are source-specific values. */ |
830de422 | 3978 | u8 |
1a2eb460 | 3979 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3980 | { |
de25eb7f | 3981 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a393e964 VS |
3982 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3983 | enum port port = encoder->port; | |
1a2eb460 | 3984 | |
a393e964 | 3985 | if (HAS_DDI(dev_priv)) |
ffe5111e | 3986 | return intel_ddi_dp_voltage_max(encoder); |
a393e964 | 3987 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3988 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
b752e995 | 3989 | else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) |
bd60018a | 3990 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3991 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3992 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3993 | else |
bd60018a | 3994 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3995 | } |
3996 | ||
830de422 JN |
3997 | u8 |
3998 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing) | |
1a2eb460 | 3999 | { |
de25eb7f | 4000 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4718a365 VS |
4001 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
4002 | enum port port = encoder->port; | |
1a2eb460 | 4003 | |
4718a365 VS |
4004 | if (HAS_DDI(dev_priv)) { |
4005 | return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing); | |
8652744b | 4006 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 4007 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
4008 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
4009 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
4010 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
4011 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
4012 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
4013 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
4014 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 4015 | default: |
bd60018a | 4016 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 4017 | } |
b752e995 | 4018 | } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
1a2eb460 | 4019 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
4020 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
4021 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
4022 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
4023 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
4024 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 4025 | default: |
bd60018a | 4026 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
4027 | } |
4028 | } else { | |
4029 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
4030 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
4031 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
4032 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
4033 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
4034 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
4035 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
4036 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 4037 | default: |
bd60018a | 4038 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 4039 | } |
a4fc5ed6 KP |
4040 | } |
4041 | } | |
4042 | ||
830de422 | 4043 | static u32 vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 4044 | { |
53d98725 | 4045 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
4046 | unsigned long demph_reg_value, preemph_reg_value, |
4047 | uniqtranscale_reg_value; | |
830de422 | 4048 | u8 train_set = intel_dp->train_set[0]; |
e2fa6fba P |
4049 | |
4050 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 4051 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
4052 | preemph_reg_value = 0x0004000; |
4053 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4054 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4055 | demph_reg_value = 0x2B405555; |
4056 | uniqtranscale_reg_value = 0x552AB83A; | |
4057 | break; | |
bd60018a | 4058 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
4059 | demph_reg_value = 0x2B404040; |
4060 | uniqtranscale_reg_value = 0x5548B83A; | |
4061 | break; | |
bd60018a | 4062 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
4063 | demph_reg_value = 0x2B245555; |
4064 | uniqtranscale_reg_value = 0x5560B83A; | |
4065 | break; | |
bd60018a | 4066 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
4067 | demph_reg_value = 0x2B405555; |
4068 | uniqtranscale_reg_value = 0x5598DA3A; | |
4069 | break; | |
4070 | default: | |
4071 | return 0; | |
4072 | } | |
4073 | break; | |
bd60018a | 4074 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
4075 | preemph_reg_value = 0x0002000; |
4076 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4077 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4078 | demph_reg_value = 0x2B404040; |
4079 | uniqtranscale_reg_value = 0x5552B83A; | |
4080 | break; | |
bd60018a | 4081 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
4082 | demph_reg_value = 0x2B404848; |
4083 | uniqtranscale_reg_value = 0x5580B83A; | |
4084 | break; | |
bd60018a | 4085 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
4086 | demph_reg_value = 0x2B404040; |
4087 | uniqtranscale_reg_value = 0x55ADDA3A; | |
4088 | break; | |
4089 | default: | |
4090 | return 0; | |
4091 | } | |
4092 | break; | |
bd60018a | 4093 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
4094 | preemph_reg_value = 0x0000000; |
4095 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4096 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4097 | demph_reg_value = 0x2B305555; |
4098 | uniqtranscale_reg_value = 0x5570B83A; | |
4099 | break; | |
bd60018a | 4100 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
4101 | demph_reg_value = 0x2B2B4040; |
4102 | uniqtranscale_reg_value = 0x55ADDA3A; | |
4103 | break; | |
4104 | default: | |
4105 | return 0; | |
4106 | } | |
4107 | break; | |
bd60018a | 4108 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
4109 | preemph_reg_value = 0x0006000; |
4110 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4111 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4112 | demph_reg_value = 0x1B405555; |
4113 | uniqtranscale_reg_value = 0x55ADDA3A; | |
4114 | break; | |
4115 | default: | |
4116 | return 0; | |
4117 | } | |
4118 | break; | |
4119 | default: | |
4120 | return 0; | |
4121 | } | |
4122 | ||
53d98725 ACO |
4123 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
4124 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
4125 | |
4126 | return 0; | |
4127 | } | |
4128 | ||
830de422 | 4129 | static u32 chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 4130 | { |
b7fa22d8 ACO |
4131 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
4132 | u32 deemph_reg_value, margin_reg_value; | |
4133 | bool uniq_trans_scale = false; | |
830de422 | 4134 | u8 train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
4135 | |
4136 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 4137 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 4138 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4139 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4140 | deemph_reg_value = 128; |
4141 | margin_reg_value = 52; | |
4142 | break; | |
bd60018a | 4143 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
4144 | deemph_reg_value = 128; |
4145 | margin_reg_value = 77; | |
4146 | break; | |
bd60018a | 4147 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
4148 | deemph_reg_value = 128; |
4149 | margin_reg_value = 102; | |
4150 | break; | |
bd60018a | 4151 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
4152 | deemph_reg_value = 128; |
4153 | margin_reg_value = 154; | |
b7fa22d8 | 4154 | uniq_trans_scale = true; |
e4a1d846 CML |
4155 | break; |
4156 | default: | |
4157 | return 0; | |
4158 | } | |
4159 | break; | |
bd60018a | 4160 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 4161 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4162 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4163 | deemph_reg_value = 85; |
4164 | margin_reg_value = 78; | |
4165 | break; | |
bd60018a | 4166 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
4167 | deemph_reg_value = 85; |
4168 | margin_reg_value = 116; | |
4169 | break; | |
bd60018a | 4170 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
4171 | deemph_reg_value = 85; |
4172 | margin_reg_value = 154; | |
4173 | break; | |
4174 | default: | |
4175 | return 0; | |
4176 | } | |
4177 | break; | |
bd60018a | 4178 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 4179 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4180 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4181 | deemph_reg_value = 64; |
4182 | margin_reg_value = 104; | |
4183 | break; | |
bd60018a | 4184 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
4185 | deemph_reg_value = 64; |
4186 | margin_reg_value = 154; | |
4187 | break; | |
4188 | default: | |
4189 | return 0; | |
4190 | } | |
4191 | break; | |
bd60018a | 4192 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 4193 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4194 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4195 | deemph_reg_value = 43; |
4196 | margin_reg_value = 154; | |
4197 | break; | |
4198 | default: | |
4199 | return 0; | |
4200 | } | |
4201 | break; | |
4202 | default: | |
4203 | return 0; | |
4204 | } | |
4205 | ||
b7fa22d8 ACO |
4206 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
4207 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
4208 | |
4209 | return 0; | |
4210 | } | |
4211 | ||
830de422 JN |
4212 | static u32 |
4213 | g4x_signal_levels(u8 train_set) | |
a4fc5ed6 | 4214 | { |
830de422 | 4215 | u32 signal_levels = 0; |
a4fc5ed6 | 4216 | |
3cf2efb1 | 4217 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4218 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
4219 | default: |
4220 | signal_levels |= DP_VOLTAGE_0_4; | |
4221 | break; | |
bd60018a | 4222 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
4223 | signal_levels |= DP_VOLTAGE_0_6; |
4224 | break; | |
bd60018a | 4225 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
4226 | signal_levels |= DP_VOLTAGE_0_8; |
4227 | break; | |
bd60018a | 4228 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
4229 | signal_levels |= DP_VOLTAGE_1_2; |
4230 | break; | |
4231 | } | |
3cf2efb1 | 4232 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 4233 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
4234 | default: |
4235 | signal_levels |= DP_PRE_EMPHASIS_0; | |
4236 | break; | |
bd60018a | 4237 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
4238 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
4239 | break; | |
bd60018a | 4240 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
4241 | signal_levels |= DP_PRE_EMPHASIS_6; |
4242 | break; | |
bd60018a | 4243 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
4244 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
4245 | break; | |
4246 | } | |
4247 | return signal_levels; | |
4248 | } | |
4249 | ||
4d82c2b5 | 4250 | /* SNB CPU eDP voltage swing and pre-emphasis control */ |
830de422 JN |
4251 | static u32 |
4252 | snb_cpu_edp_signal_levels(u8 train_set) | |
e3421a18 | 4253 | { |
3c5a62b5 YL |
4254 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
4255 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
4256 | switch (signal_levels) { | |
bd60018a SJ |
4257 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
4258 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 4259 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 4260 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 4261 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
4262 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
4263 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 4264 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
4265 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
4266 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 4267 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
4268 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
4269 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 4270 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 4271 | default: |
3c5a62b5 YL |
4272 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
4273 | "0x%x\n", signal_levels); | |
4274 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
4275 | } |
4276 | } | |
4277 | ||
4d82c2b5 | 4278 | /* IVB CPU eDP voltage swing and pre-emphasis control */ |
830de422 JN |
4279 | static u32 |
4280 | ivb_cpu_edp_signal_levels(u8 train_set) | |
1a2eb460 KP |
4281 | { |
4282 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
4283 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
4284 | switch (signal_levels) { | |
bd60018a | 4285 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4286 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 4287 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 4288 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 4289 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
4290 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
4291 | ||
bd60018a | 4292 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4293 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 4294 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
4295 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
4296 | ||
bd60018a | 4297 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4298 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 4299 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
4300 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
4301 | ||
4302 | default: | |
4303 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
4304 | "0x%x\n", signal_levels); | |
4305 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
4306 | } | |
4307 | } | |
4308 | ||
94223d04 | 4309 | void |
f4eb692e | 4310 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e | 4311 | { |
de25eb7f | 4312 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
f0a3424e | 4313 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 4314 | enum port port = intel_dig_port->base.port; |
830de422 JN |
4315 | u32 signal_levels, mask = 0; |
4316 | u8 train_set = intel_dp->train_set[0]; | |
f0a3424e | 4317 | |
61cdfb9e | 4318 | if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { |
d509af6c RV |
4319 | signal_levels = bxt_signal_levels(intel_dp); |
4320 | } else if (HAS_DDI(dev_priv)) { | |
f8896f5d | 4321 | signal_levels = ddi_signal_levels(intel_dp); |
d509af6c | 4322 | mask = DDI_BUF_EMP_MASK; |
920a14b2 | 4323 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 4324 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 4325 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 4326 | signal_levels = vlv_signal_levels(intel_dp); |
b752e995 | 4327 | } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
4d82c2b5 | 4328 | signal_levels = ivb_cpu_edp_signal_levels(train_set); |
f0a3424e | 4329 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
cf819eff | 4330 | } else if (IS_GEN(dev_priv, 6) && port == PORT_A) { |
4d82c2b5 | 4331 | signal_levels = snb_cpu_edp_signal_levels(train_set); |
f0a3424e PZ |
4332 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
4333 | } else { | |
45101e93 | 4334 | signal_levels = g4x_signal_levels(train_set); |
f0a3424e PZ |
4335 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
4336 | } | |
4337 | ||
96fb9f9b | 4338 | if (mask) |
bdc6114e WK |
4339 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", |
4340 | signal_levels); | |
4341 | ||
4342 | drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n", | |
4343 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK, | |
4344 | train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : ""); | |
4345 | drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n", | |
4346 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
4347 | DP_TRAIN_PRE_EMPHASIS_SHIFT, | |
4348 | train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? | |
4349 | " (max)" : ""); | |
f0a3424e | 4350 | |
f4eb692e | 4351 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 | 4352 | |
b4e33881 JN |
4353 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
4354 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
f0a3424e PZ |
4355 | } |
4356 | ||
94223d04 | 4357 | void |
e9c176d5 | 4358 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
830de422 | 4359 | u8 dp_train_pat) |
a4fc5ed6 | 4360 | { |
174edf1f | 4361 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
4362 | struct drm_i915_private *dev_priv = |
4363 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 4364 | |
f4eb692e | 4365 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 4366 | |
b4e33881 JN |
4367 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
4368 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
e9c176d5 ACO |
4369 | } |
4370 | ||
94223d04 | 4371 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 | 4372 | { |
de25eb7f | 4373 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
3ab9c637 | 4374 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 4375 | enum port port = intel_dig_port->base.port; |
830de422 | 4376 | u32 val; |
3ab9c637 | 4377 | |
4f8036a2 | 4378 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
4379 | return; |
4380 | ||
b4e33881 | 4381 | val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); |
3ab9c637 ID |
4382 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
4383 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
b4e33881 | 4384 | intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); |
3ab9c637 ID |
4385 | |
4386 | /* | |
99389390 JRS |
4387 | * Until TGL on PORT_A we can have only eDP in SST mode. There the only |
4388 | * reason we need to set idle transmission mode is to work around a HW | |
4389 | * issue where we enable the pipe while not in idle link-training mode. | |
3ab9c637 ID |
4390 | * In this case there is requirement to wait for a minimum number of |
4391 | * idle patterns to be sent. | |
4392 | */ | |
99389390 | 4393 | if (port == PORT_A && INTEL_GEN(dev_priv) < 12) |
3ab9c637 ID |
4394 | return; |
4395 | ||
4444df6e | 4396 | if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, |
4cb3b44d | 4397 | DP_TP_STATUS_IDLE_DONE, 1)) |
bdc6114e WK |
4398 | drm_err(&dev_priv->drm, |
4399 | "Timed out waiting for DP idle patterns\n"); | |
3ab9c637 ID |
4400 | } |
4401 | ||
a4fc5ed6 | 4402 | static void |
adc10304 VS |
4403 | intel_dp_link_down(struct intel_encoder *encoder, |
4404 | const struct intel_crtc_state *old_crtc_state) | |
a4fc5ed6 | 4405 | { |
adc10304 | 4406 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 4407 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 4408 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
adc10304 | 4409 | enum port port = encoder->port; |
830de422 | 4410 | u32 DP = intel_dp->DP; |
a4fc5ed6 | 4411 | |
eb020ca3 PB |
4412 | if (drm_WARN_ON(&dev_priv->drm, |
4413 | (intel_de_read(dev_priv, intel_dp->output_reg) & | |
4414 | DP_PORT_EN) == 0)) | |
1b39d6f3 CW |
4415 | return; |
4416 | ||
bdc6114e | 4417 | drm_dbg_kms(&dev_priv->drm, "\n"); |
32f9d658 | 4418 | |
b752e995 | 4419 | if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || |
6e266956 | 4420 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 4421 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 4422 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 4423 | } else { |
3b358cda | 4424 | DP &= ~DP_LINK_TRAIN_MASK; |
1612c8bd | 4425 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 4426 | } |
b4e33881 JN |
4427 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4428 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
5eb08b69 | 4429 | |
1612c8bd | 4430 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
b4e33881 JN |
4431 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4432 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
1612c8bd VS |
4433 | |
4434 | /* | |
4435 | * HW workaround for IBX, we need to move the port | |
4436 | * to transcoder A after disabling it to allow the | |
4437 | * matching HDMI port to be enabled on transcoder A. | |
4438 | */ | |
6e266956 | 4439 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
4440 | /* |
4441 | * We get CPU/PCH FIFO underruns on the other pipe when | |
4442 | * doing the workaround. Sweep them under the rug. | |
4443 | */ | |
4444 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
4445 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
4446 | ||
1612c8bd | 4447 | /* always enable with pattern 1 (as per spec) */ |
59b74c49 VS |
4448 | DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); |
4449 | DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | | |
4450 | DP_LINK_TRAIN_PAT_1; | |
b4e33881 JN |
4451 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4452 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
1612c8bd VS |
4453 | |
4454 | DP &= ~DP_PORT_EN; | |
b4e33881 JN |
4455 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4456 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
0c241d5b | 4457 | |
0f0f74bc | 4458 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
4459 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
4460 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
4461 | } |
4462 | ||
f01eca2e | 4463 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
4464 | |
4465 | intel_dp->DP = DP; | |
9f2bdb00 VS |
4466 | |
4467 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
69d93820 CW |
4468 | intel_wakeref_t wakeref; |
4469 | ||
4470 | with_pps_lock(intel_dp, wakeref) | |
4471 | intel_dp->active_pipe = INVALID_PIPE; | |
9f2bdb00 | 4472 | } |
a4fc5ed6 KP |
4473 | } |
4474 | ||
a1d92652 MA |
4475 | static void |
4476 | intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp) | |
4477 | { | |
af67009c | 4478 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
a1d92652 MA |
4479 | u8 dpcd_ext[6]; |
4480 | ||
4481 | /* | |
4482 | * Prior to DP1.3 the bit represented by | |
4483 | * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. | |
4484 | * if it is set DP_DPCD_REV at 0000h could be at a value less than | |
4485 | * the true capability of the panel. The only way to check is to | |
4486 | * then compare 0000h and 2200h. | |
4487 | */ | |
4488 | if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] & | |
4489 | DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) | |
4490 | return; | |
4491 | ||
4492 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV, | |
4493 | &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) { | |
af67009c JN |
4494 | drm_err(&i915->drm, |
4495 | "DPCD failed read at extended capabilities\n"); | |
a1d92652 MA |
4496 | return; |
4497 | } | |
4498 | ||
4499 | if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { | |
af67009c JN |
4500 | drm_dbg_kms(&i915->drm, |
4501 | "DPCD extended DPCD rev less than base DPCD rev\n"); | |
a1d92652 MA |
4502 | return; |
4503 | } | |
4504 | ||
4505 | if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext))) | |
4506 | return; | |
4507 | ||
af67009c JN |
4508 | drm_dbg_kms(&i915->drm, "Base DPCD: %*ph\n", |
4509 | (int)sizeof(intel_dp->dpcd), intel_dp->dpcd); | |
a1d92652 MA |
4510 | |
4511 | memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)); | |
4512 | } | |
4513 | ||
24e807e7 | 4514 | bool |
fe5a66f9 | 4515 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 4516 | { |
af67009c JN |
4517 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
4518 | ||
9f085ebb L |
4519 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
4520 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 4521 | return false; /* aux transfer failed */ |
92fd8fd1 | 4522 | |
a1d92652 MA |
4523 | intel_dp_extended_receiver_capabilities(intel_dp); |
4524 | ||
af67009c JN |
4525 | drm_dbg_kms(&i915->drm, "DPCD: %*ph\n", (int)sizeof(intel_dp->dpcd), |
4526 | intel_dp->dpcd); | |
577c7a50 | 4527 | |
fe5a66f9 VS |
4528 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
4529 | } | |
edb39244 | 4530 | |
8e9d645c GM |
4531 | bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
4532 | { | |
4533 | u8 dprx = 0; | |
4534 | ||
4535 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
4536 | &dprx) != 1) | |
4537 | return false; | |
4538 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
4539 | } | |
4540 | ||
93ac092f MN |
4541 | static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) |
4542 | { | |
af67009c JN |
4543 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
4544 | ||
93ac092f MN |
4545 | /* |
4546 | * Clear the cached register set to avoid using stale values | |
4547 | * for the sinks that do not support DSC. | |
4548 | */ | |
4549 | memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); | |
4550 | ||
08cadae8 AS |
4551 | /* Clear fec_capable to avoid using stale values */ |
4552 | intel_dp->fec_capable = 0; | |
4553 | ||
93ac092f MN |
4554 | /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ |
4555 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || | |
4556 | intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
4557 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, | |
4558 | intel_dp->dsc_dpcd, | |
4559 | sizeof(intel_dp->dsc_dpcd)) < 0) | |
af67009c JN |
4560 | drm_err(&i915->drm, |
4561 | "Failed to read DPCD register 0x%x\n", | |
4562 | DP_DSC_SUPPORT); | |
93ac092f | 4563 | |
af67009c JN |
4564 | drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n", |
4565 | (int)sizeof(intel_dp->dsc_dpcd), | |
4566 | intel_dp->dsc_dpcd); | |
0ce611c9 | 4567 | |
08cadae8 | 4568 | /* FEC is supported only on DP 1.4 */ |
0ce611c9 CW |
4569 | if (!intel_dp_is_edp(intel_dp) && |
4570 | drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, | |
4571 | &intel_dp->fec_capable) < 0) | |
af67009c JN |
4572 | drm_err(&i915->drm, |
4573 | "Failed to read FEC DPCD register\n"); | |
08cadae8 | 4574 | |
af67009c JN |
4575 | drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", |
4576 | intel_dp->fec_capable); | |
93ac092f MN |
4577 | } |
4578 | } | |
4579 | ||
fe5a66f9 VS |
4580 | static bool |
4581 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
4582 | { | |
4583 | struct drm_i915_private *dev_priv = | |
4584 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 4585 | |
fe5a66f9 | 4586 | /* this function is meant to be called only once */ |
eb020ca3 | 4587 | drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); |
30d9aa42 | 4588 | |
fe5a66f9 | 4589 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
4590 | return false; |
4591 | ||
84c36753 JN |
4592 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4593 | drm_dp_is_branch(intel_dp->dpcd)); | |
12a47a42 | 4594 | |
7c838e2a JN |
4595 | /* |
4596 | * Read the eDP display control registers. | |
4597 | * | |
4598 | * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in | |
4599 | * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it | |
4600 | * set, but require eDP 1.4+ detection (e.g. for supported link rates | |
4601 | * method). The display control registers should read zero if they're | |
4602 | * not supported anyway. | |
4603 | */ | |
4604 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
4605 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
4606 | sizeof(intel_dp->edp_dpcd)) | |
bdc6114e WK |
4607 | drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", |
4608 | (int)sizeof(intel_dp->edp_dpcd), | |
4609 | intel_dp->edp_dpcd); | |
06ea66b6 | 4610 | |
84bb2916 DP |
4611 | /* |
4612 | * This has to be called after intel_dp->edp_dpcd is filled, PSR checks | |
4613 | * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] | |
4614 | */ | |
4615 | intel_psr_init_dpcd(intel_dp); | |
4616 | ||
e6ed2a1b JN |
4617 | /* Read the eDP 1.4+ supported link rates. */ |
4618 | if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
94ca719e | 4619 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
4620 | int i; |
4621 | ||
9f085ebb L |
4622 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
4623 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 4624 | |
94ca719e VS |
4625 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
4626 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
4627 | |
4628 | if (val == 0) | |
4629 | break; | |
4630 | ||
fd81c44e DP |
4631 | /* Value read multiplied by 200kHz gives the per-lane |
4632 | * link rate in kHz. The source rates are, however, | |
4633 | * stored in terms of LS_Clk kHz. The full conversion | |
4634 | * back to symbols is | |
4635 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
4636 | */ | |
af77b974 | 4637 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 4638 | } |
94ca719e | 4639 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 4640 | } |
0336400e | 4641 | |
e6ed2a1b JN |
4642 | /* |
4643 | * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, | |
4644 | * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. | |
4645 | */ | |
68f357cb JN |
4646 | if (intel_dp->num_sink_rates) |
4647 | intel_dp->use_rate_select = true; | |
4648 | else | |
4649 | intel_dp_set_sink_rates(intel_dp); | |
4650 | ||
975ee5fc JN |
4651 | intel_dp_set_common_rates(intel_dp); |
4652 | ||
93ac092f MN |
4653 | /* Read the eDP DSC DPCD registers */ |
4654 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
4655 | intel_dp_get_dsc_sink_cap(intel_dp); | |
4656 | ||
fe5a66f9 VS |
4657 | return true; |
4658 | } | |
4659 | ||
4660 | ||
4661 | static bool | |
4662 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
4663 | { | |
4664 | if (!intel_dp_read_dpcd(intel_dp)) | |
4665 | return false; | |
4666 | ||
eaa2b31b VS |
4667 | /* |
4668 | * Don't clobber cached eDP rates. Also skip re-reading | |
4669 | * the OUI/ID since we know it won't change. | |
4670 | */ | |
1853a9da | 4671 | if (!intel_dp_is_edp(intel_dp)) { |
eaa2b31b VS |
4672 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4673 | drm_dp_is_branch(intel_dp->dpcd)); | |
4674 | ||
68f357cb | 4675 | intel_dp_set_sink_rates(intel_dp); |
975ee5fc JN |
4676 | intel_dp_set_common_rates(intel_dp); |
4677 | } | |
68f357cb | 4678 | |
fe5a66f9 | 4679 | /* |
2bb06265 JRS |
4680 | * Some eDP panels do not set a valid value for sink count, that is why |
4681 | * it don't care about read it here and in intel_edp_init_dpcd(). | |
fe5a66f9 | 4682 | */ |
eaa2b31b | 4683 | if (!intel_dp_is_edp(intel_dp) && |
0883ce81 LP |
4684 | !drm_dp_has_quirk(&intel_dp->desc, 0, |
4685 | DP_DPCD_QUIRK_NO_SINK_COUNT)) { | |
2bb06265 JRS |
4686 | u8 count; |
4687 | ssize_t r; | |
fe5a66f9 | 4688 | |
2bb06265 JRS |
4689 | r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count); |
4690 | if (r < 1) | |
4691 | return false; | |
4692 | ||
4693 | /* | |
4694 | * Sink count can change between short pulse hpd hence | |
4695 | * a member variable in intel_dp will track any changes | |
4696 | * between short pulse interrupts. | |
4697 | */ | |
4698 | intel_dp->sink_count = DP_GET_SINK_COUNT(count); | |
4699 | ||
4700 | /* | |
4701 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
4702 | * a dongle is present but no display. Unless we require to know | |
4703 | * if a dongle is present or not, we don't need to update | |
4704 | * downstream port information. So, an early return here saves | |
4705 | * time from performing other operations which are not required. | |
4706 | */ | |
4707 | if (!intel_dp->sink_count) | |
4708 | return false; | |
4709 | } | |
0336400e | 4710 | |
c726ad01 | 4711 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
4712 | return true; /* native DP sink */ |
4713 | ||
4714 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
4715 | return true; /* no per-port downstream info */ | |
4716 | ||
9f085ebb L |
4717 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
4718 | intel_dp->downstream_ports, | |
4719 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
4720 | return false; /* downstream port status fetch failed */ |
4721 | ||
4722 | return true; | |
92fd8fd1 KP |
4723 | } |
4724 | ||
0e32b39c | 4725 | static bool |
9dbf5a4e | 4726 | intel_dp_sink_can_mst(struct intel_dp *intel_dp) |
0e32b39c | 4727 | { |
010b9b39 | 4728 | u8 mstm_cap; |
0e32b39c | 4729 | |
0e32b39c DA |
4730 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) |
4731 | return false; | |
4732 | ||
010b9b39 | 4733 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1) |
c4e3170a | 4734 | return false; |
0e32b39c | 4735 | |
010b9b39 | 4736 | return mstm_cap & DP_MST_CAP; |
c4e3170a VS |
4737 | } |
4738 | ||
9dbf5a4e VS |
4739 | static bool |
4740 | intel_dp_can_mst(struct intel_dp *intel_dp) | |
4741 | { | |
4742 | return i915_modparams.enable_dp_mst && | |
4743 | intel_dp->can_mst && | |
4744 | intel_dp_sink_can_mst(intel_dp); | |
4745 | } | |
4746 | ||
c4e3170a VS |
4747 | static void |
4748 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
4749 | { | |
af67009c | 4750 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
9dbf5a4e VS |
4751 | struct intel_encoder *encoder = |
4752 | &dp_to_dig_port(intel_dp)->base; | |
4753 | bool sink_can_mst = intel_dp_sink_can_mst(intel_dp); | |
4754 | ||
af67009c JN |
4755 | drm_dbg_kms(&i915->drm, |
4756 | "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", | |
4757 | encoder->base.base.id, encoder->base.name, | |
4758 | yesno(intel_dp->can_mst), yesno(sink_can_mst), | |
4759 | yesno(i915_modparams.enable_dp_mst)); | |
c4e3170a VS |
4760 | |
4761 | if (!intel_dp->can_mst) | |
4762 | return; | |
4763 | ||
9dbf5a4e VS |
4764 | intel_dp->is_mst = sink_can_mst && |
4765 | i915_modparams.enable_dp_mst; | |
c4e3170a VS |
4766 | |
4767 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4768 | intel_dp->is_mst); | |
0e32b39c DA |
4769 | } |
4770 | ||
0e32b39c DA |
4771 | static bool |
4772 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4773 | { | |
e8b2577c PD |
4774 | return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, |
4775 | sink_irq_vector, DP_DPRX_ESI_LEN) == | |
4776 | DP_DPRX_ESI_LEN; | |
0e32b39c DA |
4777 | } |
4778 | ||
0c06fa15 GM |
4779 | bool |
4780 | intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, | |
4781 | const struct drm_connector_state *conn_state) | |
4782 | { | |
4783 | /* | |
4784 | * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication | |
4785 | * of Color Encoding Format and Content Color Gamut], in order to | |
4786 | * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. | |
4787 | */ | |
4788 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
4789 | return true; | |
4790 | ||
4791 | switch (conn_state->colorspace) { | |
4792 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
4793 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
4794 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
4795 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
4796 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
4797 | return true; | |
4798 | default: | |
4799 | break; | |
4800 | } | |
4801 | ||
4802 | return false; | |
4803 | } | |
4804 | ||
03c761b0 GM |
4805 | static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, |
4806 | struct dp_sdp *sdp, size_t size) | |
4807 | { | |
4808 | size_t length = sizeof(struct dp_sdp); | |
4809 | ||
4810 | if (size < length) | |
4811 | return -ENOSPC; | |
4812 | ||
4813 | memset(sdp, 0, size); | |
4814 | ||
4815 | /* | |
4816 | * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 | |
4817 | * VSC SDP Header Bytes | |
4818 | */ | |
4819 | sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ | |
4820 | sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ | |
4821 | sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ | |
4822 | sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ | |
4823 | ||
4824 | /* VSC SDP Payload for DB16 through DB18 */ | |
4825 | /* Pixel Encoding and Colorimetry Formats */ | |
4826 | sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ | |
4827 | sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ | |
4828 | ||
4829 | switch (vsc->bpc) { | |
4830 | case 6: | |
4831 | /* 6bpc: 0x0 */ | |
4832 | break; | |
4833 | case 8: | |
4834 | sdp->db[17] = 0x1; /* DB17[3:0] */ | |
4835 | break; | |
4836 | case 10: | |
4837 | sdp->db[17] = 0x2; | |
4838 | break; | |
4839 | case 12: | |
4840 | sdp->db[17] = 0x3; | |
4841 | break; | |
4842 | case 16: | |
4843 | sdp->db[17] = 0x4; | |
4844 | break; | |
4845 | default: | |
4846 | MISSING_CASE(vsc->bpc); | |
4847 | break; | |
4848 | } | |
4849 | /* Dynamic Range and Component Bit Depth */ | |
4850 | if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) | |
4851 | sdp->db[17] |= 0x80; /* DB17[7] */ | |
4852 | ||
4853 | /* Content Type */ | |
4854 | sdp->db[18] = vsc->content_type & 0x7; | |
4855 | ||
4856 | return length; | |
4857 | } | |
4858 | ||
4859 | static ssize_t | |
4860 | intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe, | |
4861 | struct dp_sdp *sdp, | |
4862 | size_t size) | |
4863 | { | |
4864 | size_t length = sizeof(struct dp_sdp); | |
4865 | const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; | |
4866 | unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; | |
4867 | ssize_t len; | |
4868 | ||
4869 | if (size < length) | |
4870 | return -ENOSPC; | |
4871 | ||
4872 | memset(sdp, 0, size); | |
4873 | ||
4874 | len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); | |
4875 | if (len < 0) { | |
4876 | DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n"); | |
4877 | return -ENOSPC; | |
4878 | } | |
4879 | ||
4880 | if (len != infoframe_size) { | |
4881 | DRM_DEBUG_KMS("wrong static hdr metadata size\n"); | |
4882 | return -ENOSPC; | |
4883 | } | |
4884 | ||
4885 | /* | |
4886 | * Set up the infoframe sdp packet for HDR static metadata. | |
4887 | * Prepare VSC Header for SU as per DP 1.4a spec, | |
4888 | * Table 2-100 and Table 2-101 | |
4889 | */ | |
4890 | ||
4891 | /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ | |
4892 | sdp->sdp_header.HB0 = 0; | |
4893 | /* | |
4894 | * Packet Type 80h + Non-audio INFOFRAME Type value | |
4895 | * HDMI_INFOFRAME_TYPE_DRM: 0x87 | |
4896 | * - 80h + Non-audio INFOFRAME Type value | |
4897 | * - InfoFrame Type: 0x07 | |
4898 | * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] | |
4899 | */ | |
4900 | sdp->sdp_header.HB1 = drm_infoframe->type; | |
4901 | /* | |
4902 | * Least Significant Eight Bits of (Data Byte Count – 1) | |
4903 | * infoframe_size - 1 | |
4904 | */ | |
4905 | sdp->sdp_header.HB2 = 0x1D; | |
4906 | /* INFOFRAME SDP Version Number */ | |
4907 | sdp->sdp_header.HB3 = (0x13 << 2); | |
4908 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ | |
4909 | sdp->db[0] = drm_infoframe->version; | |
4910 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ | |
4911 | sdp->db[1] = drm_infoframe->length; | |
4912 | /* | |
4913 | * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after | |
4914 | * HDMI_INFOFRAME_HEADER_SIZE | |
4915 | */ | |
4916 | BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); | |
4917 | memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], | |
4918 | HDMI_DRM_INFOFRAME_SIZE); | |
4919 | ||
4920 | /* | |
4921 | * Size of DP infoframe sdp packet for HDR static metadata consists of | |
4922 | * - DP SDP Header(struct dp_sdp_header): 4 bytes | |
4923 | * - Two Data Blocks: 2 bytes | |
4924 | * CTA Header Byte2 (INFOFRAME Version Number) | |
4925 | * CTA Header Byte3 (Length of INFOFRAME) | |
4926 | * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes | |
4927 | * | |
4928 | * Prior to GEN11's GMP register size is identical to DP HDR static metadata | |
4929 | * infoframe size. But GEN11+ has larger than that size, write_infoframe | |
4930 | * will pad rest of the size. | |
4931 | */ | |
4932 | return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; | |
4933 | } | |
4934 | ||
4935 | static void intel_write_dp_sdp(struct intel_encoder *encoder, | |
4936 | const struct intel_crtc_state *crtc_state, | |
4937 | unsigned int type) | |
4938 | { | |
4939 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
4940 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4941 | struct dp_sdp sdp = {}; | |
4942 | ssize_t len; | |
4943 | ||
4944 | if ((crtc_state->infoframes.enable & | |
4945 | intel_hdmi_infoframe_enable(type)) == 0) | |
4946 | return; | |
4947 | ||
4948 | switch (type) { | |
4949 | case DP_SDP_VSC: | |
4950 | len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, | |
4951 | sizeof(sdp)); | |
4952 | break; | |
4953 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
4954 | len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm, | |
4955 | &sdp, sizeof(sdp)); | |
4956 | break; | |
4957 | default: | |
4958 | MISSING_CASE(type); | |
d121f63c | 4959 | return; |
03c761b0 GM |
4960 | } |
4961 | ||
4962 | if (drm_WARN_ON(&dev_priv->drm, len < 0)) | |
4963 | return; | |
4964 | ||
4965 | intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); | |
4966 | } | |
4967 | ||
4968 | void intel_dp_set_infoframes(struct intel_encoder *encoder, | |
4969 | bool enable, | |
4970 | const struct intel_crtc_state *crtc_state, | |
4971 | const struct drm_connector_state *conn_state) | |
4972 | { | |
4973 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4974 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4975 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); | |
4976 | u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | | |
4977 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | | |
4978 | VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; | |
4979 | u32 val = intel_de_read(dev_priv, reg); | |
4980 | ||
4981 | /* TODO: Add DSC case (DIP_ENABLE_PPS) */ | |
4982 | /* When PSR is enabled, this routine doesn't disable VSC DIP */ | |
4983 | if (intel_psr_enabled(intel_dp)) | |
4984 | val &= ~dip_enable; | |
4985 | else | |
4986 | val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW); | |
4987 | ||
4988 | if (!enable) { | |
4989 | intel_de_write(dev_priv, reg, val); | |
4990 | intel_de_posting_read(dev_priv, reg); | |
4991 | return; | |
4992 | } | |
4993 | ||
4994 | intel_de_write(dev_priv, reg, val); | |
4995 | intel_de_posting_read(dev_priv, reg); | |
4996 | ||
4997 | /* When PSR is enabled, VSC SDP is handled by PSR routine */ | |
4998 | if (!intel_psr_enabled(intel_dp)) | |
4999 | intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); | |
5000 | ||
5001 | intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); | |
5002 | } | |
5003 | ||
3c053a96 | 5004 | static void |
bb71fb00 GM |
5005 | intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp, |
5006 | const struct intel_crtc_state *crtc_state, | |
5007 | const struct drm_connector_state *conn_state) | |
3c053a96 GM |
5008 | { |
5009 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5010 | struct dp_sdp vsc_sdp = {}; | |
5011 | ||
5012 | /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */ | |
5013 | vsc_sdp.sdp_header.HB0 = 0; | |
5014 | vsc_sdp.sdp_header.HB1 = 0x7; | |
5015 | ||
5016 | /* | |
5017 | * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ | |
5018 | * Colorimetry Format indication. | |
5019 | */ | |
5020 | vsc_sdp.sdp_header.HB2 = 0x5; | |
5021 | ||
5022 | /* | |
5023 | * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/ | |
5024 | * Colorimetry Format indication (HB2 = 05h). | |
5025 | */ | |
5026 | vsc_sdp.sdp_header.HB3 = 0x13; | |
5027 | ||
bb71fb00 GM |
5028 | /* DP 1.4a spec, Table 2-120 */ |
5029 | switch (crtc_state->output_format) { | |
5030 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
5031 | vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */ | |
5032 | break; | |
5033 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
5034 | vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */ | |
5035 | break; | |
5036 | case INTEL_OUTPUT_FORMAT_RGB: | |
5037 | default: | |
5038 | /* RGB: DB16[7:4] = 0h */ | |
5039 | break; | |
5040 | } | |
5041 | ||
5042 | switch (conn_state->colorspace) { | |
5043 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
5044 | vsc_sdp.db[16] |= 0x1; | |
5045 | break; | |
5046 | case DRM_MODE_COLORIMETRY_XVYCC_601: | |
5047 | vsc_sdp.db[16] |= 0x2; | |
5048 | break; | |
5049 | case DRM_MODE_COLORIMETRY_XVYCC_709: | |
5050 | vsc_sdp.db[16] |= 0x3; | |
5051 | break; | |
5052 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
5053 | vsc_sdp.db[16] |= 0x4; | |
5054 | break; | |
5055 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
5056 | vsc_sdp.db[16] |= 0x5; | |
5057 | break; | |
5058 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
5059 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
5060 | vsc_sdp.db[16] |= 0x6; | |
5061 | break; | |
5062 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
5063 | vsc_sdp.db[16] |= 0x7; | |
5064 | break; | |
5065 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: | |
5066 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: | |
5067 | vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */ | |
5068 | break; | |
5069 | default: | |
5070 | /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */ | |
5071 | ||
5072 | /* RGB->YCBCR color conversion uses the BT.709 color space. */ | |
5073 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
5074 | vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */ | |
5075 | break; | |
5076 | } | |
3c053a96 GM |
5077 | |
5078 | /* | |
5079 | * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only, | |
5080 | * the following Component Bit Depth values are defined: | |
5081 | * 001b = 8bpc. | |
5082 | * 010b = 10bpc. | |
5083 | * 011b = 12bpc. | |
5084 | * 100b = 16bpc. | |
5085 | */ | |
5086 | switch (crtc_state->pipe_bpp) { | |
5087 | case 24: /* 8bpc */ | |
5088 | vsc_sdp.db[17] = 0x1; | |
5089 | break; | |
5090 | case 30: /* 10bpc */ | |
5091 | vsc_sdp.db[17] = 0x2; | |
5092 | break; | |
5093 | case 36: /* 12bpc */ | |
5094 | vsc_sdp.db[17] = 0x3; | |
5095 | break; | |
5096 | case 48: /* 16bpc */ | |
5097 | vsc_sdp.db[17] = 0x4; | |
5098 | break; | |
5099 | default: | |
5100 | MISSING_CASE(crtc_state->pipe_bpp); | |
5101 | break; | |
5102 | } | |
5103 | ||
5104 | /* | |
5105 | * Dynamic Range (Bit 7) | |
5106 | * 0 = VESA range, 1 = CTA range. | |
5107 | * all YCbCr are always limited range | |
5108 | */ | |
5109 | vsc_sdp.db[17] |= 0x80; | |
5110 | ||
5111 | /* | |
5112 | * Content Type (Bits 2:0) | |
5113 | * 000b = Not defined. | |
5114 | * 001b = Graphics. | |
5115 | * 010b = Photo. | |
5116 | * 011b = Video. | |
5117 | * 100b = Game | |
5118 | * All other values are RESERVED. | |
5119 | * Note: See CTA-861-G for the definition and expected | |
5120 | * processing by a stream sink for the above contect types. | |
5121 | */ | |
5122 | vsc_sdp.db[18] = 0; | |
5123 | ||
5124 | intel_dig_port->write_infoframe(&intel_dig_port->base, | |
5125 | crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp)); | |
5126 | } | |
5127 | ||
b246cf21 GM |
5128 | static void |
5129 | intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, | |
5130 | const struct intel_crtc_state *crtc_state, | |
5131 | const struct drm_connector_state *conn_state) | |
5132 | { | |
af67009c | 5133 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b246cf21 GM |
5134 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5135 | struct dp_sdp infoframe_sdp = {}; | |
5136 | struct hdmi_drm_infoframe drm_infoframe = {}; | |
5137 | const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; | |
5138 | unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; | |
5139 | ssize_t len; | |
5140 | int ret; | |
5141 | ||
5142 | ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state); | |
5143 | if (ret) { | |
af67009c JN |
5144 | drm_dbg_kms(&i915->drm, |
5145 | "couldn't set HDR metadata in infoframe\n"); | |
b246cf21 GM |
5146 | return; |
5147 | } | |
5148 | ||
5149 | len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf)); | |
5150 | if (len < 0) { | |
af67009c JN |
5151 | drm_dbg_kms(&i915->drm, |
5152 | "buffer size is smaller than hdr metadata infoframe\n"); | |
b246cf21 GM |
5153 | return; |
5154 | } | |
5155 | ||
5156 | if (len != infoframe_size) { | |
af67009c | 5157 | drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n"); |
b246cf21 GM |
5158 | return; |
5159 | } | |
5160 | ||
5161 | /* | |
5162 | * Set up the infoframe sdp packet for HDR static metadata. | |
5163 | * Prepare VSC Header for SU as per DP 1.4a spec, | |
5164 | * Table 2-100 and Table 2-101 | |
5165 | */ | |
5166 | ||
5167 | /* Packet ID, 00h for non-Audio INFOFRAME */ | |
5168 | infoframe_sdp.sdp_header.HB0 = 0; | |
5169 | /* | |
5170 | * Packet Type 80h + Non-audio INFOFRAME Type value | |
5171 | * HDMI_INFOFRAME_TYPE_DRM: 0x87, | |
5172 | */ | |
5173 | infoframe_sdp.sdp_header.HB1 = drm_infoframe.type; | |
5174 | /* | |
5175 | * Least Significant Eight Bits of (Data Byte Count – 1) | |
5176 | * infoframe_size - 1, | |
5177 | */ | |
5178 | infoframe_sdp.sdp_header.HB2 = 0x1D; | |
5179 | /* INFOFRAME SDP Version Number */ | |
5180 | infoframe_sdp.sdp_header.HB3 = (0x13 << 2); | |
5181 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ | |
5182 | infoframe_sdp.db[0] = drm_infoframe.version; | |
5183 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ | |
5184 | infoframe_sdp.db[1] = drm_infoframe.length; | |
5185 | /* | |
5186 | * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after | |
5187 | * HDMI_INFOFRAME_HEADER_SIZE | |
5188 | */ | |
5189 | BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2); | |
5190 | memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], | |
5191 | HDMI_DRM_INFOFRAME_SIZE); | |
5192 | ||
5193 | /* | |
5194 | * Size of DP infoframe sdp packet for HDR static metadata is consist of | |
5195 | * - DP SDP Header(struct dp_sdp_header): 4 bytes | |
5196 | * - Two Data Blocks: 2 bytes | |
5197 | * CTA Header Byte2 (INFOFRAME Version Number) | |
5198 | * CTA Header Byte3 (Length of INFOFRAME) | |
5199 | * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes | |
5200 | * | |
5201 | * Prior to GEN11's GMP register size is identical to DP HDR static metadata | |
5202 | * infoframe size. But GEN11+ has larger than that size, write_infoframe | |
5203 | * will pad rest of the size. | |
5204 | */ | |
5205 | intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state, | |
5206 | HDMI_PACKET_TYPE_GAMUT_METADATA, | |
5207 | &infoframe_sdp, | |
5208 | sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE); | |
5209 | } | |
5210 | ||
bb71fb00 GM |
5211 | void intel_dp_vsc_enable(struct intel_dp *intel_dp, |
5212 | const struct intel_crtc_state *crtc_state, | |
5213 | const struct drm_connector_state *conn_state) | |
3c053a96 | 5214 | { |
0c06fa15 | 5215 | if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) |
3c053a96 GM |
5216 | return; |
5217 | ||
bb71fb00 | 5218 | intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state); |
3c053a96 GM |
5219 | } |
5220 | ||
b246cf21 GM |
5221 | void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp, |
5222 | const struct intel_crtc_state *crtc_state, | |
5223 | const struct drm_connector_state *conn_state) | |
5224 | { | |
5225 | if (!conn_state->hdr_output_metadata) | |
5226 | return; | |
5227 | ||
5228 | intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp, | |
5229 | crtc_state, | |
5230 | conn_state); | |
5231 | } | |
5232 | ||
830de422 | 5233 | static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
c5d5ab7a | 5234 | { |
af67009c | 5235 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
da15f7cb | 5236 | int status = 0; |
140ef138 | 5237 | int test_link_rate; |
830de422 | 5238 | u8 test_lane_count, test_link_bw; |
da15f7cb MN |
5239 | /* (DP CTS 1.2) |
5240 | * 4.3.1.11 | |
5241 | */ | |
5242 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
5243 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
5244 | &test_lane_count); | |
5245 | ||
5246 | if (status <= 0) { | |
af67009c | 5247 | drm_dbg_kms(&i915->drm, "Lane count read failed\n"); |
da15f7cb MN |
5248 | return DP_TEST_NAK; |
5249 | } | |
5250 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
da15f7cb MN |
5251 | |
5252 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
5253 | &test_link_bw); | |
5254 | if (status <= 0) { | |
af67009c | 5255 | drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); |
da15f7cb MN |
5256 | return DP_TEST_NAK; |
5257 | } | |
da15f7cb | 5258 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); |
140ef138 MN |
5259 | |
5260 | /* Validate the requested link rate and lane count */ | |
5261 | if (!intel_dp_link_params_valid(intel_dp, test_link_rate, | |
5262 | test_lane_count)) | |
da15f7cb MN |
5263 | return DP_TEST_NAK; |
5264 | ||
5265 | intel_dp->compliance.test_lane_count = test_lane_count; | |
5266 | intel_dp->compliance.test_link_rate = test_link_rate; | |
5267 | ||
5268 | return DP_TEST_ACK; | |
c5d5ab7a TP |
5269 | } |
5270 | ||
830de422 | 5271 | static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
c5d5ab7a | 5272 | { |
af67009c | 5273 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 JN |
5274 | u8 test_pattern; |
5275 | u8 test_misc; | |
611032bf MN |
5276 | __be16 h_width, v_height; |
5277 | int status = 0; | |
5278 | ||
5279 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
010b9b39 JN |
5280 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, |
5281 | &test_pattern); | |
611032bf | 5282 | if (status <= 0) { |
af67009c | 5283 | drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); |
611032bf MN |
5284 | return DP_TEST_NAK; |
5285 | } | |
5286 | if (test_pattern != DP_COLOR_RAMP) | |
5287 | return DP_TEST_NAK; | |
5288 | ||
5289 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
5290 | &h_width, 2); | |
5291 | if (status <= 0) { | |
af67009c | 5292 | drm_dbg_kms(&i915->drm, "H Width read failed\n"); |
611032bf MN |
5293 | return DP_TEST_NAK; |
5294 | } | |
5295 | ||
5296 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
5297 | &v_height, 2); | |
5298 | if (status <= 0) { | |
af67009c | 5299 | drm_dbg_kms(&i915->drm, "V Height read failed\n"); |
611032bf MN |
5300 | return DP_TEST_NAK; |
5301 | } | |
5302 | ||
010b9b39 JN |
5303 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, |
5304 | &test_misc); | |
611032bf | 5305 | if (status <= 0) { |
af67009c | 5306 | drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); |
611032bf MN |
5307 | return DP_TEST_NAK; |
5308 | } | |
5309 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
5310 | return DP_TEST_NAK; | |
5311 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
5312 | return DP_TEST_NAK; | |
5313 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
5314 | case DP_TEST_BIT_DEPTH_6: | |
5315 | intel_dp->compliance.test_data.bpc = 6; | |
5316 | break; | |
5317 | case DP_TEST_BIT_DEPTH_8: | |
5318 | intel_dp->compliance.test_data.bpc = 8; | |
5319 | break; | |
5320 | default: | |
5321 | return DP_TEST_NAK; | |
5322 | } | |
5323 | ||
5324 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
5325 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
5326 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
5327 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 5328 | intel_dp->compliance.test_active = true; |
611032bf MN |
5329 | |
5330 | return DP_TEST_ACK; | |
c5d5ab7a TP |
5331 | } |
5332 | ||
830de422 | 5333 | static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) |
a60f0e38 | 5334 | { |
af67009c | 5335 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 | 5336 | u8 test_result = DP_TEST_ACK; |
559be30c TP |
5337 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
5338 | struct drm_connector *connector = &intel_connector->base; | |
5339 | ||
5340 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 5341 | connector->edid_corrupt || |
559be30c TP |
5342 | intel_dp->aux.i2c_defer_count > 6) { |
5343 | /* Check EDID read for NACKs, DEFERs and corruption | |
5344 | * (DP CTS 1.2 Core r1.1) | |
5345 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
5346 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
5347 | * 4.2.2.6 : EDID corruption detected | |
5348 | * Use failsafe mode for all cases | |
5349 | */ | |
5350 | if (intel_dp->aux.i2c_nack_count > 0 || | |
5351 | intel_dp->aux.i2c_defer_count > 0) | |
af67009c JN |
5352 | drm_dbg_kms(&i915->drm, |
5353 | "EDID read had %d NACKs, %d DEFERs\n", | |
5354 | intel_dp->aux.i2c_nack_count, | |
5355 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 5356 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 5357 | } else { |
f79b468e TS |
5358 | struct edid *block = intel_connector->detect_edid; |
5359 | ||
5360 | /* We have to write the checksum | |
5361 | * of the last block read | |
5362 | */ | |
5363 | block += intel_connector->detect_edid->extensions; | |
5364 | ||
010b9b39 JN |
5365 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, |
5366 | block->checksum) <= 0) | |
af67009c JN |
5367 | drm_dbg_kms(&i915->drm, |
5368 | "Failed to write EDID checksum\n"); | |
559be30c TP |
5369 | |
5370 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 5371 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
5372 | } |
5373 | ||
5374 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 5375 | intel_dp->compliance.test_active = true; |
559be30c | 5376 | |
c5d5ab7a TP |
5377 | return test_result; |
5378 | } | |
5379 | ||
88afbfdb AM |
5380 | static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp) |
5381 | { | |
5382 | struct drm_dp_phy_test_params *data = | |
5383 | &intel_dp->compliance.test_data.phytest; | |
5384 | ||
5385 | if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { | |
5386 | DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n"); | |
5387 | return DP_TEST_NAK; | |
5388 | } | |
5389 | ||
5390 | /* | |
5391 | * link_mst is set to false to avoid executing mst related code | |
5392 | * during compliance testing. | |
5393 | */ | |
5394 | intel_dp->link_mst = false; | |
5395 | ||
5396 | return DP_TEST_ACK; | |
5397 | } | |
5398 | ||
8cdf7271 AM |
5399 | static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) |
5400 | { | |
5401 | struct drm_i915_private *dev_priv = | |
5402 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
5403 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5404 | struct drm_dp_phy_test_params *data = | |
5405 | &intel_dp->compliance.test_data.phytest; | |
5406 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); | |
5407 | enum pipe pipe = crtc->pipe; | |
5408 | u32 pattern_val; | |
5409 | ||
5410 | switch (data->phy_pattern) { | |
5411 | case DP_PHY_TEST_PATTERN_NONE: | |
5412 | DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); | |
5413 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); | |
5414 | break; | |
5415 | case DP_PHY_TEST_PATTERN_D10_2: | |
5416 | DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); | |
5417 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5418 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); | |
5419 | break; | |
5420 | case DP_PHY_TEST_PATTERN_ERROR_COUNT: | |
5421 | DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); | |
5422 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5423 | DDI_DP_COMP_CTL_ENABLE | | |
5424 | DDI_DP_COMP_CTL_SCRAMBLED_0); | |
5425 | break; | |
5426 | case DP_PHY_TEST_PATTERN_PRBS7: | |
5427 | DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); | |
5428 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5429 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); | |
5430 | break; | |
5431 | case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: | |
5432 | /* | |
5433 | * FIXME: Ideally pattern should come from DPCD 0x250. As | |
5434 | * current firmware of DPR-100 could not set it, so hardcoding | |
5435 | * now for complaince test. | |
5436 | */ | |
5437 | DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); | |
5438 | pattern_val = 0x3e0f83e0; | |
5439 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); | |
5440 | pattern_val = 0x0f83e0f8; | |
5441 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); | |
5442 | pattern_val = 0x0000f83e; | |
5443 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); | |
5444 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5445 | DDI_DP_COMP_CTL_ENABLE | | |
5446 | DDI_DP_COMP_CTL_CUSTOM80); | |
5447 | break; | |
5448 | case DP_PHY_TEST_PATTERN_CP2520: | |
5449 | /* | |
5450 | * FIXME: Ideally pattern should come from DPCD 0x24A. As | |
5451 | * current firmware of DPR-100 could not set it, so hardcoding | |
5452 | * now for complaince test. | |
5453 | */ | |
5454 | DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); | |
5455 | pattern_val = 0xFB; | |
5456 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5457 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | | |
5458 | pattern_val); | |
5459 | break; | |
5460 | default: | |
5461 | WARN(1, "Invalid Phy Test Pattern\n"); | |
5462 | } | |
5463 | } | |
5464 | ||
5465 | static void | |
5466 | intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) | |
5467 | { | |
5468 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5469 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
5470 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5471 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); | |
5472 | enum pipe pipe = crtc->pipe; | |
5473 | u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; | |
5474 | ||
5475 | trans_ddi_func_ctl_value = intel_de_read(dev_priv, | |
5476 | TRANS_DDI_FUNC_CTL(pipe)); | |
5477 | trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); | |
5478 | dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); | |
5479 | ||
5480 | trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | | |
5481 | TGL_TRANS_DDI_PORT_MASK); | |
5482 | trans_conf_value &= ~PIPECONF_ENABLE; | |
5483 | dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; | |
5484 | ||
5485 | intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); | |
5486 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), | |
5487 | trans_ddi_func_ctl_value); | |
5488 | intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); | |
5489 | } | |
5490 | ||
5491 | static void | |
5492 | intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) | |
5493 | { | |
5494 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5495 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
5496 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5497 | enum port port = intel_dig_port->base.port; | |
5498 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); | |
5499 | enum pipe pipe = crtc->pipe; | |
5500 | u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; | |
5501 | ||
5502 | trans_ddi_func_ctl_value = intel_de_read(dev_priv, | |
5503 | TRANS_DDI_FUNC_CTL(pipe)); | |
5504 | trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); | |
5505 | dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); | |
5506 | ||
5507 | trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | | |
5508 | TGL_TRANS_DDI_SELECT_PORT(port); | |
5509 | trans_conf_value |= PIPECONF_ENABLE; | |
5510 | dp_tp_ctl_value |= DP_TP_CTL_ENABLE; | |
5511 | ||
5512 | intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); | |
5513 | intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); | |
5514 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), | |
5515 | trans_ddi_func_ctl_value); | |
5516 | } | |
5517 | ||
5518 | void intel_dp_process_phy_request(struct intel_dp *intel_dp) | |
5519 | { | |
5520 | struct drm_dp_phy_test_params *data = | |
5521 | &intel_dp->compliance.test_data.phytest; | |
5522 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
5523 | ||
5524 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
5525 | DRM_DEBUG_KMS("failed to get link status\n"); | |
5526 | return; | |
5527 | } | |
5528 | ||
5529 | /* retrieve vswing & pre-emphasis setting */ | |
5530 | intel_dp_get_adjust_train(intel_dp, link_status); | |
5531 | ||
5532 | intel_dp_autotest_phy_ddi_disable(intel_dp); | |
5533 | ||
5534 | intel_dp_set_signal_levels(intel_dp); | |
5535 | ||
5536 | intel_dp_phy_pattern_update(intel_dp); | |
5537 | ||
5538 | intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes); | |
5539 | ||
5540 | drm_dp_set_phy_test_pattern(&intel_dp->aux, data, | |
5541 | link_status[DP_DPCD_REV]); | |
5542 | } | |
5543 | ||
830de422 | 5544 | static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
a60f0e38 | 5545 | { |
7479f3c9 | 5546 | u8 test_result; |
88afbfdb AM |
5547 | |
5548 | test_result = intel_dp_prepare_phytest(intel_dp); | |
5549 | if (test_result != DP_TEST_ACK) | |
5550 | DRM_ERROR("Phy test preparation failed\n"); | |
5551 | ||
8cdf7271 AM |
5552 | intel_dp_process_phy_request(intel_dp); |
5553 | ||
c5d5ab7a TP |
5554 | return test_result; |
5555 | } | |
5556 | ||
5557 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
5558 | { | |
af67009c | 5559 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 JN |
5560 | u8 response = DP_TEST_NAK; |
5561 | u8 request = 0; | |
5ec63bbd | 5562 | int status; |
c5d5ab7a | 5563 | |
5ec63bbd | 5564 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a | 5565 | if (status <= 0) { |
af67009c JN |
5566 | drm_dbg_kms(&i915->drm, |
5567 | "Could not read test request from sink\n"); | |
c5d5ab7a TP |
5568 | goto update_status; |
5569 | } | |
5570 | ||
5ec63bbd | 5571 | switch (request) { |
c5d5ab7a | 5572 | case DP_TEST_LINK_TRAINING: |
af67009c | 5573 | drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); |
c5d5ab7a TP |
5574 | response = intel_dp_autotest_link_training(intel_dp); |
5575 | break; | |
5576 | case DP_TEST_LINK_VIDEO_PATTERN: | |
af67009c | 5577 | drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); |
c5d5ab7a TP |
5578 | response = intel_dp_autotest_video_pattern(intel_dp); |
5579 | break; | |
5580 | case DP_TEST_LINK_EDID_READ: | |
af67009c | 5581 | drm_dbg_kms(&i915->drm, "EDID test requested\n"); |
c5d5ab7a TP |
5582 | response = intel_dp_autotest_edid(intel_dp); |
5583 | break; | |
5584 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
af67009c | 5585 | drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); |
c5d5ab7a TP |
5586 | response = intel_dp_autotest_phy_pattern(intel_dp); |
5587 | break; | |
5588 | default: | |
af67009c JN |
5589 | drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", |
5590 | request); | |
c5d5ab7a TP |
5591 | break; |
5592 | } | |
5593 | ||
5ec63bbd JN |
5594 | if (response & DP_TEST_ACK) |
5595 | intel_dp->compliance.test_type = request; | |
5596 | ||
c5d5ab7a | 5597 | update_status: |
5ec63bbd | 5598 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a | 5599 | if (status <= 0) |
af67009c JN |
5600 | drm_dbg_kms(&i915->drm, |
5601 | "Could not write test response to sink\n"); | |
a60f0e38 JB |
5602 | } |
5603 | ||
0e32b39c DA |
5604 | static int |
5605 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
5606 | { | |
af67009c | 5607 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
f0617ff0 | 5608 | bool need_retrain = false; |
0e32b39c | 5609 | |
3c0ec2c2 VS |
5610 | if (!intel_dp->is_mst) |
5611 | return -EINVAL; | |
5612 | ||
5613 | WARN_ON_ONCE(intel_dp->active_mst_links < 0); | |
5614 | ||
5615 | for (;;) { | |
5616 | u8 esi[DP_DPRX_ESI_LEN] = {}; | |
5617 | bool bret, handled; | |
0e32b39c | 5618 | int retry; |
45ef40aa | 5619 | |
0e32b39c | 5620 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); |
3c0ec2c2 VS |
5621 | if (!bret) { |
5622 | drm_dbg_kms(&i915->drm, | |
5623 | "failed to get ESI - device may have failed\n"); | |
5624 | return -EINVAL; | |
5625 | } | |
0e32b39c | 5626 | |
3c0ec2c2 | 5627 | /* check link status - esi[10] = 0x200c */ |
f0617ff0 | 5628 | if (intel_dp->active_mst_links > 0 && !need_retrain && |
3c0ec2c2 VS |
5629 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
5630 | drm_dbg_kms(&i915->drm, | |
5631 | "channel EQ not ok, retraining\n"); | |
f0617ff0 | 5632 | need_retrain = true; |
3c0ec2c2 | 5633 | } |
0e32b39c | 5634 | |
3c0ec2c2 | 5635 | drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); |
0e32b39c | 5636 | |
3c0ec2c2 VS |
5637 | drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
5638 | if (!handled) | |
5639 | break; | |
5640 | ||
5641 | for (retry = 0; retry < 3; retry++) { | |
5642 | int wret; | |
5643 | ||
5644 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
5645 | DP_SINK_COUNT_ESI+1, | |
5646 | &esi[1], 3); | |
5647 | if (wret == 3) | |
5648 | break; | |
0e32b39c DA |
5649 | } |
5650 | } | |
3c0ec2c2 | 5651 | |
f0617ff0 | 5652 | return need_retrain; |
0e32b39c DA |
5653 | } |
5654 | ||
c85d200e VS |
5655 | static bool |
5656 | intel_dp_needs_link_retrain(struct intel_dp *intel_dp) | |
5657 | { | |
5658 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
5659 | ||
edb2e530 | 5660 | if (!intel_dp->link_trained) |
2f8e7ea9 JRS |
5661 | return false; |
5662 | ||
5663 | /* | |
5664 | * While PSR source HW is enabled, it will control main-link sending | |
5665 | * frames, enabling and disabling it so trying to do a retrain will fail | |
5666 | * as the link would or not be on or it could mix training patterns | |
5667 | * and frame data at the same time causing retrain to fail. | |
5668 | * Also when exiting PSR, HW will retrain the link anyways fixing | |
5669 | * any link status error. | |
5670 | */ | |
5671 | if (intel_psr_enabled(intel_dp)) | |
edb2e530 VS |
5672 | return false; |
5673 | ||
5674 | if (!intel_dp_get_link_status(intel_dp, link_status)) | |
c85d200e | 5675 | return false; |
c85d200e VS |
5676 | |
5677 | /* | |
5678 | * Validate the cached values of intel_dp->link_rate and | |
5679 | * intel_dp->lane_count before attempting to retrain. | |
5680 | */ | |
5681 | if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, | |
5682 | intel_dp->lane_count)) | |
5683 | return false; | |
5684 | ||
5685 | /* Retrain if Channel EQ or CR not ok */ | |
5686 | return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); | |
5687 | } | |
5688 | ||
f0617ff0 VS |
5689 | static bool intel_dp_has_connector(struct intel_dp *intel_dp, |
5690 | const struct drm_connector_state *conn_state) | |
5691 | { | |
5692 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5693 | struct intel_encoder *encoder; | |
5694 | enum pipe pipe; | |
5695 | ||
5696 | if (!conn_state->best_encoder) | |
5697 | return false; | |
5698 | ||
5699 | /* SST */ | |
5700 | encoder = &dp_to_dig_port(intel_dp)->base; | |
5701 | if (conn_state->best_encoder == &encoder->base) | |
5702 | return true; | |
5703 | ||
5704 | /* MST */ | |
5705 | for_each_pipe(i915, pipe) { | |
5706 | encoder = &intel_dp->mst_encoders[pipe]->base; | |
5707 | if (conn_state->best_encoder == &encoder->base) | |
5708 | return true; | |
5709 | } | |
5710 | ||
5711 | return false; | |
5712 | } | |
5713 | ||
5714 | static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp, | |
5715 | struct drm_modeset_acquire_ctx *ctx, | |
5716 | u32 *crtc_mask) | |
5717 | { | |
5718 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5719 | struct drm_connector_list_iter conn_iter; | |
5720 | struct intel_connector *connector; | |
5721 | int ret = 0; | |
5722 | ||
5723 | *crtc_mask = 0; | |
5724 | ||
5725 | if (!intel_dp_needs_link_retrain(intel_dp)) | |
5726 | return 0; | |
5727 | ||
5728 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); | |
5729 | for_each_intel_connector_iter(connector, &conn_iter) { | |
5730 | struct drm_connector_state *conn_state = | |
5731 | connector->base.state; | |
5732 | struct intel_crtc_state *crtc_state; | |
5733 | struct intel_crtc *crtc; | |
5734 | ||
5735 | if (!intel_dp_has_connector(intel_dp, conn_state)) | |
5736 | continue; | |
5737 | ||
5738 | crtc = to_intel_crtc(conn_state->crtc); | |
5739 | if (!crtc) | |
5740 | continue; | |
5741 | ||
5742 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
5743 | if (ret) | |
5744 | break; | |
5745 | ||
5746 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
5747 | ||
5748 | drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); | |
5749 | ||
5750 | if (!crtc_state->hw.active) | |
5751 | continue; | |
5752 | ||
5753 | if (conn_state->commit && | |
5754 | !try_wait_for_completion(&conn_state->commit->hw_done)) | |
5755 | continue; | |
5756 | ||
5757 | *crtc_mask |= drm_crtc_mask(&crtc->base); | |
5758 | } | |
5759 | drm_connector_list_iter_end(&conn_iter); | |
5760 | ||
5761 | if (!intel_dp_needs_link_retrain(intel_dp)) | |
5762 | *crtc_mask = 0; | |
5763 | ||
5764 | return ret; | |
5765 | } | |
5766 | ||
5767 | static bool intel_dp_is_connected(struct intel_dp *intel_dp) | |
5768 | { | |
5769 | struct intel_connector *connector = intel_dp->attached_connector; | |
5770 | ||
5771 | return connector->base.status == connector_status_connected || | |
5772 | intel_dp->is_mst; | |
5773 | } | |
5774 | ||
c85d200e VS |
5775 | int intel_dp_retrain_link(struct intel_encoder *encoder, |
5776 | struct drm_modeset_acquire_ctx *ctx) | |
bfd02b3c | 5777 | { |
bfd02b3c | 5778 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 5779 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
c85d200e | 5780 | struct intel_crtc *crtc; |
f0617ff0 | 5781 | u32 crtc_mask; |
c85d200e VS |
5782 | int ret; |
5783 | ||
f0617ff0 | 5784 | if (!intel_dp_is_connected(intel_dp)) |
c85d200e VS |
5785 | return 0; |
5786 | ||
5787 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
5788 | ctx); | |
5789 | if (ret) | |
5790 | return ret; | |
5791 | ||
f0617ff0 | 5792 | ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask); |
c85d200e VS |
5793 | if (ret) |
5794 | return ret; | |
5795 | ||
f0617ff0 | 5796 | if (crtc_mask == 0) |
c85d200e VS |
5797 | return 0; |
5798 | ||
f0617ff0 VS |
5799 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", |
5800 | encoder->base.base.id, encoder->base.name); | |
c85d200e | 5801 | |
f0617ff0 VS |
5802 | for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { |
5803 | const struct intel_crtc_state *crtc_state = | |
5804 | to_intel_crtc_state(crtc->base.state); | |
bfd02b3c | 5805 | |
f0617ff0 VS |
5806 | /* Suppress underruns caused by re-training */ |
5807 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
5808 | if (crtc_state->has_pch_encoder) | |
5809 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
5810 | intel_crtc_pch_transcoder(crtc), false); | |
5811 | } | |
bfd02b3c VS |
5812 | |
5813 | intel_dp_start_link_train(intel_dp); | |
5814 | intel_dp_stop_link_train(intel_dp); | |
5815 | ||
f0617ff0 VS |
5816 | for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { |
5817 | const struct intel_crtc_state *crtc_state = | |
5818 | to_intel_crtc_state(crtc->base.state); | |
bfd02b3c | 5819 | |
f0617ff0 VS |
5820 | /* Keep underrun reporting disabled until things are stable */ |
5821 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
5822 | ||
5823 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
5824 | if (crtc_state->has_pch_encoder) | |
5825 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
5826 | intel_crtc_pch_transcoder(crtc), true); | |
5827 | } | |
c85d200e VS |
5828 | |
5829 | return 0; | |
bfd02b3c VS |
5830 | } |
5831 | ||
c85d200e VS |
5832 | /* |
5833 | * If display is now connected check links status, | |
5834 | * there has been known issues of link loss triggering | |
5835 | * long pulse. | |
5836 | * | |
5837 | * Some sinks (eg. ASUS PB287Q) seem to perform some | |
5838 | * weird HPD ping pong during modesets. So we can apparently | |
5839 | * end up with HPD going low during a modeset, and then | |
5840 | * going back up soon after. And once that happens we must | |
5841 | * retrain the link to get a picture. That's in case no | |
5842 | * userspace component reacted to intermittent HPD dip. | |
5843 | */ | |
3944709d ID |
5844 | static enum intel_hotplug_state |
5845 | intel_dp_hotplug(struct intel_encoder *encoder, | |
8c8919c7 | 5846 | struct intel_connector *connector) |
5c9114d0 | 5847 | { |
c85d200e | 5848 | struct drm_modeset_acquire_ctx ctx; |
3944709d | 5849 | enum intel_hotplug_state state; |
c85d200e | 5850 | int ret; |
5c9114d0 | 5851 | |
8c8919c7 | 5852 | state = intel_encoder_hotplug(encoder, connector); |
5c9114d0 | 5853 | |
c85d200e | 5854 | drm_modeset_acquire_init(&ctx, 0); |
42e5e657 | 5855 | |
c85d200e VS |
5856 | for (;;) { |
5857 | ret = intel_dp_retrain_link(encoder, &ctx); | |
5c9114d0 | 5858 | |
c85d200e VS |
5859 | if (ret == -EDEADLK) { |
5860 | drm_modeset_backoff(&ctx); | |
5861 | continue; | |
5862 | } | |
5c9114d0 | 5863 | |
c85d200e VS |
5864 | break; |
5865 | } | |
d4cb3fd9 | 5866 | |
c85d200e VS |
5867 | drm_modeset_drop_locks(&ctx); |
5868 | drm_modeset_acquire_fini(&ctx); | |
3a47ae20 PB |
5869 | drm_WARN(encoder->base.dev, ret, |
5870 | "Acquiring modeset locks failed with %i\n", ret); | |
bfd02b3c | 5871 | |
bb80c925 JRS |
5872 | /* |
5873 | * Keeping it consistent with intel_ddi_hotplug() and | |
5874 | * intel_hdmi_hotplug(). | |
5875 | */ | |
8c8919c7 | 5876 | if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) |
bb80c925 JRS |
5877 | state = INTEL_HOTPLUG_RETRY; |
5878 | ||
3944709d | 5879 | return state; |
5c9114d0 SS |
5880 | } |
5881 | ||
9844bc87 DP |
5882 | static void intel_dp_check_service_irq(struct intel_dp *intel_dp) |
5883 | { | |
af67009c | 5884 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
9844bc87 DP |
5885 | u8 val; |
5886 | ||
5887 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
5888 | return; | |
5889 | ||
5890 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
5891 | DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) | |
5892 | return; | |
5893 | ||
5894 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); | |
5895 | ||
5896 | if (val & DP_AUTOMATED_TEST_REQUEST) | |
5897 | intel_dp_handle_test_request(intel_dp); | |
5898 | ||
342ac601 | 5899 | if (val & DP_CP_IRQ) |
09d56393 | 5900 | intel_hdcp_handle_cp_irq(intel_dp->attached_connector); |
342ac601 R |
5901 | |
5902 | if (val & DP_SINK_SPECIFIC_IRQ) | |
af67009c | 5903 | drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); |
9844bc87 DP |
5904 | } |
5905 | ||
a4fc5ed6 KP |
5906 | /* |
5907 | * According to DP spec | |
5908 | * 5.1.2: | |
5909 | * 1. Read DPCD | |
5910 | * 2. Configure link according to Receiver Capabilities | |
5911 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
5912 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
5913 | * |
5914 | * intel_dp_short_pulse - handles short pulse interrupts | |
5915 | * when full detection is not required. | |
5916 | * Returns %true if short pulse is handled and full detection | |
5917 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 5918 | */ |
39ff747b | 5919 | static bool |
5c9114d0 | 5920 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 5921 | { |
de25eb7f | 5922 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
39ff747b SS |
5923 | u8 old_sink_count = intel_dp->sink_count; |
5924 | bool ret; | |
5b215bcf | 5925 | |
4df6960e SS |
5926 | /* |
5927 | * Clearing compliance test variables to allow capturing | |
5928 | * of values for next automated test request. | |
5929 | */ | |
c1617abc | 5930 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 5931 | |
39ff747b SS |
5932 | /* |
5933 | * Now read the DPCD to see if it's actually running | |
5934 | * If the current value of sink count doesn't match with | |
5935 | * the value that was stored earlier or dpcd read failed | |
5936 | * we need to do full detection | |
5937 | */ | |
5938 | ret = intel_dp_get_dpcd(intel_dp); | |
5939 | ||
5940 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
5941 | /* No need to proceed if we are going to do full detect */ | |
5942 | return false; | |
59cd09e1 JB |
5943 | } |
5944 | ||
9844bc87 | 5945 | intel_dp_check_service_irq(intel_dp); |
a60f0e38 | 5946 | |
82e00d11 HV |
5947 | /* Handle CEC interrupts, if any */ |
5948 | drm_dp_cec_irq(&intel_dp->aux); | |
5949 | ||
c85d200e VS |
5950 | /* defer to the hotplug work for link retraining if needed */ |
5951 | if (intel_dp_needs_link_retrain(intel_dp)) | |
5952 | return false; | |
42e5e657 | 5953 | |
cc3054ff JRS |
5954 | intel_psr_short_pulse(intel_dp); |
5955 | ||
da15f7cb | 5956 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
bdc6114e WK |
5957 | drm_dbg_kms(&dev_priv->drm, |
5958 | "Link Training Compliance Test requested\n"); | |
da15f7cb | 5959 | /* Send a Hotplug Uevent to userspace to start modeset */ |
2f773477 | 5960 | drm_kms_helper_hotplug_event(&dev_priv->drm); |
da15f7cb | 5961 | } |
39ff747b SS |
5962 | |
5963 | return true; | |
a4fc5ed6 | 5964 | } |
a4fc5ed6 | 5965 | |
caf9ab24 | 5966 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 5967 | static enum drm_connector_status |
26d61aad | 5968 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 5969 | { |
af67009c | 5970 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
e393d0d6 | 5971 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
830de422 JN |
5972 | u8 *dpcd = intel_dp->dpcd; |
5973 | u8 type; | |
caf9ab24 | 5974 | |
ad5125d6 ID |
5975 | if (WARN_ON(intel_dp_is_edp(intel_dp))) |
5976 | return connector_status_connected; | |
5977 | ||
e393d0d6 ID |
5978 | if (lspcon->active) |
5979 | lspcon_resume(lspcon); | |
5980 | ||
caf9ab24 AJ |
5981 | if (!intel_dp_get_dpcd(intel_dp)) |
5982 | return connector_status_disconnected; | |
5983 | ||
5984 | /* if there's no downstream port, we're done */ | |
c726ad01 | 5985 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 5986 | return connector_status_connected; |
caf9ab24 AJ |
5987 | |
5988 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
5989 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
5990 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 5991 | |
30d9aa42 SS |
5992 | return intel_dp->sink_count ? |
5993 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
5994 | } |
5995 | ||
c4e3170a VS |
5996 | if (intel_dp_can_mst(intel_dp)) |
5997 | return connector_status_connected; | |
5998 | ||
caf9ab24 | 5999 | /* If no HPD, poke DDC gently */ |
0b99836f | 6000 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 6001 | return connector_status_connected; |
caf9ab24 AJ |
6002 | |
6003 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
6004 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
6005 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
6006 | if (type == DP_DS_PORT_TYPE_VGA || | |
6007 | type == DP_DS_PORT_TYPE_NON_EDID) | |
6008 | return connector_status_unknown; | |
6009 | } else { | |
6010 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
6011 | DP_DWN_STRM_PORT_TYPE_MASK; | |
6012 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
6013 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
6014 | return connector_status_unknown; | |
6015 | } | |
caf9ab24 AJ |
6016 | |
6017 | /* Anything else is out of spec, warn and ignore */ | |
af67009c | 6018 | drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); |
26d61aad | 6019 | return connector_status_disconnected; |
71ba9000 AJ |
6020 | } |
6021 | ||
d410b56d CW |
6022 | static enum drm_connector_status |
6023 | edp_detect(struct intel_dp *intel_dp) | |
6024 | { | |
b93b41af | 6025 | return connector_status_connected; |
d410b56d CW |
6026 | } |
6027 | ||
7533eb4f | 6028 | static bool ibx_digital_port_connected(struct intel_encoder *encoder) |
5eb08b69 | 6029 | { |
7533eb4f | 6030 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b93433cc | 6031 | u32 bit; |
01cb9ea6 | 6032 | |
7533eb4f RV |
6033 | switch (encoder->hpd_pin) { |
6034 | case HPD_PORT_B: | |
0df53b77 JN |
6035 | bit = SDE_PORTB_HOTPLUG; |
6036 | break; | |
7533eb4f | 6037 | case HPD_PORT_C: |
0df53b77 JN |
6038 | bit = SDE_PORTC_HOTPLUG; |
6039 | break; | |
7533eb4f | 6040 | case HPD_PORT_D: |
0df53b77 JN |
6041 | bit = SDE_PORTD_HOTPLUG; |
6042 | break; | |
6043 | default: | |
7533eb4f | 6044 | MISSING_CASE(encoder->hpd_pin); |
0df53b77 JN |
6045 | return false; |
6046 | } | |
6047 | ||
b4e33881 | 6048 | return intel_de_read(dev_priv, SDEISR) & bit; |
0df53b77 JN |
6049 | } |
6050 | ||
7533eb4f | 6051 | static bool cpt_digital_port_connected(struct intel_encoder *encoder) |
0df53b77 | 6052 | { |
7533eb4f | 6053 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0df53b77 JN |
6054 | u32 bit; |
6055 | ||
7533eb4f RV |
6056 | switch (encoder->hpd_pin) { |
6057 | case HPD_PORT_B: | |
0df53b77 JN |
6058 | bit = SDE_PORTB_HOTPLUG_CPT; |
6059 | break; | |
7533eb4f | 6060 | case HPD_PORT_C: |
0df53b77 JN |
6061 | bit = SDE_PORTC_HOTPLUG_CPT; |
6062 | break; | |
7533eb4f | 6063 | case HPD_PORT_D: |
0df53b77 JN |
6064 | bit = SDE_PORTD_HOTPLUG_CPT; |
6065 | break; | |
93e5f0b6 | 6066 | default: |
7533eb4f | 6067 | MISSING_CASE(encoder->hpd_pin); |
93e5f0b6 VS |
6068 | return false; |
6069 | } | |
6070 | ||
b4e33881 | 6071 | return intel_de_read(dev_priv, SDEISR) & bit; |
93e5f0b6 VS |
6072 | } |
6073 | ||
7533eb4f | 6074 | static bool spt_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 6075 | { |
7533eb4f | 6076 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
93e5f0b6 VS |
6077 | u32 bit; |
6078 | ||
7533eb4f RV |
6079 | switch (encoder->hpd_pin) { |
6080 | case HPD_PORT_A: | |
93e5f0b6 VS |
6081 | bit = SDE_PORTA_HOTPLUG_SPT; |
6082 | break; | |
7533eb4f | 6083 | case HPD_PORT_E: |
a78695d3 JN |
6084 | bit = SDE_PORTE_HOTPLUG_SPT; |
6085 | break; | |
0df53b77 | 6086 | default: |
7533eb4f | 6087 | return cpt_digital_port_connected(encoder); |
b93433cc | 6088 | } |
1b469639 | 6089 | |
b4e33881 | 6090 | return intel_de_read(dev_priv, SDEISR) & bit; |
5eb08b69 ZW |
6091 | } |
6092 | ||
7533eb4f | 6093 | static bool g4x_digital_port_connected(struct intel_encoder *encoder) |
a4fc5ed6 | 6094 | { |
7533eb4f | 6095 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c | 6096 | u32 bit; |
5eb08b69 | 6097 | |
7533eb4f RV |
6098 | switch (encoder->hpd_pin) { |
6099 | case HPD_PORT_B: | |
9642c81c JN |
6100 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
6101 | break; | |
7533eb4f | 6102 | case HPD_PORT_C: |
9642c81c JN |
6103 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
6104 | break; | |
7533eb4f | 6105 | case HPD_PORT_D: |
9642c81c JN |
6106 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
6107 | break; | |
6108 | default: | |
7533eb4f | 6109 | MISSING_CASE(encoder->hpd_pin); |
9642c81c JN |
6110 | return false; |
6111 | } | |
6112 | ||
b4e33881 | 6113 | return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; |
9642c81c JN |
6114 | } |
6115 | ||
7533eb4f | 6116 | static bool gm45_digital_port_connected(struct intel_encoder *encoder) |
9642c81c | 6117 | { |
7533eb4f | 6118 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c JN |
6119 | u32 bit; |
6120 | ||
7533eb4f RV |
6121 | switch (encoder->hpd_pin) { |
6122 | case HPD_PORT_B: | |
0780cd36 | 6123 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 6124 | break; |
7533eb4f | 6125 | case HPD_PORT_C: |
0780cd36 | 6126 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 6127 | break; |
7533eb4f | 6128 | case HPD_PORT_D: |
0780cd36 | 6129 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
6130 | break; |
6131 | default: | |
7533eb4f | 6132 | MISSING_CASE(encoder->hpd_pin); |
9642c81c | 6133 | return false; |
a4fc5ed6 KP |
6134 | } |
6135 | ||
b4e33881 | 6136 | return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
6137 | } |
6138 | ||
7533eb4f | 6139 | static bool ilk_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 6140 | { |
7533eb4f RV |
6141 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
6142 | ||
6143 | if (encoder->hpd_pin == HPD_PORT_A) | |
b4e33881 | 6144 | return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG; |
93e5f0b6 | 6145 | else |
7533eb4f | 6146 | return ibx_digital_port_connected(encoder); |
93e5f0b6 VS |
6147 | } |
6148 | ||
7533eb4f | 6149 | static bool snb_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 6150 | { |
7533eb4f RV |
6151 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
6152 | ||
6153 | if (encoder->hpd_pin == HPD_PORT_A) | |
b4e33881 | 6154 | return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG; |
93e5f0b6 | 6155 | else |
7533eb4f | 6156 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
6157 | } |
6158 | ||
7533eb4f | 6159 | static bool ivb_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 6160 | { |
7533eb4f RV |
6161 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
6162 | ||
6163 | if (encoder->hpd_pin == HPD_PORT_A) | |
b4e33881 | 6164 | return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB; |
93e5f0b6 | 6165 | else |
7533eb4f | 6166 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
6167 | } |
6168 | ||
7533eb4f | 6169 | static bool bdw_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 6170 | { |
7533eb4f RV |
6171 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
6172 | ||
6173 | if (encoder->hpd_pin == HPD_PORT_A) | |
b4e33881 | 6174 | return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; |
93e5f0b6 | 6175 | else |
7533eb4f | 6176 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
6177 | } |
6178 | ||
7533eb4f | 6179 | static bool bxt_digital_port_connected(struct intel_encoder *encoder) |
e464bfde | 6180 | { |
7533eb4f | 6181 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e464bfde JN |
6182 | u32 bit; |
6183 | ||
7533eb4f RV |
6184 | switch (encoder->hpd_pin) { |
6185 | case HPD_PORT_A: | |
e464bfde JN |
6186 | bit = BXT_DE_PORT_HP_DDIA; |
6187 | break; | |
7533eb4f | 6188 | case HPD_PORT_B: |
e464bfde JN |
6189 | bit = BXT_DE_PORT_HP_DDIB; |
6190 | break; | |
7533eb4f | 6191 | case HPD_PORT_C: |
e464bfde JN |
6192 | bit = BXT_DE_PORT_HP_DDIC; |
6193 | break; | |
6194 | default: | |
7533eb4f | 6195 | MISSING_CASE(encoder->hpd_pin); |
e464bfde JN |
6196 | return false; |
6197 | } | |
6198 | ||
b4e33881 | 6199 | return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; |
e464bfde JN |
6200 | } |
6201 | ||
3d1e388d MR |
6202 | static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv, |
6203 | enum phy phy) | |
b9fcddab | 6204 | { |
3d1e388d | 6205 | if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) |
b4e33881 | 6206 | return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); |
53448aed | 6207 | |
b4e33881 | 6208 | return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy); |
b9fcddab PZ |
6209 | } |
6210 | ||
9695cde6 | 6211 | static bool icp_digital_port_connected(struct intel_encoder *encoder) |
b9fcddab PZ |
6212 | { |
6213 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 6214 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
d8fe2ab6 | 6215 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
b9fcddab | 6216 | |
d8fe2ab6 | 6217 | if (intel_phy_is_combo(dev_priv, phy)) |
3d1e388d | 6218 | return intel_combo_phy_connected(dev_priv, phy); |
d8fe2ab6 | 6219 | else if (intel_phy_is_tc(dev_priv, phy)) |
bc85328f | 6220 | return intel_tc_port_connected(dig_port); |
c0aa8344 | 6221 | else |
b9fcddab | 6222 | MISSING_CASE(encoder->hpd_pin); |
c0aa8344 MK |
6223 | |
6224 | return false; | |
b9fcddab PZ |
6225 | } |
6226 | ||
7e66bcf2 JN |
6227 | /* |
6228 | * intel_digital_port_connected - is the specified port connected? | |
7533eb4f | 6229 | * @encoder: intel_encoder |
7e66bcf2 | 6230 | * |
39d1e234 PZ |
6231 | * In cases where there's a connector physically connected but it can't be used |
6232 | * by our hardware we also return false, since the rest of the driver should | |
6233 | * pretty much treat the port as disconnected. This is relevant for type-C | |
6234 | * (starting on ICL) where there's ownership involved. | |
6235 | * | |
7533eb4f | 6236 | * Return %true if port is connected, %false otherwise. |
7e66bcf2 | 6237 | */ |
6cfe7ec0 | 6238 | static bool __intel_digital_port_connected(struct intel_encoder *encoder) |
7e66bcf2 | 6239 | { |
7533eb4f RV |
6240 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
6241 | ||
b2ae318a | 6242 | if (HAS_GMCH(dev_priv)) { |
93e5f0b6 | 6243 | if (IS_GM45(dev_priv)) |
7533eb4f | 6244 | return gm45_digital_port_connected(encoder); |
93e5f0b6 | 6245 | else |
7533eb4f | 6246 | return g4x_digital_port_connected(encoder); |
93e5f0b6 VS |
6247 | } |
6248 | ||
9695cde6 MR |
6249 | if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) |
6250 | return icp_digital_port_connected(encoder); | |
6251 | else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) | |
210126bd | 6252 | return spt_digital_port_connected(encoder); |
cc3f90f0 | 6253 | else if (IS_GEN9_LP(dev_priv)) |
7533eb4f | 6254 | return bxt_digital_port_connected(encoder); |
cf819eff | 6255 | else if (IS_GEN(dev_priv, 8)) |
210126bd | 6256 | return bdw_digital_port_connected(encoder); |
cf819eff | 6257 | else if (IS_GEN(dev_priv, 7)) |
210126bd | 6258 | return ivb_digital_port_connected(encoder); |
cf819eff | 6259 | else if (IS_GEN(dev_priv, 6)) |
210126bd | 6260 | return snb_digital_port_connected(encoder); |
cf819eff | 6261 | else if (IS_GEN(dev_priv, 5)) |
210126bd RV |
6262 | return ilk_digital_port_connected(encoder); |
6263 | ||
6264 | MISSING_CASE(INTEL_GEN(dev_priv)); | |
6265 | return false; | |
7e66bcf2 JN |
6266 | } |
6267 | ||
6cfe7ec0 ID |
6268 | bool intel_digital_port_connected(struct intel_encoder *encoder) |
6269 | { | |
6270 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
96ac0813 | 6271 | bool is_connected = false; |
6cfe7ec0 | 6272 | intel_wakeref_t wakeref; |
6cfe7ec0 ID |
6273 | |
6274 | with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) | |
6275 | is_connected = __intel_digital_port_connected(encoder); | |
6276 | ||
6277 | return is_connected; | |
6278 | } | |
6279 | ||
8c241fef | 6280 | static struct edid * |
beb60608 | 6281 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 6282 | { |
beb60608 | 6283 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 6284 | |
9cd300e0 JN |
6285 | /* use cached edid if we have one */ |
6286 | if (intel_connector->edid) { | |
9cd300e0 JN |
6287 | /* invalid edid */ |
6288 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
6289 | return NULL; |
6290 | ||
55e9edeb | 6291 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
6292 | } else |
6293 | return drm_get_edid(&intel_connector->base, | |
6294 | &intel_dp->aux.ddc); | |
6295 | } | |
8c241fef | 6296 | |
beb60608 CW |
6297 | static void |
6298 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
6299 | { | |
6300 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
6301 | struct edid *edid; | |
8c241fef | 6302 | |
f21a2198 | 6303 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
6304 | edid = intel_dp_get_edid(intel_dp); |
6305 | intel_connector->detect_edid = edid; | |
6306 | ||
e6b72c94 | 6307 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
82e00d11 | 6308 | drm_dp_cec_set_edid(&intel_dp->aux, edid); |
0883ce81 | 6309 | intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); |
8c241fef KP |
6310 | } |
6311 | ||
beb60608 CW |
6312 | static void |
6313 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 6314 | { |
beb60608 | 6315 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 6316 | |
82e00d11 | 6317 | drm_dp_cec_unset_edid(&intel_dp->aux); |
beb60608 CW |
6318 | kfree(intel_connector->detect_edid); |
6319 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 6320 | |
beb60608 | 6321 | intel_dp->has_audio = false; |
0883ce81 | 6322 | intel_dp->edid_quirks = 0; |
beb60608 | 6323 | } |
d6f24d0f | 6324 | |
6c5ed5ae | 6325 | static int |
cbfa8ac8 DP |
6326 | intel_dp_detect(struct drm_connector *connector, |
6327 | struct drm_modeset_acquire_ctx *ctx, | |
6328 | bool force) | |
a9756bb5 | 6329 | { |
cbfa8ac8 | 6330 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
43a6d19c | 6331 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
337837ac ID |
6332 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
6333 | struct intel_encoder *encoder = &dig_port->base; | |
a9756bb5 | 6334 | enum drm_connector_status status; |
a9756bb5 | 6335 | |
bdc6114e WK |
6336 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", |
6337 | connector->base.id, connector->name); | |
eb020ca3 PB |
6338 | drm_WARN_ON(&dev_priv->drm, |
6339 | !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); | |
6c5ed5ae | 6340 | |
b93b41af | 6341 | /* Can't disconnect eDP */ |
1853a9da | 6342 | if (intel_dp_is_edp(intel_dp)) |
d410b56d | 6343 | status = edp_detect(intel_dp); |
d5acd97f | 6344 | else if (intel_digital_port_connected(encoder)) |
c555a81d | 6345 | status = intel_dp_detect_dpcd(intel_dp); |
a9756bb5 | 6346 | else |
c555a81d ACO |
6347 | status = connector_status_disconnected; |
6348 | ||
5cb651a7 | 6349 | if (status == connector_status_disconnected) { |
c1617abc | 6350 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
93ac092f | 6351 | memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); |
4df6960e | 6352 | |
0e505a08 | 6353 | if (intel_dp->is_mst) { |
bdc6114e WK |
6354 | drm_dbg_kms(&dev_priv->drm, |
6355 | "MST device may have disappeared %d vs %d\n", | |
6356 | intel_dp->is_mst, | |
6357 | intel_dp->mst_mgr.mst_state); | |
0e505a08 | 6358 | intel_dp->is_mst = false; |
6359 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
6360 | intel_dp->is_mst); | |
6361 | } | |
6362 | ||
c8c8fb33 | 6363 | goto out; |
4df6960e | 6364 | } |
a9756bb5 | 6365 | |
d7e8ef02 | 6366 | if (intel_dp->reset_link_params) { |
540b0b7f JN |
6367 | /* Initial max link lane count */ |
6368 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
f482984a | 6369 | |
540b0b7f JN |
6370 | /* Initial max link rate */ |
6371 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
d7e8ef02 MN |
6372 | |
6373 | intel_dp->reset_link_params = false; | |
6374 | } | |
f482984a | 6375 | |
fe5a66f9 VS |
6376 | intel_dp_print_rates(intel_dp); |
6377 | ||
93ac092f MN |
6378 | /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ |
6379 | if (INTEL_GEN(dev_priv) >= 11) | |
6380 | intel_dp_get_dsc_sink_cap(intel_dp); | |
6381 | ||
c4e3170a VS |
6382 | intel_dp_configure_mst(intel_dp); |
6383 | ||
6384 | if (intel_dp->is_mst) { | |
f21a2198 SS |
6385 | /* |
6386 | * If we are in MST mode then this connector | |
6387 | * won't appear connected or have anything | |
6388 | * with EDID on it | |
6389 | */ | |
0e32b39c DA |
6390 | status = connector_status_disconnected; |
6391 | goto out; | |
f24f6eb9 DP |
6392 | } |
6393 | ||
6394 | /* | |
6395 | * Some external monitors do not signal loss of link synchronization | |
6396 | * with an IRQ_HPD, so force a link status check. | |
6397 | */ | |
47658556 DP |
6398 | if (!intel_dp_is_edp(intel_dp)) { |
6399 | int ret; | |
6400 | ||
6401 | ret = intel_dp_retrain_link(encoder, ctx); | |
6cfe7ec0 | 6402 | if (ret) |
47658556 | 6403 | return ret; |
47658556 | 6404 | } |
0e32b39c | 6405 | |
4df6960e SS |
6406 | /* |
6407 | * Clearing NACK and defer counts to get their exact values | |
6408 | * while reading EDID which are required by Compliance tests | |
6409 | * 4.2.2.4 and 4.2.2.5 | |
6410 | */ | |
6411 | intel_dp->aux.i2c_nack_count = 0; | |
6412 | intel_dp->aux.i2c_defer_count = 0; | |
6413 | ||
beb60608 | 6414 | intel_dp_set_edid(intel_dp); |
cbfa8ac8 DP |
6415 | if (intel_dp_is_edp(intel_dp) || |
6416 | to_intel_connector(connector)->detect_edid) | |
5cb651a7 | 6417 | status = connector_status_connected; |
c8c8fb33 | 6418 | |
9844bc87 | 6419 | intel_dp_check_service_irq(intel_dp); |
09b1eb13 | 6420 | |
c8c8fb33 | 6421 | out: |
5cb651a7 | 6422 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 6423 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 6424 | |
a8ddac7c ID |
6425 | /* |
6426 | * Make sure the refs for power wells enabled during detect are | |
6427 | * dropped to avoid a new detect cycle triggered by HPD polling. | |
6428 | */ | |
6429 | intel_display_power_flush_work(dev_priv); | |
6430 | ||
5cb651a7 | 6431 | return status; |
f21a2198 SS |
6432 | } |
6433 | ||
beb60608 CW |
6434 | static void |
6435 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 6436 | { |
43a6d19c | 6437 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
337837ac ID |
6438 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
6439 | struct intel_encoder *intel_encoder = &dig_port->base; | |
25f78f58 | 6440 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
337837ac ID |
6441 | enum intel_display_power_domain aux_domain = |
6442 | intel_aux_power_domain(dig_port); | |
0e6e0be4 | 6443 | intel_wakeref_t wakeref; |
a4fc5ed6 | 6444 | |
bdc6114e WK |
6445 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", |
6446 | connector->base.id, connector->name); | |
beb60608 | 6447 | intel_dp_unset_edid(intel_dp); |
a4fc5ed6 | 6448 | |
beb60608 CW |
6449 | if (connector->status != connector_status_connected) |
6450 | return; | |
671dedd2 | 6451 | |
0e6e0be4 | 6452 | wakeref = intel_display_power_get(dev_priv, aux_domain); |
beb60608 CW |
6453 | |
6454 | intel_dp_set_edid(intel_dp); | |
6455 | ||
0e6e0be4 | 6456 | intel_display_power_put(dev_priv, aux_domain, wakeref); |
beb60608 CW |
6457 | } |
6458 | ||
6459 | static int intel_dp_get_modes(struct drm_connector *connector) | |
6460 | { | |
6461 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
6462 | struct edid *edid; | |
6463 | ||
6464 | edid = intel_connector->detect_edid; | |
6465 | if (edid) { | |
6466 | int ret = intel_connector_update_modes(connector, edid); | |
6467 | if (ret) | |
6468 | return ret; | |
6469 | } | |
32f9d658 | 6470 | |
f8779fda | 6471 | /* if eDP has no EDID, fall back to fixed mode */ |
43a6d19c | 6472 | if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) && |
beb60608 | 6473 | intel_connector->panel.fixed_mode) { |
f8779fda | 6474 | struct drm_display_mode *mode; |
beb60608 CW |
6475 | |
6476 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 6477 | intel_connector->panel.fixed_mode); |
f8779fda | 6478 | if (mode) { |
32f9d658 ZW |
6479 | drm_mode_probed_add(connector, mode); |
6480 | return 1; | |
6481 | } | |
6482 | } | |
beb60608 | 6483 | |
32f9d658 | 6484 | return 0; |
a4fc5ed6 KP |
6485 | } |
6486 | ||
7a418e34 CW |
6487 | static int |
6488 | intel_dp_connector_register(struct drm_connector *connector) | |
6489 | { | |
af67009c | 6490 | struct drm_i915_private *i915 = to_i915(connector->dev); |
43a6d19c | 6491 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
1ebaa0b9 CW |
6492 | int ret; |
6493 | ||
6494 | ret = intel_connector_register(connector); | |
6495 | if (ret) | |
6496 | return ret; | |
7a418e34 | 6497 | |
af67009c JN |
6498 | drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", |
6499 | intel_dp->aux.name, connector->kdev->kobj.name); | |
7a418e34 CW |
6500 | |
6501 | intel_dp->aux.dev = connector->kdev; | |
82e00d11 HV |
6502 | ret = drm_dp_aux_register(&intel_dp->aux); |
6503 | if (!ret) | |
ae85b0df | 6504 | drm_dp_cec_register_connector(&intel_dp->aux, connector); |
82e00d11 | 6505 | return ret; |
7a418e34 CW |
6506 | } |
6507 | ||
c191eca1 CW |
6508 | static void |
6509 | intel_dp_connector_unregister(struct drm_connector *connector) | |
6510 | { | |
43a6d19c | 6511 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
82e00d11 HV |
6512 | |
6513 | drm_dp_cec_unregister_connector(&intel_dp->aux); | |
6514 | drm_dp_aux_unregister(&intel_dp->aux); | |
c191eca1 CW |
6515 | intel_connector_unregister(connector); |
6516 | } | |
6517 | ||
f6bff60e | 6518 | void intel_dp_encoder_flush_work(struct drm_encoder *encoder) |
24d05927 | 6519 | { |
b7d02c3a | 6520 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder)); |
da63a9f2 | 6521 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
24d05927 | 6522 | |
0e32b39c | 6523 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
1853a9da | 6524 | if (intel_dp_is_edp(intel_dp)) { |
69d93820 CW |
6525 | intel_wakeref_t wakeref; |
6526 | ||
bd943159 | 6527 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
951468f3 VS |
6528 | /* |
6529 | * vdd might still be enabled do to the delayed vdd off. | |
6530 | * Make sure vdd is actually turned off here. | |
6531 | */ | |
69d93820 CW |
6532 | with_pps_lock(intel_dp, wakeref) |
6533 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 6534 | |
01527b31 CT |
6535 | if (intel_dp->edp_notifier.notifier_call) { |
6536 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
6537 | intel_dp->edp_notifier.notifier_call = NULL; | |
6538 | } | |
bd943159 | 6539 | } |
99681886 CW |
6540 | |
6541 | intel_dp_aux_fini(intel_dp); | |
f6bff60e ID |
6542 | } |
6543 | ||
6544 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) | |
6545 | { | |
6546 | intel_dp_encoder_flush_work(encoder); | |
99681886 | 6547 | |
c8bd0e49 | 6548 | drm_encoder_cleanup(encoder); |
b7d02c3a | 6549 | kfree(enc_to_dig_port(to_intel_encoder(encoder))); |
24d05927 DV |
6550 | } |
6551 | ||
bf93ba67 | 6552 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b | 6553 | { |
b7d02c3a | 6554 | struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); |
69d93820 | 6555 | intel_wakeref_t wakeref; |
07f9cd0b | 6556 | |
1853a9da | 6557 | if (!intel_dp_is_edp(intel_dp)) |
07f9cd0b ID |
6558 | return; |
6559 | ||
951468f3 VS |
6560 | /* |
6561 | * vdd might still be enabled do to the delayed vdd off. | |
6562 | * Make sure vdd is actually turned off here. | |
6563 | */ | |
afa4e53a | 6564 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
69d93820 CW |
6565 | with_pps_lock(intel_dp, wakeref) |
6566 | edp_panel_vdd_off_sync(intel_dp); | |
07f9cd0b ID |
6567 | } |
6568 | ||
cf9cb35f R |
6569 | static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) |
6570 | { | |
6571 | long ret; | |
6572 | ||
6573 | #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) | |
6574 | ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, | |
6575 | msecs_to_jiffies(timeout)); | |
6576 | ||
6577 | if (!ret) | |
6578 | DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); | |
6579 | } | |
6580 | ||
20f24d77 SP |
6581 | static |
6582 | int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
6583 | u8 *an) | |
6584 | { | |
af67009c | 6585 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
b7d02c3a | 6586 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base)); |
32078b72 VS |
6587 | static const struct drm_dp_aux_msg msg = { |
6588 | .request = DP_AUX_NATIVE_WRITE, | |
6589 | .address = DP_AUX_HDCP_AKSV, | |
6590 | .size = DRM_HDCP_KSV_LEN, | |
6591 | }; | |
830de422 | 6592 | u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0; |
20f24d77 SP |
6593 | ssize_t dpcd_ret; |
6594 | int ret; | |
6595 | ||
6596 | /* Output An first, that's easy */ | |
6597 | dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, | |
6598 | an, DRM_HDCP_AN_LEN); | |
6599 | if (dpcd_ret != DRM_HDCP_AN_LEN) { | |
af67009c JN |
6600 | drm_dbg_kms(&i915->drm, |
6601 | "Failed to write An over DP/AUX (%zd)\n", | |
6602 | dpcd_ret); | |
20f24d77 SP |
6603 | return dpcd_ret >= 0 ? -EIO : dpcd_ret; |
6604 | } | |
6605 | ||
6606 | /* | |
6607 | * Since Aksv is Oh-So-Secret, we can't access it in software. So in | |
6608 | * order to get it on the wire, we need to create the AUX header as if | |
6609 | * we were writing the data, and then tickle the hardware to output the | |
6610 | * data once the header is sent out. | |
6611 | */ | |
32078b72 | 6612 | intel_dp_aux_header(txbuf, &msg); |
20f24d77 | 6613 | |
32078b72 | 6614 | ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size, |
8159c796 VS |
6615 | rxbuf, sizeof(rxbuf), |
6616 | DP_AUX_CH_CTL_AUX_AKSV_SELECT); | |
20f24d77 | 6617 | if (ret < 0) { |
af67009c JN |
6618 | drm_dbg_kms(&i915->drm, |
6619 | "Write Aksv over DP/AUX failed (%d)\n", ret); | |
20f24d77 SP |
6620 | return ret; |
6621 | } else if (ret == 0) { | |
af67009c | 6622 | drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n"); |
20f24d77 SP |
6623 | return -EIO; |
6624 | } | |
6625 | ||
6626 | reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK; | |
4cf74aaf | 6627 | if (reply != DP_AUX_NATIVE_REPLY_ACK) { |
af67009c JN |
6628 | drm_dbg_kms(&i915->drm, |
6629 | "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n", | |
6630 | reply); | |
4cf74aaf R |
6631 | return -EIO; |
6632 | } | |
6633 | return 0; | |
20f24d77 SP |
6634 | } |
6635 | ||
6636 | static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
6637 | u8 *bksv) | |
6638 | { | |
af67009c | 6639 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 | 6640 | ssize_t ret; |
af67009c | 6641 | |
20f24d77 SP |
6642 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, |
6643 | DRM_HDCP_KSV_LEN); | |
6644 | if (ret != DRM_HDCP_KSV_LEN) { | |
af67009c JN |
6645 | drm_dbg_kms(&i915->drm, |
6646 | "Read Bksv from DP/AUX failed (%zd)\n", ret); | |
20f24d77 SP |
6647 | return ret >= 0 ? -EIO : ret; |
6648 | } | |
6649 | return 0; | |
6650 | } | |
6651 | ||
6652 | static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
6653 | u8 *bstatus) | |
6654 | { | |
af67009c | 6655 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 | 6656 | ssize_t ret; |
af67009c | 6657 | |
20f24d77 SP |
6658 | /* |
6659 | * For some reason the HDMI and DP HDCP specs call this register | |
6660 | * definition by different names. In the HDMI spec, it's called BSTATUS, | |
6661 | * but in DP it's called BINFO. | |
6662 | */ | |
6663 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, | |
6664 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
6665 | if (ret != DRM_HDCP_BSTATUS_LEN) { | |
af67009c JN |
6666 | drm_dbg_kms(&i915->drm, |
6667 | "Read bstatus from DP/AUX failed (%zd)\n", ret); | |
20f24d77 SP |
6668 | return ret >= 0 ? -EIO : ret; |
6669 | } | |
6670 | return 0; | |
6671 | } | |
6672 | ||
6673 | static | |
791a98dd R |
6674 | int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, |
6675 | u8 *bcaps) | |
20f24d77 | 6676 | { |
af67009c | 6677 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 | 6678 | ssize_t ret; |
791a98dd | 6679 | |
20f24d77 | 6680 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, |
791a98dd | 6681 | bcaps, 1); |
20f24d77 | 6682 | if (ret != 1) { |
af67009c JN |
6683 | drm_dbg_kms(&i915->drm, |
6684 | "Read bcaps from DP/AUX failed (%zd)\n", ret); | |
20f24d77 SP |
6685 | return ret >= 0 ? -EIO : ret; |
6686 | } | |
791a98dd R |
6687 | |
6688 | return 0; | |
6689 | } | |
6690 | ||
6691 | static | |
6692 | int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
6693 | bool *repeater_present) | |
6694 | { | |
6695 | ssize_t ret; | |
6696 | u8 bcaps; | |
6697 | ||
6698 | ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); | |
6699 | if (ret) | |
6700 | return ret; | |
6701 | ||
20f24d77 SP |
6702 | *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; |
6703 | return 0; | |
6704 | } | |
6705 | ||
6706 | static | |
6707 | int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
6708 | u8 *ri_prime) | |
6709 | { | |
af67009c | 6710 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 | 6711 | ssize_t ret; |
af67009c | 6712 | |
20f24d77 SP |
6713 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, |
6714 | ri_prime, DRM_HDCP_RI_LEN); | |
6715 | if (ret != DRM_HDCP_RI_LEN) { | |
af67009c JN |
6716 | drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", |
6717 | ret); | |
20f24d77 SP |
6718 | return ret >= 0 ? -EIO : ret; |
6719 | } | |
6720 | return 0; | |
6721 | } | |
6722 | ||
6723 | static | |
6724 | int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
6725 | bool *ksv_ready) | |
6726 | { | |
af67009c | 6727 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 SP |
6728 | ssize_t ret; |
6729 | u8 bstatus; | |
af67009c | 6730 | |
20f24d77 SP |
6731 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, |
6732 | &bstatus, 1); | |
6733 | if (ret != 1) { | |
af67009c JN |
6734 | drm_dbg_kms(&i915->drm, |
6735 | "Read bstatus from DP/AUX failed (%zd)\n", ret); | |
20f24d77 SP |
6736 | return ret >= 0 ? -EIO : ret; |
6737 | } | |
6738 | *ksv_ready = bstatus & DP_BSTATUS_READY; | |
6739 | return 0; | |
6740 | } | |
6741 | ||
6742 | static | |
6743 | int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
6744 | int num_downstream, u8 *ksv_fifo) | |
6745 | { | |
af67009c | 6746 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 SP |
6747 | ssize_t ret; |
6748 | int i; | |
6749 | ||
6750 | /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ | |
6751 | for (i = 0; i < num_downstream; i += 3) { | |
6752 | size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; | |
6753 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6754 | DP_AUX_HDCP_KSV_FIFO, | |
6755 | ksv_fifo + i * DRM_HDCP_KSV_LEN, | |
6756 | len); | |
6757 | if (ret != len) { | |
af67009c JN |
6758 | drm_dbg_kms(&i915->drm, |
6759 | "Read ksv[%d] from DP/AUX failed (%zd)\n", | |
6760 | i, ret); | |
20f24d77 SP |
6761 | return ret >= 0 ? -EIO : ret; |
6762 | } | |
6763 | } | |
6764 | return 0; | |
6765 | } | |
6766 | ||
6767 | static | |
6768 | int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
6769 | int i, u32 *part) | |
6770 | { | |
af67009c | 6771 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 SP |
6772 | ssize_t ret; |
6773 | ||
6774 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
6775 | return -EINVAL; | |
6776 | ||
6777 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6778 | DP_AUX_HDCP_V_PRIME(i), part, | |
6779 | DRM_HDCP_V_PRIME_PART_LEN); | |
6780 | if (ret != DRM_HDCP_V_PRIME_PART_LEN) { | |
af67009c JN |
6781 | drm_dbg_kms(&i915->drm, |
6782 | "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); | |
20f24d77 SP |
6783 | return ret >= 0 ? -EIO : ret; |
6784 | } | |
6785 | return 0; | |
6786 | } | |
6787 | ||
6788 | static | |
6789 | int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
6790 | bool enable) | |
6791 | { | |
6792 | /* Not used for single stream DisplayPort setups */ | |
6793 | return 0; | |
6794 | } | |
6795 | ||
6796 | static | |
6797 | bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
6798 | { | |
af67009c | 6799 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
20f24d77 SP |
6800 | ssize_t ret; |
6801 | u8 bstatus; | |
b7fc1a9b | 6802 | |
20f24d77 SP |
6803 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, |
6804 | &bstatus, 1); | |
6805 | if (ret != 1) { | |
af67009c JN |
6806 | drm_dbg_kms(&i915->drm, |
6807 | "Read bstatus from DP/AUX failed (%zd)\n", ret); | |
b7fc1a9b | 6808 | return false; |
20f24d77 | 6809 | } |
b7fc1a9b | 6810 | |
20f24d77 SP |
6811 | return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); |
6812 | } | |
6813 | ||
791a98dd R |
6814 | static |
6815 | int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, | |
6816 | bool *hdcp_capable) | |
6817 | { | |
6818 | ssize_t ret; | |
6819 | u8 bcaps; | |
6820 | ||
6821 | ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); | |
6822 | if (ret) | |
6823 | return ret; | |
6824 | ||
6825 | *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; | |
6826 | return 0; | |
6827 | } | |
6828 | ||
238d3a9e R |
6829 | struct hdcp2_dp_errata_stream_type { |
6830 | u8 msg_id; | |
6831 | u8 stream_type; | |
6832 | } __packed; | |
6833 | ||
57bf7f43 | 6834 | struct hdcp2_dp_msg_data { |
238d3a9e R |
6835 | u8 msg_id; |
6836 | u32 offset; | |
6837 | bool msg_detectable; | |
6838 | u32 timeout; | |
6839 | u32 timeout2; /* Added for non_paired situation */ | |
57bf7f43 JN |
6840 | }; |
6841 | ||
e8465e1c | 6842 | static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { |
57bf7f43 JN |
6843 | { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 }, |
6844 | { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, | |
6845 | false, HDCP_2_2_CERT_TIMEOUT_MS, 0 }, | |
6846 | { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, | |
6847 | false, 0, 0 }, | |
6848 | { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, | |
6849 | false, 0, 0 }, | |
6850 | { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, | |
6851 | true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, | |
6852 | HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS }, | |
6853 | { HDCP_2_2_AKE_SEND_PAIRING_INFO, | |
6854 | DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, | |
6855 | HDCP_2_2_PAIRING_TIMEOUT_MS, 0 }, | |
6856 | { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 }, | |
6857 | { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, | |
6858 | false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 }, | |
6859 | { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, | |
6860 | 0, 0 }, | |
6861 | { HDCP_2_2_REP_SEND_RECVID_LIST, | |
6862 | DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, | |
6863 | HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 }, | |
6864 | { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, | |
6865 | 0, 0 }, | |
6866 | { HDCP_2_2_REP_STREAM_MANAGE, | |
6867 | DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, | |
6868 | 0, 0 }, | |
6869 | { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, | |
6870 | false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 }, | |
238d3a9e R |
6871 | /* local define to shovel this through the write_2_2 interface */ |
6872 | #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 | |
57bf7f43 JN |
6873 | { HDCP_2_2_ERRATA_DP_STREAM_TYPE, |
6874 | DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, | |
6875 | 0, 0 }, | |
6876 | }; | |
238d3a9e | 6877 | |
81b55ef1 JN |
6878 | static int |
6879 | intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, | |
6880 | u8 *rx_status) | |
238d3a9e | 6881 | { |
af67009c | 6882 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
238d3a9e R |
6883 | ssize_t ret; |
6884 | ||
6885 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
6886 | DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, | |
6887 | HDCP_2_2_DP_RXSTATUS_LEN); | |
6888 | if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { | |
af67009c JN |
6889 | drm_dbg_kms(&i915->drm, |
6890 | "Read bstatus from DP/AUX failed (%zd)\n", ret); | |
238d3a9e R |
6891 | return ret >= 0 ? -EIO : ret; |
6892 | } | |
6893 | ||
6894 | return 0; | |
6895 | } | |
6896 | ||
6897 | static | |
6898 | int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, | |
6899 | u8 msg_id, bool *msg_ready) | |
6900 | { | |
6901 | u8 rx_status; | |
6902 | int ret; | |
6903 | ||
6904 | *msg_ready = false; | |
6905 | ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); | |
6906 | if (ret < 0) | |
6907 | return ret; | |
6908 | ||
6909 | switch (msg_id) { | |
6910 | case HDCP_2_2_AKE_SEND_HPRIME: | |
6911 | if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) | |
6912 | *msg_ready = true; | |
6913 | break; | |
6914 | case HDCP_2_2_AKE_SEND_PAIRING_INFO: | |
6915 | if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) | |
6916 | *msg_ready = true; | |
6917 | break; | |
6918 | case HDCP_2_2_REP_SEND_RECVID_LIST: | |
6919 | if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) | |
6920 | *msg_ready = true; | |
6921 | break; | |
6922 | default: | |
6923 | DRM_ERROR("Unidentified msg_id: %d\n", msg_id); | |
6924 | return -EINVAL; | |
6925 | } | |
6926 | ||
6927 | return 0; | |
6928 | } | |
6929 | ||
6930 | static ssize_t | |
6931 | intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, | |
e8465e1c | 6932 | const struct hdcp2_dp_msg_data *hdcp2_msg_data) |
238d3a9e | 6933 | { |
af67009c | 6934 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
238d3a9e R |
6935 | struct intel_dp *dp = &intel_dig_port->dp; |
6936 | struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; | |
6937 | u8 msg_id = hdcp2_msg_data->msg_id; | |
6938 | int ret, timeout; | |
6939 | bool msg_ready = false; | |
6940 | ||
6941 | if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) | |
6942 | timeout = hdcp2_msg_data->timeout2; | |
6943 | else | |
6944 | timeout = hdcp2_msg_data->timeout; | |
6945 | ||
6946 | /* | |
6947 | * There is no way to detect the CERT, LPRIME and STREAM_READY | |
6948 | * availability. So Wait for timeout and read the msg. | |
6949 | */ | |
6950 | if (!hdcp2_msg_data->msg_detectable) { | |
6951 | mdelay(timeout); | |
6952 | ret = 0; | |
6953 | } else { | |
cf9cb35f R |
6954 | /* |
6955 | * As we want to check the msg availability at timeout, Ignoring | |
6956 | * the timeout at wait for CP_IRQ. | |
6957 | */ | |
6958 | intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); | |
6959 | ret = hdcp2_detect_msg_availability(intel_dig_port, | |
6960 | msg_id, &msg_ready); | |
238d3a9e R |
6961 | if (!msg_ready) |
6962 | ret = -ETIMEDOUT; | |
6963 | } | |
6964 | ||
6965 | if (ret) | |
af67009c JN |
6966 | drm_dbg_kms(&i915->drm, |
6967 | "msg_id %d, ret %d, timeout(mSec): %d\n", | |
6968 | hdcp2_msg_data->msg_id, ret, timeout); | |
238d3a9e R |
6969 | |
6970 | return ret; | |
6971 | } | |
6972 | ||
e8465e1c | 6973 | static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) |
238d3a9e R |
6974 | { |
6975 | int i; | |
6976 | ||
3be3a877 JN |
6977 | for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) |
6978 | if (hdcp2_dp_msg_data[i].msg_id == msg_id) | |
6979 | return &hdcp2_dp_msg_data[i]; | |
238d3a9e R |
6980 | |
6981 | return NULL; | |
6982 | } | |
6983 | ||
6984 | static | |
6985 | int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, | |
6986 | void *buf, size_t size) | |
6987 | { | |
cf9cb35f R |
6988 | struct intel_dp *dp = &intel_dig_port->dp; |
6989 | struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; | |
238d3a9e R |
6990 | unsigned int offset; |
6991 | u8 *byte = buf; | |
6992 | ssize_t ret, bytes_to_write, len; | |
e8465e1c | 6993 | const struct hdcp2_dp_msg_data *hdcp2_msg_data; |
238d3a9e R |
6994 | |
6995 | hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); | |
6996 | if (!hdcp2_msg_data) | |
6997 | return -EINVAL; | |
6998 | ||
6999 | offset = hdcp2_msg_data->offset; | |
7000 | ||
7001 | /* No msg_id in DP HDCP2.2 msgs */ | |
7002 | bytes_to_write = size - 1; | |
7003 | byte++; | |
7004 | ||
cf9cb35f R |
7005 | hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); |
7006 | ||
238d3a9e R |
7007 | while (bytes_to_write) { |
7008 | len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? | |
7009 | DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; | |
7010 | ||
7011 | ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, | |
7012 | offset, (void *)byte, len); | |
7013 | if (ret < 0) | |
7014 | return ret; | |
7015 | ||
7016 | bytes_to_write -= ret; | |
7017 | byte += ret; | |
7018 | offset += ret; | |
7019 | } | |
7020 | ||
7021 | return size; | |
7022 | } | |
7023 | ||
7024 | static | |
7025 | ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) | |
7026 | { | |
7027 | u8 rx_info[HDCP_2_2_RXINFO_LEN]; | |
7028 | u32 dev_cnt; | |
7029 | ssize_t ret; | |
7030 | ||
7031 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
7032 | DP_HDCP_2_2_REG_RXINFO_OFFSET, | |
7033 | (void *)rx_info, HDCP_2_2_RXINFO_LEN); | |
7034 | if (ret != HDCP_2_2_RXINFO_LEN) | |
7035 | return ret >= 0 ? -EIO : ret; | |
7036 | ||
7037 | dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | | |
7038 | HDCP_2_2_DEV_COUNT_LO(rx_info[1])); | |
7039 | ||
7040 | if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) | |
7041 | dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; | |
7042 | ||
7043 | ret = sizeof(struct hdcp2_rep_send_receiverid_list) - | |
7044 | HDCP_2_2_RECEIVER_IDS_MAX_LEN + | |
7045 | (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); | |
7046 | ||
7047 | return ret; | |
7048 | } | |
7049 | ||
7050 | static | |
7051 | int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, | |
7052 | u8 msg_id, void *buf, size_t size) | |
7053 | { | |
af67009c | 7054 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
238d3a9e R |
7055 | unsigned int offset; |
7056 | u8 *byte = buf; | |
7057 | ssize_t ret, bytes_to_recv, len; | |
e8465e1c | 7058 | const struct hdcp2_dp_msg_data *hdcp2_msg_data; |
238d3a9e R |
7059 | |
7060 | hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); | |
7061 | if (!hdcp2_msg_data) | |
7062 | return -EINVAL; | |
7063 | offset = hdcp2_msg_data->offset; | |
7064 | ||
7065 | ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); | |
7066 | if (ret < 0) | |
7067 | return ret; | |
7068 | ||
7069 | if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { | |
7070 | ret = get_receiver_id_list_size(intel_dig_port); | |
7071 | if (ret < 0) | |
7072 | return ret; | |
7073 | ||
7074 | size = ret; | |
7075 | } | |
7076 | bytes_to_recv = size - 1; | |
7077 | ||
7078 | /* DP adaptation msgs has no msg_id */ | |
7079 | byte++; | |
7080 | ||
7081 | while (bytes_to_recv) { | |
7082 | len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? | |
7083 | DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; | |
7084 | ||
7085 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, | |
7086 | (void *)byte, len); | |
7087 | if (ret < 0) { | |
af67009c JN |
7088 | drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", |
7089 | msg_id, ret); | |
238d3a9e R |
7090 | return ret; |
7091 | } | |
7092 | ||
7093 | bytes_to_recv -= ret; | |
7094 | byte += ret; | |
7095 | offset += ret; | |
7096 | } | |
7097 | byte = buf; | |
7098 | *byte = msg_id; | |
7099 | ||
7100 | return size; | |
7101 | } | |
7102 | ||
7103 | static | |
7104 | int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, | |
7105 | bool is_repeater, u8 content_type) | |
7106 | { | |
391615d9 | 7107 | int ret; |
238d3a9e R |
7108 | struct hdcp2_dp_errata_stream_type stream_type_msg; |
7109 | ||
7110 | if (is_repeater) | |
7111 | return 0; | |
7112 | ||
7113 | /* | |
7114 | * Errata for DP: As Stream type is used for encryption, Receiver | |
7115 | * should be communicated with stream type for the decryption of the | |
7116 | * content. | |
7117 | * Repeater will be communicated with stream type as a part of it's | |
7118 | * auth later in time. | |
7119 | */ | |
7120 | stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; | |
7121 | stream_type_msg.stream_type = content_type; | |
7122 | ||
391615d9 | 7123 | ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, |
238d3a9e | 7124 | sizeof(stream_type_msg)); |
391615d9 AG |
7125 | |
7126 | return ret < 0 ? ret : 0; | |
7127 | ||
238d3a9e R |
7128 | } |
7129 | ||
7130 | static | |
7131 | int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) | |
7132 | { | |
7133 | u8 rx_status; | |
7134 | int ret; | |
7135 | ||
7136 | ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); | |
7137 | if (ret) | |
7138 | return ret; | |
7139 | ||
7140 | if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) | |
7141 | ret = HDCP_REAUTH_REQUEST; | |
7142 | else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) | |
7143 | ret = HDCP_LINK_INTEGRITY_FAILURE; | |
7144 | else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) | |
7145 | ret = HDCP_TOPOLOGY_CHANGE; | |
7146 | ||
7147 | return ret; | |
7148 | } | |
7149 | ||
7150 | static | |
7151 | int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, | |
7152 | bool *capable) | |
7153 | { | |
7154 | u8 rx_caps[3]; | |
7155 | int ret; | |
7156 | ||
7157 | *capable = false; | |
7158 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
7159 | DP_HDCP_2_2_REG_RX_CAPS_OFFSET, | |
7160 | rx_caps, HDCP_2_2_RXCAPS_LEN); | |
7161 | if (ret != HDCP_2_2_RXCAPS_LEN) | |
7162 | return ret >= 0 ? -EIO : ret; | |
7163 | ||
7164 | if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && | |
7165 | HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) | |
7166 | *capable = true; | |
7167 | ||
7168 | return 0; | |
7169 | } | |
7170 | ||
20f24d77 SP |
7171 | static const struct intel_hdcp_shim intel_dp_hdcp_shim = { |
7172 | .write_an_aksv = intel_dp_hdcp_write_an_aksv, | |
7173 | .read_bksv = intel_dp_hdcp_read_bksv, | |
7174 | .read_bstatus = intel_dp_hdcp_read_bstatus, | |
7175 | .repeater_present = intel_dp_hdcp_repeater_present, | |
7176 | .read_ri_prime = intel_dp_hdcp_read_ri_prime, | |
7177 | .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, | |
7178 | .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, | |
7179 | .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, | |
7180 | .toggle_signalling = intel_dp_hdcp_toggle_signalling, | |
7181 | .check_link = intel_dp_hdcp_check_link, | |
791a98dd | 7182 | .hdcp_capable = intel_dp_hdcp_capable, |
238d3a9e R |
7183 | .write_2_2_msg = intel_dp_hdcp2_write_msg, |
7184 | .read_2_2_msg = intel_dp_hdcp2_read_msg, | |
7185 | .config_stream_type = intel_dp_hdcp2_config_stream_type, | |
7186 | .check_2_2_link = intel_dp_hdcp2_check_link, | |
7187 | .hdcp_2_2_capable = intel_dp_hdcp2_capable, | |
7188 | .protocol = HDCP_PROTOCOL_DP, | |
20f24d77 SP |
7189 | }; |
7190 | ||
49e6bc51 VS |
7191 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
7192 | { | |
de25eb7f | 7193 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
337837ac | 7194 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
49e6bc51 VS |
7195 | |
7196 | lockdep_assert_held(&dev_priv->pps_mutex); | |
7197 | ||
7198 | if (!edp_have_panel_vdd(intel_dp)) | |
7199 | return; | |
7200 | ||
7201 | /* | |
7202 | * The VDD bit needs a power domain reference, so if the bit is | |
7203 | * already enabled when we boot or resume, grab this reference and | |
7204 | * schedule a vdd off, so we don't hold on to the reference | |
7205 | * indefinitely. | |
7206 | */ | |
bdc6114e WK |
7207 | drm_dbg_kms(&dev_priv->drm, |
7208 | "VDD left on by BIOS, adjusting state tracking\n"); | |
337837ac | 7209 | intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); |
49e6bc51 VS |
7210 | |
7211 | edp_panel_vdd_schedule_off(intel_dp); | |
7212 | } | |
7213 | ||
9f2bdb00 VS |
7214 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
7215 | { | |
de25eb7f | 7216 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
59b74c49 VS |
7217 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
7218 | enum pipe pipe; | |
9f2bdb00 | 7219 | |
59b74c49 VS |
7220 | if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg, |
7221 | encoder->port, &pipe)) | |
7222 | return pipe; | |
9f2bdb00 | 7223 | |
59b74c49 | 7224 | return INVALID_PIPE; |
9f2bdb00 VS |
7225 | } |
7226 | ||
bf93ba67 | 7227 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 7228 | { |
64989ca4 | 7229 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
b7d02c3a | 7230 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); |
dd75f6dd | 7231 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
69d93820 | 7232 | intel_wakeref_t wakeref; |
64989ca4 VS |
7233 | |
7234 | if (!HAS_DDI(dev_priv)) | |
b4e33881 | 7235 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); |
49e6bc51 | 7236 | |
dd75f6dd | 7237 | if (lspcon->active) |
910530c0 SS |
7238 | lspcon_resume(lspcon); |
7239 | ||
d7e8ef02 MN |
7240 | intel_dp->reset_link_params = true; |
7241 | ||
b4c7ea63 ID |
7242 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
7243 | !intel_dp_is_edp(intel_dp)) | |
7244 | return; | |
7245 | ||
69d93820 CW |
7246 | with_pps_lock(intel_dp, wakeref) { |
7247 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
7248 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
49e6bc51 | 7249 | |
69d93820 CW |
7250 | if (intel_dp_is_edp(intel_dp)) { |
7251 | /* | |
7252 | * Reinit the power sequencer, in case BIOS did | |
7253 | * something nasty with it. | |
7254 | */ | |
7255 | intel_dp_pps_init(intel_dp); | |
7256 | intel_edp_panel_vdd_sanitize(intel_dp); | |
7257 | } | |
9f2bdb00 | 7258 | } |
6d93c0c4 ID |
7259 | } |
7260 | ||
e24bcd34 MN |
7261 | static int intel_modeset_tile_group(struct intel_atomic_state *state, |
7262 | int tile_group_id) | |
7263 | { | |
7264 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
7265 | struct drm_connector_list_iter conn_iter; | |
7266 | struct drm_connector *connector; | |
7267 | int ret = 0; | |
7268 | ||
7269 | drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); | |
7270 | drm_for_each_connector_iter(connector, &conn_iter) { | |
7271 | struct drm_connector_state *conn_state; | |
7272 | struct intel_crtc_state *crtc_state; | |
7273 | struct intel_crtc *crtc; | |
7274 | ||
7275 | if (!connector->has_tile || | |
7276 | connector->tile_group->id != tile_group_id) | |
7277 | continue; | |
7278 | ||
7279 | conn_state = drm_atomic_get_connector_state(&state->base, | |
7280 | connector); | |
7281 | if (IS_ERR(conn_state)) { | |
7282 | ret = PTR_ERR(conn_state); | |
7283 | break; | |
7284 | } | |
7285 | ||
7286 | crtc = to_intel_crtc(conn_state->crtc); | |
7287 | ||
7288 | if (!crtc) | |
7289 | continue; | |
7290 | ||
7291 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); | |
7292 | crtc_state->uapi.mode_changed = true; | |
7293 | ||
7294 | ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); | |
7295 | if (ret) | |
7296 | break; | |
7297 | } | |
b7079cbd | 7298 | drm_connector_list_iter_end(&conn_iter); |
e24bcd34 MN |
7299 | |
7300 | return ret; | |
7301 | } | |
7302 | ||
7303 | static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) | |
7304 | { | |
7305 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
7306 | struct intel_crtc *crtc; | |
7307 | ||
7308 | if (transcoders == 0) | |
7309 | return 0; | |
7310 | ||
7311 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
7312 | struct intel_crtc_state *crtc_state; | |
7313 | int ret; | |
7314 | ||
7315 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
7316 | if (IS_ERR(crtc_state)) | |
7317 | return PTR_ERR(crtc_state); | |
7318 | ||
7319 | if (!crtc_state->hw.enable) | |
7320 | continue; | |
7321 | ||
7322 | if (!(transcoders & BIT(crtc_state->cpu_transcoder))) | |
7323 | continue; | |
7324 | ||
7325 | crtc_state->uapi.mode_changed = true; | |
7326 | ||
7327 | ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); | |
7328 | if (ret) | |
7329 | return ret; | |
7330 | ||
7331 | ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); | |
7332 | if (ret) | |
7333 | return ret; | |
7334 | ||
7335 | transcoders &= ~BIT(crtc_state->cpu_transcoder); | |
7336 | } | |
7337 | ||
eb020ca3 | 7338 | drm_WARN_ON(&dev_priv->drm, transcoders != 0); |
e24bcd34 MN |
7339 | |
7340 | return 0; | |
7341 | } | |
7342 | ||
7343 | static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, | |
7344 | struct drm_connector *connector) | |
7345 | { | |
7346 | const struct drm_connector_state *old_conn_state = | |
7347 | drm_atomic_get_old_connector_state(&state->base, connector); | |
7348 | const struct intel_crtc_state *old_crtc_state; | |
7349 | struct intel_crtc *crtc; | |
7350 | u8 transcoders; | |
7351 | ||
7352 | crtc = to_intel_crtc(old_conn_state->crtc); | |
7353 | if (!crtc) | |
7354 | return 0; | |
7355 | ||
7356 | old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); | |
7357 | ||
7358 | if (!old_crtc_state->hw.active) | |
7359 | return 0; | |
7360 | ||
7361 | transcoders = old_crtc_state->sync_mode_slaves_mask; | |
7362 | if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) | |
7363 | transcoders |= BIT(old_crtc_state->master_transcoder); | |
7364 | ||
7365 | return intel_modeset_affected_transcoders(state, | |
7366 | transcoders); | |
7367 | } | |
7368 | ||
7369 | static int intel_dp_connector_atomic_check(struct drm_connector *conn, | |
7370 | struct drm_atomic_state *_state) | |
7371 | { | |
7372 | struct drm_i915_private *dev_priv = to_i915(conn->dev); | |
7373 | struct intel_atomic_state *state = to_intel_atomic_state(_state); | |
7374 | int ret; | |
7375 | ||
7376 | ret = intel_digital_connector_atomic_check(conn, &state->base); | |
7377 | if (ret) | |
7378 | return ret; | |
7379 | ||
dc5b8ed5 VS |
7380 | /* |
7381 | * We don't enable port sync on BDW due to missing w/as and | |
7382 | * due to not having adjusted the modeset sequence appropriately. | |
7383 | */ | |
7384 | if (INTEL_GEN(dev_priv) < 9) | |
e24bcd34 MN |
7385 | return 0; |
7386 | ||
7387 | if (!intel_connector_needs_modeset(state, conn)) | |
7388 | return 0; | |
7389 | ||
7390 | if (conn->has_tile) { | |
7391 | ret = intel_modeset_tile_group(state, conn->tile_group->id); | |
7392 | if (ret) | |
7393 | return ret; | |
7394 | } | |
7395 | ||
7396 | return intel_modeset_synced_crtcs(state, conn); | |
7397 | } | |
7398 | ||
a4fc5ed6 | 7399 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
beb60608 | 7400 | .force = intel_dp_force, |
a4fc5ed6 | 7401 | .fill_modes = drm_helper_probe_single_connector_modes, |
8f647a01 ML |
7402 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
7403 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
7a418e34 | 7404 | .late_register = intel_dp_connector_register, |
c191eca1 | 7405 | .early_unregister = intel_dp_connector_unregister, |
d4b26e4f | 7406 | .destroy = intel_connector_destroy, |
c6f95f27 | 7407 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
8f647a01 | 7408 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
a4fc5ed6 KP |
7409 | }; |
7410 | ||
7411 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
6c5ed5ae | 7412 | .detect_ctx = intel_dp_detect, |
a4fc5ed6 KP |
7413 | .get_modes = intel_dp_get_modes, |
7414 | .mode_valid = intel_dp_mode_valid, | |
e24bcd34 | 7415 | .atomic_check = intel_dp_connector_atomic_check, |
a4fc5ed6 KP |
7416 | }; |
7417 | ||
a4fc5ed6 | 7418 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 7419 | .reset = intel_dp_encoder_reset, |
24d05927 | 7420 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
7421 | }; |
7422 | ||
13ea6db2 AG |
7423 | static bool intel_edp_have_power(struct intel_dp *intel_dp) |
7424 | { | |
7425 | intel_wakeref_t wakeref; | |
7426 | bool have_power = false; | |
7427 | ||
7428 | with_pps_lock(intel_dp, wakeref) { | |
7429 | have_power = edp_have_panel_power(intel_dp) && | |
7430 | edp_have_panel_vdd(intel_dp); | |
7431 | } | |
7432 | ||
7433 | return have_power; | |
7434 | } | |
7435 | ||
b2c5c181 | 7436 | enum irqreturn |
13cf5504 DA |
7437 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
7438 | { | |
af67009c | 7439 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
13cf5504 | 7440 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
1c767b33 | 7441 | |
13ea6db2 AG |
7442 | if (intel_dig_port->base.type == INTEL_OUTPUT_EDP && |
7443 | (long_hpd || !intel_edp_have_power(intel_dp))) { | |
7a7f84cc | 7444 | /* |
13ea6db2 | 7445 | * vdd off can generate a long/short pulse on eDP which |
7a7f84cc VS |
7446 | * would require vdd on to handle it, and thus we |
7447 | * would end up in an endless cycle of | |
13ea6db2 | 7448 | * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." |
7a7f84cc | 7449 | */ |
af67009c JN |
7450 | drm_dbg_kms(&i915->drm, |
7451 | "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", | |
7452 | long_hpd ? "long" : "short", | |
7453 | intel_dig_port->base.base.base.id, | |
7454 | intel_dig_port->base.base.name); | |
a8b3d52f | 7455 | return IRQ_HANDLED; |
7a7f84cc VS |
7456 | } |
7457 | ||
af67009c JN |
7458 | drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", |
7459 | intel_dig_port->base.base.base.id, | |
7460 | intel_dig_port->base.base.name, | |
7461 | long_hpd ? "long" : "short"); | |
13cf5504 | 7462 | |
27d4efc5 | 7463 | if (long_hpd) { |
d7e8ef02 | 7464 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
7465 | return IRQ_NONE; |
7466 | } | |
7467 | ||
27d4efc5 | 7468 | if (intel_dp->is_mst) { |
f0617ff0 VS |
7469 | switch (intel_dp_check_mst_status(intel_dp)) { |
7470 | case -EINVAL: | |
27d4efc5 VS |
7471 | /* |
7472 | * If we were in MST mode, and device is not | |
7473 | * there, get out of MST mode | |
7474 | */ | |
af67009c JN |
7475 | drm_dbg_kms(&i915->drm, |
7476 | "MST device may have disappeared %d vs %d\n", | |
7477 | intel_dp->is_mst, | |
7478 | intel_dp->mst_mgr.mst_state); | |
27d4efc5 VS |
7479 | intel_dp->is_mst = false; |
7480 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
7481 | intel_dp->is_mst); | |
6f08ebe7 ID |
7482 | |
7483 | return IRQ_NONE; | |
f0617ff0 VS |
7484 | case 1: |
7485 | return IRQ_NONE; | |
7486 | default: | |
7487 | break; | |
0e32b39c | 7488 | } |
27d4efc5 | 7489 | } |
0e32b39c | 7490 | |
27d4efc5 | 7491 | if (!intel_dp->is_mst) { |
c85d200e | 7492 | bool handled; |
42e5e657 DV |
7493 | |
7494 | handled = intel_dp_short_pulse(intel_dp); | |
7495 | ||
cbfa8ac8 | 7496 | if (!handled) |
6f08ebe7 | 7497 | return IRQ_NONE; |
0e32b39c | 7498 | } |
b2c5c181 | 7499 | |
6f08ebe7 | 7500 | return IRQ_HANDLED; |
13cf5504 DA |
7501 | } |
7502 | ||
477ec328 | 7503 | /* check the VBT to see whether the eDP is on another port */ |
7b91bf7f | 7504 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 7505 | { |
53ce81a7 VS |
7506 | /* |
7507 | * eDP not supported on g4x. so bail out early just | |
7508 | * for a bit extra safety in case the VBT is bonkers. | |
7509 | */ | |
dd11bc10 | 7510 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
7511 | return false; |
7512 | ||
a98d9c1d | 7513 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
7514 | return true; |
7515 | ||
951d9efe | 7516 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
7517 | } |
7518 | ||
200819ab | 7519 | static void |
f684960e CW |
7520 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
7521 | { | |
8b45330a | 7522 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
68ec0736 VS |
7523 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
7524 | ||
7525 | if (!IS_G4X(dev_priv) && port != PORT_A) | |
7526 | intel_attach_force_audio_property(connector); | |
8b45330a | 7527 | |
e953fd7b | 7528 | intel_attach_broadcast_rgb_property(connector); |
b2ae318a | 7529 | if (HAS_GMCH(dev_priv)) |
f1a12172 RS |
7530 | drm_connector_attach_max_bpc_property(connector, 6, 10); |
7531 | else if (INTEL_GEN(dev_priv) >= 5) | |
7532 | drm_connector_attach_max_bpc_property(connector, 6, 12); | |
53b41837 | 7533 | |
9d1bb6f0 GM |
7534 | intel_attach_colorspace_property(connector); |
7535 | ||
0299dfa7 GM |
7536 | if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11) |
7537 | drm_object_attach_property(&connector->base, | |
7538 | connector->dev->mode_config.hdr_output_metadata_property, | |
7539 | 0); | |
7540 | ||
1853a9da | 7541 | if (intel_dp_is_edp(intel_dp)) { |
8b45330a ML |
7542 | u32 allowed_scalers; |
7543 | ||
7544 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
b2ae318a | 7545 | if (!HAS_GMCH(dev_priv)) |
8b45330a ML |
7546 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); |
7547 | ||
7548 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
7549 | ||
eead06df | 7550 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
8b45330a | 7551 | |
53b41837 | 7552 | } |
f684960e CW |
7553 | } |
7554 | ||
dada1a9f ID |
7555 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
7556 | { | |
d28d4731 | 7557 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
7558 | intel_dp->last_power_on = jiffies; |
7559 | intel_dp->last_backlight_off = jiffies; | |
7560 | } | |
7561 | ||
67a54566 | 7562 | static void |
46bd8383 | 7563 | intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) |
67a54566 | 7564 | { |
de25eb7f | 7565 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ab3517c1 | 7566 | u32 pp_on, pp_off, pp_ctl; |
8e8232d5 | 7567 | struct pps_registers regs; |
453c5420 | 7568 | |
46bd8383 | 7569 | intel_pps_get_registers(intel_dp, ®s); |
67a54566 | 7570 | |
9eae5e27 | 7571 | pp_ctl = ilk_get_pp_control(intel_dp); |
67a54566 | 7572 | |
1b61c4a3 JN |
7573 | /* Ensure PPS is unlocked */ |
7574 | if (!HAS_DDI(dev_priv)) | |
b4e33881 | 7575 | intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); |
1b61c4a3 | 7576 | |
b4e33881 JN |
7577 | pp_on = intel_de_read(dev_priv, regs.pp_on); |
7578 | pp_off = intel_de_read(dev_priv, regs.pp_off); | |
67a54566 DV |
7579 | |
7580 | /* Pull timing values out of registers */ | |
78b36b10 JN |
7581 | seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); |
7582 | seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); | |
7583 | seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); | |
7584 | seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); | |
67a54566 | 7585 | |
ab3517c1 JN |
7586 | if (i915_mmio_reg_valid(regs.pp_div)) { |
7587 | u32 pp_div; | |
7588 | ||
b4e33881 | 7589 | pp_div = intel_de_read(dev_priv, regs.pp_div); |
ab3517c1 | 7590 | |
78b36b10 | 7591 | seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; |
ab3517c1 | 7592 | } else { |
78b36b10 | 7593 | seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; |
b0a08bec | 7594 | } |
54648618 ID |
7595 | } |
7596 | ||
de9c1b6b ID |
7597 | static void |
7598 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
7599 | { | |
7600 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
7601 | state_name, | |
7602 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
7603 | } | |
7604 | ||
7605 | static void | |
46bd8383 | 7606 | intel_pps_verify_state(struct intel_dp *intel_dp) |
de9c1b6b ID |
7607 | { |
7608 | struct edp_power_seq hw; | |
7609 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
7610 | ||
46bd8383 | 7611 | intel_pps_readout_hw_state(intel_dp, &hw); |
de9c1b6b ID |
7612 | |
7613 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
7614 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
7615 | DRM_ERROR("PPS state mismatch\n"); | |
7616 | intel_pps_dump_state("sw", sw); | |
7617 | intel_pps_dump_state("hw", &hw); | |
7618 | } | |
7619 | } | |
7620 | ||
54648618 | 7621 | static void |
46bd8383 | 7622 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) |
54648618 | 7623 | { |
de25eb7f | 7624 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
54648618 ID |
7625 | struct edp_power_seq cur, vbt, spec, |
7626 | *final = &intel_dp->pps_delays; | |
7627 | ||
7628 | lockdep_assert_held(&dev_priv->pps_mutex); | |
7629 | ||
7630 | /* already initialized? */ | |
7631 | if (final->t11_t12 != 0) | |
7632 | return; | |
7633 | ||
46bd8383 | 7634 | intel_pps_readout_hw_state(intel_dp, &cur); |
67a54566 | 7635 | |
de9c1b6b | 7636 | intel_pps_dump_state("cur", &cur); |
67a54566 | 7637 | |
6aa23e65 | 7638 | vbt = dev_priv->vbt.edp.pps; |
c99a259b MN |
7639 | /* On Toshiba Satellite P50-C-18C system the VBT T12 delay |
7640 | * of 500ms appears to be too short. Ocassionally the panel | |
7641 | * just fails to power back on. Increasing the delay to 800ms | |
7642 | * seems sufficient to avoid this problem. | |
7643 | */ | |
7644 | if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { | |
7313f5a9 | 7645 | vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); |
bdc6114e WK |
7646 | drm_dbg_kms(&dev_priv->drm, |
7647 | "Increasing T12 panel delay as per the quirk to %d\n", | |
7648 | vbt.t11_t12); | |
c99a259b | 7649 | } |
770a17a5 MN |
7650 | /* T11_T12 delay is special and actually in units of 100ms, but zero |
7651 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
7652 | * table multiplies it with 1000 to make it in units of 100usec, | |
7653 | * too. */ | |
7654 | vbt.t11_t12 += 100 * 10; | |
67a54566 DV |
7655 | |
7656 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
7657 | * our hw here, which are all in 100usec. */ | |
7658 | spec.t1_t3 = 210 * 10; | |
7659 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
7660 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
7661 | spec.t10 = 500 * 10; | |
7662 | /* This one is special and actually in units of 100ms, but zero | |
7663 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
7664 | * table multiplies it with 1000 to make it in units of 100usec, | |
7665 | * too. */ | |
7666 | spec.t11_t12 = (510 + 100) * 10; | |
7667 | ||
de9c1b6b | 7668 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
7669 | |
7670 | /* Use the max of the register settings and vbt. If both are | |
7671 | * unset, fall back to the spec limits. */ | |
36b5f425 | 7672 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
7673 | spec.field : \ |
7674 | max(cur.field, vbt.field)) | |
7675 | assign_final(t1_t3); | |
7676 | assign_final(t8); | |
7677 | assign_final(t9); | |
7678 | assign_final(t10); | |
7679 | assign_final(t11_t12); | |
7680 | #undef assign_final | |
7681 | ||
36b5f425 | 7682 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
7683 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
7684 | intel_dp->backlight_on_delay = get_delay(t8); | |
7685 | intel_dp->backlight_off_delay = get_delay(t9); | |
7686 | intel_dp->panel_power_down_delay = get_delay(t10); | |
7687 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
7688 | #undef get_delay | |
7689 | ||
bdc6114e WK |
7690 | drm_dbg_kms(&dev_priv->drm, |
7691 | "panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
7692 | intel_dp->panel_power_up_delay, | |
7693 | intel_dp->panel_power_down_delay, | |
7694 | intel_dp->panel_power_cycle_delay); | |
f30d26e4 | 7695 | |
bdc6114e WK |
7696 | drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", |
7697 | intel_dp->backlight_on_delay, | |
7698 | intel_dp->backlight_off_delay); | |
de9c1b6b ID |
7699 | |
7700 | /* | |
7701 | * We override the HW backlight delays to 1 because we do manual waits | |
7702 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
7703 | * don't do this, we'll end up waiting for the backlight off delay | |
7704 | * twice: once when we do the manual sleep, and once when we disable | |
7705 | * the panel and wait for the PP_STATUS bit to become zero. | |
7706 | */ | |
7707 | final->t8 = 1; | |
7708 | final->t9 = 1; | |
5643205c ID |
7709 | |
7710 | /* | |
7711 | * HW has only a 100msec granularity for t11_t12 so round it up | |
7712 | * accordingly. | |
7713 | */ | |
7714 | final->t11_t12 = roundup(final->t11_t12, 100 * 10); | |
f30d26e4 JN |
7715 | } |
7716 | ||
7717 | static void | |
46bd8383 | 7718 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 7719 | bool force_disable_vdd) |
f30d26e4 | 7720 | { |
de25eb7f | 7721 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ab3517c1 | 7722 | u32 pp_on, pp_off, port_sel = 0; |
b04002f4 | 7723 | int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; |
8e8232d5 | 7724 | struct pps_registers regs; |
8f4f2797 | 7725 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
36b5f425 | 7726 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 7727 | |
e39b999a | 7728 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 7729 | |
46bd8383 | 7730 | intel_pps_get_registers(intel_dp, ®s); |
453c5420 | 7731 | |
5d5ab2d2 VS |
7732 | /* |
7733 | * On some VLV machines the BIOS can leave the VDD | |
e7f2af78 | 7734 | * enabled even on power sequencers which aren't |
5d5ab2d2 VS |
7735 | * hooked up to any port. This would mess up the |
7736 | * power domain tracking the first time we pick | |
7737 | * one of these power sequencers for use since | |
7738 | * edp_panel_vdd_on() would notice that the VDD was | |
7739 | * already on and therefore wouldn't grab the power | |
7740 | * domain reference. Disable VDD first to avoid this. | |
7741 | * This also avoids spuriously turning the VDD on as | |
e7f2af78 | 7742 | * soon as the new power sequencer gets initialized. |
5d5ab2d2 VS |
7743 | */ |
7744 | if (force_disable_vdd) { | |
9eae5e27 | 7745 | u32 pp = ilk_get_pp_control(intel_dp); |
5d5ab2d2 | 7746 | |
eb020ca3 PB |
7747 | drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON, |
7748 | "Panel power already on\n"); | |
5d5ab2d2 VS |
7749 | |
7750 | if (pp & EDP_FORCE_VDD) | |
bdc6114e WK |
7751 | drm_dbg_kms(&dev_priv->drm, |
7752 | "VDD already on, disabling first\n"); | |
5d5ab2d2 VS |
7753 | |
7754 | pp &= ~EDP_FORCE_VDD; | |
7755 | ||
b4e33881 | 7756 | intel_de_write(dev_priv, regs.pp_ctrl, pp); |
5d5ab2d2 VS |
7757 | } |
7758 | ||
78b36b10 JN |
7759 | pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | |
7760 | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); | |
7761 | pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | | |
7762 | REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); | |
67a54566 DV |
7763 | |
7764 | /* Haswell doesn't have any port selection bits for the panel | |
7765 | * power sequencer any more. */ | |
920a14b2 | 7766 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 7767 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 7768 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
05bf51d3 VS |
7769 | switch (port) { |
7770 | case PORT_A: | |
a24c144c | 7771 | port_sel = PANEL_PORT_SELECT_DPA; |
05bf51d3 VS |
7772 | break; |
7773 | case PORT_C: | |
7774 | port_sel = PANEL_PORT_SELECT_DPC; | |
7775 | break; | |
7776 | case PORT_D: | |
a24c144c | 7777 | port_sel = PANEL_PORT_SELECT_DPD; |
05bf51d3 VS |
7778 | break; |
7779 | default: | |
7780 | MISSING_CASE(port); | |
7781 | break; | |
7782 | } | |
67a54566 DV |
7783 | } |
7784 | ||
453c5420 JB |
7785 | pp_on |= port_sel; |
7786 | ||
b4e33881 JN |
7787 | intel_de_write(dev_priv, regs.pp_on, pp_on); |
7788 | intel_de_write(dev_priv, regs.pp_off, pp_off); | |
ab3517c1 JN |
7789 | |
7790 | /* | |
7791 | * Compute the divisor for the pp clock, simply match the Bspec formula. | |
7792 | */ | |
7793 | if (i915_mmio_reg_valid(regs.pp_div)) { | |
b4e33881 JN |
7794 | intel_de_write(dev_priv, regs.pp_div, |
7795 | REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); | |
ab3517c1 JN |
7796 | } else { |
7797 | u32 pp_ctl; | |
7798 | ||
b4e33881 | 7799 | pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl); |
ab3517c1 | 7800 | pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; |
78b36b10 | 7801 | pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); |
b4e33881 | 7802 | intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); |
ab3517c1 | 7803 | } |
67a54566 | 7804 | |
bdc6114e WK |
7805 | drm_dbg_kms(&dev_priv->drm, |
7806 | "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", | |
b4e33881 JN |
7807 | intel_de_read(dev_priv, regs.pp_on), |
7808 | intel_de_read(dev_priv, regs.pp_off), | |
bdc6114e | 7809 | i915_mmio_reg_valid(regs.pp_div) ? |
b4e33881 JN |
7810 | intel_de_read(dev_priv, regs.pp_div) : |
7811 | (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); | |
f684960e CW |
7812 | } |
7813 | ||
46bd8383 | 7814 | static void intel_dp_pps_init(struct intel_dp *intel_dp) |
335f752b | 7815 | { |
de25eb7f | 7816 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
920a14b2 TU |
7817 | |
7818 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
7819 | vlv_initial_power_sequencer_setup(intel_dp); |
7820 | } else { | |
46bd8383 VS |
7821 | intel_dp_init_panel_power_sequencer(intel_dp); |
7822 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
335f752b ID |
7823 | } |
7824 | } | |
7825 | ||
b33a2815 VK |
7826 | /** |
7827 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 7828 | * @dev_priv: i915 device |
e896402c | 7829 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
7830 | * @refresh_rate: RR to be programmed |
7831 | * | |
7832 | * This function gets called when refresh rate (RR) has to be changed from | |
7833 | * one frequency to another. Switches can be between high and low RR | |
7834 | * supported by the panel or to any other RR based on media playback (in | |
7835 | * this case, RR value needs to be passed from user space). | |
7836 | * | |
7837 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
7838 | */ | |
85cb48a1 | 7839 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5f88a9c6 | 7840 | const struct intel_crtc_state *crtc_state, |
85cb48a1 | 7841 | int refresh_rate) |
439d7ac0 | 7842 | { |
96178eeb | 7843 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
2225f3c6 | 7844 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
96178eeb | 7845 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
7846 | |
7847 | if (refresh_rate <= 0) { | |
bdc6114e WK |
7848 | drm_dbg_kms(&dev_priv->drm, |
7849 | "Refresh rate should be positive non-zero.\n"); | |
439d7ac0 PB |
7850 | return; |
7851 | } | |
7852 | ||
96178eeb | 7853 | if (intel_dp == NULL) { |
bdc6114e | 7854 | drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); |
439d7ac0 PB |
7855 | return; |
7856 | } | |
7857 | ||
439d7ac0 | 7858 | if (!intel_crtc) { |
bdc6114e WK |
7859 | drm_dbg_kms(&dev_priv->drm, |
7860 | "DRRS: intel_crtc not initialized\n"); | |
439d7ac0 PB |
7861 | return; |
7862 | } | |
7863 | ||
96178eeb | 7864 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
bdc6114e | 7865 | drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); |
439d7ac0 PB |
7866 | return; |
7867 | } | |
7868 | ||
96178eeb VK |
7869 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
7870 | refresh_rate) | |
439d7ac0 PB |
7871 | index = DRRS_LOW_RR; |
7872 | ||
96178eeb | 7873 | if (index == dev_priv->drrs.refresh_rate_type) { |
bdc6114e WK |
7874 | drm_dbg_kms(&dev_priv->drm, |
7875 | "DRRS requested for previously set RR...ignoring\n"); | |
439d7ac0 PB |
7876 | return; |
7877 | } | |
7878 | ||
1326a92c | 7879 | if (!crtc_state->hw.active) { |
bdc6114e WK |
7880 | drm_dbg_kms(&dev_priv->drm, |
7881 | "eDP encoder disabled. CRTC not Active\n"); | |
439d7ac0 PB |
7882 | return; |
7883 | } | |
7884 | ||
85cb48a1 | 7885 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
7886 | switch (index) { |
7887 | case DRRS_HIGH_RR: | |
4c354754 | 7888 | intel_dp_set_m_n(crtc_state, M1_N1); |
a4c30b1d VK |
7889 | break; |
7890 | case DRRS_LOW_RR: | |
4c354754 | 7891 | intel_dp_set_m_n(crtc_state, M2_N2); |
a4c30b1d VK |
7892 | break; |
7893 | case DRRS_MAX_RR: | |
7894 | default: | |
bdc6114e WK |
7895 | drm_err(&dev_priv->drm, |
7896 | "Unsupported refreshrate type\n"); | |
a4c30b1d | 7897 | } |
85cb48a1 ML |
7898 | } else if (INTEL_GEN(dev_priv) > 6) { |
7899 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 7900 | u32 val; |
a4c30b1d | 7901 | |
b4e33881 | 7902 | val = intel_de_read(dev_priv, reg); |
439d7ac0 | 7903 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 7904 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
7905 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
7906 | else | |
7907 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 7908 | } else { |
85cb48a1 | 7909 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
7910 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
7911 | else | |
7912 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 7913 | } |
b4e33881 | 7914 | intel_de_write(dev_priv, reg, val); |
439d7ac0 PB |
7915 | } |
7916 | ||
4e9ac947 VK |
7917 | dev_priv->drrs.refresh_rate_type = index; |
7918 | ||
bdc6114e WK |
7919 | drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", |
7920 | refresh_rate); | |
4e9ac947 VK |
7921 | } |
7922 | ||
b33a2815 VK |
7923 | /** |
7924 | * intel_edp_drrs_enable - init drrs struct if supported | |
7925 | * @intel_dp: DP struct | |
5423adf1 | 7926 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
7927 | * |
7928 | * Initializes frontbuffer_bits and drrs.dp | |
7929 | */ | |
85cb48a1 | 7930 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 7931 | const struct intel_crtc_state *crtc_state) |
c395578e | 7932 | { |
de25eb7f | 7933 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c395578e | 7934 | |
85cb48a1 | 7935 | if (!crtc_state->has_drrs) { |
bdc6114e | 7936 | drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n"); |
c395578e VK |
7937 | return; |
7938 | } | |
7939 | ||
da83ef85 | 7940 | if (dev_priv->psr.enabled) { |
bdc6114e WK |
7941 | drm_dbg_kms(&dev_priv->drm, |
7942 | "PSR enabled. Not enabling DRRS.\n"); | |
da83ef85 RS |
7943 | return; |
7944 | } | |
7945 | ||
c395578e | 7946 | mutex_lock(&dev_priv->drrs.mutex); |
f69a0d71 | 7947 | if (dev_priv->drrs.dp) { |
bdc6114e | 7948 | drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n"); |
c395578e VK |
7949 | goto unlock; |
7950 | } | |
7951 | ||
7952 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
7953 | ||
7954 | dev_priv->drrs.dp = intel_dp; | |
7955 | ||
7956 | unlock: | |
7957 | mutex_unlock(&dev_priv->drrs.mutex); | |
7958 | } | |
7959 | ||
b33a2815 VK |
7960 | /** |
7961 | * intel_edp_drrs_disable - Disable DRRS | |
7962 | * @intel_dp: DP struct | |
5423adf1 | 7963 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
7964 | * |
7965 | */ | |
85cb48a1 | 7966 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 7967 | const struct intel_crtc_state *old_crtc_state) |
c395578e | 7968 | { |
de25eb7f | 7969 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c395578e | 7970 | |
85cb48a1 | 7971 | if (!old_crtc_state->has_drrs) |
c395578e VK |
7972 | return; |
7973 | ||
7974 | mutex_lock(&dev_priv->drrs.mutex); | |
7975 | if (!dev_priv->drrs.dp) { | |
7976 | mutex_unlock(&dev_priv->drrs.mutex); | |
7977 | return; | |
7978 | } | |
7979 | ||
7980 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
7981 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
7982 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
7983 | |
7984 | dev_priv->drrs.dp = NULL; | |
7985 | mutex_unlock(&dev_priv->drrs.mutex); | |
7986 | ||
7987 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
7988 | } | |
7989 | ||
4e9ac947 VK |
7990 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
7991 | { | |
7992 | struct drm_i915_private *dev_priv = | |
7993 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
7994 | struct intel_dp *intel_dp; | |
7995 | ||
7996 | mutex_lock(&dev_priv->drrs.mutex); | |
7997 | ||
7998 | intel_dp = dev_priv->drrs.dp; | |
7999 | ||
8000 | if (!intel_dp) | |
8001 | goto unlock; | |
8002 | ||
439d7ac0 | 8003 | /* |
4e9ac947 VK |
8004 | * The delayed work can race with an invalidate hence we need to |
8005 | * recheck. | |
439d7ac0 PB |
8006 | */ |
8007 | ||
4e9ac947 VK |
8008 | if (dev_priv->drrs.busy_frontbuffer_bits) |
8009 | goto unlock; | |
439d7ac0 | 8010 | |
85cb48a1 ML |
8011 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
8012 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
8013 | ||
8014 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
8015 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
8016 | } | |
439d7ac0 | 8017 | |
4e9ac947 | 8018 | unlock: |
4e9ac947 | 8019 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
8020 | } |
8021 | ||
b33a2815 | 8022 | /** |
0ddfd203 | 8023 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 8024 | * @dev_priv: i915 device |
b33a2815 VK |
8025 | * @frontbuffer_bits: frontbuffer plane tracking bits |
8026 | * | |
0ddfd203 R |
8027 | * This function gets called everytime rendering on the given planes start. |
8028 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
8029 | * |
8030 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
8031 | */ | |
5748b6a1 CW |
8032 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
8033 | unsigned int frontbuffer_bits) | |
a93fad0f | 8034 | { |
a93fad0f VK |
8035 | struct drm_crtc *crtc; |
8036 | enum pipe pipe; | |
8037 | ||
9da7d693 | 8038 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
8039 | return; |
8040 | ||
88f933a8 | 8041 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 8042 | |
a93fad0f | 8043 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
8044 | if (!dev_priv->drrs.dp) { |
8045 | mutex_unlock(&dev_priv->drrs.mutex); | |
8046 | return; | |
8047 | } | |
8048 | ||
a93fad0f VK |
8049 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
8050 | pipe = to_intel_crtc(crtc)->pipe; | |
8051 | ||
c1d038c6 DV |
8052 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
8053 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
8054 | ||
0ddfd203 | 8055 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 8056 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
8057 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
8058 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 8059 | |
a93fad0f VK |
8060 | mutex_unlock(&dev_priv->drrs.mutex); |
8061 | } | |
8062 | ||
b33a2815 | 8063 | /** |
0ddfd203 | 8064 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 8065 | * @dev_priv: i915 device |
b33a2815 VK |
8066 | * @frontbuffer_bits: frontbuffer plane tracking bits |
8067 | * | |
0ddfd203 R |
8068 | * This function gets called every time rendering on the given planes has |
8069 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
8070 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
8071 | * if no other planes are dirty. | |
b33a2815 VK |
8072 | * |
8073 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
8074 | */ | |
5748b6a1 CW |
8075 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
8076 | unsigned int frontbuffer_bits) | |
a93fad0f | 8077 | { |
a93fad0f VK |
8078 | struct drm_crtc *crtc; |
8079 | enum pipe pipe; | |
8080 | ||
9da7d693 | 8081 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
8082 | return; |
8083 | ||
88f933a8 | 8084 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 8085 | |
a93fad0f | 8086 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
8087 | if (!dev_priv->drrs.dp) { |
8088 | mutex_unlock(&dev_priv->drrs.mutex); | |
8089 | return; | |
8090 | } | |
8091 | ||
a93fad0f VK |
8092 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
8093 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
8094 | |
8095 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
8096 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
8097 | ||
0ddfd203 | 8098 | /* flush means busy screen hence upclock */ |
c1d038c6 | 8099 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
8100 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
8101 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
8102 | |
8103 | /* | |
8104 | * flush also means no more activity hence schedule downclock, if all | |
8105 | * other fbs are quiescent too | |
8106 | */ | |
8107 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
8108 | schedule_delayed_work(&dev_priv->drrs.work, |
8109 | msecs_to_jiffies(1000)); | |
8110 | mutex_unlock(&dev_priv->drrs.mutex); | |
8111 | } | |
8112 | ||
b33a2815 VK |
8113 | /** |
8114 | * DOC: Display Refresh Rate Switching (DRRS) | |
8115 | * | |
8116 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
8117 | * which enables swtching between low and high refresh rates, | |
8118 | * dynamically, based on the usage scenario. This feature is applicable | |
8119 | * for internal panels. | |
8120 | * | |
8121 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
8122 | * would list multiple refresh rates for one resolution. | |
8123 | * | |
8124 | * DRRS is of 2 types - static and seamless. | |
8125 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
8126 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
8127 | * Seamless DRRS involves changing RR without any visual effect to the user | |
8128 | * and can be used during normal system usage. This is done by programming | |
8129 | * certain registers. | |
8130 | * | |
8131 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
8132 | * inputs from the panel spec. | |
8133 | * | |
8134 | * DRRS saves power by switching to low RR based on usage scenarios. | |
8135 | * | |
2e7a5701 DV |
8136 | * The implementation is based on frontbuffer tracking implementation. When |
8137 | * there is a disturbance on the screen triggered by user activity or a periodic | |
8138 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
8139 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
8140 | * made. | |
8141 | * | |
8142 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
8143 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
8144 | * |
8145 | * DRRS can be further extended to support other internal panels and also | |
8146 | * the scenario of video playback wherein RR is set based on the rate | |
8147 | * requested by userspace. | |
8148 | */ | |
8149 | ||
8150 | /** | |
8151 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
2f773477 | 8152 | * @connector: eDP connector |
b33a2815 VK |
8153 | * @fixed_mode: preferred mode of panel |
8154 | * | |
8155 | * This function is called only once at driver load to initialize basic | |
8156 | * DRRS stuff. | |
8157 | * | |
8158 | * Returns: | |
8159 | * Downclock mode if panel supports it, else return NULL. | |
8160 | * DRRS support is determined by the presence of downclock mode (apart | |
8161 | * from VBT setting). | |
8162 | */ | |
4f9db5b5 | 8163 | static struct drm_display_mode * |
2f773477 VS |
8164 | intel_dp_drrs_init(struct intel_connector *connector, |
8165 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 | 8166 | { |
2f773477 | 8167 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
4f9db5b5 PB |
8168 | struct drm_display_mode *downclock_mode = NULL; |
8169 | ||
9da7d693 DV |
8170 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
8171 | mutex_init(&dev_priv->drrs.mutex); | |
8172 | ||
dd11bc10 | 8173 | if (INTEL_GEN(dev_priv) <= 6) { |
bdc6114e WK |
8174 | drm_dbg_kms(&dev_priv->drm, |
8175 | "DRRS supported for Gen7 and above\n"); | |
4f9db5b5 PB |
8176 | return NULL; |
8177 | } | |
8178 | ||
8179 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
bdc6114e | 8180 | drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
8181 | return NULL; |
8182 | } | |
8183 | ||
abf1aae8 | 8184 | downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); |
4f9db5b5 | 8185 | if (!downclock_mode) { |
bdc6114e WK |
8186 | drm_dbg_kms(&dev_priv->drm, |
8187 | "Downclock mode is not found. DRRS not supported\n"); | |
4f9db5b5 PB |
8188 | return NULL; |
8189 | } | |
8190 | ||
96178eeb | 8191 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 8192 | |
96178eeb | 8193 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
bdc6114e WK |
8194 | drm_dbg_kms(&dev_priv->drm, |
8195 | "seamless DRRS supported for eDP panel.\n"); | |
4f9db5b5 PB |
8196 | return downclock_mode; |
8197 | } | |
8198 | ||
ed92f0b2 | 8199 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 8200 | struct intel_connector *intel_connector) |
ed92f0b2 | 8201 | { |
de25eb7f RV |
8202 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
8203 | struct drm_device *dev = &dev_priv->drm; | |
2f773477 | 8204 | struct drm_connector *connector = &intel_connector->base; |
ed92f0b2 | 8205 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 8206 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 | 8207 | bool has_dpcd; |
6517d273 | 8208 | enum pipe pipe = INVALID_PIPE; |
69d93820 CW |
8209 | intel_wakeref_t wakeref; |
8210 | struct edid *edid; | |
ed92f0b2 | 8211 | |
1853a9da | 8212 | if (!intel_dp_is_edp(intel_dp)) |
ed92f0b2 PZ |
8213 | return true; |
8214 | ||
36b80aa3 JRS |
8215 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work); |
8216 | ||
97a824e1 ID |
8217 | /* |
8218 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
8219 | * driver uses the only internal power sequencer available for both | |
8220 | * eDP and LVDS bail out early in this case to prevent interfering | |
8221 | * with an already powered-on LVDS power sequencer. | |
8222 | */ | |
17be4942 | 8223 | if (intel_get_lvds_encoder(dev_priv)) { |
eb020ca3 PB |
8224 | drm_WARN_ON(dev, |
8225 | !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
bdc6114e WK |
8226 | drm_info(&dev_priv->drm, |
8227 | "LVDS was detected, not registering eDP\n"); | |
97a824e1 ID |
8228 | |
8229 | return false; | |
8230 | } | |
8231 | ||
69d93820 CW |
8232 | with_pps_lock(intel_dp, wakeref) { |
8233 | intel_dp_init_panel_power_timestamps(intel_dp); | |
8234 | intel_dp_pps_init(intel_dp); | |
8235 | intel_edp_panel_vdd_sanitize(intel_dp); | |
8236 | } | |
63635217 | 8237 | |
ed92f0b2 | 8238 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 8239 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 8240 | |
fe5a66f9 | 8241 | if (!has_dpcd) { |
ed92f0b2 | 8242 | /* if this fails, presume the device is a ghost */ |
bdc6114e WK |
8243 | drm_info(&dev_priv->drm, |
8244 | "failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 8245 | goto out_vdd_off; |
ed92f0b2 PZ |
8246 | } |
8247 | ||
060c8778 | 8248 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 8249 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
8250 | if (edid) { |
8251 | if (drm_add_edid_modes(connector, edid)) { | |
0883ce81 LP |
8252 | drm_connector_update_edid_property(connector, edid); |
8253 | intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); | |
ed92f0b2 PZ |
8254 | } else { |
8255 | kfree(edid); | |
8256 | edid = ERR_PTR(-EINVAL); | |
8257 | } | |
8258 | } else { | |
8259 | edid = ERR_PTR(-ENOENT); | |
8260 | } | |
8261 | intel_connector->edid = edid; | |
8262 | ||
0dc927eb VS |
8263 | fixed_mode = intel_panel_edid_fixed_mode(intel_connector); |
8264 | if (fixed_mode) | |
8265 | downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode); | |
ed92f0b2 PZ |
8266 | |
8267 | /* fallback to VBT if available for eDP */ | |
325710d3 VS |
8268 | if (!fixed_mode) |
8269 | fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); | |
060c8778 | 8270 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 8271 | |
920a14b2 | 8272 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
8273 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
8274 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
8275 | |
8276 | /* | |
8277 | * Figure out the current pipe for the initial backlight setup. | |
8278 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
8279 | * fails just assume pipe A. | |
8280 | */ | |
9f2bdb00 | 8281 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
8282 | |
8283 | if (pipe != PIPE_A && pipe != PIPE_B) | |
8284 | pipe = intel_dp->pps_pipe; | |
8285 | ||
8286 | if (pipe != PIPE_A && pipe != PIPE_B) | |
8287 | pipe = PIPE_A; | |
8288 | ||
bdc6114e WK |
8289 | drm_dbg_kms(&dev_priv->drm, |
8290 | "using pipe %c for initial backlight setup\n", | |
8291 | pipe_name(pipe)); | |
01527b31 CT |
8292 | } |
8293 | ||
d93fa1b4 | 8294 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 8295 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 8296 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 | 8297 | |
69654c63 | 8298 | if (fixed_mode) { |
69654c63 | 8299 | drm_connector_set_panel_orientation_with_quirk(connector, |
0dd5b133 | 8300 | dev_priv->vbt.orientation, |
69654c63 DB |
8301 | fixed_mode->hdisplay, fixed_mode->vdisplay); |
8302 | } | |
9531221d | 8303 | |
ed92f0b2 | 8304 | return true; |
b4d06ede ID |
8305 | |
8306 | out_vdd_off: | |
8307 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
8308 | /* | |
8309 | * vdd might still be enabled do to the delayed vdd off. | |
8310 | * Make sure vdd is actually turned off here. | |
8311 | */ | |
69d93820 CW |
8312 | with_pps_lock(intel_dp, wakeref) |
8313 | edp_panel_vdd_off_sync(intel_dp); | |
b4d06ede ID |
8314 | |
8315 | return false; | |
ed92f0b2 PZ |
8316 | } |
8317 | ||
9301397a MN |
8318 | static void intel_dp_modeset_retry_work_fn(struct work_struct *work) |
8319 | { | |
8320 | struct intel_connector *intel_connector; | |
8321 | struct drm_connector *connector; | |
8322 | ||
8323 | intel_connector = container_of(work, typeof(*intel_connector), | |
8324 | modeset_retry_work); | |
8325 | connector = &intel_connector->base; | |
8326 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, | |
8327 | connector->name); | |
8328 | ||
8329 | /* Grab the locks before changing connector property*/ | |
8330 | mutex_lock(&connector->dev->mode_config.mutex); | |
8331 | /* Set connector link status to BAD and send a Uevent to notify | |
8332 | * userspace to do a modeset. | |
8333 | */ | |
97e14fbe DV |
8334 | drm_connector_set_link_status_property(connector, |
8335 | DRM_MODE_LINK_STATUS_BAD); | |
9301397a MN |
8336 | mutex_unlock(&connector->dev->mode_config.mutex); |
8337 | /* Send Hotplug uevent so userspace can reprobe */ | |
8338 | drm_kms_helper_hotplug_event(connector->dev); | |
8339 | } | |
8340 | ||
16c25533 | 8341 | bool |
f0fec3f2 PZ |
8342 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
8343 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 8344 | { |
f0fec3f2 PZ |
8345 | struct drm_connector *connector = &intel_connector->base; |
8346 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
8347 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
8348 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 8349 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 8350 | enum port port = intel_encoder->port; |
d8fe2ab6 | 8351 | enum phy phy = intel_port_to_phy(dev_priv, port); |
7a418e34 | 8352 | int type; |
a4fc5ed6 | 8353 | |
9301397a MN |
8354 | /* Initialize the work for modeset in case of link train failure */ |
8355 | INIT_WORK(&intel_connector->modeset_retry_work, | |
8356 | intel_dp_modeset_retry_work_fn); | |
8357 | ||
eb020ca3 PB |
8358 | if (drm_WARN(dev, intel_dig_port->max_lanes < 1, |
8359 | "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", | |
8360 | intel_dig_port->max_lanes, intel_encoder->base.base.id, | |
8361 | intel_encoder->base.name)) | |
ccb1a831 VS |
8362 | return false; |
8363 | ||
55cfc580 JN |
8364 | intel_dp_set_source_rates(intel_dp); |
8365 | ||
d7e8ef02 | 8366 | intel_dp->reset_link_params = true; |
a4a5d2f8 | 8367 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 8368 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 8369 | |
0767935e | 8370 | /* Preserve the current hw state. */ |
b4e33881 | 8371 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); |
dd06f90e | 8372 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 8373 | |
4e309baf ID |
8374 | if (intel_dp_is_port_edp(dev_priv, port)) { |
8375 | /* | |
8376 | * Currently we don't support eDP on TypeC ports, although in | |
8377 | * theory it could work on TypeC legacy ports. | |
8378 | */ | |
eb020ca3 | 8379 | drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); |
b329530c | 8380 | type = DRM_MODE_CONNECTOR_eDP; |
4e309baf | 8381 | } else { |
3b32a35b | 8382 | type = DRM_MODE_CONNECTOR_DisplayPort; |
4e309baf | 8383 | } |
b329530c | 8384 | |
9f2bdb00 VS |
8385 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
8386 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
8387 | ||
f7d24902 ID |
8388 | /* |
8389 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
8390 | * for DP the encoder type can be set by the caller to | |
8391 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
8392 | */ | |
8393 | if (type == DRM_MODE_CONNECTOR_eDP) | |
8394 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
8395 | ||
c17ed5b5 | 8396 | /* eDP only on port B and/or C on vlv/chv */ |
eb020ca3 PB |
8397 | if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || |
8398 | IS_CHERRYVIEW(dev_priv)) && | |
8399 | intel_dp_is_edp(intel_dp) && | |
8400 | port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
8401 | return false; |
8402 | ||
bdc6114e WK |
8403 | drm_dbg_kms(&dev_priv->drm, |
8404 | "Adding %s connector on [ENCODER:%d:%s]\n", | |
8405 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
8406 | intel_encoder->base.base.id, intel_encoder->base.name); | |
e7281eab | 8407 | |
b329530c | 8408 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
8409 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
8410 | ||
b2ae318a | 8411 | if (!HAS_GMCH(dev_priv)) |
05021389 | 8412 | connector->interlace_allowed = true; |
a4fc5ed6 KP |
8413 | connector->doublescan_allowed = 0; |
8414 | ||
47d0ccec GM |
8415 | if (INTEL_GEN(dev_priv) >= 11) |
8416 | connector->ycbcr_420_allowed = true; | |
8417 | ||
bdabdb63 | 8418 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
5fb908eb | 8419 | intel_connector->polled = DRM_CONNECTOR_POLL_HPD; |
5432fcaf | 8420 | |
b6339585 | 8421 | intel_dp_aux_init(intel_dp); |
7a418e34 | 8422 | |
df0e9248 | 8423 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 8424 | |
4f8036a2 | 8425 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
8426 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
8427 | else | |
8428 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
8429 | ||
0e32b39c | 8430 | /* init MST on ports that can support it */ |
10d987fd LDM |
8431 | intel_dp_mst_encoder_init(intel_dig_port, |
8432 | intel_connector->base.base.id); | |
0e32b39c | 8433 | |
36b5f425 | 8434 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
8435 | intel_dp_aux_fini(intel_dp); |
8436 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
8437 | goto fail; | |
b2f246a8 | 8438 | } |
32f9d658 | 8439 | |
f684960e | 8440 | intel_dp_add_properties(intel_dp, connector); |
20f24d77 | 8441 | |
fdddd08c | 8442 | if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { |
20f24d77 SP |
8443 | int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); |
8444 | if (ret) | |
bdc6114e WK |
8445 | drm_dbg_kms(&dev_priv->drm, |
8446 | "HDCP init failed, skipping.\n"); | |
20f24d77 | 8447 | } |
f684960e | 8448 | |
a4fc5ed6 KP |
8449 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
8450 | * 0xd. Failure to do so will result in spurious interrupts being | |
8451 | * generated on the port when a cable is not attached. | |
8452 | */ | |
1c0f1b3d | 8453 | if (IS_G45(dev_priv)) { |
b4e33881 JN |
8454 | u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); |
8455 | intel_de_write(dev_priv, PEG_BAND_GAP_DATA, | |
8456 | (temp & ~0xf) | 0xd); | |
a4fc5ed6 | 8457 | } |
16c25533 PZ |
8458 | |
8459 | return true; | |
a121f4e5 VS |
8460 | |
8461 | fail: | |
a121f4e5 VS |
8462 | drm_connector_cleanup(connector); |
8463 | ||
8464 | return false; | |
a4fc5ed6 | 8465 | } |
f0fec3f2 | 8466 | |
c39055b0 | 8467 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
8468 | i915_reg_t output_reg, |
8469 | enum port port) | |
f0fec3f2 PZ |
8470 | { |
8471 | struct intel_digital_port *intel_dig_port; | |
8472 | struct intel_encoder *intel_encoder; | |
8473 | struct drm_encoder *encoder; | |
8474 | struct intel_connector *intel_connector; | |
8475 | ||
b14c5679 | 8476 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 8477 | if (!intel_dig_port) |
457c52d8 | 8478 | return false; |
f0fec3f2 | 8479 | |
08d9bc92 | 8480 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
8481 | if (!intel_connector) |
8482 | goto err_connector_alloc; | |
f0fec3f2 PZ |
8483 | |
8484 | intel_encoder = &intel_dig_port->base; | |
8485 | encoder = &intel_encoder->base; | |
8486 | ||
c39055b0 ACO |
8487 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
8488 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
8489 | "DP %c", port_name(port))) | |
893da0c9 | 8490 | goto err_encoder_init; |
f0fec3f2 | 8491 | |
c85d200e | 8492 | intel_encoder->hotplug = intel_dp_hotplug; |
5bfe2ac0 | 8493 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 8494 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 8495 | intel_encoder->get_config = intel_dp_get_config; |
63a23d24 | 8496 | intel_encoder->update_pipe = intel_panel_update_backlight; |
07f9cd0b | 8497 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 8498 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 8499 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
8500 | intel_encoder->pre_enable = chv_pre_enable_dp; |
8501 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 8502 | intel_encoder->disable = vlv_disable_dp; |
580d3811 | 8503 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 8504 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 8505 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 8506 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
8507 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
8508 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 8509 | intel_encoder->disable = vlv_disable_dp; |
49277c31 | 8510 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 8511 | } else { |
ecff4f3b JN |
8512 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
8513 | intel_encoder->enable = g4x_enable_dp; | |
1a8ff607 | 8514 | intel_encoder->disable = g4x_disable_dp; |
51a9f6df | 8515 | intel_encoder->post_disable = g4x_post_disable_dp; |
ab1f90f9 | 8516 | } |
f0fec3f2 | 8517 | |
f0fec3f2 | 8518 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 8519 | intel_dig_port->max_lanes = 4; |
edcb9028 JRS |
8520 | intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); |
8521 | intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); | |
f0fec3f2 | 8522 | |
cca0502b | 8523 | intel_encoder->type = INTEL_OUTPUT_DP; |
79f255a0 | 8524 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
920a14b2 | 8525 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 | 8526 | if (port == PORT_D) |
981329ce | 8527 | intel_encoder->pipe_mask = BIT(PIPE_C); |
882ec384 | 8528 | else |
981329ce | 8529 | intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); |
882ec384 | 8530 | } else { |
34053ee1 | 8531 | intel_encoder->pipe_mask = ~0; |
882ec384 | 8532 | } |
bc079e8b | 8533 | intel_encoder->cloneable = 0; |
03cdc1d4 | 8534 | intel_encoder->port = port; |
f0fec3f2 | 8535 | |
13cf5504 | 8536 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
13cf5504 | 8537 | |
385e4de0 VS |
8538 | if (port != PORT_A) |
8539 | intel_infoframe_init(intel_dig_port); | |
8540 | ||
39053089 | 8541 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
11aee0f6 SM |
8542 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
8543 | goto err_init_connector; | |
8544 | ||
457c52d8 | 8545 | return true; |
11aee0f6 SM |
8546 | |
8547 | err_init_connector: | |
8548 | drm_encoder_cleanup(encoder); | |
893da0c9 | 8549 | err_encoder_init: |
11aee0f6 SM |
8550 | kfree(intel_connector); |
8551 | err_connector_alloc: | |
8552 | kfree(intel_dig_port); | |
457c52d8 | 8553 | return false; |
f0fec3f2 | 8554 | } |
0e32b39c | 8555 | |
1a4313d1 | 8556 | void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) |
0e32b39c | 8557 | { |
1a4313d1 VS |
8558 | struct intel_encoder *encoder; |
8559 | ||
8560 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
8561 | struct intel_dp *intel_dp; | |
0e32b39c | 8562 | |
1a4313d1 VS |
8563 | if (encoder->type != INTEL_OUTPUT_DDI) |
8564 | continue; | |
5aa56969 | 8565 | |
b7d02c3a | 8566 | intel_dp = enc_to_intel_dp(encoder); |
5aa56969 | 8567 | |
1a4313d1 | 8568 | if (!intel_dp->can_mst) |
0e32b39c DA |
8569 | continue; |
8570 | ||
1a4313d1 VS |
8571 | if (intel_dp->is_mst) |
8572 | drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); | |
0e32b39c DA |
8573 | } |
8574 | } | |
8575 | ||
1a4313d1 | 8576 | void intel_dp_mst_resume(struct drm_i915_private *dev_priv) |
0e32b39c | 8577 | { |
1a4313d1 | 8578 | struct intel_encoder *encoder; |
0e32b39c | 8579 | |
1a4313d1 VS |
8580 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
8581 | struct intel_dp *intel_dp; | |
5aa56969 | 8582 | int ret; |
0e32b39c | 8583 | |
1a4313d1 VS |
8584 | if (encoder->type != INTEL_OUTPUT_DDI) |
8585 | continue; | |
8586 | ||
b7d02c3a | 8587 | intel_dp = enc_to_intel_dp(encoder); |
1a4313d1 VS |
8588 | |
8589 | if (!intel_dp->can_mst) | |
5aa56969 | 8590 | continue; |
0e32b39c | 8591 | |
6f85f738 LP |
8592 | ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, |
8593 | true); | |
6be1cf96 LP |
8594 | if (ret) { |
8595 | intel_dp->is_mst = false; | |
8596 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
8597 | false); | |
8598 | } | |
0e32b39c DA |
8599 | } |
8600 | } |