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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
2d1a8a48 | 28 | #include <linux/export.h> |
331c201a | 29 | #include <linux/i2c.h> |
01527b31 | 30 | #include <linux/notifier.h> |
331c201a JN |
31 | #include <linux/slab.h> |
32 | #include <linux/types.h> | |
56c5098f | 33 | |
611032bf | 34 | #include <asm/byteorder.h> |
331c201a | 35 | |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 | 37 | #include <drm/drm_crtc.h> |
20f24d77 | 38 | #include <drm/drm_dp_helper.h> |
760285e7 | 39 | #include <drm/drm_edid.h> |
fcd70cd3 | 40 | #include <drm/drm_probe_helper.h> |
331c201a | 41 | |
2126d3e9 | 42 | #include "i915_debugfs.h" |
a4fc5ed6 | 43 | #include "i915_drv.h" |
a09d9a80 | 44 | #include "i915_trace.h" |
12392a74 | 45 | #include "intel_atomic.h" |
331c201a | 46 | #include "intel_audio.h" |
ec7f29ff | 47 | #include "intel_connector.h" |
fdc24cf3 | 48 | #include "intel_ddi.h" |
1d455f8d | 49 | #include "intel_display_types.h" |
27fec1f9 | 50 | #include "intel_dp.h" |
e075094f | 51 | #include "intel_dp_link_training.h" |
46f2066e | 52 | #include "intel_dp_mst.h" |
b1ad4c39 | 53 | #include "intel_dpio_phy.h" |
8834e365 | 54 | #include "intel_fifo_underrun.h" |
408bd917 | 55 | #include "intel_hdcp.h" |
0550691d | 56 | #include "intel_hdmi.h" |
dbeb38d9 | 57 | #include "intel_hotplug.h" |
f3e18947 | 58 | #include "intel_lspcon.h" |
42406fdc | 59 | #include "intel_lvds.h" |
44c1220a | 60 | #include "intel_panel.h" |
55367a27 | 61 | #include "intel_psr.h" |
56c5098f | 62 | #include "intel_sideband.h" |
bc85328f | 63 | #include "intel_tc.h" |
b375d0ef | 64 | #include "intel_vdsc.h" |
a4fc5ed6 | 65 | |
e8b2577c | 66 | #define DP_DPRX_ESI_LEN 14 |
a4fc5ed6 | 67 | |
d9218c8f MN |
68 | /* DP DSC throughput values used for slice count calculations KPixels/s */ |
69 | #define DP_DSC_PEAK_PIXEL_RATE 2720000 | |
70 | #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 | |
71 | #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 | |
72 | ||
ed06efb8 ML |
73 | /* DP DSC FEC Overhead factor = 1/(0.972261) */ |
74 | #define DP_DSC_FEC_OVERHEAD_FACTOR 972261 | |
d9218c8f | 75 | |
559be30c TP |
76 | /* Compliance test status bits */ |
77 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
78 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
79 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
80 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
81 | ||
9dd4ffdf | 82 | struct dp_link_dpll { |
840b32b7 | 83 | int clock; |
9dd4ffdf CML |
84 | struct dpll dpll; |
85 | }; | |
86 | ||
45101e93 | 87 | static const struct dp_link_dpll g4x_dpll[] = { |
840b32b7 | 88 | { 162000, |
9dd4ffdf | 89 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 90 | { 270000, |
9dd4ffdf CML |
91 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
92 | }; | |
93 | ||
94 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 95 | { 162000, |
9dd4ffdf | 96 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 97 | { 270000, |
9dd4ffdf CML |
98 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
99 | }; | |
100 | ||
65ce4bf5 | 101 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 102 | { 162000, |
58f6e632 | 103 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 104 | { 270000, |
65ce4bf5 CML |
105 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
106 | }; | |
107 | ||
ef9348c8 CML |
108 | /* |
109 | * CHV supports eDP 1.4 that have more link rates. | |
110 | * Below only provides the fixed rate but exclude variable rate. | |
111 | */ | |
112 | static const struct dp_link_dpll chv_dpll[] = { | |
113 | /* | |
114 | * CHV requires to program fractional division for m2. | |
115 | * m2 is stored in fixed point format using formula below | |
116 | * (m2_int << 22) | m2_fraction | |
117 | */ | |
840b32b7 | 118 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 119 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 120 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 121 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
ef9348c8 | 122 | }; |
637a9c63 | 123 | |
d9218c8f MN |
124 | /* Constants for DP DSC configurations */ |
125 | static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; | |
126 | ||
127 | /* With Single pipe configuration, HW is capable of supporting maximum | |
128 | * of 4 slices per line. | |
129 | */ | |
130 | static const u8 valid_dsc_slicecount[] = {1, 2, 4}; | |
131 | ||
cfcb0fc9 | 132 | /** |
1853a9da | 133 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
cfcb0fc9 JB |
134 | * @intel_dp: DP struct |
135 | * | |
136 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
137 | * will return true, and false otherwise. | |
138 | */ | |
1853a9da | 139 | bool intel_dp_is_edp(struct intel_dp *intel_dp) |
cfcb0fc9 | 140 | { |
7801f3b7 | 141 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
da63a9f2 | 142 | |
7801f3b7 | 143 | return dig_port->base.type == INTEL_OUTPUT_EDP; |
cfcb0fc9 JB |
144 | } |
145 | ||
adc10304 VS |
146 | static void intel_dp_link_down(struct intel_encoder *encoder, |
147 | const struct intel_crtc_state *old_crtc_state); | |
1e0560e0 | 148 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 149 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
adc10304 VS |
150 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
151 | const struct intel_crtc_state *crtc_state); | |
46bd8383 | 152 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a8c3344e | 153 | enum pipe pipe); |
f21a2198 | 154 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 155 | |
68f357cb JN |
156 | /* update sink rates from dpcd */ |
157 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) | |
158 | { | |
229675d5 | 159 | static const int dp_rates[] = { |
c71b53cc | 160 | 162000, 270000, 540000, 810000 |
229675d5 | 161 | }; |
a8a08886 | 162 | int i, max_rate; |
68f357cb | 163 | |
639e0db2 MK |
164 | if (drm_dp_has_quirk(&intel_dp->desc, 0, |
165 | DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { | |
166 | /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ | |
167 | static const int quirk_rates[] = { 162000, 270000, 324000 }; | |
168 | ||
169 | memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); | |
170 | intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); | |
171 | ||
172 | return; | |
173 | } | |
174 | ||
a8a08886 | 175 | max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); |
68f357cb | 176 | |
229675d5 JN |
177 | for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { |
178 | if (dp_rates[i] > max_rate) | |
a8a08886 | 179 | break; |
229675d5 | 180 | intel_dp->sink_rates[i] = dp_rates[i]; |
a8a08886 | 181 | } |
68f357cb | 182 | |
a8a08886 | 183 | intel_dp->num_sink_rates = i; |
68f357cb JN |
184 | } |
185 | ||
10ebb736 JN |
186 | /* Get length of rates array potentially limited by max_rate. */ |
187 | static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) | |
188 | { | |
189 | int i; | |
190 | ||
191 | /* Limit results by potentially reduced max rate */ | |
192 | for (i = 0; i < len; i++) { | |
193 | if (rates[len - i - 1] <= max_rate) | |
194 | return len - i; | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | /* Get length of common rates array potentially limited by max_rate. */ | |
201 | static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, | |
202 | int max_rate) | |
203 | { | |
204 | return intel_dp_rate_limit_len(intel_dp->common_rates, | |
205 | intel_dp->num_common_rates, max_rate); | |
206 | } | |
207 | ||
540b0b7f JN |
208 | /* Theoretical max between source and sink */ |
209 | static int intel_dp_max_common_rate(struct intel_dp *intel_dp) | |
a4fc5ed6 | 210 | { |
540b0b7f | 211 | return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
a4fc5ed6 KP |
212 | } |
213 | ||
540b0b7f JN |
214 | /* Theoretical max between source and sink */ |
215 | static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) | |
eeb6324d | 216 | { |
7801f3b7 LDM |
217 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
218 | int source_max = dig_port->max_lanes; | |
540b0b7f | 219 | int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
7801f3b7 | 220 | int fia_max = intel_tc_port_fia_max_lane_count(dig_port); |
eeb6324d | 221 | |
db7295c2 | 222 | return min3(source_max, sink_max, fia_max); |
eeb6324d PZ |
223 | } |
224 | ||
3d65a735 | 225 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
540b0b7f JN |
226 | { |
227 | return intel_dp->max_link_lane_count; | |
228 | } | |
229 | ||
22a2c8e0 | 230 | int |
c898261c | 231 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 232 | { |
fd81c44e DP |
233 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
234 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
235 | } |
236 | ||
22a2c8e0 | 237 | int |
fe27d53e DA |
238 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
239 | { | |
fd81c44e DP |
240 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
241 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
242 | * is transmitted every LS_Clk per lane, there is no need to account for | |
243 | * the channel encoding that is done in the PHY layer here. | |
244 | */ | |
245 | ||
246 | return max_link_clock * max_lanes; | |
fe27d53e DA |
247 | } |
248 | ||
4ba285d4 | 249 | static int cnl_max_source_rate(struct intel_dp *intel_dp) |
53ddb3cd RV |
250 | { |
251 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
252 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
253 | enum port port = dig_port->base.port; | |
254 | ||
b4e33881 | 255 | u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; |
53ddb3cd RV |
256 | |
257 | /* Low voltage SKUs are limited to max of 5.4G */ | |
258 | if (voltage == VOLTAGE_INFO_0_85V) | |
4ba285d4 | 259 | return 540000; |
53ddb3cd RV |
260 | |
261 | /* For this SKU 8.1G is supported in all ports */ | |
262 | if (IS_CNL_WITH_PORT_F(dev_priv)) | |
4ba285d4 | 263 | return 810000; |
53ddb3cd | 264 | |
3758d968 | 265 | /* For other SKUs, max rate on ports A and D is 5.4G */ |
53ddb3cd | 266 | if (port == PORT_A || port == PORT_D) |
4ba285d4 | 267 | return 540000; |
53ddb3cd | 268 | |
4ba285d4 | 269 | return 810000; |
53ddb3cd RV |
270 | } |
271 | ||
46b527d1 MN |
272 | static int icl_max_source_rate(struct intel_dp *intel_dp) |
273 | { | |
274 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
b265a2a6 | 275 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
d8fe2ab6 | 276 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
46b527d1 | 277 | |
d8fe2ab6 | 278 | if (intel_phy_is_combo(dev_priv, phy) && |
b265a2a6 | 279 | !intel_dp_is_edp(intel_dp)) |
46b527d1 MN |
280 | return 540000; |
281 | ||
282 | return 810000; | |
283 | } | |
284 | ||
cf725620 JRS |
285 | static int ehl_max_source_rate(struct intel_dp *intel_dp) |
286 | { | |
287 | if (intel_dp_is_edp(intel_dp)) | |
288 | return 540000; | |
289 | ||
290 | return 810000; | |
291 | } | |
292 | ||
55cfc580 JN |
293 | static void |
294 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 | 295 | { |
229675d5 JN |
296 | /* The values must be in increasing order */ |
297 | static const int cnl_rates[] = { | |
298 | 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 | |
299 | }; | |
300 | static const int bxt_rates[] = { | |
301 | 162000, 216000, 243000, 270000, 324000, 432000, 540000 | |
302 | }; | |
303 | static const int skl_rates[] = { | |
304 | 162000, 216000, 270000, 324000, 432000, 540000 | |
305 | }; | |
306 | static const int hsw_rates[] = { | |
307 | 162000, 270000, 540000 | |
308 | }; | |
309 | static const int g4x_rates[] = { | |
310 | 162000, 270000 | |
311 | }; | |
40dba341 | 312 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
f83acdab | 313 | struct intel_encoder *encoder = &dig_port->base; |
40dba341 | 314 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
55cfc580 | 315 | const int *source_rates; |
f83acdab | 316 | int size, max_rate = 0, vbt_max_rate; |
40dba341 | 317 | |
55cfc580 | 318 | /* This should only be done once */ |
eb020ca3 PB |
319 | drm_WARN_ON(&dev_priv->drm, |
320 | intel_dp->source_rates || intel_dp->num_source_rates); | |
55cfc580 | 321 | |
46b527d1 | 322 | if (INTEL_GEN(dev_priv) >= 10) { |
d907b665 | 323 | source_rates = cnl_rates; |
4ba285d4 | 324 | size = ARRAY_SIZE(cnl_rates); |
cf819eff | 325 | if (IS_GEN(dev_priv, 10)) |
46b527d1 | 326 | max_rate = cnl_max_source_rate(intel_dp); |
cf725620 JRS |
327 | else if (IS_ELKHARTLAKE(dev_priv)) |
328 | max_rate = ehl_max_source_rate(intel_dp); | |
46b527d1 MN |
329 | else |
330 | max_rate = icl_max_source_rate(intel_dp); | |
ba1c06a5 MN |
331 | } else if (IS_GEN9_LP(dev_priv)) { |
332 | source_rates = bxt_rates; | |
333 | size = ARRAY_SIZE(bxt_rates); | |
b976dc53 | 334 | } else if (IS_GEN9_BC(dev_priv)) { |
55cfc580 | 335 | source_rates = skl_rates; |
40dba341 | 336 | size = ARRAY_SIZE(skl_rates); |
fc603ca7 JN |
337 | } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
338 | IS_BROADWELL(dev_priv)) { | |
229675d5 JN |
339 | source_rates = hsw_rates; |
340 | size = ARRAY_SIZE(hsw_rates); | |
fc603ca7 | 341 | } else { |
229675d5 JN |
342 | source_rates = g4x_rates; |
343 | size = ARRAY_SIZE(g4x_rates); | |
40dba341 NM |
344 | } |
345 | ||
f83acdab | 346 | vbt_max_rate = intel_bios_dp_max_link_rate(encoder); |
99b91bda JN |
347 | if (max_rate && vbt_max_rate) |
348 | max_rate = min(max_rate, vbt_max_rate); | |
349 | else if (vbt_max_rate) | |
350 | max_rate = vbt_max_rate; | |
351 | ||
4ba285d4 JN |
352 | if (max_rate) |
353 | size = intel_dp_rate_limit_len(source_rates, size, max_rate); | |
354 | ||
55cfc580 JN |
355 | intel_dp->source_rates = source_rates; |
356 | intel_dp->num_source_rates = size; | |
40dba341 NM |
357 | } |
358 | ||
359 | static int intersect_rates(const int *source_rates, int source_len, | |
360 | const int *sink_rates, int sink_len, | |
361 | int *common_rates) | |
362 | { | |
363 | int i = 0, j = 0, k = 0; | |
364 | ||
365 | while (i < source_len && j < sink_len) { | |
366 | if (source_rates[i] == sink_rates[j]) { | |
367 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
368 | return k; | |
369 | common_rates[k] = source_rates[i]; | |
370 | ++k; | |
371 | ++i; | |
372 | ++j; | |
373 | } else if (source_rates[i] < sink_rates[j]) { | |
374 | ++i; | |
375 | } else { | |
376 | ++j; | |
377 | } | |
378 | } | |
379 | return k; | |
380 | } | |
381 | ||
8001b754 JN |
382 | /* return index of rate in rates array, or -1 if not found */ |
383 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
384 | { | |
385 | int i; | |
386 | ||
387 | for (i = 0; i < len; i++) | |
388 | if (rate == rates[i]) | |
389 | return i; | |
390 | ||
391 | return -1; | |
392 | } | |
393 | ||
975ee5fc | 394 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 395 | { |
4f360482 PB |
396 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
397 | ||
398 | drm_WARN_ON(&i915->drm, | |
399 | !intel_dp->num_source_rates || !intel_dp->num_sink_rates); | |
40dba341 | 400 | |
975ee5fc JN |
401 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
402 | intel_dp->num_source_rates, | |
403 | intel_dp->sink_rates, | |
404 | intel_dp->num_sink_rates, | |
405 | intel_dp->common_rates); | |
406 | ||
407 | /* Paranoia, there should always be something in common. */ | |
4f360482 | 408 | if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { |
229675d5 | 409 | intel_dp->common_rates[0] = 162000; |
975ee5fc JN |
410 | intel_dp->num_common_rates = 1; |
411 | } | |
412 | } | |
413 | ||
1a92c70e | 414 | static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
830de422 | 415 | u8 lane_count) |
14c562c0 MN |
416 | { |
417 | /* | |
418 | * FIXME: we need to synchronize the current link parameters with | |
419 | * hardware readout. Currently fast link training doesn't work on | |
420 | * boot-up. | |
421 | */ | |
1a92c70e MN |
422 | if (link_rate == 0 || |
423 | link_rate > intel_dp->max_link_rate) | |
14c562c0 MN |
424 | return false; |
425 | ||
1a92c70e MN |
426 | if (lane_count == 0 || |
427 | lane_count > intel_dp_max_lane_count(intel_dp)) | |
14c562c0 MN |
428 | return false; |
429 | ||
430 | return true; | |
431 | } | |
432 | ||
1e712535 MN |
433 | static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, |
434 | int link_rate, | |
830de422 | 435 | u8 lane_count) |
1e712535 MN |
436 | { |
437 | const struct drm_display_mode *fixed_mode = | |
438 | intel_dp->attached_connector->panel.fixed_mode; | |
439 | int mode_rate, max_rate; | |
440 | ||
441 | mode_rate = intel_dp_link_required(fixed_mode->clock, 18); | |
442 | max_rate = intel_dp_max_data_rate(link_rate, lane_count); | |
443 | if (mode_rate > max_rate) | |
444 | return false; | |
445 | ||
446 | return true; | |
447 | } | |
448 | ||
fdb14d33 | 449 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
830de422 | 450 | int link_rate, u8 lane_count) |
fdb14d33 | 451 | { |
af67009c | 452 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b1810a74 | 453 | int index; |
fdb14d33 | 454 | |
80a8cecf ID |
455 | /* |
456 | * TODO: Enable fallback on MST links once MST link compute can handle | |
457 | * the fallback params. | |
458 | */ | |
459 | if (intel_dp->is_mst) { | |
460 | drm_err(&i915->drm, "Link Training Unsuccessful\n"); | |
461 | return -1; | |
462 | } | |
463 | ||
b1810a74 JN |
464 | index = intel_dp_rate_index(intel_dp->common_rates, |
465 | intel_dp->num_common_rates, | |
466 | link_rate); | |
467 | if (index > 0) { | |
1e712535 MN |
468 | if (intel_dp_is_edp(intel_dp) && |
469 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
470 | intel_dp->common_rates[index - 1], | |
471 | lane_count)) { | |
af67009c JN |
472 | drm_dbg_kms(&i915->drm, |
473 | "Retrying Link training for eDP with same parameters\n"); | |
1e712535 MN |
474 | return 0; |
475 | } | |
e6c0c64a JN |
476 | intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
477 | intel_dp->max_link_lane_count = lane_count; | |
fdb14d33 | 478 | } else if (lane_count > 1) { |
1e712535 MN |
479 | if (intel_dp_is_edp(intel_dp) && |
480 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
481 | intel_dp_max_common_rate(intel_dp), | |
482 | lane_count >> 1)) { | |
af67009c JN |
483 | drm_dbg_kms(&i915->drm, |
484 | "Retrying Link training for eDP with same parameters\n"); | |
1e712535 MN |
485 | return 0; |
486 | } | |
540b0b7f | 487 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
e6c0c64a | 488 | intel_dp->max_link_lane_count = lane_count >> 1; |
fdb14d33 | 489 | } else { |
af67009c | 490 | drm_err(&i915->drm, "Link Training Unsuccessful\n"); |
fdb14d33 MN |
491 | return -1; |
492 | } | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
ed06efb8 ML |
497 | u32 intel_dp_mode_to_fec_clock(u32 mode_clock) |
498 | { | |
499 | return div_u64(mul_u32_u32(mode_clock, 1000000U), | |
500 | DP_DSC_FEC_OVERHEAD_FACTOR); | |
501 | } | |
502 | ||
45d3c5cd MR |
503 | static int |
504 | small_joiner_ram_size_bits(struct drm_i915_private *i915) | |
505 | { | |
506 | if (INTEL_GEN(i915) >= 11) | |
507 | return 7680 * 8; | |
508 | else | |
509 | return 6144 * 8; | |
510 | } | |
511 | ||
512 | static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, | |
513 | u32 link_clock, u32 lane_count, | |
ed06efb8 ML |
514 | u32 mode_clock, u32 mode_hdisplay) |
515 | { | |
516 | u32 bits_per_pixel, max_bpp_small_joiner_ram; | |
517 | int i; | |
518 | ||
519 | /* | |
520 | * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* | |
521 | * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) | |
522 | * for SST -> TimeSlotsPerMTP is 1, | |
523 | * for MST -> TimeSlotsPerMTP has to be calculated | |
524 | */ | |
525 | bits_per_pixel = (link_clock * lane_count * 8) / | |
526 | intel_dp_mode_to_fec_clock(mode_clock); | |
bdc6114e | 527 | drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); |
ed06efb8 ML |
528 | |
529 | /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ | |
45d3c5cd MR |
530 | max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / |
531 | mode_hdisplay; | |
bdc6114e WK |
532 | drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n", |
533 | max_bpp_small_joiner_ram); | |
ed06efb8 ML |
534 | |
535 | /* | |
536 | * Greatest allowed DSC BPP = MIN (output BPP from available Link BW | |
537 | * check, output bpp from small joiner RAM check) | |
538 | */ | |
539 | bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); | |
540 | ||
541 | /* Error out if the max bpp is less than smallest allowed valid bpp */ | |
542 | if (bits_per_pixel < valid_dsc_bpp[0]) { | |
bdc6114e WK |
543 | drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", |
544 | bits_per_pixel, valid_dsc_bpp[0]); | |
ed06efb8 ML |
545 | return 0; |
546 | } | |
547 | ||
548 | /* Find the nearest match in the array of known BPPs from VESA */ | |
549 | for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { | |
550 | if (bits_per_pixel < valid_dsc_bpp[i + 1]) | |
551 | break; | |
552 | } | |
553 | bits_per_pixel = valid_dsc_bpp[i]; | |
554 | ||
555 | /* | |
556 | * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, | |
557 | * fractional part is 0 | |
558 | */ | |
559 | return bits_per_pixel << 4; | |
560 | } | |
561 | ||
562 | static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, | |
563 | int mode_clock, int mode_hdisplay) | |
564 | { | |
af67009c | 565 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
ed06efb8 ML |
566 | u8 min_slice_count, i; |
567 | int max_slice_width; | |
568 | ||
569 | if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) | |
570 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
571 | DP_DSC_MAX_ENC_THROUGHPUT_0); | |
572 | else | |
573 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
574 | DP_DSC_MAX_ENC_THROUGHPUT_1); | |
575 | ||
576 | max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); | |
577 | if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { | |
af67009c JN |
578 | drm_dbg_kms(&i915->drm, |
579 | "Unsupported slice width %d by DP DSC Sink device\n", | |
580 | max_slice_width); | |
ed06efb8 ML |
581 | return 0; |
582 | } | |
583 | /* Also take into account max slice width */ | |
584 | min_slice_count = min_t(u8, min_slice_count, | |
585 | DIV_ROUND_UP(mode_hdisplay, | |
586 | max_slice_width)); | |
587 | ||
588 | /* Find the closest match to the valid slice count values */ | |
589 | for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { | |
590 | if (valid_dsc_slicecount[i] > | |
591 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, | |
592 | false)) | |
593 | break; | |
594 | if (min_slice_count <= valid_dsc_slicecount[i]) | |
595 | return valid_dsc_slicecount[i]; | |
596 | } | |
597 | ||
af67009c JN |
598 | drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", |
599 | min_slice_count); | |
ed06efb8 ML |
600 | return 0; |
601 | } | |
602 | ||
773bd825 VS |
603 | static enum intel_output_format |
604 | intel_dp_output_format(struct drm_connector *connector, | |
605 | const struct drm_display_mode *mode) | |
606 | { | |
607 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); | |
608 | const struct drm_display_info *info = &connector->display_info; | |
609 | ||
610 | if (!drm_mode_is_420_only(info, mode)) | |
611 | return INTEL_OUTPUT_FORMAT_RGB; | |
612 | ||
613 | if (intel_dp->dfp.ycbcr_444_to_420) | |
614 | return INTEL_OUTPUT_FORMAT_YCBCR444; | |
615 | else | |
616 | return INTEL_OUTPUT_FORMAT_YCBCR420; | |
617 | } | |
618 | ||
0bf8dedc VS |
619 | int intel_dp_min_bpp(enum intel_output_format output_format) |
620 | { | |
621 | if (output_format == INTEL_OUTPUT_FORMAT_RGB) | |
622 | return 6 * 3; | |
623 | else | |
624 | return 8 * 3; | |
625 | } | |
626 | ||
627 | static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) | |
628 | { | |
629 | /* | |
630 | * bpp value was assumed to RGB format. And YCbCr 4:2:0 output | |
631 | * format of the number of bytes per pixel will be half the number | |
632 | * of bytes of RGB pixel. | |
633 | */ | |
634 | if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
635 | bpp /= 2; | |
636 | ||
637 | return bpp; | |
638 | } | |
639 | ||
640 | static int | |
641 | intel_dp_mode_min_output_bpp(struct drm_connector *connector, | |
642 | const struct drm_display_mode *mode) | |
643 | { | |
644 | enum intel_output_format output_format = | |
645 | intel_dp_output_format(connector, mode); | |
646 | ||
647 | return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); | |
648 | } | |
649 | ||
98c93394 VS |
650 | static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, |
651 | int hdisplay) | |
652 | { | |
653 | /* | |
654 | * Older platforms don't like hdisplay==4096 with DP. | |
655 | * | |
656 | * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline | |
657 | * and frame counter increment), but we don't get vblank interrupts, | |
658 | * and the pipe underruns immediately. The link also doesn't seem | |
659 | * to get trained properly. | |
660 | * | |
661 | * On CHV the vblank interrupts don't seem to disappear but | |
662 | * otherwise the symptoms are similar. | |
663 | * | |
664 | * TODO: confirm the behaviour on HSW+ | |
665 | */ | |
666 | return hdisplay == 4096 && !HAS_DDI(dev_priv); | |
667 | } | |
668 | ||
fe7cf496 VS |
669 | static enum drm_mode_status |
670 | intel_dp_mode_valid_downstream(struct intel_connector *connector, | |
3977cd1c | 671 | const struct drm_display_mode *mode, |
fe7cf496 VS |
672 | int target_clock) |
673 | { | |
674 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
3977cd1c VS |
675 | const struct drm_display_info *info = &connector->base.display_info; |
676 | int tmds_clock; | |
fe7cf496 VS |
677 | |
678 | if (intel_dp->dfp.max_dotclock && | |
679 | target_clock > intel_dp->dfp.max_dotclock) | |
680 | return MODE_CLOCK_HIGH; | |
681 | ||
3977cd1c VS |
682 | /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ |
683 | tmds_clock = target_clock; | |
684 | if (drm_mode_is_420_only(info, mode)) | |
685 | tmds_clock /= 2; | |
686 | ||
687 | if (intel_dp->dfp.min_tmds_clock && | |
688 | tmds_clock < intel_dp->dfp.min_tmds_clock) | |
689 | return MODE_CLOCK_LOW; | |
690 | if (intel_dp->dfp.max_tmds_clock && | |
691 | tmds_clock > intel_dp->dfp.max_tmds_clock) | |
692 | return MODE_CLOCK_HIGH; | |
693 | ||
fe7cf496 VS |
694 | return MODE_OK; |
695 | } | |
696 | ||
c19de8eb | 697 | static enum drm_mode_status |
a4fc5ed6 KP |
698 | intel_dp_mode_valid(struct drm_connector *connector, |
699 | struct drm_display_mode *mode) | |
700 | { | |
43a6d19c | 701 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
dd06f90e JN |
702 | struct intel_connector *intel_connector = to_intel_connector(connector); |
703 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
6cfd04b0 | 704 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
36008365 DV |
705 | int target_clock = mode->clock; |
706 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
fe7cf496 | 707 | int max_dotclk = dev_priv->max_dotclk_freq; |
6cfd04b0 MN |
708 | u16 dsc_max_output_bpp = 0; |
709 | u8 dsc_slice_count = 0; | |
fe7cf496 | 710 | enum drm_mode_status status; |
70ec0645 | 711 | |
e4dd27aa VS |
712 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
713 | return MODE_NO_DBLESCAN; | |
714 | ||
1853a9da | 715 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
dd06f90e | 716 | if (mode->hdisplay > fixed_mode->hdisplay) |
7de56f43 ZY |
717 | return MODE_PANEL; |
718 | ||
dd06f90e | 719 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 720 | return MODE_PANEL; |
03afc4a2 DV |
721 | |
722 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
723 | } |
724 | ||
50fec21a | 725 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 726 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
727 | |
728 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
0bf8dedc VS |
729 | mode_rate = intel_dp_link_required(target_clock, |
730 | intel_dp_mode_min_output_bpp(connector, mode)); | |
36008365 | 731 | |
98c93394 VS |
732 | if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) |
733 | return MODE_H_ILLEGAL; | |
734 | ||
6cfd04b0 MN |
735 | /* |
736 | * Output bpp is stored in 6.4 format so right shift by 4 to get the | |
737 | * integer value since we support only integer values of bpp. | |
738 | */ | |
739 | if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && | |
740 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { | |
741 | if (intel_dp_is_edp(intel_dp)) { | |
742 | dsc_max_output_bpp = | |
743 | drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; | |
744 | dsc_slice_count = | |
745 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, | |
746 | true); | |
240999cf | 747 | } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { |
6cfd04b0 | 748 | dsc_max_output_bpp = |
45d3c5cd MR |
749 | intel_dp_dsc_get_output_bpp(dev_priv, |
750 | max_link_clock, | |
6cfd04b0 MN |
751 | max_lanes, |
752 | target_clock, | |
753 | mode->hdisplay) >> 4; | |
754 | dsc_slice_count = | |
755 | intel_dp_dsc_get_slice_count(intel_dp, | |
756 | target_clock, | |
757 | mode->hdisplay); | |
758 | } | |
759 | } | |
760 | ||
761 | if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || | |
762 | target_clock > max_dotclk) | |
c4867936 | 763 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
764 | |
765 | if (mode->clock < 10000) | |
766 | return MODE_CLOCK_LOW; | |
767 | ||
0af78a2b DV |
768 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
769 | return MODE_H_ILLEGAL; | |
770 | ||
3977cd1c VS |
771 | status = intel_dp_mode_valid_downstream(intel_connector, |
772 | mode, target_clock); | |
fe7cf496 VS |
773 | if (status != MODE_OK) |
774 | return status; | |
775 | ||
2d20411e | 776 | return intel_mode_valid_max_plane_size(dev_priv, mode); |
a4fc5ed6 KP |
777 | } |
778 | ||
830de422 | 779 | u32 intel_dp_pack_aux(const u8 *src, int src_bytes) |
a4fc5ed6 | 780 | { |
830de422 JN |
781 | int i; |
782 | u32 v = 0; | |
a4fc5ed6 KP |
783 | |
784 | if (src_bytes > 4) | |
785 | src_bytes = 4; | |
786 | for (i = 0; i < src_bytes; i++) | |
830de422 | 787 | v |= ((u32)src[i]) << ((3 - i) * 8); |
a4fc5ed6 KP |
788 | return v; |
789 | } | |
790 | ||
830de422 | 791 | static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) |
a4fc5ed6 KP |
792 | { |
793 | int i; | |
794 | if (dst_bytes > 4) | |
795 | dst_bytes = 4; | |
796 | for (i = 0; i < dst_bytes; i++) | |
797 | dst[i] = src >> ((3-i) * 8); | |
798 | } | |
799 | ||
bf13e81b | 800 | static void |
46bd8383 | 801 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); |
bf13e81b | 802 | static void |
46bd8383 | 803 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 804 | bool force_disable_vdd); |
335f752b | 805 | static void |
46bd8383 | 806 | intel_dp_pps_init(struct intel_dp *intel_dp); |
bf13e81b | 807 | |
69d93820 CW |
808 | static intel_wakeref_t |
809 | pps_lock(struct intel_dp *intel_dp) | |
773538e8 | 810 | { |
de25eb7f | 811 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 812 | intel_wakeref_t wakeref; |
773538e8 VS |
813 | |
814 | /* | |
40c7ae45 | 815 | * See intel_power_sequencer_reset() why we need |
773538e8 VS |
816 | * a power domain reference here. |
817 | */ | |
69d93820 CW |
818 | wakeref = intel_display_power_get(dev_priv, |
819 | intel_aux_power_domain(dp_to_dig_port(intel_dp))); | |
773538e8 VS |
820 | |
821 | mutex_lock(&dev_priv->pps_mutex); | |
69d93820 CW |
822 | |
823 | return wakeref; | |
773538e8 VS |
824 | } |
825 | ||
69d93820 CW |
826 | static intel_wakeref_t |
827 | pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) | |
773538e8 | 828 | { |
de25eb7f | 829 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
773538e8 VS |
830 | |
831 | mutex_unlock(&dev_priv->pps_mutex); | |
69d93820 CW |
832 | intel_display_power_put(dev_priv, |
833 | intel_aux_power_domain(dp_to_dig_port(intel_dp)), | |
834 | wakeref); | |
835 | return 0; | |
773538e8 VS |
836 | } |
837 | ||
69d93820 CW |
838 | #define with_pps_lock(dp, wf) \ |
839 | for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) | |
840 | ||
961a0db0 VS |
841 | static void |
842 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
843 | { | |
de25eb7f | 844 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7801f3b7 | 845 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
961a0db0 | 846 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
847 | bool pll_enabled, release_cl_override = false; |
848 | enum dpio_phy phy = DPIO_PHY(pipe); | |
849 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
830de422 | 850 | u32 DP; |
961a0db0 | 851 | |
eb020ca3 PB |
852 | if (drm_WARN(&dev_priv->drm, |
853 | intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, | |
854 | "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", | |
7801f3b7 LDM |
855 | pipe_name(pipe), dig_port->base.base.base.id, |
856 | dig_port->base.base.name)) | |
961a0db0 VS |
857 | return; |
858 | ||
bdc6114e WK |
859 | drm_dbg_kms(&dev_priv->drm, |
860 | "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", | |
7801f3b7 LDM |
861 | pipe_name(pipe), dig_port->base.base.base.id, |
862 | dig_port->base.base.name); | |
961a0db0 VS |
863 | |
864 | /* Preserve the BIOS-computed detected bit. This is | |
865 | * supposed to be read-only. | |
866 | */ | |
b4e33881 | 867 | DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; |
961a0db0 VS |
868 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
869 | DP |= DP_PORT_WIDTH(1); | |
870 | DP |= DP_LINK_TRAIN_PAT_1; | |
871 | ||
920a14b2 | 872 | if (IS_CHERRYVIEW(dev_priv)) |
59b74c49 VS |
873 | DP |= DP_PIPE_SEL_CHV(pipe); |
874 | else | |
875 | DP |= DP_PIPE_SEL(pipe); | |
961a0db0 | 876 | |
b4e33881 | 877 | pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; |
d288f65f VS |
878 | |
879 | /* | |
880 | * The DPLL for the pipe must be enabled for this to work. | |
881 | * So enable temporarily it if it's not already enabled. | |
882 | */ | |
0047eedc | 883 | if (!pll_enabled) { |
920a14b2 | 884 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
885 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
886 | ||
30ad9814 | 887 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 | 888 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
bdc6114e WK |
889 | drm_err(&dev_priv->drm, |
890 | "Failed to force on pll for pipe %c!\n", | |
891 | pipe_name(pipe)); | |
3f36b937 TU |
892 | return; |
893 | } | |
0047eedc | 894 | } |
d288f65f | 895 | |
961a0db0 VS |
896 | /* |
897 | * Similar magic as in intel_dp_enable_port(). | |
898 | * We _must_ do this port enable + disable trick | |
e7f2af78 | 899 | * to make this power sequencer lock onto the port. |
961a0db0 VS |
900 | * Otherwise even VDD force bit won't work. |
901 | */ | |
b4e33881 JN |
902 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
903 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
961a0db0 | 904 | |
b4e33881 JN |
905 | intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); |
906 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
961a0db0 | 907 | |
b4e33881 JN |
908 | intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); |
909 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
d288f65f | 910 | |
0047eedc | 911 | if (!pll_enabled) { |
30ad9814 | 912 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
913 | |
914 | if (release_cl_override) | |
915 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
916 | } | |
961a0db0 VS |
917 | } |
918 | ||
9f2bdb00 VS |
919 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
920 | { | |
921 | struct intel_encoder *encoder; | |
922 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
923 | ||
924 | /* | |
925 | * We don't have power sequencer currently. | |
926 | * Pick one that's not used by other ports. | |
927 | */ | |
14aa521c | 928 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 929 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
9f2bdb00 VS |
930 | |
931 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
eb020ca3 PB |
932 | drm_WARN_ON(&dev_priv->drm, |
933 | intel_dp->active_pipe != INVALID_PIPE && | |
934 | intel_dp->active_pipe != | |
935 | intel_dp->pps_pipe); | |
9f2bdb00 VS |
936 | |
937 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
938 | pipes &= ~(1 << intel_dp->pps_pipe); | |
939 | } else { | |
eb020ca3 PB |
940 | drm_WARN_ON(&dev_priv->drm, |
941 | intel_dp->pps_pipe != INVALID_PIPE); | |
9f2bdb00 VS |
942 | |
943 | if (intel_dp->active_pipe != INVALID_PIPE) | |
944 | pipes &= ~(1 << intel_dp->active_pipe); | |
945 | } | |
946 | } | |
947 | ||
948 | if (pipes == 0) | |
949 | return INVALID_PIPE; | |
950 | ||
951 | return ffs(pipes) - 1; | |
952 | } | |
953 | ||
bf13e81b JN |
954 | static enum pipe |
955 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
956 | { | |
de25eb7f | 957 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7801f3b7 | 958 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
a8c3344e | 959 | enum pipe pipe; |
bf13e81b | 960 | |
e39b999a | 961 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 962 | |
a8c3344e | 963 | /* We should never land here with regular DP ports */ |
eb020ca3 | 964 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); |
a8c3344e | 965 | |
eb020ca3 PB |
966 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE && |
967 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
9f2bdb00 | 968 | |
a4a5d2f8 VS |
969 | if (intel_dp->pps_pipe != INVALID_PIPE) |
970 | return intel_dp->pps_pipe; | |
971 | ||
9f2bdb00 | 972 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
973 | |
974 | /* | |
975 | * Didn't find one. This should not happen since there | |
976 | * are two power sequencers and up to two eDP ports. | |
977 | */ | |
eb020ca3 | 978 | if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)) |
a8c3344e | 979 | pipe = PIPE_A; |
a4a5d2f8 | 980 | |
46bd8383 | 981 | vlv_steal_power_sequencer(dev_priv, pipe); |
a8c3344e | 982 | intel_dp->pps_pipe = pipe; |
a4a5d2f8 | 983 | |
bdc6114e WK |
984 | drm_dbg_kms(&dev_priv->drm, |
985 | "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", | |
986 | pipe_name(intel_dp->pps_pipe), | |
7801f3b7 LDM |
987 | dig_port->base.base.base.id, |
988 | dig_port->base.base.name); | |
a4a5d2f8 VS |
989 | |
990 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
991 | intel_dp_init_panel_power_sequencer(intel_dp); |
992 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 | 993 | |
961a0db0 VS |
994 | /* |
995 | * Even vdd force doesn't work until we've made | |
996 | * the power sequencer lock in on the port. | |
997 | */ | |
998 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
999 | |
1000 | return intel_dp->pps_pipe; | |
1001 | } | |
1002 | ||
78597996 ID |
1003 | static int |
1004 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
1005 | { | |
de25eb7f | 1006 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
73c0fcac | 1007 | int backlight_controller = dev_priv->vbt.backlight.controller; |
78597996 ID |
1008 | |
1009 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1010 | ||
1011 | /* We should never land here with regular DP ports */ | |
eb020ca3 | 1012 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); |
78597996 | 1013 | |
78597996 | 1014 | if (!intel_dp->pps_reset) |
73c0fcac | 1015 | return backlight_controller; |
78597996 ID |
1016 | |
1017 | intel_dp->pps_reset = false; | |
1018 | ||
1019 | /* | |
1020 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
1021 | * has been setup during connector init. | |
1022 | */ | |
46bd8383 | 1023 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); |
78597996 | 1024 | |
73c0fcac | 1025 | return backlight_controller; |
78597996 ID |
1026 | } |
1027 | ||
6491ab27 VS |
1028 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
1029 | enum pipe pipe); | |
1030 | ||
1031 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
1032 | enum pipe pipe) | |
1033 | { | |
b4e33881 | 1034 | return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
1035 | } |
1036 | ||
1037 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
1038 | enum pipe pipe) | |
1039 | { | |
b4e33881 | 1040 | return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
1041 | } |
1042 | ||
1043 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
1044 | enum pipe pipe) | |
1045 | { | |
1046 | return true; | |
1047 | } | |
bf13e81b | 1048 | |
a4a5d2f8 | 1049 | static enum pipe |
6491ab27 VS |
1050 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
1051 | enum port port, | |
1052 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
1053 | { |
1054 | enum pipe pipe; | |
bf13e81b | 1055 | |
bf13e81b | 1056 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
b4e33881 | 1057 | u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & |
bf13e81b | 1058 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
1059 | |
1060 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
1061 | continue; | |
1062 | ||
6491ab27 VS |
1063 | if (!pipe_check(dev_priv, pipe)) |
1064 | continue; | |
1065 | ||
a4a5d2f8 | 1066 | return pipe; |
bf13e81b JN |
1067 | } |
1068 | ||
a4a5d2f8 VS |
1069 | return INVALID_PIPE; |
1070 | } | |
1071 | ||
1072 | static void | |
1073 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
1074 | { | |
de25eb7f | 1075 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7801f3b7 LDM |
1076 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1077 | enum port port = dig_port->base.port; | |
a4a5d2f8 VS |
1078 | |
1079 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1080 | ||
1081 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
1082 | /* first pick one where the panel is on */ |
1083 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
1084 | vlv_pipe_has_pp_on); | |
1085 | /* didn't find one? pick one where vdd is on */ | |
1086 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
1087 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
1088 | vlv_pipe_has_vdd_on); | |
1089 | /* didn't find one? pick one with just the correct port */ | |
1090 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
1091 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
1092 | vlv_pipe_any); | |
a4a5d2f8 VS |
1093 | |
1094 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
1095 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
bdc6114e WK |
1096 | drm_dbg_kms(&dev_priv->drm, |
1097 | "no initial power sequencer for [ENCODER:%d:%s]\n", | |
7801f3b7 LDM |
1098 | dig_port->base.base.base.id, |
1099 | dig_port->base.base.name); | |
a4a5d2f8 | 1100 | return; |
bf13e81b JN |
1101 | } |
1102 | ||
bdc6114e WK |
1103 | drm_dbg_kms(&dev_priv->drm, |
1104 | "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", | |
7801f3b7 LDM |
1105 | dig_port->base.base.base.id, |
1106 | dig_port->base.base.name, | |
bdc6114e | 1107 | pipe_name(intel_dp->pps_pipe)); |
a4a5d2f8 | 1108 | |
46bd8383 VS |
1109 | intel_dp_init_panel_power_sequencer(intel_dp); |
1110 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
bf13e81b JN |
1111 | } |
1112 | ||
78597996 | 1113 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 1114 | { |
773538e8 VS |
1115 | struct intel_encoder *encoder; |
1116 | ||
a2ab4ab6 CW |
1117 | if (drm_WARN_ON(&dev_priv->drm, |
1118 | !(IS_VALLEYVIEW(dev_priv) || | |
1119 | IS_CHERRYVIEW(dev_priv) || | |
1120 | IS_GEN9_LP(dev_priv)))) | |
773538e8 VS |
1121 | return; |
1122 | ||
1123 | /* | |
1124 | * We can't grab pps_mutex here due to deadlock with power_domain | |
1125 | * mutex when power_domain functions are called while holding pps_mutex. | |
1126 | * That also means that in order to use pps_pipe the code needs to | |
1127 | * hold both a power domain reference and pps_mutex, and the power domain | |
1128 | * reference get/put must be done while _not_ holding pps_mutex. | |
1129 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
1130 | * should use them always. | |
1131 | */ | |
1132 | ||
14aa521c | 1133 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 1134 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7e732cac | 1135 | |
eb020ca3 PB |
1136 | drm_WARN_ON(&dev_priv->drm, |
1137 | intel_dp->active_pipe != INVALID_PIPE); | |
9f2bdb00 VS |
1138 | |
1139 | if (encoder->type != INTEL_OUTPUT_EDP) | |
1140 | continue; | |
1141 | ||
cc3f90f0 | 1142 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
1143 | intel_dp->pps_reset = true; |
1144 | else | |
1145 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 1146 | } |
bf13e81b JN |
1147 | } |
1148 | ||
8e8232d5 ID |
1149 | struct pps_registers { |
1150 | i915_reg_t pp_ctrl; | |
1151 | i915_reg_t pp_stat; | |
1152 | i915_reg_t pp_on; | |
1153 | i915_reg_t pp_off; | |
1154 | i915_reg_t pp_div; | |
1155 | }; | |
1156 | ||
46bd8383 | 1157 | static void intel_pps_get_registers(struct intel_dp *intel_dp, |
8e8232d5 ID |
1158 | struct pps_registers *regs) |
1159 | { | |
de25eb7f | 1160 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
44cb734c ID |
1161 | int pps_idx = 0; |
1162 | ||
8e8232d5 ID |
1163 | memset(regs, 0, sizeof(*regs)); |
1164 | ||
cc3f90f0 | 1165 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
1166 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
1167 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1168 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 1169 | |
44cb734c ID |
1170 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
1171 | regs->pp_stat = PP_STATUS(pps_idx); | |
1172 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
1173 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
ab3517c1 JN |
1174 | |
1175 | /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ | |
c6c30b91 | 1176 | if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) |
ab3517c1 JN |
1177 | regs->pp_div = INVALID_MMIO_REG; |
1178 | else | |
44cb734c | 1179 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
1180 | } |
1181 | ||
f0f59a00 VS |
1182 | static i915_reg_t |
1183 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 1184 | { |
8e8232d5 | 1185 | struct pps_registers regs; |
bf13e81b | 1186 | |
46bd8383 | 1187 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
1188 | |
1189 | return regs.pp_ctrl; | |
bf13e81b JN |
1190 | } |
1191 | ||
f0f59a00 VS |
1192 | static i915_reg_t |
1193 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 1194 | { |
8e8232d5 | 1195 | struct pps_registers regs; |
bf13e81b | 1196 | |
46bd8383 | 1197 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
1198 | |
1199 | return regs.pp_stat; | |
bf13e81b JN |
1200 | } |
1201 | ||
4be73780 | 1202 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 1203 | { |
de25eb7f | 1204 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1205 | |
e39b999a VS |
1206 | lockdep_assert_held(&dev_priv->pps_mutex); |
1207 | ||
920a14b2 | 1208 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
1209 | intel_dp->pps_pipe == INVALID_PIPE) |
1210 | return false; | |
1211 | ||
b4e33881 | 1212 | return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
1213 | } |
1214 | ||
4be73780 | 1215 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 1216 | { |
de25eb7f | 1217 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1218 | |
e39b999a VS |
1219 | lockdep_assert_held(&dev_priv->pps_mutex); |
1220 | ||
920a14b2 | 1221 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
1222 | intel_dp->pps_pipe == INVALID_PIPE) |
1223 | return false; | |
1224 | ||
b4e33881 | 1225 | return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
1226 | } |
1227 | ||
9b984dae KP |
1228 | static void |
1229 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
1230 | { | |
de25eb7f | 1231 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ebf33b18 | 1232 | |
1853a9da | 1233 | if (!intel_dp_is_edp(intel_dp)) |
9b984dae | 1234 | return; |
453c5420 | 1235 | |
4be73780 | 1236 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
eb020ca3 PB |
1237 | drm_WARN(&dev_priv->drm, 1, |
1238 | "eDP powered off while attempting aux channel communication.\n"); | |
bdc6114e | 1239 | drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", |
b4e33881 JN |
1240 | intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), |
1241 | intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
1242 | } |
1243 | } | |
1244 | ||
830de422 | 1245 | static u32 |
8a29c778 | 1246 | intel_dp_aux_wait_done(struct intel_dp *intel_dp) |
9ee32fea | 1247 | { |
5a31d30b | 1248 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
4904fa66 | 1249 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
54516464 | 1250 | const unsigned int timeout_ms = 10; |
830de422 | 1251 | u32 status; |
9ee32fea DV |
1252 | bool done; |
1253 | ||
5a31d30b TU |
1254 | #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1255 | done = wait_event_timeout(i915->gmbus_wait_queue, C, | |
54516464 | 1256 | msecs_to_jiffies_timeout(timeout_ms)); |
39806c3f VS |
1257 | |
1258 | /* just trace the final value */ | |
1259 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); | |
1260 | ||
9ee32fea | 1261 | if (!done) |
bdc6114e | 1262 | drm_err(&i915->drm, |
264c0247 | 1263 | "%s: did not complete or timeout within %ums (status 0x%08x)\n", |
bdc6114e | 1264 | intel_dp->aux.name, timeout_ms, status); |
9ee32fea DV |
1265 | #undef C |
1266 | ||
1267 | return status; | |
1268 | } | |
1269 | ||
830de422 | 1270 | static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 1271 | { |
de25eb7f | 1272 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
9ee32fea | 1273 | |
a457f54b VS |
1274 | if (index) |
1275 | return 0; | |
1276 | ||
ec5b01dd DL |
1277 | /* |
1278 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 1279 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 1280 | */ |
b04002f4 | 1281 | return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); |
ec5b01dd DL |
1282 | } |
1283 | ||
830de422 | 1284 | static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
ec5b01dd | 1285 | { |
de25eb7f | 1286 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 | 1287 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
b04002f4 | 1288 | u32 freq; |
ec5b01dd DL |
1289 | |
1290 | if (index) | |
1291 | return 0; | |
1292 | ||
a457f54b VS |
1293 | /* |
1294 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
1295 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
1296 | * divide by 2000 and use that | |
1297 | */ | |
563d22a0 | 1298 | if (dig_port->aux_ch == AUX_CH_A) |
b04002f4 | 1299 | freq = dev_priv->cdclk.hw.cdclk; |
e7dc33f3 | 1300 | else |
b04002f4 CW |
1301 | freq = RUNTIME_INFO(dev_priv)->rawclk_freq; |
1302 | return DIV_ROUND_CLOSEST(freq, 2000); | |
ec5b01dd DL |
1303 | } |
1304 | ||
830de422 | 1305 | static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
ec5b01dd | 1306 | { |
de25eb7f | 1307 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 | 1308 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
ec5b01dd | 1309 | |
563d22a0 | 1310 | if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 1311 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
1312 | switch (index) { |
1313 | case 0: return 63; | |
1314 | case 1: return 72; | |
1315 | default: return 0; | |
1316 | } | |
2c55c336 | 1317 | } |
a457f54b VS |
1318 | |
1319 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
1320 | } |
1321 | ||
830de422 | 1322 | static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
b6b5e383 DL |
1323 | { |
1324 | /* | |
1325 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
1326 | * derive the clock from CDCLK automatically). We still implement the | |
1327 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
1328 | */ | |
1329 | return index ? 0 : 1; | |
1330 | } | |
1331 | ||
830de422 JN |
1332 | static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
1333 | int send_bytes, | |
1334 | u32 aux_clock_divider) | |
5ed12a19 | 1335 | { |
7801f3b7 | 1336 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
8652744b | 1337 | struct drm_i915_private *dev_priv = |
7801f3b7 | 1338 | to_i915(dig_port->base.base.dev); |
830de422 | 1339 | u32 precharge, timeout; |
5ed12a19 | 1340 | |
cf819eff | 1341 | if (IS_GEN(dev_priv, 6)) |
5ed12a19 DL |
1342 | precharge = 3; |
1343 | else | |
1344 | precharge = 5; | |
1345 | ||
8f5f63d5 | 1346 | if (IS_BROADWELL(dev_priv)) |
5ed12a19 DL |
1347 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
1348 | else | |
1349 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
1350 | ||
1351 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 1352 | DP_AUX_CH_CTL_DONE | |
8a29c778 | 1353 | DP_AUX_CH_CTL_INTERRUPT | |
788d4433 | 1354 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 1355 | timeout | |
788d4433 | 1356 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
1357 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1358 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 1359 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
1360 | } |
1361 | ||
830de422 JN |
1362 | static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
1363 | int send_bytes, | |
1364 | u32 unused) | |
b9ca5fad | 1365 | { |
7801f3b7 | 1366 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
49748264 | 1367 | struct drm_i915_private *i915 = |
7801f3b7 LDM |
1368 | to_i915(dig_port->base.base.dev); |
1369 | enum phy phy = intel_port_to_phy(i915, dig_port->base.port); | |
830de422 | 1370 | u32 ret; |
6f211ed4 AS |
1371 | |
1372 | ret = DP_AUX_CH_CTL_SEND_BUSY | | |
1373 | DP_AUX_CH_CTL_DONE | | |
1374 | DP_AUX_CH_CTL_INTERRUPT | | |
1375 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1376 | DP_AUX_CH_CTL_TIME_OUT_MAX | | |
1377 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
1378 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1379 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | | |
1380 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); | |
1381 | ||
49748264 | 1382 | if (intel_phy_is_tc(i915, phy) && |
7801f3b7 | 1383 | dig_port->tc_mode == TC_PORT_TBT_ALT) |
6f211ed4 AS |
1384 | ret |= DP_AUX_CH_CTL_TBT_IO; |
1385 | ||
1386 | return ret; | |
b9ca5fad DL |
1387 | } |
1388 | ||
b84a1cf8 | 1389 | static int |
f7606265 | 1390 | intel_dp_aux_xfer(struct intel_dp *intel_dp, |
830de422 JN |
1391 | const u8 *send, int send_bytes, |
1392 | u8 *recv, int recv_size, | |
8159c796 | 1393 | u32 aux_send_ctl_flags) |
b84a1cf8 | 1394 | { |
7801f3b7 | 1395 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5a31d30b | 1396 | struct drm_i915_private *i915 = |
7801f3b7 | 1397 | to_i915(dig_port->base.base.dev); |
5a31d30b | 1398 | struct intel_uncore *uncore = &i915->uncore; |
7801f3b7 | 1399 | enum phy phy = intel_port_to_phy(i915, dig_port->base.port); |
d8fe2ab6 | 1400 | bool is_tc_port = intel_phy_is_tc(i915, phy); |
4904fa66 | 1401 | i915_reg_t ch_ctl, ch_data[5]; |
830de422 | 1402 | u32 aux_clock_divider; |
ae9b6cfe | 1403 | enum intel_display_power_domain aux_domain; |
f39194a7 ID |
1404 | intel_wakeref_t aux_wakeref; |
1405 | intel_wakeref_t pps_wakeref; | |
b84a1cf8 | 1406 | int i, ret, recv_bytes; |
5ed12a19 | 1407 | int try, clock = 0; |
830de422 | 1408 | u32 status; |
884f19e9 JN |
1409 | bool vdd; |
1410 | ||
4904fa66 VS |
1411 | ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
1412 | for (i = 0; i < ARRAY_SIZE(ch_data); i++) | |
1413 | ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); | |
1414 | ||
8c10e226 | 1415 | if (is_tc_port) |
7801f3b7 | 1416 | intel_tc_port_lock(dig_port); |
8c10e226 | 1417 | |
7801f3b7 | 1418 | aux_domain = intel_aux_power_domain(dig_port); |
ae9b6cfe | 1419 | |
5a31d30b | 1420 | aux_wakeref = intel_display_power_get(i915, aux_domain); |
f39194a7 | 1421 | pps_wakeref = pps_lock(intel_dp); |
e39b999a | 1422 | |
72c3500a VS |
1423 | /* |
1424 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1425 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1426 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1427 | * ourselves. | |
1428 | */ | |
1e0560e0 | 1429 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1430 | |
1431 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1432 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1433 | * deep sleep states. | |
1434 | */ | |
4d4dda48 | 1435 | cpu_latency_qos_update_request(&i915->pm_qos, 0); |
b84a1cf8 RV |
1436 | |
1437 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1438 | |
11bee43e JB |
1439 | /* Try to wait for any previous AUX channel activity */ |
1440 | for (try = 0; try < 3; try++) { | |
5a31d30b | 1441 | status = intel_uncore_read_notrace(uncore, ch_ctl); |
11bee43e JB |
1442 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1443 | break; | |
1444 | msleep(1); | |
1445 | } | |
39806c3f VS |
1446 | /* just trace the final value */ |
1447 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); | |
11bee43e JB |
1448 | |
1449 | if (try == 3) { | |
5a31d30b | 1450 | const u32 status = intel_uncore_read(uncore, ch_ctl); |
02196c77 | 1451 | |
81cdeca4 | 1452 | if (status != intel_dp->aux_busy_last_status) { |
eb020ca3 PB |
1453 | drm_WARN(&i915->drm, 1, |
1454 | "%s: not started (status 0x%08x)\n", | |
1455 | intel_dp->aux.name, status); | |
81cdeca4 | 1456 | intel_dp->aux_busy_last_status = status; |
02196c77 MK |
1457 | } |
1458 | ||
9ee32fea DV |
1459 | ret = -EBUSY; |
1460 | goto out; | |
4f7f7b7e CW |
1461 | } |
1462 | ||
46a5ae9f | 1463 | /* Only 5 data registers! */ |
eb020ca3 | 1464 | if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { |
46a5ae9f PZ |
1465 | ret = -E2BIG; |
1466 | goto out; | |
1467 | } | |
1468 | ||
ec5b01dd | 1469 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
8159c796 | 1470 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
8159c796 VS |
1471 | send_bytes, |
1472 | aux_clock_divider); | |
1473 | ||
1474 | send_ctl |= aux_send_ctl_flags; | |
5ed12a19 | 1475 | |
bc86625a CW |
1476 | /* Must try at least 3 times according to DP spec */ |
1477 | for (try = 0; try < 5; try++) { | |
1478 | /* Load the send data into the aux channel data registers */ | |
1479 | for (i = 0; i < send_bytes; i += 4) | |
5a31d30b TU |
1480 | intel_uncore_write(uncore, |
1481 | ch_data[i >> 2], | |
1482 | intel_dp_pack_aux(send + i, | |
1483 | send_bytes - i)); | |
bc86625a CW |
1484 | |
1485 | /* Send the command and wait for it to complete */ | |
5a31d30b | 1486 | intel_uncore_write(uncore, ch_ctl, send_ctl); |
bc86625a | 1487 | |
8a29c778 | 1488 | status = intel_dp_aux_wait_done(intel_dp); |
bc86625a CW |
1489 | |
1490 | /* Clear done status and any errors */ | |
5a31d30b TU |
1491 | intel_uncore_write(uncore, |
1492 | ch_ctl, | |
1493 | status | | |
1494 | DP_AUX_CH_CTL_DONE | | |
1495 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1496 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
bc86625a | 1497 | |
74ebf294 TP |
1498 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
1499 | * 400us delay required for errors and timeouts | |
1500 | * Timeout errors from the HW already meet this | |
1501 | * requirement so skip to next iteration | |
1502 | */ | |
3975f0aa DP |
1503 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
1504 | continue; | |
1505 | ||
74ebf294 TP |
1506 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1507 | usleep_range(400, 500); | |
bc86625a | 1508 | continue; |
74ebf294 | 1509 | } |
bc86625a | 1510 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1511 | goto done; |
bc86625a | 1512 | } |
a4fc5ed6 KP |
1513 | } |
1514 | ||
a4fc5ed6 | 1515 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
264c0247 VS |
1516 | drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", |
1517 | intel_dp->aux.name, status); | |
9ee32fea DV |
1518 | ret = -EBUSY; |
1519 | goto out; | |
a4fc5ed6 KP |
1520 | } |
1521 | ||
e058c945 | 1522 | done: |
a4fc5ed6 KP |
1523 | /* Check for timeout or receive error. |
1524 | * Timeouts occur when the sink is not connected | |
1525 | */ | |
a5b3da54 | 1526 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
264c0247 VS |
1527 | drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", |
1528 | intel_dp->aux.name, status); | |
9ee32fea DV |
1529 | ret = -EIO; |
1530 | goto out; | |
a5b3da54 | 1531 | } |
1ae8c0a5 KP |
1532 | |
1533 | /* Timeouts occur when the device isn't connected, so they're | |
1534 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1535 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
264c0247 VS |
1536 | drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", |
1537 | intel_dp->aux.name, status); | |
9ee32fea DV |
1538 | ret = -ETIMEDOUT; |
1539 | goto out; | |
a4fc5ed6 KP |
1540 | } |
1541 | ||
1542 | /* Unload any bytes sent back from the other side */ | |
1543 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1544 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1545 | |
1546 | /* | |
1547 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1548 | * We have no idea of what happened so we return -EBUSY so | |
1549 | * drm layer takes care for the necessary retries. | |
1550 | */ | |
1551 | if (recv_bytes == 0 || recv_bytes > 20) { | |
bdc6114e | 1552 | drm_dbg_kms(&i915->drm, |
264c0247 VS |
1553 | "%s: Forbidden recv_bytes = %d on aux transaction\n", |
1554 | intel_dp->aux.name, recv_bytes); | |
14e01889 RV |
1555 | ret = -EBUSY; |
1556 | goto out; | |
1557 | } | |
1558 | ||
a4fc5ed6 KP |
1559 | if (recv_bytes > recv_size) |
1560 | recv_bytes = recv_size; | |
0206e353 | 1561 | |
4f7f7b7e | 1562 | for (i = 0; i < recv_bytes; i += 4) |
5a31d30b | 1563 | intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), |
a4f1289e | 1564 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1565 | |
9ee32fea DV |
1566 | ret = recv_bytes; |
1567 | out: | |
4d4dda48 | 1568 | cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 1569 | |
884f19e9 JN |
1570 | if (vdd) |
1571 | edp_panel_vdd_off(intel_dp, false); | |
1572 | ||
f39194a7 | 1573 | pps_unlock(intel_dp, pps_wakeref); |
5a31d30b | 1574 | intel_display_power_put_async(i915, aux_domain, aux_wakeref); |
e39b999a | 1575 | |
8c10e226 | 1576 | if (is_tc_port) |
7801f3b7 | 1577 | intel_tc_port_unlock(dig_port); |
8c10e226 | 1578 | |
9ee32fea | 1579 | return ret; |
a4fc5ed6 KP |
1580 | } |
1581 | ||
a6c8aff0 JN |
1582 | #define BARE_ADDRESS_SIZE 3 |
1583 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
32078b72 VS |
1584 | |
1585 | static void | |
1586 | intel_dp_aux_header(u8 txbuf[HEADER_SIZE], | |
1587 | const struct drm_dp_aux_msg *msg) | |
1588 | { | |
1589 | txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); | |
1590 | txbuf[1] = (msg->address >> 8) & 0xff; | |
1591 | txbuf[2] = msg->address & 0xff; | |
1592 | txbuf[3] = msg->size - 1; | |
1593 | } | |
1594 | ||
58418f0c SP |
1595 | static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) |
1596 | { | |
1597 | /* | |
1598 | * If we're trying to send the HDCP Aksv, we need to set a the Aksv | |
1599 | * select bit to inform the hardware to send the Aksv after our header | |
1600 | * since we can't access that data from software. | |
1601 | */ | |
1602 | if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && | |
1603 | msg->address == DP_AUX_HDCP_AKSV) | |
1604 | return DP_AUX_CH_CTL_AUX_AKSV_SELECT; | |
1605 | ||
1606 | return 0; | |
1607 | } | |
1608 | ||
9d1a1031 JN |
1609 | static ssize_t |
1610 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1611 | { |
9d1a1031 | 1612 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
4f360482 | 1613 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 | 1614 | u8 txbuf[20], rxbuf[20]; |
9d1a1031 | 1615 | size_t txsize, rxsize; |
58418f0c | 1616 | u32 flags = intel_dp_aux_xfer_flags(msg); |
a4fc5ed6 | 1617 | int ret; |
a4fc5ed6 | 1618 | |
32078b72 | 1619 | intel_dp_aux_header(txbuf, msg); |
46a5ae9f | 1620 | |
9d1a1031 JN |
1621 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1622 | case DP_AUX_NATIVE_WRITE: | |
1623 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1624 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1625 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1626 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1627 | |
4f360482 | 1628 | if (drm_WARN_ON(&i915->drm, txsize > 20)) |
9d1a1031 | 1629 | return -E2BIG; |
a4fc5ed6 | 1630 | |
4f360482 | 1631 | drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); |
dd788090 | 1632 | |
d81a67cc ID |
1633 | if (msg->buffer) |
1634 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1635 | |
f7606265 | 1636 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
58418f0c | 1637 | rxbuf, rxsize, flags); |
9d1a1031 JN |
1638 | if (ret > 0) { |
1639 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1640 | |
a1ddefd8 JN |
1641 | if (ret > 1) { |
1642 | /* Number of bytes written in a short write. */ | |
1643 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1644 | } else { | |
1645 | /* Return payload size. */ | |
1646 | ret = msg->size; | |
1647 | } | |
9d1a1031 JN |
1648 | } |
1649 | break; | |
46a5ae9f | 1650 | |
9d1a1031 JN |
1651 | case DP_AUX_NATIVE_READ: |
1652 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1653 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1654 | rxsize = msg->size + 1; |
a4fc5ed6 | 1655 | |
4f360482 | 1656 | if (drm_WARN_ON(&i915->drm, rxsize > 20)) |
9d1a1031 | 1657 | return -E2BIG; |
a4fc5ed6 | 1658 | |
f7606265 | 1659 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
58418f0c | 1660 | rxbuf, rxsize, flags); |
9d1a1031 JN |
1661 | if (ret > 0) { |
1662 | msg->reply = rxbuf[0] >> 4; | |
1663 | /* | |
1664 | * Assume happy day, and copy the data. The caller is | |
1665 | * expected to check msg->reply before touching it. | |
1666 | * | |
1667 | * Return payload size. | |
1668 | */ | |
1669 | ret--; | |
1670 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1671 | } |
9d1a1031 JN |
1672 | break; |
1673 | ||
1674 | default: | |
1675 | ret = -EINVAL; | |
1676 | break; | |
a4fc5ed6 | 1677 | } |
f51a44b9 | 1678 | |
9d1a1031 | 1679 | return ret; |
a4fc5ed6 KP |
1680 | } |
1681 | ||
8f7ce038 | 1682 | |
4904fa66 | 1683 | static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) |
da00bdcf | 1684 | { |
de25eb7f | 1685 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1686 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1687 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1688 | |
bdabdb63 VS |
1689 | switch (aux_ch) { |
1690 | case AUX_CH_B: | |
1691 | case AUX_CH_C: | |
1692 | case AUX_CH_D: | |
1693 | return DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1694 | default: |
bdabdb63 VS |
1695 | MISSING_CASE(aux_ch); |
1696 | return DP_AUX_CH_CTL(AUX_CH_B); | |
da00bdcf VS |
1697 | } |
1698 | } | |
1699 | ||
4904fa66 | 1700 | static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) |
330e20ec | 1701 | { |
de25eb7f | 1702 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1703 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1704 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1705 | |
bdabdb63 VS |
1706 | switch (aux_ch) { |
1707 | case AUX_CH_B: | |
1708 | case AUX_CH_C: | |
1709 | case AUX_CH_D: | |
1710 | return DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1711 | default: |
bdabdb63 VS |
1712 | MISSING_CASE(aux_ch); |
1713 | return DP_AUX_CH_DATA(AUX_CH_B, index); | |
330e20ec VS |
1714 | } |
1715 | } | |
1716 | ||
4904fa66 | 1717 | static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1718 | { |
de25eb7f | 1719 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1720 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1721 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1722 | |
bdabdb63 VS |
1723 | switch (aux_ch) { |
1724 | case AUX_CH_A: | |
1725 | return DP_AUX_CH_CTL(aux_ch); | |
1726 | case AUX_CH_B: | |
1727 | case AUX_CH_C: | |
1728 | case AUX_CH_D: | |
1729 | return PCH_DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1730 | default: |
bdabdb63 VS |
1731 | MISSING_CASE(aux_ch); |
1732 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1733 | } |
1734 | } | |
1735 | ||
4904fa66 | 1736 | static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1737 | { |
de25eb7f | 1738 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1739 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1740 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1741 | |
bdabdb63 VS |
1742 | switch (aux_ch) { |
1743 | case AUX_CH_A: | |
1744 | return DP_AUX_CH_DATA(aux_ch, index); | |
1745 | case AUX_CH_B: | |
1746 | case AUX_CH_C: | |
1747 | case AUX_CH_D: | |
1748 | return PCH_DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1749 | default: |
bdabdb63 VS |
1750 | MISSING_CASE(aux_ch); |
1751 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1752 | } |
1753 | } | |
1754 | ||
4904fa66 | 1755 | static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1756 | { |
de25eb7f | 1757 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1758 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1759 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1760 | |
bdabdb63 VS |
1761 | switch (aux_ch) { |
1762 | case AUX_CH_A: | |
1763 | case AUX_CH_B: | |
1764 | case AUX_CH_C: | |
1765 | case AUX_CH_D: | |
bb187e93 | 1766 | case AUX_CH_E: |
bdabdb63 | 1767 | case AUX_CH_F: |
eb8de23c | 1768 | case AUX_CH_G: |
bdabdb63 | 1769 | return DP_AUX_CH_CTL(aux_ch); |
da00bdcf | 1770 | default: |
bdabdb63 VS |
1771 | MISSING_CASE(aux_ch); |
1772 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1773 | } |
1774 | } | |
1775 | ||
4904fa66 | 1776 | static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1777 | { |
de25eb7f | 1778 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1779 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1780 | enum aux_ch aux_ch = dig_port->aux_ch; | |
4904fa66 | 1781 | |
bdabdb63 VS |
1782 | switch (aux_ch) { |
1783 | case AUX_CH_A: | |
1784 | case AUX_CH_B: | |
1785 | case AUX_CH_C: | |
1786 | case AUX_CH_D: | |
bb187e93 | 1787 | case AUX_CH_E: |
bdabdb63 | 1788 | case AUX_CH_F: |
eb8de23c | 1789 | case AUX_CH_G: |
bdabdb63 | 1790 | return DP_AUX_CH_DATA(aux_ch, index); |
330e20ec | 1791 | default: |
bdabdb63 VS |
1792 | MISSING_CASE(aux_ch); |
1793 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1794 | } |
1795 | } | |
1796 | ||
91e939ae VS |
1797 | static void |
1798 | intel_dp_aux_fini(struct intel_dp *intel_dp) | |
1799 | { | |
1800 | kfree(intel_dp->aux.name); | |
1801 | } | |
1802 | ||
1803 | static void | |
1804 | intel_dp_aux_init(struct intel_dp *intel_dp) | |
330e20ec | 1805 | { |
de25eb7f | 1806 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
563d22a0 ID |
1807 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1808 | struct intel_encoder *encoder = &dig_port->base; | |
91e939ae | 1809 | |
4904fa66 VS |
1810 | if (INTEL_GEN(dev_priv) >= 9) { |
1811 | intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; | |
1812 | intel_dp->aux_ch_data_reg = skl_aux_data_reg; | |
1813 | } else if (HAS_PCH_SPLIT(dev_priv)) { | |
1814 | intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; | |
1815 | intel_dp->aux_ch_data_reg = ilk_aux_data_reg; | |
1816 | } else { | |
1817 | intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; | |
1818 | intel_dp->aux_ch_data_reg = g4x_aux_data_reg; | |
1819 | } | |
330e20ec | 1820 | |
91e939ae VS |
1821 | if (INTEL_GEN(dev_priv) >= 9) |
1822 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
1823 | else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
1824 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
1825 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1826 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
1827 | else | |
1828 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; | |
bdabdb63 | 1829 | |
91e939ae VS |
1830 | if (INTEL_GEN(dev_priv) >= 9) |
1831 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
1832 | else | |
1833 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; | |
ab2c0672 | 1834 | |
7a418e34 | 1835 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1836 | |
7a418e34 | 1837 | /* Failure to allocate our preferred name is not critical */ |
a87e692a VS |
1838 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c", |
1839 | aux_ch_name(dig_port->aux_ch), | |
bdabdb63 | 1840 | port_name(encoder->port)); |
9d1a1031 | 1841 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1842 | } |
1843 | ||
e588fa18 | 1844 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1845 | { |
fc603ca7 | 1846 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
e588fa18 | 1847 | |
fc603ca7 | 1848 | return max_rate >= 540000; |
ed63baaf TS |
1849 | } |
1850 | ||
2edd5327 MN |
1851 | bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) |
1852 | { | |
1853 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; | |
1854 | ||
1855 | return max_rate >= 810000; | |
1856 | } | |
1857 | ||
c6bb3538 DV |
1858 | static void |
1859 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1860 | struct intel_crtc_state *pipe_config) |
c6bb3538 | 1861 | { |
2f773477 | 1862 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9dd4ffdf CML |
1863 | const struct dp_link_dpll *divisor = NULL; |
1864 | int i, count = 0; | |
c6bb3538 | 1865 | |
9beb5fea | 1866 | if (IS_G4X(dev_priv)) { |
45101e93 VS |
1867 | divisor = g4x_dpll; |
1868 | count = ARRAY_SIZE(g4x_dpll); | |
6e266956 | 1869 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1870 | divisor = pch_dpll; |
1871 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1872 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1873 | divisor = chv_dpll; |
1874 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1875 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1876 | divisor = vlv_dpll; |
1877 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1878 | } |
9dd4ffdf CML |
1879 | |
1880 | if (divisor && count) { | |
1881 | for (i = 0; i < count; i++) { | |
840b32b7 | 1882 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1883 | pipe_config->dpll = divisor[i].dpll; |
1884 | pipe_config->clock_set = true; | |
1885 | break; | |
1886 | } | |
1887 | } | |
c6bb3538 DV |
1888 | } |
1889 | } | |
1890 | ||
0336400e VS |
1891 | static void snprintf_int_array(char *str, size_t len, |
1892 | const int *array, int nelem) | |
1893 | { | |
1894 | int i; | |
1895 | ||
1896 | str[0] = '\0'; | |
1897 | ||
1898 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1899 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1900 | if (r >= len) |
1901 | return; | |
1902 | str += r; | |
1903 | len -= r; | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1908 | { | |
af67009c | 1909 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
0336400e VS |
1910 | char str[128]; /* FIXME: too big for stack? */ |
1911 | ||
bdbf43d7 | 1912 | if (!drm_debug_enabled(DRM_UT_KMS)) |
0336400e VS |
1913 | return; |
1914 | ||
55cfc580 JN |
1915 | snprintf_int_array(str, sizeof(str), |
1916 | intel_dp->source_rates, intel_dp->num_source_rates); | |
af67009c | 1917 | drm_dbg_kms(&i915->drm, "source rates: %s\n", str); |
0336400e | 1918 | |
68f357cb JN |
1919 | snprintf_int_array(str, sizeof(str), |
1920 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
af67009c | 1921 | drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); |
0336400e | 1922 | |
975ee5fc JN |
1923 | snprintf_int_array(str, sizeof(str), |
1924 | intel_dp->common_rates, intel_dp->num_common_rates); | |
af67009c | 1925 | drm_dbg_kms(&i915->drm, "common rates: %s\n", str); |
0336400e VS |
1926 | } |
1927 | ||
50fec21a VS |
1928 | int |
1929 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1930 | { | |
4f360482 | 1931 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
50fec21a VS |
1932 | int len; |
1933 | ||
e6c0c64a | 1934 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
4f360482 | 1935 | if (drm_WARN_ON(&i915->drm, len <= 0)) |
50fec21a VS |
1936 | return 162000; |
1937 | ||
975ee5fc | 1938 | return intel_dp->common_rates[len - 1]; |
50fec21a VS |
1939 | } |
1940 | ||
ed4e9c1d VS |
1941 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1942 | { | |
4f360482 | 1943 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
8001b754 JN |
1944 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1945 | intel_dp->num_sink_rates, rate); | |
b5c72b20 | 1946 | |
4f360482 | 1947 | if (drm_WARN_ON(&i915->drm, i < 0)) |
b5c72b20 JN |
1948 | i = 0; |
1949 | ||
1950 | return i; | |
ed4e9c1d VS |
1951 | } |
1952 | ||
94223d04 | 1953 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
830de422 | 1954 | u8 *link_bw, u8 *rate_select) |
04a60f9f | 1955 | { |
68f357cb JN |
1956 | /* eDP 1.4 rate select method. */ |
1957 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1958 | *link_bw = 0; |
1959 | *rate_select = | |
1960 | intel_dp_rate_select(intel_dp, port_clock); | |
1961 | } else { | |
1962 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1963 | *rate_select = 0; | |
1964 | } | |
1965 | } | |
1966 | ||
240999cf | 1967 | static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, |
a4a15777 MN |
1968 | const struct intel_crtc_state *pipe_config) |
1969 | { | |
1970 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
1971 | ||
9770f220 MTP |
1972 | /* On TGL, FEC is supported on all Pipes */ |
1973 | if (INTEL_GEN(dev_priv) >= 12) | |
1974 | return true; | |
1975 | ||
1976 | if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) | |
1977 | return true; | |
1978 | ||
1979 | return false; | |
240999cf AS |
1980 | } |
1981 | ||
1982 | static bool intel_dp_supports_fec(struct intel_dp *intel_dp, | |
1983 | const struct intel_crtc_state *pipe_config) | |
1984 | { | |
1985 | return intel_dp_source_supports_fec(intel_dp, pipe_config) && | |
1986 | drm_dp_sink_supports_fec(intel_dp->fec_capable); | |
1987 | } | |
1988 | ||
a4a15777 | 1989 | static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, |
deaaff49 | 1990 | const struct intel_crtc_state *crtc_state) |
a4a15777 | 1991 | { |
deaaff49 JN |
1992 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
1993 | ||
1994 | if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable) | |
240999cf AS |
1995 | return false; |
1996 | ||
deaaff49 | 1997 | return intel_dsc_source_support(encoder, crtc_state) && |
a4a15777 MN |
1998 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); |
1999 | } | |
2000 | ||
bc7ca6a6 VS |
2001 | static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp, |
2002 | const struct intel_crtc_state *crtc_state) | |
2003 | { | |
181567aa VS |
2004 | return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
2005 | (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && | |
2006 | intel_dp->dfp.ycbcr_444_to_420); | |
bc7ca6a6 VS |
2007 | } |
2008 | ||
2009 | static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp, | |
2010 | const struct intel_crtc_state *crtc_state, int bpc) | |
2011 | { | |
2012 | int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8; | |
2013 | ||
2014 | if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) | |
2015 | clock /= 2; | |
2016 | ||
2017 | return clock; | |
2018 | } | |
2019 | ||
2020 | static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp, | |
2021 | const struct intel_crtc_state *crtc_state, int bpc) | |
2022 | { | |
2023 | int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc); | |
2024 | ||
2025 | if (intel_dp->dfp.min_tmds_clock && | |
2026 | tmds_clock < intel_dp->dfp.min_tmds_clock) | |
2027 | return false; | |
2028 | ||
2029 | if (intel_dp->dfp.max_tmds_clock && | |
2030 | tmds_clock > intel_dp->dfp.max_tmds_clock) | |
2031 | return false; | |
2032 | ||
2033 | return true; | |
2034 | } | |
2035 | ||
2036 | static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp, | |
2037 | const struct intel_crtc_state *crtc_state, | |
2038 | int bpc) | |
2039 | { | |
bc7ca6a6 | 2040 | |
181567aa VS |
2041 | return intel_hdmi_deep_color_possible(crtc_state, bpc, |
2042 | intel_dp->has_hdmi_sink, | |
2043 | intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) && | |
bc7ca6a6 VS |
2044 | intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc); |
2045 | } | |
2046 | ||
2047 | static int intel_dp_max_bpp(struct intel_dp *intel_dp, | |
2048 | const struct intel_crtc_state *crtc_state) | |
f9bb705e | 2049 | { |
de25eb7f | 2050 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ef32659a | 2051 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
bc7ca6a6 | 2052 | int bpp, bpc; |
f9bb705e | 2053 | |
bc7ca6a6 | 2054 | bpc = crtc_state->pipe_bpp / 3; |
f9bb705e | 2055 | |
530df3c0 | 2056 | if (intel_dp->dfp.max_bpc) |
bc7ca6a6 VS |
2057 | bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); |
2058 | ||
2059 | if (intel_dp->dfp.min_tmds_clock) { | |
2060 | for (; bpc >= 10; bpc -= 2) { | |
2061 | if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc)) | |
2062 | break; | |
2063 | } | |
2064 | } | |
f9bb705e | 2065 | |
bc7ca6a6 | 2066 | bpp = bpc * 3; |
ef32659a JN |
2067 | if (intel_dp_is_edp(intel_dp)) { |
2068 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
2069 | if (intel_connector->base.display_info.bpc == 0 && | |
2070 | dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { | |
bdc6114e WK |
2071 | drm_dbg_kms(&dev_priv->drm, |
2072 | "clamping bpp for eDP panel to BIOS-provided %i\n", | |
2073 | dev_priv->vbt.edp.bpp); | |
ef32659a JN |
2074 | bpp = dev_priv->vbt.edp.bpp; |
2075 | } | |
2076 | } | |
2077 | ||
f9bb705e MK |
2078 | return bpp; |
2079 | } | |
2080 | ||
a4971453 | 2081 | /* Adjust link config limits based on compliance test requests. */ |
f1477219 | 2082 | void |
a4971453 JN |
2083 | intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, |
2084 | struct intel_crtc_state *pipe_config, | |
2085 | struct link_config_limits *limits) | |
2086 | { | |
af67009c JN |
2087 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
2088 | ||
a4971453 JN |
2089 | /* For DP Compliance we override the computed bpp for the pipe */ |
2090 | if (intel_dp->compliance.test_data.bpc != 0) { | |
2091 | int bpp = 3 * intel_dp->compliance.test_data.bpc; | |
2092 | ||
2093 | limits->min_bpp = limits->max_bpp = bpp; | |
2094 | pipe_config->dither_force_disable = bpp == 6 * 3; | |
2095 | ||
af67009c | 2096 | drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); |
a4971453 JN |
2097 | } |
2098 | ||
2099 | /* Use values requested by Compliance Test Request */ | |
2100 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
2101 | int index; | |
2102 | ||
2103 | /* Validate the compliance test data since max values | |
2104 | * might have changed due to link train fallback. | |
2105 | */ | |
2106 | if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, | |
2107 | intel_dp->compliance.test_lane_count)) { | |
2108 | index = intel_dp_rate_index(intel_dp->common_rates, | |
2109 | intel_dp->num_common_rates, | |
2110 | intel_dp->compliance.test_link_rate); | |
2111 | if (index >= 0) | |
2112 | limits->min_clock = limits->max_clock = index; | |
2113 | limits->min_lane_count = limits->max_lane_count = | |
2114 | intel_dp->compliance.test_lane_count; | |
2115 | } | |
2116 | } | |
2117 | } | |
2118 | ||
3acd115d | 2119 | /* Optimize link config in order: max bpp, min clock, min lanes */ |
204474a6 | 2120 | static int |
3acd115d JN |
2121 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, |
2122 | struct intel_crtc_state *pipe_config, | |
2123 | const struct link_config_limits *limits) | |
2124 | { | |
1326a92c | 2125 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
3acd115d JN |
2126 | int bpp, clock, lane_count; |
2127 | int mode_rate, link_clock, link_avail; | |
2128 | ||
2129 | for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { | |
f1bce832 | 2130 | int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); |
ddb3d12a | 2131 | |
3acd115d | 2132 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
ddb3d12a | 2133 | output_bpp); |
3acd115d JN |
2134 | |
2135 | for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { | |
2136 | for (lane_count = limits->min_lane_count; | |
2137 | lane_count <= limits->max_lane_count; | |
2138 | lane_count <<= 1) { | |
2139 | link_clock = intel_dp->common_rates[clock]; | |
2140 | link_avail = intel_dp_max_data_rate(link_clock, | |
2141 | lane_count); | |
2142 | ||
2143 | if (mode_rate <= link_avail) { | |
2144 | pipe_config->lane_count = lane_count; | |
2145 | pipe_config->pipe_bpp = bpp; | |
2146 | pipe_config->port_clock = link_clock; | |
2147 | ||
204474a6 | 2148 | return 0; |
3acd115d JN |
2149 | } |
2150 | } | |
2151 | } | |
2152 | } | |
2153 | ||
204474a6 | 2154 | return -EINVAL; |
3acd115d JN |
2155 | } |
2156 | ||
a4a15777 MN |
2157 | static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) |
2158 | { | |
2159 | int i, num_bpc; | |
2160 | u8 dsc_bpc[3] = {0}; | |
2161 | ||
2162 | num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, | |
2163 | dsc_bpc); | |
2164 | for (i = 0; i < num_bpc; i++) { | |
2165 | if (dsc_max_bpc >= dsc_bpc[i]) | |
2166 | return dsc_bpc[i] * 3; | |
2167 | } | |
2168 | ||
2169 | return 0; | |
2170 | } | |
2171 | ||
7a7b5be9 JN |
2172 | #define DSC_SUPPORTED_VERSION_MIN 1 |
2173 | ||
2174 | static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, | |
2175 | struct intel_crtc_state *crtc_state) | |
2176 | { | |
af67009c | 2177 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
b7d02c3a | 2178 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7a7b5be9 JN |
2179 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; |
2180 | u8 line_buf_depth; | |
2181 | int ret; | |
2182 | ||
2183 | ret = intel_dsc_compute_params(encoder, crtc_state); | |
2184 | if (ret) | |
2185 | return ret; | |
2186 | ||
c42c38ec JN |
2187 | /* |
2188 | * Slice Height of 8 works for all currently available panels. So start | |
2189 | * with that if pic_height is an integral multiple of 8. Eventually add | |
2190 | * logic to try multiple slice heights. | |
2191 | */ | |
2192 | if (vdsc_cfg->pic_height % 8 == 0) | |
2193 | vdsc_cfg->slice_height = 8; | |
2194 | else if (vdsc_cfg->pic_height % 4 == 0) | |
2195 | vdsc_cfg->slice_height = 4; | |
2196 | else | |
2197 | vdsc_cfg->slice_height = 2; | |
2198 | ||
7a7b5be9 JN |
2199 | vdsc_cfg->dsc_version_major = |
2200 | (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & | |
2201 | DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; | |
2202 | vdsc_cfg->dsc_version_minor = | |
2203 | min(DSC_SUPPORTED_VERSION_MIN, | |
2204 | (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & | |
2205 | DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); | |
2206 | ||
2207 | vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & | |
2208 | DP_DSC_RGB; | |
2209 | ||
2210 | line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); | |
2211 | if (!line_buf_depth) { | |
af67009c JN |
2212 | drm_dbg_kms(&i915->drm, |
2213 | "DSC Sink Line Buffer Depth invalid\n"); | |
7a7b5be9 JN |
2214 | return -EINVAL; |
2215 | } | |
2216 | ||
2217 | if (vdsc_cfg->dsc_version_minor == 2) | |
2218 | vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? | |
2219 | DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; | |
2220 | else | |
2221 | vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? | |
2222 | DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; | |
2223 | ||
2224 | vdsc_cfg->block_pred_enable = | |
2225 | intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & | |
2226 | DP_DSC_BLK_PREDICTION_IS_SUPPORTED; | |
2227 | ||
2228 | return drm_dsc_compute_rc_parameters(vdsc_cfg); | |
2229 | } | |
2230 | ||
204474a6 LP |
2231 | static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
2232 | struct intel_crtc_state *pipe_config, | |
2233 | struct drm_connector_state *conn_state, | |
2234 | struct link_config_limits *limits) | |
a4a15777 MN |
2235 | { |
2236 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2237 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
0c1abaa7 VS |
2238 | const struct drm_display_mode *adjusted_mode = |
2239 | &pipe_config->hw.adjusted_mode; | |
a4a15777 MN |
2240 | u8 dsc_max_bpc; |
2241 | int pipe_bpp; | |
204474a6 | 2242 | int ret; |
a4a15777 | 2243 | |
6fd3134a VS |
2244 | pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && |
2245 | intel_dp_supports_fec(intel_dp, pipe_config); | |
2246 | ||
a4a15777 | 2247 | if (!intel_dp_supports_dsc(intel_dp, pipe_config)) |
204474a6 | 2248 | return -EINVAL; |
a4a15777 | 2249 | |
cee508a0 AS |
2250 | /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ |
2251 | if (INTEL_GEN(dev_priv) >= 12) | |
2252 | dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); | |
2253 | else | |
2254 | dsc_max_bpc = min_t(u8, 10, | |
2255 | conn_state->max_requested_bpc); | |
a4a15777 MN |
2256 | |
2257 | pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); | |
cee508a0 AS |
2258 | |
2259 | /* Min Input BPC for ICL+ is 8 */ | |
2260 | if (pipe_bpp < 8 * 3) { | |
bdc6114e WK |
2261 | drm_dbg_kms(&dev_priv->drm, |
2262 | "No DSC support for less than 8bpc\n"); | |
204474a6 | 2263 | return -EINVAL; |
a4a15777 MN |
2264 | } |
2265 | ||
2266 | /* | |
2267 | * For now enable DSC for max bpp, max link rate, max lane count. | |
2268 | * Optimize this later for the minimum possible link rate/lane count | |
2269 | * with DSC enabled for the requested mode. | |
2270 | */ | |
2271 | pipe_config->pipe_bpp = pipe_bpp; | |
2272 | pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; | |
2273 | pipe_config->lane_count = limits->max_lane_count; | |
2274 | ||
2275 | if (intel_dp_is_edp(intel_dp)) { | |
010663a6 | 2276 | pipe_config->dsc.compressed_bpp = |
a4a15777 MN |
2277 | min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, |
2278 | pipe_config->pipe_bpp); | |
010663a6 | 2279 | pipe_config->dsc.slice_count = |
a4a15777 MN |
2280 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
2281 | true); | |
2282 | } else { | |
2283 | u16 dsc_max_output_bpp; | |
2284 | u8 dsc_dp_slice_count; | |
2285 | ||
2286 | dsc_max_output_bpp = | |
45d3c5cd MR |
2287 | intel_dp_dsc_get_output_bpp(dev_priv, |
2288 | pipe_config->port_clock, | |
a4a15777 MN |
2289 | pipe_config->lane_count, |
2290 | adjusted_mode->crtc_clock, | |
2291 | adjusted_mode->crtc_hdisplay); | |
2292 | dsc_dp_slice_count = | |
2293 | intel_dp_dsc_get_slice_count(intel_dp, | |
2294 | adjusted_mode->crtc_clock, | |
2295 | adjusted_mode->crtc_hdisplay); | |
2296 | if (!dsc_max_output_bpp || !dsc_dp_slice_count) { | |
bdc6114e WK |
2297 | drm_dbg_kms(&dev_priv->drm, |
2298 | "Compressed BPP/Slice Count not supported\n"); | |
204474a6 | 2299 | return -EINVAL; |
a4a15777 | 2300 | } |
010663a6 | 2301 | pipe_config->dsc.compressed_bpp = min_t(u16, |
a4a15777 MN |
2302 | dsc_max_output_bpp >> 4, |
2303 | pipe_config->pipe_bpp); | |
010663a6 | 2304 | pipe_config->dsc.slice_count = dsc_dp_slice_count; |
a4a15777 MN |
2305 | } |
2306 | /* | |
2307 | * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate | |
2308 | * is greater than the maximum Cdclock and if slice count is even | |
2309 | * then we need to use 2 VDSC instances. | |
2310 | */ | |
2311 | if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { | |
010663a6 JN |
2312 | if (pipe_config->dsc.slice_count > 1) { |
2313 | pipe_config->dsc.dsc_split = true; | |
a4a15777 | 2314 | } else { |
bdc6114e WK |
2315 | drm_dbg_kms(&dev_priv->drm, |
2316 | "Cannot split stream to use 2 VDSC instances\n"); | |
204474a6 | 2317 | return -EINVAL; |
a4a15777 MN |
2318 | } |
2319 | } | |
204474a6 | 2320 | |
7a7b5be9 | 2321 | ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); |
204474a6 | 2322 | if (ret < 0) { |
bdc6114e WK |
2323 | drm_dbg_kms(&dev_priv->drm, |
2324 | "Cannot compute valid DSC parameters for Input Bpp = %d " | |
2325 | "Compressed BPP = %d\n", | |
2326 | pipe_config->pipe_bpp, | |
2327 | pipe_config->dsc.compressed_bpp); | |
204474a6 | 2328 | return ret; |
168243c1 | 2329 | } |
204474a6 | 2330 | |
010663a6 | 2331 | pipe_config->dsc.compression_enable = true; |
bdc6114e WK |
2332 | drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " |
2333 | "Compressed Bpp = %d Slice Count = %d\n", | |
2334 | pipe_config->pipe_bpp, | |
2335 | pipe_config->dsc.compressed_bpp, | |
2336 | pipe_config->dsc.slice_count); | |
a4a15777 | 2337 | |
204474a6 | 2338 | return 0; |
a4a15777 MN |
2339 | } |
2340 | ||
204474a6 | 2341 | static int |
981a63eb | 2342 | intel_dp_compute_link_config(struct intel_encoder *encoder, |
a4a15777 MN |
2343 | struct intel_crtc_state *pipe_config, |
2344 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 2345 | { |
af67009c | 2346 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
0c1abaa7 VS |
2347 | const struct drm_display_mode *adjusted_mode = |
2348 | &pipe_config->hw.adjusted_mode; | |
b7d02c3a | 2349 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7c2781e4 | 2350 | struct link_config_limits limits; |
94ca719e | 2351 | int common_len; |
204474a6 | 2352 | int ret; |
7c2781e4 | 2353 | |
975ee5fc | 2354 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
e6c0c64a | 2355 | intel_dp->max_link_rate); |
a8f3ef61 SJ |
2356 | |
2357 | /* No common link rates between source and sink */ | |
3a47ae20 | 2358 | drm_WARN_ON(encoder->base.dev, common_len <= 0); |
a8f3ef61 | 2359 | |
7c2781e4 JN |
2360 | limits.min_clock = 0; |
2361 | limits.max_clock = common_len - 1; | |
2362 | ||
2363 | limits.min_lane_count = 1; | |
2364 | limits.max_lane_count = intel_dp_max_lane_count(intel_dp); | |
2365 | ||
f1bce832 | 2366 | limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); |
bc7ca6a6 | 2367 | limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); |
a4fc5ed6 | 2368 | |
f11cb1c1 | 2369 | if (intel_dp_is_edp(intel_dp)) { |
344c5bbc JN |
2370 | /* |
2371 | * Use the maximum clock and number of lanes the eDP panel | |
f11cb1c1 JN |
2372 | * advertizes being capable of. The panels are generally |
2373 | * designed to support only a single clock and lane | |
2374 | * configuration, and typically these values correspond to the | |
2375 | * native resolution of the panel. | |
344c5bbc | 2376 | */ |
7c2781e4 JN |
2377 | limits.min_lane_count = limits.max_lane_count; |
2378 | limits.min_clock = limits.max_clock; | |
7984211e | 2379 | } |
657445fe | 2380 | |
a4971453 JN |
2381 | intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |
2382 | ||
af67009c JN |
2383 | drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " |
2384 | "max rate %d max bpp %d pixel clock %iKHz\n", | |
2385 | limits.max_lane_count, | |
2386 | intel_dp->common_rates[limits.max_clock], | |
2387 | limits.max_bpp, adjusted_mode->crtc_clock); | |
7c2781e4 | 2388 | |
f11cb1c1 JN |
2389 | /* |
2390 | * Optimize for slow and wide. This is the place to add alternative | |
2391 | * optimization policy. | |
2392 | */ | |
2393 | ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); | |
a4a15777 MN |
2394 | |
2395 | /* enable compression if the mode doesn't fit available BW */ | |
af67009c | 2396 | drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); |
204474a6 LP |
2397 | if (ret || intel_dp->force_dsc_en) { |
2398 | ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, | |
2399 | conn_state, &limits); | |
2400 | if (ret < 0) | |
2401 | return ret; | |
7769db58 | 2402 | } |
981a63eb | 2403 | |
010663a6 | 2404 | if (pipe_config->dsc.compression_enable) { |
af67009c JN |
2405 | drm_dbg_kms(&i915->drm, |
2406 | "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", | |
2407 | pipe_config->lane_count, pipe_config->port_clock, | |
2408 | pipe_config->pipe_bpp, | |
2409 | pipe_config->dsc.compressed_bpp); | |
2410 | ||
2411 | drm_dbg_kms(&i915->drm, | |
2412 | "DP link rate required %i available %i\n", | |
2413 | intel_dp_link_required(adjusted_mode->crtc_clock, | |
2414 | pipe_config->dsc.compressed_bpp), | |
2415 | intel_dp_max_data_rate(pipe_config->port_clock, | |
2416 | pipe_config->lane_count)); | |
a4a15777 | 2417 | } else { |
af67009c JN |
2418 | drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", |
2419 | pipe_config->lane_count, pipe_config->port_clock, | |
2420 | pipe_config->pipe_bpp); | |
a4a15777 | 2421 | |
af67009c JN |
2422 | drm_dbg_kms(&i915->drm, |
2423 | "DP link rate required %i available %i\n", | |
2424 | intel_dp_link_required(adjusted_mode->crtc_clock, | |
2425 | pipe_config->pipe_bpp), | |
2426 | intel_dp_max_data_rate(pipe_config->port_clock, | |
2427 | pipe_config->lane_count)); | |
a4a15777 | 2428 | } |
204474a6 | 2429 | return 0; |
981a63eb JN |
2430 | } |
2431 | ||
8e9d645c | 2432 | static int |
773bd825 | 2433 | intel_dp_ycbcr420_config(struct intel_crtc_state *crtc_state, |
4cecc7c0 | 2434 | const struct drm_connector_state *conn_state) |
8e9d645c | 2435 | { |
4cecc7c0 | 2436 | struct drm_connector *connector = conn_state->connector; |
8e9d645c | 2437 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 2438 | &crtc_state->hw.adjusted_mode; |
8e9d645c | 2439 | |
181567aa | 2440 | if (!connector->ycbcr_420_allowed) |
8e9d645c GM |
2441 | return 0; |
2442 | ||
773bd825 | 2443 | crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode); |
181567aa | 2444 | |
773bd825 | 2445 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) |
181567aa | 2446 | return 0; |
8e9d645c | 2447 | |
d7ff281c | 2448 | return intel_pch_panel_fitting(crtc_state, conn_state); |
8e9d645c GM |
2449 | } |
2450 | ||
37aa52bf VS |
2451 | bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
2452 | const struct drm_connector_state *conn_state) | |
2453 | { | |
2454 | const struct intel_digital_connector_state *intel_conn_state = | |
2455 | to_intel_digital_connector_state(conn_state); | |
2456 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 2457 | &crtc_state->hw.adjusted_mode; |
37aa52bf | 2458 | |
cae154fc VS |
2459 | /* |
2460 | * Our YCbCr output is always limited range. | |
2461 | * crtc_state->limited_color_range only applies to RGB, | |
2462 | * and it must never be set for YCbCr or we risk setting | |
2463 | * some conflicting bits in PIPECONF which will mess up | |
2464 | * the colors on the monitor. | |
2465 | */ | |
2466 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
2467 | return false; | |
2468 | ||
37aa52bf VS |
2469 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
2470 | /* | |
2471 | * See: | |
2472 | * CEA-861-E - 5.1 Default Encoding Parameters | |
2473 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
2474 | */ | |
2475 | return crtc_state->pipe_bpp != 18 && | |
2476 | drm_default_rgb_quant_range(adjusted_mode) == | |
2477 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
2478 | } else { | |
2479 | return intel_conn_state->broadcast_rgb == | |
2480 | INTEL_BROADCAST_RGB_LIMITED; | |
2481 | } | |
2482 | } | |
2483 | ||
07130981 KV |
2484 | static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, |
2485 | enum port port) | |
2486 | { | |
2487 | if (IS_G4X(dev_priv)) | |
2488 | return false; | |
2489 | if (INTEL_GEN(dev_priv) < 12 && port == PORT_A) | |
2490 | return false; | |
2491 | ||
2492 | return true; | |
2493 | } | |
2494 | ||
9799c4c3 GM |
2495 | static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, |
2496 | const struct drm_connector_state *conn_state, | |
2497 | struct drm_dp_vsc_sdp *vsc) | |
2498 | { | |
2499 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
2500 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
2501 | ||
2502 | /* | |
2503 | * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 | |
2504 | * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ | |
2505 | * Colorimetry Format indication. | |
2506 | */ | |
2507 | vsc->revision = 0x5; | |
2508 | vsc->length = 0x13; | |
2509 | ||
2510 | /* DP 1.4a spec, Table 2-120 */ | |
2511 | switch (crtc_state->output_format) { | |
2512 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
2513 | vsc->pixelformat = DP_PIXELFORMAT_YUV444; | |
2514 | break; | |
2515 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
2516 | vsc->pixelformat = DP_PIXELFORMAT_YUV420; | |
2517 | break; | |
2518 | case INTEL_OUTPUT_FORMAT_RGB: | |
2519 | default: | |
2520 | vsc->pixelformat = DP_PIXELFORMAT_RGB; | |
2521 | } | |
2522 | ||
2523 | switch (conn_state->colorspace) { | |
2524 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
2525 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; | |
2526 | break; | |
2527 | case DRM_MODE_COLORIMETRY_XVYCC_601: | |
2528 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; | |
2529 | break; | |
2530 | case DRM_MODE_COLORIMETRY_XVYCC_709: | |
2531 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; | |
2532 | break; | |
2533 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
2534 | vsc->colorimetry = DP_COLORIMETRY_SYCC_601; | |
2535 | break; | |
2536 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
2537 | vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; | |
2538 | break; | |
2539 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
2540 | vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; | |
2541 | break; | |
2542 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
2543 | vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; | |
2544 | break; | |
2545 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
2546 | vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; | |
2547 | break; | |
2548 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: | |
2549 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: | |
2550 | vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; | |
2551 | break; | |
2552 | default: | |
2553 | /* | |
2554 | * RGB->YCBCR color conversion uses the BT.709 | |
2555 | * color space. | |
2556 | */ | |
2557 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
2558 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; | |
2559 | else | |
2560 | vsc->colorimetry = DP_COLORIMETRY_DEFAULT; | |
2561 | break; | |
2562 | } | |
2563 | ||
2564 | vsc->bpc = crtc_state->pipe_bpp / 3; | |
2565 | ||
2566 | /* only RGB pixelformat supports 6 bpc */ | |
2567 | drm_WARN_ON(&dev_priv->drm, | |
2568 | vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); | |
2569 | ||
2570 | /* all YCbCr are always limited range */ | |
2571 | vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; | |
2572 | vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; | |
2573 | } | |
2574 | ||
2575 | static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, | |
2576 | struct intel_crtc_state *crtc_state, | |
2577 | const struct drm_connector_state *conn_state) | |
2578 | { | |
2579 | struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; | |
2580 | ||
cafac5a9 GM |
2581 | /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */ |
2582 | if (crtc_state->has_psr) | |
9799c4c3 GM |
2583 | return; |
2584 | ||
2585 | if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) | |
2586 | return; | |
2587 | ||
2588 | crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); | |
2589 | vsc->sdp_type = DP_SDP_VSC; | |
2590 | intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, | |
2591 | &crtc_state->infoframes.vsc); | |
2592 | } | |
2593 | ||
cafac5a9 GM |
2594 | void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, |
2595 | const struct intel_crtc_state *crtc_state, | |
2596 | const struct drm_connector_state *conn_state, | |
2597 | struct drm_dp_vsc_sdp *vsc) | |
2598 | { | |
2599 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
2600 | ||
2601 | vsc->sdp_type = DP_SDP_VSC; | |
2602 | ||
2603 | if (dev_priv->psr.psr2_enabled) { | |
2604 | if (dev_priv->psr.colorimetry_support && | |
2605 | intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { | |
2606 | /* [PSR2, +Colorimetry] */ | |
2607 | intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, | |
2608 | vsc); | |
2609 | } else { | |
2610 | /* | |
2611 | * [PSR2, -Colorimetry] | |
2612 | * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 | |
2613 | * 3D stereo + PSR/PSR2 + Y-coordinate. | |
2614 | */ | |
2615 | vsc->revision = 0x4; | |
2616 | vsc->length = 0xe; | |
2617 | } | |
2618 | } else { | |
2619 | /* | |
2620 | * [PSR1] | |
2621 | * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 | |
2622 | * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or | |
2623 | * higher). | |
2624 | */ | |
2625 | vsc->revision = 0x2; | |
2626 | vsc->length = 0x8; | |
2627 | } | |
2628 | } | |
2629 | ||
d1eed96d GM |
2630 | static void |
2631 | intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, | |
2632 | struct intel_crtc_state *crtc_state, | |
2633 | const struct drm_connector_state *conn_state) | |
2634 | { | |
2635 | int ret; | |
2636 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
2637 | struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; | |
2638 | ||
2639 | if (!conn_state->hdr_output_metadata) | |
2640 | return; | |
2641 | ||
2642 | ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); | |
2643 | ||
2644 | if (ret) { | |
2645 | drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); | |
2646 | return; | |
2647 | } | |
2648 | ||
2649 | crtc_state->infoframes.enable |= | |
2650 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); | |
2651 | } | |
2652 | ||
be2dd718 JRS |
2653 | static void |
2654 | intel_dp_drrs_compute_config(struct intel_dp *intel_dp, | |
2655 | struct intel_crtc_state *pipe_config, | |
2656 | int output_bpp, bool constant_n) | |
2657 | { | |
2658 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
2659 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
2660 | ||
2661 | /* | |
2662 | * DRRS and PSR can't be enable together, so giving preference to PSR | |
2663 | * as it allows more power-savings by complete shutting down display, | |
2664 | * so to guarantee this, intel_dp_drrs_compute_config() must be called | |
2665 | * after intel_psr_compute_config(). | |
2666 | */ | |
2667 | if (pipe_config->has_psr) | |
2668 | return; | |
2669 | ||
2670 | if (!intel_connector->panel.downclock_mode || | |
2671 | dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) | |
2672 | return; | |
2673 | ||
2674 | pipe_config->has_drrs = true; | |
2675 | intel_link_compute_m_n(output_bpp, pipe_config->lane_count, | |
2676 | intel_connector->panel.downclock_mode->clock, | |
2677 | pipe_config->port_clock, &pipe_config->dp_m2_n2, | |
2678 | constant_n, pipe_config->fec_enable); | |
2679 | } | |
2680 | ||
204474a6 | 2681 | int |
981a63eb JN |
2682 | intel_dp_compute_config(struct intel_encoder *encoder, |
2683 | struct intel_crtc_state *pipe_config, | |
2684 | struct drm_connector_state *conn_state) | |
2685 | { | |
2686 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1326a92c | 2687 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
b7d02c3a VS |
2688 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2689 | struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); | |
981a63eb | 2690 | enum port port = encoder->port; |
981a63eb JN |
2691 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
2692 | struct intel_digital_connector_state *intel_conn_state = | |
2693 | to_intel_digital_connector_state(conn_state); | |
0883ce81 | 2694 | bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, |
53ca2edc | 2695 | DP_DPCD_QUIRK_CONSTANT_N); |
8e9d645c | 2696 | int ret = 0, output_bpp; |
981a63eb JN |
2697 | |
2698 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) | |
2699 | pipe_config->has_pch_encoder = true; | |
2700 | ||
d9facae6 | 2701 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
0c06fa15 | 2702 | |
668b6c17 SS |
2703 | if (lspcon->active) |
2704 | lspcon_ycbcr420_config(&intel_connector->base, pipe_config); | |
8e9d645c | 2705 | else |
773bd825 | 2706 | ret = intel_dp_ycbcr420_config(pipe_config, conn_state); |
8e9d645c GM |
2707 | if (ret) |
2708 | return ret; | |
668b6c17 | 2709 | |
07130981 | 2710 | if (!intel_dp_port_has_audio(dev_priv, port)) |
981a63eb JN |
2711 | pipe_config->has_audio = false; |
2712 | else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2713 | pipe_config->has_audio = intel_dp->has_audio; | |
2714 | else | |
2715 | pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2716 | ||
2717 | if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { | |
d93fa1b4 JN |
2718 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
2719 | adjusted_mode); | |
981a63eb | 2720 | |
b2ae318a | 2721 | if (HAS_GMCH(dev_priv)) |
d7ff281c | 2722 | ret = intel_gmch_panel_fitting(pipe_config, conn_state); |
981a63eb | 2723 | else |
d7ff281c VS |
2724 | ret = intel_pch_panel_fitting(pipe_config, conn_state); |
2725 | if (ret) | |
2726 | return ret; | |
981a63eb JN |
2727 | } |
2728 | ||
e4dd27aa | 2729 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2730 | return -EINVAL; |
e4dd27aa | 2731 | |
b2ae318a | 2732 | if (HAS_GMCH(dev_priv) && |
981a63eb | 2733 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
204474a6 | 2734 | return -EINVAL; |
981a63eb JN |
2735 | |
2736 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
204474a6 | 2737 | return -EINVAL; |
981a63eb | 2738 | |
98c93394 VS |
2739 | if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) |
2740 | return -EINVAL; | |
2741 | ||
204474a6 LP |
2742 | ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); |
2743 | if (ret < 0) | |
2744 | return ret; | |
981a63eb | 2745 | |
37aa52bf VS |
2746 | pipe_config->limited_color_range = |
2747 | intel_dp_limited_color_range(pipe_config, conn_state); | |
55bc60db | 2748 | |
010663a6 JN |
2749 | if (pipe_config->dsc.compression_enable) |
2750 | output_bpp = pipe_config->dsc.compressed_bpp; | |
a4a15777 | 2751 | else |
f1bce832 VS |
2752 | output_bpp = intel_dp_output_bpp(pipe_config->output_format, |
2753 | pipe_config->pipe_bpp); | |
aefa95ba VS |
2754 | |
2755 | intel_link_compute_m_n(output_bpp, | |
2756 | pipe_config->lane_count, | |
2757 | adjusted_mode->crtc_clock, | |
2758 | pipe_config->port_clock, | |
2759 | &pipe_config->dp_m_n, | |
ed06efb8 | 2760 | constant_n, pipe_config->fec_enable); |
9d1a455b | 2761 | |
4f8036a2 | 2762 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 2763 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 2764 | |
4d90f2d5 | 2765 | intel_psr_compute_config(intel_dp, pipe_config); |
be2dd718 JRS |
2766 | intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp, |
2767 | constant_n); | |
9799c4c3 | 2768 | intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); |
d1eed96d | 2769 | intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); |
4d90f2d5 | 2770 | |
204474a6 | 2771 | return 0; |
a4fc5ed6 KP |
2772 | } |
2773 | ||
901c2daf | 2774 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
a621860a | 2775 | int link_rate, int lane_count) |
901c2daf | 2776 | { |
edb2e530 | 2777 | intel_dp->link_trained = false; |
dfa10480 ACO |
2778 | intel_dp->link_rate = link_rate; |
2779 | intel_dp->lane_count = lane_count; | |
901c2daf VS |
2780 | } |
2781 | ||
85cb48a1 | 2782 | static void intel_dp_prepare(struct intel_encoder *encoder, |
5f88a9c6 | 2783 | const struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 2784 | { |
2f773477 | 2785 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 2786 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
8f4f2797 | 2787 | enum port port = encoder->port; |
2225f3c6 | 2788 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
1326a92c | 2789 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
a4fc5ed6 | 2790 | |
a621860a VS |
2791 | intel_dp_set_link_params(intel_dp, |
2792 | pipe_config->port_clock, | |
2793 | pipe_config->lane_count); | |
901c2daf | 2794 | |
417e822d | 2795 | /* |
1a2eb460 | 2796 | * There are four kinds of DP registers: |
417e822d KP |
2797 | * |
2798 | * IBX PCH | |
1a2eb460 KP |
2799 | * SNB CPU |
2800 | * IVB CPU | |
417e822d KP |
2801 | * CPT PCH |
2802 | * | |
2803 | * IBX PCH and CPU are the same for almost everything, | |
2804 | * except that the CPU DP PLL is configured in this | |
2805 | * register | |
2806 | * | |
2807 | * CPT PCH is quite different, having many bits moved | |
2808 | * to the TRANS_DP_CTL register instead. That | |
9eae5e27 | 2809 | * configuration happens (oddly) in ilk_pch_enable |
417e822d | 2810 | */ |
9c9e7927 | 2811 | |
417e822d KP |
2812 | /* Preserve the BIOS-computed detected bit. This is |
2813 | * supposed to be read-only. | |
2814 | */ | |
b4e33881 | 2815 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; |
a4fc5ed6 | 2816 | |
417e822d | 2817 | /* Handle DP bits in common between all three register formats */ |
417e822d | 2818 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 2819 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 2820 | |
417e822d | 2821 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 2822 | |
b752e995 | 2823 | if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
2824 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
2825 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
2826 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
2827 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
2828 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
2829 | ||
6aba5b6c | 2830 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
2831 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2832 | ||
59b74c49 | 2833 | intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); |
6e266956 | 2834 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
2835 | u32 trans_dp; |
2836 | ||
39e5fa88 | 2837 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 | 2838 | |
b4e33881 | 2839 | trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); |
e3ef4479 VS |
2840 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
2841 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
2842 | else | |
2843 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
b4e33881 | 2844 | intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); |
39e5fa88 | 2845 | } else { |
c99f53f7 | 2846 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 2847 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
2848 | |
2849 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
2850 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
2851 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
2852 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
2853 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
2854 | ||
6aba5b6c | 2855 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
2856 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2857 | ||
920a14b2 | 2858 | if (IS_CHERRYVIEW(dev_priv)) |
59b74c49 VS |
2859 | intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); |
2860 | else | |
2861 | intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); | |
32f9d658 | 2862 | } |
a4fc5ed6 KP |
2863 | } |
2864 | ||
ffd6749d PZ |
2865 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
2866 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 2867 | |
1a5ef5b7 PZ |
2868 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
2869 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 2870 | |
ffd6749d PZ |
2871 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
2872 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 2873 | |
46bd8383 | 2874 | static void intel_pps_verify_state(struct intel_dp *intel_dp); |
de9c1b6b | 2875 | |
4be73780 | 2876 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
2877 | u32 mask, |
2878 | u32 value) | |
bd943159 | 2879 | { |
de25eb7f | 2880 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
f0f59a00 | 2881 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 2882 | |
e39b999a VS |
2883 | lockdep_assert_held(&dev_priv->pps_mutex); |
2884 | ||
46bd8383 | 2885 | intel_pps_verify_state(intel_dp); |
de9c1b6b | 2886 | |
bf13e81b JN |
2887 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2888 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 2889 | |
bdc6114e WK |
2890 | drm_dbg_kms(&dev_priv->drm, |
2891 | "mask %08x value %08x status %08x control %08x\n", | |
2892 | mask, value, | |
b4e33881 JN |
2893 | intel_de_read(dev_priv, pp_stat_reg), |
2894 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
32ce697c | 2895 | |
4cb3b44d DCS |
2896 | if (intel_de_wait_for_register(dev_priv, pp_stat_reg, |
2897 | mask, value, 5000)) | |
bdc6114e WK |
2898 | drm_err(&dev_priv->drm, |
2899 | "Panel status timeout: status %08x control %08x\n", | |
b4e33881 JN |
2900 | intel_de_read(dev_priv, pp_stat_reg), |
2901 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
54c136d4 | 2902 | |
bdc6114e | 2903 | drm_dbg_kms(&dev_priv->drm, "Wait complete\n"); |
99ea7127 | 2904 | } |
32ce697c | 2905 | |
4be73780 | 2906 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 | 2907 | { |
af67009c JN |
2908 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
2909 | ||
2910 | drm_dbg_kms(&i915->drm, "Wait for panel power on\n"); | |
4be73780 | 2911 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
2912 | } |
2913 | ||
4be73780 | 2914 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 | 2915 | { |
af67009c JN |
2916 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
2917 | ||
2918 | drm_dbg_kms(&i915->drm, "Wait for panel power off time\n"); | |
4be73780 | 2919 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
2920 | } |
2921 | ||
4be73780 | 2922 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 2923 | { |
af67009c | 2924 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
d28d4731 AK |
2925 | ktime_t panel_power_on_time; |
2926 | s64 panel_power_off_duration; | |
2927 | ||
af67009c | 2928 | drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n"); |
dce56b3c | 2929 | |
d28d4731 AK |
2930 | /* take the difference of currrent time and panel power off time |
2931 | * and then make panel wait for t11_t12 if needed. */ | |
2932 | panel_power_on_time = ktime_get_boottime(); | |
2933 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
2934 | ||
dce56b3c PZ |
2935 | /* When we disable the VDD override bit last we have to do the manual |
2936 | * wait. */ | |
d28d4731 AK |
2937 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
2938 | wait_remaining_ms_from_jiffies(jiffies, | |
2939 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 2940 | |
4be73780 | 2941 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
2942 | } |
2943 | ||
4be73780 | 2944 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
2945 | { |
2946 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
2947 | intel_dp->backlight_on_delay); | |
2948 | } | |
2949 | ||
4be73780 | 2950 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
2951 | { |
2952 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
2953 | intel_dp->backlight_off_delay); | |
2954 | } | |
99ea7127 | 2955 | |
832dd3c1 KP |
2956 | /* Read the current pp_control value, unlocking the register if it |
2957 | * is locked | |
2958 | */ | |
2959 | ||
9eae5e27 | 2960 | static u32 ilk_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 2961 | { |
de25eb7f | 2962 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
453c5420 | 2963 | u32 control; |
832dd3c1 | 2964 | |
e39b999a VS |
2965 | lockdep_assert_held(&dev_priv->pps_mutex); |
2966 | ||
b4e33881 | 2967 | control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)); |
eb020ca3 PB |
2968 | if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) && |
2969 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
2970 | control &= ~PANEL_UNLOCK_MASK; |
2971 | control |= PANEL_UNLOCK_REGS; | |
2972 | } | |
832dd3c1 | 2973 | return control; |
bd943159 KP |
2974 | } |
2975 | ||
951468f3 VS |
2976 | /* |
2977 | * Must be paired with edp_panel_vdd_off(). | |
2978 | * Must hold pps_mutex around the whole on/off sequence. | |
2979 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2980 | */ | |
1e0560e0 | 2981 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2982 | { |
de25eb7f | 2983 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7801f3b7 | 2984 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5d613501 | 2985 | u32 pp; |
f0f59a00 | 2986 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2987 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2988 | |
e39b999a VS |
2989 | lockdep_assert_held(&dev_priv->pps_mutex); |
2990 | ||
1853a9da | 2991 | if (!intel_dp_is_edp(intel_dp)) |
adddaaf4 | 2992 | return false; |
bd943159 | 2993 | |
2c623c11 | 2994 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2995 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2996 | |
4be73780 | 2997 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2998 | return need_to_disable; |
b0665d57 | 2999 | |
337837ac | 3000 | intel_display_power_get(dev_priv, |
7801f3b7 | 3001 | intel_aux_power_domain(dig_port)); |
e9cb81a2 | 3002 | |
bdc6114e | 3003 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", |
7801f3b7 LDM |
3004 | dig_port->base.base.base.id, |
3005 | dig_port->base.base.name); | |
bd943159 | 3006 | |
4be73780 DV |
3007 | if (!edp_have_panel_power(intel_dp)) |
3008 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 3009 | |
9eae5e27 | 3010 | pp = ilk_get_pp_control(intel_dp); |
5d613501 | 3011 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 3012 | |
bf13e81b JN |
3013 | pp_stat_reg = _pp_stat_reg(intel_dp); |
3014 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 | 3015 | |
b4e33881 JN |
3016 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3017 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
bdc6114e | 3018 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
b4e33881 JN |
3019 | intel_de_read(dev_priv, pp_stat_reg), |
3020 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
ebf33b18 KP |
3021 | /* |
3022 | * If the panel wasn't on, delay before accessing aux channel | |
3023 | */ | |
4be73780 | 3024 | if (!edp_have_panel_power(intel_dp)) { |
bdc6114e WK |
3025 | drm_dbg_kms(&dev_priv->drm, |
3026 | "[ENCODER:%d:%s] panel power wasn't enabled\n", | |
7801f3b7 LDM |
3027 | dig_port->base.base.base.id, |
3028 | dig_port->base.base.name); | |
f01eca2e | 3029 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 3030 | } |
adddaaf4 JN |
3031 | |
3032 | return need_to_disable; | |
3033 | } | |
3034 | ||
951468f3 VS |
3035 | /* |
3036 | * Must be paired with intel_edp_panel_vdd_off() or | |
3037 | * intel_edp_panel_off(). | |
3038 | * Nested calls to these functions are not allowed since | |
3039 | * we drop the lock. Caller must use some higher level | |
3040 | * locking to prevent nested calls from other threads. | |
3041 | */ | |
b80d6c78 | 3042 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 3043 | { |
69d93820 | 3044 | intel_wakeref_t wakeref; |
c695b6b6 | 3045 | bool vdd; |
adddaaf4 | 3046 | |
1853a9da | 3047 | if (!intel_dp_is_edp(intel_dp)) |
c695b6b6 VS |
3048 | return; |
3049 | ||
69d93820 CW |
3050 | vdd = false; |
3051 | with_pps_lock(intel_dp, wakeref) | |
3052 | vdd = edp_panel_vdd_on(intel_dp); | |
66a990dd VS |
3053 | I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n", |
3054 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
3055 | dp_to_dig_port(intel_dp)->base.base.name); | |
5d613501 JB |
3056 | } |
3057 | ||
4be73780 | 3058 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 3059 | { |
de25eb7f | 3060 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7801f3b7 | 3061 | struct intel_digital_port *dig_port = |
be2c9196 | 3062 | dp_to_dig_port(intel_dp); |
5d613501 | 3063 | u32 pp; |
f0f59a00 | 3064 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 3065 | |
e39b999a | 3066 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 3067 | |
eb020ca3 | 3068 | drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd); |
4e6e1a54 | 3069 | |
15e899a0 | 3070 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 3071 | return; |
b0665d57 | 3072 | |
bdc6114e | 3073 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", |
7801f3b7 LDM |
3074 | dig_port->base.base.base.id, |
3075 | dig_port->base.base.name); | |
bd943159 | 3076 | |
9eae5e27 | 3077 | pp = ilk_get_pp_control(intel_dp); |
be2c9196 | 3078 | pp &= ~EDP_FORCE_VDD; |
453c5420 | 3079 | |
be2c9196 VS |
3080 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
3081 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 3082 | |
b4e33881 JN |
3083 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3084 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
90791a5c | 3085 | |
be2c9196 | 3086 | /* Make sure sequencer is idle before allowing subsequent activity */ |
bdc6114e | 3087 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
b4e33881 JN |
3088 | intel_de_read(dev_priv, pp_stat_reg), |
3089 | intel_de_read(dev_priv, pp_ctrl_reg)); | |
e9cb81a2 | 3090 | |
5a162e22 | 3091 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 3092 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 3093 | |
0e6e0be4 | 3094 | intel_display_power_put_unchecked(dev_priv, |
7801f3b7 | 3095 | intel_aux_power_domain(dig_port)); |
bd943159 | 3096 | } |
5d613501 | 3097 | |
4be73780 | 3098 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 | 3099 | { |
69d93820 CW |
3100 | struct intel_dp *intel_dp = |
3101 | container_of(to_delayed_work(__work), | |
3102 | struct intel_dp, panel_vdd_work); | |
3103 | intel_wakeref_t wakeref; | |
bd943159 | 3104 | |
69d93820 CW |
3105 | with_pps_lock(intel_dp, wakeref) { |
3106 | if (!intel_dp->want_panel_vdd) | |
3107 | edp_panel_vdd_off_sync(intel_dp); | |
3108 | } | |
bd943159 KP |
3109 | } |
3110 | ||
aba86890 ID |
3111 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
3112 | { | |
3113 | unsigned long delay; | |
3114 | ||
3115 | /* | |
3116 | * Queue the timer to fire a long time from now (relative to the power | |
3117 | * down delay) to keep the panel power up across a sequence of | |
3118 | * operations. | |
3119 | */ | |
3120 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
3121 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
3122 | } | |
3123 | ||
951468f3 VS |
3124 | /* |
3125 | * Must be paired with edp_panel_vdd_on(). | |
3126 | * Must hold pps_mutex around the whole on/off sequence. | |
3127 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
3128 | */ | |
4be73780 | 3129 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 3130 | { |
de25eb7f | 3131 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e39b999a VS |
3132 | |
3133 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3134 | ||
1853a9da | 3135 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 3136 | return; |
5d613501 | 3137 | |
66a990dd VS |
3138 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on", |
3139 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
3140 | dp_to_dig_port(intel_dp)->base.base.name); | |
f2e8b18a | 3141 | |
bd943159 KP |
3142 | intel_dp->want_panel_vdd = false; |
3143 | ||
aba86890 | 3144 | if (sync) |
4be73780 | 3145 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
3146 | else |
3147 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
3148 | } |
3149 | ||
9f0fb5be | 3150 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 3151 | { |
de25eb7f | 3152 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
99ea7127 | 3153 | u32 pp; |
f0f59a00 | 3154 | i915_reg_t pp_ctrl_reg; |
9934c132 | 3155 | |
9f0fb5be VS |
3156 | lockdep_assert_held(&dev_priv->pps_mutex); |
3157 | ||
1853a9da | 3158 | if (!intel_dp_is_edp(intel_dp)) |
bd943159 | 3159 | return; |
99ea7127 | 3160 | |
bdc6114e WK |
3161 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n", |
3162 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
3163 | dp_to_dig_port(intel_dp)->base.base.name); | |
e39b999a | 3164 | |
eb020ca3 PB |
3165 | if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), |
3166 | "[ENCODER:%d:%s] panel power already on\n", | |
3167 | dp_to_dig_port(intel_dp)->base.base.base.id, | |
3168 | dp_to_dig_port(intel_dp)->base.base.name)) | |
9f0fb5be | 3169 | return; |
9934c132 | 3170 | |
4be73780 | 3171 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 3172 | |
bf13e81b | 3173 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
9eae5e27 | 3174 | pp = ilk_get_pp_control(intel_dp); |
cf819eff | 3175 | if (IS_GEN(dev_priv, 5)) { |
05ce1a49 KP |
3176 | /* ILK workaround: disable reset around power sequence */ |
3177 | pp &= ~PANEL_POWER_RESET; | |
b4e33881 JN |
3178 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3179 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
05ce1a49 | 3180 | } |
37c6c9b0 | 3181 | |
5a162e22 | 3182 | pp |= PANEL_POWER_ON; |
cf819eff | 3183 | if (!IS_GEN(dev_priv, 5)) |
99ea7127 KP |
3184 | pp |= PANEL_POWER_RESET; |
3185 | ||
b4e33881 JN |
3186 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3187 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
9934c132 | 3188 | |
4be73780 | 3189 | wait_panel_on(intel_dp); |
dce56b3c | 3190 | intel_dp->last_power_on = jiffies; |
9934c132 | 3191 | |
cf819eff | 3192 | if (IS_GEN(dev_priv, 5)) { |
05ce1a49 | 3193 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
b4e33881 JN |
3194 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3195 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
05ce1a49 | 3196 | } |
9f0fb5be | 3197 | } |
e39b999a | 3198 | |
9f0fb5be VS |
3199 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
3200 | { | |
69d93820 CW |
3201 | intel_wakeref_t wakeref; |
3202 | ||
1853a9da | 3203 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be VS |
3204 | return; |
3205 | ||
69d93820 CW |
3206 | with_pps_lock(intel_dp, wakeref) |
3207 | edp_panel_on(intel_dp); | |
9934c132 JB |
3208 | } |
3209 | ||
9f0fb5be VS |
3210 | |
3211 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 3212 | { |
de25eb7f | 3213 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
337837ac | 3214 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
99ea7127 | 3215 | u32 pp; |
f0f59a00 | 3216 | i915_reg_t pp_ctrl_reg; |
9934c132 | 3217 | |
9f0fb5be VS |
3218 | lockdep_assert_held(&dev_priv->pps_mutex); |
3219 | ||
1853a9da | 3220 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 3221 | return; |
37c6c9b0 | 3222 | |
bdc6114e WK |
3223 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n", |
3224 | dig_port->base.base.base.id, dig_port->base.base.name); | |
37c6c9b0 | 3225 | |
eb020ca3 PB |
3226 | drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd, |
3227 | "Need [ENCODER:%d:%s] VDD to turn off panel\n", | |
3228 | dig_port->base.base.base.id, dig_port->base.base.name); | |
24f3e092 | 3229 | |
9eae5e27 | 3230 | pp = ilk_get_pp_control(intel_dp); |
35a38556 DV |
3231 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
3232 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 3233 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 3234 | EDP_BLC_ENABLE); |
453c5420 | 3235 | |
bf13e81b | 3236 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 3237 | |
849e39f5 PZ |
3238 | intel_dp->want_panel_vdd = false; |
3239 | ||
b4e33881 JN |
3240 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3241 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
9934c132 | 3242 | |
4be73780 | 3243 | wait_panel_off(intel_dp); |
d7ba25bd | 3244 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
849e39f5 PZ |
3245 | |
3246 | /* We got a reference when we enabled the VDD. */ | |
0e6e0be4 | 3247 | intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port)); |
9f0fb5be | 3248 | } |
e39b999a | 3249 | |
9f0fb5be VS |
3250 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
3251 | { | |
69d93820 CW |
3252 | intel_wakeref_t wakeref; |
3253 | ||
1853a9da | 3254 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be | 3255 | return; |
e39b999a | 3256 | |
69d93820 CW |
3257 | with_pps_lock(intel_dp, wakeref) |
3258 | edp_panel_off(intel_dp); | |
9934c132 JB |
3259 | } |
3260 | ||
1250d107 JN |
3261 | /* Enable backlight in the panel power control. */ |
3262 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 3263 | { |
de25eb7f | 3264 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 3265 | intel_wakeref_t wakeref; |
32f9d658 | 3266 | |
01cb9ea6 JB |
3267 | /* |
3268 | * If we enable the backlight right away following a panel power | |
3269 | * on, we may see slight flicker as the panel syncs with the eDP | |
3270 | * link. So delay a bit to make sure the image is solid before | |
3271 | * allowing it to appear. | |
3272 | */ | |
4be73780 | 3273 | wait_backlight_on(intel_dp); |
e39b999a | 3274 | |
69d93820 CW |
3275 | with_pps_lock(intel_dp, wakeref) { |
3276 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
3277 | u32 pp; | |
453c5420 | 3278 | |
9eae5e27 | 3279 | pp = ilk_get_pp_control(intel_dp); |
69d93820 | 3280 | pp |= EDP_BLC_ENABLE; |
453c5420 | 3281 | |
b4e33881 JN |
3282 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3283 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
69d93820 | 3284 | } |
32f9d658 ZW |
3285 | } |
3286 | ||
1250d107 | 3287 | /* Enable backlight PWM and backlight PP control. */ |
b037d58f ML |
3288 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
3289 | const struct drm_connector_state *conn_state) | |
1250d107 | 3290 | { |
b7d02c3a | 3291 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); |
af67009c | 3292 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b037d58f | 3293 | |
1853a9da | 3294 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
3295 | return; |
3296 | ||
af67009c | 3297 | drm_dbg_kms(&i915->drm, "\n"); |
1250d107 | 3298 | |
b037d58f | 3299 | intel_panel_enable_backlight(crtc_state, conn_state); |
1250d107 JN |
3300 | _intel_edp_backlight_on(intel_dp); |
3301 | } | |
3302 | ||
3303 | /* Disable backlight in the panel power control. */ | |
3304 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 3305 | { |
de25eb7f | 3306 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
69d93820 | 3307 | intel_wakeref_t wakeref; |
32f9d658 | 3308 | |
1853a9da | 3309 | if (!intel_dp_is_edp(intel_dp)) |
f01eca2e KP |
3310 | return; |
3311 | ||
69d93820 CW |
3312 | with_pps_lock(intel_dp, wakeref) { |
3313 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
3314 | u32 pp; | |
e39b999a | 3315 | |
9eae5e27 | 3316 | pp = ilk_get_pp_control(intel_dp); |
69d93820 | 3317 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 3318 | |
b4e33881 JN |
3319 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
3320 | intel_de_posting_read(dev_priv, pp_ctrl_reg); | |
69d93820 | 3321 | } |
e39b999a VS |
3322 | |
3323 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 3324 | edp_wait_backlight_off(intel_dp); |
1250d107 | 3325 | } |
f7d2323c | 3326 | |
1250d107 | 3327 | /* Disable backlight PP control and backlight PWM. */ |
b037d58f | 3328 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
1250d107 | 3329 | { |
b7d02c3a | 3330 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); |
af67009c | 3331 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b037d58f | 3332 | |
1853a9da | 3333 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
3334 | return; |
3335 | ||
af67009c | 3336 | drm_dbg_kms(&i915->drm, "\n"); |
f7d2323c | 3337 | |
1250d107 | 3338 | _intel_edp_backlight_off(intel_dp); |
b037d58f | 3339 | intel_panel_disable_backlight(old_conn_state); |
32f9d658 | 3340 | } |
a4fc5ed6 | 3341 | |
73580fb7 JN |
3342 | /* |
3343 | * Hook for controlling the panel power control backlight through the bl_power | |
3344 | * sysfs attribute. Take care to handle multiple calls. | |
3345 | */ | |
3346 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
3347 | bool enable) | |
3348 | { | |
af67009c | 3349 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
43a6d19c | 3350 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
69d93820 | 3351 | intel_wakeref_t wakeref; |
e39b999a VS |
3352 | bool is_enabled; |
3353 | ||
69d93820 CW |
3354 | is_enabled = false; |
3355 | with_pps_lock(intel_dp, wakeref) | |
9eae5e27 | 3356 | is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
73580fb7 JN |
3357 | if (is_enabled == enable) |
3358 | return; | |
3359 | ||
af67009c JN |
3360 | drm_dbg_kms(&i915->drm, "panel power control backlight %s\n", |
3361 | enable ? "enable" : "disable"); | |
73580fb7 JN |
3362 | |
3363 | if (enable) | |
3364 | _intel_edp_backlight_on(intel_dp); | |
3365 | else | |
3366 | _intel_edp_backlight_off(intel_dp); | |
3367 | } | |
3368 | ||
64e1077a VS |
3369 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
3370 | { | |
3371 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
3372 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
b4e33881 | 3373 | bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; |
64e1077a VS |
3374 | |
3375 | I915_STATE_WARN(cur_state != state, | |
66a990dd VS |
3376 | "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", |
3377 | dig_port->base.base.base.id, dig_port->base.base.name, | |
87ad3212 | 3378 | onoff(state), onoff(cur_state)); |
64e1077a VS |
3379 | } |
3380 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
3381 | ||
3382 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
3383 | { | |
b4e33881 | 3384 | bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; |
64e1077a VS |
3385 | |
3386 | I915_STATE_WARN(cur_state != state, | |
3387 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 3388 | onoff(state), onoff(cur_state)); |
64e1077a VS |
3389 | } |
3390 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
3391 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
3392 | ||
9eae5e27 LDM |
3393 | static void ilk_edp_pll_on(struct intel_dp *intel_dp, |
3394 | const struct intel_crtc_state *pipe_config) | |
d240f20f | 3395 | { |
2225f3c6 | 3396 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
64e1077a | 3397 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 3398 | |
5c34ba27 | 3399 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); |
64e1077a VS |
3400 | assert_dp_port_disabled(intel_dp); |
3401 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 3402 | |
bdc6114e WK |
3403 | drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", |
3404 | pipe_config->port_clock); | |
abfce949 VS |
3405 | |
3406 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
3407 | ||
85cb48a1 | 3408 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
3409 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
3410 | else | |
3411 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
3412 | ||
b4e33881 JN |
3413 | intel_de_write(dev_priv, DP_A, intel_dp->DP); |
3414 | intel_de_posting_read(dev_priv, DP_A); | |
abfce949 VS |
3415 | udelay(500); |
3416 | ||
6b23f3e8 VS |
3417 | /* |
3418 | * [DevILK] Work around required when enabling DP PLL | |
3419 | * while a pipe is enabled going to FDI: | |
3420 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
3421 | * 2. Program DP PLL enable | |
3422 | */ | |
cf819eff | 3423 | if (IS_GEN(dev_priv, 5)) |
0f0f74bc | 3424 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 3425 | |
0767935e | 3426 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 3427 | |
b4e33881 JN |
3428 | intel_de_write(dev_priv, DP_A, intel_dp->DP); |
3429 | intel_de_posting_read(dev_priv, DP_A); | |
298b0b39 | 3430 | udelay(200); |
d240f20f JB |
3431 | } |
3432 | ||
9eae5e27 LDM |
3433 | static void ilk_edp_pll_off(struct intel_dp *intel_dp, |
3434 | const struct intel_crtc_state *old_crtc_state) | |
d240f20f | 3435 | { |
2225f3c6 | 3436 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
64e1077a | 3437 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 3438 | |
5c34ba27 | 3439 | assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); |
64e1077a VS |
3440 | assert_dp_port_disabled(intel_dp); |
3441 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 3442 | |
bdc6114e | 3443 | drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); |
abfce949 | 3444 | |
6fec7662 | 3445 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 3446 | |
b4e33881 JN |
3447 | intel_de_write(dev_priv, DP_A, intel_dp->DP); |
3448 | intel_de_posting_read(dev_priv, DP_A); | |
d240f20f JB |
3449 | udelay(200); |
3450 | } | |
3451 | ||
857c416e VS |
3452 | static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) |
3453 | { | |
3454 | /* | |
3455 | * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus | |
3456 | * be capable of signalling downstream hpd with a long pulse. | |
3457 | * Whether or not that means D3 is safe to use is not clear, | |
3458 | * but let's assume so until proven otherwise. | |
3459 | * | |
3460 | * FIXME should really check all downstream ports... | |
3461 | */ | |
3462 | return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && | |
b4c32073 | 3463 | drm_dp_is_branch(intel_dp->dpcd) && |
857c416e VS |
3464 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; |
3465 | } | |
3466 | ||
2279298d GS |
3467 | void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, |
3468 | const struct intel_crtc_state *crtc_state, | |
3469 | bool enable) | |
3470 | { | |
af67009c | 3471 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
2279298d GS |
3472 | int ret; |
3473 | ||
010663a6 | 3474 | if (!crtc_state->dsc.compression_enable) |
2279298d GS |
3475 | return; |
3476 | ||
3477 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, | |
3478 | enable ? DP_DECOMPRESSION_EN : 0); | |
3479 | if (ret < 0) | |
af67009c JN |
3480 | drm_dbg_kms(&i915->drm, |
3481 | "Failed to %s sink decompression state\n", | |
3482 | enable ? "enable" : "disable"); | |
2279298d GS |
3483 | } |
3484 | ||
c7ad3810 | 3485 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 3486 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 | 3487 | { |
af67009c | 3488 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
c7ad3810 JB |
3489 | int ret, i; |
3490 | ||
3491 | /* Should have a valid DPCD by this point */ | |
3492 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
3493 | return; | |
3494 | ||
3495 | if (mode != DRM_MODE_DPMS_ON) { | |
857c416e VS |
3496 | if (downstream_hpd_needs_d0(intel_dp)) |
3497 | return; | |
3498 | ||
9d1a1031 JN |
3499 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
3500 | DP_SET_POWER_D3); | |
c7ad3810 | 3501 | } else { |
357c0ae9 ID |
3502 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
3503 | ||
c7ad3810 JB |
3504 | /* |
3505 | * When turning on, we need to retry for 1ms to give the sink | |
3506 | * time to wake up. | |
3507 | */ | |
3508 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
3509 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
3510 | DP_SET_POWER_D0); | |
c7ad3810 JB |
3511 | if (ret == 1) |
3512 | break; | |
3513 | msleep(1); | |
3514 | } | |
357c0ae9 ID |
3515 | |
3516 | if (ret == 1 && lspcon->active) | |
3517 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 3518 | } |
f9cac721 JN |
3519 | |
3520 | if (ret != 1) | |
af67009c JN |
3521 | drm_dbg_kms(&i915->drm, "failed to %s sink power state\n", |
3522 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
3523 | } |
3524 | ||
59b74c49 VS |
3525 | static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, |
3526 | enum port port, enum pipe *pipe) | |
3527 | { | |
3528 | enum pipe p; | |
3529 | ||
3530 | for_each_pipe(dev_priv, p) { | |
b4e33881 | 3531 | u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); |
59b74c49 VS |
3532 | |
3533 | if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { | |
3534 | *pipe = p; | |
3535 | return true; | |
3536 | } | |
3537 | } | |
3538 | ||
bdc6114e WK |
3539 | drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", |
3540 | port_name(port)); | |
59b74c49 VS |
3541 | |
3542 | /* must initialize pipe to something for the asserts */ | |
3543 | *pipe = PIPE_A; | |
3544 | ||
3545 | return false; | |
3546 | } | |
3547 | ||
3548 | bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, | |
3549 | i915_reg_t dp_reg, enum port port, | |
3550 | enum pipe *pipe) | |
3551 | { | |
3552 | bool ret; | |
3553 | u32 val; | |
3554 | ||
b4e33881 | 3555 | val = intel_de_read(dev_priv, dp_reg); |
59b74c49 VS |
3556 | |
3557 | ret = val & DP_PORT_EN; | |
3558 | ||
3559 | /* asserts want to know the pipe even if the port is disabled */ | |
3560 | if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) | |
3561 | *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; | |
3562 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) | |
3563 | ret &= cpt_dp_port_selected(dev_priv, port, pipe); | |
3564 | else if (IS_CHERRYVIEW(dev_priv)) | |
3565 | *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; | |
3566 | else | |
3567 | *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; | |
3568 | ||
3569 | return ret; | |
3570 | } | |
3571 | ||
19d8fe15 DV |
3572 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
3573 | enum pipe *pipe) | |
d240f20f | 3574 | { |
2f773477 | 3575 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3576 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
0e6e0be4 | 3577 | intel_wakeref_t wakeref; |
6fa9a5ec | 3578 | bool ret; |
6d129bea | 3579 | |
0e6e0be4 CW |
3580 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
3581 | encoder->power_domain); | |
3582 | if (!wakeref) | |
6d129bea ID |
3583 | return false; |
3584 | ||
59b74c49 VS |
3585 | ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, |
3586 | encoder->port, pipe); | |
6fa9a5ec | 3587 | |
0e6e0be4 | 3588 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
6fa9a5ec ID |
3589 | |
3590 | return ret; | |
19d8fe15 | 3591 | } |
d240f20f | 3592 | |
045ac3b5 | 3593 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 3594 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 3595 | { |
2f773477 | 3596 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3597 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
045ac3b5 | 3598 | u32 tmp, flags = 0; |
8f4f2797 | 3599 | enum port port = encoder->port; |
2225f3c6 | 3600 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
045ac3b5 | 3601 | |
e1214b95 VS |
3602 | if (encoder->type == INTEL_OUTPUT_EDP) |
3603 | pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); | |
3604 | else | |
3605 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); | |
045ac3b5 | 3606 | |
b4e33881 | 3607 | tmp = intel_de_read(dev_priv, intel_dp->output_reg); |
9fcb1704 JN |
3608 | |
3609 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 3610 | |
6e266956 | 3611 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b4e33881 JN |
3612 | u32 trans_dp = intel_de_read(dev_priv, |
3613 | TRANS_DP_CTL(crtc->pipe)); | |
b81e34c2 VS |
3614 | |
3615 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
3616 | flags |= DRM_MODE_FLAG_PHSYNC; |
3617 | else | |
3618 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 3619 | |
b81e34c2 | 3620 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
3621 | flags |= DRM_MODE_FLAG_PVSYNC; |
3622 | else | |
3623 | flags |= DRM_MODE_FLAG_NVSYNC; | |
3624 | } else { | |
39e5fa88 | 3625 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
3626 | flags |= DRM_MODE_FLAG_PHSYNC; |
3627 | else | |
3628 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 3629 | |
39e5fa88 | 3630 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
3631 | flags |= DRM_MODE_FLAG_PVSYNC; |
3632 | else | |
3633 | flags |= DRM_MODE_FLAG_NVSYNC; | |
3634 | } | |
045ac3b5 | 3635 | |
1326a92c | 3636 | pipe_config->hw.adjusted_mode.flags |= flags; |
f1f644dc | 3637 | |
c99f53f7 | 3638 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
3639 | pipe_config->limited_color_range = true; |
3640 | ||
90a6b7b0 VS |
3641 | pipe_config->lane_count = |
3642 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
3643 | ||
eb14cb74 VS |
3644 | intel_dp_get_m_n(crtc, pipe_config); |
3645 | ||
18442d08 | 3646 | if (port == PORT_A) { |
b4e33881 | 3647 | if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
3648 | pipe_config->port_clock = 162000; |
3649 | else | |
3650 | pipe_config->port_clock = 270000; | |
3651 | } | |
18442d08 | 3652 | |
1326a92c | 3653 | pipe_config->hw.adjusted_mode.crtc_clock = |
e3b247da VS |
3654 | intel_dotclock_calculate(pipe_config->port_clock, |
3655 | &pipe_config->dp_m_n); | |
7f16e5c1 | 3656 | |
1853a9da | 3657 | if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
6aa23e65 | 3658 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
c6cd2ee2 JN |
3659 | /* |
3660 | * This is a big fat ugly hack. | |
3661 | * | |
3662 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
3663 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
3664 | * unknown we fail to light up. Yet the same BIOS boots up with | |
3665 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
3666 | * max, not what it tells us to use. | |
3667 | * | |
3668 | * Note: This will still be broken if the eDP panel is not lit | |
3669 | * up by the BIOS, and thus we can't get the mode at module | |
3670 | * load. | |
3671 | */ | |
bdc6114e WK |
3672 | drm_dbg_kms(&dev_priv->drm, |
3673 | "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
3674 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); | |
6aa23e65 | 3675 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
c6cd2ee2 | 3676 | } |
045ac3b5 JB |
3677 | } |
3678 | ||
f9e76a6e ID |
3679 | static bool |
3680 | intel_dp_get_dpcd(struct intel_dp *intel_dp); | |
3681 | ||
3682 | /** | |
3683 | * intel_dp_sync_state - sync the encoder state during init/resume | |
3684 | * @encoder: intel encoder to sync | |
3685 | * @crtc_state: state for the CRTC connected to the encoder | |
3686 | * | |
3687 | * Sync any state stored in the encoder wrt. HW state during driver init | |
3688 | * and system resume. | |
3689 | */ | |
3690 | void intel_dp_sync_state(struct intel_encoder *encoder, | |
3691 | const struct intel_crtc_state *crtc_state) | |
3692 | { | |
3693 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
3694 | ||
3695 | /* | |
3696 | * Don't clobber DPCD if it's been already read out during output | |
3697 | * setup (eDP) or detect. | |
3698 | */ | |
3699 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) | |
3700 | intel_dp_get_dpcd(intel_dp); | |
3701 | ||
3702 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
3703 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
3704 | } | |
3705 | ||
b671d6ef ID |
3706 | bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, |
3707 | struct intel_crtc_state *crtc_state) | |
3708 | { | |
3709 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
7d6287a8 ID |
3710 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
3711 | ||
3712 | /* | |
3713 | * If BIOS has set an unsupported or non-standard link rate for some | |
3714 | * reason force an encoder recompute and full modeset. | |
3715 | */ | |
3716 | if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, | |
3717 | crtc_state->port_clock) < 0) { | |
3718 | drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n"); | |
3719 | crtc_state->uapi.connectors_changed = true; | |
3720 | return false; | |
3721 | } | |
b671d6ef ID |
3722 | |
3723 | /* | |
3724 | * FIXME hack to force full modeset when DSC is being used. | |
3725 | * | |
3726 | * As long as we do not have full state readout and config comparison | |
3727 | * of crtc_state->dsc, we have no way to ensure reliable fastset. | |
3728 | * Remove once we have readout for DSC. | |
3729 | */ | |
3730 | if (crtc_state->dsc.compression_enable) { | |
3731 | drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n"); | |
3732 | crtc_state->uapi.mode_changed = true; | |
3733 | return false; | |
3734 | } | |
3735 | ||
3736 | return true; | |
3737 | } | |
3738 | ||
ede9771d VS |
3739 | static void intel_disable_dp(struct intel_atomic_state *state, |
3740 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3741 | const struct intel_crtc_state *old_crtc_state, |
3742 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 3743 | { |
b7d02c3a | 3744 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
495a5bb8 | 3745 | |
edb2e530 VS |
3746 | intel_dp->link_trained = false; |
3747 | ||
85cb48a1 | 3748 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
3749 | intel_audio_codec_disable(encoder, |
3750 | old_crtc_state, old_conn_state); | |
6cb49835 DV |
3751 | |
3752 | /* Make sure the panel is off before trying to change the mode. But also | |
3753 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 3754 | intel_edp_panel_vdd_on(intel_dp); |
b037d58f | 3755 | intel_edp_backlight_off(old_conn_state); |
fdbc3b1f | 3756 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 3757 | intel_edp_panel_off(intel_dp); |
1a8ff607 VS |
3758 | } |
3759 | ||
ede9771d VS |
3760 | static void g4x_disable_dp(struct intel_atomic_state *state, |
3761 | struct intel_encoder *encoder, | |
1a8ff607 VS |
3762 | const struct intel_crtc_state *old_crtc_state, |
3763 | const struct drm_connector_state *old_conn_state) | |
1a8ff607 | 3764 | { |
ede9771d | 3765 | intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); |
1a8ff607 VS |
3766 | } |
3767 | ||
ede9771d VS |
3768 | static void vlv_disable_dp(struct intel_atomic_state *state, |
3769 | struct intel_encoder *encoder, | |
1a8ff607 VS |
3770 | const struct intel_crtc_state *old_crtc_state, |
3771 | const struct drm_connector_state *old_conn_state) | |
3772 | { | |
ede9771d | 3773 | intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); |
d240f20f JB |
3774 | } |
3775 | ||
ede9771d VS |
3776 | static void g4x_post_disable_dp(struct intel_atomic_state *state, |
3777 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3778 | const struct intel_crtc_state *old_crtc_state, |
3779 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 3780 | { |
b7d02c3a | 3781 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
adc10304 | 3782 | enum port port = encoder->port; |
2bd2ad64 | 3783 | |
51a9f6df VS |
3784 | /* |
3785 | * Bspec does not list a specific disable sequence for g4x DP. | |
3786 | * Follow the ilk+ sequence (disable pipe before the port) for | |
3787 | * g4x DP as it does not suffer from underruns like the normal | |
3788 | * g4x modeset sequence (disable pipe after the port). | |
3789 | */ | |
adc10304 | 3790 | intel_dp_link_down(encoder, old_crtc_state); |
abfce949 VS |
3791 | |
3792 | /* Only ilk+ has port A */ | |
08aff3fe | 3793 | if (port == PORT_A) |
9eae5e27 | 3794 | ilk_edp_pll_off(intel_dp, old_crtc_state); |
49277c31 VS |
3795 | } |
3796 | ||
ede9771d VS |
3797 | static void vlv_post_disable_dp(struct intel_atomic_state *state, |
3798 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3799 | const struct intel_crtc_state *old_crtc_state, |
3800 | const struct drm_connector_state *old_conn_state) | |
49277c31 | 3801 | { |
adc10304 | 3802 | intel_dp_link_down(encoder, old_crtc_state); |
2bd2ad64 DV |
3803 | } |
3804 | ||
ede9771d VS |
3805 | static void chv_post_disable_dp(struct intel_atomic_state *state, |
3806 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3807 | const struct intel_crtc_state *old_crtc_state, |
3808 | const struct drm_connector_state *old_conn_state) | |
a8f327fb | 3809 | { |
adc10304 | 3810 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
97fd4d5c | 3811 | |
adc10304 | 3812 | intel_dp_link_down(encoder, old_crtc_state); |
a8f327fb | 3813 | |
221c7862 | 3814 | vlv_dpio_get(dev_priv); |
a8f327fb VS |
3815 | |
3816 | /* Assert data lane reset */ | |
2e1029c6 | 3817 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 3818 | |
221c7862 | 3819 | vlv_dpio_put(dev_priv); |
580d3811 VS |
3820 | } |
3821 | ||
7b13b58a | 3822 | static void |
eee3f911 | 3823 | cpt_set_link_train(struct intel_dp *intel_dp, |
a621860a | 3824 | const struct intel_crtc_state *crtc_state, |
eee3f911 | 3825 | u8 dp_train_pat) |
7b13b58a | 3826 | { |
de25eb7f | 3827 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
eee3f911 | 3828 | u32 *DP = &intel_dp->DP; |
8b0878a0 | 3829 | |
eee3f911 | 3830 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
7b13b58a | 3831 | |
6777a855 | 3832 | switch (intel_dp_training_pattern_symbol(dp_train_pat)) { |
eee3f911 VS |
3833 | case DP_TRAINING_PATTERN_DISABLE: |
3834 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
3835 | break; | |
3836 | case DP_TRAINING_PATTERN_1: | |
3837 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
3838 | break; | |
3839 | case DP_TRAINING_PATTERN_2: | |
3840 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
3841 | break; | |
3842 | case DP_TRAINING_PATTERN_3: | |
3843 | drm_dbg_kms(&dev_priv->drm, | |
3844 | "TPS3 not supported, using TPS2 instead\n"); | |
3845 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
3846 | break; | |
3847 | } | |
7b13b58a | 3848 | |
eee3f911 VS |
3849 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
3850 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
3851 | } | |
7b13b58a | 3852 | |
eee3f911 VS |
3853 | static void |
3854 | g4x_set_link_train(struct intel_dp *intel_dp, | |
a621860a | 3855 | const struct intel_crtc_state *crtc_state, |
eee3f911 VS |
3856 | u8 dp_train_pat) |
3857 | { | |
3858 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
3859 | u32 *DP = &intel_dp->DP; | |
7b13b58a | 3860 | |
eee3f911 | 3861 | *DP &= ~DP_LINK_TRAIN_MASK; |
7b13b58a | 3862 | |
6777a855 | 3863 | switch (intel_dp_training_pattern_symbol(dp_train_pat)) { |
eee3f911 VS |
3864 | case DP_TRAINING_PATTERN_DISABLE: |
3865 | *DP |= DP_LINK_TRAIN_OFF; | |
3866 | break; | |
3867 | case DP_TRAINING_PATTERN_1: | |
3868 | *DP |= DP_LINK_TRAIN_PAT_1; | |
3869 | break; | |
3870 | case DP_TRAINING_PATTERN_2: | |
3871 | *DP |= DP_LINK_TRAIN_PAT_2; | |
3872 | break; | |
3873 | case DP_TRAINING_PATTERN_3: | |
3874 | drm_dbg_kms(&dev_priv->drm, | |
3875 | "TPS3 not supported, using TPS2 instead\n"); | |
3876 | *DP |= DP_LINK_TRAIN_PAT_2; | |
3877 | break; | |
7b13b58a | 3878 | } |
eee3f911 VS |
3879 | |
3880 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); | |
3881 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
7b13b58a VS |
3882 | } |
3883 | ||
85cb48a1 | 3884 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
95cef532 | 3885 | const struct intel_crtc_state *crtc_state) |
7b13b58a | 3886 | { |
de25eb7f | 3887 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7b13b58a | 3888 | |
7b13b58a | 3889 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 3890 | |
a621860a VS |
3891 | intel_dp_program_link_training_pattern(intel_dp, crtc_state, |
3892 | DP_TRAINING_PATTERN_1); | |
7b713f50 VS |
3893 | |
3894 | /* | |
3895 | * Magic for VLV/CHV. We _must_ first set up the register | |
3896 | * without actually enabling the port, and then do another | |
3897 | * write to enable the port. Otherwise link training will | |
3898 | * fail when the power sequencer is freshly used for this port. | |
3899 | */ | |
3900 | intel_dp->DP |= DP_PORT_EN; | |
95cef532 | 3901 | if (crtc_state->has_audio) |
6fec7662 | 3902 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 | 3903 | |
b4e33881 JN |
3904 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
3905 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
580d3811 VS |
3906 | } |
3907 | ||
b7feffd5 VS |
3908 | void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp) |
3909 | { | |
3910 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
3911 | u8 tmp; | |
3912 | ||
3913 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) | |
3914 | return; | |
3915 | ||
3916 | if (!drm_dp_is_branch(intel_dp->dpcd)) | |
3917 | return; | |
3918 | ||
3919 | tmp = intel_dp->has_hdmi_sink ? | |
3920 | DP_HDMI_DVI_OUTPUT_CONFIG : 0; | |
3921 | ||
3922 | if (drm_dp_dpcd_writeb(&intel_dp->aux, | |
181567aa | 3923 | DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) |
b7feffd5 VS |
3924 | drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n", |
3925 | enableddisabled(intel_dp->has_hdmi_sink)); | |
3926 | ||
181567aa VS |
3927 | tmp = intel_dp->dfp.ycbcr_444_to_420 ? |
3928 | DP_CONVERSION_TO_YCBCR420_ENABLE : 0; | |
3929 | ||
3930 | if (drm_dp_dpcd_writeb(&intel_dp->aux, | |
3931 | DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) | |
3932 | drm_dbg_kms(&i915->drm, | |
3933 | "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n", | |
3934 | enableddisabled(intel_dp->dfp.ycbcr_444_to_420)); | |
3935 | ||
3936 | tmp = 0; | |
3937 | ||
3938 | if (drm_dp_dpcd_writeb(&intel_dp->aux, | |
3939 | DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0) | |
3940 | drm_dbg_kms(&i915->drm, | |
3941 | "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n", | |
3942 | enableddisabled(false)); | |
b7feffd5 VS |
3943 | } |
3944 | ||
ede9771d VS |
3945 | static void intel_enable_dp(struct intel_atomic_state *state, |
3946 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3947 | const struct intel_crtc_state *pipe_config, |
3948 | const struct drm_connector_state *conn_state) | |
d240f20f | 3949 | { |
2f773477 | 3950 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 3951 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 3952 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
b4e33881 | 3953 | u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); |
d6fbdd15 | 3954 | enum pipe pipe = crtc->pipe; |
69d93820 | 3955 | intel_wakeref_t wakeref; |
5d613501 | 3956 | |
eb020ca3 | 3957 | if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) |
0c33d8d7 | 3958 | return; |
5d613501 | 3959 | |
69d93820 CW |
3960 | with_pps_lock(intel_dp, wakeref) { |
3961 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
3962 | vlv_init_panel_power_sequencer(encoder, pipe_config); | |
093e3f13 | 3963 | |
69d93820 | 3964 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 | 3965 | |
69d93820 CW |
3966 | edp_panel_vdd_on(intel_dp); |
3967 | edp_panel_on(intel_dp); | |
3968 | edp_panel_vdd_off(intel_dp, true); | |
3969 | } | |
093e3f13 | 3970 | |
920a14b2 | 3971 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
3972 | unsigned int lane_mask = 0x0; |
3973 | ||
920a14b2 | 3974 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 3975 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 3976 | |
9b6de0a1 VS |
3977 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
3978 | lane_mask); | |
e0fce78f | 3979 | } |
61234fa5 | 3980 | |
f01eca2e | 3981 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
b7feffd5 | 3982 | intel_dp_configure_protocol_converter(intel_dp); |
a621860a VS |
3983 | intel_dp_start_link_train(intel_dp, pipe_config); |
3984 | intel_dp_stop_link_train(intel_dp, pipe_config); | |
c1dec79a | 3985 | |
85cb48a1 | 3986 | if (pipe_config->has_audio) { |
bdc6114e WK |
3987 | drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n", |
3988 | pipe_name(pipe)); | |
bbf35e9d | 3989 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 3990 | } |
ab1f90f9 | 3991 | } |
89b667f8 | 3992 | |
ede9771d VS |
3993 | static void g4x_enable_dp(struct intel_atomic_state *state, |
3994 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
3995 | const struct intel_crtc_state *pipe_config, |
3996 | const struct drm_connector_state *conn_state) | |
ecff4f3b | 3997 | { |
ede9771d | 3998 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
b037d58f | 3999 | intel_edp_backlight_on(pipe_config, conn_state); |
ab1f90f9 | 4000 | } |
89b667f8 | 4001 | |
ede9771d VS |
4002 | static void vlv_enable_dp(struct intel_atomic_state *state, |
4003 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
4004 | const struct intel_crtc_state *pipe_config, |
4005 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 4006 | { |
b037d58f | 4007 | intel_edp_backlight_on(pipe_config, conn_state); |
d240f20f JB |
4008 | } |
4009 | ||
ede9771d VS |
4010 | static void g4x_pre_enable_dp(struct intel_atomic_state *state, |
4011 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
4012 | const struct intel_crtc_state *pipe_config, |
4013 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 4014 | { |
b7d02c3a | 4015 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
8f4f2797 | 4016 | enum port port = encoder->port; |
ab1f90f9 | 4017 | |
85cb48a1 | 4018 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 4019 | |
d41f1efb | 4020 | /* Only ilk+ has port A */ |
abfce949 | 4021 | if (port == PORT_A) |
9eae5e27 | 4022 | ilk_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
4023 | } |
4024 | ||
83b84597 VS |
4025 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
4026 | { | |
7801f3b7 LDM |
4027 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4028 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
83b84597 | 4029 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 4030 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 4031 | |
eb020ca3 | 4032 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); |
9f2bdb00 | 4033 | |
eb020ca3 | 4034 | if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) |
d158694f VS |
4035 | return; |
4036 | ||
83b84597 VS |
4037 | edp_panel_vdd_off_sync(intel_dp); |
4038 | ||
4039 | /* | |
e7f2af78 | 4040 | * VLV seems to get confused when multiple power sequencers |
83b84597 VS |
4041 | * have the same port selected (even if only one has power/vdd |
4042 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
4043 | * CHV on the other hand doesn't seem to mind having the same port | |
e7f2af78 | 4044 | * selected in multiple power sequencers, but let's clear the |
83b84597 VS |
4045 | * port select always when logically disconnecting a power sequencer |
4046 | * from a port. | |
4047 | */ | |
bdc6114e WK |
4048 | drm_dbg_kms(&dev_priv->drm, |
4049 | "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", | |
7801f3b7 LDM |
4050 | pipe_name(pipe), dig_port->base.base.base.id, |
4051 | dig_port->base.base.name); | |
b4e33881 JN |
4052 | intel_de_write(dev_priv, pp_on_reg, 0); |
4053 | intel_de_posting_read(dev_priv, pp_on_reg); | |
83b84597 VS |
4054 | |
4055 | intel_dp->pps_pipe = INVALID_PIPE; | |
4056 | } | |
4057 | ||
46bd8383 | 4058 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a4a5d2f8 VS |
4059 | enum pipe pipe) |
4060 | { | |
a4a5d2f8 VS |
4061 | struct intel_encoder *encoder; |
4062 | ||
4063 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4064 | ||
14aa521c | 4065 | for_each_intel_dp(&dev_priv->drm, encoder) { |
b7d02c3a | 4066 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4a5d2f8 | 4067 | |
eb020ca3 PB |
4068 | drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe, |
4069 | "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", | |
4070 | pipe_name(pipe), encoder->base.base.id, | |
4071 | encoder->base.name); | |
9f2bdb00 | 4072 | |
a4a5d2f8 VS |
4073 | if (intel_dp->pps_pipe != pipe) |
4074 | continue; | |
4075 | ||
bdc6114e WK |
4076 | drm_dbg_kms(&dev_priv->drm, |
4077 | "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", | |
4078 | pipe_name(pipe), encoder->base.base.id, | |
4079 | encoder->base.name); | |
a4a5d2f8 VS |
4080 | |
4081 | /* make sure vdd is off before we steal it */ | |
83b84597 | 4082 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
4083 | } |
4084 | } | |
4085 | ||
adc10304 VS |
4086 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
4087 | const struct intel_crtc_state *crtc_state) | |
a4a5d2f8 | 4088 | { |
46bd8383 | 4089 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 4090 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 4091 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
a4a5d2f8 VS |
4092 | |
4093 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4094 | ||
eb020ca3 | 4095 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 4096 | |
9f2bdb00 VS |
4097 | if (intel_dp->pps_pipe != INVALID_PIPE && |
4098 | intel_dp->pps_pipe != crtc->pipe) { | |
4099 | /* | |
4100 | * If another power sequencer was being used on this | |
4101 | * port previously make sure to turn off vdd there while | |
4102 | * we still have control of it. | |
4103 | */ | |
83b84597 | 4104 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 4105 | } |
a4a5d2f8 VS |
4106 | |
4107 | /* | |
4108 | * We may be stealing the power | |
4109 | * sequencer from another port. | |
4110 | */ | |
46bd8383 | 4111 | vlv_steal_power_sequencer(dev_priv, crtc->pipe); |
a4a5d2f8 | 4112 | |
9f2bdb00 VS |
4113 | intel_dp->active_pipe = crtc->pipe; |
4114 | ||
1853a9da | 4115 | if (!intel_dp_is_edp(intel_dp)) |
9f2bdb00 VS |
4116 | return; |
4117 | ||
a4a5d2f8 VS |
4118 | /* now it's all ours */ |
4119 | intel_dp->pps_pipe = crtc->pipe; | |
4120 | ||
bdc6114e WK |
4121 | drm_dbg_kms(&dev_priv->drm, |
4122 | "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", | |
4123 | pipe_name(intel_dp->pps_pipe), encoder->base.base.id, | |
4124 | encoder->base.name); | |
a4a5d2f8 VS |
4125 | |
4126 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
4127 | intel_dp_init_panel_power_sequencer(intel_dp); |
4128 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 VS |
4129 | } |
4130 | ||
ede9771d VS |
4131 | static void vlv_pre_enable_dp(struct intel_atomic_state *state, |
4132 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
4133 | const struct intel_crtc_state *pipe_config, |
4134 | const struct drm_connector_state *conn_state) | |
a4fc5ed6 | 4135 | { |
2e1029c6 | 4136 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
ab1f90f9 | 4137 | |
ede9771d | 4138 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
89b667f8 JB |
4139 | } |
4140 | ||
ede9771d VS |
4141 | static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, |
4142 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
4143 | const struct intel_crtc_state *pipe_config, |
4144 | const struct drm_connector_state *conn_state) | |
89b667f8 | 4145 | { |
85cb48a1 | 4146 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 4147 | |
2e1029c6 | 4148 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
a4fc5ed6 KP |
4149 | } |
4150 | ||
ede9771d VS |
4151 | static void chv_pre_enable_dp(struct intel_atomic_state *state, |
4152 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
4153 | const struct intel_crtc_state *pipe_config, |
4154 | const struct drm_connector_state *conn_state) | |
e4a1d846 | 4155 | { |
2e1029c6 | 4156 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
e4a1d846 | 4157 | |
ede9771d | 4158 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
b0b33846 VS |
4159 | |
4160 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 4161 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
4162 | } |
4163 | ||
ede9771d VS |
4164 | static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, |
4165 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
4166 | const struct intel_crtc_state *pipe_config, |
4167 | const struct drm_connector_state *conn_state) | |
9197c88b | 4168 | { |
85cb48a1 | 4169 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 4170 | |
2e1029c6 | 4171 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
4172 | } |
4173 | ||
ede9771d VS |
4174 | static void chv_dp_post_pll_disable(struct intel_atomic_state *state, |
4175 | struct intel_encoder *encoder, | |
2e1029c6 VS |
4176 | const struct intel_crtc_state *old_crtc_state, |
4177 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 4178 | { |
2e1029c6 | 4179 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
4180 | } |
4181 | ||
a4fc5ed6 KP |
4182 | /* |
4183 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
4184 | * link status information | |
4185 | */ | |
94223d04 | 4186 | bool |
830de422 | 4187 | intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 4188 | { |
9f085ebb L |
4189 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
4190 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
4191 | } |
4192 | ||
a621860a VS |
4193 | static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, |
4194 | const struct intel_crtc_state *crtc_state) | |
a4fc5ed6 | 4195 | { |
53de0a20 VS |
4196 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
4197 | } | |
1a2eb460 | 4198 | |
a621860a VS |
4199 | static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, |
4200 | const struct intel_crtc_state *crtc_state) | |
53de0a20 VS |
4201 | { |
4202 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; | |
1a2eb460 KP |
4203 | } |
4204 | ||
6694d2be | 4205 | static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) |
1a2eb460 | 4206 | { |
53de0a20 VS |
4207 | return DP_TRAIN_PRE_EMPH_LEVEL_2; |
4208 | } | |
1a2eb460 | 4209 | |
6694d2be | 4210 | static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) |
53de0a20 VS |
4211 | { |
4212 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
a4fc5ed6 KP |
4213 | } |
4214 | ||
a621860a VS |
4215 | static void vlv_set_signal_levels(struct intel_dp *intel_dp, |
4216 | const struct intel_crtc_state *crtc_state) | |
e2fa6fba | 4217 | { |
53d98725 | 4218 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
4219 | unsigned long demph_reg_value, preemph_reg_value, |
4220 | uniqtranscale_reg_value; | |
830de422 | 4221 | u8 train_set = intel_dp->train_set[0]; |
e2fa6fba P |
4222 | |
4223 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 4224 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
4225 | preemph_reg_value = 0x0004000; |
4226 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4227 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4228 | demph_reg_value = 0x2B405555; |
4229 | uniqtranscale_reg_value = 0x552AB83A; | |
4230 | break; | |
bd60018a | 4231 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
4232 | demph_reg_value = 0x2B404040; |
4233 | uniqtranscale_reg_value = 0x5548B83A; | |
4234 | break; | |
bd60018a | 4235 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
4236 | demph_reg_value = 0x2B245555; |
4237 | uniqtranscale_reg_value = 0x5560B83A; | |
4238 | break; | |
bd60018a | 4239 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
4240 | demph_reg_value = 0x2B405555; |
4241 | uniqtranscale_reg_value = 0x5598DA3A; | |
4242 | break; | |
4243 | default: | |
fb83f72c | 4244 | return; |
e2fa6fba P |
4245 | } |
4246 | break; | |
bd60018a | 4247 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
4248 | preemph_reg_value = 0x0002000; |
4249 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4250 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4251 | demph_reg_value = 0x2B404040; |
4252 | uniqtranscale_reg_value = 0x5552B83A; | |
4253 | break; | |
bd60018a | 4254 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
4255 | demph_reg_value = 0x2B404848; |
4256 | uniqtranscale_reg_value = 0x5580B83A; | |
4257 | break; | |
bd60018a | 4258 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
4259 | demph_reg_value = 0x2B404040; |
4260 | uniqtranscale_reg_value = 0x55ADDA3A; | |
4261 | break; | |
4262 | default: | |
fb83f72c | 4263 | return; |
e2fa6fba P |
4264 | } |
4265 | break; | |
bd60018a | 4266 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
4267 | preemph_reg_value = 0x0000000; |
4268 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4269 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4270 | demph_reg_value = 0x2B305555; |
4271 | uniqtranscale_reg_value = 0x5570B83A; | |
4272 | break; | |
bd60018a | 4273 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
4274 | demph_reg_value = 0x2B2B4040; |
4275 | uniqtranscale_reg_value = 0x55ADDA3A; | |
4276 | break; | |
4277 | default: | |
fb83f72c | 4278 | return; |
e2fa6fba P |
4279 | } |
4280 | break; | |
bd60018a | 4281 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
4282 | preemph_reg_value = 0x0006000; |
4283 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 4284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
4285 | demph_reg_value = 0x1B405555; |
4286 | uniqtranscale_reg_value = 0x55ADDA3A; | |
4287 | break; | |
4288 | default: | |
fb83f72c | 4289 | return; |
e2fa6fba P |
4290 | } |
4291 | break; | |
4292 | default: | |
fb83f72c | 4293 | return; |
e2fa6fba P |
4294 | } |
4295 | ||
a621860a VS |
4296 | vlv_set_phy_signal_level(encoder, crtc_state, |
4297 | demph_reg_value, preemph_reg_value, | |
53d98725 | 4298 | uniqtranscale_reg_value, 0); |
e2fa6fba P |
4299 | } |
4300 | ||
a621860a VS |
4301 | static void chv_set_signal_levels(struct intel_dp *intel_dp, |
4302 | const struct intel_crtc_state *crtc_state) | |
e4a1d846 | 4303 | { |
b7fa22d8 ACO |
4304 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
4305 | u32 deemph_reg_value, margin_reg_value; | |
4306 | bool uniq_trans_scale = false; | |
830de422 | 4307 | u8 train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
4308 | |
4309 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 4310 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 4311 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4312 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4313 | deemph_reg_value = 128; |
4314 | margin_reg_value = 52; | |
4315 | break; | |
bd60018a | 4316 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
4317 | deemph_reg_value = 128; |
4318 | margin_reg_value = 77; | |
4319 | break; | |
bd60018a | 4320 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
4321 | deemph_reg_value = 128; |
4322 | margin_reg_value = 102; | |
4323 | break; | |
bd60018a | 4324 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
4325 | deemph_reg_value = 128; |
4326 | margin_reg_value = 154; | |
b7fa22d8 | 4327 | uniq_trans_scale = true; |
e4a1d846 CML |
4328 | break; |
4329 | default: | |
fb83f72c | 4330 | return; |
e4a1d846 CML |
4331 | } |
4332 | break; | |
bd60018a | 4333 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 4334 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4335 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4336 | deemph_reg_value = 85; |
4337 | margin_reg_value = 78; | |
4338 | break; | |
bd60018a | 4339 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
4340 | deemph_reg_value = 85; |
4341 | margin_reg_value = 116; | |
4342 | break; | |
bd60018a | 4343 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
4344 | deemph_reg_value = 85; |
4345 | margin_reg_value = 154; | |
4346 | break; | |
4347 | default: | |
fb83f72c | 4348 | return; |
e4a1d846 CML |
4349 | } |
4350 | break; | |
bd60018a | 4351 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 4352 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4353 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4354 | deemph_reg_value = 64; |
4355 | margin_reg_value = 104; | |
4356 | break; | |
bd60018a | 4357 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
4358 | deemph_reg_value = 64; |
4359 | margin_reg_value = 154; | |
4360 | break; | |
4361 | default: | |
fb83f72c | 4362 | return; |
e4a1d846 CML |
4363 | } |
4364 | break; | |
bd60018a | 4365 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 4366 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4367 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
4368 | deemph_reg_value = 43; |
4369 | margin_reg_value = 154; | |
4370 | break; | |
4371 | default: | |
fb83f72c | 4372 | return; |
e4a1d846 CML |
4373 | } |
4374 | break; | |
4375 | default: | |
fb83f72c | 4376 | return; |
e4a1d846 CML |
4377 | } |
4378 | ||
a621860a VS |
4379 | chv_set_phy_signal_level(encoder, crtc_state, |
4380 | deemph_reg_value, margin_reg_value, | |
4381 | uniq_trans_scale); | |
e4a1d846 CML |
4382 | } |
4383 | ||
fb83f72c | 4384 | static u32 g4x_signal_levels(u8 train_set) |
a4fc5ed6 | 4385 | { |
830de422 | 4386 | u32 signal_levels = 0; |
a4fc5ed6 | 4387 | |
3cf2efb1 | 4388 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 4389 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
4390 | default: |
4391 | signal_levels |= DP_VOLTAGE_0_4; | |
4392 | break; | |
bd60018a | 4393 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
4394 | signal_levels |= DP_VOLTAGE_0_6; |
4395 | break; | |
bd60018a | 4396 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
4397 | signal_levels |= DP_VOLTAGE_0_8; |
4398 | break; | |
bd60018a | 4399 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
4400 | signal_levels |= DP_VOLTAGE_1_2; |
4401 | break; | |
4402 | } | |
3cf2efb1 | 4403 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 4404 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
4405 | default: |
4406 | signal_levels |= DP_PRE_EMPHASIS_0; | |
4407 | break; | |
bd60018a | 4408 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
4409 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
4410 | break; | |
bd60018a | 4411 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
4412 | signal_levels |= DP_PRE_EMPHASIS_6; |
4413 | break; | |
bd60018a | 4414 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
4415 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
4416 | break; | |
4417 | } | |
4418 | return signal_levels; | |
4419 | } | |
4420 | ||
fb83f72c | 4421 | static void |
a621860a VS |
4422 | g4x_set_signal_levels(struct intel_dp *intel_dp, |
4423 | const struct intel_crtc_state *crtc_state) | |
fb83f72c VS |
4424 | { |
4425 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
4426 | u8 train_set = intel_dp->train_set[0]; | |
4427 | u32 signal_levels; | |
4428 | ||
4429 | signal_levels = g4x_signal_levels(train_set); | |
4430 | ||
4431 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", | |
4432 | signal_levels); | |
4433 | ||
4434 | intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); | |
4435 | intel_dp->DP |= signal_levels; | |
4436 | ||
4437 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); | |
4438 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
4439 | } | |
4440 | ||
4d82c2b5 | 4441 | /* SNB CPU eDP voltage swing and pre-emphasis control */ |
fb83f72c | 4442 | static u32 snb_cpu_edp_signal_levels(u8 train_set) |
e3421a18 | 4443 | { |
fb83f72c VS |
4444 | u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
4445 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
4446 | ||
3c5a62b5 | 4447 | switch (signal_levels) { |
bd60018a SJ |
4448 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
4449 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 4450 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 4451 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 4452 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
4453 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
4454 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 4455 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
4456 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
4457 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 4458 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
4459 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
4460 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 4461 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 4462 | default: |
3c5a62b5 YL |
4463 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
4464 | "0x%x\n", signal_levels); | |
4465 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
4466 | } |
4467 | } | |
4468 | ||
fb83f72c | 4469 | static void |
a621860a VS |
4470 | snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, |
4471 | const struct intel_crtc_state *crtc_state) | |
fb83f72c VS |
4472 | { |
4473 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
4474 | u8 train_set = intel_dp->train_set[0]; | |
4475 | u32 signal_levels; | |
4476 | ||
4477 | signal_levels = snb_cpu_edp_signal_levels(train_set); | |
4478 | ||
4479 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", | |
4480 | signal_levels); | |
4481 | ||
4482 | intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
4483 | intel_dp->DP |= signal_levels; | |
4484 | ||
4485 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); | |
4486 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
4487 | } | |
4488 | ||
4d82c2b5 | 4489 | /* IVB CPU eDP voltage swing and pre-emphasis control */ |
fb83f72c | 4490 | static u32 ivb_cpu_edp_signal_levels(u8 train_set) |
1a2eb460 | 4491 | { |
fb83f72c VS |
4492 | u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
4493 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
4494 | ||
1a2eb460 | 4495 | switch (signal_levels) { |
bd60018a | 4496 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4497 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 4498 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 4499 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 4500 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
33520eae | 4501 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
4502 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
4503 | ||
bd60018a | 4504 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4505 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 4506 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
4507 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
4508 | ||
bd60018a | 4509 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 4510 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 4511 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
4512 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
4513 | ||
4514 | default: | |
4515 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
4516 | "0x%x\n", signal_levels); | |
4517 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
4518 | } | |
4519 | } | |
4520 | ||
fb83f72c | 4521 | static void |
a621860a VS |
4522 | ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, |
4523 | const struct intel_crtc_state *crtc_state) | |
f0a3424e | 4524 | { |
de25eb7f | 4525 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
830de422 | 4526 | u8 train_set = intel_dp->train_set[0]; |
fb83f72c | 4527 | u32 signal_levels; |
f0a3424e | 4528 | |
fb83f72c VS |
4529 | signal_levels = ivb_cpu_edp_signal_levels(train_set); |
4530 | ||
4531 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", | |
4532 | signal_levels); | |
4533 | ||
4534 | intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
4535 | intel_dp->DP |= signal_levels; | |
f0a3424e | 4536 | |
fb83f72c VS |
4537 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
4538 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
4539 | } | |
4540 | ||
a621860a VS |
4541 | void intel_dp_set_signal_levels(struct intel_dp *intel_dp, |
4542 | const struct intel_crtc_state *crtc_state) | |
fb83f72c VS |
4543 | { |
4544 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
4545 | u8 train_set = intel_dp->train_set[0]; | |
bdc6114e WK |
4546 | |
4547 | drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n", | |
4548 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK, | |
4549 | train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : ""); | |
4550 | drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n", | |
4551 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
4552 | DP_TRAIN_PRE_EMPHASIS_SHIFT, | |
4553 | train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? | |
4554 | " (max)" : ""); | |
f0a3424e | 4555 | |
a621860a | 4556 | intel_dp->set_signal_levels(intel_dp, crtc_state); |
f0a3424e PZ |
4557 | } |
4558 | ||
94223d04 | 4559 | void |
e9c176d5 | 4560 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
a621860a | 4561 | const struct intel_crtc_state *crtc_state, |
830de422 | 4562 | u8 dp_train_pat) |
a4fc5ed6 | 4563 | { |
eee3f911 | 4564 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a4fc5ed6 | 4565 | |
6777a855 ID |
4566 | if ((intel_dp_training_pattern_symbol(dp_train_pat)) != |
4567 | DP_TRAINING_PATTERN_DISABLE) | |
eee3f911 VS |
4568 | drm_dbg_kms(&dev_priv->drm, |
4569 | "Using DP training pattern TPS%d\n", | |
6777a855 | 4570 | intel_dp_training_pattern_symbol(dp_train_pat)); |
47ea7542 | 4571 | |
a621860a | 4572 | intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); |
e9c176d5 ACO |
4573 | } |
4574 | ||
a4fc5ed6 | 4575 | static void |
adc10304 VS |
4576 | intel_dp_link_down(struct intel_encoder *encoder, |
4577 | const struct intel_crtc_state *old_crtc_state) | |
a4fc5ed6 | 4578 | { |
adc10304 | 4579 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 4580 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2225f3c6 | 4581 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
adc10304 | 4582 | enum port port = encoder->port; |
830de422 | 4583 | u32 DP = intel_dp->DP; |
a4fc5ed6 | 4584 | |
eb020ca3 PB |
4585 | if (drm_WARN_ON(&dev_priv->drm, |
4586 | (intel_de_read(dev_priv, intel_dp->output_reg) & | |
4587 | DP_PORT_EN) == 0)) | |
1b39d6f3 CW |
4588 | return; |
4589 | ||
bdc6114e | 4590 | drm_dbg_kms(&dev_priv->drm, "\n"); |
32f9d658 | 4591 | |
b752e995 | 4592 | if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || |
6e266956 | 4593 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 4594 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 4595 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 4596 | } else { |
3b358cda | 4597 | DP &= ~DP_LINK_TRAIN_MASK; |
1612c8bd | 4598 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 4599 | } |
b4e33881 JN |
4600 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4601 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
5eb08b69 | 4602 | |
1612c8bd | 4603 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
b4e33881 JN |
4604 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4605 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
1612c8bd VS |
4606 | |
4607 | /* | |
4608 | * HW workaround for IBX, we need to move the port | |
4609 | * to transcoder A after disabling it to allow the | |
4610 | * matching HDMI port to be enabled on transcoder A. | |
4611 | */ | |
6e266956 | 4612 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
4613 | /* |
4614 | * We get CPU/PCH FIFO underruns on the other pipe when | |
4615 | * doing the workaround. Sweep them under the rug. | |
4616 | */ | |
4617 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
4618 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
4619 | ||
1612c8bd | 4620 | /* always enable with pattern 1 (as per spec) */ |
59b74c49 VS |
4621 | DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); |
4622 | DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | | |
4623 | DP_LINK_TRAIN_PAT_1; | |
b4e33881 JN |
4624 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4625 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
1612c8bd VS |
4626 | |
4627 | DP &= ~DP_PORT_EN; | |
b4e33881 JN |
4628 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
4629 | intel_de_posting_read(dev_priv, intel_dp->output_reg); | |
0c241d5b | 4630 | |
0f0f74bc | 4631 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
4632 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
4633 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
4634 | } |
4635 | ||
f01eca2e | 4636 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
4637 | |
4638 | intel_dp->DP = DP; | |
9f2bdb00 VS |
4639 | |
4640 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
69d93820 CW |
4641 | intel_wakeref_t wakeref; |
4642 | ||
4643 | with_pps_lock(intel_dp, wakeref) | |
4644 | intel_dp->active_pipe = INVALID_PIPE; | |
9f2bdb00 | 4645 | } |
a4fc5ed6 KP |
4646 | } |
4647 | ||
8e9d645c GM |
4648 | bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
4649 | { | |
4650 | u8 dprx = 0; | |
4651 | ||
4652 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
4653 | &dprx) != 1) | |
4654 | return false; | |
4655 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
4656 | } | |
4657 | ||
93ac092f MN |
4658 | static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) |
4659 | { | |
af67009c JN |
4660 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
4661 | ||
93ac092f MN |
4662 | /* |
4663 | * Clear the cached register set to avoid using stale values | |
4664 | * for the sinks that do not support DSC. | |
4665 | */ | |
4666 | memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); | |
4667 | ||
08cadae8 AS |
4668 | /* Clear fec_capable to avoid using stale values */ |
4669 | intel_dp->fec_capable = 0; | |
4670 | ||
93ac092f MN |
4671 | /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ |
4672 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || | |
4673 | intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
4674 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, | |
4675 | intel_dp->dsc_dpcd, | |
4676 | sizeof(intel_dp->dsc_dpcd)) < 0) | |
af67009c JN |
4677 | drm_err(&i915->drm, |
4678 | "Failed to read DPCD register 0x%x\n", | |
4679 | DP_DSC_SUPPORT); | |
93ac092f | 4680 | |
af67009c JN |
4681 | drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n", |
4682 | (int)sizeof(intel_dp->dsc_dpcd), | |
4683 | intel_dp->dsc_dpcd); | |
0ce611c9 | 4684 | |
08cadae8 | 4685 | /* FEC is supported only on DP 1.4 */ |
0ce611c9 CW |
4686 | if (!intel_dp_is_edp(intel_dp) && |
4687 | drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, | |
4688 | &intel_dp->fec_capable) < 0) | |
af67009c JN |
4689 | drm_err(&i915->drm, |
4690 | "Failed to read FEC DPCD register\n"); | |
08cadae8 | 4691 | |
af67009c JN |
4692 | drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", |
4693 | intel_dp->fec_capable); | |
93ac092f MN |
4694 | } |
4695 | } | |
4696 | ||
fe5a66f9 VS |
4697 | static bool |
4698 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
4699 | { | |
4700 | struct drm_i915_private *dev_priv = | |
4701 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 4702 | |
fe5a66f9 | 4703 | /* this function is meant to be called only once */ |
eb020ca3 | 4704 | drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); |
30d9aa42 | 4705 | |
b9936121 | 4706 | if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) |
30d9aa42 SS |
4707 | return false; |
4708 | ||
84c36753 JN |
4709 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4710 | drm_dp_is_branch(intel_dp->dpcd)); | |
12a47a42 | 4711 | |
7c838e2a JN |
4712 | /* |
4713 | * Read the eDP display control registers. | |
4714 | * | |
4715 | * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in | |
4716 | * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it | |
4717 | * set, but require eDP 1.4+ detection (e.g. for supported link rates | |
4718 | * method). The display control registers should read zero if they're | |
4719 | * not supported anyway. | |
4720 | */ | |
4721 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
4722 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
4723 | sizeof(intel_dp->edp_dpcd)) | |
bdc6114e WK |
4724 | drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", |
4725 | (int)sizeof(intel_dp->edp_dpcd), | |
4726 | intel_dp->edp_dpcd); | |
06ea66b6 | 4727 | |
84bb2916 DP |
4728 | /* |
4729 | * This has to be called after intel_dp->edp_dpcd is filled, PSR checks | |
4730 | * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] | |
4731 | */ | |
4732 | intel_psr_init_dpcd(intel_dp); | |
4733 | ||
e6ed2a1b JN |
4734 | /* Read the eDP 1.4+ supported link rates. */ |
4735 | if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
94ca719e | 4736 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
4737 | int i; |
4738 | ||
9f085ebb L |
4739 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
4740 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 4741 | |
94ca719e VS |
4742 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
4743 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
4744 | |
4745 | if (val == 0) | |
4746 | break; | |
4747 | ||
fd81c44e DP |
4748 | /* Value read multiplied by 200kHz gives the per-lane |
4749 | * link rate in kHz. The source rates are, however, | |
4750 | * stored in terms of LS_Clk kHz. The full conversion | |
4751 | * back to symbols is | |
4752 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
4753 | */ | |
af77b974 | 4754 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 4755 | } |
94ca719e | 4756 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 4757 | } |
0336400e | 4758 | |
e6ed2a1b JN |
4759 | /* |
4760 | * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, | |
4761 | * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. | |
4762 | */ | |
68f357cb JN |
4763 | if (intel_dp->num_sink_rates) |
4764 | intel_dp->use_rate_select = true; | |
4765 | else | |
4766 | intel_dp_set_sink_rates(intel_dp); | |
4767 | ||
975ee5fc JN |
4768 | intel_dp_set_common_rates(intel_dp); |
4769 | ||
93ac092f MN |
4770 | /* Read the eDP DSC DPCD registers */ |
4771 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
4772 | intel_dp_get_dsc_sink_cap(intel_dp); | |
4773 | ||
fe5a66f9 VS |
4774 | return true; |
4775 | } | |
4776 | ||
693c3ec5 LP |
4777 | static bool |
4778 | intel_dp_has_sink_count(struct intel_dp *intel_dp) | |
4779 | { | |
4780 | if (!intel_dp->attached_connector) | |
4781 | return false; | |
4782 | ||
4783 | return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, | |
4784 | intel_dp->dpcd, | |
4785 | &intel_dp->desc); | |
4786 | } | |
fe5a66f9 VS |
4787 | |
4788 | static bool | |
4789 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
4790 | { | |
4778ff05 LP |
4791 | int ret; |
4792 | ||
7b2a4ab8 ID |
4793 | intel_dp_lttpr_init(intel_dp); |
4794 | ||
b9936121 | 4795 | if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) |
fe5a66f9 VS |
4796 | return false; |
4797 | ||
eaa2b31b VS |
4798 | /* |
4799 | * Don't clobber cached eDP rates. Also skip re-reading | |
4800 | * the OUI/ID since we know it won't change. | |
4801 | */ | |
1853a9da | 4802 | if (!intel_dp_is_edp(intel_dp)) { |
eaa2b31b VS |
4803 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4804 | drm_dp_is_branch(intel_dp->dpcd)); | |
4805 | ||
68f357cb | 4806 | intel_dp_set_sink_rates(intel_dp); |
975ee5fc JN |
4807 | intel_dp_set_common_rates(intel_dp); |
4808 | } | |
68f357cb | 4809 | |
693c3ec5 | 4810 | if (intel_dp_has_sink_count(intel_dp)) { |
4778ff05 LP |
4811 | ret = drm_dp_read_sink_count(&intel_dp->aux); |
4812 | if (ret < 0) | |
2bb06265 JRS |
4813 | return false; |
4814 | ||
4815 | /* | |
4816 | * Sink count can change between short pulse hpd hence | |
4817 | * a member variable in intel_dp will track any changes | |
4818 | * between short pulse interrupts. | |
4819 | */ | |
4778ff05 | 4820 | intel_dp->sink_count = ret; |
2bb06265 JRS |
4821 | |
4822 | /* | |
4823 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
4824 | * a dongle is present but no display. Unless we require to know | |
4825 | * if a dongle is present or not, we don't need to update | |
4826 | * downstream port information. So, an early return here saves | |
4827 | * time from performing other operations which are not required. | |
4828 | */ | |
4829 | if (!intel_dp->sink_count) | |
4830 | return false; | |
4831 | } | |
0336400e | 4832 | |
3d3721cc LP |
4833 | return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, |
4834 | intel_dp->downstream_ports) == 0; | |
c4e3170a VS |
4835 | } |
4836 | ||
9dbf5a4e VS |
4837 | static bool |
4838 | intel_dp_can_mst(struct intel_dp *intel_dp) | |
4839 | { | |
8a25c4be JN |
4840 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
4841 | ||
4842 | return i915->params.enable_dp_mst && | |
9dbf5a4e | 4843 | intel_dp->can_mst && |
4b465912 | 4844 | drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); |
9dbf5a4e VS |
4845 | } |
4846 | ||
c4e3170a VS |
4847 | static void |
4848 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
4849 | { | |
af67009c | 4850 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
9dbf5a4e VS |
4851 | struct intel_encoder *encoder = |
4852 | &dp_to_dig_port(intel_dp)->base; | |
4b465912 | 4853 | bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); |
9dbf5a4e | 4854 | |
af67009c JN |
4855 | drm_dbg_kms(&i915->drm, |
4856 | "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", | |
4857 | encoder->base.base.id, encoder->base.name, | |
4858 | yesno(intel_dp->can_mst), yesno(sink_can_mst), | |
8a25c4be | 4859 | yesno(i915->params.enable_dp_mst)); |
c4e3170a VS |
4860 | |
4861 | if (!intel_dp->can_mst) | |
4862 | return; | |
4863 | ||
9dbf5a4e | 4864 | intel_dp->is_mst = sink_can_mst && |
8a25c4be | 4865 | i915->params.enable_dp_mst; |
c4e3170a VS |
4866 | |
4867 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4868 | intel_dp->is_mst); | |
0e32b39c DA |
4869 | } |
4870 | ||
0e32b39c DA |
4871 | static bool |
4872 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4873 | { | |
e8b2577c PD |
4874 | return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, |
4875 | sink_irq_vector, DP_DPRX_ESI_LEN) == | |
4876 | DP_DPRX_ESI_LEN; | |
0e32b39c DA |
4877 | } |
4878 | ||
0c06fa15 GM |
4879 | bool |
4880 | intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, | |
4881 | const struct drm_connector_state *conn_state) | |
4882 | { | |
4883 | /* | |
4884 | * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication | |
4885 | * of Color Encoding Format and Content Color Gamut], in order to | |
4886 | * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. | |
4887 | */ | |
4888 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
4889 | return true; | |
4890 | ||
4891 | switch (conn_state->colorspace) { | |
4892 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
4893 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
4894 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
4895 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
4896 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
4897 | return true; | |
4898 | default: | |
4899 | break; | |
4900 | } | |
4901 | ||
4902 | return false; | |
4903 | } | |
4904 | ||
03c761b0 GM |
4905 | static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, |
4906 | struct dp_sdp *sdp, size_t size) | |
4907 | { | |
4908 | size_t length = sizeof(struct dp_sdp); | |
4909 | ||
4910 | if (size < length) | |
4911 | return -ENOSPC; | |
4912 | ||
4913 | memset(sdp, 0, size); | |
4914 | ||
4915 | /* | |
4916 | * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 | |
4917 | * VSC SDP Header Bytes | |
4918 | */ | |
4919 | sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ | |
4920 | sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ | |
4921 | sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ | |
4922 | sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ | |
4923 | ||
cafac5a9 GM |
4924 | /* |
4925 | * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as | |
4926 | * per DP 1.4a spec. | |
4927 | */ | |
4928 | if (vsc->revision != 0x5) | |
4929 | goto out; | |
4930 | ||
03c761b0 GM |
4931 | /* VSC SDP Payload for DB16 through DB18 */ |
4932 | /* Pixel Encoding and Colorimetry Formats */ | |
4933 | sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ | |
4934 | sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ | |
4935 | ||
4936 | switch (vsc->bpc) { | |
4937 | case 6: | |
4938 | /* 6bpc: 0x0 */ | |
4939 | break; | |
4940 | case 8: | |
4941 | sdp->db[17] = 0x1; /* DB17[3:0] */ | |
4942 | break; | |
4943 | case 10: | |
4944 | sdp->db[17] = 0x2; | |
4945 | break; | |
4946 | case 12: | |
4947 | sdp->db[17] = 0x3; | |
4948 | break; | |
4949 | case 16: | |
4950 | sdp->db[17] = 0x4; | |
4951 | break; | |
4952 | default: | |
4953 | MISSING_CASE(vsc->bpc); | |
4954 | break; | |
4955 | } | |
4956 | /* Dynamic Range and Component Bit Depth */ | |
4957 | if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) | |
4958 | sdp->db[17] |= 0x80; /* DB17[7] */ | |
4959 | ||
4960 | /* Content Type */ | |
4961 | sdp->db[18] = vsc->content_type & 0x7; | |
4962 | ||
cafac5a9 | 4963 | out: |
03c761b0 GM |
4964 | return length; |
4965 | } | |
4966 | ||
4967 | static ssize_t | |
4968 | intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe, | |
4969 | struct dp_sdp *sdp, | |
4970 | size_t size) | |
4971 | { | |
4972 | size_t length = sizeof(struct dp_sdp); | |
4973 | const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; | |
4974 | unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; | |
4975 | ssize_t len; | |
4976 | ||
4977 | if (size < length) | |
4978 | return -ENOSPC; | |
4979 | ||
4980 | memset(sdp, 0, size); | |
4981 | ||
4982 | len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); | |
4983 | if (len < 0) { | |
4984 | DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n"); | |
4985 | return -ENOSPC; | |
4986 | } | |
4987 | ||
4988 | if (len != infoframe_size) { | |
4989 | DRM_DEBUG_KMS("wrong static hdr metadata size\n"); | |
4990 | return -ENOSPC; | |
4991 | } | |
4992 | ||
4993 | /* | |
4994 | * Set up the infoframe sdp packet for HDR static metadata. | |
4995 | * Prepare VSC Header for SU as per DP 1.4a spec, | |
4996 | * Table 2-100 and Table 2-101 | |
4997 | */ | |
4998 | ||
4999 | /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ | |
5000 | sdp->sdp_header.HB0 = 0; | |
5001 | /* | |
5002 | * Packet Type 80h + Non-audio INFOFRAME Type value | |
5003 | * HDMI_INFOFRAME_TYPE_DRM: 0x87 | |
5004 | * - 80h + Non-audio INFOFRAME Type value | |
5005 | * - InfoFrame Type: 0x07 | |
5006 | * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] | |
5007 | */ | |
5008 | sdp->sdp_header.HB1 = drm_infoframe->type; | |
5009 | /* | |
5010 | * Least Significant Eight Bits of (Data Byte Count – 1) | |
5011 | * infoframe_size - 1 | |
5012 | */ | |
5013 | sdp->sdp_header.HB2 = 0x1D; | |
5014 | /* INFOFRAME SDP Version Number */ | |
5015 | sdp->sdp_header.HB3 = (0x13 << 2); | |
5016 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ | |
5017 | sdp->db[0] = drm_infoframe->version; | |
5018 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ | |
5019 | sdp->db[1] = drm_infoframe->length; | |
5020 | /* | |
5021 | * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after | |
5022 | * HDMI_INFOFRAME_HEADER_SIZE | |
5023 | */ | |
5024 | BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); | |
5025 | memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], | |
5026 | HDMI_DRM_INFOFRAME_SIZE); | |
5027 | ||
5028 | /* | |
5029 | * Size of DP infoframe sdp packet for HDR static metadata consists of | |
5030 | * - DP SDP Header(struct dp_sdp_header): 4 bytes | |
5031 | * - Two Data Blocks: 2 bytes | |
5032 | * CTA Header Byte2 (INFOFRAME Version Number) | |
5033 | * CTA Header Byte3 (Length of INFOFRAME) | |
5034 | * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes | |
5035 | * | |
5036 | * Prior to GEN11's GMP register size is identical to DP HDR static metadata | |
5037 | * infoframe size. But GEN11+ has larger than that size, write_infoframe | |
5038 | * will pad rest of the size. | |
5039 | */ | |
5040 | return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; | |
5041 | } | |
5042 | ||
5043 | static void intel_write_dp_sdp(struct intel_encoder *encoder, | |
5044 | const struct intel_crtc_state *crtc_state, | |
5045 | unsigned int type) | |
5046 | { | |
7801f3b7 | 5047 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
03c761b0 GM |
5048 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5049 | struct dp_sdp sdp = {}; | |
5050 | ssize_t len; | |
5051 | ||
5052 | if ((crtc_state->infoframes.enable & | |
5053 | intel_hdmi_infoframe_enable(type)) == 0) | |
5054 | return; | |
5055 | ||
5056 | switch (type) { | |
5057 | case DP_SDP_VSC: | |
5058 | len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, | |
5059 | sizeof(sdp)); | |
5060 | break; | |
5061 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
5062 | len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm, | |
5063 | &sdp, sizeof(sdp)); | |
5064 | break; | |
5065 | default: | |
5066 | MISSING_CASE(type); | |
d121f63c | 5067 | return; |
03c761b0 GM |
5068 | } |
5069 | ||
5070 | if (drm_WARN_ON(&dev_priv->drm, len < 0)) | |
5071 | return; | |
5072 | ||
7801f3b7 | 5073 | dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); |
03c761b0 GM |
5074 | } |
5075 | ||
cafac5a9 GM |
5076 | void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, |
5077 | const struct intel_crtc_state *crtc_state, | |
5078 | struct drm_dp_vsc_sdp *vsc) | |
5079 | { | |
7801f3b7 | 5080 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
cafac5a9 GM |
5081 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5082 | struct dp_sdp sdp = {}; | |
5083 | ssize_t len; | |
5084 | ||
5085 | len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp)); | |
5086 | ||
5087 | if (drm_WARN_ON(&dev_priv->drm, len < 0)) | |
5088 | return; | |
5089 | ||
7801f3b7 | 5090 | dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, |
cafac5a9 GM |
5091 | &sdp, len); |
5092 | } | |
5093 | ||
03c761b0 GM |
5094 | void intel_dp_set_infoframes(struct intel_encoder *encoder, |
5095 | bool enable, | |
5096 | const struct intel_crtc_state *crtc_state, | |
5097 | const struct drm_connector_state *conn_state) | |
5098 | { | |
5099 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
5100 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
5101 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); | |
5102 | u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | | |
5103 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | | |
5104 | VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; | |
5105 | u32 val = intel_de_read(dev_priv, reg); | |
5106 | ||
5107 | /* TODO: Add DSC case (DIP_ENABLE_PPS) */ | |
5108 | /* When PSR is enabled, this routine doesn't disable VSC DIP */ | |
5109 | if (intel_psr_enabled(intel_dp)) | |
5110 | val &= ~dip_enable; | |
5111 | else | |
5112 | val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW); | |
5113 | ||
5114 | if (!enable) { | |
5115 | intel_de_write(dev_priv, reg, val); | |
5116 | intel_de_posting_read(dev_priv, reg); | |
5117 | return; | |
5118 | } | |
5119 | ||
5120 | intel_de_write(dev_priv, reg, val); | |
5121 | intel_de_posting_read(dev_priv, reg); | |
5122 | ||
5123 | /* When PSR is enabled, VSC SDP is handled by PSR routine */ | |
5124 | if (!intel_psr_enabled(intel_dp)) | |
5125 | intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); | |
5126 | ||
5127 | intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); | |
5128 | } | |
5129 | ||
1b404b7d GM |
5130 | static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, |
5131 | const void *buffer, size_t size) | |
5132 | { | |
5133 | const struct dp_sdp *sdp = buffer; | |
5134 | ||
5135 | if (size < sizeof(struct dp_sdp)) | |
5136 | return -EINVAL; | |
5137 | ||
5138 | memset(vsc, 0, size); | |
5139 | ||
5140 | if (sdp->sdp_header.HB0 != 0) | |
5141 | return -EINVAL; | |
5142 | ||
5143 | if (sdp->sdp_header.HB1 != DP_SDP_VSC) | |
5144 | return -EINVAL; | |
5145 | ||
5146 | vsc->sdp_type = sdp->sdp_header.HB1; | |
5147 | vsc->revision = sdp->sdp_header.HB2; | |
5148 | vsc->length = sdp->sdp_header.HB3; | |
5149 | ||
5150 | if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || | |
5151 | (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { | |
5152 | /* | |
5153 | * - HB2 = 0x2, HB3 = 0x8 | |
5154 | * VSC SDP supporting 3D stereo + PSR | |
5155 | * - HB2 = 0x4, HB3 = 0xe | |
5156 | * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of | |
5157 | * first scan line of the SU region (applies to eDP v1.4b | |
5158 | * and higher). | |
5159 | */ | |
5160 | return 0; | |
5161 | } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { | |
5162 | /* | |
5163 | * - HB2 = 0x5, HB3 = 0x13 | |
5164 | * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry | |
5165 | * Format. | |
5166 | */ | |
5167 | vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; | |
5168 | vsc->colorimetry = sdp->db[16] & 0xf; | |
5169 | vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; | |
5170 | ||
5171 | switch (sdp->db[17] & 0x7) { | |
5172 | case 0x0: | |
5173 | vsc->bpc = 6; | |
5174 | break; | |
5175 | case 0x1: | |
5176 | vsc->bpc = 8; | |
5177 | break; | |
5178 | case 0x2: | |
5179 | vsc->bpc = 10; | |
5180 | break; | |
5181 | case 0x3: | |
5182 | vsc->bpc = 12; | |
5183 | break; | |
5184 | case 0x4: | |
5185 | vsc->bpc = 16; | |
5186 | break; | |
5187 | default: | |
5188 | MISSING_CASE(sdp->db[17] & 0x7); | |
5189 | return -EINVAL; | |
5190 | } | |
5191 | ||
5192 | vsc->content_type = sdp->db[18] & 0x7; | |
5193 | } else { | |
5194 | return -EINVAL; | |
5195 | } | |
5196 | ||
5197 | return 0; | |
5198 | } | |
5199 | ||
5200 | static int | |
5201 | intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, | |
5202 | const void *buffer, size_t size) | |
5203 | { | |
5204 | int ret; | |
5205 | ||
5206 | const struct dp_sdp *sdp = buffer; | |
5207 | ||
5208 | if (size < sizeof(struct dp_sdp)) | |
5209 | return -EINVAL; | |
5210 | ||
5211 | if (sdp->sdp_header.HB0 != 0) | |
5212 | return -EINVAL; | |
5213 | ||
5214 | if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) | |
5215 | return -EINVAL; | |
5216 | ||
5217 | /* | |
5218 | * Least Significant Eight Bits of (Data Byte Count – 1) | |
5219 | * 1Dh (i.e., Data Byte Count = 30 bytes). | |
5220 | */ | |
5221 | if (sdp->sdp_header.HB2 != 0x1D) | |
5222 | return -EINVAL; | |
5223 | ||
5224 | /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ | |
5225 | if ((sdp->sdp_header.HB3 & 0x3) != 0) | |
5226 | return -EINVAL; | |
5227 | ||
5228 | /* INFOFRAME SDP Version Number */ | |
5229 | if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) | |
5230 | return -EINVAL; | |
5231 | ||
5232 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ | |
5233 | if (sdp->db[0] != 1) | |
5234 | return -EINVAL; | |
5235 | ||
5236 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ | |
5237 | if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) | |
5238 | return -EINVAL; | |
5239 | ||
5240 | ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], | |
5241 | HDMI_DRM_INFOFRAME_SIZE); | |
5242 | ||
5243 | return ret; | |
5244 | } | |
5245 | ||
5246 | static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, | |
5247 | struct intel_crtc_state *crtc_state, | |
5248 | struct drm_dp_vsc_sdp *vsc) | |
5249 | { | |
7801f3b7 | 5250 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
1b404b7d GM |
5251 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5252 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
5253 | unsigned int type = DP_SDP_VSC; | |
5254 | struct dp_sdp sdp = {}; | |
5255 | int ret; | |
5256 | ||
5257 | /* When PSR is enabled, VSC SDP is handled by PSR routine */ | |
5258 | if (intel_psr_enabled(intel_dp)) | |
5259 | return; | |
5260 | ||
5261 | if ((crtc_state->infoframes.enable & | |
5262 | intel_hdmi_infoframe_enable(type)) == 0) | |
5263 | return; | |
5264 | ||
7801f3b7 | 5265 | dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); |
1b404b7d GM |
5266 | |
5267 | ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); | |
5268 | ||
5269 | if (ret) | |
5270 | drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); | |
5271 | } | |
5272 | ||
5273 | static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, | |
5274 | struct intel_crtc_state *crtc_state, | |
5275 | struct hdmi_drm_infoframe *drm_infoframe) | |
5276 | { | |
7801f3b7 | 5277 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
1b404b7d GM |
5278 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5279 | unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; | |
5280 | struct dp_sdp sdp = {}; | |
5281 | int ret; | |
5282 | ||
5283 | if ((crtc_state->infoframes.enable & | |
5284 | intel_hdmi_infoframe_enable(type)) == 0) | |
5285 | return; | |
5286 | ||
7801f3b7 LDM |
5287 | dig_port->read_infoframe(encoder, crtc_state, type, &sdp, |
5288 | sizeof(sdp)); | |
1b404b7d GM |
5289 | |
5290 | ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, | |
5291 | sizeof(sdp)); | |
5292 | ||
5293 | if (ret) | |
5294 | drm_dbg_kms(&dev_priv->drm, | |
5295 | "Failed to unpack DP HDR Metadata Infoframe SDP\n"); | |
5296 | } | |
5297 | ||
5298 | void intel_read_dp_sdp(struct intel_encoder *encoder, | |
5299 | struct intel_crtc_state *crtc_state, | |
5300 | unsigned int type) | |
5301 | { | |
22da5d84 CW |
5302 | if (encoder->type != INTEL_OUTPUT_DDI) |
5303 | return; | |
5304 | ||
1b404b7d GM |
5305 | switch (type) { |
5306 | case DP_SDP_VSC: | |
5307 | intel_read_dp_vsc_sdp(encoder, crtc_state, | |
5308 | &crtc_state->infoframes.vsc); | |
5309 | break; | |
5310 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
5311 | intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, | |
5312 | &crtc_state->infoframes.drm.drm); | |
5313 | break; | |
5314 | default: | |
5315 | MISSING_CASE(type); | |
5316 | break; | |
5317 | } | |
5318 | } | |
5319 | ||
830de422 | 5320 | static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
c5d5ab7a | 5321 | { |
af67009c | 5322 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
da15f7cb | 5323 | int status = 0; |
140ef138 | 5324 | int test_link_rate; |
830de422 | 5325 | u8 test_lane_count, test_link_bw; |
da15f7cb MN |
5326 | /* (DP CTS 1.2) |
5327 | * 4.3.1.11 | |
5328 | */ | |
5329 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
5330 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
5331 | &test_lane_count); | |
5332 | ||
5333 | if (status <= 0) { | |
af67009c | 5334 | drm_dbg_kms(&i915->drm, "Lane count read failed\n"); |
da15f7cb MN |
5335 | return DP_TEST_NAK; |
5336 | } | |
5337 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
da15f7cb MN |
5338 | |
5339 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
5340 | &test_link_bw); | |
5341 | if (status <= 0) { | |
af67009c | 5342 | drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); |
da15f7cb MN |
5343 | return DP_TEST_NAK; |
5344 | } | |
da15f7cb | 5345 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); |
140ef138 MN |
5346 | |
5347 | /* Validate the requested link rate and lane count */ | |
5348 | if (!intel_dp_link_params_valid(intel_dp, test_link_rate, | |
5349 | test_lane_count)) | |
da15f7cb MN |
5350 | return DP_TEST_NAK; |
5351 | ||
5352 | intel_dp->compliance.test_lane_count = test_lane_count; | |
5353 | intel_dp->compliance.test_link_rate = test_link_rate; | |
5354 | ||
5355 | return DP_TEST_ACK; | |
c5d5ab7a TP |
5356 | } |
5357 | ||
830de422 | 5358 | static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
c5d5ab7a | 5359 | { |
af67009c | 5360 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 JN |
5361 | u8 test_pattern; |
5362 | u8 test_misc; | |
611032bf MN |
5363 | __be16 h_width, v_height; |
5364 | int status = 0; | |
5365 | ||
5366 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
010b9b39 JN |
5367 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, |
5368 | &test_pattern); | |
611032bf | 5369 | if (status <= 0) { |
af67009c | 5370 | drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); |
611032bf MN |
5371 | return DP_TEST_NAK; |
5372 | } | |
5373 | if (test_pattern != DP_COLOR_RAMP) | |
5374 | return DP_TEST_NAK; | |
5375 | ||
5376 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
5377 | &h_width, 2); | |
5378 | if (status <= 0) { | |
af67009c | 5379 | drm_dbg_kms(&i915->drm, "H Width read failed\n"); |
611032bf MN |
5380 | return DP_TEST_NAK; |
5381 | } | |
5382 | ||
5383 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
5384 | &v_height, 2); | |
5385 | if (status <= 0) { | |
af67009c | 5386 | drm_dbg_kms(&i915->drm, "V Height read failed\n"); |
611032bf MN |
5387 | return DP_TEST_NAK; |
5388 | } | |
5389 | ||
010b9b39 JN |
5390 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, |
5391 | &test_misc); | |
611032bf | 5392 | if (status <= 0) { |
af67009c | 5393 | drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); |
611032bf MN |
5394 | return DP_TEST_NAK; |
5395 | } | |
5396 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
5397 | return DP_TEST_NAK; | |
5398 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
5399 | return DP_TEST_NAK; | |
5400 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
5401 | case DP_TEST_BIT_DEPTH_6: | |
5402 | intel_dp->compliance.test_data.bpc = 6; | |
5403 | break; | |
5404 | case DP_TEST_BIT_DEPTH_8: | |
5405 | intel_dp->compliance.test_data.bpc = 8; | |
5406 | break; | |
5407 | default: | |
5408 | return DP_TEST_NAK; | |
5409 | } | |
5410 | ||
5411 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
5412 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
5413 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
5414 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 5415 | intel_dp->compliance.test_active = true; |
611032bf MN |
5416 | |
5417 | return DP_TEST_ACK; | |
c5d5ab7a TP |
5418 | } |
5419 | ||
830de422 | 5420 | static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) |
a60f0e38 | 5421 | { |
af67009c | 5422 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 | 5423 | u8 test_result = DP_TEST_ACK; |
559be30c TP |
5424 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
5425 | struct drm_connector *connector = &intel_connector->base; | |
5426 | ||
5427 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 5428 | connector->edid_corrupt || |
559be30c TP |
5429 | intel_dp->aux.i2c_defer_count > 6) { |
5430 | /* Check EDID read for NACKs, DEFERs and corruption | |
5431 | * (DP CTS 1.2 Core r1.1) | |
5432 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
5433 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
5434 | * 4.2.2.6 : EDID corruption detected | |
5435 | * Use failsafe mode for all cases | |
5436 | */ | |
5437 | if (intel_dp->aux.i2c_nack_count > 0 || | |
5438 | intel_dp->aux.i2c_defer_count > 0) | |
af67009c JN |
5439 | drm_dbg_kms(&i915->drm, |
5440 | "EDID read had %d NACKs, %d DEFERs\n", | |
5441 | intel_dp->aux.i2c_nack_count, | |
5442 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 5443 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 5444 | } else { |
f79b468e TS |
5445 | struct edid *block = intel_connector->detect_edid; |
5446 | ||
5447 | /* We have to write the checksum | |
5448 | * of the last block read | |
5449 | */ | |
5450 | block += intel_connector->detect_edid->extensions; | |
5451 | ||
010b9b39 JN |
5452 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, |
5453 | block->checksum) <= 0) | |
af67009c JN |
5454 | drm_dbg_kms(&i915->drm, |
5455 | "Failed to write EDID checksum\n"); | |
559be30c TP |
5456 | |
5457 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 5458 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
5459 | } |
5460 | ||
5461 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 5462 | intel_dp->compliance.test_active = true; |
559be30c | 5463 | |
c5d5ab7a TP |
5464 | return test_result; |
5465 | } | |
5466 | ||
a621860a VS |
5467 | static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, |
5468 | const struct intel_crtc_state *crtc_state) | |
8cdf7271 AM |
5469 | { |
5470 | struct drm_i915_private *dev_priv = | |
5471 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
8cdf7271 AM |
5472 | struct drm_dp_phy_test_params *data = |
5473 | &intel_dp->compliance.test_data.phytest; | |
a621860a | 5474 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
8cdf7271 AM |
5475 | enum pipe pipe = crtc->pipe; |
5476 | u32 pattern_val; | |
5477 | ||
5478 | switch (data->phy_pattern) { | |
5479 | case DP_PHY_TEST_PATTERN_NONE: | |
5480 | DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); | |
5481 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); | |
5482 | break; | |
5483 | case DP_PHY_TEST_PATTERN_D10_2: | |
5484 | DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); | |
5485 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5486 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); | |
5487 | break; | |
5488 | case DP_PHY_TEST_PATTERN_ERROR_COUNT: | |
5489 | DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); | |
5490 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5491 | DDI_DP_COMP_CTL_ENABLE | | |
5492 | DDI_DP_COMP_CTL_SCRAMBLED_0); | |
5493 | break; | |
5494 | case DP_PHY_TEST_PATTERN_PRBS7: | |
5495 | DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); | |
5496 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5497 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); | |
5498 | break; | |
5499 | case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: | |
5500 | /* | |
5501 | * FIXME: Ideally pattern should come from DPCD 0x250. As | |
5502 | * current firmware of DPR-100 could not set it, so hardcoding | |
5503 | * now for complaince test. | |
5504 | */ | |
5505 | DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); | |
5506 | pattern_val = 0x3e0f83e0; | |
5507 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); | |
5508 | pattern_val = 0x0f83e0f8; | |
5509 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); | |
5510 | pattern_val = 0x0000f83e; | |
5511 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); | |
5512 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5513 | DDI_DP_COMP_CTL_ENABLE | | |
5514 | DDI_DP_COMP_CTL_CUSTOM80); | |
5515 | break; | |
5516 | case DP_PHY_TEST_PATTERN_CP2520: | |
5517 | /* | |
5518 | * FIXME: Ideally pattern should come from DPCD 0x24A. As | |
5519 | * current firmware of DPR-100 could not set it, so hardcoding | |
5520 | * now for complaince test. | |
5521 | */ | |
5522 | DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); | |
5523 | pattern_val = 0xFB; | |
5524 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
5525 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | | |
5526 | pattern_val); | |
5527 | break; | |
5528 | default: | |
5529 | WARN(1, "Invalid Phy Test Pattern\n"); | |
5530 | } | |
5531 | } | |
5532 | ||
5533 | static void | |
a621860a VS |
5534 | intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp, |
5535 | const struct intel_crtc_state *crtc_state) | |
8cdf7271 | 5536 | { |
7801f3b7 LDM |
5537 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5538 | struct drm_device *dev = dig_port->base.base.dev; | |
8cdf7271 | 5539 | struct drm_i915_private *dev_priv = to_i915(dev); |
7801f3b7 | 5540 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
8cdf7271 AM |
5541 | enum pipe pipe = crtc->pipe; |
5542 | u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; | |
5543 | ||
5544 | trans_ddi_func_ctl_value = intel_de_read(dev_priv, | |
5545 | TRANS_DDI_FUNC_CTL(pipe)); | |
5546 | trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); | |
5547 | dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); | |
5548 | ||
5549 | trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | | |
5550 | TGL_TRANS_DDI_PORT_MASK); | |
5551 | trans_conf_value &= ~PIPECONF_ENABLE; | |
5552 | dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; | |
5553 | ||
5554 | intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); | |
5555 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), | |
5556 | trans_ddi_func_ctl_value); | |
5557 | intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); | |
5558 | } | |
5559 | ||
5560 | static void | |
a621860a VS |
5561 | intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, |
5562 | const struct intel_crtc_state *crtc_state) | |
8cdf7271 | 5563 | { |
7801f3b7 LDM |
5564 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5565 | struct drm_device *dev = dig_port->base.base.dev; | |
8cdf7271 | 5566 | struct drm_i915_private *dev_priv = to_i915(dev); |
7801f3b7 LDM |
5567 | enum port port = dig_port->base.port; |
5568 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
8cdf7271 AM |
5569 | enum pipe pipe = crtc->pipe; |
5570 | u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; | |
5571 | ||
5572 | trans_ddi_func_ctl_value = intel_de_read(dev_priv, | |
5573 | TRANS_DDI_FUNC_CTL(pipe)); | |
5574 | trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); | |
5575 | dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); | |
5576 | ||
5577 | trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | | |
5578 | TGL_TRANS_DDI_SELECT_PORT(port); | |
5579 | trans_conf_value |= PIPECONF_ENABLE; | |
5580 | dp_tp_ctl_value |= DP_TP_CTL_ENABLE; | |
5581 | ||
5582 | intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); | |
5583 | intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); | |
5584 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), | |
5585 | trans_ddi_func_ctl_value); | |
5586 | } | |
5587 | ||
a621860a VS |
5588 | static void intel_dp_process_phy_request(struct intel_dp *intel_dp, |
5589 | const struct intel_crtc_state *crtc_state) | |
8cdf7271 AM |
5590 | { |
5591 | struct drm_dp_phy_test_params *data = | |
5592 | &intel_dp->compliance.test_data.phytest; | |
5593 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
5594 | ||
5595 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
5596 | DRM_DEBUG_KMS("failed to get link status\n"); | |
5597 | return; | |
5598 | } | |
5599 | ||
5600 | /* retrieve vswing & pre-emphasis setting */ | |
a621860a | 5601 | intel_dp_get_adjust_train(intel_dp, crtc_state, link_status); |
8cdf7271 | 5602 | |
a621860a | 5603 | intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state); |
8cdf7271 | 5604 | |
a621860a | 5605 | intel_dp_set_signal_levels(intel_dp, crtc_state); |
8cdf7271 | 5606 | |
a621860a | 5607 | intel_dp_phy_pattern_update(intel_dp, crtc_state); |
8cdf7271 | 5608 | |
a621860a | 5609 | intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state); |
8cdf7271 AM |
5610 | |
5611 | drm_dp_set_phy_test_pattern(&intel_dp->aux, data, | |
5612 | link_status[DP_DPCD_REV]); | |
5613 | } | |
5614 | ||
830de422 | 5615 | static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
a60f0e38 | 5616 | { |
193af12c VS |
5617 | struct drm_dp_phy_test_params *data = |
5618 | &intel_dp->compliance.test_data.phytest; | |
88afbfdb | 5619 | |
193af12c VS |
5620 | if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { |
5621 | DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n"); | |
5622 | return DP_TEST_NAK; | |
5623 | } | |
88afbfdb | 5624 | |
193af12c VS |
5625 | /* Set test active flag here so userspace doesn't interrupt things */ |
5626 | intel_dp->compliance.test_active = true; | |
8cdf7271 | 5627 | |
193af12c | 5628 | return DP_TEST_ACK; |
c5d5ab7a TP |
5629 | } |
5630 | ||
5631 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
5632 | { | |
af67009c | 5633 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 JN |
5634 | u8 response = DP_TEST_NAK; |
5635 | u8 request = 0; | |
5ec63bbd | 5636 | int status; |
c5d5ab7a | 5637 | |
5ec63bbd | 5638 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a | 5639 | if (status <= 0) { |
af67009c JN |
5640 | drm_dbg_kms(&i915->drm, |
5641 | "Could not read test request from sink\n"); | |
c5d5ab7a TP |
5642 | goto update_status; |
5643 | } | |
5644 | ||
5ec63bbd | 5645 | switch (request) { |
c5d5ab7a | 5646 | case DP_TEST_LINK_TRAINING: |
af67009c | 5647 | drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); |
c5d5ab7a TP |
5648 | response = intel_dp_autotest_link_training(intel_dp); |
5649 | break; | |
5650 | case DP_TEST_LINK_VIDEO_PATTERN: | |
af67009c | 5651 | drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); |
c5d5ab7a TP |
5652 | response = intel_dp_autotest_video_pattern(intel_dp); |
5653 | break; | |
5654 | case DP_TEST_LINK_EDID_READ: | |
af67009c | 5655 | drm_dbg_kms(&i915->drm, "EDID test requested\n"); |
c5d5ab7a TP |
5656 | response = intel_dp_autotest_edid(intel_dp); |
5657 | break; | |
5658 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
af67009c | 5659 | drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); |
c5d5ab7a TP |
5660 | response = intel_dp_autotest_phy_pattern(intel_dp); |
5661 | break; | |
5662 | default: | |
af67009c JN |
5663 | drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", |
5664 | request); | |
c5d5ab7a TP |
5665 | break; |
5666 | } | |
5667 | ||
5ec63bbd JN |
5668 | if (response & DP_TEST_ACK) |
5669 | intel_dp->compliance.test_type = request; | |
5670 | ||
c5d5ab7a | 5671 | update_status: |
5ec63bbd | 5672 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a | 5673 | if (status <= 0) |
af67009c JN |
5674 | drm_dbg_kms(&i915->drm, |
5675 | "Could not write test response to sink\n"); | |
a60f0e38 JB |
5676 | } |
5677 | ||
8d712a7e ID |
5678 | /** |
5679 | * intel_dp_check_mst_status - service any pending MST interrupts, check link status | |
5680 | * @intel_dp: Intel DP struct | |
5681 | * | |
5682 | * Read any pending MST interrupts, call MST core to handle these and ack the | |
5683 | * interrupts. Check if the main and AUX link state is ok. | |
5684 | * | |
5685 | * Returns: | |
5686 | * - %true if pending interrupts were serviced (or no interrupts were | |
5687 | * pending) w/o detecting an error condition. | |
5688 | * - %false if an error condition - like AUX failure or a loss of link - is | |
5689 | * detected, which needs servicing from the hotplug work. | |
5690 | */ | |
5691 | static bool | |
0e32b39c DA |
5692 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
5693 | { | |
af67009c | 5694 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
8d712a7e | 5695 | bool link_ok = true; |
3c0ec2c2 | 5696 | |
4f360482 | 5697 | drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); |
3c0ec2c2 VS |
5698 | |
5699 | for (;;) { | |
5700 | u8 esi[DP_DPRX_ESI_LEN] = {}; | |
8d712a7e | 5701 | bool handled; |
0e32b39c | 5702 | int retry; |
45ef40aa | 5703 | |
8d712a7e | 5704 | if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { |
3c0ec2c2 VS |
5705 | drm_dbg_kms(&i915->drm, |
5706 | "failed to get ESI - device may have failed\n"); | |
8d712a7e ID |
5707 | link_ok = false; |
5708 | ||
5709 | break; | |
3c0ec2c2 | 5710 | } |
0e32b39c | 5711 | |
3c0ec2c2 | 5712 | /* check link status - esi[10] = 0x200c */ |
8d712a7e | 5713 | if (intel_dp->active_mst_links > 0 && link_ok && |
3c0ec2c2 VS |
5714 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
5715 | drm_dbg_kms(&i915->drm, | |
5716 | "channel EQ not ok, retraining\n"); | |
8d712a7e | 5717 | link_ok = false; |
3c0ec2c2 | 5718 | } |
0e32b39c | 5719 | |
3c0ec2c2 | 5720 | drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); |
0e32b39c | 5721 | |
3c0ec2c2 VS |
5722 | drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
5723 | if (!handled) | |
5724 | break; | |
5725 | ||
5726 | for (retry = 0; retry < 3; retry++) { | |
5727 | int wret; | |
5728 | ||
5729 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
5730 | DP_SINK_COUNT_ESI+1, | |
5731 | &esi[1], 3); | |
5732 | if (wret == 3) | |
5733 | break; | |
0e32b39c DA |
5734 | } |
5735 | } | |
3c0ec2c2 | 5736 | |
8d712a7e | 5737 | return link_ok; |
0e32b39c DA |
5738 | } |
5739 | ||
c85d200e VS |
5740 | static bool |
5741 | intel_dp_needs_link_retrain(struct intel_dp *intel_dp) | |
5742 | { | |
5743 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
5744 | ||
edb2e530 | 5745 | if (!intel_dp->link_trained) |
2f8e7ea9 JRS |
5746 | return false; |
5747 | ||
5748 | /* | |
5749 | * While PSR source HW is enabled, it will control main-link sending | |
5750 | * frames, enabling and disabling it so trying to do a retrain will fail | |
5751 | * as the link would or not be on or it could mix training patterns | |
5752 | * and frame data at the same time causing retrain to fail. | |
5753 | * Also when exiting PSR, HW will retrain the link anyways fixing | |
5754 | * any link status error. | |
5755 | */ | |
5756 | if (intel_psr_enabled(intel_dp)) | |
edb2e530 VS |
5757 | return false; |
5758 | ||
5759 | if (!intel_dp_get_link_status(intel_dp, link_status)) | |
c85d200e | 5760 | return false; |
c85d200e VS |
5761 | |
5762 | /* | |
5763 | * Validate the cached values of intel_dp->link_rate and | |
5764 | * intel_dp->lane_count before attempting to retrain. | |
a621860a VS |
5765 | * |
5766 | * FIXME would be nice to user the crtc state here, but since | |
5767 | * we need to call this from the short HPD handler that seems | |
5768 | * a bit hard. | |
c85d200e VS |
5769 | */ |
5770 | if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, | |
5771 | intel_dp->lane_count)) | |
5772 | return false; | |
5773 | ||
5774 | /* Retrain if Channel EQ or CR not ok */ | |
5775 | return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); | |
5776 | } | |
5777 | ||
f0617ff0 VS |
5778 | static bool intel_dp_has_connector(struct intel_dp *intel_dp, |
5779 | const struct drm_connector_state *conn_state) | |
5780 | { | |
5781 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5782 | struct intel_encoder *encoder; | |
5783 | enum pipe pipe; | |
5784 | ||
5785 | if (!conn_state->best_encoder) | |
5786 | return false; | |
5787 | ||
5788 | /* SST */ | |
5789 | encoder = &dp_to_dig_port(intel_dp)->base; | |
5790 | if (conn_state->best_encoder == &encoder->base) | |
5791 | return true; | |
5792 | ||
5793 | /* MST */ | |
5794 | for_each_pipe(i915, pipe) { | |
5795 | encoder = &intel_dp->mst_encoders[pipe]->base; | |
5796 | if (conn_state->best_encoder == &encoder->base) | |
5797 | return true; | |
5798 | } | |
5799 | ||
5800 | return false; | |
5801 | } | |
5802 | ||
5803 | static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp, | |
5804 | struct drm_modeset_acquire_ctx *ctx, | |
5805 | u32 *crtc_mask) | |
5806 | { | |
5807 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5808 | struct drm_connector_list_iter conn_iter; | |
5809 | struct intel_connector *connector; | |
5810 | int ret = 0; | |
5811 | ||
5812 | *crtc_mask = 0; | |
5813 | ||
5814 | if (!intel_dp_needs_link_retrain(intel_dp)) | |
5815 | return 0; | |
5816 | ||
5817 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); | |
5818 | for_each_intel_connector_iter(connector, &conn_iter) { | |
5819 | struct drm_connector_state *conn_state = | |
5820 | connector->base.state; | |
5821 | struct intel_crtc_state *crtc_state; | |
5822 | struct intel_crtc *crtc; | |
5823 | ||
5824 | if (!intel_dp_has_connector(intel_dp, conn_state)) | |
5825 | continue; | |
5826 | ||
5827 | crtc = to_intel_crtc(conn_state->crtc); | |
5828 | if (!crtc) | |
5829 | continue; | |
5830 | ||
5831 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
5832 | if (ret) | |
5833 | break; | |
5834 | ||
5835 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
5836 | ||
5837 | drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); | |
5838 | ||
5839 | if (!crtc_state->hw.active) | |
5840 | continue; | |
5841 | ||
5842 | if (conn_state->commit && | |
5843 | !try_wait_for_completion(&conn_state->commit->hw_done)) | |
5844 | continue; | |
5845 | ||
5846 | *crtc_mask |= drm_crtc_mask(&crtc->base); | |
5847 | } | |
5848 | drm_connector_list_iter_end(&conn_iter); | |
5849 | ||
5850 | if (!intel_dp_needs_link_retrain(intel_dp)) | |
5851 | *crtc_mask = 0; | |
5852 | ||
5853 | return ret; | |
5854 | } | |
5855 | ||
5856 | static bool intel_dp_is_connected(struct intel_dp *intel_dp) | |
5857 | { | |
5858 | struct intel_connector *connector = intel_dp->attached_connector; | |
5859 | ||
5860 | return connector->base.status == connector_status_connected || | |
5861 | intel_dp->is_mst; | |
5862 | } | |
5863 | ||
c85d200e VS |
5864 | int intel_dp_retrain_link(struct intel_encoder *encoder, |
5865 | struct drm_modeset_acquire_ctx *ctx) | |
bfd02b3c | 5866 | { |
bfd02b3c | 5867 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 5868 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
c85d200e | 5869 | struct intel_crtc *crtc; |
f0617ff0 | 5870 | u32 crtc_mask; |
c85d200e VS |
5871 | int ret; |
5872 | ||
f0617ff0 | 5873 | if (!intel_dp_is_connected(intel_dp)) |
c85d200e VS |
5874 | return 0; |
5875 | ||
5876 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
5877 | ctx); | |
5878 | if (ret) | |
5879 | return ret; | |
5880 | ||
f0617ff0 | 5881 | ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask); |
c85d200e VS |
5882 | if (ret) |
5883 | return ret; | |
5884 | ||
f0617ff0 | 5885 | if (crtc_mask == 0) |
c85d200e VS |
5886 | return 0; |
5887 | ||
f0617ff0 VS |
5888 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", |
5889 | encoder->base.base.id, encoder->base.name); | |
c85d200e | 5890 | |
f0617ff0 VS |
5891 | for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { |
5892 | const struct intel_crtc_state *crtc_state = | |
5893 | to_intel_crtc_state(crtc->base.state); | |
bfd02b3c | 5894 | |
f0617ff0 VS |
5895 | /* Suppress underruns caused by re-training */ |
5896 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
5897 | if (crtc_state->has_pch_encoder) | |
5898 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
5899 | intel_crtc_pch_transcoder(crtc), false); | |
5900 | } | |
bfd02b3c | 5901 | |
a621860a VS |
5902 | for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { |
5903 | const struct intel_crtc_state *crtc_state = | |
5904 | to_intel_crtc_state(crtc->base.state); | |
5905 | ||
5906 | /* retrain on the MST master transcoder */ | |
5907 | if (INTEL_GEN(dev_priv) >= 12 && | |
5908 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && | |
5909 | !intel_dp_mst_is_master_trans(crtc_state)) | |
5910 | continue; | |
5911 | ||
5912 | intel_dp_start_link_train(intel_dp, crtc_state); | |
5913 | intel_dp_stop_link_train(intel_dp, crtc_state); | |
5914 | break; | |
5915 | } | |
bfd02b3c | 5916 | |
f0617ff0 VS |
5917 | for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { |
5918 | const struct intel_crtc_state *crtc_state = | |
5919 | to_intel_crtc_state(crtc->base.state); | |
bfd02b3c | 5920 | |
f0617ff0 VS |
5921 | /* Keep underrun reporting disabled until things are stable */ |
5922 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
5923 | ||
5924 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
5925 | if (crtc_state->has_pch_encoder) | |
5926 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
5927 | intel_crtc_pch_transcoder(crtc), true); | |
5928 | } | |
c85d200e VS |
5929 | |
5930 | return 0; | |
bfd02b3c VS |
5931 | } |
5932 | ||
193af12c VS |
5933 | static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, |
5934 | struct drm_modeset_acquire_ctx *ctx, | |
5935 | u32 *crtc_mask) | |
5936 | { | |
5937 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5938 | struct drm_connector_list_iter conn_iter; | |
5939 | struct intel_connector *connector; | |
5940 | int ret = 0; | |
5941 | ||
5942 | *crtc_mask = 0; | |
5943 | ||
5944 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); | |
5945 | for_each_intel_connector_iter(connector, &conn_iter) { | |
5946 | struct drm_connector_state *conn_state = | |
5947 | connector->base.state; | |
5948 | struct intel_crtc_state *crtc_state; | |
5949 | struct intel_crtc *crtc; | |
5950 | ||
5951 | if (!intel_dp_has_connector(intel_dp, conn_state)) | |
5952 | continue; | |
5953 | ||
5954 | crtc = to_intel_crtc(conn_state->crtc); | |
5955 | if (!crtc) | |
5956 | continue; | |
5957 | ||
5958 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
5959 | if (ret) | |
5960 | break; | |
5961 | ||
5962 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
5963 | ||
5964 | drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); | |
5965 | ||
5966 | if (!crtc_state->hw.active) | |
5967 | continue; | |
5968 | ||
5969 | if (conn_state->commit && | |
5970 | !try_wait_for_completion(&conn_state->commit->hw_done)) | |
5971 | continue; | |
5972 | ||
5973 | *crtc_mask |= drm_crtc_mask(&crtc->base); | |
5974 | } | |
5975 | drm_connector_list_iter_end(&conn_iter); | |
5976 | ||
5977 | return ret; | |
5978 | } | |
5979 | ||
5980 | static int intel_dp_do_phy_test(struct intel_encoder *encoder, | |
5981 | struct drm_modeset_acquire_ctx *ctx) | |
5982 | { | |
5983 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
5984 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
a621860a | 5985 | struct intel_crtc *crtc; |
193af12c VS |
5986 | u32 crtc_mask; |
5987 | int ret; | |
5988 | ||
5989 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
5990 | ctx); | |
5991 | if (ret) | |
5992 | return ret; | |
5993 | ||
5994 | ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask); | |
5995 | if (ret) | |
5996 | return ret; | |
5997 | ||
5998 | if (crtc_mask == 0) | |
5999 | return 0; | |
6000 | ||
6001 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", | |
6002 | encoder->base.base.id, encoder->base.name); | |
a621860a VS |
6003 | |
6004 | for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { | |
6005 | const struct intel_crtc_state *crtc_state = | |
6006 | to_intel_crtc_state(crtc->base.state); | |
6007 | ||
6008 | /* test on the MST master transcoder */ | |
6009 | if (INTEL_GEN(dev_priv) >= 12 && | |
6010 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && | |
6011 | !intel_dp_mst_is_master_trans(crtc_state)) | |
6012 | continue; | |
6013 | ||
6014 | intel_dp_process_phy_request(intel_dp, crtc_state); | |
6015 | break; | |
6016 | } | |
193af12c VS |
6017 | |
6018 | return 0; | |
6019 | } | |
6020 | ||
6021 | static void intel_dp_phy_test(struct intel_encoder *encoder) | |
6022 | { | |
6023 | struct drm_modeset_acquire_ctx ctx; | |
6024 | int ret; | |
6025 | ||
6026 | drm_modeset_acquire_init(&ctx, 0); | |
6027 | ||
6028 | for (;;) { | |
6029 | ret = intel_dp_do_phy_test(encoder, &ctx); | |
6030 | ||
6031 | if (ret == -EDEADLK) { | |
6032 | drm_modeset_backoff(&ctx); | |
6033 | continue; | |
6034 | } | |
6035 | ||
6036 | break; | |
6037 | } | |
6038 | ||
6039 | drm_modeset_drop_locks(&ctx); | |
6040 | drm_modeset_acquire_fini(&ctx); | |
6041 | drm_WARN(encoder->base.dev, ret, | |
6042 | "Acquiring modeset locks failed with %i\n", ret); | |
6043 | } | |
6044 | ||
c85d200e VS |
6045 | /* |
6046 | * If display is now connected check links status, | |
6047 | * there has been known issues of link loss triggering | |
6048 | * long pulse. | |
6049 | * | |
6050 | * Some sinks (eg. ASUS PB287Q) seem to perform some | |
6051 | * weird HPD ping pong during modesets. So we can apparently | |
6052 | * end up with HPD going low during a modeset, and then | |
6053 | * going back up soon after. And once that happens we must | |
6054 | * retrain the link to get a picture. That's in case no | |
6055 | * userspace component reacted to intermittent HPD dip. | |
6056 | */ | |
3944709d ID |
6057 | static enum intel_hotplug_state |
6058 | intel_dp_hotplug(struct intel_encoder *encoder, | |
8c8919c7 | 6059 | struct intel_connector *connector) |
5c9114d0 | 6060 | { |
193af12c | 6061 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
c85d200e | 6062 | struct drm_modeset_acquire_ctx ctx; |
3944709d | 6063 | enum intel_hotplug_state state; |
c85d200e | 6064 | int ret; |
5c9114d0 | 6065 | |
193af12c VS |
6066 | if (intel_dp->compliance.test_active && |
6067 | intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { | |
6068 | intel_dp_phy_test(encoder); | |
6069 | /* just do the PHY test and nothing else */ | |
6070 | return INTEL_HOTPLUG_UNCHANGED; | |
6071 | } | |
6072 | ||
8c8919c7 | 6073 | state = intel_encoder_hotplug(encoder, connector); |
5c9114d0 | 6074 | |
c85d200e | 6075 | drm_modeset_acquire_init(&ctx, 0); |
42e5e657 | 6076 | |
c85d200e VS |
6077 | for (;;) { |
6078 | ret = intel_dp_retrain_link(encoder, &ctx); | |
5c9114d0 | 6079 | |
c85d200e VS |
6080 | if (ret == -EDEADLK) { |
6081 | drm_modeset_backoff(&ctx); | |
6082 | continue; | |
6083 | } | |
5c9114d0 | 6084 | |
c85d200e VS |
6085 | break; |
6086 | } | |
d4cb3fd9 | 6087 | |
c85d200e VS |
6088 | drm_modeset_drop_locks(&ctx); |
6089 | drm_modeset_acquire_fini(&ctx); | |
3a47ae20 PB |
6090 | drm_WARN(encoder->base.dev, ret, |
6091 | "Acquiring modeset locks failed with %i\n", ret); | |
bfd02b3c | 6092 | |
bb80c925 JRS |
6093 | /* |
6094 | * Keeping it consistent with intel_ddi_hotplug() and | |
6095 | * intel_hdmi_hotplug(). | |
6096 | */ | |
8c8919c7 | 6097 | if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) |
bb80c925 JRS |
6098 | state = INTEL_HOTPLUG_RETRY; |
6099 | ||
3944709d | 6100 | return state; |
5c9114d0 SS |
6101 | } |
6102 | ||
9844bc87 DP |
6103 | static void intel_dp_check_service_irq(struct intel_dp *intel_dp) |
6104 | { | |
af67009c | 6105 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
9844bc87 DP |
6106 | u8 val; |
6107 | ||
6108 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
6109 | return; | |
6110 | ||
6111 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
6112 | DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) | |
6113 | return; | |
6114 | ||
6115 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); | |
6116 | ||
6117 | if (val & DP_AUTOMATED_TEST_REQUEST) | |
6118 | intel_dp_handle_test_request(intel_dp); | |
6119 | ||
342ac601 | 6120 | if (val & DP_CP_IRQ) |
09d56393 | 6121 | intel_hdcp_handle_cp_irq(intel_dp->attached_connector); |
342ac601 R |
6122 | |
6123 | if (val & DP_SINK_SPECIFIC_IRQ) | |
af67009c | 6124 | drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); |
9844bc87 DP |
6125 | } |
6126 | ||
a4fc5ed6 KP |
6127 | /* |
6128 | * According to DP spec | |
6129 | * 5.1.2: | |
6130 | * 1. Read DPCD | |
6131 | * 2. Configure link according to Receiver Capabilities | |
6132 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
6133 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
6134 | * |
6135 | * intel_dp_short_pulse - handles short pulse interrupts | |
6136 | * when full detection is not required. | |
6137 | * Returns %true if short pulse is handled and full detection | |
6138 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 6139 | */ |
39ff747b | 6140 | static bool |
5c9114d0 | 6141 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 6142 | { |
de25eb7f | 6143 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
39ff747b SS |
6144 | u8 old_sink_count = intel_dp->sink_count; |
6145 | bool ret; | |
5b215bcf | 6146 | |
4df6960e SS |
6147 | /* |
6148 | * Clearing compliance test variables to allow capturing | |
6149 | * of values for next automated test request. | |
6150 | */ | |
c1617abc | 6151 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 6152 | |
39ff747b SS |
6153 | /* |
6154 | * Now read the DPCD to see if it's actually running | |
6155 | * If the current value of sink count doesn't match with | |
6156 | * the value that was stored earlier or dpcd read failed | |
6157 | * we need to do full detection | |
6158 | */ | |
6159 | ret = intel_dp_get_dpcd(intel_dp); | |
6160 | ||
6161 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
6162 | /* No need to proceed if we are going to do full detect */ | |
6163 | return false; | |
59cd09e1 JB |
6164 | } |
6165 | ||
9844bc87 | 6166 | intel_dp_check_service_irq(intel_dp); |
a60f0e38 | 6167 | |
82e00d11 HV |
6168 | /* Handle CEC interrupts, if any */ |
6169 | drm_dp_cec_irq(&intel_dp->aux); | |
6170 | ||
c85d200e VS |
6171 | /* defer to the hotplug work for link retraining if needed */ |
6172 | if (intel_dp_needs_link_retrain(intel_dp)) | |
6173 | return false; | |
42e5e657 | 6174 | |
cc3054ff JRS |
6175 | intel_psr_short_pulse(intel_dp); |
6176 | ||
193af12c VS |
6177 | switch (intel_dp->compliance.test_type) { |
6178 | case DP_TEST_LINK_TRAINING: | |
bdc6114e WK |
6179 | drm_dbg_kms(&dev_priv->drm, |
6180 | "Link Training Compliance Test requested\n"); | |
da15f7cb | 6181 | /* Send a Hotplug Uevent to userspace to start modeset */ |
2f773477 | 6182 | drm_kms_helper_hotplug_event(&dev_priv->drm); |
193af12c VS |
6183 | break; |
6184 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
6185 | drm_dbg_kms(&dev_priv->drm, | |
6186 | "PHY test pattern Compliance Test requested\n"); | |
6187 | /* | |
6188 | * Schedule long hpd to do the test | |
6189 | * | |
6190 | * FIXME get rid of the ad-hoc phy test modeset code | |
6191 | * and properly incorporate it into the normal modeset. | |
6192 | */ | |
6193 | return false; | |
da15f7cb | 6194 | } |
39ff747b SS |
6195 | |
6196 | return true; | |
a4fc5ed6 | 6197 | } |
a4fc5ed6 | 6198 | |
caf9ab24 | 6199 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 6200 | static enum drm_connector_status |
26d61aad | 6201 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 6202 | { |
af67009c | 6203 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
f542d671 | 6204 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
830de422 JN |
6205 | u8 *dpcd = intel_dp->dpcd; |
6206 | u8 type; | |
caf9ab24 | 6207 | |
4f360482 | 6208 | if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) |
ad5125d6 ID |
6209 | return connector_status_connected; |
6210 | ||
f542d671 | 6211 | lspcon_resume(dig_port); |
e393d0d6 | 6212 | |
caf9ab24 AJ |
6213 | if (!intel_dp_get_dpcd(intel_dp)) |
6214 | return connector_status_disconnected; | |
6215 | ||
6216 | /* if there's no downstream port, we're done */ | |
c726ad01 | 6217 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 6218 | return connector_status_connected; |
caf9ab24 AJ |
6219 | |
6220 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
693c3ec5 | 6221 | if (intel_dp_has_sink_count(intel_dp) && |
c9ff160b | 6222 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
30d9aa42 SS |
6223 | return intel_dp->sink_count ? |
6224 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
6225 | } |
6226 | ||
c4e3170a VS |
6227 | if (intel_dp_can_mst(intel_dp)) |
6228 | return connector_status_connected; | |
6229 | ||
caf9ab24 | 6230 | /* If no HPD, poke DDC gently */ |
0b99836f | 6231 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 6232 | return connector_status_connected; |
caf9ab24 AJ |
6233 | |
6234 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
6235 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
6236 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
6237 | if (type == DP_DS_PORT_TYPE_VGA || | |
6238 | type == DP_DS_PORT_TYPE_NON_EDID) | |
6239 | return connector_status_unknown; | |
6240 | } else { | |
6241 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
6242 | DP_DWN_STRM_PORT_TYPE_MASK; | |
6243 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
6244 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
6245 | return connector_status_unknown; | |
6246 | } | |
caf9ab24 AJ |
6247 | |
6248 | /* Anything else is out of spec, warn and ignore */ | |
af67009c | 6249 | drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); |
26d61aad | 6250 | return connector_status_disconnected; |
71ba9000 AJ |
6251 | } |
6252 | ||
d410b56d CW |
6253 | static enum drm_connector_status |
6254 | edp_detect(struct intel_dp *intel_dp) | |
6255 | { | |
b93b41af | 6256 | return connector_status_connected; |
d410b56d CW |
6257 | } |
6258 | ||
7533eb4f | 6259 | static bool ibx_digital_port_connected(struct intel_encoder *encoder) |
5eb08b69 | 6260 | { |
7533eb4f | 6261 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c7e8a3d6 | 6262 | u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; |
93e5f0b6 | 6263 | |
b4e33881 | 6264 | return intel_de_read(dev_priv, SDEISR) & bit; |
93e5f0b6 VS |
6265 | } |
6266 | ||
7533eb4f | 6267 | static bool g4x_digital_port_connected(struct intel_encoder *encoder) |
a4fc5ed6 | 6268 | { |
7533eb4f | 6269 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c | 6270 | u32 bit; |
5eb08b69 | 6271 | |
7533eb4f RV |
6272 | switch (encoder->hpd_pin) { |
6273 | case HPD_PORT_B: | |
9642c81c JN |
6274 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
6275 | break; | |
7533eb4f | 6276 | case HPD_PORT_C: |
9642c81c JN |
6277 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
6278 | break; | |
7533eb4f | 6279 | case HPD_PORT_D: |
9642c81c JN |
6280 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
6281 | break; | |
6282 | default: | |
7533eb4f | 6283 | MISSING_CASE(encoder->hpd_pin); |
9642c81c JN |
6284 | return false; |
6285 | } | |
6286 | ||
b4e33881 | 6287 | return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; |
9642c81c JN |
6288 | } |
6289 | ||
7533eb4f | 6290 | static bool gm45_digital_port_connected(struct intel_encoder *encoder) |
9642c81c | 6291 | { |
7533eb4f | 6292 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c JN |
6293 | u32 bit; |
6294 | ||
7533eb4f RV |
6295 | switch (encoder->hpd_pin) { |
6296 | case HPD_PORT_B: | |
0780cd36 | 6297 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 6298 | break; |
7533eb4f | 6299 | case HPD_PORT_C: |
0780cd36 | 6300 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 6301 | break; |
7533eb4f | 6302 | case HPD_PORT_D: |
0780cd36 | 6303 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
6304 | break; |
6305 | default: | |
7533eb4f | 6306 | MISSING_CASE(encoder->hpd_pin); |
9642c81c | 6307 | return false; |
a4fc5ed6 KP |
6308 | } |
6309 | ||
b4e33881 | 6310 | return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
6311 | } |
6312 | ||
7533eb4f | 6313 | static bool ilk_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 6314 | { |
7533eb4f | 6315 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c7e8a3d6 | 6316 | u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; |
7533eb4f | 6317 | |
c7e8a3d6 | 6318 | return intel_de_read(dev_priv, DEISR) & bit; |
b9fcddab PZ |
6319 | } |
6320 | ||
7e66bcf2 JN |
6321 | /* |
6322 | * intel_digital_port_connected - is the specified port connected? | |
7533eb4f | 6323 | * @encoder: intel_encoder |
7e66bcf2 | 6324 | * |
39d1e234 PZ |
6325 | * In cases where there's a connector physically connected but it can't be used |
6326 | * by our hardware we also return false, since the rest of the driver should | |
6327 | * pretty much treat the port as disconnected. This is relevant for type-C | |
6328 | * (starting on ICL) where there's ownership involved. | |
6329 | * | |
7533eb4f | 6330 | * Return %true if port is connected, %false otherwise. |
7e66bcf2 | 6331 | */ |
6cfe7ec0 ID |
6332 | bool intel_digital_port_connected(struct intel_encoder *encoder) |
6333 | { | |
6334 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
edc0e09c | 6335 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
96ac0813 | 6336 | bool is_connected = false; |
6cfe7ec0 | 6337 | intel_wakeref_t wakeref; |
6cfe7ec0 ID |
6338 | |
6339 | with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) | |
edc0e09c | 6340 | is_connected = dig_port->connected(encoder); |
6cfe7ec0 ID |
6341 | |
6342 | return is_connected; | |
6343 | } | |
6344 | ||
8c241fef | 6345 | static struct edid * |
beb60608 | 6346 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 6347 | { |
beb60608 | 6348 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 6349 | |
9cd300e0 JN |
6350 | /* use cached edid if we have one */ |
6351 | if (intel_connector->edid) { | |
9cd300e0 JN |
6352 | /* invalid edid */ |
6353 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
6354 | return NULL; |
6355 | ||
55e9edeb | 6356 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
6357 | } else |
6358 | return drm_get_edid(&intel_connector->base, | |
6359 | &intel_dp->aux.ddc); | |
6360 | } | |
8c241fef | 6361 | |
beb60608 | 6362 | static void |
181567aa VS |
6363 | intel_dp_update_dfp(struct intel_dp *intel_dp, |
6364 | const struct edid *edid) | |
beb60608 | 6365 | { |
530df3c0 VS |
6366 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
6367 | struct intel_connector *connector = intel_dp->attached_connector; | |
530df3c0 VS |
6368 | |
6369 | intel_dp->dfp.max_bpc = | |
6370 | drm_dp_downstream_max_bpc(intel_dp->dpcd, | |
42f2562c | 6371 | intel_dp->downstream_ports, edid); |
530df3c0 | 6372 | |
fe7cf496 VS |
6373 | intel_dp->dfp.max_dotclock = |
6374 | drm_dp_downstream_max_dotclock(intel_dp->dpcd, | |
6375 | intel_dp->downstream_ports); | |
6376 | ||
3977cd1c VS |
6377 | intel_dp->dfp.min_tmds_clock = |
6378 | drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, | |
6379 | intel_dp->downstream_ports, | |
6380 | edid); | |
6381 | intel_dp->dfp.max_tmds_clock = | |
6382 | drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, | |
6383 | intel_dp->downstream_ports, | |
6384 | edid); | |
6385 | ||
fe7cf496 | 6386 | drm_dbg_kms(&i915->drm, |
3977cd1c | 6387 | "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n", |
530df3c0 | 6388 | connector->base.base.id, connector->base.name, |
3977cd1c VS |
6389 | intel_dp->dfp.max_bpc, |
6390 | intel_dp->dfp.max_dotclock, | |
6391 | intel_dp->dfp.min_tmds_clock, | |
6392 | intel_dp->dfp.max_tmds_clock); | |
181567aa VS |
6393 | } |
6394 | ||
6395 | static void | |
6396 | intel_dp_update_420(struct intel_dp *intel_dp) | |
6397 | { | |
6398 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
6399 | struct intel_connector *connector = intel_dp->attached_connector; | |
6400 | bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420; | |
6401 | ||
6402 | /* No YCbCr output support on gmch platforms */ | |
6403 | if (HAS_GMCH(i915)) | |
6404 | return; | |
6405 | ||
6406 | /* | |
6407 | * ILK doesn't seem capable of DP YCbCr output. The | |
6408 | * displayed image is severly corrupted. SNB+ is fine. | |
6409 | */ | |
6410 | if (IS_GEN(i915, 5)) | |
6411 | return; | |
6412 | ||
6413 | is_branch = drm_dp_is_branch(intel_dp->dpcd); | |
6414 | ycbcr_420_passthrough = | |
6415 | drm_dp_downstream_420_passthrough(intel_dp->dpcd, | |
6416 | intel_dp->downstream_ports); | |
6417 | ycbcr_444_to_420 = | |
6418 | drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, | |
6419 | intel_dp->downstream_ports); | |
6420 | ||
6421 | if (INTEL_GEN(i915) >= 11) { | |
6422 | /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ | |
6423 | intel_dp->dfp.ycbcr_444_to_420 = | |
6424 | ycbcr_444_to_420 && !ycbcr_420_passthrough; | |
6425 | ||
6426 | connector->base.ycbcr_420_allowed = | |
6427 | !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough; | |
6428 | } else { | |
6429 | /* 4:4:4->4:2:0 conversion is the only way */ | |
6430 | intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420; | |
6431 | ||
6432 | connector->base.ycbcr_420_allowed = ycbcr_444_to_420; | |
6433 | } | |
6434 | ||
6435 | drm_dbg_kms(&i915->drm, | |
6436 | "[CONNECTOR:%d:%s] YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", | |
6437 | connector->base.base.id, connector->base.name, | |
6438 | yesno(connector->base.ycbcr_420_allowed), | |
6439 | yesno(intel_dp->dfp.ycbcr_444_to_420)); | |
6440 | } | |
6441 | ||
6442 | static void | |
6443 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
6444 | { | |
6445 | struct intel_connector *connector = intel_dp->attached_connector; | |
6446 | struct edid *edid; | |
6447 | ||
6448 | intel_dp_unset_edid(intel_dp); | |
6449 | edid = intel_dp_get_edid(intel_dp); | |
6450 | connector->detect_edid = edid; | |
6451 | ||
6452 | intel_dp_update_dfp(intel_dp, edid); | |
6453 | intel_dp_update_420(intel_dp); | |
beb60608 | 6454 | |
f7af425d VS |
6455 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { |
6456 | intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); | |
6457 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
6458 | } | |
6459 | ||
82e00d11 | 6460 | drm_dp_cec_set_edid(&intel_dp->aux, edid); |
0883ce81 | 6461 | intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); |
8c241fef KP |
6462 | } |
6463 | ||
beb60608 CW |
6464 | static void |
6465 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 6466 | { |
181567aa | 6467 | struct intel_connector *connector = intel_dp->attached_connector; |
8c241fef | 6468 | |
82e00d11 | 6469 | drm_dp_cec_unset_edid(&intel_dp->aux); |
181567aa VS |
6470 | kfree(connector->detect_edid); |
6471 | connector->detect_edid = NULL; | |
9cd300e0 | 6472 | |
f7af425d | 6473 | intel_dp->has_hdmi_sink = false; |
beb60608 | 6474 | intel_dp->has_audio = false; |
0883ce81 | 6475 | intel_dp->edid_quirks = 0; |
530df3c0 VS |
6476 | |
6477 | intel_dp->dfp.max_bpc = 0; | |
fe7cf496 | 6478 | intel_dp->dfp.max_dotclock = 0; |
3977cd1c VS |
6479 | intel_dp->dfp.min_tmds_clock = 0; |
6480 | intel_dp->dfp.max_tmds_clock = 0; | |
181567aa VS |
6481 | |
6482 | intel_dp->dfp.ycbcr_444_to_420 = false; | |
6483 | connector->base.ycbcr_420_allowed = false; | |
beb60608 | 6484 | } |
d6f24d0f | 6485 | |
6c5ed5ae | 6486 | static int |
cbfa8ac8 DP |
6487 | intel_dp_detect(struct drm_connector *connector, |
6488 | struct drm_modeset_acquire_ctx *ctx, | |
6489 | bool force) | |
a9756bb5 | 6490 | { |
cbfa8ac8 | 6491 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
43a6d19c | 6492 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
337837ac ID |
6493 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
6494 | struct intel_encoder *encoder = &dig_port->base; | |
a9756bb5 | 6495 | enum drm_connector_status status; |
a9756bb5 | 6496 | |
bdc6114e WK |
6497 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", |
6498 | connector->base.id, connector->name); | |
eb020ca3 PB |
6499 | drm_WARN_ON(&dev_priv->drm, |
6500 | !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); | |
6c5ed5ae | 6501 | |
b81dddb9 VS |
6502 | if (!INTEL_DISPLAY_ENABLED(dev_priv)) |
6503 | return connector_status_disconnected; | |
6504 | ||
b93b41af | 6505 | /* Can't disconnect eDP */ |
1853a9da | 6506 | if (intel_dp_is_edp(intel_dp)) |
d410b56d | 6507 | status = edp_detect(intel_dp); |
d5acd97f | 6508 | else if (intel_digital_port_connected(encoder)) |
c555a81d | 6509 | status = intel_dp_detect_dpcd(intel_dp); |
a9756bb5 | 6510 | else |
c555a81d ACO |
6511 | status = connector_status_disconnected; |
6512 | ||
5cb651a7 | 6513 | if (status == connector_status_disconnected) { |
c1617abc | 6514 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
93ac092f | 6515 | memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); |
4df6960e | 6516 | |
0e505a08 | 6517 | if (intel_dp->is_mst) { |
bdc6114e WK |
6518 | drm_dbg_kms(&dev_priv->drm, |
6519 | "MST device may have disappeared %d vs %d\n", | |
6520 | intel_dp->is_mst, | |
6521 | intel_dp->mst_mgr.mst_state); | |
0e505a08 | 6522 | intel_dp->is_mst = false; |
6523 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
6524 | intel_dp->is_mst); | |
6525 | } | |
6526 | ||
c8c8fb33 | 6527 | goto out; |
4df6960e | 6528 | } |
a9756bb5 | 6529 | |
80a8cecf ID |
6530 | /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ |
6531 | if (INTEL_GEN(dev_priv) >= 11) | |
6532 | intel_dp_get_dsc_sink_cap(intel_dp); | |
6533 | ||
6534 | intel_dp_configure_mst(intel_dp); | |
6535 | ||
6536 | /* | |
6537 | * TODO: Reset link params when switching to MST mode, until MST | |
6538 | * supports link training fallback params. | |
6539 | */ | |
6540 | if (intel_dp->reset_link_params || intel_dp->is_mst) { | |
540b0b7f JN |
6541 | /* Initial max link lane count */ |
6542 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
f482984a | 6543 | |
540b0b7f JN |
6544 | /* Initial max link rate */ |
6545 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
d7e8ef02 MN |
6546 | |
6547 | intel_dp->reset_link_params = false; | |
6548 | } | |
f482984a | 6549 | |
fe5a66f9 VS |
6550 | intel_dp_print_rates(intel_dp); |
6551 | ||
c4e3170a | 6552 | if (intel_dp->is_mst) { |
f21a2198 SS |
6553 | /* |
6554 | * If we are in MST mode then this connector | |
6555 | * won't appear connected or have anything | |
6556 | * with EDID on it | |
6557 | */ | |
0e32b39c DA |
6558 | status = connector_status_disconnected; |
6559 | goto out; | |
f24f6eb9 DP |
6560 | } |
6561 | ||
6562 | /* | |
6563 | * Some external monitors do not signal loss of link synchronization | |
6564 | * with an IRQ_HPD, so force a link status check. | |
6565 | */ | |
47658556 DP |
6566 | if (!intel_dp_is_edp(intel_dp)) { |
6567 | int ret; | |
6568 | ||
6569 | ret = intel_dp_retrain_link(encoder, ctx); | |
6cfe7ec0 | 6570 | if (ret) |
47658556 | 6571 | return ret; |
47658556 | 6572 | } |
0e32b39c | 6573 | |
4df6960e SS |
6574 | /* |
6575 | * Clearing NACK and defer counts to get their exact values | |
6576 | * while reading EDID which are required by Compliance tests | |
6577 | * 4.2.2.4 and 4.2.2.5 | |
6578 | */ | |
6579 | intel_dp->aux.i2c_nack_count = 0; | |
6580 | intel_dp->aux.i2c_defer_count = 0; | |
6581 | ||
beb60608 | 6582 | intel_dp_set_edid(intel_dp); |
cbfa8ac8 DP |
6583 | if (intel_dp_is_edp(intel_dp) || |
6584 | to_intel_connector(connector)->detect_edid) | |
5cb651a7 | 6585 | status = connector_status_connected; |
c8c8fb33 | 6586 | |
9844bc87 | 6587 | intel_dp_check_service_irq(intel_dp); |
09b1eb13 | 6588 | |
c8c8fb33 | 6589 | out: |
5cb651a7 | 6590 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 6591 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 6592 | |
a8ddac7c ID |
6593 | /* |
6594 | * Make sure the refs for power wells enabled during detect are | |
6595 | * dropped to avoid a new detect cycle triggered by HPD polling. | |
6596 | */ | |
6597 | intel_display_power_flush_work(dev_priv); | |
6598 | ||
fb823134 OV |
6599 | if (!intel_dp_is_edp(intel_dp)) |
6600 | drm_dp_set_subconnector_property(connector, | |
6601 | status, | |
6602 | intel_dp->dpcd, | |
6603 | intel_dp->downstream_ports); | |
5cb651a7 | 6604 | return status; |
f21a2198 SS |
6605 | } |
6606 | ||
beb60608 CW |
6607 | static void |
6608 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 6609 | { |
43a6d19c | 6610 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
337837ac ID |
6611 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
6612 | struct intel_encoder *intel_encoder = &dig_port->base; | |
25f78f58 | 6613 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
337837ac ID |
6614 | enum intel_display_power_domain aux_domain = |
6615 | intel_aux_power_domain(dig_port); | |
0e6e0be4 | 6616 | intel_wakeref_t wakeref; |
a4fc5ed6 | 6617 | |
bdc6114e WK |
6618 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", |
6619 | connector->base.id, connector->name); | |
beb60608 | 6620 | intel_dp_unset_edid(intel_dp); |
a4fc5ed6 | 6621 | |
beb60608 CW |
6622 | if (connector->status != connector_status_connected) |
6623 | return; | |
671dedd2 | 6624 | |
0e6e0be4 | 6625 | wakeref = intel_display_power_get(dev_priv, aux_domain); |
beb60608 CW |
6626 | |
6627 | intel_dp_set_edid(intel_dp); | |
6628 | ||
0e6e0be4 | 6629 | intel_display_power_put(dev_priv, aux_domain, wakeref); |
beb60608 CW |
6630 | } |
6631 | ||
6632 | static int intel_dp_get_modes(struct drm_connector *connector) | |
6633 | { | |
6634 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
6635 | struct edid *edid; | |
6636 | ||
6637 | edid = intel_connector->detect_edid; | |
6638 | if (edid) { | |
6639 | int ret = intel_connector_update_modes(connector, edid); | |
6640 | if (ret) | |
6641 | return ret; | |
6642 | } | |
32f9d658 | 6643 | |
f8779fda | 6644 | /* if eDP has no EDID, fall back to fixed mode */ |
4b3bb839 | 6645 | if (intel_dp_is_edp(intel_attached_dp(intel_connector)) && |
beb60608 | 6646 | intel_connector->panel.fixed_mode) { |
f8779fda | 6647 | struct drm_display_mode *mode; |
beb60608 CW |
6648 | |
6649 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 6650 | intel_connector->panel.fixed_mode); |
f8779fda | 6651 | if (mode) { |
32f9d658 ZW |
6652 | drm_mode_probed_add(connector, mode); |
6653 | return 1; | |
6654 | } | |
6655 | } | |
beb60608 | 6656 | |
4b3bb839 VS |
6657 | if (!edid) { |
6658 | struct intel_dp *intel_dp = intel_attached_dp(intel_connector); | |
6659 | struct drm_display_mode *mode; | |
6660 | ||
6661 | mode = drm_dp_downstream_mode(connector->dev, | |
6662 | intel_dp->dpcd, | |
6663 | intel_dp->downstream_ports); | |
6664 | if (mode) { | |
6665 | drm_mode_probed_add(connector, mode); | |
6666 | return 1; | |
6667 | } | |
6668 | } | |
6669 | ||
32f9d658 | 6670 | return 0; |
a4fc5ed6 KP |
6671 | } |
6672 | ||
7a418e34 CW |
6673 | static int |
6674 | intel_dp_connector_register(struct drm_connector *connector) | |
6675 | { | |
af67009c | 6676 | struct drm_i915_private *i915 = to_i915(connector->dev); |
43a6d19c | 6677 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
1ebaa0b9 CW |
6678 | int ret; |
6679 | ||
6680 | ret = intel_connector_register(connector); | |
6681 | if (ret) | |
6682 | return ret; | |
7a418e34 | 6683 | |
af67009c JN |
6684 | drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", |
6685 | intel_dp->aux.name, connector->kdev->kobj.name); | |
7a418e34 CW |
6686 | |
6687 | intel_dp->aux.dev = connector->kdev; | |
82e00d11 HV |
6688 | ret = drm_dp_aux_register(&intel_dp->aux); |
6689 | if (!ret) | |
ae85b0df | 6690 | drm_dp_cec_register_connector(&intel_dp->aux, connector); |
82e00d11 | 6691 | return ret; |
7a418e34 CW |
6692 | } |
6693 | ||
c191eca1 CW |
6694 | static void |
6695 | intel_dp_connector_unregister(struct drm_connector *connector) | |
6696 | { | |
43a6d19c | 6697 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
82e00d11 HV |
6698 | |
6699 | drm_dp_cec_unregister_connector(&intel_dp->aux); | |
6700 | drm_dp_aux_unregister(&intel_dp->aux); | |
c191eca1 CW |
6701 | intel_connector_unregister(connector); |
6702 | } | |
6703 | ||
f6bff60e | 6704 | void intel_dp_encoder_flush_work(struct drm_encoder *encoder) |
24d05927 | 6705 | { |
7801f3b7 LDM |
6706 | struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); |
6707 | struct intel_dp *intel_dp = &dig_port->dp; | |
24d05927 | 6708 | |
7801f3b7 | 6709 | intel_dp_mst_encoder_cleanup(dig_port); |
1853a9da | 6710 | if (intel_dp_is_edp(intel_dp)) { |
69d93820 CW |
6711 | intel_wakeref_t wakeref; |
6712 | ||
bd943159 | 6713 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
951468f3 VS |
6714 | /* |
6715 | * vdd might still be enabled do to the delayed vdd off. | |
6716 | * Make sure vdd is actually turned off here. | |
6717 | */ | |
69d93820 CW |
6718 | with_pps_lock(intel_dp, wakeref) |
6719 | edp_panel_vdd_off_sync(intel_dp); | |
bd943159 | 6720 | } |
99681886 CW |
6721 | |
6722 | intel_dp_aux_fini(intel_dp); | |
f6bff60e ID |
6723 | } |
6724 | ||
6725 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) | |
6726 | { | |
6727 | intel_dp_encoder_flush_work(encoder); | |
99681886 | 6728 | |
c8bd0e49 | 6729 | drm_encoder_cleanup(encoder); |
b7d02c3a | 6730 | kfree(enc_to_dig_port(to_intel_encoder(encoder))); |
24d05927 DV |
6731 | } |
6732 | ||
bf93ba67 | 6733 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b | 6734 | { |
b7d02c3a | 6735 | struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); |
69d93820 | 6736 | intel_wakeref_t wakeref; |
07f9cd0b | 6737 | |
1853a9da | 6738 | if (!intel_dp_is_edp(intel_dp)) |
07f9cd0b ID |
6739 | return; |
6740 | ||
951468f3 VS |
6741 | /* |
6742 | * vdd might still be enabled do to the delayed vdd off. | |
6743 | * Make sure vdd is actually turned off here. | |
6744 | */ | |
afa4e53a | 6745 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
69d93820 CW |
6746 | with_pps_lock(intel_dp, wakeref) |
6747 | edp_panel_vdd_off_sync(intel_dp); | |
07f9cd0b ID |
6748 | } |
6749 | ||
e219ef91 | 6750 | void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) |
063348f6 VS |
6751 | { |
6752 | struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); | |
6753 | intel_wakeref_t wakeref; | |
6754 | ||
6755 | if (!intel_dp_is_edp(intel_dp)) | |
6756 | return; | |
6757 | ||
6758 | with_pps_lock(intel_dp, wakeref) | |
6759 | wait_panel_power_cycle(intel_dp); | |
6760 | } | |
6761 | ||
49e6bc51 VS |
6762 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
6763 | { | |
de25eb7f | 6764 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
337837ac | 6765 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
49e6bc51 VS |
6766 | |
6767 | lockdep_assert_held(&dev_priv->pps_mutex); | |
6768 | ||
6769 | if (!edp_have_panel_vdd(intel_dp)) | |
6770 | return; | |
6771 | ||
6772 | /* | |
6773 | * The VDD bit needs a power domain reference, so if the bit is | |
6774 | * already enabled when we boot or resume, grab this reference and | |
6775 | * schedule a vdd off, so we don't hold on to the reference | |
6776 | * indefinitely. | |
6777 | */ | |
bdc6114e WK |
6778 | drm_dbg_kms(&dev_priv->drm, |
6779 | "VDD left on by BIOS, adjusting state tracking\n"); | |
337837ac | 6780 | intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); |
49e6bc51 VS |
6781 | |
6782 | edp_panel_vdd_schedule_off(intel_dp); | |
6783 | } | |
6784 | ||
9f2bdb00 VS |
6785 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
6786 | { | |
de25eb7f | 6787 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
59b74c49 VS |
6788 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
6789 | enum pipe pipe; | |
9f2bdb00 | 6790 | |
59b74c49 VS |
6791 | if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg, |
6792 | encoder->port, &pipe)) | |
6793 | return pipe; | |
9f2bdb00 | 6794 | |
59b74c49 | 6795 | return INVALID_PIPE; |
9f2bdb00 VS |
6796 | } |
6797 | ||
bf93ba67 | 6798 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 6799 | { |
64989ca4 | 6800 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
b7d02c3a | 6801 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); |
f542d671 | 6802 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
69d93820 | 6803 | intel_wakeref_t wakeref; |
64989ca4 VS |
6804 | |
6805 | if (!HAS_DDI(dev_priv)) | |
b4e33881 | 6806 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); |
49e6bc51 | 6807 | |
f542d671 | 6808 | lspcon_resume(dig_port); |
910530c0 | 6809 | |
d7e8ef02 MN |
6810 | intel_dp->reset_link_params = true; |
6811 | ||
b4c7ea63 ID |
6812 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6813 | !intel_dp_is_edp(intel_dp)) | |
6814 | return; | |
6815 | ||
69d93820 CW |
6816 | with_pps_lock(intel_dp, wakeref) { |
6817 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
6818 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
49e6bc51 | 6819 | |
69d93820 CW |
6820 | if (intel_dp_is_edp(intel_dp)) { |
6821 | /* | |
6822 | * Reinit the power sequencer, in case BIOS did | |
6823 | * something nasty with it. | |
6824 | */ | |
6825 | intel_dp_pps_init(intel_dp); | |
6826 | intel_edp_panel_vdd_sanitize(intel_dp); | |
6827 | } | |
9f2bdb00 | 6828 | } |
6d93c0c4 ID |
6829 | } |
6830 | ||
e24bcd34 MN |
6831 | static int intel_modeset_tile_group(struct intel_atomic_state *state, |
6832 | int tile_group_id) | |
6833 | { | |
6834 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
6835 | struct drm_connector_list_iter conn_iter; | |
6836 | struct drm_connector *connector; | |
6837 | int ret = 0; | |
6838 | ||
6839 | drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); | |
6840 | drm_for_each_connector_iter(connector, &conn_iter) { | |
6841 | struct drm_connector_state *conn_state; | |
6842 | struct intel_crtc_state *crtc_state; | |
6843 | struct intel_crtc *crtc; | |
6844 | ||
6845 | if (!connector->has_tile || | |
6846 | connector->tile_group->id != tile_group_id) | |
6847 | continue; | |
6848 | ||
6849 | conn_state = drm_atomic_get_connector_state(&state->base, | |
6850 | connector); | |
6851 | if (IS_ERR(conn_state)) { | |
6852 | ret = PTR_ERR(conn_state); | |
6853 | break; | |
6854 | } | |
6855 | ||
6856 | crtc = to_intel_crtc(conn_state->crtc); | |
6857 | ||
6858 | if (!crtc) | |
6859 | continue; | |
6860 | ||
6861 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); | |
6862 | crtc_state->uapi.mode_changed = true; | |
6863 | ||
6864 | ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); | |
6865 | if (ret) | |
6866 | break; | |
6867 | } | |
b7079cbd | 6868 | drm_connector_list_iter_end(&conn_iter); |
e24bcd34 MN |
6869 | |
6870 | return ret; | |
6871 | } | |
6872 | ||
6873 | static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) | |
6874 | { | |
6875 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
6876 | struct intel_crtc *crtc; | |
6877 | ||
6878 | if (transcoders == 0) | |
6879 | return 0; | |
6880 | ||
6881 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
6882 | struct intel_crtc_state *crtc_state; | |
6883 | int ret; | |
6884 | ||
6885 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
6886 | if (IS_ERR(crtc_state)) | |
6887 | return PTR_ERR(crtc_state); | |
6888 | ||
6889 | if (!crtc_state->hw.enable) | |
6890 | continue; | |
6891 | ||
6892 | if (!(transcoders & BIT(crtc_state->cpu_transcoder))) | |
6893 | continue; | |
6894 | ||
6895 | crtc_state->uapi.mode_changed = true; | |
6896 | ||
6897 | ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); | |
6898 | if (ret) | |
6899 | return ret; | |
6900 | ||
6901 | ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); | |
6902 | if (ret) | |
6903 | return ret; | |
6904 | ||
6905 | transcoders &= ~BIT(crtc_state->cpu_transcoder); | |
6906 | } | |
6907 | ||
eb020ca3 | 6908 | drm_WARN_ON(&dev_priv->drm, transcoders != 0); |
e24bcd34 MN |
6909 | |
6910 | return 0; | |
6911 | } | |
6912 | ||
6913 | static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, | |
6914 | struct drm_connector *connector) | |
6915 | { | |
6916 | const struct drm_connector_state *old_conn_state = | |
6917 | drm_atomic_get_old_connector_state(&state->base, connector); | |
6918 | const struct intel_crtc_state *old_crtc_state; | |
6919 | struct intel_crtc *crtc; | |
6920 | u8 transcoders; | |
6921 | ||
6922 | crtc = to_intel_crtc(old_conn_state->crtc); | |
6923 | if (!crtc) | |
6924 | return 0; | |
6925 | ||
6926 | old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); | |
6927 | ||
6928 | if (!old_crtc_state->hw.active) | |
6929 | return 0; | |
6930 | ||
6931 | transcoders = old_crtc_state->sync_mode_slaves_mask; | |
6932 | if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) | |
6933 | transcoders |= BIT(old_crtc_state->master_transcoder); | |
6934 | ||
6935 | return intel_modeset_affected_transcoders(state, | |
6936 | transcoders); | |
6937 | } | |
6938 | ||
6939 | static int intel_dp_connector_atomic_check(struct drm_connector *conn, | |
6940 | struct drm_atomic_state *_state) | |
6941 | { | |
6942 | struct drm_i915_private *dev_priv = to_i915(conn->dev); | |
6943 | struct intel_atomic_state *state = to_intel_atomic_state(_state); | |
6944 | int ret; | |
6945 | ||
6946 | ret = intel_digital_connector_atomic_check(conn, &state->base); | |
6947 | if (ret) | |
6948 | return ret; | |
6949 | ||
dc5b8ed5 VS |
6950 | /* |
6951 | * We don't enable port sync on BDW due to missing w/as and | |
6952 | * due to not having adjusted the modeset sequence appropriately. | |
6953 | */ | |
6954 | if (INTEL_GEN(dev_priv) < 9) | |
e24bcd34 MN |
6955 | return 0; |
6956 | ||
6957 | if (!intel_connector_needs_modeset(state, conn)) | |
6958 | return 0; | |
6959 | ||
6960 | if (conn->has_tile) { | |
6961 | ret = intel_modeset_tile_group(state, conn->tile_group->id); | |
6962 | if (ret) | |
6963 | return ret; | |
6964 | } | |
6965 | ||
6966 | return intel_modeset_synced_crtcs(state, conn); | |
6967 | } | |
6968 | ||
a4fc5ed6 | 6969 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
beb60608 | 6970 | .force = intel_dp_force, |
a4fc5ed6 | 6971 | .fill_modes = drm_helper_probe_single_connector_modes, |
8f647a01 ML |
6972 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
6973 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
7a418e34 | 6974 | .late_register = intel_dp_connector_register, |
c191eca1 | 6975 | .early_unregister = intel_dp_connector_unregister, |
d4b26e4f | 6976 | .destroy = intel_connector_destroy, |
c6f95f27 | 6977 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
8f647a01 | 6978 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
a4fc5ed6 KP |
6979 | }; |
6980 | ||
6981 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
6c5ed5ae | 6982 | .detect_ctx = intel_dp_detect, |
a4fc5ed6 KP |
6983 | .get_modes = intel_dp_get_modes, |
6984 | .mode_valid = intel_dp_mode_valid, | |
e24bcd34 | 6985 | .atomic_check = intel_dp_connector_atomic_check, |
a4fc5ed6 KP |
6986 | }; |
6987 | ||
a4fc5ed6 | 6988 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 6989 | .reset = intel_dp_encoder_reset, |
24d05927 | 6990 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
6991 | }; |
6992 | ||
13ea6db2 AG |
6993 | static bool intel_edp_have_power(struct intel_dp *intel_dp) |
6994 | { | |
6995 | intel_wakeref_t wakeref; | |
6996 | bool have_power = false; | |
6997 | ||
6998 | with_pps_lock(intel_dp, wakeref) { | |
6999 | have_power = edp_have_panel_power(intel_dp) && | |
7000 | edp_have_panel_vdd(intel_dp); | |
7001 | } | |
7002 | ||
7003 | return have_power; | |
7004 | } | |
7005 | ||
b2c5c181 | 7006 | enum irqreturn |
7801f3b7 | 7007 | intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) |
13cf5504 | 7008 | { |
7801f3b7 LDM |
7009 | struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); |
7010 | struct intel_dp *intel_dp = &dig_port->dp; | |
1c767b33 | 7011 | |
7801f3b7 | 7012 | if (dig_port->base.type == INTEL_OUTPUT_EDP && |
13ea6db2 | 7013 | (long_hpd || !intel_edp_have_power(intel_dp))) { |
7a7f84cc | 7014 | /* |
13ea6db2 | 7015 | * vdd off can generate a long/short pulse on eDP which |
7a7f84cc VS |
7016 | * would require vdd on to handle it, and thus we |
7017 | * would end up in an endless cycle of | |
13ea6db2 | 7018 | * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." |
7a7f84cc | 7019 | */ |
af67009c JN |
7020 | drm_dbg_kms(&i915->drm, |
7021 | "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", | |
7022 | long_hpd ? "long" : "short", | |
7801f3b7 LDM |
7023 | dig_port->base.base.base.id, |
7024 | dig_port->base.base.name); | |
a8b3d52f | 7025 | return IRQ_HANDLED; |
7a7f84cc VS |
7026 | } |
7027 | ||
af67009c | 7028 | drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", |
7801f3b7 LDM |
7029 | dig_port->base.base.base.id, |
7030 | dig_port->base.base.name, | |
af67009c | 7031 | long_hpd ? "long" : "short"); |
13cf5504 | 7032 | |
27d4efc5 | 7033 | if (long_hpd) { |
d7e8ef02 | 7034 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
7035 | return IRQ_NONE; |
7036 | } | |
7037 | ||
27d4efc5 | 7038 | if (intel_dp->is_mst) { |
8d712a7e | 7039 | if (!intel_dp_check_mst_status(intel_dp)) |
6f08ebe7 | 7040 | return IRQ_NONE; |
8d712a7e ID |
7041 | } else if (!intel_dp_short_pulse(intel_dp)) { |
7042 | return IRQ_NONE; | |
0e32b39c | 7043 | } |
b2c5c181 | 7044 | |
6f08ebe7 | 7045 | return IRQ_HANDLED; |
13cf5504 DA |
7046 | } |
7047 | ||
477ec328 | 7048 | /* check the VBT to see whether the eDP is on another port */ |
7b91bf7f | 7049 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 7050 | { |
53ce81a7 VS |
7051 | /* |
7052 | * eDP not supported on g4x. so bail out early just | |
7053 | * for a bit extra safety in case the VBT is bonkers. | |
7054 | */ | |
dd11bc10 | 7055 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
7056 | return false; |
7057 | ||
a98d9c1d | 7058 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
7059 | return true; |
7060 | ||
951d9efe | 7061 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
7062 | } |
7063 | ||
200819ab | 7064 | static void |
f684960e CW |
7065 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
7066 | { | |
8b45330a | 7067 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
68ec0736 VS |
7068 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
7069 | ||
fb823134 OV |
7070 | if (!intel_dp_is_edp(intel_dp)) |
7071 | drm_connector_attach_dp_subconnector_property(connector); | |
7072 | ||
68ec0736 VS |
7073 | if (!IS_G4X(dev_priv) && port != PORT_A) |
7074 | intel_attach_force_audio_property(connector); | |
8b45330a | 7075 | |
e953fd7b | 7076 | intel_attach_broadcast_rgb_property(connector); |
b2ae318a | 7077 | if (HAS_GMCH(dev_priv)) |
f1a12172 RS |
7078 | drm_connector_attach_max_bpc_property(connector, 6, 10); |
7079 | else if (INTEL_GEN(dev_priv) >= 5) | |
7080 | drm_connector_attach_max_bpc_property(connector, 6, 12); | |
53b41837 | 7081 | |
9d1bb6f0 GM |
7082 | intel_attach_colorspace_property(connector); |
7083 | ||
0299dfa7 GM |
7084 | if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11) |
7085 | drm_object_attach_property(&connector->base, | |
7086 | connector->dev->mode_config.hdr_output_metadata_property, | |
7087 | 0); | |
7088 | ||
1853a9da | 7089 | if (intel_dp_is_edp(intel_dp)) { |
8b45330a ML |
7090 | u32 allowed_scalers; |
7091 | ||
7092 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
b2ae318a | 7093 | if (!HAS_GMCH(dev_priv)) |
8b45330a ML |
7094 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); |
7095 | ||
7096 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
7097 | ||
eead06df | 7098 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
8b45330a | 7099 | |
53b41837 | 7100 | } |
f684960e CW |
7101 | } |
7102 | ||
dada1a9f ID |
7103 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
7104 | { | |
d28d4731 | 7105 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
7106 | intel_dp->last_power_on = jiffies; |
7107 | intel_dp->last_backlight_off = jiffies; | |
7108 | } | |
7109 | ||
67a54566 | 7110 | static void |
46bd8383 | 7111 | intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) |
67a54566 | 7112 | { |
de25eb7f | 7113 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ab3517c1 | 7114 | u32 pp_on, pp_off, pp_ctl; |
8e8232d5 | 7115 | struct pps_registers regs; |
453c5420 | 7116 | |
46bd8383 | 7117 | intel_pps_get_registers(intel_dp, ®s); |
67a54566 | 7118 | |
9eae5e27 | 7119 | pp_ctl = ilk_get_pp_control(intel_dp); |
67a54566 | 7120 | |
1b61c4a3 JN |
7121 | /* Ensure PPS is unlocked */ |
7122 | if (!HAS_DDI(dev_priv)) | |
b4e33881 | 7123 | intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); |
1b61c4a3 | 7124 | |
b4e33881 JN |
7125 | pp_on = intel_de_read(dev_priv, regs.pp_on); |
7126 | pp_off = intel_de_read(dev_priv, regs.pp_off); | |
67a54566 DV |
7127 | |
7128 | /* Pull timing values out of registers */ | |
78b36b10 JN |
7129 | seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); |
7130 | seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); | |
7131 | seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); | |
7132 | seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); | |
67a54566 | 7133 | |
ab3517c1 JN |
7134 | if (i915_mmio_reg_valid(regs.pp_div)) { |
7135 | u32 pp_div; | |
7136 | ||
b4e33881 | 7137 | pp_div = intel_de_read(dev_priv, regs.pp_div); |
ab3517c1 | 7138 | |
78b36b10 | 7139 | seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; |
ab3517c1 | 7140 | } else { |
78b36b10 | 7141 | seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; |
b0a08bec | 7142 | } |
54648618 ID |
7143 | } |
7144 | ||
de9c1b6b ID |
7145 | static void |
7146 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
7147 | { | |
7148 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
7149 | state_name, | |
7150 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
7151 | } | |
7152 | ||
7153 | static void | |
46bd8383 | 7154 | intel_pps_verify_state(struct intel_dp *intel_dp) |
de9c1b6b ID |
7155 | { |
7156 | struct edp_power_seq hw; | |
7157 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
7158 | ||
46bd8383 | 7159 | intel_pps_readout_hw_state(intel_dp, &hw); |
de9c1b6b ID |
7160 | |
7161 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
7162 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
7163 | DRM_ERROR("PPS state mismatch\n"); | |
7164 | intel_pps_dump_state("sw", sw); | |
7165 | intel_pps_dump_state("hw", &hw); | |
7166 | } | |
7167 | } | |
7168 | ||
54648618 | 7169 | static void |
46bd8383 | 7170 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) |
54648618 | 7171 | { |
de25eb7f | 7172 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
54648618 ID |
7173 | struct edp_power_seq cur, vbt, spec, |
7174 | *final = &intel_dp->pps_delays; | |
7175 | ||
7176 | lockdep_assert_held(&dev_priv->pps_mutex); | |
7177 | ||
7178 | /* already initialized? */ | |
7179 | if (final->t11_t12 != 0) | |
7180 | return; | |
7181 | ||
46bd8383 | 7182 | intel_pps_readout_hw_state(intel_dp, &cur); |
67a54566 | 7183 | |
de9c1b6b | 7184 | intel_pps_dump_state("cur", &cur); |
67a54566 | 7185 | |
6aa23e65 | 7186 | vbt = dev_priv->vbt.edp.pps; |
c99a259b MN |
7187 | /* On Toshiba Satellite P50-C-18C system the VBT T12 delay |
7188 | * of 500ms appears to be too short. Ocassionally the panel | |
7189 | * just fails to power back on. Increasing the delay to 800ms | |
7190 | * seems sufficient to avoid this problem. | |
7191 | */ | |
7192 | if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { | |
7313f5a9 | 7193 | vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); |
bdc6114e WK |
7194 | drm_dbg_kms(&dev_priv->drm, |
7195 | "Increasing T12 panel delay as per the quirk to %d\n", | |
7196 | vbt.t11_t12); | |
c99a259b | 7197 | } |
770a17a5 MN |
7198 | /* T11_T12 delay is special and actually in units of 100ms, but zero |
7199 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
7200 | * table multiplies it with 1000 to make it in units of 100usec, | |
7201 | * too. */ | |
7202 | vbt.t11_t12 += 100 * 10; | |
67a54566 DV |
7203 | |
7204 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
7205 | * our hw here, which are all in 100usec. */ | |
7206 | spec.t1_t3 = 210 * 10; | |
7207 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
7208 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
7209 | spec.t10 = 500 * 10; | |
7210 | /* This one is special and actually in units of 100ms, but zero | |
7211 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
7212 | * table multiplies it with 1000 to make it in units of 100usec, | |
7213 | * too. */ | |
7214 | spec.t11_t12 = (510 + 100) * 10; | |
7215 | ||
de9c1b6b | 7216 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
7217 | |
7218 | /* Use the max of the register settings and vbt. If both are | |
7219 | * unset, fall back to the spec limits. */ | |
36b5f425 | 7220 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
7221 | spec.field : \ |
7222 | max(cur.field, vbt.field)) | |
7223 | assign_final(t1_t3); | |
7224 | assign_final(t8); | |
7225 | assign_final(t9); | |
7226 | assign_final(t10); | |
7227 | assign_final(t11_t12); | |
7228 | #undef assign_final | |
7229 | ||
36b5f425 | 7230 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
7231 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
7232 | intel_dp->backlight_on_delay = get_delay(t8); | |
7233 | intel_dp->backlight_off_delay = get_delay(t9); | |
7234 | intel_dp->panel_power_down_delay = get_delay(t10); | |
7235 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
7236 | #undef get_delay | |
7237 | ||
bdc6114e WK |
7238 | drm_dbg_kms(&dev_priv->drm, |
7239 | "panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
7240 | intel_dp->panel_power_up_delay, | |
7241 | intel_dp->panel_power_down_delay, | |
7242 | intel_dp->panel_power_cycle_delay); | |
f30d26e4 | 7243 | |
bdc6114e WK |
7244 | drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", |
7245 | intel_dp->backlight_on_delay, | |
7246 | intel_dp->backlight_off_delay); | |
de9c1b6b ID |
7247 | |
7248 | /* | |
7249 | * We override the HW backlight delays to 1 because we do manual waits | |
7250 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
7251 | * don't do this, we'll end up waiting for the backlight off delay | |
7252 | * twice: once when we do the manual sleep, and once when we disable | |
7253 | * the panel and wait for the PP_STATUS bit to become zero. | |
7254 | */ | |
7255 | final->t8 = 1; | |
7256 | final->t9 = 1; | |
5643205c ID |
7257 | |
7258 | /* | |
7259 | * HW has only a 100msec granularity for t11_t12 so round it up | |
7260 | * accordingly. | |
7261 | */ | |
7262 | final->t11_t12 = roundup(final->t11_t12, 100 * 10); | |
f30d26e4 JN |
7263 | } |
7264 | ||
7265 | static void | |
46bd8383 | 7266 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 7267 | bool force_disable_vdd) |
f30d26e4 | 7268 | { |
de25eb7f | 7269 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ab3517c1 | 7270 | u32 pp_on, pp_off, port_sel = 0; |
b04002f4 | 7271 | int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; |
8e8232d5 | 7272 | struct pps_registers regs; |
8f4f2797 | 7273 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
36b5f425 | 7274 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 7275 | |
e39b999a | 7276 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 7277 | |
46bd8383 | 7278 | intel_pps_get_registers(intel_dp, ®s); |
453c5420 | 7279 | |
5d5ab2d2 VS |
7280 | /* |
7281 | * On some VLV machines the BIOS can leave the VDD | |
e7f2af78 | 7282 | * enabled even on power sequencers which aren't |
5d5ab2d2 VS |
7283 | * hooked up to any port. This would mess up the |
7284 | * power domain tracking the first time we pick | |
7285 | * one of these power sequencers for use since | |
7286 | * edp_panel_vdd_on() would notice that the VDD was | |
7287 | * already on and therefore wouldn't grab the power | |
7288 | * domain reference. Disable VDD first to avoid this. | |
7289 | * This also avoids spuriously turning the VDD on as | |
e7f2af78 | 7290 | * soon as the new power sequencer gets initialized. |
5d5ab2d2 VS |
7291 | */ |
7292 | if (force_disable_vdd) { | |
9eae5e27 | 7293 | u32 pp = ilk_get_pp_control(intel_dp); |
5d5ab2d2 | 7294 | |
eb020ca3 PB |
7295 | drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON, |
7296 | "Panel power already on\n"); | |
5d5ab2d2 VS |
7297 | |
7298 | if (pp & EDP_FORCE_VDD) | |
bdc6114e WK |
7299 | drm_dbg_kms(&dev_priv->drm, |
7300 | "VDD already on, disabling first\n"); | |
5d5ab2d2 VS |
7301 | |
7302 | pp &= ~EDP_FORCE_VDD; | |
7303 | ||
b4e33881 | 7304 | intel_de_write(dev_priv, regs.pp_ctrl, pp); |
5d5ab2d2 VS |
7305 | } |
7306 | ||
78b36b10 JN |
7307 | pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | |
7308 | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); | |
7309 | pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | | |
7310 | REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); | |
67a54566 DV |
7311 | |
7312 | /* Haswell doesn't have any port selection bits for the panel | |
7313 | * power sequencer any more. */ | |
920a14b2 | 7314 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 7315 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 7316 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
05bf51d3 VS |
7317 | switch (port) { |
7318 | case PORT_A: | |
a24c144c | 7319 | port_sel = PANEL_PORT_SELECT_DPA; |
05bf51d3 VS |
7320 | break; |
7321 | case PORT_C: | |
7322 | port_sel = PANEL_PORT_SELECT_DPC; | |
7323 | break; | |
7324 | case PORT_D: | |
a24c144c | 7325 | port_sel = PANEL_PORT_SELECT_DPD; |
05bf51d3 VS |
7326 | break; |
7327 | default: | |
7328 | MISSING_CASE(port); | |
7329 | break; | |
7330 | } | |
67a54566 DV |
7331 | } |
7332 | ||
453c5420 JB |
7333 | pp_on |= port_sel; |
7334 | ||
b4e33881 JN |
7335 | intel_de_write(dev_priv, regs.pp_on, pp_on); |
7336 | intel_de_write(dev_priv, regs.pp_off, pp_off); | |
ab3517c1 JN |
7337 | |
7338 | /* | |
7339 | * Compute the divisor for the pp clock, simply match the Bspec formula. | |
7340 | */ | |
7341 | if (i915_mmio_reg_valid(regs.pp_div)) { | |
b4e33881 JN |
7342 | intel_de_write(dev_priv, regs.pp_div, |
7343 | REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); | |
ab3517c1 JN |
7344 | } else { |
7345 | u32 pp_ctl; | |
7346 | ||
b4e33881 | 7347 | pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl); |
ab3517c1 | 7348 | pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; |
78b36b10 | 7349 | pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); |
b4e33881 | 7350 | intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); |
ab3517c1 | 7351 | } |
67a54566 | 7352 | |
bdc6114e WK |
7353 | drm_dbg_kms(&dev_priv->drm, |
7354 | "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", | |
b4e33881 JN |
7355 | intel_de_read(dev_priv, regs.pp_on), |
7356 | intel_de_read(dev_priv, regs.pp_off), | |
bdc6114e | 7357 | i915_mmio_reg_valid(regs.pp_div) ? |
b4e33881 JN |
7358 | intel_de_read(dev_priv, regs.pp_div) : |
7359 | (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); | |
f684960e CW |
7360 | } |
7361 | ||
46bd8383 | 7362 | static void intel_dp_pps_init(struct intel_dp *intel_dp) |
335f752b | 7363 | { |
de25eb7f | 7364 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
920a14b2 TU |
7365 | |
7366 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
7367 | vlv_initial_power_sequencer_setup(intel_dp); |
7368 | } else { | |
46bd8383 VS |
7369 | intel_dp_init_panel_power_sequencer(intel_dp); |
7370 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
335f752b ID |
7371 | } |
7372 | } | |
7373 | ||
b33a2815 VK |
7374 | /** |
7375 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 7376 | * @dev_priv: i915 device |
e896402c | 7377 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
7378 | * @refresh_rate: RR to be programmed |
7379 | * | |
7380 | * This function gets called when refresh rate (RR) has to be changed from | |
7381 | * one frequency to another. Switches can be between high and low RR | |
7382 | * supported by the panel or to any other RR based on media playback (in | |
7383 | * this case, RR value needs to be passed from user space). | |
7384 | * | |
7385 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
7386 | */ | |
85cb48a1 | 7387 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5f88a9c6 | 7388 | const struct intel_crtc_state *crtc_state, |
85cb48a1 | 7389 | int refresh_rate) |
439d7ac0 | 7390 | { |
96178eeb | 7391 | struct intel_dp *intel_dp = dev_priv->drrs.dp; |
2225f3c6 | 7392 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
96178eeb | 7393 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
7394 | |
7395 | if (refresh_rate <= 0) { | |
bdc6114e WK |
7396 | drm_dbg_kms(&dev_priv->drm, |
7397 | "Refresh rate should be positive non-zero.\n"); | |
439d7ac0 PB |
7398 | return; |
7399 | } | |
7400 | ||
96178eeb | 7401 | if (intel_dp == NULL) { |
bdc6114e | 7402 | drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); |
439d7ac0 PB |
7403 | return; |
7404 | } | |
7405 | ||
439d7ac0 | 7406 | if (!intel_crtc) { |
bdc6114e WK |
7407 | drm_dbg_kms(&dev_priv->drm, |
7408 | "DRRS: intel_crtc not initialized\n"); | |
439d7ac0 PB |
7409 | return; |
7410 | } | |
7411 | ||
96178eeb | 7412 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
bdc6114e | 7413 | drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); |
439d7ac0 PB |
7414 | return; |
7415 | } | |
7416 | ||
0425662f | 7417 | if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) == |
96178eeb | 7418 | refresh_rate) |
439d7ac0 PB |
7419 | index = DRRS_LOW_RR; |
7420 | ||
96178eeb | 7421 | if (index == dev_priv->drrs.refresh_rate_type) { |
bdc6114e WK |
7422 | drm_dbg_kms(&dev_priv->drm, |
7423 | "DRRS requested for previously set RR...ignoring\n"); | |
439d7ac0 PB |
7424 | return; |
7425 | } | |
7426 | ||
1326a92c | 7427 | if (!crtc_state->hw.active) { |
bdc6114e WK |
7428 | drm_dbg_kms(&dev_priv->drm, |
7429 | "eDP encoder disabled. CRTC not Active\n"); | |
439d7ac0 PB |
7430 | return; |
7431 | } | |
7432 | ||
85cb48a1 | 7433 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
7434 | switch (index) { |
7435 | case DRRS_HIGH_RR: | |
4c354754 | 7436 | intel_dp_set_m_n(crtc_state, M1_N1); |
a4c30b1d VK |
7437 | break; |
7438 | case DRRS_LOW_RR: | |
4c354754 | 7439 | intel_dp_set_m_n(crtc_state, M2_N2); |
a4c30b1d VK |
7440 | break; |
7441 | case DRRS_MAX_RR: | |
7442 | default: | |
bdc6114e WK |
7443 | drm_err(&dev_priv->drm, |
7444 | "Unsupported refreshrate type\n"); | |
a4c30b1d | 7445 | } |
85cb48a1 ML |
7446 | } else if (INTEL_GEN(dev_priv) > 6) { |
7447 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 7448 | u32 val; |
a4c30b1d | 7449 | |
b4e33881 | 7450 | val = intel_de_read(dev_priv, reg); |
439d7ac0 | 7451 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 7452 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
7453 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
7454 | else | |
7455 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 7456 | } else { |
85cb48a1 | 7457 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
7458 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
7459 | else | |
7460 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 7461 | } |
b4e33881 | 7462 | intel_de_write(dev_priv, reg, val); |
439d7ac0 PB |
7463 | } |
7464 | ||
4e9ac947 VK |
7465 | dev_priv->drrs.refresh_rate_type = index; |
7466 | ||
bdc6114e WK |
7467 | drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", |
7468 | refresh_rate); | |
4e9ac947 VK |
7469 | } |
7470 | ||
8040fefa JRS |
7471 | static void |
7472 | intel_edp_drrs_enable_locked(struct intel_dp *intel_dp) | |
7473 | { | |
7474 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
7475 | ||
7476 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
7477 | dev_priv->drrs.dp = intel_dp; | |
7478 | } | |
7479 | ||
b33a2815 VK |
7480 | /** |
7481 | * intel_edp_drrs_enable - init drrs struct if supported | |
7482 | * @intel_dp: DP struct | |
5423adf1 | 7483 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
7484 | * |
7485 | * Initializes frontbuffer_bits and drrs.dp | |
7486 | */ | |
85cb48a1 | 7487 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 7488 | const struct intel_crtc_state *crtc_state) |
c395578e | 7489 | { |
de25eb7f | 7490 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c395578e | 7491 | |
be2dd718 | 7492 | if (!crtc_state->has_drrs) |
c395578e | 7493 | return; |
c395578e | 7494 | |
be2dd718 | 7495 | drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); |
da83ef85 | 7496 | |
c395578e | 7497 | mutex_lock(&dev_priv->drrs.mutex); |
8040fefa | 7498 | |
f69a0d71 | 7499 | if (dev_priv->drrs.dp) { |
8040fefa | 7500 | drm_warn(&dev_priv->drm, "DRRS already enabled\n"); |
c395578e VK |
7501 | goto unlock; |
7502 | } | |
7503 | ||
8040fefa | 7504 | intel_edp_drrs_enable_locked(intel_dp); |
c395578e VK |
7505 | |
7506 | unlock: | |
7507 | mutex_unlock(&dev_priv->drrs.mutex); | |
7508 | } | |
7509 | ||
8040fefa JRS |
7510 | static void |
7511 | intel_edp_drrs_disable_locked(struct intel_dp *intel_dp, | |
7512 | const struct intel_crtc_state *crtc_state) | |
7513 | { | |
7514 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
7515 | ||
7516 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) { | |
7517 | int refresh; | |
7518 | ||
7519 | refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode); | |
7520 | intel_dp_set_drrs_state(dev_priv, crtc_state, refresh); | |
7521 | } | |
7522 | ||
7523 | dev_priv->drrs.dp = NULL; | |
7524 | } | |
7525 | ||
b33a2815 VK |
7526 | /** |
7527 | * intel_edp_drrs_disable - Disable DRRS | |
7528 | * @intel_dp: DP struct | |
5423adf1 | 7529 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
7530 | * |
7531 | */ | |
85cb48a1 | 7532 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 7533 | const struct intel_crtc_state *old_crtc_state) |
c395578e | 7534 | { |
de25eb7f | 7535 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c395578e | 7536 | |
85cb48a1 | 7537 | if (!old_crtc_state->has_drrs) |
c395578e VK |
7538 | return; |
7539 | ||
7540 | mutex_lock(&dev_priv->drrs.mutex); | |
7541 | if (!dev_priv->drrs.dp) { | |
7542 | mutex_unlock(&dev_priv->drrs.mutex); | |
7543 | return; | |
7544 | } | |
7545 | ||
8040fefa | 7546 | intel_edp_drrs_disable_locked(intel_dp, old_crtc_state); |
c395578e VK |
7547 | mutex_unlock(&dev_priv->drrs.mutex); |
7548 | ||
7549 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
7550 | } | |
7551 | ||
8040fefa JRS |
7552 | /** |
7553 | * intel_edp_drrs_update - Update DRRS state | |
7554 | * @intel_dp: Intel DP | |
7555 | * @crtc_state: new CRTC state | |
7556 | * | |
7557 | * This function will update DRRS states, disabling or enabling DRRS when | |
7558 | * executing fastsets. For full modeset, intel_edp_drrs_disable() and | |
7559 | * intel_edp_drrs_enable() should be called instead. | |
7560 | */ | |
7561 | void | |
7562 | intel_edp_drrs_update(struct intel_dp *intel_dp, | |
7563 | const struct intel_crtc_state *crtc_state) | |
7564 | { | |
7565 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
7566 | ||
7567 | if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) | |
7568 | return; | |
7569 | ||
7570 | mutex_lock(&dev_priv->drrs.mutex); | |
7571 | ||
7572 | /* New state matches current one? */ | |
7573 | if (crtc_state->has_drrs == !!dev_priv->drrs.dp) | |
7574 | goto unlock; | |
7575 | ||
7576 | if (crtc_state->has_drrs) | |
7577 | intel_edp_drrs_enable_locked(intel_dp); | |
7578 | else | |
7579 | intel_edp_drrs_disable_locked(intel_dp, crtc_state); | |
7580 | ||
7581 | unlock: | |
7582 | mutex_unlock(&dev_priv->drrs.mutex); | |
7583 | } | |
7584 | ||
4e9ac947 VK |
7585 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
7586 | { | |
7587 | struct drm_i915_private *dev_priv = | |
7588 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
7589 | struct intel_dp *intel_dp; | |
7590 | ||
7591 | mutex_lock(&dev_priv->drrs.mutex); | |
7592 | ||
7593 | intel_dp = dev_priv->drrs.dp; | |
7594 | ||
7595 | if (!intel_dp) | |
7596 | goto unlock; | |
7597 | ||
439d7ac0 | 7598 | /* |
4e9ac947 VK |
7599 | * The delayed work can race with an invalidate hence we need to |
7600 | * recheck. | |
439d7ac0 PB |
7601 | */ |
7602 | ||
4e9ac947 VK |
7603 | if (dev_priv->drrs.busy_frontbuffer_bits) |
7604 | goto unlock; | |
439d7ac0 | 7605 | |
85cb48a1 ML |
7606 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
7607 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
7608 | ||
7609 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
0425662f | 7610 | drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode)); |
85cb48a1 | 7611 | } |
439d7ac0 | 7612 | |
4e9ac947 | 7613 | unlock: |
4e9ac947 | 7614 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
7615 | } |
7616 | ||
b33a2815 | 7617 | /** |
0ddfd203 | 7618 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 7619 | * @dev_priv: i915 device |
b33a2815 VK |
7620 | * @frontbuffer_bits: frontbuffer plane tracking bits |
7621 | * | |
0ddfd203 R |
7622 | * This function gets called everytime rendering on the given planes start. |
7623 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
7624 | * |
7625 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
7626 | */ | |
5748b6a1 CW |
7627 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
7628 | unsigned int frontbuffer_bits) | |
a93fad0f | 7629 | { |
6770ef33 | 7630 | struct intel_dp *intel_dp; |
a93fad0f VK |
7631 | struct drm_crtc *crtc; |
7632 | enum pipe pipe; | |
7633 | ||
9da7d693 | 7634 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
7635 | return; |
7636 | ||
88f933a8 | 7637 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 7638 | |
a93fad0f | 7639 | mutex_lock(&dev_priv->drrs.mutex); |
6770ef33 VS |
7640 | |
7641 | intel_dp = dev_priv->drrs.dp; | |
7642 | if (!intel_dp) { | |
9da7d693 DV |
7643 | mutex_unlock(&dev_priv->drrs.mutex); |
7644 | return; | |
7645 | } | |
7646 | ||
6770ef33 | 7647 | crtc = dp_to_dig_port(intel_dp)->base.base.crtc; |
a93fad0f VK |
7648 | pipe = to_intel_crtc(crtc)->pipe; |
7649 | ||
c1d038c6 DV |
7650 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
7651 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
7652 | ||
0ddfd203 | 7653 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 7654 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 | 7655 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
0425662f | 7656 | drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode)); |
a93fad0f | 7657 | |
a93fad0f VK |
7658 | mutex_unlock(&dev_priv->drrs.mutex); |
7659 | } | |
7660 | ||
b33a2815 | 7661 | /** |
0ddfd203 | 7662 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 7663 | * @dev_priv: i915 device |
b33a2815 VK |
7664 | * @frontbuffer_bits: frontbuffer plane tracking bits |
7665 | * | |
0ddfd203 R |
7666 | * This function gets called every time rendering on the given planes has |
7667 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
7668 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
7669 | * if no other planes are dirty. | |
b33a2815 VK |
7670 | * |
7671 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
7672 | */ | |
5748b6a1 CW |
7673 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
7674 | unsigned int frontbuffer_bits) | |
a93fad0f | 7675 | { |
6770ef33 | 7676 | struct intel_dp *intel_dp; |
a93fad0f VK |
7677 | struct drm_crtc *crtc; |
7678 | enum pipe pipe; | |
7679 | ||
9da7d693 | 7680 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
7681 | return; |
7682 | ||
88f933a8 | 7683 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 7684 | |
a93fad0f | 7685 | mutex_lock(&dev_priv->drrs.mutex); |
6770ef33 VS |
7686 | |
7687 | intel_dp = dev_priv->drrs.dp; | |
7688 | if (!intel_dp) { | |
9da7d693 DV |
7689 | mutex_unlock(&dev_priv->drrs.mutex); |
7690 | return; | |
7691 | } | |
7692 | ||
6770ef33 | 7693 | crtc = dp_to_dig_port(intel_dp)->base.base.crtc; |
a93fad0f | 7694 | pipe = to_intel_crtc(crtc)->pipe; |
c1d038c6 DV |
7695 | |
7696 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
7697 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
7698 | ||
0ddfd203 | 7699 | /* flush means busy screen hence upclock */ |
c1d038c6 | 7700 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 | 7701 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
0425662f | 7702 | drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode)); |
0ddfd203 R |
7703 | |
7704 | /* | |
7705 | * flush also means no more activity hence schedule downclock, if all | |
7706 | * other fbs are quiescent too | |
7707 | */ | |
7708 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
7709 | schedule_delayed_work(&dev_priv->drrs.work, |
7710 | msecs_to_jiffies(1000)); | |
7711 | mutex_unlock(&dev_priv->drrs.mutex); | |
7712 | } | |
7713 | ||
b33a2815 VK |
7714 | /** |
7715 | * DOC: Display Refresh Rate Switching (DRRS) | |
7716 | * | |
7717 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
7718 | * which enables swtching between low and high refresh rates, | |
7719 | * dynamically, based on the usage scenario. This feature is applicable | |
7720 | * for internal panels. | |
7721 | * | |
7722 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
7723 | * would list multiple refresh rates for one resolution. | |
7724 | * | |
7725 | * DRRS is of 2 types - static and seamless. | |
7726 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
7727 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
7728 | * Seamless DRRS involves changing RR without any visual effect to the user | |
7729 | * and can be used during normal system usage. This is done by programming | |
7730 | * certain registers. | |
7731 | * | |
7732 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
7733 | * inputs from the panel spec. | |
7734 | * | |
7735 | * DRRS saves power by switching to low RR based on usage scenarios. | |
7736 | * | |
2e7a5701 DV |
7737 | * The implementation is based on frontbuffer tracking implementation. When |
7738 | * there is a disturbance on the screen triggered by user activity or a periodic | |
7739 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
7740 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
7741 | * made. | |
7742 | * | |
7743 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
7744 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
7745 | * |
7746 | * DRRS can be further extended to support other internal panels and also | |
7747 | * the scenario of video playback wherein RR is set based on the rate | |
7748 | * requested by userspace. | |
7749 | */ | |
7750 | ||
7751 | /** | |
7752 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
2f773477 | 7753 | * @connector: eDP connector |
b33a2815 VK |
7754 | * @fixed_mode: preferred mode of panel |
7755 | * | |
7756 | * This function is called only once at driver load to initialize basic | |
7757 | * DRRS stuff. | |
7758 | * | |
7759 | * Returns: | |
7760 | * Downclock mode if panel supports it, else return NULL. | |
7761 | * DRRS support is determined by the presence of downclock mode (apart | |
7762 | * from VBT setting). | |
7763 | */ | |
4f9db5b5 | 7764 | static struct drm_display_mode * |
2f773477 VS |
7765 | intel_dp_drrs_init(struct intel_connector *connector, |
7766 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 | 7767 | { |
2f773477 | 7768 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
4f9db5b5 PB |
7769 | struct drm_display_mode *downclock_mode = NULL; |
7770 | ||
9da7d693 DV |
7771 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
7772 | mutex_init(&dev_priv->drrs.mutex); | |
7773 | ||
dd11bc10 | 7774 | if (INTEL_GEN(dev_priv) <= 6) { |
bdc6114e WK |
7775 | drm_dbg_kms(&dev_priv->drm, |
7776 | "DRRS supported for Gen7 and above\n"); | |
4f9db5b5 PB |
7777 | return NULL; |
7778 | } | |
7779 | ||
7780 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
bdc6114e | 7781 | drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
7782 | return NULL; |
7783 | } | |
7784 | ||
abf1aae8 | 7785 | downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); |
4f9db5b5 | 7786 | if (!downclock_mode) { |
bdc6114e WK |
7787 | drm_dbg_kms(&dev_priv->drm, |
7788 | "Downclock mode is not found. DRRS not supported\n"); | |
4f9db5b5 PB |
7789 | return NULL; |
7790 | } | |
7791 | ||
96178eeb | 7792 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 7793 | |
96178eeb | 7794 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
bdc6114e WK |
7795 | drm_dbg_kms(&dev_priv->drm, |
7796 | "seamless DRRS supported for eDP panel.\n"); | |
4f9db5b5 PB |
7797 | return downclock_mode; |
7798 | } | |
7799 | ||
ed92f0b2 | 7800 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 7801 | struct intel_connector *intel_connector) |
ed92f0b2 | 7802 | { |
de25eb7f RV |
7803 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
7804 | struct drm_device *dev = &dev_priv->drm; | |
2f773477 | 7805 | struct drm_connector *connector = &intel_connector->base; |
ed92f0b2 | 7806 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 7807 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 | 7808 | bool has_dpcd; |
6517d273 | 7809 | enum pipe pipe = INVALID_PIPE; |
69d93820 CW |
7810 | intel_wakeref_t wakeref; |
7811 | struct edid *edid; | |
ed92f0b2 | 7812 | |
1853a9da | 7813 | if (!intel_dp_is_edp(intel_dp)) |
ed92f0b2 PZ |
7814 | return true; |
7815 | ||
36b80aa3 JRS |
7816 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work); |
7817 | ||
97a824e1 ID |
7818 | /* |
7819 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
7820 | * driver uses the only internal power sequencer available for both | |
7821 | * eDP and LVDS bail out early in this case to prevent interfering | |
7822 | * with an already powered-on LVDS power sequencer. | |
7823 | */ | |
17be4942 | 7824 | if (intel_get_lvds_encoder(dev_priv)) { |
eb020ca3 PB |
7825 | drm_WARN_ON(dev, |
7826 | !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
bdc6114e WK |
7827 | drm_info(&dev_priv->drm, |
7828 | "LVDS was detected, not registering eDP\n"); | |
97a824e1 ID |
7829 | |
7830 | return false; | |
7831 | } | |
7832 | ||
69d93820 CW |
7833 | with_pps_lock(intel_dp, wakeref) { |
7834 | intel_dp_init_panel_power_timestamps(intel_dp); | |
7835 | intel_dp_pps_init(intel_dp); | |
7836 | intel_edp_panel_vdd_sanitize(intel_dp); | |
7837 | } | |
63635217 | 7838 | |
ed92f0b2 | 7839 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 7840 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 7841 | |
fe5a66f9 | 7842 | if (!has_dpcd) { |
ed92f0b2 | 7843 | /* if this fails, presume the device is a ghost */ |
bdc6114e WK |
7844 | drm_info(&dev_priv->drm, |
7845 | "failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 7846 | goto out_vdd_off; |
ed92f0b2 PZ |
7847 | } |
7848 | ||
060c8778 | 7849 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 7850 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
7851 | if (edid) { |
7852 | if (drm_add_edid_modes(connector, edid)) { | |
0883ce81 LP |
7853 | drm_connector_update_edid_property(connector, edid); |
7854 | intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); | |
ed92f0b2 PZ |
7855 | } else { |
7856 | kfree(edid); | |
7857 | edid = ERR_PTR(-EINVAL); | |
7858 | } | |
7859 | } else { | |
7860 | edid = ERR_PTR(-ENOENT); | |
7861 | } | |
7862 | intel_connector->edid = edid; | |
7863 | ||
0dc927eb VS |
7864 | fixed_mode = intel_panel_edid_fixed_mode(intel_connector); |
7865 | if (fixed_mode) | |
7866 | downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode); | |
ed92f0b2 PZ |
7867 | |
7868 | /* fallback to VBT if available for eDP */ | |
325710d3 VS |
7869 | if (!fixed_mode) |
7870 | fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); | |
060c8778 | 7871 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 7872 | |
920a14b2 | 7873 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
6517d273 VS |
7874 | /* |
7875 | * Figure out the current pipe for the initial backlight setup. | |
7876 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
7877 | * fails just assume pipe A. | |
7878 | */ | |
9f2bdb00 | 7879 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
7880 | |
7881 | if (pipe != PIPE_A && pipe != PIPE_B) | |
7882 | pipe = intel_dp->pps_pipe; | |
7883 | ||
7884 | if (pipe != PIPE_A && pipe != PIPE_B) | |
7885 | pipe = PIPE_A; | |
7886 | ||
bdc6114e WK |
7887 | drm_dbg_kms(&dev_priv->drm, |
7888 | "using pipe %c for initial backlight setup\n", | |
7889 | pipe_name(pipe)); | |
01527b31 CT |
7890 | } |
7891 | ||
d93fa1b4 | 7892 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 7893 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 7894 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 | 7895 | |
69654c63 | 7896 | if (fixed_mode) { |
69654c63 | 7897 | drm_connector_set_panel_orientation_with_quirk(connector, |
0dd5b133 | 7898 | dev_priv->vbt.orientation, |
69654c63 DB |
7899 | fixed_mode->hdisplay, fixed_mode->vdisplay); |
7900 | } | |
9531221d | 7901 | |
ed92f0b2 | 7902 | return true; |
b4d06ede ID |
7903 | |
7904 | out_vdd_off: | |
7905 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
7906 | /* | |
7907 | * vdd might still be enabled do to the delayed vdd off. | |
7908 | * Make sure vdd is actually turned off here. | |
7909 | */ | |
69d93820 CW |
7910 | with_pps_lock(intel_dp, wakeref) |
7911 | edp_panel_vdd_off_sync(intel_dp); | |
b4d06ede ID |
7912 | |
7913 | return false; | |
ed92f0b2 PZ |
7914 | } |
7915 | ||
9301397a MN |
7916 | static void intel_dp_modeset_retry_work_fn(struct work_struct *work) |
7917 | { | |
7918 | struct intel_connector *intel_connector; | |
7919 | struct drm_connector *connector; | |
7920 | ||
7921 | intel_connector = container_of(work, typeof(*intel_connector), | |
7922 | modeset_retry_work); | |
7923 | connector = &intel_connector->base; | |
7924 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, | |
7925 | connector->name); | |
7926 | ||
7927 | /* Grab the locks before changing connector property*/ | |
7928 | mutex_lock(&connector->dev->mode_config.mutex); | |
7929 | /* Set connector link status to BAD and send a Uevent to notify | |
7930 | * userspace to do a modeset. | |
7931 | */ | |
97e14fbe DV |
7932 | drm_connector_set_link_status_property(connector, |
7933 | DRM_MODE_LINK_STATUS_BAD); | |
9301397a MN |
7934 | mutex_unlock(&connector->dev->mode_config.mutex); |
7935 | /* Send Hotplug uevent so userspace can reprobe */ | |
7936 | drm_kms_helper_hotplug_event(connector->dev); | |
7937 | } | |
7938 | ||
16c25533 | 7939 | bool |
7801f3b7 | 7940 | intel_dp_init_connector(struct intel_digital_port *dig_port, |
f0fec3f2 | 7941 | struct intel_connector *intel_connector) |
a4fc5ed6 | 7942 | { |
f0fec3f2 | 7943 | struct drm_connector *connector = &intel_connector->base; |
7801f3b7 LDM |
7944 | struct intel_dp *intel_dp = &dig_port->dp; |
7945 | struct intel_encoder *intel_encoder = &dig_port->base; | |
f0fec3f2 | 7946 | struct drm_device *dev = intel_encoder->base.dev; |
fac5e23e | 7947 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 7948 | enum port port = intel_encoder->port; |
d8fe2ab6 | 7949 | enum phy phy = intel_port_to_phy(dev_priv, port); |
7a418e34 | 7950 | int type; |
a4fc5ed6 | 7951 | |
9301397a MN |
7952 | /* Initialize the work for modeset in case of link train failure */ |
7953 | INIT_WORK(&intel_connector->modeset_retry_work, | |
7954 | intel_dp_modeset_retry_work_fn); | |
7955 | ||
7801f3b7 | 7956 | if (drm_WARN(dev, dig_port->max_lanes < 1, |
eb020ca3 | 7957 | "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", |
7801f3b7 | 7958 | dig_port->max_lanes, intel_encoder->base.base.id, |
eb020ca3 | 7959 | intel_encoder->base.name)) |
ccb1a831 VS |
7960 | return false; |
7961 | ||
d3913019 MA |
7962 | intel_dp_set_source_rates(intel_dp); |
7963 | ||
d7e8ef02 | 7964 | intel_dp->reset_link_params = true; |
a4a5d2f8 | 7965 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 7966 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 7967 | |
0767935e | 7968 | /* Preserve the current hw state. */ |
b4e33881 | 7969 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); |
dd06f90e | 7970 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 7971 | |
4e309baf ID |
7972 | if (intel_dp_is_port_edp(dev_priv, port)) { |
7973 | /* | |
7974 | * Currently we don't support eDP on TypeC ports, although in | |
7975 | * theory it could work on TypeC legacy ports. | |
7976 | */ | |
eb020ca3 | 7977 | drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); |
b329530c | 7978 | type = DRM_MODE_CONNECTOR_eDP; |
4e309baf | 7979 | } else { |
3b32a35b | 7980 | type = DRM_MODE_CONNECTOR_DisplayPort; |
4e309baf | 7981 | } |
b329530c | 7982 | |
9f2bdb00 VS |
7983 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
7984 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
7985 | ||
d3913019 MA |
7986 | /* |
7987 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
7988 | * for DP the encoder type can be set by the caller to | |
7989 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
7990 | */ | |
7991 | if (type == DRM_MODE_CONNECTOR_eDP) | |
7992 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
7993 | ||
7994 | /* eDP only on port B and/or C on vlv/chv */ | |
7995 | if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || | |
7996 | IS_CHERRYVIEW(dev_priv)) && | |
7997 | intel_dp_is_edp(intel_dp) && | |
7998 | port != PORT_B && port != PORT_C)) | |
7999 | return false; | |
8000 | ||
bdc6114e WK |
8001 | drm_dbg_kms(&dev_priv->drm, |
8002 | "Adding %s connector on [ENCODER:%d:%s]\n", | |
8003 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
8004 | intel_encoder->base.base.id, intel_encoder->base.name); | |
e7281eab | 8005 | |
b329530c | 8006 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
8007 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
8008 | ||
b2ae318a | 8009 | if (!HAS_GMCH(dev_priv)) |
05021389 | 8010 | connector->interlace_allowed = true; |
a4fc5ed6 KP |
8011 | connector->doublescan_allowed = 0; |
8012 | ||
5fb908eb | 8013 | intel_connector->polled = DRM_CONNECTOR_POLL_HPD; |
5432fcaf | 8014 | |
b6339585 | 8015 | intel_dp_aux_init(intel_dp); |
7a418e34 | 8016 | |
df0e9248 | 8017 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 8018 | |
4f8036a2 | 8019 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
8020 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
8021 | else | |
8022 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
8023 | ||
0e32b39c | 8024 | /* init MST on ports that can support it */ |
7801f3b7 | 8025 | intel_dp_mst_encoder_init(dig_port, |
10d987fd | 8026 | intel_connector->base.base.id); |
0e32b39c | 8027 | |
36b5f425 | 8028 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 | 8029 | intel_dp_aux_fini(intel_dp); |
7801f3b7 | 8030 | intel_dp_mst_encoder_cleanup(dig_port); |
a121f4e5 | 8031 | goto fail; |
b2f246a8 | 8032 | } |
32f9d658 | 8033 | |
f684960e | 8034 | intel_dp_add_properties(intel_dp, connector); |
20f24d77 | 8035 | |
fdddd08c | 8036 | if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { |
d079b7e4 | 8037 | int ret = intel_dp_init_hdcp(dig_port, intel_connector); |
20f24d77 | 8038 | if (ret) |
bdc6114e WK |
8039 | drm_dbg_kms(&dev_priv->drm, |
8040 | "HDCP init failed, skipping.\n"); | |
20f24d77 | 8041 | } |
f684960e | 8042 | |
a4fc5ed6 KP |
8043 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
8044 | * 0xd. Failure to do so will result in spurious interrupts being | |
8045 | * generated on the port when a cable is not attached. | |
8046 | */ | |
1c0f1b3d | 8047 | if (IS_G45(dev_priv)) { |
b4e33881 JN |
8048 | u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); |
8049 | intel_de_write(dev_priv, PEG_BAND_GAP_DATA, | |
8050 | (temp & ~0xf) | 0xd); | |
a4fc5ed6 | 8051 | } |
16c25533 PZ |
8052 | |
8053 | return true; | |
a121f4e5 VS |
8054 | |
8055 | fail: | |
a121f4e5 VS |
8056 | drm_connector_cleanup(connector); |
8057 | ||
8058 | return false; | |
a4fc5ed6 | 8059 | } |
f0fec3f2 | 8060 | |
c39055b0 | 8061 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
8062 | i915_reg_t output_reg, |
8063 | enum port port) | |
f0fec3f2 | 8064 | { |
7801f3b7 | 8065 | struct intel_digital_port *dig_port; |
f0fec3f2 PZ |
8066 | struct intel_encoder *intel_encoder; |
8067 | struct drm_encoder *encoder; | |
8068 | struct intel_connector *intel_connector; | |
8069 | ||
7801f3b7 LDM |
8070 | dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); |
8071 | if (!dig_port) | |
457c52d8 | 8072 | return false; |
f0fec3f2 | 8073 | |
08d9bc92 | 8074 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
8075 | if (!intel_connector) |
8076 | goto err_connector_alloc; | |
f0fec3f2 | 8077 | |
7801f3b7 | 8078 | intel_encoder = &dig_port->base; |
f0fec3f2 PZ |
8079 | encoder = &intel_encoder->base; |
8080 | ||
36e5e704 SP |
8081 | mutex_init(&dig_port->hdcp_mutex); |
8082 | ||
c39055b0 ACO |
8083 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
8084 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
8085 | "DP %c", port_name(port))) | |
893da0c9 | 8086 | goto err_encoder_init; |
f0fec3f2 | 8087 | |
c85d200e | 8088 | intel_encoder->hotplug = intel_dp_hotplug; |
5bfe2ac0 | 8089 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 8090 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 8091 | intel_encoder->get_config = intel_dp_get_config; |
f9e76a6e | 8092 | intel_encoder->sync_state = intel_dp_sync_state; |
b671d6ef | 8093 | intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; |
63a23d24 | 8094 | intel_encoder->update_pipe = intel_panel_update_backlight; |
07f9cd0b | 8095 | intel_encoder->suspend = intel_dp_encoder_suspend; |
e219ef91 | 8096 | intel_encoder->shutdown = intel_dp_encoder_shutdown; |
920a14b2 | 8097 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 8098 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
8099 | intel_encoder->pre_enable = chv_pre_enable_dp; |
8100 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 8101 | intel_encoder->disable = vlv_disable_dp; |
580d3811 | 8102 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 8103 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 8104 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 8105 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
8106 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
8107 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 8108 | intel_encoder->disable = vlv_disable_dp; |
49277c31 | 8109 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 8110 | } else { |
ecff4f3b JN |
8111 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
8112 | intel_encoder->enable = g4x_enable_dp; | |
1a8ff607 | 8113 | intel_encoder->disable = g4x_disable_dp; |
51a9f6df | 8114 | intel_encoder->post_disable = g4x_post_disable_dp; |
ab1f90f9 | 8115 | } |
f0fec3f2 | 8116 | |
eee3f911 VS |
8117 | if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || |
8118 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) | |
7801f3b7 | 8119 | dig_port->dp.set_link_train = cpt_set_link_train; |
eee3f911 | 8120 | else |
7801f3b7 | 8121 | dig_port->dp.set_link_train = g4x_set_link_train; |
eee3f911 | 8122 | |
fb83f72c | 8123 | if (IS_CHERRYVIEW(dev_priv)) |
7801f3b7 | 8124 | dig_port->dp.set_signal_levels = chv_set_signal_levels; |
fb83f72c | 8125 | else if (IS_VALLEYVIEW(dev_priv)) |
7801f3b7 | 8126 | dig_port->dp.set_signal_levels = vlv_set_signal_levels; |
fb83f72c | 8127 | else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) |
7801f3b7 | 8128 | dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; |
fb83f72c | 8129 | else if (IS_GEN(dev_priv, 6) && port == PORT_A) |
7801f3b7 | 8130 | dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; |
fb83f72c | 8131 | else |
7801f3b7 | 8132 | dig_port->dp.set_signal_levels = g4x_set_signal_levels; |
fb83f72c | 8133 | |
53de0a20 VS |
8134 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || |
8135 | (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { | |
6694d2be | 8136 | dig_port->dp.preemph_max = intel_dp_preemph_max_3; |
7801f3b7 | 8137 | dig_port->dp.voltage_max = intel_dp_voltage_max_3; |
53de0a20 | 8138 | } else { |
6694d2be | 8139 | dig_port->dp.preemph_max = intel_dp_preemph_max_2; |
7801f3b7 | 8140 | dig_port->dp.voltage_max = intel_dp_voltage_max_2; |
53de0a20 VS |
8141 | } |
8142 | ||
7801f3b7 LDM |
8143 | dig_port->dp.output_reg = output_reg; |
8144 | dig_port->max_lanes = 4; | |
f0fec3f2 | 8145 | |
cca0502b | 8146 | intel_encoder->type = INTEL_OUTPUT_DP; |
79f255a0 | 8147 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
920a14b2 | 8148 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 | 8149 | if (port == PORT_D) |
981329ce | 8150 | intel_encoder->pipe_mask = BIT(PIPE_C); |
882ec384 | 8151 | else |
981329ce | 8152 | intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); |
882ec384 | 8153 | } else { |
34053ee1 | 8154 | intel_encoder->pipe_mask = ~0; |
882ec384 | 8155 | } |
bc079e8b | 8156 | intel_encoder->cloneable = 0; |
03cdc1d4 | 8157 | intel_encoder->port = port; |
03c7e4f1 | 8158 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
f0fec3f2 | 8159 | |
7801f3b7 | 8160 | dig_port->hpd_pulse = intel_dp_hpd_pulse; |
13cf5504 | 8161 | |
edc0e09c VS |
8162 | if (HAS_GMCH(dev_priv)) { |
8163 | if (IS_GM45(dev_priv)) | |
7801f3b7 | 8164 | dig_port->connected = gm45_digital_port_connected; |
edc0e09c | 8165 | else |
7801f3b7 | 8166 | dig_port->connected = g4x_digital_port_connected; |
edc0e09c | 8167 | } else { |
c7e8a3d6 | 8168 | if (port == PORT_A) |
7801f3b7 | 8169 | dig_port->connected = ilk_digital_port_connected; |
edc0e09c | 8170 | else |
7801f3b7 | 8171 | dig_port->connected = ibx_digital_port_connected; |
edc0e09c VS |
8172 | } |
8173 | ||
385e4de0 | 8174 | if (port != PORT_A) |
7801f3b7 | 8175 | intel_infoframe_init(dig_port); |
385e4de0 | 8176 | |
7801f3b7 LDM |
8177 | dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
8178 | if (!intel_dp_init_connector(dig_port, intel_connector)) | |
11aee0f6 SM |
8179 | goto err_init_connector; |
8180 | ||
457c52d8 | 8181 | return true; |
11aee0f6 SM |
8182 | |
8183 | err_init_connector: | |
8184 | drm_encoder_cleanup(encoder); | |
893da0c9 | 8185 | err_encoder_init: |
11aee0f6 SM |
8186 | kfree(intel_connector); |
8187 | err_connector_alloc: | |
7801f3b7 | 8188 | kfree(dig_port); |
457c52d8 | 8189 | return false; |
f0fec3f2 | 8190 | } |
0e32b39c | 8191 | |
1a4313d1 | 8192 | void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) |
0e32b39c | 8193 | { |
1a4313d1 VS |
8194 | struct intel_encoder *encoder; |
8195 | ||
8196 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
8197 | struct intel_dp *intel_dp; | |
0e32b39c | 8198 | |
1a4313d1 VS |
8199 | if (encoder->type != INTEL_OUTPUT_DDI) |
8200 | continue; | |
5aa56969 | 8201 | |
b7d02c3a | 8202 | intel_dp = enc_to_intel_dp(encoder); |
5aa56969 | 8203 | |
1a4313d1 | 8204 | if (!intel_dp->can_mst) |
0e32b39c DA |
8205 | continue; |
8206 | ||
1a4313d1 VS |
8207 | if (intel_dp->is_mst) |
8208 | drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); | |
0e32b39c DA |
8209 | } |
8210 | } | |
8211 | ||
1a4313d1 | 8212 | void intel_dp_mst_resume(struct drm_i915_private *dev_priv) |
0e32b39c | 8213 | { |
1a4313d1 | 8214 | struct intel_encoder *encoder; |
0e32b39c | 8215 | |
1a4313d1 VS |
8216 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
8217 | struct intel_dp *intel_dp; | |
5aa56969 | 8218 | int ret; |
0e32b39c | 8219 | |
1a4313d1 VS |
8220 | if (encoder->type != INTEL_OUTPUT_DDI) |
8221 | continue; | |
8222 | ||
b7d02c3a | 8223 | intel_dp = enc_to_intel_dp(encoder); |
1a4313d1 VS |
8224 | |
8225 | if (!intel_dp->can_mst) | |
5aa56969 | 8226 | continue; |
0e32b39c | 8227 | |
6f85f738 LP |
8228 | ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, |
8229 | true); | |
6be1cf96 LP |
8230 | if (ret) { |
8231 | intel_dp->is_mst = false; | |
8232 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
8233 | false); | |
8234 | } | |
0e32b39c DA |
8235 | } |
8236 | } |