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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
2d1a8a48 | 28 | #include <linux/export.h> |
331c201a | 29 | #include <linux/i2c.h> |
01527b31 | 30 | #include <linux/notifier.h> |
331c201a | 31 | #include <linux/slab.h> |
01fabda8 | 32 | #include <linux/string_helpers.h> |
c7c90b0b | 33 | #include <linux/timekeeping.h> |
331c201a | 34 | #include <linux/types.h> |
56c5098f | 35 | |
611032bf | 36 | #include <asm/byteorder.h> |
331c201a | 37 | |
da68386d | 38 | #include <drm/display/drm_dp_helper.h> |
fb687904 | 39 | #include <drm/display/drm_dp_tunnel.h> |
2a64b147 | 40 | #include <drm/display/drm_dsc_helper.h> |
4fc8cb47 | 41 | #include <drm/display/drm_hdmi_helper.h> |
c6f95f27 | 42 | #include <drm/drm_atomic_helper.h> |
760285e7 | 43 | #include <drm/drm_crtc.h> |
255490f9 | 44 | #include <drm/drm_edid.h> |
fcd70cd3 | 45 | #include <drm/drm_probe_helper.h> |
331c201a | 46 | |
917c2899 | 47 | #include "g4x_dp.h" |
a4fc5ed6 | 48 | #include "i915_drv.h" |
cfe5bdfb | 49 | #include "i915_irq.h" |
801543b2 | 50 | #include "i915_reg.h" |
12392a74 | 51 | #include "intel_atomic.h" |
331c201a | 52 | #include "intel_audio.h" |
6cc42fbe | 53 | #include "intel_backlight.h" |
d0864ee4 | 54 | #include "intel_combo_phy_regs.h" |
ec7f29ff | 55 | #include "intel_connector.h" |
fd2b94a5 | 56 | #include "intel_crtc.h" |
62618c7f | 57 | #include "intel_cx0_phy.h" |
fdc24cf3 | 58 | #include "intel_ddi.h" |
7785ae0b | 59 | #include "intel_de.h" |
bab87ef4 | 60 | #include "intel_display_driver.h" |
1d455f8d | 61 | #include "intel_display_types.h" |
27fec1f9 | 62 | #include "intel_dp.h" |
aa850fb1 | 63 | #include "intel_dp_aux.h" |
b23109c5 | 64 | #include "intel_dp_hdcp.h" |
e075094f | 65 | #include "intel_dp_link_training.h" |
46f2066e | 66 | #include "intel_dp_mst.h" |
259e2e0a | 67 | #include "intel_dp_tunnel.h" |
b1ad4c39 | 68 | #include "intel_dpio_phy.h" |
b23109c5 | 69 | #include "intel_dpll.h" |
2d04f815 | 70 | #include "intel_drrs.h" |
8834e365 | 71 | #include "intel_fifo_underrun.h" |
408bd917 | 72 | #include "intel_hdcp.h" |
0550691d | 73 | #include "intel_hdmi.h" |
dbeb38d9 | 74 | #include "intel_hotplug.h" |
da38ba98 | 75 | #include "intel_hotplug_irq.h" |
f3e18947 | 76 | #include "intel_lspcon.h" |
42406fdc | 77 | #include "intel_lvds.h" |
44c1220a | 78 | #include "intel_panel.h" |
a9708702 | 79 | #include "intel_pch_display.h" |
abad6805 | 80 | #include "intel_pps.h" |
55367a27 | 81 | #include "intel_psr.h" |
bc85328f | 82 | #include "intel_tc.h" |
b375d0ef | 83 | #include "intel_vdsc.h" |
3dafe8a8 | 84 | #include "intel_vrr.h" |
d4d17377 | 85 | #include "intel_crtc_state_dump.h" |
a4fc5ed6 | 86 | |
d9218c8f MN |
87 | /* DP DSC throughput values used for slice count calculations KPixels/s */ |
88 | #define DP_DSC_PEAK_PIXEL_RATE 2720000 | |
89 | #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 | |
90 | #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 | |
91 | ||
3e306daa ID |
92 | /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ |
93 | #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 | |
d9218c8f | 94 | |
559be30c TP |
95 | /* Compliance test status bits */ |
96 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
97 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
98 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
99 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
100 | ||
abad6805 | 101 | |
d9218c8f MN |
102 | /* Constants for DP DSC configurations */ |
103 | static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; | |
104 | ||
105 | /* With Single pipe configuration, HW is capable of supporting maximum | |
106 | * of 4 slices per line. | |
107 | */ | |
108 | static const u8 valid_dsc_slicecount[] = {1, 2, 4}; | |
109 | ||
cfcb0fc9 | 110 | /** |
1853a9da | 111 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
cfcb0fc9 JB |
112 | * @intel_dp: DP struct |
113 | * | |
114 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
115 | * will return true, and false otherwise. | |
6fd5a7c9 MA |
116 | * |
117 | * This function is not safe to use prior to encoder type being set. | |
cfcb0fc9 | 118 | */ |
1853a9da | 119 | bool intel_dp_is_edp(struct intel_dp *intel_dp) |
cfcb0fc9 | 120 | { |
7801f3b7 | 121 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
da63a9f2 | 122 | |
7801f3b7 | 123 | return dig_port->base.type == INTEL_OUTPUT_EDP; |
cfcb0fc9 JB |
124 | } |
125 | ||
f21a2198 | 126 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 127 | |
4e718a0e JN |
128 | /* Is link rate UHBR and thus 128b/132b? */ |
129 | bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) | |
130 | { | |
3c460872 | 131 | return drm_dp_is_uhbr_rate(crtc_state->port_clock); |
4e718a0e JN |
132 | } |
133 | ||
7e175377 ID |
134 | /** |
135 | * intel_dp_link_symbol_size - get the link symbol size for a given link rate | |
136 | * @rate: link rate in 10kbit/s units | |
137 | * | |
138 | * Returns the link symbol size in bits/symbol units depending on the link | |
139 | * rate -> channel coding. | |
140 | */ | |
141 | int intel_dp_link_symbol_size(int rate) | |
142 | { | |
143 | return drm_dp_is_uhbr_rate(rate) ? 32 : 10; | |
144 | } | |
145 | ||
146 | /** | |
147 | * intel_dp_link_symbol_clock - convert link rate to link symbol clock | |
148 | * @rate: link rate in 10kbit/s units | |
149 | * | |
150 | * Returns the link symbol clock frequency in kHz units depending on the | |
151 | * link rate and channel coding. | |
152 | */ | |
153 | int intel_dp_link_symbol_clock(int rate) | |
154 | { | |
155 | return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); | |
156 | } | |
157 | ||
259e2e0a ID |
158 | static int max_dprx_rate(struct intel_dp *intel_dp) |
159 | { | |
160 | if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) | |
161 | return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); | |
162 | ||
163 | return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); | |
164 | } | |
165 | ||
166 | static int max_dprx_lane_count(struct intel_dp *intel_dp) | |
167 | { | |
168 | if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) | |
169 | return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); | |
170 | ||
171 | return drm_dp_max_lane_count(intel_dp->dpcd); | |
172 | } | |
173 | ||
3f61ef97 ID |
174 | static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) |
175 | { | |
176 | intel_dp->sink_rates[0] = 162000; | |
177 | intel_dp->num_sink_rates = 1; | |
178 | } | |
179 | ||
68f357cb | 180 | /* update sink rates from dpcd */ |
caae4fb5 | 181 | static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) |
68f357cb | 182 | { |
229675d5 | 183 | static const int dp_rates[] = { |
c71b53cc | 184 | 162000, 270000, 540000, 810000 |
229675d5 | 185 | }; |
a8a08886 | 186 | int i, max_rate; |
b30edfd8 | 187 | int max_lttpr_rate; |
68f357cb | 188 | |
7c553f8b | 189 | if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { |
639e0db2 MK |
190 | /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ |
191 | static const int quirk_rates[] = { 162000, 270000, 324000 }; | |
192 | ||
193 | memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); | |
194 | intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); | |
195 | ||
196 | return; | |
197 | } | |
198 | ||
c474420b JN |
199 | /* |
200 | * Sink rates for 8b/10b. | |
201 | */ | |
259e2e0a | 202 | max_rate = max_dprx_rate(intel_dp); |
b30edfd8 ID |
203 | max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); |
204 | if (max_lttpr_rate) | |
205 | max_rate = min(max_rate, max_lttpr_rate); | |
68f357cb | 206 | |
229675d5 JN |
207 | for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { |
208 | if (dp_rates[i] > max_rate) | |
a8a08886 | 209 | break; |
229675d5 | 210 | intel_dp->sink_rates[i] = dp_rates[i]; |
a8a08886 | 211 | } |
68f357cb | 212 | |
9ab29e15 JN |
213 | /* |
214 | * Sink rates for 128b/132b. If set, sink should support all 8b/10b | |
215 | * rates and 10 Gbps. | |
216 | */ | |
217 | if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { | |
218 | u8 uhbr_rates = 0; | |
219 | ||
220 | BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); | |
221 | ||
222 | drm_dp_dpcd_readb(&intel_dp->aux, | |
223 | DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); | |
224 | ||
c474420b JN |
225 | if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { |
226 | /* We have a repeater */ | |
227 | if (intel_dp->lttpr_common_caps[0] >= 0x20 && | |
228 | intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - | |
229 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & | |
230 | DP_PHY_REPEATER_128B132B_SUPPORTED) { | |
231 | /* Repeater supports 128b/132b, valid UHBR rates */ | |
232 | uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - | |
233 | DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; | |
234 | } else { | |
235 | /* Does not support 128b/132b */ | |
236 | uhbr_rates = 0; | |
237 | } | |
238 | } | |
239 | ||
9ab29e15 JN |
240 | if (uhbr_rates & DP_UHBR10) |
241 | intel_dp->sink_rates[i++] = 1000000; | |
242 | if (uhbr_rates & DP_UHBR13_5) | |
243 | intel_dp->sink_rates[i++] = 1350000; | |
244 | if (uhbr_rates & DP_UHBR20) | |
245 | intel_dp->sink_rates[i++] = 2000000; | |
246 | } | |
247 | ||
a8a08886 | 248 | intel_dp->num_sink_rates = i; |
68f357cb JN |
249 | } |
250 | ||
caae4fb5 ID |
251 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) |
252 | { | |
253 | struct intel_connector *connector = intel_dp->attached_connector; | |
254 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
255 | struct intel_encoder *encoder = &intel_dig_port->base; | |
256 | ||
257 | intel_dp_set_dpcd_sink_rates(intel_dp); | |
258 | ||
259 | if (intel_dp->num_sink_rates) | |
260 | return; | |
261 | ||
262 | drm_err(&dp_to_i915(intel_dp)->drm, | |
263 | "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", | |
264 | connector->base.base.id, connector->base.name, | |
265 | encoder->base.base.id, encoder->base.name); | |
266 | ||
267 | intel_dp_set_default_sink_rates(intel_dp); | |
268 | } | |
269 | ||
bedcadda ID |
270 | static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) |
271 | { | |
272 | intel_dp->max_sink_lane_count = 1; | |
273 | } | |
274 | ||
275 | static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) | |
276 | { | |
277 | struct intel_connector *connector = intel_dp->attached_connector; | |
278 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
279 | struct intel_encoder *encoder = &intel_dig_port->base; | |
280 | ||
259e2e0a | 281 | intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); |
bedcadda ID |
282 | |
283 | switch (intel_dp->max_sink_lane_count) { | |
284 | case 1: | |
285 | case 2: | |
286 | case 4: | |
287 | return; | |
288 | } | |
289 | ||
290 | drm_err(&dp_to_i915(intel_dp)->drm, | |
291 | "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", | |
292 | connector->base.base.id, connector->base.name, | |
293 | encoder->base.base.id, encoder->base.name, | |
294 | intel_dp->max_sink_lane_count); | |
295 | ||
296 | intel_dp_set_default_max_sink_lane_count(intel_dp); | |
297 | } | |
298 | ||
10ebb736 JN |
299 | /* Get length of rates array potentially limited by max_rate. */ |
300 | static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) | |
301 | { | |
302 | int i; | |
303 | ||
304 | /* Limit results by potentially reduced max rate */ | |
305 | for (i = 0; i < len; i++) { | |
306 | if (rates[len - i - 1] <= max_rate) | |
307 | return len - i; | |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | /* Get length of common rates array potentially limited by max_rate. */ | |
314 | static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, | |
315 | int max_rate) | |
316 | { | |
317 | return intel_dp_rate_limit_len(intel_dp->common_rates, | |
318 | intel_dp->num_common_rates, max_rate); | |
319 | } | |
320 | ||
ce679dea ID |
321 | static int intel_dp_common_rate(struct intel_dp *intel_dp, int index) |
322 | { | |
323 | if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, | |
324 | index < 0 || index >= intel_dp->num_common_rates)) | |
325 | return 162000; | |
326 | ||
327 | return intel_dp->common_rates[index]; | |
328 | } | |
329 | ||
540b0b7f | 330 | /* Theoretical max between source and sink */ |
4ba732a6 | 331 | int intel_dp_max_common_rate(struct intel_dp *intel_dp) |
a4fc5ed6 | 332 | { |
ce679dea | 333 | return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); |
a4fc5ed6 KP |
334 | } |
335 | ||
4182a311 VS |
336 | static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) |
337 | { | |
02107ef1 | 338 | int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); |
4182a311 VS |
339 | int max_lanes = dig_port->max_lanes; |
340 | ||
341 | if (vbt_max_lanes) | |
342 | max_lanes = min(max_lanes, vbt_max_lanes); | |
343 | ||
344 | return max_lanes; | |
345 | } | |
346 | ||
540b0b7f | 347 | /* Theoretical max between source and sink */ |
4ba732a6 | 348 | int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) |
eeb6324d | 349 | { |
7801f3b7 | 350 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4182a311 | 351 | int source_max = intel_dp_max_source_lane_count(dig_port); |
bedcadda | 352 | int sink_max = intel_dp->max_sink_lane_count; |
182ccc43 | 353 | int lane_max = intel_tc_port_max_lane_count(dig_port); |
b30edfd8 ID |
354 | int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); |
355 | ||
356 | if (lttpr_max) | |
357 | sink_max = min(sink_max, lttpr_max); | |
eeb6324d | 358 | |
182ccc43 | 359 | return min3(source_max, sink_max, lane_max); |
eeb6324d PZ |
360 | } |
361 | ||
3d65a735 | 362 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
540b0b7f | 363 | { |
bedcadda ID |
364 | switch (intel_dp->max_link_lane_count) { |
365 | case 1: | |
366 | case 2: | |
367 | case 4: | |
368 | return intel_dp->max_link_lane_count; | |
369 | default: | |
370 | MISSING_CASE(intel_dp->max_link_lane_count); | |
371 | return 1; | |
372 | } | |
540b0b7f JN |
373 | } |
374 | ||
48efd014 JN |
375 | /* |
376 | * The required data bandwidth for a mode with given pixel clock and bpp. This | |
377 | * is the required net bandwidth independent of the data bandwidth efficiency. | |
9069b775 ID |
378 | * |
379 | * TODO: check if callers of this functions should use | |
380 | * intel_dp_effective_data_rate() instead. | |
48efd014 | 381 | */ |
22a2c8e0 | 382 | int |
c898261c | 383 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 384 | { |
fd81c44e DP |
385 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
386 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
387 | } |
388 | ||
9069b775 ID |
389 | /** |
390 | * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead | |
391 | * @pixel_clock: pixel clock in kHz | |
392 | * @bpp_x16: bits per pixel .4 fixed point format | |
393 | * @bw_overhead: BW allocation overhead in 1ppm units | |
394 | * | |
395 | * Return the effective pixel data rate in kB/sec units taking into account | |
396 | * the provided SSC, FEC, DSC BW allocation overhead. | |
397 | */ | |
398 | int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, | |
399 | int bw_overhead) | |
400 | { | |
401 | return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), | |
402 | 1000000 * 16 * 8); | |
403 | } | |
404 | ||
a4ea61b7 ID |
405 | /** |
406 | * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params | |
407 | * @intel_dp: Intel DP object | |
408 | * @max_dprx_rate: Maximum data rate of the DPRX | |
409 | * @max_dprx_lanes: Maximum lane count of the DPRX | |
410 | * | |
259e2e0a ID |
411 | * Calculate the maximum data rate for the provided link parameters taking into |
412 | * account any BW limitations by a DP tunnel attached to @intel_dp. | |
a4ea61b7 ID |
413 | * |
414 | * Returns the maximum data rate in kBps units. | |
415 | */ | |
416 | int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, | |
417 | int max_dprx_rate, int max_dprx_lanes) | |
418 | { | |
259e2e0a ID |
419 | int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); |
420 | ||
421 | if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) | |
422 | max_rate = min(max_rate, | |
423 | drm_dp_tunnel_available_bw(intel_dp->tunnel)); | |
424 | ||
425 | return max_rate; | |
a4ea61b7 ID |
426 | } |
427 | ||
63dc014e ML |
428 | bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp) |
429 | { | |
430 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
431 | struct intel_encoder *encoder = &intel_dig_port->base; | |
432 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
433 | ||
005e9537 | 434 | return DISPLAY_VER(dev_priv) >= 12 || |
93e7e61e | 435 | (DISPLAY_VER(dev_priv) == 11 && |
63dc014e ML |
436 | encoder->port != PORT_A); |
437 | } | |
438 | ||
e752d1f9 JN |
439 | static int dg2_max_source_rate(struct intel_dp *intel_dp) |
440 | { | |
441 | return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; | |
442 | } | |
443 | ||
46b527d1 MN |
444 | static int icl_max_source_rate(struct intel_dp *intel_dp) |
445 | { | |
7fcf7558 | 446 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
46b527d1 | 447 | |
7fcf7558 | 448 | if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) |
46b527d1 MN |
449 | return 540000; |
450 | ||
451 | return 810000; | |
452 | } | |
453 | ||
cf725620 JRS |
454 | static int ehl_max_source_rate(struct intel_dp *intel_dp) |
455 | { | |
483e3d87 | 456 | if (intel_dp_is_edp(intel_dp)) |
bc41f059 JN |
457 | return 540000; |
458 | ||
459 | return 810000; | |
460 | } | |
461 | ||
7cb3eb33 MK |
462 | static int mtl_max_source_rate(struct intel_dp *intel_dp) |
463 | { | |
7fcf7558 | 464 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
62618c7f | 465 | |
7fcf7558 | 466 | if (intel_encoder_is_c10phy(encoder)) |
a3431650 | 467 | return 810000; |
62618c7f MK |
468 | |
469 | return 2000000; | |
7cb3eb33 MK |
470 | } |
471 | ||
24b8b74e VS |
472 | static int vbt_max_link_rate(struct intel_dp *intel_dp) |
473 | { | |
474 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
475 | int max_rate; | |
476 | ||
02107ef1 | 477 | max_rate = intel_bios_dp_max_link_rate(encoder->devdata); |
24b8b74e VS |
478 | |
479 | if (intel_dp_is_edp(intel_dp)) { | |
480 | struct intel_connector *connector = intel_dp->attached_connector; | |
481 | int edp_max_rate = connector->panel.vbt.edp.max_link_rate; | |
482 | ||
483 | if (max_rate && edp_max_rate) | |
484 | max_rate = min(max_rate, edp_max_rate); | |
485 | else if (edp_max_rate) | |
486 | max_rate = edp_max_rate; | |
487 | } | |
488 | ||
489 | return max_rate; | |
490 | } | |
491 | ||
55cfc580 JN |
492 | static void |
493 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 | 494 | { |
229675d5 | 495 | /* The values must be in increasing order */ |
7cb3eb33 MK |
496 | static const int mtl_rates[] = { |
497 | 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, | |
ddf8a8bb | 498 | 810000, 1000000, 2000000, |
7cb3eb33 | 499 | }; |
94a79070 | 500 | static const int icl_rates[] = { |
e752d1f9 JN |
501 | 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, |
502 | 1000000, 1350000, | |
229675d5 JN |
503 | }; |
504 | static const int bxt_rates[] = { | |
505 | 162000, 216000, 243000, 270000, 324000, 432000, 540000 | |
506 | }; | |
507 | static const int skl_rates[] = { | |
508 | 162000, 216000, 270000, 324000, 432000, 540000 | |
509 | }; | |
510 | static const int hsw_rates[] = { | |
511 | 162000, 270000, 540000 | |
512 | }; | |
513 | static const int g4x_rates[] = { | |
514 | 162000, 270000 | |
515 | }; | |
40dba341 NM |
516 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
517 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
55cfc580 | 518 | const int *source_rates; |
f83acdab | 519 | int size, max_rate = 0, vbt_max_rate; |
40dba341 | 520 | |
55cfc580 | 521 | /* This should only be done once */ |
eb020ca3 PB |
522 | drm_WARN_ON(&dev_priv->drm, |
523 | intel_dp->source_rates || intel_dp->num_source_rates); | |
55cfc580 | 524 | |
7cb3eb33 MK |
525 | if (DISPLAY_VER(dev_priv) >= 14) { |
526 | source_rates = mtl_rates; | |
527 | size = ARRAY_SIZE(mtl_rates); | |
528 | max_rate = mtl_max_source_rate(intel_dp); | |
529 | } else if (DISPLAY_VER(dev_priv) >= 11) { | |
94a79070 LDM |
530 | source_rates = icl_rates; |
531 | size = ARRAY_SIZE(icl_rates); | |
e752d1f9 JN |
532 | if (IS_DG2(dev_priv)) |
533 | max_rate = dg2_max_source_rate(intel_dp); | |
555ae26d AM |
534 | else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) || |
535 | IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) | |
483e3d87 | 536 | max_rate = 810000; |
0c65dc06 | 537 | else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) |
cf725620 | 538 | max_rate = ehl_max_source_rate(intel_dp); |
46b527d1 MN |
539 | else |
540 | max_rate = icl_max_source_rate(intel_dp); | |
70bfb307 | 541 | } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { |
ba1c06a5 MN |
542 | source_rates = bxt_rates; |
543 | size = ARRAY_SIZE(bxt_rates); | |
93e7e61e | 544 | } else if (DISPLAY_VER(dev_priv) == 9) { |
55cfc580 | 545 | source_rates = skl_rates; |
40dba341 | 546 | size = ARRAY_SIZE(skl_rates); |
927a8e38 | 547 | } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) || |
fc603ca7 | 548 | IS_BROADWELL(dev_priv)) { |
229675d5 JN |
549 | source_rates = hsw_rates; |
550 | size = ARRAY_SIZE(hsw_rates); | |
fc603ca7 | 551 | } else { |
229675d5 JN |
552 | source_rates = g4x_rates; |
553 | size = ARRAY_SIZE(g4x_rates); | |
40dba341 NM |
554 | } |
555 | ||
24b8b74e | 556 | vbt_max_rate = vbt_max_link_rate(intel_dp); |
99b91bda JN |
557 | if (max_rate && vbt_max_rate) |
558 | max_rate = min(max_rate, vbt_max_rate); | |
559 | else if (vbt_max_rate) | |
560 | max_rate = vbt_max_rate; | |
561 | ||
4ba285d4 JN |
562 | if (max_rate) |
563 | size = intel_dp_rate_limit_len(source_rates, size, max_rate); | |
564 | ||
55cfc580 JN |
565 | intel_dp->source_rates = source_rates; |
566 | intel_dp->num_source_rates = size; | |
40dba341 NM |
567 | } |
568 | ||
569 | static int intersect_rates(const int *source_rates, int source_len, | |
570 | const int *sink_rates, int sink_len, | |
571 | int *common_rates) | |
572 | { | |
573 | int i = 0, j = 0, k = 0; | |
574 | ||
575 | while (i < source_len && j < sink_len) { | |
576 | if (source_rates[i] == sink_rates[j]) { | |
577 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
578 | return k; | |
579 | common_rates[k] = source_rates[i]; | |
580 | ++k; | |
581 | ++i; | |
582 | ++j; | |
583 | } else if (source_rates[i] < sink_rates[j]) { | |
584 | ++i; | |
585 | } else { | |
586 | ++j; | |
587 | } | |
588 | } | |
589 | return k; | |
590 | } | |
591 | ||
8001b754 JN |
592 | /* return index of rate in rates array, or -1 if not found */ |
593 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
594 | { | |
595 | int i; | |
596 | ||
597 | for (i = 0; i < len; i++) | |
598 | if (rate == rates[i]) | |
599 | return i; | |
600 | ||
601 | return -1; | |
602 | } | |
603 | ||
975ee5fc | 604 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 605 | { |
4f360482 PB |
606 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
607 | ||
608 | drm_WARN_ON(&i915->drm, | |
609 | !intel_dp->num_source_rates || !intel_dp->num_sink_rates); | |
40dba341 | 610 | |
975ee5fc JN |
611 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
612 | intel_dp->num_source_rates, | |
613 | intel_dp->sink_rates, | |
614 | intel_dp->num_sink_rates, | |
615 | intel_dp->common_rates); | |
616 | ||
617 | /* Paranoia, there should always be something in common. */ | |
4f360482 | 618 | if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { |
229675d5 | 619 | intel_dp->common_rates[0] = 162000; |
975ee5fc JN |
620 | intel_dp->num_common_rates = 1; |
621 | } | |
622 | } | |
623 | ||
1a92c70e | 624 | static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
830de422 | 625 | u8 lane_count) |
14c562c0 MN |
626 | { |
627 | /* | |
628 | * FIXME: we need to synchronize the current link parameters with | |
629 | * hardware readout. Currently fast link training doesn't work on | |
630 | * boot-up. | |
631 | */ | |
1a92c70e MN |
632 | if (link_rate == 0 || |
633 | link_rate > intel_dp->max_link_rate) | |
14c562c0 MN |
634 | return false; |
635 | ||
1a92c70e MN |
636 | if (lane_count == 0 || |
637 | lane_count > intel_dp_max_lane_count(intel_dp)) | |
14c562c0 MN |
638 | return false; |
639 | ||
640 | return true; | |
641 | } | |
642 | ||
1e712535 MN |
643 | static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, |
644 | int link_rate, | |
830de422 | 645 | u8 lane_count) |
1e712535 | 646 | { |
43af6743 | 647 | /* FIXME figure out what we actually want here */ |
1e712535 | 648 | const struct drm_display_mode *fixed_mode = |
43af6743 | 649 | intel_panel_preferred_fixed_mode(intel_dp->attached_connector); |
1e712535 MN |
650 | int mode_rate, max_rate; |
651 | ||
652 | mode_rate = intel_dp_link_required(fixed_mode->clock, 18); | |
a4ea61b7 | 653 | max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); |
1e712535 MN |
654 | if (mode_rate > max_rate) |
655 | return false; | |
656 | ||
657 | return true; | |
658 | } | |
659 | ||
fdb14d33 | 660 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
830de422 | 661 | int link_rate, u8 lane_count) |
fdb14d33 | 662 | { |
af67009c | 663 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b1810a74 | 664 | int index; |
fdb14d33 | 665 | |
80a8cecf ID |
666 | /* |
667 | * TODO: Enable fallback on MST links once MST link compute can handle | |
668 | * the fallback params. | |
669 | */ | |
670 | if (intel_dp->is_mst) { | |
671 | drm_err(&i915->drm, "Link Training Unsuccessful\n"); | |
672 | return -1; | |
673 | } | |
674 | ||
2bbd6dba VS |
675 | if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { |
676 | drm_dbg_kms(&i915->drm, | |
677 | "Retrying Link training for eDP with max parameters\n"); | |
678 | intel_dp->use_max_params = true; | |
679 | return 0; | |
680 | } | |
681 | ||
b1810a74 JN |
682 | index = intel_dp_rate_index(intel_dp->common_rates, |
683 | intel_dp->num_common_rates, | |
684 | link_rate); | |
685 | if (index > 0) { | |
1e712535 MN |
686 | if (intel_dp_is_edp(intel_dp) && |
687 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
ce679dea | 688 | intel_dp_common_rate(intel_dp, index - 1), |
1e712535 | 689 | lane_count)) { |
af67009c JN |
690 | drm_dbg_kms(&i915->drm, |
691 | "Retrying Link training for eDP with same parameters\n"); | |
1e712535 MN |
692 | return 0; |
693 | } | |
ce679dea | 694 | intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1); |
e6c0c64a | 695 | intel_dp->max_link_lane_count = lane_count; |
fdb14d33 | 696 | } else if (lane_count > 1) { |
1e712535 MN |
697 | if (intel_dp_is_edp(intel_dp) && |
698 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, | |
699 | intel_dp_max_common_rate(intel_dp), | |
700 | lane_count >> 1)) { | |
af67009c JN |
701 | drm_dbg_kms(&i915->drm, |
702 | "Retrying Link training for eDP with same parameters\n"); | |
1e712535 MN |
703 | return 0; |
704 | } | |
540b0b7f | 705 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
e6c0c64a | 706 | intel_dp->max_link_lane_count = lane_count >> 1; |
fdb14d33 | 707 | } else { |
af67009c | 708 | drm_err(&i915->drm, "Link Training Unsuccessful\n"); |
fdb14d33 MN |
709 | return -1; |
710 | } | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
ed06efb8 ML |
715 | u32 intel_dp_mode_to_fec_clock(u32 mode_clock) |
716 | { | |
3e306daa ID |
717 | return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), |
718 | 1000000U); | |
ed06efb8 ML |
719 | } |
720 | ||
7ff2090c ID |
721 | int intel_dp_bw_fec_overhead(bool fec_enabled) |
722 | { | |
723 | /* | |
724 | * TODO: Calculate the actual overhead for a given mode. | |
725 | * The hard-coded 1/0.972261=2.853% overhead factor | |
726 | * corresponds (for instance) to the 8b/10b DP FEC 2.4% + | |
727 | * 0.453% DSC overhead. This is enough for a 3840 width mode, | |
728 | * which has a DSC overhead of up to ~0.2%, but may not be | |
729 | * enough for a 1024 width mode where this is ~0.8% (on a 4 | |
730 | * lane DP link, with 2 DSC slices and 8 bpp color depth). | |
731 | */ | |
732 | return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; | |
733 | } | |
734 | ||
45d3c5cd MR |
735 | static int |
736 | small_joiner_ram_size_bits(struct drm_i915_private *i915) | |
737 | { | |
f7a8f9af VK |
738 | if (DISPLAY_VER(i915) >= 13) |
739 | return 17280 * 8; | |
740 | else if (DISPLAY_VER(i915) >= 11) | |
45d3c5cd MR |
741 | return 7680 * 8; |
742 | else | |
743 | return 6144 * 8; | |
744 | } | |
745 | ||
d797f67d SL |
746 | u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp) |
747 | { | |
748 | u32 bits_per_pixel = bpp; | |
749 | int i; | |
750 | ||
751 | /* Error out if the max bpp is less than smallest allowed valid bpp */ | |
752 | if (bits_per_pixel < valid_dsc_bpp[0]) { | |
753 | drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", | |
754 | bits_per_pixel, valid_dsc_bpp[0]); | |
755 | return 0; | |
756 | } | |
757 | ||
758 | /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ | |
759 | if (DISPLAY_VER(i915) >= 13) { | |
760 | bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); | |
ce086a32 SL |
761 | |
762 | /* | |
763 | * According to BSpec, 27 is the max DSC output bpp, | |
a1222433 SL |
764 | * 8 is the min DSC output bpp. |
765 | * While we can still clamp higher bpp values to 27, saving bandwidth, | |
766 | * if it is required to oompress up to bpp < 8, means we can't do | |
767 | * that and probably means we can't fit the required mode, even with | |
768 | * DSC enabled. | |
ce086a32 | 769 | */ |
a1222433 SL |
770 | if (bits_per_pixel < 8) { |
771 | drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n", | |
772 | bits_per_pixel); | |
773 | return 0; | |
774 | } | |
775 | bits_per_pixel = min_t(u32, bits_per_pixel, 27); | |
d797f67d SL |
776 | } else { |
777 | /* Find the nearest match in the array of known BPPs from VESA */ | |
778 | for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { | |
779 | if (bits_per_pixel < valid_dsc_bpp[i + 1]) | |
780 | break; | |
781 | } | |
782 | drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n", | |
783 | bits_per_pixel, valid_dsc_bpp[i]); | |
784 | ||
785 | bits_per_pixel = valid_dsc_bpp[i]; | |
786 | } | |
787 | ||
788 | return bits_per_pixel; | |
789 | } | |
790 | ||
a4d30841 AN |
791 | static |
792 | u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, | |
793 | u32 mode_clock, u32 mode_hdisplay, | |
794 | bool bigjoiner) | |
795 | { | |
796 | u32 max_bpp_small_joiner_ram; | |
797 | ||
798 | /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ | |
799 | max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; | |
800 | ||
801 | if (bigjoiner) { | |
802 | int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; | |
803 | /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ | |
804 | int ppc = 2; | |
805 | u32 max_bpp_bigjoiner = | |
806 | i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / | |
807 | intel_dp_mode_to_fec_clock(mode_clock); | |
808 | ||
809 | max_bpp_small_joiner_ram *= 2; | |
810 | ||
811 | return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); | |
812 | } | |
813 | ||
814 | return max_bpp_small_joiner_ram; | |
815 | } | |
816 | ||
8d528476 AN |
817 | u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, |
818 | u32 link_clock, u32 lane_count, | |
819 | u32 mode_clock, u32 mode_hdisplay, | |
820 | bool bigjoiner, | |
821 | enum intel_output_format output_format, | |
822 | u32 pipe_bpp, | |
823 | u32 timeslots) | |
ed06efb8 | 824 | { |
a4d30841 | 825 | u32 bits_per_pixel, joiner_max_bpp; |
ed06efb8 ML |
826 | |
827 | /* | |
828 | * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* | |
a6fd6f94 SL |
829 | * (LinkSymbolClock)* 8 * (TimeSlots / 64) |
830 | * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) | |
831 | * for MST -> TimeSlots has to be calculated, based on mode requirements | |
68070b76 AN |
832 | * |
833 | * Due to FEC overhead, the available bw is reduced to 97.2261%. | |
834 | * To support the given mode: | |
835 | * Bandwidth required should be <= Available link Bandwidth * FEC Overhead | |
836 | * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead | |
837 | * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock | |
838 | * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / | |
839 | * (ModeClock / FEC Overhead) | |
840 | * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / | |
841 | * (ModeClock / FEC Overhead * 8) | |
ed06efb8 | 842 | */ |
68070b76 AN |
843 | bits_per_pixel = ((link_clock * lane_count) * timeslots) / |
844 | (intel_dp_mode_to_fec_clock(mode_clock) * 8); | |
52f14682 | 845 | |
a1476c2a AN |
846 | /* Bandwidth required for 420 is half, that of 444 format */ |
847 | if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
848 | bits_per_pixel *= 2; | |
849 | ||
3a4b4809 AN |
850 | /* |
851 | * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum | |
852 | * supported PPS value can be 63.9375 and with the further | |
853 | * mention that for 420, 422 formats, bpp should be programmed double | |
854 | * the target bpp restricting our target bpp to be 31.9375 at max. | |
855 | */ | |
856 | if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
857 | bits_per_pixel = min_t(u32, bits_per_pixel, 31); | |
858 | ||
52f14682 SL |
859 | drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " |
860 | "total bw %u pixel clock %u\n", | |
861 | bits_per_pixel, timeslots, | |
862 | (link_clock * lane_count * 8), | |
863 | intel_dp_mode_to_fec_clock(mode_clock)); | |
ed06efb8 | 864 | |
a4d30841 AN |
865 | joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock, |
866 | mode_hdisplay, bigjoiner); | |
867 | bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); | |
63dc014e | 868 | |
d797f67d | 869 | bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); |
ed06efb8 | 870 | |
51dda148 | 871 | return bits_per_pixel; |
ed06efb8 ML |
872 | } |
873 | ||
7bca1b80 | 874 | u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, |
d51f25eb SL |
875 | int mode_clock, int mode_hdisplay, |
876 | bool bigjoiner) | |
ed06efb8 | 877 | { |
7bca1b80 | 878 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
ed06efb8 ML |
879 | u8 min_slice_count, i; |
880 | int max_slice_width; | |
881 | ||
882 | if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) | |
883 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
884 | DP_DSC_MAX_ENC_THROUGHPUT_0); | |
885 | else | |
886 | min_slice_count = DIV_ROUND_UP(mode_clock, | |
887 | DP_DSC_MAX_ENC_THROUGHPUT_1); | |
888 | ||
ce086a32 SL |
889 | /* |
890 | * Due to some DSC engine BW limitations, we need to enable second | |
891 | * slice and VDSC engine, whenever we approach close enough to max CDCLK | |
892 | */ | |
893 | if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) | |
894 | min_slice_count = max_t(u8, min_slice_count, 2); | |
895 | ||
7bca1b80 | 896 | max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); |
ed06efb8 | 897 | if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { |
af67009c JN |
898 | drm_dbg_kms(&i915->drm, |
899 | "Unsupported slice width %d by DP DSC Sink device\n", | |
900 | max_slice_width); | |
ed06efb8 ML |
901 | return 0; |
902 | } | |
903 | /* Also take into account max slice width */ | |
f6cbe49b | 904 | min_slice_count = max_t(u8, min_slice_count, |
ed06efb8 ML |
905 | DIV_ROUND_UP(mode_hdisplay, |
906 | max_slice_width)); | |
907 | ||
908 | /* Find the closest match to the valid slice count values */ | |
909 | for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { | |
63dc014e ML |
910 | u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner; |
911 | ||
912 | if (test_slice_count > | |
7bca1b80 | 913 | drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) |
ed06efb8 | 914 | break; |
63dc014e ML |
915 | |
916 | /* big joiner needs small joiner to be enabled */ | |
917 | if (bigjoiner && test_slice_count < 4) | |
918 | continue; | |
919 | ||
920 | if (min_slice_count <= test_slice_count) | |
921 | return test_slice_count; | |
ed06efb8 ML |
922 | } |
923 | ||
af67009c JN |
924 | drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", |
925 | min_slice_count); | |
ed06efb8 ML |
926 | return 0; |
927 | } | |
928 | ||
68910c2a AN |
929 | static bool source_can_output(struct intel_dp *intel_dp, |
930 | enum intel_output_format format) | |
931 | { | |
932 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
933 | ||
934 | switch (format) { | |
935 | case INTEL_OUTPUT_FORMAT_RGB: | |
936 | return true; | |
937 | ||
938 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
939 | /* | |
940 | * No YCbCr output support on gmch platforms. | |
941 | * Also, ILK doesn't seem capable of DP YCbCr output. | |
942 | * The displayed image is severly corrupted. SNB+ is fine. | |
943 | */ | |
944 | return !HAS_GMCH(i915) && !IS_IRONLAKE(i915); | |
945 | ||
946 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
947 | /* Platform < Gen 11 cannot output YCbCr420 format */ | |
948 | return DISPLAY_VER(i915) >= 11; | |
949 | ||
950 | default: | |
951 | MISSING_CASE(format); | |
952 | return false; | |
953 | } | |
954 | } | |
955 | ||
956 | static bool | |
957 | dfp_can_convert_from_rgb(struct intel_dp *intel_dp, | |
958 | enum intel_output_format sink_format) | |
959 | { | |
960 | if (!drm_dp_is_branch(intel_dp->dpcd)) | |
961 | return false; | |
962 | ||
963 | if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) | |
964 | return intel_dp->dfp.rgb_to_ycbcr; | |
965 | ||
966 | if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
967 | return intel_dp->dfp.rgb_to_ycbcr && | |
968 | intel_dp->dfp.ycbcr_444_to_420; | |
969 | ||
970 | return false; | |
971 | } | |
972 | ||
973 | static bool | |
974 | dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, | |
975 | enum intel_output_format sink_format) | |
976 | { | |
977 | if (!drm_dp_is_branch(intel_dp->dpcd)) | |
978 | return false; | |
979 | ||
980 | if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
981 | return intel_dp->dfp.ycbcr_444_to_420; | |
982 | ||
983 | return false; | |
984 | } | |
985 | ||
7adfec8c AN |
986 | static bool |
987 | dfp_can_convert(struct intel_dp *intel_dp, | |
988 | enum intel_output_format output_format, | |
989 | enum intel_output_format sink_format) | |
990 | { | |
991 | switch (output_format) { | |
992 | case INTEL_OUTPUT_FORMAT_RGB: | |
993 | return dfp_can_convert_from_rgb(intel_dp, sink_format); | |
994 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
995 | return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); | |
996 | default: | |
997 | MISSING_CASE(output_format); | |
998 | return false; | |
999 | } | |
1000 | ||
1001 | return false; | |
1002 | } | |
1003 | ||
773bd825 | 1004 | static enum intel_output_format |
2cad4279 | 1005 | intel_dp_output_format(struct intel_connector *connector, |
a04d27cd | 1006 | enum intel_output_format sink_format) |
773bd825 | 1007 | { |
2cad4279 | 1008 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
68910c2a | 1009 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
7adfec8c AN |
1010 | enum intel_output_format force_dsc_output_format = |
1011 | intel_dp->force_dsc_output_format; | |
68910c2a | 1012 | enum intel_output_format output_format; |
7adfec8c AN |
1013 | if (force_dsc_output_format) { |
1014 | if (source_can_output(intel_dp, force_dsc_output_format) && | |
1015 | (!drm_dp_is_branch(intel_dp->dpcd) || | |
1016 | sink_format != force_dsc_output_format || | |
1017 | dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) | |
1018 | return force_dsc_output_format; | |
1019 | ||
1020 | drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n"); | |
1021 | } | |
d4d17377 | 1022 | |
68910c2a AN |
1023 | if (sink_format == INTEL_OUTPUT_FORMAT_RGB || |
1024 | dfp_can_convert_from_rgb(intel_dp, sink_format)) | |
1025 | output_format = INTEL_OUTPUT_FORMAT_RGB; | |
773bd825 | 1026 | |
68910c2a AN |
1027 | else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || |
1028 | dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) | |
1029 | output_format = INTEL_OUTPUT_FORMAT_YCBCR444; | |
522508b6 | 1030 | |
773bd825 | 1031 | else |
68910c2a AN |
1032 | output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
1033 | ||
1034 | drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format)); | |
1035 | ||
1036 | return output_format; | |
773bd825 VS |
1037 | } |
1038 | ||
0bf8dedc VS |
1039 | int intel_dp_min_bpp(enum intel_output_format output_format) |
1040 | { | |
1041 | if (output_format == INTEL_OUTPUT_FORMAT_RGB) | |
1042 | return 6 * 3; | |
1043 | else | |
1044 | return 8 * 3; | |
1045 | } | |
1046 | ||
fd279d21 | 1047 | int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) |
0bf8dedc VS |
1048 | { |
1049 | /* | |
1050 | * bpp value was assumed to RGB format. And YCbCr 4:2:0 output | |
1051 | * format of the number of bytes per pixel will be half the number | |
1052 | * of bytes of RGB pixel. | |
1053 | */ | |
1054 | if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
1055 | bpp /= 2; | |
1056 | ||
1057 | return bpp; | |
1058 | } | |
1059 | ||
5814227d AN |
1060 | static enum intel_output_format |
1061 | intel_dp_sink_format(struct intel_connector *connector, | |
1062 | const struct drm_display_mode *mode) | |
1063 | { | |
1064 | const struct drm_display_info *info = &connector->base.display_info; | |
1065 | ||
1066 | if (drm_mode_is_420_only(info, mode)) | |
1067 | return INTEL_OUTPUT_FORMAT_YCBCR420; | |
1068 | ||
1069 | return INTEL_OUTPUT_FORMAT_RGB; | |
1070 | } | |
1071 | ||
0bf8dedc | 1072 | static int |
2cad4279 | 1073 | intel_dp_mode_min_output_bpp(struct intel_connector *connector, |
0bf8dedc VS |
1074 | const struct drm_display_mode *mode) |
1075 | { | |
a04d27cd AN |
1076 | enum intel_output_format output_format, sink_format; |
1077 | ||
5814227d | 1078 | sink_format = intel_dp_sink_format(connector, mode); |
a04d27cd AN |
1079 | |
1080 | output_format = intel_dp_output_format(connector, sink_format); | |
0bf8dedc VS |
1081 | |
1082 | return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); | |
1083 | } | |
1084 | ||
98c93394 VS |
1085 | static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, |
1086 | int hdisplay) | |
1087 | { | |
1088 | /* | |
1089 | * Older platforms don't like hdisplay==4096 with DP. | |
1090 | * | |
1091 | * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline | |
1092 | * and frame counter increment), but we don't get vblank interrupts, | |
1093 | * and the pipe underruns immediately. The link also doesn't seem | |
1094 | * to get trained properly. | |
1095 | * | |
1096 | * On CHV the vblank interrupts don't seem to disappear but | |
1097 | * otherwise the symptoms are similar. | |
1098 | * | |
1099 | * TODO: confirm the behaviour on HSW+ | |
1100 | */ | |
1101 | return hdisplay == 4096 && !HAS_DDI(dev_priv); | |
1102 | } | |
1103 | ||
069b78f5 VS |
1104 | static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) |
1105 | { | |
1106 | struct intel_connector *connector = intel_dp->attached_connector; | |
1107 | const struct drm_display_info *info = &connector->base.display_info; | |
1108 | int max_tmds_clock = intel_dp->dfp.max_tmds_clock; | |
1109 | ||
1110 | /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ | |
1111 | if (max_tmds_clock && info->max_tmds_clock) | |
1112 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | |
1113 | ||
1114 | return max_tmds_clock; | |
1115 | } | |
1116 | ||
a707a55f VS |
1117 | static enum drm_mode_status |
1118 | intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, | |
52315679 AN |
1119 | int clock, int bpc, |
1120 | enum intel_output_format sink_format, | |
56185b90 | 1121 | bool respect_downstream_limits) |
a707a55f | 1122 | { |
069b78f5 | 1123 | int tmds_clock, min_tmds_clock, max_tmds_clock; |
a707a55f | 1124 | |
56185b90 VS |
1125 | if (!respect_downstream_limits) |
1126 | return MODE_OK; | |
1127 | ||
52315679 | 1128 | tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); |
a707a55f | 1129 | |
069b78f5 VS |
1130 | min_tmds_clock = intel_dp->dfp.min_tmds_clock; |
1131 | max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); | |
1132 | ||
1133 | if (min_tmds_clock && tmds_clock < min_tmds_clock) | |
a707a55f VS |
1134 | return MODE_CLOCK_LOW; |
1135 | ||
069b78f5 | 1136 | if (max_tmds_clock && tmds_clock > max_tmds_clock) |
a707a55f VS |
1137 | return MODE_CLOCK_HIGH; |
1138 | ||
1139 | return MODE_OK; | |
1140 | } | |
1141 | ||
fe7cf496 VS |
1142 | static enum drm_mode_status |
1143 | intel_dp_mode_valid_downstream(struct intel_connector *connector, | |
3977cd1c | 1144 | const struct drm_display_mode *mode, |
fe7cf496 VS |
1145 | int target_clock) |
1146 | { | |
1147 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
3977cd1c | 1148 | const struct drm_display_info *info = &connector->base.display_info; |
632f8535 | 1149 | enum drm_mode_status status; |
52315679 | 1150 | enum intel_output_format sink_format; |
fe7cf496 | 1151 | |
2f78347e AN |
1152 | /* If PCON supports FRL MODE, check FRL bandwidth constraints */ |
1153 | if (intel_dp->dfp.pcon_max_frl_bw) { | |
1154 | int target_bw; | |
1155 | int max_frl_bw; | |
2cad4279 | 1156 | int bpp = intel_dp_mode_min_output_bpp(connector, mode); |
2f78347e AN |
1157 | |
1158 | target_bw = bpp * target_clock; | |
1159 | ||
1160 | max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; | |
1161 | ||
1162 | /* converting bw from Gbps to Kbps*/ | |
1163 | max_frl_bw = max_frl_bw * 1000000; | |
1164 | ||
1165 | if (target_bw > max_frl_bw) | |
1166 | return MODE_CLOCK_HIGH; | |
1167 | ||
1168 | return MODE_OK; | |
1169 | } | |
1170 | ||
fe7cf496 VS |
1171 | if (intel_dp->dfp.max_dotclock && |
1172 | target_clock > intel_dp->dfp.max_dotclock) | |
1173 | return MODE_CLOCK_HIGH; | |
1174 | ||
5814227d | 1175 | sink_format = intel_dp_sink_format(connector, mode); |
52315679 | 1176 | |
3977cd1c | 1177 | /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ |
632f8535 | 1178 | status = intel_dp_tmds_clock_valid(intel_dp, target_clock, |
52315679 | 1179 | 8, sink_format, true); |
632f8535 VS |
1180 | |
1181 | if (status != MODE_OK) { | |
52315679 | 1182 | if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
632f8535 VS |
1183 | !connector->base.ycbcr_420_allowed || |
1184 | !drm_mode_is_420_also(info, mode)) | |
1185 | return status; | |
52315679 | 1186 | sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
632f8535 | 1187 | status = intel_dp_tmds_clock_valid(intel_dp, target_clock, |
52315679 | 1188 | 8, sink_format, true); |
632f8535 VS |
1189 | if (status != MODE_OK) |
1190 | return status; | |
1191 | } | |
1192 | ||
1193 | return MODE_OK; | |
fe7cf496 VS |
1194 | } |
1195 | ||
d51f25eb SL |
1196 | bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, |
1197 | int hdisplay, int clock) | |
e0ccf1d6 VS |
1198 | { |
1199 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
00c3959d | 1200 | struct intel_connector *connector = intel_dp->attached_connector; |
e0ccf1d6 VS |
1201 | |
1202 | if (!intel_dp_can_bigjoiner(intel_dp)) | |
1203 | return false; | |
1204 | ||
00c3959d SL |
1205 | return clock > i915->max_dotclk_freq || hdisplay > 5120 || |
1206 | connector->force_bigjoiner_enable; | |
e0ccf1d6 VS |
1207 | } |
1208 | ||
c19de8eb | 1209 | static enum drm_mode_status |
2cad4279 | 1210 | intel_dp_mode_valid(struct drm_connector *_connector, |
a4fc5ed6 KP |
1211 | struct drm_display_mode *mode) |
1212 | { | |
2cad4279 VS |
1213 | struct intel_connector *connector = to_intel_connector(_connector); |
1214 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1215 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
09270678 | 1216 | const struct drm_display_mode *fixed_mode; |
36008365 DV |
1217 | int target_clock = mode->clock; |
1218 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
fe7cf496 | 1219 | int max_dotclk = dev_priv->max_dotclk_freq; |
8d528476 | 1220 | u16 dsc_max_compressed_bpp = 0; |
6cfd04b0 | 1221 | u8 dsc_slice_count = 0; |
fe7cf496 | 1222 | enum drm_mode_status status; |
63dc014e | 1223 | bool dsc = false, bigjoiner = false; |
70ec0645 | 1224 | |
e0ef2daa VS |
1225 | status = intel_cpu_transcoder_mode_valid(dev_priv, mode); |
1226 | if (status != MODE_OK) | |
1227 | return status; | |
1228 | ||
6ec29d2b MN |
1229 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1230 | return MODE_H_ILLEGAL; | |
1231 | ||
2cad4279 | 1232 | fixed_mode = intel_panel_fixed_mode(connector, mode); |
1853a9da | 1233 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
2cad4279 | 1234 | status = intel_panel_mode_valid(connector, mode); |
08243606 VS |
1235 | if (status != MODE_OK) |
1236 | return status; | |
03afc4a2 DV |
1237 | |
1238 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
1239 | } |
1240 | ||
6ec29d2b MN |
1241 | if (mode->clock < 10000) |
1242 | return MODE_CLOCK_LOW; | |
1243 | ||
e0ccf1d6 | 1244 | if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { |
63dc014e ML |
1245 | bigjoiner = true; |
1246 | max_dotclk *= 2; | |
1247 | } | |
1248 | if (target_clock > max_dotclk) | |
1249 | return MODE_CLOCK_HIGH; | |
1250 | ||
1dc56576 AN |
1251 | if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) |
1252 | return MODE_H_ILLEGAL; | |
1253 | ||
50fec21a | 1254 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 1255 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 | 1256 | |
a4ea61b7 ID |
1257 | max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); |
1258 | ||
0bf8dedc VS |
1259 | mode_rate = intel_dp_link_required(target_clock, |
1260 | intel_dp_mode_min_output_bpp(connector, mode)); | |
36008365 | 1261 | |
8f5c2f6e | 1262 | if (HAS_DSC(dev_priv) && |
031c19b5 | 1263 | drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) { |
a1476c2a AN |
1264 | enum intel_output_format sink_format, output_format; |
1265 | int pipe_bpp; | |
1266 | ||
1267 | sink_format = intel_dp_sink_format(connector, mode); | |
1268 | output_format = intel_dp_output_format(connector, sink_format); | |
831d5aa9 VK |
1269 | /* |
1270 | * TBD pass the connector BPC, | |
1271 | * for now U8_MAX so that max BPC on that platform would be picked | |
1272 | */ | |
f52bbfe2 | 1273 | pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); |
831d5aa9 | 1274 | |
1dc56576 AN |
1275 | /* |
1276 | * Output bpp is stored in 6.4 format so right shift by 4 to get the | |
1277 | * integer value since we support only integer values of bpp. | |
1278 | */ | |
6cfd04b0 | 1279 | if (intel_dp_is_edp(intel_dp)) { |
8d528476 | 1280 | dsc_max_compressed_bpp = |
031c19b5 | 1281 | drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; |
6cfd04b0 | 1282 | dsc_slice_count = |
031c19b5 | 1283 | drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, |
6cfd04b0 | 1284 | true); |
031c19b5 | 1285 | } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { |
8d528476 AN |
1286 | dsc_max_compressed_bpp = |
1287 | intel_dp_dsc_get_max_compressed_bpp(dev_priv, | |
1288 | max_link_clock, | |
1289 | max_lanes, | |
1290 | target_clock, | |
1291 | mode->hdisplay, | |
1292 | bigjoiner, | |
1293 | output_format, | |
51dda148 | 1294 | pipe_bpp, 64); |
6cfd04b0 | 1295 | dsc_slice_count = |
7bca1b80 | 1296 | intel_dp_dsc_get_slice_count(connector, |
6cfd04b0 | 1297 | target_clock, |
63dc014e ML |
1298 | mode->hdisplay, |
1299 | bigjoiner); | |
6cfd04b0 | 1300 | } |
63dc014e | 1301 | |
8d528476 | 1302 | dsc = dsc_max_compressed_bpp && dsc_slice_count; |
6cfd04b0 MN |
1303 | } |
1304 | ||
ca844ea7 AM |
1305 | /* |
1306 | * Big joiner configuration needs DSC for TGL which is not true for | |
1307 | * XE_LPD where uncompressed joiner is supported. | |
1308 | */ | |
1309 | if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) | |
c4867936 | 1310 | return MODE_CLOCK_HIGH; |
a4fc5ed6 | 1311 | |
63dc014e | 1312 | if (mode_rate > max_rate && !dsc) |
c4867936 | 1313 | return MODE_CLOCK_HIGH; |
0af78a2b | 1314 | |
2cad4279 | 1315 | status = intel_dp_mode_valid_downstream(connector, mode, target_clock); |
fe7cf496 VS |
1316 | if (status != MODE_OK) |
1317 | return status; | |
1318 | ||
63dc014e | 1319 | return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner); |
a4fc5ed6 KP |
1320 | } |
1321 | ||
1e39da5a | 1322 | bool intel_dp_source_supports_tps3(struct drm_i915_private *i915) |
ed63baaf | 1323 | { |
1e39da5a | 1324 | return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915); |
ed63baaf TS |
1325 | } |
1326 | ||
1e39da5a | 1327 | bool intel_dp_source_supports_tps4(struct drm_i915_private *i915) |
2edd5327 | 1328 | { |
1e39da5a | 1329 | return DISPLAY_VER(i915) >= 10; |
2edd5327 MN |
1330 | } |
1331 | ||
0336400e VS |
1332 | static void snprintf_int_array(char *str, size_t len, |
1333 | const int *array, int nelem) | |
1334 | { | |
1335 | int i; | |
1336 | ||
1337 | str[0] = '\0'; | |
1338 | ||
1339 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1340 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1341 | if (r >= len) |
1342 | return; | |
1343 | str += r; | |
1344 | len -= r; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1349 | { | |
af67009c | 1350 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
0336400e VS |
1351 | char str[128]; /* FIXME: too big for stack? */ |
1352 | ||
bdbf43d7 | 1353 | if (!drm_debug_enabled(DRM_UT_KMS)) |
0336400e VS |
1354 | return; |
1355 | ||
55cfc580 JN |
1356 | snprintf_int_array(str, sizeof(str), |
1357 | intel_dp->source_rates, intel_dp->num_source_rates); | |
af67009c | 1358 | drm_dbg_kms(&i915->drm, "source rates: %s\n", str); |
0336400e | 1359 | |
68f357cb JN |
1360 | snprintf_int_array(str, sizeof(str), |
1361 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
af67009c | 1362 | drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); |
0336400e | 1363 | |
975ee5fc JN |
1364 | snprintf_int_array(str, sizeof(str), |
1365 | intel_dp->common_rates, intel_dp->num_common_rates); | |
af67009c | 1366 | drm_dbg_kms(&i915->drm, "common rates: %s\n", str); |
0336400e VS |
1367 | } |
1368 | ||
50fec21a VS |
1369 | int |
1370 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1371 | { | |
50fec21a VS |
1372 | int len; |
1373 | ||
e6c0c64a | 1374 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
50fec21a | 1375 | |
ce679dea | 1376 | return intel_dp_common_rate(intel_dp, len - 1); |
50fec21a VS |
1377 | } |
1378 | ||
ed4e9c1d VS |
1379 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1380 | { | |
4f360482 | 1381 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
8001b754 JN |
1382 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1383 | intel_dp->num_sink_rates, rate); | |
b5c72b20 | 1384 | |
4f360482 | 1385 | if (drm_WARN_ON(&i915->drm, i < 0)) |
b5c72b20 JN |
1386 | i = 0; |
1387 | ||
1388 | return i; | |
ed4e9c1d VS |
1389 | } |
1390 | ||
94223d04 | 1391 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
830de422 | 1392 | u8 *link_bw, u8 *rate_select) |
04a60f9f | 1393 | { |
68f357cb JN |
1394 | /* eDP 1.4 rate select method. */ |
1395 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1396 | *link_bw = 0; |
1397 | *rate_select = | |
1398 | intel_dp_rate_select(intel_dp, port_clock); | |
1399 | } else { | |
1400 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1401 | *rate_select = 0; | |
1402 | } | |
1403 | } | |
1404 | ||
7ffa2f27 JN |
1405 | bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) |
1406 | { | |
1407 | struct intel_connector *connector = intel_dp->attached_connector; | |
1408 | ||
1409 | return connector->base.display_info.is_hdmi; | |
1410 | } | |
1411 | ||
240999cf | 1412 | static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, |
a4a15777 MN |
1413 | const struct intel_crtc_state *pipe_config) |
1414 | { | |
126f94e8 | 1415 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
a4a15777 MN |
1416 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
1417 | ||
005e9537 | 1418 | if (DISPLAY_VER(dev_priv) >= 12) |
9770f220 MTP |
1419 | return true; |
1420 | ||
126f94e8 | 1421 | if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A) |
9770f220 MTP |
1422 | return true; |
1423 | ||
1424 | return false; | |
240999cf AS |
1425 | } |
1426 | ||
d91680ef ID |
1427 | bool intel_dp_supports_fec(struct intel_dp *intel_dp, |
1428 | const struct intel_connector *connector, | |
1429 | const struct intel_crtc_state *pipe_config) | |
240999cf AS |
1430 | { |
1431 | return intel_dp_source_supports_fec(intel_dp, pipe_config) && | |
987c945a | 1432 | drm_dp_sink_supports_fec(connector->dp.fec_capability); |
240999cf AS |
1433 | } |
1434 | ||
0d8665e0 | 1435 | static bool intel_dp_supports_dsc(const struct intel_connector *connector, |
deaaff49 | 1436 | const struct intel_crtc_state *crtc_state) |
a4a15777 | 1437 | { |
8a029c11 | 1438 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) |
240999cf AS |
1439 | return false; |
1440 | ||
8a029c11 | 1441 | return intel_dsc_source_support(crtc_state) && |
b2608c6b | 1442 | connector->dp.dsc_decompression_aux && |
0d8665e0 | 1443 | drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd); |
a4a15777 MN |
1444 | } |
1445 | ||
7299b530 VS |
1446 | static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, |
1447 | const struct intel_crtc_state *crtc_state, | |
56185b90 | 1448 | int bpc, bool respect_downstream_limits) |
bc7ca6a6 | 1449 | { |
a707a55f | 1450 | int clock = crtc_state->hw.adjusted_mode.crtc_clock; |
bc7ca6a6 | 1451 | |
7299b530 VS |
1452 | /* |
1453 | * Current bpc could already be below 8bpc due to | |
1454 | * FDI bandwidth constraints or other limits. | |
1455 | * HDMI minimum is 8bpc however. | |
1456 | */ | |
1457 | bpc = max(bpc, 8); | |
1458 | ||
56185b90 VS |
1459 | /* |
1460 | * We will never exceed downstream TMDS clock limits while | |
1461 | * attempting deep color. If the user insists on forcing an | |
1462 | * out of spec mode they will have to be satisfied with 8bpc. | |
1463 | */ | |
1464 | if (!respect_downstream_limits) | |
1465 | bpc = 8; | |
1466 | ||
7299b530 VS |
1467 | for (; bpc >= 8; bpc -= 2) { |
1468 | if (intel_hdmi_bpc_possible(crtc_state, bpc, | |
7ffa2f27 | 1469 | intel_dp_has_hdmi_sink(intel_dp)) && |
52315679 | 1470 | intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, |
56185b90 | 1471 | respect_downstream_limits) == MODE_OK) |
7299b530 VS |
1472 | return bpc; |
1473 | } | |
1474 | ||
1475 | return -EINVAL; | |
bc7ca6a6 VS |
1476 | } |
1477 | ||
1478 | static int intel_dp_max_bpp(struct intel_dp *intel_dp, | |
56185b90 VS |
1479 | const struct intel_crtc_state *crtc_state, |
1480 | bool respect_downstream_limits) | |
f9bb705e | 1481 | { |
de25eb7f | 1482 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
ef32659a | 1483 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
bc7ca6a6 | 1484 | int bpp, bpc; |
f9bb705e | 1485 | |
bc7ca6a6 | 1486 | bpc = crtc_state->pipe_bpp / 3; |
f9bb705e | 1487 | |
530df3c0 | 1488 | if (intel_dp->dfp.max_bpc) |
bc7ca6a6 VS |
1489 | bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); |
1490 | ||
1491 | if (intel_dp->dfp.min_tmds_clock) { | |
7299b530 VS |
1492 | int max_hdmi_bpc; |
1493 | ||
56185b90 VS |
1494 | max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, |
1495 | respect_downstream_limits); | |
7299b530 VS |
1496 | if (max_hdmi_bpc < 0) |
1497 | return 0; | |
1498 | ||
1499 | bpc = min(bpc, max_hdmi_bpc); | |
bc7ca6a6 | 1500 | } |
f9bb705e | 1501 | |
bc7ca6a6 | 1502 | bpp = bpc * 3; |
ef32659a JN |
1503 | if (intel_dp_is_edp(intel_dp)) { |
1504 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1505 | if (intel_connector->base.display_info.bpc == 0 && | |
3cf05076 VS |
1506 | intel_connector->panel.vbt.edp.bpp && |
1507 | intel_connector->panel.vbt.edp.bpp < bpp) { | |
bdc6114e WK |
1508 | drm_dbg_kms(&dev_priv->drm, |
1509 | "clamping bpp for eDP panel to BIOS-provided %i\n", | |
3cf05076 VS |
1510 | intel_connector->panel.vbt.edp.bpp); |
1511 | bpp = intel_connector->panel.vbt.edp.bpp; | |
ef32659a JN |
1512 | } |
1513 | } | |
1514 | ||
f9bb705e MK |
1515 | return bpp; |
1516 | } | |
1517 | ||
a4971453 | 1518 | /* Adjust link config limits based on compliance test requests. */ |
f1477219 | 1519 | void |
a4971453 JN |
1520 | intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, |
1521 | struct intel_crtc_state *pipe_config, | |
1522 | struct link_config_limits *limits) | |
1523 | { | |
af67009c JN |
1524 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
1525 | ||
a4971453 JN |
1526 | /* For DP Compliance we override the computed bpp for the pipe */ |
1527 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1528 | int bpp = 3 * intel_dp->compliance.test_data.bpc; | |
1529 | ||
703c5994 | 1530 | limits->pipe.min_bpp = limits->pipe.max_bpp = bpp; |
a4971453 JN |
1531 | pipe_config->dither_force_disable = bpp == 6 * 3; |
1532 | ||
af67009c | 1533 | drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); |
a4971453 JN |
1534 | } |
1535 | ||
1536 | /* Use values requested by Compliance Test Request */ | |
1537 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
1538 | int index; | |
1539 | ||
1540 | /* Validate the compliance test data since max values | |
1541 | * might have changed due to link train fallback. | |
1542 | */ | |
1543 | if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, | |
1544 | intel_dp->compliance.test_lane_count)) { | |
1545 | index = intel_dp_rate_index(intel_dp->common_rates, | |
1546 | intel_dp->num_common_rates, | |
1547 | intel_dp->compliance.test_link_rate); | |
1548 | if (index >= 0) | |
f5b21c2e JN |
1549 | limits->min_rate = limits->max_rate = |
1550 | intel_dp->compliance.test_link_rate; | |
a4971453 JN |
1551 | limits->min_lane_count = limits->max_lane_count = |
1552 | intel_dp->compliance.test_lane_count; | |
1553 | } | |
1554 | } | |
1555 | } | |
1556 | ||
e6f29923 VS |
1557 | static bool has_seamless_m_n(struct intel_connector *connector) |
1558 | { | |
1559 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
1560 | ||
1561 | /* | |
1562 | * Seamless M/N reprogramming only implemented | |
1563 | * for BDW+ double buffered M/N registers so far. | |
1564 | */ | |
1565 | return HAS_DOUBLE_BUFFERED_M_N(i915) && | |
1566 | intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; | |
1567 | } | |
1568 | ||
1569 | static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, | |
1570 | const struct drm_connector_state *conn_state) | |
1571 | { | |
1572 | struct intel_connector *connector = to_intel_connector(conn_state->connector); | |
1573 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; | |
1574 | ||
1575 | /* FIXME a bit of a mess wrt clock vs. crtc_clock */ | |
1576 | if (has_seamless_m_n(connector)) | |
1577 | return intel_panel_highest_mode(connector, adjusted_mode)->clock; | |
1578 | else | |
1579 | return adjusted_mode->crtc_clock; | |
1580 | } | |
1581 | ||
3acd115d | 1582 | /* Optimize link config in order: max bpp, min clock, min lanes */ |
204474a6 | 1583 | static int |
3acd115d JN |
1584 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, |
1585 | struct intel_crtc_state *pipe_config, | |
e6f29923 | 1586 | const struct drm_connector_state *conn_state, |
3acd115d JN |
1587 | const struct link_config_limits *limits) |
1588 | { | |
e6f29923 | 1589 | int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); |
f5b21c2e | 1590 | int mode_rate, link_rate, link_avail; |
3acd115d | 1591 | |
703c5994 ID |
1592 | for (bpp = to_bpp_int(limits->link.max_bpp_x16); |
1593 | bpp >= to_bpp_int(limits->link.min_bpp_x16); | |
1594 | bpp -= 2 * 3) { | |
8d528476 | 1595 | int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); |
ddb3d12a | 1596 | |
8d528476 | 1597 | mode_rate = intel_dp_link_required(clock, link_bpp); |
3acd115d | 1598 | |
f5b21c2e | 1599 | for (i = 0; i < intel_dp->num_common_rates; i++) { |
ce679dea | 1600 | link_rate = intel_dp_common_rate(intel_dp, i); |
f5b21c2e JN |
1601 | if (link_rate < limits->min_rate || |
1602 | link_rate > limits->max_rate) | |
1603 | continue; | |
1604 | ||
3acd115d JN |
1605 | for (lane_count = limits->min_lane_count; |
1606 | lane_count <= limits->max_lane_count; | |
1607 | lane_count <<= 1) { | |
a4ea61b7 ID |
1608 | link_avail = intel_dp_max_link_data_rate(intel_dp, |
1609 | link_rate, | |
1610 | lane_count); | |
1611 | ||
3acd115d JN |
1612 | |
1613 | if (mode_rate <= link_avail) { | |
1614 | pipe_config->lane_count = lane_count; | |
1615 | pipe_config->pipe_bpp = bpp; | |
f5b21c2e | 1616 | pipe_config->port_clock = link_rate; |
3acd115d | 1617 | |
204474a6 | 1618 | return 0; |
3acd115d JN |
1619 | } |
1620 | } | |
1621 | } | |
1622 | } | |
1623 | ||
204474a6 | 1624 | return -EINVAL; |
3acd115d JN |
1625 | } |
1626 | ||
8a969033 AN |
1627 | static |
1628 | u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) | |
1629 | { | |
1630 | /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ | |
1631 | if (DISPLAY_VER(i915) >= 12) | |
1632 | return 12; | |
1633 | if (DISPLAY_VER(i915) == 11) | |
1634 | return 10; | |
1635 | ||
1636 | return 0; | |
1637 | } | |
1638 | ||
f52bbfe2 ID |
1639 | int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, |
1640 | u8 max_req_bpc) | |
a4a15777 | 1641 | { |
f52bbfe2 | 1642 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
a4a15777 | 1643 | int i, num_bpc; |
eebc1525 | 1644 | u8 dsc_bpc[3] = {}; |
6ee9dea5 VK |
1645 | u8 dsc_max_bpc; |
1646 | ||
8a969033 AN |
1647 | dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); |
1648 | ||
1649 | if (!dsc_max_bpc) | |
1650 | return dsc_max_bpc; | |
1651 | ||
1652 | dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); | |
a4a15777 | 1653 | |
f52bbfe2 | 1654 | num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, |
a4a15777 MN |
1655 | dsc_bpc); |
1656 | for (i = 0; i < num_bpc; i++) { | |
1657 | if (dsc_max_bpc >= dsc_bpc[i]) | |
1658 | return dsc_bpc[i] * 3; | |
1659 | } | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
6a60a8fa | 1664 | static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915) |
20052dee | 1665 | { |
20052dee VK |
1666 | return DISPLAY_VER(i915) >= 14 ? 2 : 1; |
1667 | } | |
1668 | ||
11a33d6b | 1669 | static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) |
20052dee | 1670 | { |
11a33d6b | 1671 | return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> |
20052dee VK |
1672 | DP_DSC_MINOR_SHIFT; |
1673 | } | |
7a7b5be9 | 1674 | |
f1dc979b SK |
1675 | static int intel_dp_get_slice_height(int vactive) |
1676 | { | |
1677 | int slice_height; | |
1678 | ||
1679 | /* | |
1680 | * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 | |
1681 | * lines is an optimal slice height, but any size can be used as long as | |
1682 | * vertical active integer multiple and maximum vertical slice count | |
1683 | * requirements are met. | |
1684 | */ | |
1685 | for (slice_height = 108; slice_height <= vactive; slice_height += 2) | |
1686 | if (vactive % slice_height == 0) | |
1687 | return slice_height; | |
1688 | ||
1689 | /* | |
1690 | * Highly unlikely we reach here as most of the resolutions will end up | |
1691 | * finding appropriate slice_height in above loop but returning | |
1692 | * slice_height as 2 here as it should work with all resolutions. | |
1693 | */ | |
1694 | return 2; | |
1695 | } | |
1696 | ||
2c4907c2 | 1697 | static int intel_dp_dsc_compute_params(const struct intel_connector *connector, |
7a7b5be9 JN |
1698 | struct intel_crtc_state *crtc_state) |
1699 | { | |
2c4907c2 | 1700 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
7a7b5be9 JN |
1701 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; |
1702 | u8 line_buf_depth; | |
1703 | int ret; | |
1704 | ||
420798a0 JN |
1705 | /* |
1706 | * RC_MODEL_SIZE is currently a constant across all configurations. | |
1707 | * | |
1708 | * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and | |
1709 | * DP_DSC_RC_BUF_SIZE for this. | |
1710 | */ | |
1711 | vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; | |
e72df53d | 1712 | vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; |
420798a0 | 1713 | |
f1dc979b | 1714 | vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); |
c42c38ec | 1715 | |
3126977d | 1716 | ret = intel_dsc_compute_params(crtc_state); |
5a6d866f VK |
1717 | if (ret) |
1718 | return ret; | |
1719 | ||
7a7b5be9 | 1720 | vdsc_cfg->dsc_version_major = |
2c4907c2 | 1721 | (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & |
7a7b5be9 JN |
1722 | DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; |
1723 | vdsc_cfg->dsc_version_minor = | |
6a60a8fa | 1724 | min(intel_dp_source_dsc_version_minor(i915), |
2c4907c2 | 1725 | intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); |
9aeabe19 SK |
1726 | if (vdsc_cfg->convert_rgb) |
1727 | vdsc_cfg->convert_rgb = | |
2c4907c2 | 1728 | connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & |
9aeabe19 | 1729 | DP_DSC_RGB; |
7a7b5be9 | 1730 | |
2c4907c2 | 1731 | line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd); |
7a7b5be9 | 1732 | if (!line_buf_depth) { |
af67009c JN |
1733 | drm_dbg_kms(&i915->drm, |
1734 | "DSC Sink Line Buffer Depth invalid\n"); | |
7a7b5be9 JN |
1735 | return -EINVAL; |
1736 | } | |
1737 | ||
1738 | if (vdsc_cfg->dsc_version_minor == 2) | |
1739 | vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? | |
1740 | DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; | |
1741 | else | |
1742 | vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? | |
1743 | DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; | |
1744 | ||
1745 | vdsc_cfg->block_pred_enable = | |
2c4907c2 | 1746 | connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & |
7a7b5be9 JN |
1747 | DP_DSC_BLK_PREDICTION_IS_SUPPORTED; |
1748 | ||
1749 | return drm_dsc_compute_rc_parameters(vdsc_cfg); | |
1750 | } | |
1751 | ||
926b726c | 1752 | static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, |
5011f291 AN |
1753 | enum intel_output_format output_format) |
1754 | { | |
926b726c | 1755 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5011f291 AN |
1756 | u8 sink_dsc_format; |
1757 | ||
1758 | switch (output_format) { | |
1759 | case INTEL_OUTPUT_FORMAT_RGB: | |
1760 | sink_dsc_format = DP_DSC_RGB; | |
1761 | break; | |
1762 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
1763 | sink_dsc_format = DP_DSC_YCbCr444; | |
1764 | break; | |
1765 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
6a60a8fa | 1766 | if (min(intel_dp_source_dsc_version_minor(i915), |
926b726c | 1767 | intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) |
5011f291 AN |
1768 | return false; |
1769 | sink_dsc_format = DP_DSC_YCbCr420_Native; | |
1770 | break; | |
1771 | default: | |
1772 | return false; | |
1773 | } | |
1774 | ||
926b726c | 1775 | return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); |
5011f291 AN |
1776 | } |
1777 | ||
dc59990e | 1778 | static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock, |
1c56e9a3 AN |
1779 | u32 lane_count, u32 mode_clock, |
1780 | enum intel_output_format output_format, | |
1781 | int timeslots) | |
1782 | { | |
1783 | u32 available_bw, required_bw; | |
1784 | ||
dc59990e AN |
1785 | available_bw = (link_clock * lane_count * timeslots * 16) / 8; |
1786 | required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock)); | |
1c56e9a3 AN |
1787 | |
1788 | return available_bw > required_bw; | |
1789 | } | |
1790 | ||
1791 | static int dsc_compute_link_config(struct intel_dp *intel_dp, | |
1792 | struct intel_crtc_state *pipe_config, | |
1793 | struct link_config_limits *limits, | |
dc59990e | 1794 | u16 compressed_bppx16, |
1c56e9a3 AN |
1795 | int timeslots) |
1796 | { | |
1797 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; | |
1798 | int link_rate, lane_count; | |
1799 | int i; | |
1800 | ||
1801 | for (i = 0; i < intel_dp->num_common_rates; i++) { | |
1802 | link_rate = intel_dp_common_rate(intel_dp, i); | |
1803 | if (link_rate < limits->min_rate || link_rate > limits->max_rate) | |
1804 | continue; | |
1805 | ||
1806 | for (lane_count = limits->min_lane_count; | |
1807 | lane_count <= limits->max_lane_count; | |
1808 | lane_count <<= 1) { | |
dc59990e AN |
1809 | if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, |
1810 | lane_count, adjusted_mode->clock, | |
1c56e9a3 AN |
1811 | pipe_config->output_format, |
1812 | timeslots)) | |
1813 | continue; | |
1814 | ||
1815 | pipe_config->lane_count = lane_count; | |
1816 | pipe_config->port_clock = link_rate; | |
1817 | ||
1818 | return 0; | |
1819 | } | |
1820 | } | |
1821 | ||
1822 | return -EINVAL; | |
1823 | } | |
1824 | ||
1825 | static | |
bb414c94 | 1826 | u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, |
1c56e9a3 AN |
1827 | struct intel_crtc_state *pipe_config, |
1828 | int bpc) | |
1829 | { | |
bb414c94 | 1830 | u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); |
1c56e9a3 AN |
1831 | |
1832 | if (max_bppx16) | |
1833 | return max_bppx16; | |
1834 | /* | |
1835 | * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate | |
1836 | * values as given in spec Table 2-157 DP v2.0 | |
1837 | */ | |
1838 | switch (pipe_config->output_format) { | |
1839 | case INTEL_OUTPUT_FORMAT_RGB: | |
1840 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
1841 | return (3 * bpc) << 4; | |
1842 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
1843 | return (3 * (bpc / 2)) << 4; | |
1844 | default: | |
1845 | MISSING_CASE(pipe_config->output_format); | |
1846 | break; | |
1847 | } | |
1848 | ||
1849 | return 0; | |
1850 | } | |
1851 | ||
99831ab9 | 1852 | int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) |
1c56e9a3 AN |
1853 | { |
1854 | /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ | |
1855 | switch (pipe_config->output_format) { | |
1856 | case INTEL_OUTPUT_FORMAT_RGB: | |
1857 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
1858 | return 8; | |
1859 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
1860 | return 6; | |
1861 | default: | |
1862 | MISSING_CASE(pipe_config->output_format); | |
1863 | break; | |
1864 | } | |
1865 | ||
1866 | return 0; | |
1867 | } | |
1868 | ||
99831ab9 SL |
1869 | int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, |
1870 | struct intel_crtc_state *pipe_config, | |
1871 | int bpc) | |
1c56e9a3 | 1872 | { |
bb414c94 | 1873 | return intel_dp_dsc_max_sink_compressed_bppx16(connector, |
1c56e9a3 AN |
1874 | pipe_config, bpc) >> 4; |
1875 | } | |
1876 | ||
1877 | static int dsc_src_min_compressed_bpp(void) | |
1878 | { | |
1879 | /* Min Compressed bpp supported by source is 8 */ | |
1880 | return 8; | |
1881 | } | |
1882 | ||
1883 | static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) | |
1884 | { | |
1885 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
1886 | ||
1887 | /* | |
1888 | * Max Compressed bpp for Gen 13+ is 27bpp. | |
1889 | * For earlier platform is 23bpp. (Bspec:49259). | |
1890 | */ | |
8dfce5f3 | 1891 | if (DISPLAY_VER(i915) < 13) |
1c56e9a3 AN |
1892 | return 23; |
1893 | else | |
1894 | return 27; | |
1895 | } | |
1896 | ||
1897 | /* | |
1898 | * From a list of valid compressed bpps try different compressed bpp and find a | |
1899 | * suitable link configuration that can support it. | |
1900 | */ | |
1901 | static int | |
1902 | icl_dsc_compute_link_config(struct intel_dp *intel_dp, | |
1903 | struct intel_crtc_state *pipe_config, | |
1904 | struct link_config_limits *limits, | |
1905 | int dsc_max_bpp, | |
1906 | int dsc_min_bpp, | |
1907 | int pipe_bpp, | |
1908 | int timeslots) | |
1909 | { | |
1910 | int i, ret; | |
1911 | ||
1912 | /* Compressed BPP should be less than the Input DSC bpp */ | |
1913 | dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); | |
1914 | ||
1915 | for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { | |
5a1da42b AN |
1916 | if (valid_dsc_bpp[i] < dsc_min_bpp) |
1917 | continue; | |
1918 | if (valid_dsc_bpp[i] > dsc_max_bpp) | |
1c56e9a3 AN |
1919 | break; |
1920 | ||
1921 | ret = dsc_compute_link_config(intel_dp, | |
1922 | pipe_config, | |
1923 | limits, | |
dc59990e | 1924 | valid_dsc_bpp[i] << 4, |
1c56e9a3 AN |
1925 | timeslots); |
1926 | if (ret == 0) { | |
59a266f0 AN |
1927 | pipe_config->dsc.compressed_bpp_x16 = |
1928 | to_bpp_x16(valid_dsc_bpp[i]); | |
1c56e9a3 AN |
1929 | return 0; |
1930 | } | |
1931 | } | |
1932 | ||
1933 | return -EINVAL; | |
1934 | } | |
1935 | ||
1936 | /* | |
1937 | * From XE_LPD onwards we supports compression bpps in steps of 1 up to | |
1938 | * uncompressed bpp-1. So we start from max compressed bpp and see if any | |
1939 | * link configuration is able to support that compressed bpp, if not we | |
1940 | * step down and check for lower compressed bpp. | |
1941 | */ | |
1942 | static int | |
1943 | xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, | |
dc59990e | 1944 | const struct intel_connector *connector, |
1c56e9a3 AN |
1945 | struct intel_crtc_state *pipe_config, |
1946 | struct link_config_limits *limits, | |
1947 | int dsc_max_bpp, | |
1948 | int dsc_min_bpp, | |
1949 | int pipe_bpp, | |
1950 | int timeslots) | |
1951 | { | |
dc59990e AN |
1952 | u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); |
1953 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
1954 | u16 compressed_bppx16; | |
1955 | u8 bppx16_step; | |
1c56e9a3 AN |
1956 | int ret; |
1957 | ||
dc59990e AN |
1958 | if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) |
1959 | bppx16_step = 16; | |
1960 | else | |
1961 | bppx16_step = 16 / bppx16_incr; | |
1962 | ||
1c56e9a3 | 1963 | /* Compressed BPP should be less than the Input DSC bpp */ |
dc59990e AN |
1964 | dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step); |
1965 | dsc_min_bpp = dsc_min_bpp << 4; | |
1c56e9a3 | 1966 | |
dc59990e AN |
1967 | for (compressed_bppx16 = dsc_max_bpp; |
1968 | compressed_bppx16 >= dsc_min_bpp; | |
1969 | compressed_bppx16 -= bppx16_step) { | |
5bbdcc86 SS |
1970 | if (intel_dp->force_dsc_fractional_bpp_en && |
1971 | !to_bpp_frac(compressed_bppx16)) | |
1972 | continue; | |
1c56e9a3 AN |
1973 | ret = dsc_compute_link_config(intel_dp, |
1974 | pipe_config, | |
1975 | limits, | |
dc59990e | 1976 | compressed_bppx16, |
1c56e9a3 AN |
1977 | timeslots); |
1978 | if (ret == 0) { | |
dc59990e | 1979 | pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; |
5bbdcc86 SS |
1980 | if (intel_dp->force_dsc_fractional_bpp_en && |
1981 | to_bpp_frac(compressed_bppx16)) | |
1982 | drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n"); | |
1983 | ||
1c56e9a3 AN |
1984 | return 0; |
1985 | } | |
1986 | } | |
1987 | return -EINVAL; | |
1988 | } | |
1989 | ||
1990 | static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, | |
bb414c94 | 1991 | const struct intel_connector *connector, |
1c56e9a3 AN |
1992 | struct intel_crtc_state *pipe_config, |
1993 | struct link_config_limits *limits, | |
1994 | int pipe_bpp, | |
1995 | int timeslots) | |
1996 | { | |
1997 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; | |
1998 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
1999 | int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; | |
2000 | int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; | |
2001 | int dsc_joiner_max_bpp; | |
2002 | ||
2003 | dsc_src_min_bpp = dsc_src_min_compressed_bpp(); | |
99831ab9 | 2004 | dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); |
1c56e9a3 | 2005 | dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); |
592b9bfd | 2006 | dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); |
1c56e9a3 AN |
2007 | |
2008 | dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); | |
99831ab9 SL |
2009 | dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, |
2010 | pipe_config, | |
2011 | pipe_bpp / 3); | |
1c56e9a3 AN |
2012 | dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; |
2013 | ||
2014 | dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, | |
2015 | adjusted_mode->hdisplay, | |
2016 | pipe_config->bigjoiner_pipes); | |
2017 | dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp); | |
592b9bfd | 2018 | dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); |
1c56e9a3 AN |
2019 | |
2020 | if (DISPLAY_VER(i915) >= 13) | |
dc59990e | 2021 | return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits, |
1c56e9a3 AN |
2022 | dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); |
2023 | return icl_dsc_compute_link_config(intel_dp, pipe_config, limits, | |
2024 | dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); | |
2025 | } | |
2026 | ||
8a969033 AN |
2027 | static |
2028 | u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) | |
2029 | { | |
2030 | /* Min DSC Input BPC for ICL+ is 8 */ | |
2031 | return HAS_DSC(i915) ? 8 : 0; | |
2032 | } | |
2033 | ||
2f4761c6 | 2034 | static |
874aa4a3 AN |
2035 | bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, |
2036 | struct drm_connector_state *conn_state, | |
2037 | struct link_config_limits *limits, | |
2038 | int pipe_bpp) | |
2f4761c6 | 2039 | { |
874aa4a3 AN |
2040 | u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp; |
2041 | ||
2042 | dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc); | |
2043 | dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); | |
2044 | ||
703c5994 ID |
2045 | dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); |
2046 | dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); | |
874aa4a3 AN |
2047 | |
2048 | return pipe_bpp >= dsc_min_pipe_bpp && | |
2049 | pipe_bpp <= dsc_max_pipe_bpp; | |
2f4761c6 AN |
2050 | } |
2051 | ||
9c8160a3 | 2052 | static |
874aa4a3 AN |
2053 | int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, |
2054 | struct drm_connector_state *conn_state, | |
2055 | struct link_config_limits *limits) | |
9c8160a3 AN |
2056 | { |
2057 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
2058 | int forced_bpp; | |
2059 | ||
2060 | if (!intel_dp->force_dsc_bpc) | |
2061 | return 0; | |
2062 | ||
2063 | forced_bpp = intel_dp->force_dsc_bpc * 3; | |
2064 | ||
874aa4a3 | 2065 | if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) { |
9c8160a3 AN |
2066 | drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); |
2067 | return forced_bpp; | |
2068 | } | |
2069 | ||
2070 | drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n", | |
2071 | intel_dp->force_dsc_bpc); | |
2072 | ||
2073 | return 0; | |
2074 | } | |
2075 | ||
2076 | static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, | |
2077 | struct intel_crtc_state *pipe_config, | |
2078 | struct drm_connector_state *conn_state, | |
2079 | struct link_config_limits *limits, | |
2080 | int timeslots) | |
2081 | { | |
9c8160a3 | 2082 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
bb414c94 ID |
2083 | const struct intel_connector *connector = |
2084 | to_intel_connector(conn_state->connector); | |
1c56e9a3 AN |
2085 | u8 max_req_bpc = conn_state->max_requested_bpc; |
2086 | u8 dsc_max_bpc, dsc_max_bpp; | |
2087 | u8 dsc_min_bpc, dsc_min_bpp; | |
eebc1525 | 2088 | u8 dsc_bpc[3] = {}; |
9c8160a3 | 2089 | int forced_bpp, pipe_bpp; |
1c56e9a3 | 2090 | int num_bpc, i, ret; |
9c8160a3 | 2091 | |
874aa4a3 | 2092 | forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); |
9c8160a3 AN |
2093 | |
2094 | if (forced_bpp) { | |
bb414c94 | 2095 | ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, |
1c56e9a3 AN |
2096 | limits, forced_bpp, timeslots); |
2097 | if (ret == 0) { | |
2098 | pipe_config->pipe_bpp = forced_bpp; | |
2099 | return 0; | |
9c8160a3 AN |
2100 | } |
2101 | } | |
1c56e9a3 | 2102 | |
cd7b0b2d | 2103 | dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); |
1c56e9a3 | 2104 | if (!dsc_max_bpc) |
9c8160a3 | 2105 | return -EINVAL; |
9c8160a3 | 2106 | |
1c56e9a3 | 2107 | dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); |
703c5994 | 2108 | dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); |
9c8160a3 | 2109 | |
1c56e9a3 | 2110 | dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); |
703c5994 | 2111 | dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); |
9c8160a3 | 2112 | |
1c56e9a3 AN |
2113 | /* |
2114 | * Get the maximum DSC bpc that will be supported by any valid | |
2115 | * link configuration and compressed bpp. | |
2116 | */ | |
cc81951d | 2117 | num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); |
1c56e9a3 AN |
2118 | for (i = 0; i < num_bpc; i++) { |
2119 | pipe_bpp = dsc_bpc[i] * 3; | |
2120 | if (pipe_bpp < dsc_min_bpp) | |
2121 | break; | |
2122 | if (pipe_bpp > dsc_max_bpp) | |
2123 | continue; | |
bb414c94 | 2124 | ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, |
1c56e9a3 AN |
2125 | limits, pipe_bpp, timeslots); |
2126 | if (ret == 0) { | |
2127 | pipe_config->pipe_bpp = pipe_bpp; | |
2128 | return 0; | |
2129 | } | |
2130 | } | |
9c8160a3 | 2131 | |
1c56e9a3 | 2132 | return -EINVAL; |
9c8160a3 AN |
2133 | } |
2134 | ||
2135 | static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, | |
2136 | struct intel_crtc_state *pipe_config, | |
2137 | struct drm_connector_state *conn_state, | |
2138 | struct link_config_limits *limits) | |
2139 | { | |
2140 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
f52bbfe2 ID |
2141 | struct intel_connector *connector = |
2142 | to_intel_connector(conn_state->connector); | |
9c8160a3 | 2143 | int pipe_bpp, forced_bpp; |
61d340fa AN |
2144 | int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; |
2145 | int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; | |
9c8160a3 | 2146 | |
874aa4a3 | 2147 | forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); |
9c8160a3 AN |
2148 | |
2149 | if (forced_bpp) { | |
2150 | pipe_bpp = forced_bpp; | |
2151 | } else { | |
703c5994 | 2152 | int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc); |
a10ca2af | 2153 | |
9c8160a3 | 2154 | /* For eDP use max bpp that can be supported with DSC. */ |
f52bbfe2 | 2155 | pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); |
874aa4a3 | 2156 | if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) { |
9c8160a3 | 2157 | drm_dbg_kms(&i915->drm, |
874aa4a3 | 2158 | "Computed BPC is not in DSC BPC limits\n"); |
9c8160a3 AN |
2159 | return -EINVAL; |
2160 | } | |
2161 | } | |
2162 | pipe_config->port_clock = limits->max_rate; | |
2163 | pipe_config->lane_count = limits->max_lane_count; | |
61d340fa AN |
2164 | |
2165 | dsc_src_min_bpp = dsc_src_min_compressed_bpp(); | |
99831ab9 | 2166 | dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); |
61d340fa | 2167 | dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); |
592b9bfd | 2168 | dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); |
61d340fa AN |
2169 | |
2170 | dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); | |
99831ab9 SL |
2171 | dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, |
2172 | pipe_config, | |
2173 | pipe_bpp / 3); | |
61d340fa | 2174 | dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; |
592b9bfd | 2175 | dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); |
61d340fa AN |
2176 | |
2177 | /* Compressed BPP should be less than the Input DSC bpp */ | |
2178 | dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); | |
2179 | ||
59a266f0 AN |
2180 | pipe_config->dsc.compressed_bpp_x16 = |
2181 | to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp)); | |
9c8160a3 AN |
2182 | |
2183 | pipe_config->pipe_bpp = pipe_bpp; | |
2184 | ||
2185 | return 0; | |
2186 | } | |
2187 | ||
d51f25eb SL |
2188 | int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
2189 | struct intel_crtc_state *pipe_config, | |
2190 | struct drm_connector_state *conn_state, | |
2191 | struct link_config_limits *limits, | |
52f14682 SL |
2192 | int timeslots, |
2193 | bool compute_pipe_bpp) | |
a4a15777 MN |
2194 | { |
2195 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2196 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
987c945a ID |
2197 | const struct intel_connector *connector = |
2198 | to_intel_connector(conn_state->connector); | |
0c1abaa7 VS |
2199 | const struct drm_display_mode *adjusted_mode = |
2200 | &pipe_config->hw.adjusted_mode; | |
204474a6 | 2201 | int ret; |
a4a15777 | 2202 | |
36f579ff ID |
2203 | pipe_config->fec_enable = pipe_config->fec_enable || |
2204 | (!intel_dp_is_edp(intel_dp) && | |
2205 | intel_dp_supports_fec(intel_dp, connector, pipe_config)); | |
6fd3134a | 2206 | |
0d8665e0 | 2207 | if (!intel_dp_supports_dsc(connector, pipe_config)) |
204474a6 | 2208 | return -EINVAL; |
a4a15777 | 2209 | |
926b726c | 2210 | if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) |
5011f291 AN |
2211 | return -EINVAL; |
2212 | ||
9c8160a3 AN |
2213 | /* |
2214 | * compute pipe bpp is set to false for DP MST DSC case | |
2215 | * and compressed_bpp is calculated same time once | |
2216 | * vpci timeslots are allocated, because overall bpp | |
2217 | * calculation procedure is bit different for MST case. | |
2218 | */ | |
2f4761c6 | 2219 | if (compute_pipe_bpp) { |
9c8160a3 AN |
2220 | if (intel_dp_is_edp(intel_dp)) |
2221 | ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, | |
2222 | conn_state, limits); | |
2223 | else | |
2224 | ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, | |
2225 | conn_state, limits, timeslots); | |
2226 | if (ret) { | |
2227 | drm_dbg_kms(&dev_priv->drm, | |
2228 | "No Valid pipe bpp for given mode ret = %d\n", ret); | |
2229 | return ret; | |
2f4761c6 | 2230 | } |
a4a15777 MN |
2231 | } |
2232 | ||
9c8160a3 | 2233 | /* Calculate Slice count */ |
a4a15777 | 2234 | if (intel_dp_is_edp(intel_dp)) { |
010663a6 | 2235 | pipe_config->dsc.slice_count = |
2bd3d20f | 2236 | drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, |
a4a15777 | 2237 | true); |
51f70082 NZ |
2238 | if (!pipe_config->dsc.slice_count) { |
2239 | drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n", | |
2240 | pipe_config->dsc.slice_count); | |
2241 | return -EINVAL; | |
2242 | } | |
a4a15777 | 2243 | } else { |
a4a15777 MN |
2244 | u8 dsc_dp_slice_count; |
2245 | ||
a4a15777 | 2246 | dsc_dp_slice_count = |
7bca1b80 | 2247 | intel_dp_dsc_get_slice_count(connector, |
a4a15777 | 2248 | adjusted_mode->crtc_clock, |
63dc014e | 2249 | adjusted_mode->crtc_hdisplay, |
4d1b53df | 2250 | pipe_config->bigjoiner_pipes); |
52f14682 | 2251 | if (!dsc_dp_slice_count) { |
bdc6114e | 2252 | drm_dbg_kms(&dev_priv->drm, |
52f14682 | 2253 | "Compressed Slice Count not supported\n"); |
204474a6 | 2254 | return -EINVAL; |
a4a15777 | 2255 | } |
52f14682 | 2256 | |
010663a6 | 2257 | pipe_config->dsc.slice_count = dsc_dp_slice_count; |
a4a15777 MN |
2258 | } |
2259 | /* | |
2260 | * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate | |
2261 | * is greater than the maximum Cdclock and if slice count is even | |
2262 | * then we need to use 2 VDSC instances. | |
2263 | */ | |
ce086a32 SL |
2264 | if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1) |
2265 | pipe_config->dsc.dsc_split = true; | |
204474a6 | 2266 | |
2c4907c2 | 2267 | ret = intel_dp_dsc_compute_params(connector, pipe_config); |
204474a6 | 2268 | if (ret < 0) { |
bdc6114e | 2269 | drm_dbg_kms(&dev_priv->drm, |
59a266f0 AN |
2270 | "Cannot compute valid DSC parameters for Input Bpp = %d" |
2271 | "Compressed BPP = " BPP_X16_FMT "\n", | |
bdc6114e | 2272 | pipe_config->pipe_bpp, |
59a266f0 | 2273 | BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16)); |
204474a6 | 2274 | return ret; |
168243c1 | 2275 | } |
204474a6 | 2276 | |
010663a6 | 2277 | pipe_config->dsc.compression_enable = true; |
bdc6114e | 2278 | drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " |
59a266f0 | 2279 | "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n", |
bdc6114e | 2280 | pipe_config->pipe_bpp, |
59a266f0 | 2281 | BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16), |
bdc6114e | 2282 | pipe_config->dsc.slice_count); |
a4a15777 | 2283 | |
204474a6 | 2284 | return 0; |
a4a15777 MN |
2285 | } |
2286 | ||
78015e27 ID |
2287 | /** |
2288 | * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits | |
2289 | * @intel_dp: intel DP | |
2290 | * @crtc_state: crtc state | |
2291 | * @dsc: DSC compression mode | |
2292 | * @limits: link configuration limits | |
2293 | * | |
2294 | * Calculates the output link min, max bpp values in @limits based on the | |
2295 | * pipe bpp range, @crtc_state and @dsc mode. | |
2296 | * | |
2297 | * Returns %true in case of success. | |
2298 | */ | |
2299 | bool | |
2300 | intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, | |
2301 | const struct intel_crtc_state *crtc_state, | |
2302 | bool dsc, | |
2303 | struct link_config_limits *limits) | |
2304 | { | |
2305 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); | |
2306 | const struct drm_display_mode *adjusted_mode = | |
2307 | &crtc_state->hw.adjusted_mode; | |
2308 | const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
2309 | const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
2310 | int max_link_bpp_x16; | |
2311 | ||
998d2cd3 ID |
2312 | max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, |
2313 | to_bpp_x16(limits->pipe.max_bpp)); | |
78015e27 ID |
2314 | |
2315 | if (!dsc) { | |
2316 | max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3)); | |
2317 | ||
2318 | if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp)) | |
2319 | return false; | |
2320 | ||
2321 | limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp); | |
2322 | } else { | |
2323 | /* | |
2324 | * TODO: set the DSC link limits already here, atm these are | |
2325 | * initialized only later in intel_edp_dsc_compute_pipe_bpp() / | |
2326 | * intel_dp_dsc_compute_pipe_bpp() | |
2327 | */ | |
2328 | limits->link.min_bpp_x16 = 0; | |
2329 | } | |
2330 | ||
2331 | limits->link.max_bpp_x16 = max_link_bpp_x16; | |
2332 | ||
2333 | drm_dbg_kms(&i915->drm, | |
2334 | "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n", | |
2335 | encoder->base.base.id, encoder->base.name, | |
2336 | crtc->base.base.id, crtc->base.name, | |
2337 | adjusted_mode->crtc_clock, | |
2338 | dsc ? "on" : "off", | |
2339 | limits->max_lane_count, | |
2340 | limits->max_rate, | |
2341 | limits->pipe.max_bpp, | |
2342 | BPP_X16_ARGS(limits->link.max_bpp_x16)); | |
2343 | ||
2344 | return true; | |
2345 | } | |
2346 | ||
2347 | static bool | |
72b2d2a6 ID |
2348 | intel_dp_compute_config_limits(struct intel_dp *intel_dp, |
2349 | struct intel_crtc_state *crtc_state, | |
2350 | bool respect_downstream_limits, | |
78015e27 | 2351 | bool dsc, |
72b2d2a6 | 2352 | struct link_config_limits *limits) |
a4fc5ed6 | 2353 | { |
72b2d2a6 ID |
2354 | limits->min_rate = intel_dp_common_rate(intel_dp, 0); |
2355 | limits->max_rate = intel_dp_max_link_rate(intel_dp); | |
7c2781e4 | 2356 | |
6061811d VS |
2357 | /* FIXME 128b/132b SST support missing */ |
2358 | limits->max_rate = min(limits->max_rate, 810000); | |
2359 | ||
72b2d2a6 ID |
2360 | limits->min_lane_count = 1; |
2361 | limits->max_lane_count = intel_dp_max_lane_count(intel_dp); | |
7c2781e4 | 2362 | |
703c5994 ID |
2363 | limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); |
2364 | limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, | |
2365 | respect_downstream_limits); | |
a4fc5ed6 | 2366 | |
2bbd6dba | 2367 | if (intel_dp->use_max_params) { |
344c5bbc JN |
2368 | /* |
2369 | * Use the maximum clock and number of lanes the eDP panel | |
2bbd6dba VS |
2370 | * advertizes being capable of in case the initial fast |
2371 | * optimal params failed us. The panels are generally | |
f11cb1c1 | 2372 | * designed to support only a single clock and lane |
2bbd6dba VS |
2373 | * configuration, and typically on older panels these |
2374 | * values correspond to the native resolution of the panel. | |
344c5bbc | 2375 | */ |
72b2d2a6 ID |
2376 | limits->min_lane_count = limits->max_lane_count; |
2377 | limits->min_rate = limits->max_rate; | |
7984211e | 2378 | } |
657445fe | 2379 | |
72b2d2a6 | 2380 | intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); |
a4971453 | 2381 | |
78015e27 ID |
2382 | return intel_dp_compute_config_link_bpp_limits(intel_dp, |
2383 | crtc_state, | |
2384 | dsc, | |
2385 | limits); | |
72b2d2a6 ID |
2386 | } |
2387 | ||
e35cce93 ID |
2388 | int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) |
2389 | { | |
2390 | const struct drm_display_mode *adjusted_mode = | |
2391 | &crtc_state->hw.adjusted_mode; | |
2392 | int bpp = crtc_state->dsc.compression_enable ? | |
2393 | to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) : | |
2394 | crtc_state->pipe_bpp; | |
2395 | ||
2396 | return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); | |
2397 | } | |
2398 | ||
72b2d2a6 ID |
2399 | static int |
2400 | intel_dp_compute_link_config(struct intel_encoder *encoder, | |
2401 | struct intel_crtc_state *pipe_config, | |
2402 | struct drm_connector_state *conn_state, | |
2403 | bool respect_downstream_limits) | |
2404 | { | |
2405 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2406 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); | |
36f579ff ID |
2407 | const struct intel_connector *connector = |
2408 | to_intel_connector(conn_state->connector); | |
72b2d2a6 ID |
2409 | const struct drm_display_mode *adjusted_mode = |
2410 | &pipe_config->hw.adjusted_mode; | |
2411 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2412 | struct link_config_limits limits; | |
2413 | bool joiner_needs_dsc = false; | |
7d0f2f68 ID |
2414 | bool dsc_needed; |
2415 | int ret = 0; | |
72b2d2a6 | 2416 | |
36f579ff ID |
2417 | if (pipe_config->fec_enable && |
2418 | !intel_dp_supports_fec(intel_dp, connector, pipe_config)) | |
2419 | return -EINVAL; | |
2420 | ||
e0ccf1d6 VS |
2421 | if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay, |
2422 | adjusted_mode->crtc_clock)) | |
4d1b53df | 2423 | pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); |
19f65a3d | 2424 | |
1dedcdd0 JN |
2425 | /* |
2426 | * Pipe joiner needs compression up to display 12 due to bandwidth | |
2427 | * limitation. DG2 onwards pipe joiner can be enabled without | |
2428 | * compression. | |
2429 | */ | |
2430 | joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes; | |
2431 | ||
78015e27 ID |
2432 | dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || |
2433 | !intel_dp_compute_config_limits(intel_dp, pipe_config, | |
2434 | respect_downstream_limits, | |
2435 | false, | |
2436 | &limits); | |
7d0f2f68 ID |
2437 | |
2438 | if (!dsc_needed) { | |
2439 | /* | |
2440 | * Optimize for slow and wide for everything, because there are some | |
2441 | * eDP 1.3 and 1.4 panels don't work well with fast and narrow. | |
2442 | */ | |
2443 | ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, | |
2444 | conn_state, &limits); | |
2445 | if (ret) | |
2446 | dsc_needed = true; | |
2447 | } | |
a4a15777 | 2448 | |
7d0f2f68 | 2449 | if (dsc_needed) { |
1dedcdd0 JN |
2450 | drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", |
2451 | str_yes_no(ret), str_yes_no(joiner_needs_dsc), | |
2452 | str_yes_no(intel_dp->force_dsc_en)); | |
78015e27 ID |
2453 | |
2454 | if (!intel_dp_compute_config_limits(intel_dp, pipe_config, | |
2455 | respect_downstream_limits, | |
2456 | true, | |
2457 | &limits)) | |
2458 | return -EINVAL; | |
2459 | ||
204474a6 | 2460 | ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, |
a6fd6f94 | 2461 | conn_state, &limits, 64, true); |
204474a6 LP |
2462 | if (ret < 0) |
2463 | return ret; | |
7769db58 | 2464 | } |
981a63eb | 2465 | |
e35cce93 ID |
2466 | drm_dbg_kms(&i915->drm, |
2467 | "DP lane count %d clock %d bpp input %d compressed " BPP_X16_FMT " link rate required %d available %d\n", | |
2468 | pipe_config->lane_count, pipe_config->port_clock, | |
2469 | pipe_config->pipe_bpp, | |
2470 | BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16), | |
2471 | intel_dp_config_required_rate(pipe_config), | |
a4ea61b7 ID |
2472 | intel_dp_max_link_data_rate(intel_dp, |
2473 | pipe_config->port_clock, | |
2474 | pipe_config->lane_count)); | |
a4a15777 | 2475 | |
204474a6 | 2476 | return 0; |
981a63eb JN |
2477 | } |
2478 | ||
37aa52bf VS |
2479 | bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
2480 | const struct drm_connector_state *conn_state) | |
2481 | { | |
2482 | const struct intel_digital_connector_state *intel_conn_state = | |
2483 | to_intel_digital_connector_state(conn_state); | |
2484 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 2485 | &crtc_state->hw.adjusted_mode; |
37aa52bf | 2486 | |
cae154fc VS |
2487 | /* |
2488 | * Our YCbCr output is always limited range. | |
2489 | * crtc_state->limited_color_range only applies to RGB, | |
2490 | * and it must never be set for YCbCr or we risk setting | |
3eb08ea5 | 2491 | * some conflicting bits in TRANSCONF which will mess up |
cae154fc VS |
2492 | * the colors on the monitor. |
2493 | */ | |
2494 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
2495 | return false; | |
2496 | ||
37aa52bf VS |
2497 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
2498 | /* | |
2499 | * See: | |
2500 | * CEA-861-E - 5.1 Default Encoding Parameters | |
2501 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
2502 | */ | |
2503 | return crtc_state->pipe_bpp != 18 && | |
2504 | drm_default_rgb_quant_range(adjusted_mode) == | |
2505 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
2506 | } else { | |
2507 | return intel_conn_state->broadcast_rgb == | |
2508 | INTEL_BROADCAST_RGB_LIMITED; | |
2509 | } | |
2510 | } | |
2511 | ||
07130981 KV |
2512 | static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, |
2513 | enum port port) | |
2514 | { | |
2515 | if (IS_G4X(dev_priv)) | |
2516 | return false; | |
005e9537 | 2517 | if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A) |
07130981 KV |
2518 | return false; |
2519 | ||
2520 | return true; | |
2521 | } | |
2522 | ||
9799c4c3 GM |
2523 | static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, |
2524 | const struct drm_connector_state *conn_state, | |
2525 | struct drm_dp_vsc_sdp *vsc) | |
2526 | { | |
2527 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
2528 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
2529 | ||
b8cf5b5d AM |
2530 | if (crtc_state->has_panel_replay) { |
2531 | /* | |
2532 | * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 | |
2533 | * VSC SDP supporting 3D stereo, Panel Replay, and Pixel | |
2534 | * Encoding/Colorimetry Format indication. | |
2535 | */ | |
2536 | vsc->revision = 0x7; | |
2537 | } else { | |
2538 | /* | |
2539 | * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 | |
2540 | * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ | |
2541 | * Colorimetry Format indication. | |
2542 | */ | |
2543 | vsc->revision = 0x5; | |
2544 | } | |
2545 | ||
9799c4c3 GM |
2546 | vsc->length = 0x13; |
2547 | ||
2548 | /* DP 1.4a spec, Table 2-120 */ | |
2549 | switch (crtc_state->output_format) { | |
2550 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
2551 | vsc->pixelformat = DP_PIXELFORMAT_YUV444; | |
2552 | break; | |
2553 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
2554 | vsc->pixelformat = DP_PIXELFORMAT_YUV420; | |
2555 | break; | |
2556 | case INTEL_OUTPUT_FORMAT_RGB: | |
2557 | default: | |
2558 | vsc->pixelformat = DP_PIXELFORMAT_RGB; | |
2559 | } | |
2560 | ||
2561 | switch (conn_state->colorspace) { | |
2562 | case DRM_MODE_COLORIMETRY_BT709_YCC: | |
2563 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; | |
2564 | break; | |
2565 | case DRM_MODE_COLORIMETRY_XVYCC_601: | |
2566 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; | |
2567 | break; | |
2568 | case DRM_MODE_COLORIMETRY_XVYCC_709: | |
2569 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; | |
2570 | break; | |
2571 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
2572 | vsc->colorimetry = DP_COLORIMETRY_SYCC_601; | |
2573 | break; | |
2574 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
2575 | vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; | |
2576 | break; | |
2577 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
2578 | vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; | |
2579 | break; | |
2580 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
2581 | vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; | |
2582 | break; | |
2583 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
2584 | vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; | |
2585 | break; | |
2586 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: | |
2587 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: | |
2588 | vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; | |
2589 | break; | |
2590 | default: | |
2591 | /* | |
2592 | * RGB->YCBCR color conversion uses the BT.709 | |
2593 | * color space. | |
2594 | */ | |
2595 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
2596 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; | |
2597 | else | |
2598 | vsc->colorimetry = DP_COLORIMETRY_DEFAULT; | |
2599 | break; | |
2600 | } | |
2601 | ||
2602 | vsc->bpc = crtc_state->pipe_bpp / 3; | |
2603 | ||
2604 | /* only RGB pixelformat supports 6 bpc */ | |
2605 | drm_WARN_ON(&dev_priv->drm, | |
2606 | vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); | |
2607 | ||
2608 | /* all YCbCr are always limited range */ | |
2609 | vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; | |
2610 | vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; | |
2611 | } | |
2612 | ||
2613 | static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, | |
2614 | struct intel_crtc_state *crtc_state, | |
2615 | const struct drm_connector_state *conn_state) | |
2616 | { | |
31a5b6ed | 2617 | struct drm_dp_vsc_sdp *vsc; |
9799c4c3 | 2618 | |
31a5b6ed JH |
2619 | if ((!intel_dp->colorimetry_support || |
2620 | !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && | |
2621 | !crtc_state->has_psr) | |
9799c4c3 GM |
2622 | return; |
2623 | ||
31a5b6ed | 2624 | vsc = &crtc_state->infoframes.vsc; |
9799c4c3 GM |
2625 | |
2626 | crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); | |
2627 | vsc->sdp_type = DP_SDP_VSC; | |
cafac5a9 | 2628 | |
fde53fa1 JH |
2629 | /* Needs colorimetry */ |
2630 | if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { | |
2631 | intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, | |
2632 | vsc); | |
2633 | } else if (crtc_state->has_psr2) { | |
2634 | /* | |
2635 | * [PSR2 without colorimetry] | |
2636 | * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 | |
2637 | * 3D stereo + PSR/PSR2 + Y-coordinate. | |
2638 | */ | |
2639 | vsc->revision = 0x4; | |
2640 | vsc->length = 0xe; | |
b8cf5b5d | 2641 | } else if (crtc_state->has_panel_replay) { |
fde53fa1 JH |
2642 | /* |
2643 | * [Panel Replay without colorimetry info] | |
2644 | * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 | |
2645 | * VSC SDP supporting 3D stereo + Panel Replay. | |
2646 | */ | |
2647 | vsc->revision = 0x6; | |
2648 | vsc->length = 0x10; | |
cafac5a9 GM |
2649 | } else { |
2650 | /* | |
2651 | * [PSR1] | |
2652 | * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 | |
2653 | * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or | |
2654 | * higher). | |
2655 | */ | |
2656 | vsc->revision = 0x2; | |
2657 | vsc->length = 0x8; | |
2658 | } | |
2659 | } | |
2660 | ||
d1eed96d GM |
2661 | static void |
2662 | intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, | |
2663 | struct intel_crtc_state *crtc_state, | |
2664 | const struct drm_connector_state *conn_state) | |
2665 | { | |
2666 | int ret; | |
2667 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
2668 | struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; | |
2669 | ||
2670 | if (!conn_state->hdr_output_metadata) | |
2671 | return; | |
2672 | ||
2673 | ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); | |
2674 | ||
2675 | if (ret) { | |
2676 | drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); | |
2677 | return; | |
2678 | } | |
2679 | ||
2680 | crtc_state->infoframes.enable |= | |
2681 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); | |
2682 | } | |
2683 | ||
f244cdfa VS |
2684 | static bool can_enable_drrs(struct intel_connector *connector, |
2685 | const struct intel_crtc_state *pipe_config, | |
2686 | const struct drm_display_mode *downclock_mode) | |
2687 | { | |
1159c833 VS |
2688 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
2689 | ||
f244cdfa VS |
2690 | if (pipe_config->vrr.enable) |
2691 | return false; | |
2692 | ||
2693 | /* | |
2694 | * DRRS and PSR can't be enable together, so giving preference to PSR | |
2695 | * as it allows more power-savings by complete shutting down display, | |
2696 | * so to guarantee this, intel_drrs_compute_config() must be called | |
2697 | * after intel_psr_compute_config(). | |
2698 | */ | |
2699 | if (pipe_config->has_psr) | |
2700 | return false; | |
2701 | ||
1159c833 VS |
2702 | /* FIXME missing FDI M2/N2 etc. */ |
2703 | if (pipe_config->has_pch_encoder) | |
2704 | return false; | |
2705 | ||
2d04f815 | 2706 | if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) |
1159c833 VS |
2707 | return false; |
2708 | ||
f244cdfa VS |
2709 | return downclock_mode && |
2710 | intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; | |
2711 | } | |
2712 | ||
2713 | static void | |
2714 | intel_dp_drrs_compute_config(struct intel_connector *connector, | |
2715 | struct intel_crtc_state *pipe_config, | |
87c8812f | 2716 | int link_bpp_x16) |
f244cdfa VS |
2717 | { |
2718 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
2719 | const struct drm_display_mode *downclock_mode = | |
2720 | intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); | |
2721 | int pixel_clock; | |
2722 | ||
e6f29923 | 2723 | if (has_seamless_m_n(connector)) |
825edc8b | 2724 | pipe_config->update_m_n = true; |
e6f29923 | 2725 | |
f244cdfa VS |
2726 | if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { |
2727 | if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) | |
2728 | intel_zero_m_n(&pipe_config->dp_m2_n2); | |
2729 | return; | |
2730 | } | |
2731 | ||
2732 | if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) | |
3cf05076 | 2733 | pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; |
f244cdfa VS |
2734 | |
2735 | pipe_config->has_drrs = true; | |
2736 | ||
2737 | pixel_clock = downclock_mode->clock; | |
2738 | if (pipe_config->splitter.enable) | |
2739 | pixel_clock /= pipe_config->splitter.link_count; | |
2740 | ||
87c8812f | 2741 | intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, |
7ff2090c ID |
2742 | pipe_config->port_clock, |
2743 | intel_dp_bw_fec_overhead(pipe_config->fec_enable), | |
2744 | &pipe_config->dp_m2_n2); | |
f244cdfa VS |
2745 | |
2746 | /* FIXME: abstract this better */ | |
2747 | if (pipe_config->splitter.enable) | |
2748 | pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; | |
2749 | } | |
2750 | ||
97e04764 | 2751 | static bool intel_dp_has_audio(struct intel_encoder *encoder, |
2e775f2d | 2752 | struct intel_crtc_state *crtc_state, |
97e04764 VS |
2753 | const struct drm_connector_state *conn_state) |
2754 | { | |
2755 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
97e04764 VS |
2756 | const struct intel_digital_connector_state *intel_conn_state = |
2757 | to_intel_digital_connector_state(conn_state); | |
2e775f2d VG |
2758 | struct intel_connector *connector = |
2759 | to_intel_connector(conn_state->connector); | |
97e04764 | 2760 | |
2e775f2d VG |
2761 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && |
2762 | !intel_dp_port_has_audio(i915, encoder->port)) | |
97e04764 VS |
2763 | return false; |
2764 | ||
2765 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
28da4f83 | 2766 | return connector->base.display_info.has_audio; |
97e04764 VS |
2767 | else |
2768 | return intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2769 | } | |
2770 | ||
632f8535 VS |
2771 | static int |
2772 | intel_dp_compute_output_format(struct intel_encoder *encoder, | |
2773 | struct intel_crtc_state *crtc_state, | |
56185b90 VS |
2774 | struct drm_connector_state *conn_state, |
2775 | bool respect_downstream_limits) | |
632f8535 VS |
2776 | { |
2777 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2778 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2779 | struct intel_connector *connector = intel_dp->attached_connector; | |
2780 | const struct drm_display_info *info = &connector->base.display_info; | |
2781 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; | |
2782 | bool ycbcr_420_only; | |
2783 | int ret; | |
2784 | ||
2785 | ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); | |
2786 | ||
a04d27cd | 2787 | if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { |
632f8535 VS |
2788 | drm_dbg_kms(&i915->drm, |
2789 | "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); | |
a04d27cd | 2790 | crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; |
a04d27cd | 2791 | } else { |
5814227d | 2792 | crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); |
632f8535 VS |
2793 | } |
2794 | ||
a04d27cd AN |
2795 | crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); |
2796 | ||
56185b90 VS |
2797 | ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, |
2798 | respect_downstream_limits); | |
632f8535 | 2799 | if (ret) { |
a04d27cd | 2800 | if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
632f8535 VS |
2801 | !connector->base.ycbcr_420_allowed || |
2802 | !drm_mode_is_420_also(info, adjusted_mode)) | |
2803 | return ret; | |
2804 | ||
a04d27cd AN |
2805 | crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
2806 | crtc_state->output_format = intel_dp_output_format(connector, | |
2807 | crtc_state->sink_format); | |
56185b90 VS |
2808 | ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, |
2809 | respect_downstream_limits); | |
632f8535 VS |
2810 | } |
2811 | ||
2812 | return ret; | |
2813 | } | |
2814 | ||
6297ee90 | 2815 | void |
8853750d VG |
2816 | intel_dp_audio_compute_config(struct intel_encoder *encoder, |
2817 | struct intel_crtc_state *pipe_config, | |
2818 | struct drm_connector_state *conn_state) | |
2819 | { | |
1bd1817b | 2820 | pipe_config->has_audio = |
2e775f2d | 2821 | intel_dp_has_audio(encoder, pipe_config, conn_state) && |
1bd1817b VG |
2822 | intel_audio_compute_config(encoder, pipe_config, conn_state); |
2823 | ||
2824 | pipe_config->sdp_split_enable = pipe_config->has_audio && | |
2825 | intel_dp_is_uhbr(pipe_config); | |
8853750d VG |
2826 | } |
2827 | ||
d1e217d4 ID |
2828 | void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) |
2829 | { | |
2830 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
2831 | ||
2832 | drm_connector_get(&connector->base); | |
2833 | if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work)) | |
2834 | drm_connector_put(&connector->base); | |
2835 | } | |
2836 | ||
2837 | void | |
2838 | intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, | |
2839 | struct intel_encoder *encoder, | |
2840 | const struct intel_crtc_state *crtc_state) | |
2841 | { | |
2842 | struct intel_connector *connector; | |
2843 | struct intel_digital_connector_state *conn_state; | |
2844 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2845 | int i; | |
2846 | ||
2847 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { | |
2848 | intel_dp_queue_modeset_retry_work(intel_dp->attached_connector); | |
2849 | ||
2850 | return; | |
2851 | } | |
2852 | ||
2853 | for_each_new_intel_connector_in_state(state, connector, conn_state, i) { | |
2854 | if (!conn_state->base.crtc) | |
2855 | continue; | |
2856 | ||
2857 | if (connector->mst_port == intel_dp) | |
2858 | intel_dp_queue_modeset_retry_work(connector); | |
2859 | } | |
2860 | } | |
2861 | ||
204474a6 | 2862 | int |
981a63eb JN |
2863 | intel_dp_compute_config(struct intel_encoder *encoder, |
2864 | struct intel_crtc_state *pipe_config, | |
2865 | struct drm_connector_state *conn_state) | |
2866 | { | |
2867 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
a4efae87 | 2868 | struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); |
1326a92c | 2869 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
b7d02c3a | 2870 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
09270678 | 2871 | const struct drm_display_mode *fixed_mode; |
2cad4279 | 2872 | struct intel_connector *connector = intel_dp->attached_connector; |
87c8812f | 2873 | int ret = 0, link_bpp_x16; |
981a63eb | 2874 | |
97e04764 | 2875 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) |
981a63eb JN |
2876 | pipe_config->has_pch_encoder = true; |
2877 | ||
2cad4279 | 2878 | fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); |
09270678 | 2879 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
2cad4279 | 2880 | ret = intel_panel_compute_config(connector, adjusted_mode); |
cff4c2c6 VS |
2881 | if (ret) |
2882 | return ret; | |
981a63eb JN |
2883 | } |
2884 | ||
e4dd27aa | 2885 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2886 | return -EINVAL; |
e4dd27aa | 2887 | |
f71c9b7b | 2888 | if (!connector->base.interlace_allowed && |
981a63eb | 2889 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
204474a6 | 2890 | return -EINVAL; |
981a63eb JN |
2891 | |
2892 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
204474a6 | 2893 | return -EINVAL; |
981a63eb | 2894 | |
98c93394 VS |
2895 | if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) |
2896 | return -EINVAL; | |
2897 | ||
56185b90 VS |
2898 | /* |
2899 | * Try to respect downstream TMDS clock limits first, if | |
2900 | * that fails assume the user might know something we don't. | |
2901 | */ | |
2902 | ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); | |
2903 | if (ret) | |
2904 | ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); | |
632f8535 | 2905 | if (ret) |
204474a6 | 2906 | return ret; |
981a63eb | 2907 | |
dd934010 VS |
2908 | if ((intel_dp_is_edp(intel_dp) && fixed_mode) || |
2909 | pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { | |
2910 | ret = intel_panel_fitting(pipe_config, conn_state); | |
2911 | if (ret) | |
2912 | return ret; | |
2913 | } | |
2914 | ||
37aa52bf VS |
2915 | pipe_config->limited_color_range = |
2916 | intel_dp_limited_color_range(pipe_config, conn_state); | |
55bc60db | 2917 | |
3072a24c VS |
2918 | pipe_config->enhanced_framing = |
2919 | drm_dp_enhanced_frame_cap(intel_dp->dpcd); | |
2920 | ||
010663a6 | 2921 | if (pipe_config->dsc.compression_enable) |
87c8812f | 2922 | link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; |
a4a15777 | 2923 | else |
87c8812f AN |
2924 | link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format, |
2925 | pipe_config->pipe_bpp)); | |
aefa95ba | 2926 | |
bc71194e JN |
2927 | if (intel_dp->mso_link_count) { |
2928 | int n = intel_dp->mso_link_count; | |
2929 | int overlap = intel_dp->mso_pixel_overlap; | |
2930 | ||
2931 | pipe_config->splitter.enable = true; | |
2932 | pipe_config->splitter.link_count = n; | |
2933 | pipe_config->splitter.pixel_overlap = overlap; | |
2934 | ||
2935 | drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n", | |
2936 | n, overlap); | |
2937 | ||
2938 | adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; | |
2939 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; | |
2940 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; | |
2941 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; | |
2942 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; | |
2943 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; | |
2944 | adjusted_mode->crtc_clock /= n; | |
2945 | } | |
2946 | ||
8853750d VG |
2947 | intel_dp_audio_compute_config(encoder, pipe_config, conn_state); |
2948 | ||
87c8812f | 2949 | intel_link_compute_m_n(link_bpp_x16, |
aefa95ba VS |
2950 | pipe_config->lane_count, |
2951 | adjusted_mode->crtc_clock, | |
2952 | pipe_config->port_clock, | |
7ff2090c ID |
2953 | intel_dp_bw_fec_overhead(pipe_config->fec_enable), |
2954 | &pipe_config->dp_m_n); | |
9d1a455b | 2955 | |
bc71194e JN |
2956 | /* FIXME: abstract this better */ |
2957 | if (pipe_config->splitter.enable) | |
5f721a5d | 2958 | pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; |
bc71194e | 2959 | |
4f8036a2 | 2960 | if (!HAS_DDI(dev_priv)) |
053ffdd1 | 2961 | g4x_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 2962 | |
117cd09b | 2963 | intel_vrr_compute_config(pipe_config, conn_state); |
9ce5884e | 2964 | intel_psr_compute_config(intel_dp, pipe_config, conn_state); |
87c8812f | 2965 | intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); |
9799c4c3 | 2966 | intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); |
d1eed96d | 2967 | intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); |
4d90f2d5 | 2968 | |
a4efae87 ID |
2969 | return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, |
2970 | pipe_config); | |
a4fc5ed6 KP |
2971 | } |
2972 | ||
901c2daf | 2973 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
a621860a | 2974 | int link_rate, int lane_count) |
901c2daf | 2975 | { |
1e9ae61d | 2976 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
edb2e530 | 2977 | intel_dp->link_trained = false; |
dfa10480 ACO |
2978 | intel_dp->link_rate = link_rate; |
2979 | intel_dp->lane_count = lane_count; | |
901c2daf VS |
2980 | } |
2981 | ||
9ad87de4 ID |
2982 | static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp) |
2983 | { | |
2984 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
2985 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
2986 | } | |
2987 | ||
1250d107 | 2988 | /* Enable backlight PWM and backlight PP control. */ |
b037d58f ML |
2989 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
2990 | const struct drm_connector_state *conn_state) | |
1250d107 | 2991 | { |
b7d02c3a | 2992 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); |
af67009c | 2993 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b037d58f | 2994 | |
1853a9da | 2995 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2996 | return; |
2997 | ||
af67009c | 2998 | drm_dbg_kms(&i915->drm, "\n"); |
1250d107 | 2999 | |
c0a52f8b | 3000 | intel_backlight_enable(crtc_state, conn_state); |
f4249942 | 3001 | intel_pps_backlight_on(intel_dp); |
1250d107 JN |
3002 | } |
3003 | ||
1250d107 | 3004 | /* Disable backlight PP control and backlight PWM. */ |
b037d58f | 3005 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
1250d107 | 3006 | { |
b7d02c3a | 3007 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); |
af67009c | 3008 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
b037d58f | 3009 | |
1853a9da | 3010 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
3011 | return; |
3012 | ||
af67009c | 3013 | drm_dbg_kms(&i915->drm, "\n"); |
f7d2323c | 3014 | |
f4249942 | 3015 | intel_pps_backlight_off(intel_dp); |
c0a52f8b | 3016 | intel_backlight_disable(old_conn_state); |
32f9d658 | 3017 | } |
a4fc5ed6 | 3018 | |
857c416e VS |
3019 | static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) |
3020 | { | |
3021 | /* | |
3022 | * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus | |
3023 | * be capable of signalling downstream hpd with a long pulse. | |
3024 | * Whether or not that means D3 is safe to use is not clear, | |
3025 | * but let's assume so until proven otherwise. | |
3026 | * | |
3027 | * FIXME should really check all downstream ports... | |
3028 | */ | |
3029 | return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && | |
b4c32073 | 3030 | drm_dp_is_branch(intel_dp->dpcd) && |
857c416e VS |
3031 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; |
3032 | } | |
3033 | ||
7c4631ff ID |
3034 | static int |
3035 | write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) | |
2279298d | 3036 | { |
7c4631ff ID |
3037 | int err; |
3038 | u8 val; | |
2279298d | 3039 | |
7c4631ff ID |
3040 | err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); |
3041 | if (err < 0) | |
3042 | return err; | |
2279298d | 3043 | |
7c4631ff ID |
3044 | if (set) |
3045 | val |= flag; | |
3046 | else | |
3047 | val &= ~flag; | |
3048 | ||
3049 | return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); | |
3050 | } | |
3051 | ||
3052 | static void | |
3053 | intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, | |
3054 | bool enable) | |
3055 | { | |
3056 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
3057 | ||
3058 | if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, | |
3059 | DP_DECOMPRESSION_EN, enable) < 0) | |
af67009c JN |
3060 | drm_dbg_kms(&i915->drm, |
3061 | "Failed to %s sink decompression state\n", | |
707c3a7d | 3062 | str_enable_disable(enable)); |
2279298d GS |
3063 | } |
3064 | ||
751dbac1 ID |
3065 | static void |
3066 | intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, | |
3067 | bool enable) | |
3068 | { | |
3069 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
3070 | struct drm_dp_aux *aux = connector->port ? | |
3071 | connector->port->passthrough_aux : NULL; | |
3072 | ||
3073 | if (!aux) | |
3074 | return; | |
3075 | ||
3076 | if (write_dsc_decompression_flag(aux, | |
3077 | DP_DSC_PASSTHROUGH_EN, enable) < 0) | |
3078 | drm_dbg_kms(&i915->drm, | |
3079 | "Failed to %s sink compression passthrough state\n", | |
3080 | str_enable_disable(enable)); | |
3081 | } | |
3082 | ||
b2608c6b ID |
3083 | static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, |
3084 | const struct intel_connector *connector, | |
3085 | bool for_get_ref) | |
3086 | { | |
3087 | struct drm_i915_private *i915 = to_i915(state->base.dev); | |
3088 | struct drm_connector *_connector_iter; | |
3089 | struct drm_connector_state *old_conn_state; | |
3090 | struct drm_connector_state *new_conn_state; | |
3091 | int ref_count = 0; | |
3092 | int i; | |
3093 | ||
3094 | /* | |
3095 | * On SST the decompression AUX device won't be shared, each connector | |
3096 | * uses for this its own AUX targeting the sink device. | |
3097 | */ | |
3098 | if (!connector->mst_port) | |
3099 | return connector->dp.dsc_decompression_enabled ? 1 : 0; | |
3100 | ||
3101 | for_each_oldnew_connector_in_state(&state->base, _connector_iter, | |
3102 | old_conn_state, new_conn_state, i) { | |
3103 | const struct intel_connector * | |
3104 | connector_iter = to_intel_connector(_connector_iter); | |
3105 | ||
3106 | if (connector_iter->mst_port != connector->mst_port) | |
3107 | continue; | |
3108 | ||
3109 | if (!connector_iter->dp.dsc_decompression_enabled) | |
3110 | continue; | |
3111 | ||
3112 | drm_WARN_ON(&i915->drm, | |
3113 | (for_get_ref && !new_conn_state->crtc) || | |
3114 | (!for_get_ref && !old_conn_state->crtc)); | |
3115 | ||
3116 | if (connector_iter->dp.dsc_decompression_aux == | |
3117 | connector->dp.dsc_decompression_aux) | |
3118 | ref_count++; | |
3119 | } | |
3120 | ||
3121 | return ref_count; | |
3122 | } | |
3123 | ||
3124 | static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, | |
3125 | struct intel_connector *connector) | |
3126 | { | |
3127 | bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; | |
3128 | ||
3129 | connector->dp.dsc_decompression_enabled = true; | |
3130 | ||
3131 | return ret; | |
3132 | } | |
3133 | ||
3134 | static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, | |
3135 | struct intel_connector *connector) | |
3136 | { | |
3137 | connector->dp.dsc_decompression_enabled = false; | |
3138 | ||
3139 | return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; | |
3140 | } | |
3141 | ||
7c4631ff ID |
3142 | /** |
3143 | * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device | |
3144 | * @state: atomic state | |
3145 | * @connector: connector to enable the decompression for | |
3146 | * @new_crtc_state: new state for the CRTC driving @connector | |
3147 | * | |
3148 | * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD | |
3149 | * register of the appropriate sink/branch device. On SST this is always the | |
3150 | * sink device, whereas on MST based on each device's DSC capabilities it's | |
3151 | * either the last branch device (enabling decompression in it) or both the | |
3152 | * last branch device (enabling passthrough in it) and the sink device | |
3153 | * (enabling decompression in it). | |
3154 | */ | |
3155 | void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, | |
3156 | struct intel_connector *connector, | |
3157 | const struct intel_crtc_state *new_crtc_state) | |
3158 | { | |
3159 | struct drm_i915_private *i915 = to_i915(state->base.dev); | |
3160 | ||
3161 | if (!new_crtc_state->dsc.compression_enable) | |
3162 | return; | |
3163 | ||
3164 | if (drm_WARN_ON(&i915->drm, | |
b2608c6b ID |
3165 | !connector->dp.dsc_decompression_aux || |
3166 | connector->dp.dsc_decompression_enabled)) | |
3167 | return; | |
3168 | ||
3169 | if (!intel_dp_dsc_aux_get_ref(state, connector)) | |
7c4631ff ID |
3170 | return; |
3171 | ||
751dbac1 | 3172 | intel_dp_sink_set_dsc_passthrough(connector, true); |
7c4631ff ID |
3173 | intel_dp_sink_set_dsc_decompression(connector, true); |
3174 | } | |
3175 | ||
3176 | /** | |
3177 | * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device | |
3178 | * @state: atomic state | |
3179 | * @connector: connector to disable the decompression for | |
3180 | * @old_crtc_state: old state for the CRTC driving @connector | |
3181 | * | |
3182 | * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD | |
3183 | * register of the appropriate sink/branch device, corresponding to the | |
3184 | * sequence in intel_dp_sink_enable_decompression(). | |
3185 | */ | |
3186 | void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, | |
3187 | struct intel_connector *connector, | |
3188 | const struct intel_crtc_state *old_crtc_state) | |
3189 | { | |
3190 | struct drm_i915_private *i915 = to_i915(state->base.dev); | |
3191 | ||
3192 | if (!old_crtc_state->dsc.compression_enable) | |
3193 | return; | |
3194 | ||
3195 | if (drm_WARN_ON(&i915->drm, | |
b2608c6b ID |
3196 | !connector->dp.dsc_decompression_aux || |
3197 | !connector->dp.dsc_decompression_enabled)) | |
3198 | return; | |
3199 | ||
3200 | if (!intel_dp_dsc_aux_put_ref(state, connector)) | |
7c4631ff ID |
3201 | return; |
3202 | ||
3203 | intel_dp_sink_set_dsc_decompression(connector, false); | |
751dbac1 | 3204 | intel_dp_sink_set_dsc_passthrough(connector, false); |
7c4631ff ID |
3205 | } |
3206 | ||
f12110af LP |
3207 | static void |
3208 | intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) | |
3209 | { | |
3210 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
3211 | u8 oui[] = { 0x00, 0xaa, 0x01 }; | |
eebc1525 | 3212 | u8 buf[3] = {}; |
f12110af LP |
3213 | |
3214 | /* | |
3215 | * During driver init, we want to be careful and avoid changing the source OUI if it's | |
3216 | * already set to what we want, so as to avoid clearing any state by accident | |
3217 | */ | |
3218 | if (careful) { | |
3219 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) | |
3220 | drm_err(&i915->drm, "Failed to read source OUI\n"); | |
3221 | ||
3222 | if (memcmp(oui, buf, sizeof(oui)) == 0) | |
3223 | return; | |
3224 | } | |
3225 | ||
3226 | if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) | |
3227 | drm_err(&i915->drm, "Failed to write source OUI\n"); | |
c7c90b0b LP |
3228 | |
3229 | intel_dp->last_oui_write = jiffies; | |
3230 | } | |
3231 | ||
3232 | void intel_dp_wait_source_oui(struct intel_dp *intel_dp) | |
3233 | { | |
fe82b93f | 3234 | struct intel_connector *connector = intel_dp->attached_connector; |
c7c90b0b LP |
3235 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
3236 | ||
fe82b93f VS |
3237 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", |
3238 | connector->base.base.id, connector->base.name, | |
3239 | connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); | |
3240 | ||
3241 | wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, | |
3242 | connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); | |
f12110af LP |
3243 | } |
3244 | ||
0e634efd VS |
3245 | /* If the device supports it, try to set the power state appropriately */ |
3246 | void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) | |
c7ad3810 | 3247 | { |
0e634efd VS |
3248 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3249 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
c7ad3810 JB |
3250 | int ret, i; |
3251 | ||
3252 | /* Should have a valid DPCD by this point */ | |
3253 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
3254 | return; | |
3255 | ||
0e634efd | 3256 | if (mode != DP_SET_POWER_D0) { |
857c416e VS |
3257 | if (downstream_hpd_needs_d0(intel_dp)) |
3258 | return; | |
3259 | ||
0e634efd | 3260 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); |
c7ad3810 | 3261 | } else { |
357c0ae9 ID |
3262 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
3263 | ||
0a5a7499 VS |
3264 | lspcon_resume(dp_to_dig_port(intel_dp)); |
3265 | ||
f12110af LP |
3266 | /* Write the source OUI as early as possible */ |
3267 | if (intel_dp_is_edp(intel_dp)) | |
3268 | intel_edp_init_source_oui(intel_dp, false); | |
3269 | ||
c7ad3810 JB |
3270 | /* |
3271 | * When turning on, we need to retry for 1ms to give the sink | |
3272 | * time to wake up. | |
3273 | */ | |
3274 | for (i = 0; i < 3; i++) { | |
0e634efd | 3275 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); |
c7ad3810 JB |
3276 | if (ret == 1) |
3277 | break; | |
3278 | msleep(1); | |
3279 | } | |
357c0ae9 ID |
3280 | |
3281 | if (ret == 1 && lspcon->active) | |
3282 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 3283 | } |
f9cac721 JN |
3284 | |
3285 | if (ret != 1) | |
0e634efd VS |
3286 | drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n", |
3287 | encoder->base.base.id, encoder->base.name, | |
3288 | mode == DP_SET_POWER_D0 ? "D0" : "D3"); | |
c7ad3810 JB |
3289 | } |
3290 | ||
f9e76a6e ID |
3291 | static bool |
3292 | intel_dp_get_dpcd(struct intel_dp *intel_dp); | |
3293 | ||
3294 | /** | |
3295 | * intel_dp_sync_state - sync the encoder state during init/resume | |
3296 | * @encoder: intel encoder to sync | |
3297 | * @crtc_state: state for the CRTC connected to the encoder | |
3298 | * | |
3299 | * Sync any state stored in the encoder wrt. HW state during driver init | |
3300 | * and system resume. | |
3301 | */ | |
3302 | void intel_dp_sync_state(struct intel_encoder *encoder, | |
3303 | const struct intel_crtc_state *crtc_state) | |
3304 | { | |
3305 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
fb687904 | 3306 | bool dpcd_updated = false; |
4ec5ffc3 | 3307 | |
f9e76a6e ID |
3308 | /* |
3309 | * Don't clobber DPCD if it's been already read out during output | |
3310 | * setup (eDP) or detect. | |
3311 | */ | |
fb687904 | 3312 | if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { |
f9e76a6e | 3313 | intel_dp_get_dpcd(intel_dp); |
fb687904 ID |
3314 | dpcd_updated = true; |
3315 | } | |
f9e76a6e | 3316 | |
fb687904 ID |
3317 | intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); |
3318 | ||
3319 | if (crtc_state) | |
3320 | intel_dp_reset_max_link_params(intel_dp); | |
f9e76a6e ID |
3321 | } |
3322 | ||
b671d6ef ID |
3323 | bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, |
3324 | struct intel_crtc_state *crtc_state) | |
3325 | { | |
3326 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
7d6287a8 | 3327 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
fea1beb6 | 3328 | bool fastset = true; |
7d6287a8 ID |
3329 | |
3330 | /* | |
3331 | * If BIOS has set an unsupported or non-standard link rate for some | |
3332 | * reason force an encoder recompute and full modeset. | |
3333 | */ | |
3334 | if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, | |
3335 | crtc_state->port_clock) < 0) { | |
fea1beb6 VS |
3336 | drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", |
3337 | encoder->base.base.id, encoder->base.name); | |
7d6287a8 | 3338 | crtc_state->uapi.connectors_changed = true; |
fea1beb6 | 3339 | fastset = false; |
7d6287a8 | 3340 | } |
b671d6ef ID |
3341 | |
3342 | /* | |
3343 | * FIXME hack to force full modeset when DSC is being used. | |
3344 | * | |
3345 | * As long as we do not have full state readout and config comparison | |
3346 | * of crtc_state->dsc, we have no way to ensure reliable fastset. | |
3347 | * Remove once we have readout for DSC. | |
3348 | */ | |
3349 | if (crtc_state->dsc.compression_enable) { | |
fea1beb6 VS |
3350 | drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", |
3351 | encoder->base.base.id, encoder->base.name); | |
b671d6ef | 3352 | crtc_state->uapi.mode_changed = true; |
fea1beb6 | 3353 | fastset = false; |
b671d6ef ID |
3354 | } |
3355 | ||
fea1beb6 | 3356 | return fastset; |
b671d6ef ID |
3357 | } |
3358 | ||
b9d96dac AN |
3359 | static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) |
3360 | { | |
3361 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
3362 | ||
3363 | /* Clear the cached register set to avoid using stale values */ | |
3364 | ||
3365 | memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); | |
3366 | ||
3367 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, | |
3368 | intel_dp->pcon_dsc_dpcd, | |
3369 | sizeof(intel_dp->pcon_dsc_dpcd)) < 0) | |
3370 | drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", | |
3371 | DP_PCON_DSC_ENCODER); | |
3372 | ||
3373 | drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", | |
3374 | (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); | |
3375 | } | |
3376 | ||
ced42f2d AN |
3377 | static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) |
3378 | { | |
3379 | int bw_gbps[] = {9, 18, 24, 32, 40, 48}; | |
3380 | int i; | |
3381 | ||
3382 | for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { | |
3383 | if (frl_bw_mask & (1 << i)) | |
3384 | return bw_gbps[i]; | |
3385 | } | |
3386 | return 0; | |
3387 | } | |
3388 | ||
3389 | static int intel_dp_pcon_set_frl_mask(int max_frl) | |
3390 | { | |
3391 | switch (max_frl) { | |
3392 | case 48: | |
3393 | return DP_PCON_FRL_BW_MASK_48GBPS; | |
3394 | case 40: | |
3395 | return DP_PCON_FRL_BW_MASK_40GBPS; | |
3396 | case 32: | |
3397 | return DP_PCON_FRL_BW_MASK_32GBPS; | |
3398 | case 24: | |
3399 | return DP_PCON_FRL_BW_MASK_24GBPS; | |
3400 | case 18: | |
3401 | return DP_PCON_FRL_BW_MASK_18GBPS; | |
3402 | case 9: | |
3403 | return DP_PCON_FRL_BW_MASK_9GBPS; | |
3404 | } | |
3405 | ||
3406 | return 0; | |
3407 | } | |
3408 | ||
3409 | static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) | |
3410 | { | |
3411 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
3412 | struct drm_connector *connector = &intel_connector->base; | |
10fec80b AN |
3413 | int max_frl_rate; |
3414 | int max_lanes, rate_per_lane; | |
3415 | int max_dsc_lanes, dsc_rate_per_lane; | |
ced42f2d | 3416 | |
10fec80b AN |
3417 | max_lanes = connector->display_info.hdmi.max_lanes; |
3418 | rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; | |
3419 | max_frl_rate = max_lanes * rate_per_lane; | |
3420 | ||
3421 | if (connector->display_info.hdmi.dsc_cap.v_1p2) { | |
3422 | max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes; | |
3423 | dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane; | |
3424 | if (max_dsc_lanes && dsc_rate_per_lane) | |
3425 | max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); | |
3426 | } | |
3427 | ||
3428 | return max_frl_rate; | |
ced42f2d AN |
3429 | } |
3430 | ||
078e2bb2 AN |
3431 | static bool |
3432 | intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, | |
3433 | u8 max_frl_bw_mask, u8 *frl_trained_mask) | |
3434 | { | |
3435 | if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && | |
3436 | drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && | |
3437 | *frl_trained_mask >= max_frl_bw_mask) | |
3438 | return true; | |
3439 | ||
3440 | return false; | |
3441 | } | |
3442 | ||
ced42f2d AN |
3443 | static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) |
3444 | { | |
ced42f2d AN |
3445 | #define TIMEOUT_FRL_READY_MS 500 |
3446 | #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 | |
3447 | ||
3448 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
3449 | int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; | |
3450 | u8 max_frl_bw_mask = 0, frl_trained_mask; | |
3451 | bool is_active; | |
3452 | ||
ced42f2d AN |
3453 | max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; |
3454 | drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); | |
3455 | ||
3456 | max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); | |
3457 | drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw); | |
3458 | ||
3459 | max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); | |
3460 | ||
3461 | if (max_frl_bw <= 0) | |
3462 | return -EINVAL; | |
3463 | ||
078e2bb2 AN |
3464 | max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); |
3465 | drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); | |
3466 | ||
3467 | if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) | |
3468 | goto frl_trained; | |
3469 | ||
ced42f2d AN |
3470 | ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); |
3471 | if (ret < 0) | |
3472 | return ret; | |
3473 | /* Wait for PCON to be FRL Ready */ | |
3474 | wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); | |
3475 | ||
3476 | if (!is_active) | |
3477 | return -ETIMEDOUT; | |
3478 | ||
68a8c645 AN |
3479 | ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, |
3480 | DP_PCON_ENABLE_SEQUENTIAL_LINK); | |
ced42f2d AN |
3481 | if (ret < 0) |
3482 | return ret; | |
68a8c645 AN |
3483 | ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, |
3484 | DP_PCON_FRL_LINK_TRAIN_NORMAL); | |
ced42f2d AN |
3485 | if (ret < 0) |
3486 | return ret; | |
3487 | ret = drm_dp_pcon_frl_enable(&intel_dp->aux); | |
3488 | if (ret < 0) | |
3489 | return ret; | |
3490 | /* | |
3491 | * Wait for FRL to be completed | |
3492 | * Check if the HDMI Link is up and active. | |
3493 | */ | |
078e2bb2 AN |
3494 | wait_for(is_active = |
3495 | intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), | |
3496 | TIMEOUT_HDMI_LINK_ACTIVE_MS); | |
ced42f2d AN |
3497 | |
3498 | if (!is_active) | |
3499 | return -ETIMEDOUT; | |
3500 | ||
078e2bb2 AN |
3501 | frl_trained: |
3502 | drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); | |
ced42f2d AN |
3503 | intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); |
3504 | intel_dp->frl.is_trained = true; | |
3505 | drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps); | |
3506 | ||
3507 | return 0; | |
3508 | } | |
3509 | ||
3510 | static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) | |
3511 | { | |
3512 | if (drm_dp_is_branch(intel_dp->dpcd) && | |
7ffa2f27 | 3513 | intel_dp_has_hdmi_sink(intel_dp) && |
ced42f2d AN |
3514 | intel_dp_hdmi_sink_max_frl(intel_dp) > 0) |
3515 | return true; | |
3516 | ||
3517 | return false; | |
3518 | } | |
3519 | ||
f35294e1 AN |
3520 | static |
3521 | int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) | |
3522 | { | |
3523 | int ret; | |
3524 | u8 buf = 0; | |
3525 | ||
3526 | /* Set PCON source control mode */ | |
3527 | buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; | |
3528 | ||
3529 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); | |
3530 | if (ret < 0) | |
3531 | return ret; | |
3532 | ||
3533 | /* Set HDMI LINK ENABLE */ | |
3534 | buf |= DP_PCON_ENABLE_HDMI_LINK; | |
3535 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); | |
3536 | if (ret < 0) | |
3537 | return ret; | |
3538 | ||
3539 | return 0; | |
3540 | } | |
3541 | ||
ced42f2d AN |
3542 | void intel_dp_check_frl_training(struct intel_dp *intel_dp) |
3543 | { | |
3544 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); | |
3545 | ||
04b6603d AN |
3546 | /* |
3547 | * Always go for FRL training if: | |
3548 | * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) | |
3549 | * -sink is HDMI2.1 | |
3550 | */ | |
88a9c548 | 3551 | if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || |
04b6603d | 3552 | !intel_dp_is_hdmi_2_1_sink(intel_dp) || |
ced42f2d AN |
3553 | intel_dp->frl.is_trained) |
3554 | return; | |
3555 | ||
3556 | if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { | |
3557 | int ret, mode; | |
3558 | ||
58a92bce | 3559 | drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n"); |
f35294e1 | 3560 | ret = intel_dp_pcon_set_tmds_mode(intel_dp); |
ced42f2d AN |
3561 | mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); |
3562 | ||
3563 | if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) | |
3564 | drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n"); | |
3565 | } else { | |
3566 | drm_dbg(&dev_priv->drm, "FRL training Completed\n"); | |
3567 | } | |
3568 | } | |
3569 | ||
10fec80b AN |
3570 | static int |
3571 | intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) | |
3572 | { | |
3573 | int vactive = crtc_state->hw.adjusted_mode.vdisplay; | |
3574 | ||
3575 | return intel_hdmi_dsc_get_slice_height(vactive); | |
3576 | } | |
3577 | ||
3578 | static int | |
3579 | intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, | |
3580 | const struct intel_crtc_state *crtc_state) | |
3581 | { | |
3582 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
3583 | struct drm_connector *connector = &intel_connector->base; | |
3584 | int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice; | |
3585 | int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; | |
3586 | int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); | |
3587 | int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); | |
3588 | ||
3589 | return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, | |
3590 | pcon_max_slice_width, | |
3591 | hdmi_max_slices, hdmi_throughput); | |
3592 | } | |
3593 | ||
3594 | static int | |
3595 | intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, | |
3596 | const struct intel_crtc_state *crtc_state, | |
3597 | int num_slices, int slice_width) | |
3598 | { | |
3599 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
3600 | struct drm_connector *connector = &intel_connector->base; | |
3601 | int output_format = crtc_state->output_format; | |
3602 | bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; | |
3603 | int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); | |
3604 | int hdmi_max_chunk_bytes = | |
3605 | connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024; | |
917c2899 VS |
3606 | |
3607 | return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, | |
3608 | num_slices, output_format, hdmi_all_bpp, | |
3609 | hdmi_max_chunk_bytes); | |
e3421a18 ZW |
3610 | } |
3611 | ||
917c2899 VS |
3612 | void |
3613 | intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, | |
3614 | const struct intel_crtc_state *crtc_state) | |
fb83f72c | 3615 | { |
917c2899 VS |
3616 | u8 pps_param[6]; |
3617 | int slice_height; | |
3618 | int slice_width; | |
3619 | int num_slices; | |
3620 | int bits_per_pixel; | |
3621 | int ret; | |
3622 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
3623 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
3624 | struct drm_connector *connector; | |
3625 | bool hdmi_is_dsc_1_2; | |
fb83f72c | 3626 | |
917c2899 VS |
3627 | if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) |
3628 | return; | |
fb83f72c | 3629 | |
917c2899 VS |
3630 | if (!intel_connector) |
3631 | return; | |
3632 | connector = &intel_connector->base; | |
3633 | hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; | |
fb83f72c | 3634 | |
917c2899 VS |
3635 | if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || |
3636 | !hdmi_is_dsc_1_2) | |
3637 | return; | |
fb83f72c | 3638 | |
917c2899 VS |
3639 | slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); |
3640 | if (!slice_height) | |
3641 | return; | |
fb83f72c | 3642 | |
917c2899 VS |
3643 | num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); |
3644 | if (!num_slices) | |
3645 | return; | |
fb83f72c | 3646 | |
917c2899 VS |
3647 | slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, |
3648 | num_slices); | |
1a2eb460 | 3649 | |
917c2899 VS |
3650 | bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, |
3651 | num_slices, slice_width); | |
3652 | if (!bits_per_pixel) | |
3653 | return; | |
1a2eb460 | 3654 | |
917c2899 VS |
3655 | pps_param[0] = slice_height & 0xFF; |
3656 | pps_param[1] = slice_height >> 8; | |
3657 | pps_param[2] = slice_width & 0xFF; | |
3658 | pps_param[3] = slice_width >> 8; | |
3659 | pps_param[4] = bits_per_pixel & 0xFF; | |
3660 | pps_param[5] = (bits_per_pixel >> 8) & 0x3; | |
1a2eb460 | 3661 | |
917c2899 VS |
3662 | ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); |
3663 | if (ret < 0) | |
3664 | drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); | |
1a2eb460 KP |
3665 | } |
3666 | ||
917c2899 VS |
3667 | void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, |
3668 | const struct intel_crtc_state *crtc_state) | |
f0a3424e | 3669 | { |
917c2899 | 3670 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
68910c2a AN |
3671 | bool ycbcr444_to_420 = false; |
3672 | bool rgb_to_ycbcr = false; | |
917c2899 | 3673 | u8 tmp; |
fb83f72c | 3674 | |
917c2899 VS |
3675 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) |
3676 | return; | |
f0a3424e | 3677 | |
917c2899 VS |
3678 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
3679 | return; | |
fb83f72c | 3680 | |
7ffa2f27 | 3681 | tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; |
a4fc5ed6 | 3682 | |
917c2899 VS |
3683 | if (drm_dp_dpcd_writeb(&intel_dp->aux, |
3684 | DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) | |
3a11529d | 3685 | drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", |
7ffa2f27 | 3686 | str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); |
1b39d6f3 | 3687 | |
68910c2a AN |
3688 | if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { |
3689 | switch (crtc_state->output_format) { | |
3690 | case INTEL_OUTPUT_FORMAT_YCBCR420: | |
3691 | break; | |
3692 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
3693 | ycbcr444_to_420 = true; | |
3694 | break; | |
3695 | case INTEL_OUTPUT_FORMAT_RGB: | |
3696 | rgb_to_ycbcr = true; | |
3697 | ycbcr444_to_420 = true; | |
3698 | break; | |
3699 | default: | |
3700 | MISSING_CASE(crtc_state->output_format); | |
3701 | break; | |
3702 | } | |
9cca0fe3 AN |
3703 | } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { |
3704 | switch (crtc_state->output_format) { | |
3705 | case INTEL_OUTPUT_FORMAT_YCBCR444: | |
3706 | break; | |
3707 | case INTEL_OUTPUT_FORMAT_RGB: | |
3708 | rgb_to_ycbcr = true; | |
3709 | break; | |
3710 | default: | |
3711 | MISSING_CASE(crtc_state->output_format); | |
3712 | break; | |
3713 | } | |
68910c2a AN |
3714 | } |
3715 | ||
3716 | tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; | |
32f9d658 | 3717 | |
917c2899 VS |
3718 | if (drm_dp_dpcd_writeb(&intel_dp->aux, |
3719 | DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) | |
3720 | drm_dbg_kms(&i915->drm, | |
3a11529d | 3721 | "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", |
707c3a7d | 3722 | str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); |
5eb08b69 | 3723 | |
68910c2a | 3724 | tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; |
5bddd17f | 3725 | |
917c2899 VS |
3726 | if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) |
3727 | drm_dbg_kms(&i915->drm, | |
68910c2a AN |
3728 | "Failed to %s protocol converter RGB->YCbCr conversion mode\n", |
3729 | str_enable_disable(tmp)); | |
a4fc5ed6 KP |
3730 | } |
3731 | ||
8e9d645c GM |
3732 | bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
3733 | { | |
3734 | u8 dprx = 0; | |
3735 | ||
3736 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
3737 | &dprx) != 1) | |
3738 | return false; | |
3739 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
3740 | } | |
3741 | ||
90780a63 ID |
3742 | static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, |
3743 | u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) | |
3744 | { | |
3745 | if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, | |
3746 | DP_DSC_RECEIVER_CAP_SIZE) < 0) { | |
3747 | drm_err(aux->drm_dev, | |
3748 | "Failed to read DPCD register 0x%x\n", | |
3749 | DP_DSC_SUPPORT); | |
3750 | return; | |
3751 | } | |
3752 | ||
3753 | drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", | |
3754 | DP_DSC_RECEIVER_CAP_SIZE, | |
3755 | dsc_dpcd); | |
3756 | } | |
3757 | ||
02c8d561 | 3758 | void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) |
93ac092f | 3759 | { |
02c8d561 | 3760 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
af67009c | 3761 | |
93ac092f MN |
3762 | /* |
3763 | * Clear the cached register set to avoid using stale values | |
3764 | * for the sinks that do not support DSC. | |
3765 | */ | |
7389829f | 3766 | memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); |
93ac092f | 3767 | |
08cadae8 | 3768 | /* Clear fec_capable to avoid using stale values */ |
7389829f | 3769 | connector->dp.fec_capability = 0; |
08cadae8 | 3770 | |
90780a63 ID |
3771 | if (dpcd_rev < DP_DPCD_REV_14) |
3772 | return; | |
3773 | ||
7389829f ID |
3774 | intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, |
3775 | connector->dp.dsc_dpcd); | |
90780a63 | 3776 | |
7389829f ID |
3777 | if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, |
3778 | &connector->dp.fec_capability) < 0) { | |
90780a63 ID |
3779 | drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); |
3780 | return; | |
93ac092f | 3781 | } |
90780a63 ID |
3782 | |
3783 | drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", | |
7389829f | 3784 | connector->dp.fec_capability); |
90780a63 ID |
3785 | } |
3786 | ||
02c8d561 | 3787 | static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) |
90780a63 ID |
3788 | { |
3789 | if (edp_dpcd_rev < DP_EDP_14) | |
3790 | return; | |
3791 | ||
7389829f | 3792 | intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); |
93ac092f MN |
3793 | } |
3794 | ||
512005d9 JN |
3795 | static void intel_edp_mso_mode_fixup(struct intel_connector *connector, |
3796 | struct drm_display_mode *mode) | |
3797 | { | |
3798 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
3799 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
3800 | int n = intel_dp->mso_link_count; | |
3801 | int overlap = intel_dp->mso_pixel_overlap; | |
3802 | ||
3803 | if (!mode || !n) | |
3804 | return; | |
3805 | ||
3806 | mode->hdisplay = (mode->hdisplay - overlap) * n; | |
3807 | mode->hsync_start = (mode->hsync_start - overlap) * n; | |
3808 | mode->hsync_end = (mode->hsync_end - overlap) * n; | |
3809 | mode->htotal = (mode->htotal - overlap) * n; | |
3810 | mode->clock *= n; | |
3811 | ||
3812 | drm_mode_set_name(mode); | |
3813 | ||
3814 | drm_dbg_kms(&i915->drm, | |
f01bae2d VS |
3815 | "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", |
3816 | connector->base.base.id, connector->base.name, | |
3817 | DRM_MODE_ARG(mode)); | |
512005d9 JN |
3818 | } |
3819 | ||
822e5ae7 VS |
3820 | void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) |
3821 | { | |
3822 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
3cf05076 VS |
3823 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
3824 | struct intel_connector *connector = intel_dp->attached_connector; | |
822e5ae7 | 3825 | |
3cf05076 | 3826 | if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { |
822e5ae7 VS |
3827 | /* |
3828 | * This is a big fat ugly hack. | |
3829 | * | |
3830 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
3831 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
3832 | * unknown we fail to light up. Yet the same BIOS boots up with | |
3833 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
3834 | * max, not what it tells us to use. | |
3835 | * | |
3836 | * Note: This will still be broken if the eDP panel is not lit | |
3837 | * up by the BIOS, and thus we can't get the mode at module | |
3838 | * load. | |
3839 | */ | |
3840 | drm_dbg_kms(&dev_priv->drm, | |
3841 | "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
3cf05076 VS |
3842 | pipe_bpp, connector->panel.vbt.edp.bpp); |
3843 | connector->panel.vbt.edp.bpp = pipe_bpp; | |
822e5ae7 VS |
3844 | } |
3845 | } | |
3846 | ||
de46dbe4 JN |
3847 | static void intel_edp_mso_init(struct intel_dp *intel_dp) |
3848 | { | |
3849 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
185667c2 JN |
3850 | struct intel_connector *connector = intel_dp->attached_connector; |
3851 | struct drm_display_info *info = &connector->base.display_info; | |
de46dbe4 JN |
3852 | u8 mso; |
3853 | ||
3854 | if (intel_dp->edp_dpcd[0] < DP_EDP_14) | |
3855 | return; | |
3856 | ||
3857 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { | |
3858 | drm_err(&i915->drm, "Failed to read MSO cap\n"); | |
3859 | return; | |
3860 | } | |
3861 | ||
3862 | /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ | |
3863 | mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; | |
3864 | if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { | |
3865 | drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); | |
3866 | mso = 0; | |
3867 | } | |
3868 | ||
3869 | if (mso) { | |
185667c2 JN |
3870 | drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n", |
3871 | mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, | |
3872 | info->mso_pixel_overlap); | |
bc71194e JN |
3873 | if (!HAS_MSO(i915)) { |
3874 | drm_err(&i915->drm, "No source MSO support, disabling\n"); | |
3875 | mso = 0; | |
3876 | } | |
de46dbe4 JN |
3877 | } |
3878 | ||
3879 | intel_dp->mso_link_count = mso; | |
185667c2 | 3880 | intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; |
de46dbe4 JN |
3881 | } |
3882 | ||
fe5a66f9 | 3883 | static bool |
7389829f | 3884 | intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) |
fe5a66f9 VS |
3885 | { |
3886 | struct drm_i915_private *dev_priv = | |
3887 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3888 | |
fe5a66f9 | 3889 | /* this function is meant to be called only once */ |
eb020ca3 | 3890 | drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); |
30d9aa42 | 3891 | |
b9936121 | 3892 | if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) |
30d9aa42 SS |
3893 | return false; |
3894 | ||
84c36753 JN |
3895 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
3896 | drm_dp_is_branch(intel_dp->dpcd)); | |
12a47a42 | 3897 | |
7c838e2a JN |
3898 | /* |
3899 | * Read the eDP display control registers. | |
3900 | * | |
3901 | * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in | |
3902 | * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it | |
3903 | * set, but require eDP 1.4+ detection (e.g. for supported link rates | |
3904 | * method). The display control registers should read zero if they're | |
3905 | * not supported anyway. | |
3906 | */ | |
3907 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e | 3908 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
d7f213c1 | 3909 | sizeof(intel_dp->edp_dpcd)) { |
bdc6114e WK |
3910 | drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", |
3911 | (int)sizeof(intel_dp->edp_dpcd), | |
3912 | intel_dp->edp_dpcd); | |
06ea66b6 | 3913 | |
d7f213c1 KHF |
3914 | intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; |
3915 | } | |
3916 | ||
84bb2916 DP |
3917 | /* |
3918 | * This has to be called after intel_dp->edp_dpcd is filled, PSR checks | |
3919 | * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] | |
3920 | */ | |
3921 | intel_psr_init_dpcd(intel_dp); | |
3922 | ||
3f61ef97 ID |
3923 | /* Clear the default sink rates */ |
3924 | intel_dp->num_sink_rates = 0; | |
3925 | ||
e6ed2a1b JN |
3926 | /* Read the eDP 1.4+ supported link rates. */ |
3927 | if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
94ca719e | 3928 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3929 | int i; |
3930 | ||
9f085ebb L |
3931 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3932 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3933 | |
94ca719e VS |
3934 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3935 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3936 | |
3937 | if (val == 0) | |
3938 | break; | |
3939 | ||
fd81c44e DP |
3940 | /* Value read multiplied by 200kHz gives the per-lane |
3941 | * link rate in kHz. The source rates are, however, | |
3942 | * stored in terms of LS_Clk kHz. The full conversion | |
3943 | * back to symbols is | |
3944 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
3945 | */ | |
af77b974 | 3946 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 3947 | } |
94ca719e | 3948 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3949 | } |
0336400e | 3950 | |
e6ed2a1b JN |
3951 | /* |
3952 | * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, | |
3953 | * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. | |
3954 | */ | |
68f357cb JN |
3955 | if (intel_dp->num_sink_rates) |
3956 | intel_dp->use_rate_select = true; | |
3957 | else | |
3958 | intel_dp_set_sink_rates(intel_dp); | |
bedcadda | 3959 | intel_dp_set_max_sink_lane_count(intel_dp); |
68f357cb | 3960 | |
93ac092f | 3961 | /* Read the eDP DSC DPCD registers */ |
8f5c2f6e | 3962 | if (HAS_DSC(dev_priv)) |
90780a63 | 3963 | intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], |
7389829f | 3964 | connector); |
93ac092f | 3965 | |
f12110af LP |
3966 | /* |
3967 | * If needed, program our source OUI so we can make various Intel-specific AUX services | |
3968 | * available (such as HDR backlight controls) | |
3969 | */ | |
3970 | intel_edp_init_source_oui(intel_dp, true); | |
3971 | ||
fe5a66f9 VS |
3972 | return true; |
3973 | } | |
3974 | ||
693c3ec5 LP |
3975 | static bool |
3976 | intel_dp_has_sink_count(struct intel_dp *intel_dp) | |
3977 | { | |
3978 | if (!intel_dp->attached_connector) | |
3979 | return false; | |
3980 | ||
3981 | return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, | |
3982 | intel_dp->dpcd, | |
3983 | &intel_dp->desc); | |
3984 | } | |
fe5a66f9 | 3985 | |
85e5be68 ID |
3986 | void intel_dp_update_sink_caps(struct intel_dp *intel_dp) |
3987 | { | |
3988 | intel_dp_set_sink_rates(intel_dp); | |
3989 | intel_dp_set_max_sink_lane_count(intel_dp); | |
3990 | intel_dp_set_common_rates(intel_dp); | |
3991 | } | |
3992 | ||
fe5a66f9 VS |
3993 | static bool |
3994 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3995 | { | |
4778ff05 LP |
3996 | int ret; |
3997 | ||
264613b4 | 3998 | if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) |
fe5a66f9 VS |
3999 | return false; |
4000 | ||
eaa2b31b VS |
4001 | /* |
4002 | * Don't clobber cached eDP rates. Also skip re-reading | |
4003 | * the OUI/ID since we know it won't change. | |
4004 | */ | |
1853a9da | 4005 | if (!intel_dp_is_edp(intel_dp)) { |
eaa2b31b VS |
4006 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4007 | drm_dp_is_branch(intel_dp->dpcd)); | |
4008 | ||
85e5be68 | 4009 | intel_dp_update_sink_caps(intel_dp); |
975ee5fc | 4010 | } |
68f357cb | 4011 | |
693c3ec5 | 4012 | if (intel_dp_has_sink_count(intel_dp)) { |
4778ff05 LP |
4013 | ret = drm_dp_read_sink_count(&intel_dp->aux); |
4014 | if (ret < 0) | |
2bb06265 JRS |
4015 | return false; |
4016 | ||
4017 | /* | |
4018 | * Sink count can change between short pulse hpd hence | |
4019 | * a member variable in intel_dp will track any changes | |
4020 | * between short pulse interrupts. | |
4021 | */ | |
4778ff05 | 4022 | intel_dp->sink_count = ret; |
2bb06265 JRS |
4023 | |
4024 | /* | |
4025 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
4026 | * a dongle is present but no display. Unless we require to know | |
4027 | * if a dongle is present or not, we don't need to update | |
4028 | * downstream port information. So, an early return here saves | |
4029 | * time from performing other operations which are not required. | |
4030 | */ | |
4031 | if (!intel_dp->sink_count) | |
4032 | return false; | |
4033 | } | |
0336400e | 4034 | |
3d3721cc LP |
4035 | return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, |
4036 | intel_dp->downstream_ports) == 0; | |
c4e3170a VS |
4037 | } |
4038 | ||
20fbb14b JN |
4039 | static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) |
4040 | { | |
4041 | if (mst_mode == DRM_DP_MST) | |
4042 | return "MST"; | |
4043 | else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) | |
4044 | return "SST w/ sideband messaging"; | |
4045 | else | |
4046 | return "SST"; | |
4047 | } | |
4048 | ||
d4e16b8b JN |
4049 | static enum drm_dp_mst_mode |
4050 | intel_dp_mst_mode_choose(struct intel_dp *intel_dp, | |
4051 | enum drm_dp_mst_mode sink_mst_mode) | |
4052 | { | |
4053 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
4054 | ||
4055 | if (!i915->display.params.enable_dp_mst) | |
4056 | return DRM_DP_SST; | |
4057 | ||
4058 | if (!intel_dp_mst_source_support(intel_dp)) | |
4059 | return DRM_DP_SST; | |
4060 | ||
4c8d5562 JN |
4061 | if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && |
4062 | !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) | |
d4e16b8b JN |
4063 | return DRM_DP_SST; |
4064 | ||
4065 | return sink_mst_mode; | |
4066 | } | |
4067 | ||
20fbb14b JN |
4068 | static enum drm_dp_mst_mode |
4069 | intel_dp_mst_detect(struct intel_dp *intel_dp) | |
9dbf5a4e | 4070 | { |
8a25c4be | 4071 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
20fbb14b JN |
4072 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
4073 | enum drm_dp_mst_mode sink_mst_mode; | |
4074 | enum drm_dp_mst_mode mst_detect; | |
4075 | ||
4076 | sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); | |
4077 | ||
d4e16b8b | 4078 | mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); |
8a25c4be | 4079 | |
20fbb14b JN |
4080 | drm_dbg_kms(&i915->drm, |
4081 | "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", | |
4082 | encoder->base.base.id, encoder->base.name, | |
4083 | str_yes_no(intel_dp_mst_source_support(intel_dp)), | |
4084 | intel_dp_mst_mode_str(sink_mst_mode), | |
4085 | str_yes_no(i915->display.params.enable_dp_mst), | |
4086 | intel_dp_mst_mode_str(mst_detect)); | |
4087 | ||
4088 | return mst_detect; | |
9dbf5a4e VS |
4089 | } |
4090 | ||
c4e3170a | 4091 | static void |
2e9720e9 | 4092 | intel_dp_mst_configure(struct intel_dp *intel_dp) |
c4e3170a | 4093 | { |
a94a6d76 | 4094 | if (!intel_dp_mst_source_support(intel_dp)) |
c4e3170a VS |
4095 | return; |
4096 | ||
2e9720e9 | 4097 | intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; |
c4e3170a | 4098 | |
2e9720e9 JN |
4099 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); |
4100 | ||
4101 | /* Avoid stale info on the next detect cycle. */ | |
4102 | intel_dp->mst_detect = DRM_DP_SST; | |
0e32b39c DA |
4103 | } |
4104 | ||
0a31ed64 JN |
4105 | static void |
4106 | intel_dp_mst_disconnect(struct intel_dp *intel_dp) | |
4107 | { | |
4108 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
4109 | ||
4110 | if (!intel_dp->is_mst) | |
4111 | return; | |
4112 | ||
4113 | drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n", | |
4114 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4115 | intel_dp->is_mst = false; | |
4116 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4117 | } | |
4118 | ||
0e32b39c | 4119 | static bool |
1d50942d | 4120 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) |
0e32b39c | 4121 | { |
1d50942d | 4122 | return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; |
0e32b39c DA |
4123 | } |
4124 | ||
603801d0 JN |
4125 | static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) |
4126 | { | |
4127 | int retry; | |
4128 | ||
4129 | for (retry = 0; retry < 3; retry++) { | |
4130 | if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, | |
4131 | &esi[1], 3) == 3) | |
4132 | return true; | |
4133 | } | |
4134 | ||
4135 | return false; | |
4136 | } | |
4137 | ||
0c06fa15 GM |
4138 | bool |
4139 | intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, | |
4140 | const struct drm_connector_state *conn_state) | |
4141 | { | |
4142 | /* | |
4143 | * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication | |
4144 | * of Color Encoding Format and Content Color Gamut], in order to | |
4145 | * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. | |
4146 | */ | |
4147 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
4148 | return true; | |
4149 | ||
4150 | switch (conn_state->colorspace) { | |
4151 | case DRM_MODE_COLORIMETRY_SYCC_601: | |
4152 | case DRM_MODE_COLORIMETRY_OPYCC_601: | |
4153 | case DRM_MODE_COLORIMETRY_BT2020_YCC: | |
4154 | case DRM_MODE_COLORIMETRY_BT2020_RGB: | |
4155 | case DRM_MODE_COLORIMETRY_BT2020_CYCC: | |
4156 | return true; | |
4157 | default: | |
4158 | break; | |
4159 | } | |
4160 | ||
4161 | return false; | |
4162 | } | |
4163 | ||
03c761b0 GM |
4164 | static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, |
4165 | struct dp_sdp *sdp, size_t size) | |
4166 | { | |
4167 | size_t length = sizeof(struct dp_sdp); | |
4168 | ||
4169 | if (size < length) | |
4170 | return -ENOSPC; | |
4171 | ||
4172 | memset(sdp, 0, size); | |
4173 | ||
4174 | /* | |
4175 | * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 | |
4176 | * VSC SDP Header Bytes | |
4177 | */ | |
4178 | sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ | |
4179 | sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ | |
4180 | sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ | |
4181 | sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ | |
4182 | ||
b8cf5b5d AM |
4183 | if (vsc->revision == 0x6) { |
4184 | sdp->db[0] = 1; | |
4185 | sdp->db[3] = 1; | |
4186 | } | |
4187 | ||
cafac5a9 | 4188 | /* |
b8cf5b5d AM |
4189 | * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry |
4190 | * Format as per DP 1.4a spec and DP 2.0 respectively. | |
cafac5a9 | 4191 | */ |
b8cf5b5d | 4192 | if (!(vsc->revision == 0x5 || vsc->revision == 0x7)) |
cafac5a9 GM |
4193 | goto out; |
4194 | ||
03c761b0 GM |
4195 | /* VSC SDP Payload for DB16 through DB18 */ |
4196 | /* Pixel Encoding and Colorimetry Formats */ | |
4197 | sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ | |
4198 | sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ | |
4199 | ||
4200 | switch (vsc->bpc) { | |
4201 | case 6: | |
4202 | /* 6bpc: 0x0 */ | |
4203 | break; | |
4204 | case 8: | |
4205 | sdp->db[17] = 0x1; /* DB17[3:0] */ | |
4206 | break; | |
4207 | case 10: | |
4208 | sdp->db[17] = 0x2; | |
4209 | break; | |
4210 | case 12: | |
4211 | sdp->db[17] = 0x3; | |
4212 | break; | |
4213 | case 16: | |
4214 | sdp->db[17] = 0x4; | |
4215 | break; | |
4216 | default: | |
4217 | MISSING_CASE(vsc->bpc); | |
4218 | break; | |
4219 | } | |
4220 | /* Dynamic Range and Component Bit Depth */ | |
4221 | if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) | |
4222 | sdp->db[17] |= 0x80; /* DB17[7] */ | |
4223 | ||
4224 | /* Content Type */ | |
4225 | sdp->db[18] = vsc->content_type & 0x7; | |
4226 | ||
cafac5a9 | 4227 | out: |
03c761b0 GM |
4228 | return length; |
4229 | } | |
4230 | ||
4231 | static ssize_t | |
9d0bfa7a JN |
4232 | intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915, |
4233 | const struct hdmi_drm_infoframe *drm_infoframe, | |
03c761b0 GM |
4234 | struct dp_sdp *sdp, |
4235 | size_t size) | |
4236 | { | |
4237 | size_t length = sizeof(struct dp_sdp); | |
4238 | const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; | |
4239 | unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; | |
4240 | ssize_t len; | |
4241 | ||
4242 | if (size < length) | |
4243 | return -ENOSPC; | |
4244 | ||
4245 | memset(sdp, 0, size); | |
4246 | ||
4247 | len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); | |
4248 | if (len < 0) { | |
9d0bfa7a | 4249 | drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n"); |
03c761b0 GM |
4250 | return -ENOSPC; |
4251 | } | |
4252 | ||
4253 | if (len != infoframe_size) { | |
9d0bfa7a | 4254 | drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n"); |
03c761b0 GM |
4255 | return -ENOSPC; |
4256 | } | |
4257 | ||
4258 | /* | |
4259 | * Set up the infoframe sdp packet for HDR static metadata. | |
4260 | * Prepare VSC Header for SU as per DP 1.4a spec, | |
4261 | * Table 2-100 and Table 2-101 | |
4262 | */ | |
4263 | ||
4264 | /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ | |
4265 | sdp->sdp_header.HB0 = 0; | |
4266 | /* | |
4267 | * Packet Type 80h + Non-audio INFOFRAME Type value | |
4268 | * HDMI_INFOFRAME_TYPE_DRM: 0x87 | |
4269 | * - 80h + Non-audio INFOFRAME Type value | |
4270 | * - InfoFrame Type: 0x07 | |
4271 | * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] | |
4272 | */ | |
4273 | sdp->sdp_header.HB1 = drm_infoframe->type; | |
4274 | /* | |
4275 | * Least Significant Eight Bits of (Data Byte Count – 1) | |
4276 | * infoframe_size - 1 | |
4277 | */ | |
4278 | sdp->sdp_header.HB2 = 0x1D; | |
4279 | /* INFOFRAME SDP Version Number */ | |
4280 | sdp->sdp_header.HB3 = (0x13 << 2); | |
4281 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ | |
4282 | sdp->db[0] = drm_infoframe->version; | |
4283 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ | |
4284 | sdp->db[1] = drm_infoframe->length; | |
4285 | /* | |
4286 | * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after | |
4287 | * HDMI_INFOFRAME_HEADER_SIZE | |
4288 | */ | |
4289 | BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); | |
4290 | memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], | |
4291 | HDMI_DRM_INFOFRAME_SIZE); | |
4292 | ||
4293 | /* | |
4294 | * Size of DP infoframe sdp packet for HDR static metadata consists of | |
4295 | * - DP SDP Header(struct dp_sdp_header): 4 bytes | |
4296 | * - Two Data Blocks: 2 bytes | |
4297 | * CTA Header Byte2 (INFOFRAME Version Number) | |
4298 | * CTA Header Byte3 (Length of INFOFRAME) | |
4299 | * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes | |
4300 | * | |
4301 | * Prior to GEN11's GMP register size is identical to DP HDR static metadata | |
4302 | * infoframe size. But GEN11+ has larger than that size, write_infoframe | |
4303 | * will pad rest of the size. | |
4304 | */ | |
4305 | return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; | |
4306 | } | |
4307 | ||
4308 | static void intel_write_dp_sdp(struct intel_encoder *encoder, | |
4309 | const struct intel_crtc_state *crtc_state, | |
4310 | unsigned int type) | |
4311 | { | |
7801f3b7 | 4312 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
03c761b0 GM |
4313 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4314 | struct dp_sdp sdp = {}; | |
4315 | ssize_t len; | |
4316 | ||
4317 | if ((crtc_state->infoframes.enable & | |
4318 | intel_hdmi_infoframe_enable(type)) == 0) | |
4319 | return; | |
4320 | ||
4321 | switch (type) { | |
4322 | case DP_SDP_VSC: | |
4323 | len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, | |
4324 | sizeof(sdp)); | |
4325 | break; | |
4326 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
9d0bfa7a JN |
4327 | len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv, |
4328 | &crtc_state->infoframes.drm.drm, | |
03c761b0 GM |
4329 | &sdp, sizeof(sdp)); |
4330 | break; | |
4331 | default: | |
4332 | MISSING_CASE(type); | |
d121f63c | 4333 | return; |
03c761b0 GM |
4334 | } |
4335 | ||
4336 | if (drm_WARN_ON(&dev_priv->drm, len < 0)) | |
4337 | return; | |
4338 | ||
7801f3b7 | 4339 | dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); |
03c761b0 GM |
4340 | } |
4341 | ||
4342 | void intel_dp_set_infoframes(struct intel_encoder *encoder, | |
4343 | bool enable, | |
4344 | const struct intel_crtc_state *crtc_state, | |
4345 | const struct drm_connector_state *conn_state) | |
4346 | { | |
4347 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
03c761b0 GM |
4348 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
4349 | u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | | |
4350 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | | |
4351 | VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; | |
62e37c44 | 4352 | u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; |
03c761b0 | 4353 | |
aaa80e75 ID |
4354 | /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ |
4355 | if (!enable && HAS_DSC(dev_priv)) | |
4356 | val &= ~VDIP_ENABLE_PPS; | |
4357 | ||
03c761b0 | 4358 | /* When PSR is enabled, this routine doesn't disable VSC DIP */ |
62e37c44 JRS |
4359 | if (!crtc_state->has_psr) |
4360 | val &= ~VIDEO_DIP_ENABLE_VSC_HSW; | |
03c761b0 GM |
4361 | |
4362 | intel_de_write(dev_priv, reg, val); | |
4363 | intel_de_posting_read(dev_priv, reg); | |
4364 | ||
62e37c44 JRS |
4365 | if (!enable) |
4366 | return; | |
4367 | ||
31a5b6ed | 4368 | intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); |
03c761b0 GM |
4369 | |
4370 | intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); | |
4371 | } | |
4372 | ||
1b404b7d GM |
4373 | static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, |
4374 | const void *buffer, size_t size) | |
4375 | { | |
4376 | const struct dp_sdp *sdp = buffer; | |
4377 | ||
4378 | if (size < sizeof(struct dp_sdp)) | |
4379 | return -EINVAL; | |
4380 | ||
c88e2647 | 4381 | memset(vsc, 0, sizeof(*vsc)); |
1b404b7d GM |
4382 | |
4383 | if (sdp->sdp_header.HB0 != 0) | |
4384 | return -EINVAL; | |
4385 | ||
4386 | if (sdp->sdp_header.HB1 != DP_SDP_VSC) | |
4387 | return -EINVAL; | |
4388 | ||
4389 | vsc->sdp_type = sdp->sdp_header.HB1; | |
4390 | vsc->revision = sdp->sdp_header.HB2; | |
4391 | vsc->length = sdp->sdp_header.HB3; | |
4392 | ||
4393 | if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || | |
4394 | (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { | |
4395 | /* | |
4396 | * - HB2 = 0x2, HB3 = 0x8 | |
4397 | * VSC SDP supporting 3D stereo + PSR | |
4398 | * - HB2 = 0x4, HB3 = 0xe | |
4399 | * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of | |
4400 | * first scan line of the SU region (applies to eDP v1.4b | |
4401 | * and higher). | |
4402 | */ | |
4403 | return 0; | |
4404 | } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { | |
4405 | /* | |
4406 | * - HB2 = 0x5, HB3 = 0x13 | |
4407 | * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry | |
4408 | * Format. | |
4409 | */ | |
4410 | vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; | |
4411 | vsc->colorimetry = sdp->db[16] & 0xf; | |
4412 | vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; | |
4413 | ||
4414 | switch (sdp->db[17] & 0x7) { | |
4415 | case 0x0: | |
4416 | vsc->bpc = 6; | |
4417 | break; | |
4418 | case 0x1: | |
4419 | vsc->bpc = 8; | |
4420 | break; | |
4421 | case 0x2: | |
4422 | vsc->bpc = 10; | |
4423 | break; | |
4424 | case 0x3: | |
4425 | vsc->bpc = 12; | |
4426 | break; | |
4427 | case 0x4: | |
4428 | vsc->bpc = 16; | |
4429 | break; | |
4430 | default: | |
4431 | MISSING_CASE(sdp->db[17] & 0x7); | |
4432 | return -EINVAL; | |
4433 | } | |
4434 | ||
4435 | vsc->content_type = sdp->db[18] & 0x7; | |
4436 | } else { | |
4437 | return -EINVAL; | |
4438 | } | |
4439 | ||
4440 | return 0; | |
4441 | } | |
4442 | ||
4443 | static int | |
4444 | intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, | |
4445 | const void *buffer, size_t size) | |
4446 | { | |
4447 | int ret; | |
4448 | ||
4449 | const struct dp_sdp *sdp = buffer; | |
4450 | ||
4451 | if (size < sizeof(struct dp_sdp)) | |
4452 | return -EINVAL; | |
4453 | ||
4454 | if (sdp->sdp_header.HB0 != 0) | |
4455 | return -EINVAL; | |
4456 | ||
4457 | if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) | |
4458 | return -EINVAL; | |
4459 | ||
4460 | /* | |
4461 | * Least Significant Eight Bits of (Data Byte Count – 1) | |
4462 | * 1Dh (i.e., Data Byte Count = 30 bytes). | |
4463 | */ | |
4464 | if (sdp->sdp_header.HB2 != 0x1D) | |
4465 | return -EINVAL; | |
4466 | ||
4467 | /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ | |
4468 | if ((sdp->sdp_header.HB3 & 0x3) != 0) | |
4469 | return -EINVAL; | |
4470 | ||
4471 | /* INFOFRAME SDP Version Number */ | |
4472 | if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) | |
4473 | return -EINVAL; | |
4474 | ||
4475 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ | |
4476 | if (sdp->db[0] != 1) | |
4477 | return -EINVAL; | |
4478 | ||
4479 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ | |
4480 | if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) | |
4481 | return -EINVAL; | |
4482 | ||
4483 | ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], | |
4484 | HDMI_DRM_INFOFRAME_SIZE); | |
4485 | ||
4486 | return ret; | |
4487 | } | |
4488 | ||
4489 | static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, | |
4490 | struct intel_crtc_state *crtc_state, | |
4491 | struct drm_dp_vsc_sdp *vsc) | |
4492 | { | |
7801f3b7 | 4493 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
1b404b7d GM |
4494 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4495 | unsigned int type = DP_SDP_VSC; | |
4496 | struct dp_sdp sdp = {}; | |
4497 | int ret; | |
4498 | ||
1b404b7d GM |
4499 | if ((crtc_state->infoframes.enable & |
4500 | intel_hdmi_infoframe_enable(type)) == 0) | |
4501 | return; | |
4502 | ||
7801f3b7 | 4503 | dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); |
1b404b7d GM |
4504 | |
4505 | ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); | |
4506 | ||
4507 | if (ret) | |
4508 | drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); | |
4509 | } | |
4510 | ||
4511 | static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, | |
4512 | struct intel_crtc_state *crtc_state, | |
4513 | struct hdmi_drm_infoframe *drm_infoframe) | |
4514 | { | |
7801f3b7 | 4515 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
1b404b7d GM |
4516 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4517 | unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; | |
4518 | struct dp_sdp sdp = {}; | |
4519 | int ret; | |
4520 | ||
4521 | if ((crtc_state->infoframes.enable & | |
4522 | intel_hdmi_infoframe_enable(type)) == 0) | |
4523 | return; | |
4524 | ||
7801f3b7 LDM |
4525 | dig_port->read_infoframe(encoder, crtc_state, type, &sdp, |
4526 | sizeof(sdp)); | |
1b404b7d GM |
4527 | |
4528 | ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, | |
4529 | sizeof(sdp)); | |
4530 | ||
4531 | if (ret) | |
4532 | drm_dbg_kms(&dev_priv->drm, | |
4533 | "Failed to unpack DP HDR Metadata Infoframe SDP\n"); | |
4534 | } | |
4535 | ||
4536 | void intel_read_dp_sdp(struct intel_encoder *encoder, | |
4537 | struct intel_crtc_state *crtc_state, | |
4538 | unsigned int type) | |
4539 | { | |
4540 | switch (type) { | |
4541 | case DP_SDP_VSC: | |
4542 | intel_read_dp_vsc_sdp(encoder, crtc_state, | |
4543 | &crtc_state->infoframes.vsc); | |
4544 | break; | |
4545 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
4546 | intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, | |
4547 | &crtc_state->infoframes.drm.drm); | |
4548 | break; | |
4549 | default: | |
4550 | MISSING_CASE(type); | |
4551 | break; | |
4552 | } | |
4553 | } | |
4554 | ||
830de422 | 4555 | static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
c5d5ab7a | 4556 | { |
af67009c | 4557 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
da15f7cb | 4558 | int status = 0; |
140ef138 | 4559 | int test_link_rate; |
830de422 | 4560 | u8 test_lane_count, test_link_bw; |
da15f7cb MN |
4561 | /* (DP CTS 1.2) |
4562 | * 4.3.1.11 | |
4563 | */ | |
4564 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
4565 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
4566 | &test_lane_count); | |
4567 | ||
4568 | if (status <= 0) { | |
af67009c | 4569 | drm_dbg_kms(&i915->drm, "Lane count read failed\n"); |
da15f7cb MN |
4570 | return DP_TEST_NAK; |
4571 | } | |
4572 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
da15f7cb MN |
4573 | |
4574 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
4575 | &test_link_bw); | |
4576 | if (status <= 0) { | |
af67009c | 4577 | drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); |
da15f7cb MN |
4578 | return DP_TEST_NAK; |
4579 | } | |
da15f7cb | 4580 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); |
140ef138 MN |
4581 | |
4582 | /* Validate the requested link rate and lane count */ | |
4583 | if (!intel_dp_link_params_valid(intel_dp, test_link_rate, | |
4584 | test_lane_count)) | |
da15f7cb MN |
4585 | return DP_TEST_NAK; |
4586 | ||
4587 | intel_dp->compliance.test_lane_count = test_lane_count; | |
4588 | intel_dp->compliance.test_link_rate = test_link_rate; | |
4589 | ||
4590 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4591 | } |
4592 | ||
830de422 | 4593 | static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
c5d5ab7a | 4594 | { |
af67009c | 4595 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 JN |
4596 | u8 test_pattern; |
4597 | u8 test_misc; | |
611032bf MN |
4598 | __be16 h_width, v_height; |
4599 | int status = 0; | |
4600 | ||
4601 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
010b9b39 JN |
4602 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, |
4603 | &test_pattern); | |
611032bf | 4604 | if (status <= 0) { |
af67009c | 4605 | drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); |
611032bf MN |
4606 | return DP_TEST_NAK; |
4607 | } | |
4608 | if (test_pattern != DP_COLOR_RAMP) | |
4609 | return DP_TEST_NAK; | |
4610 | ||
4611 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
4612 | &h_width, 2); | |
4613 | if (status <= 0) { | |
af67009c | 4614 | drm_dbg_kms(&i915->drm, "H Width read failed\n"); |
611032bf MN |
4615 | return DP_TEST_NAK; |
4616 | } | |
4617 | ||
4618 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
4619 | &v_height, 2); | |
4620 | if (status <= 0) { | |
af67009c | 4621 | drm_dbg_kms(&i915->drm, "V Height read failed\n"); |
611032bf MN |
4622 | return DP_TEST_NAK; |
4623 | } | |
4624 | ||
010b9b39 JN |
4625 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, |
4626 | &test_misc); | |
611032bf | 4627 | if (status <= 0) { |
af67009c | 4628 | drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); |
611032bf MN |
4629 | return DP_TEST_NAK; |
4630 | } | |
4631 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
4632 | return DP_TEST_NAK; | |
4633 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
4634 | return DP_TEST_NAK; | |
4635 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
4636 | case DP_TEST_BIT_DEPTH_6: | |
4637 | intel_dp->compliance.test_data.bpc = 6; | |
4638 | break; | |
4639 | case DP_TEST_BIT_DEPTH_8: | |
4640 | intel_dp->compliance.test_data.bpc = 8; | |
4641 | break; | |
4642 | default: | |
4643 | return DP_TEST_NAK; | |
4644 | } | |
4645 | ||
4646 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
4647 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
4648 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
4649 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 4650 | intel_dp->compliance.test_active = true; |
611032bf MN |
4651 | |
4652 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4653 | } |
4654 | ||
830de422 | 4655 | static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) |
a60f0e38 | 4656 | { |
af67009c | 4657 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 | 4658 | u8 test_result = DP_TEST_ACK; |
559be30c TP |
4659 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4660 | struct drm_connector *connector = &intel_connector->base; | |
4661 | ||
4662 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4663 | connector->edid_corrupt || |
559be30c TP |
4664 | intel_dp->aux.i2c_defer_count > 6) { |
4665 | /* Check EDID read for NACKs, DEFERs and corruption | |
4666 | * (DP CTS 1.2 Core r1.1) | |
4667 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4668 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4669 | * 4.2.2.6 : EDID corruption detected | |
4670 | * Use failsafe mode for all cases | |
4671 | */ | |
4672 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4673 | intel_dp->aux.i2c_defer_count > 0) | |
af67009c JN |
4674 | drm_dbg_kms(&i915->drm, |
4675 | "EDID read had %d NACKs, %d DEFERs\n", | |
4676 | intel_dp->aux.i2c_nack_count, | |
4677 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 4678 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 4679 | } else { |
25fa6b0f JN |
4680 | /* FIXME: Get rid of drm_edid_raw() */ |
4681 | const struct edid *block = drm_edid_raw(intel_connector->detect_edid); | |
f79b468e | 4682 | |
25fa6b0f JN |
4683 | /* We have to write the checksum of the last block read */ |
4684 | block += block->extensions; | |
f79b468e | 4685 | |
010b9b39 JN |
4686 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, |
4687 | block->checksum) <= 0) | |
af67009c JN |
4688 | drm_dbg_kms(&i915->drm, |
4689 | "Failed to write EDID checksum\n"); | |
559be30c TP |
4690 | |
4691 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 4692 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
4693 | } |
4694 | ||
4695 | /* Set test active flag here so userspace doesn't interrupt things */ | |
dd93cecf | 4696 | intel_dp->compliance.test_active = true; |
559be30c | 4697 | |
c5d5ab7a TP |
4698 | return test_result; |
4699 | } | |
4700 | ||
a621860a VS |
4701 | static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, |
4702 | const struct intel_crtc_state *crtc_state) | |
8cdf7271 AM |
4703 | { |
4704 | struct drm_i915_private *dev_priv = | |
4705 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
8cdf7271 AM |
4706 | struct drm_dp_phy_test_params *data = |
4707 | &intel_dp->compliance.test_data.phytest; | |
a621860a | 4708 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
6c7ffa7a | 4709 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
8cdf7271 AM |
4710 | enum pipe pipe = crtc->pipe; |
4711 | u32 pattern_val; | |
4712 | ||
4713 | switch (data->phy_pattern) { | |
8e1cd40d | 4714 | case DP_LINK_QUAL_PATTERN_DISABLE: |
9d0bfa7a | 4715 | drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); |
8cdf7271 | 4716 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); |
6c7ffa7a KA |
4717 | if (DISPLAY_VER(dev_priv) >= 10) |
4718 | intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), | |
4719 | DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, | |
4720 | DP_TP_CTL_LINK_TRAIN_NORMAL); | |
8cdf7271 | 4721 | break; |
8e1cd40d | 4722 | case DP_LINK_QUAL_PATTERN_D10_2: |
9d0bfa7a | 4723 | drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); |
8cdf7271 AM |
4724 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), |
4725 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); | |
4726 | break; | |
8e1cd40d | 4727 | case DP_LINK_QUAL_PATTERN_ERROR_RATE: |
9d0bfa7a | 4728 | drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); |
8cdf7271 AM |
4729 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), |
4730 | DDI_DP_COMP_CTL_ENABLE | | |
4731 | DDI_DP_COMP_CTL_SCRAMBLED_0); | |
4732 | break; | |
8e1cd40d | 4733 | case DP_LINK_QUAL_PATTERN_PRBS7: |
9d0bfa7a | 4734 | drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); |
8cdf7271 AM |
4735 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), |
4736 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); | |
4737 | break; | |
8e1cd40d | 4738 | case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: |
8cdf7271 AM |
4739 | /* |
4740 | * FIXME: Ideally pattern should come from DPCD 0x250. As | |
4741 | * current firmware of DPR-100 could not set it, so hardcoding | |
4742 | * now for complaince test. | |
4743 | */ | |
9d0bfa7a JN |
4744 | drm_dbg_kms(&dev_priv->drm, |
4745 | "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); | |
8cdf7271 AM |
4746 | pattern_val = 0x3e0f83e0; |
4747 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); | |
4748 | pattern_val = 0x0f83e0f8; | |
4749 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); | |
4750 | pattern_val = 0x0000f83e; | |
4751 | intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); | |
4752 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
4753 | DDI_DP_COMP_CTL_ENABLE | | |
4754 | DDI_DP_COMP_CTL_CUSTOM80); | |
4755 | break; | |
8e1cd40d | 4756 | case DP_LINK_QUAL_PATTERN_CP2520_PAT_1: |
8cdf7271 AM |
4757 | /* |
4758 | * FIXME: Ideally pattern should come from DPCD 0x24A. As | |
4759 | * current firmware of DPR-100 could not set it, so hardcoding | |
4760 | * now for complaince test. | |
4761 | */ | |
9d0bfa7a | 4762 | drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n"); |
8cdf7271 AM |
4763 | pattern_val = 0xFB; |
4764 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), | |
4765 | DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | | |
4766 | pattern_val); | |
4767 | break; | |
6c7ffa7a KA |
4768 | case DP_LINK_QUAL_PATTERN_CP2520_PAT_3: |
4769 | if (DISPLAY_VER(dev_priv) < 10) { | |
4770 | drm_warn(&dev_priv->drm, "Platform does not support TPS4\n"); | |
4771 | break; | |
4772 | } | |
4773 | drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n"); | |
4774 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); | |
4775 | intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), | |
4776 | DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, | |
4777 | DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4); | |
4778 | break; | |
8cdf7271 | 4779 | default: |
6c7ffa7a | 4780 | drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n"); |
8cdf7271 AM |
4781 | } |
4782 | } | |
4783 | ||
a621860a VS |
4784 | static void intel_dp_process_phy_request(struct intel_dp *intel_dp, |
4785 | const struct intel_crtc_state *crtc_state) | |
8cdf7271 | 4786 | { |
9d0bfa7a | 4787 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
8cdf7271 AM |
4788 | struct drm_dp_phy_test_params *data = |
4789 | &intel_dp->compliance.test_data.phytest; | |
4790 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4791 | ||
b30edfd8 ID |
4792 | if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, |
4793 | link_status) < 0) { | |
9d0bfa7a | 4794 | drm_dbg_kms(&i915->drm, "failed to get link status\n"); |
8cdf7271 AM |
4795 | return; |
4796 | } | |
4797 | ||
4798 | /* retrieve vswing & pre-emphasis setting */ | |
b30edfd8 ID |
4799 | intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, |
4800 | link_status); | |
8cdf7271 | 4801 | |
67fba3f1 | 4802 | intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX); |
8cdf7271 | 4803 | |
a621860a | 4804 | intel_dp_phy_pattern_update(intel_dp, crtc_state); |
8cdf7271 | 4805 | |
155b8645 KA |
4806 | drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
4807 | intel_dp->train_set, crtc_state->lane_count); | |
4808 | ||
8cdf7271 | 4809 | drm_dp_set_phy_test_pattern(&intel_dp->aux, data, |
3ee302ec | 4810 | intel_dp->dpcd[DP_DPCD_REV]); |
8cdf7271 AM |
4811 | } |
4812 | ||
830de422 | 4813 | static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) |
a60f0e38 | 4814 | { |
9d0bfa7a | 4815 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
193af12c VS |
4816 | struct drm_dp_phy_test_params *data = |
4817 | &intel_dp->compliance.test_data.phytest; | |
88afbfdb | 4818 | |
193af12c | 4819 | if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { |
9d0bfa7a | 4820 | drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n"); |
193af12c VS |
4821 | return DP_TEST_NAK; |
4822 | } | |
88afbfdb | 4823 | |
193af12c VS |
4824 | /* Set test active flag here so userspace doesn't interrupt things */ |
4825 | intel_dp->compliance.test_active = true; | |
8cdf7271 | 4826 | |
193af12c | 4827 | return DP_TEST_ACK; |
c5d5ab7a TP |
4828 | } |
4829 | ||
4830 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4831 | { | |
af67009c | 4832 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
830de422 JN |
4833 | u8 response = DP_TEST_NAK; |
4834 | u8 request = 0; | |
5ec63bbd | 4835 | int status; |
c5d5ab7a | 4836 | |
5ec63bbd | 4837 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a | 4838 | if (status <= 0) { |
af67009c JN |
4839 | drm_dbg_kms(&i915->drm, |
4840 | "Could not read test request from sink\n"); | |
c5d5ab7a TP |
4841 | goto update_status; |
4842 | } | |
4843 | ||
5ec63bbd | 4844 | switch (request) { |
c5d5ab7a | 4845 | case DP_TEST_LINK_TRAINING: |
af67009c | 4846 | drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); |
c5d5ab7a TP |
4847 | response = intel_dp_autotest_link_training(intel_dp); |
4848 | break; | |
4849 | case DP_TEST_LINK_VIDEO_PATTERN: | |
af67009c | 4850 | drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); |
c5d5ab7a TP |
4851 | response = intel_dp_autotest_video_pattern(intel_dp); |
4852 | break; | |
4853 | case DP_TEST_LINK_EDID_READ: | |
af67009c | 4854 | drm_dbg_kms(&i915->drm, "EDID test requested\n"); |
c5d5ab7a TP |
4855 | response = intel_dp_autotest_edid(intel_dp); |
4856 | break; | |
4857 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
af67009c | 4858 | drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); |
c5d5ab7a TP |
4859 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4860 | break; | |
4861 | default: | |
af67009c JN |
4862 | drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", |
4863 | request); | |
c5d5ab7a TP |
4864 | break; |
4865 | } | |
4866 | ||
5ec63bbd JN |
4867 | if (response & DP_TEST_ACK) |
4868 | intel_dp->compliance.test_type = request; | |
4869 | ||
c5d5ab7a | 4870 | update_status: |
5ec63bbd | 4871 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a | 4872 | if (status <= 0) |
af67009c JN |
4873 | drm_dbg_kms(&i915->drm, |
4874 | "Could not write test response to sink\n"); | |
a60f0e38 JB |
4875 | } |
4876 | ||
3ee7fab0 JN |
4877 | static bool intel_dp_link_ok(struct intel_dp *intel_dp, |
4878 | u8 link_status[DP_LINK_STATUS_SIZE]) | |
4879 | { | |
4880 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
4881 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
4882 | bool uhbr = intel_dp->link_rate >= 1000000; | |
4883 | bool ok; | |
4884 | ||
4885 | if (uhbr) | |
4886 | ok = drm_dp_128b132b_lane_channel_eq_done(link_status, | |
4887 | intel_dp->lane_count); | |
4888 | else | |
4889 | ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); | |
4890 | ||
4891 | if (ok) | |
4892 | return true; | |
4893 | ||
4894 | intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); | |
4895 | drm_dbg_kms(&i915->drm, | |
4896 | "[ENCODER:%d:%s] %s link not ok, retraining\n", | |
4897 | encoder->base.base.id, encoder->base.name, | |
4898 | uhbr ? "128b/132b" : "8b/10b"); | |
4899 | ||
4900 | return false; | |
4901 | } | |
4902 | ||
0abd3acf | 4903 | static void |
784a2ec0 | 4904 | intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) |
0abd3acf | 4905 | { |
784a2ec0 JN |
4906 | bool handled = false; |
4907 | ||
72f1de49 | 4908 | drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled); |
0abd3acf | 4909 | |
26950f29 JN |
4910 | if (esi[1] & DP_CP_IRQ) { |
4911 | intel_hdcp_handle_cp_irq(intel_dp->attached_connector); | |
784a2ec0 | 4912 | ack[1] |= DP_CP_IRQ; |
26950f29 | 4913 | } |
0abd3acf AG |
4914 | } |
4915 | ||
1d50942d | 4916 | static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) |
1358139b JN |
4917 | { |
4918 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
4919 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
1d50942d JN |
4920 | u8 link_status[DP_LINK_STATUS_SIZE] = {}; |
4921 | const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; | |
4922 | ||
4923 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, | |
4924 | esi_link_status_size) != esi_link_status_size) { | |
4925 | drm_err(&i915->drm, | |
4926 | "[ENCODER:%d:%s] Failed to read link status\n", | |
4927 | encoder->base.base.id, encoder->base.name); | |
4928 | return false; | |
4929 | } | |
1358139b | 4930 | |
3ee7fab0 | 4931 | return intel_dp_link_ok(intel_dp, link_status); |
1358139b JN |
4932 | } |
4933 | ||
8d712a7e ID |
4934 | /** |
4935 | * intel_dp_check_mst_status - service any pending MST interrupts, check link status | |
4936 | * @intel_dp: Intel DP struct | |
4937 | * | |
4938 | * Read any pending MST interrupts, call MST core to handle these and ack the | |
4939 | * interrupts. Check if the main and AUX link state is ok. | |
4940 | * | |
4941 | * Returns: | |
4942 | * - %true if pending interrupts were serviced (or no interrupts were | |
4943 | * pending) w/o detecting an error condition. | |
4944 | * - %false if an error condition - like AUX failure or a loss of link - is | |
6496dbec ID |
4945 | * detected, or another condition - like a DP tunnel BW state change - needs |
4946 | * servicing from the hotplug work. | |
8d712a7e ID |
4947 | */ |
4948 | static bool | |
0e32b39c DA |
4949 | intel_dp_check_mst_status(struct intel_dp *intel_dp) |
4950 | { | |
af67009c | 4951 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
8d712a7e | 4952 | bool link_ok = true; |
6496dbec | 4953 | bool reprobe_needed = false; |
3c0ec2c2 | 4954 | |
4f360482 | 4955 | drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); |
3c0ec2c2 VS |
4956 | |
4957 | for (;;) { | |
1d50942d | 4958 | u8 esi[4] = {}; |
784a2ec0 | 4959 | u8 ack[4] = {}; |
45ef40aa | 4960 | |
8d712a7e | 4961 | if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { |
3c0ec2c2 VS |
4962 | drm_dbg_kms(&i915->drm, |
4963 | "failed to get ESI - device may have failed\n"); | |
8d712a7e ID |
4964 | link_ok = false; |
4965 | ||
4966 | break; | |
3c0ec2c2 | 4967 | } |
0e32b39c | 4968 | |
34ed3e83 JN |
4969 | drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi); |
4970 | ||
1d50942d JN |
4971 | if (intel_dp->active_mst_links > 0 && link_ok && |
4972 | esi[3] & LINK_STATUS_CHANGED) { | |
4973 | if (!intel_dp_mst_link_status(intel_dp)) | |
1358139b | 4974 | link_ok = false; |
784a2ec0 | 4975 | ack[3] |= LINK_STATUS_CHANGED; |
3c0ec2c2 | 4976 | } |
0e32b39c | 4977 | |
784a2ec0 | 4978 | intel_dp_mst_hpd_irq(intel_dp, esi, ack); |
0abd3acf | 4979 | |
6496dbec ID |
4980 | if (esi[3] & DP_TUNNELING_IRQ) { |
4981 | if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr, | |
4982 | &intel_dp->aux)) | |
4983 | reprobe_needed = true; | |
4984 | ack[3] |= DP_TUNNELING_IRQ; | |
4985 | } | |
4986 | ||
784a2ec0 | 4987 | if (!memchr_inv(ack, 0, sizeof(ack))) |
3c0ec2c2 VS |
4988 | break; |
4989 | ||
784a2ec0 | 4990 | if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) |
603801d0 | 4991 | drm_dbg_kms(&i915->drm, "Failed to ack ESI\n"); |
72f1de49 WL |
4992 | |
4993 | if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) | |
4994 | drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); | |
0e32b39c | 4995 | } |
3c0ec2c2 | 4996 | |
6496dbec | 4997 | return link_ok && !reprobe_needed; |
0e32b39c DA |
4998 | } |
4999 | ||
9488a030 SS |
5000 | static void |
5001 | intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) | |
5002 | { | |
5003 | bool is_active; | |
5004 | u8 buf = 0; | |
5005 | ||
5006 | is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); | |
5007 | if (intel_dp->frl.is_trained && !is_active) { | |
5008 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) | |
5009 | return; | |
5010 | ||
5011 | buf &= ~DP_PCON_ENABLE_HDMI_LINK; | |
5012 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) | |
5013 | return; | |
5014 | ||
5015 | drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); | |
5016 | ||
47e1a59e AN |
5017 | intel_dp->frl.is_trained = false; |
5018 | ||
9488a030 SS |
5019 | /* Restart FRL training or fall back to TMDS mode */ |
5020 | intel_dp_check_frl_training(intel_dp); | |
5021 | } | |
5022 | } | |
5023 | ||
c85d200e VS |
5024 | static bool |
5025 | intel_dp_needs_link_retrain(struct intel_dp *intel_dp) | |
5026 | { | |
5027 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
5028 | ||
edb2e530 | 5029 | if (!intel_dp->link_trained) |
2f8e7ea9 JRS |
5030 | return false; |
5031 | ||
5032 | /* | |
5033 | * While PSR source HW is enabled, it will control main-link sending | |
5034 | * frames, enabling and disabling it so trying to do a retrain will fail | |
5035 | * as the link would or not be on or it could mix training patterns | |
5036 | * and frame data at the same time causing retrain to fail. | |
5037 | * Also when exiting PSR, HW will retrain the link anyways fixing | |
5038 | * any link status error. | |
5039 | */ | |
5040 | if (intel_psr_enabled(intel_dp)) | |
edb2e530 VS |
5041 | return false; |
5042 | ||
b30edfd8 ID |
5043 | if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, |
5044 | link_status) < 0) | |
c85d200e | 5045 | return false; |
c85d200e VS |
5046 | |
5047 | /* | |
5048 | * Validate the cached values of intel_dp->link_rate and | |
5049 | * intel_dp->lane_count before attempting to retrain. | |
a621860a VS |
5050 | * |
5051 | * FIXME would be nice to user the crtc state here, but since | |
5052 | * we need to call this from the short HPD handler that seems | |
5053 | * a bit hard. | |
c85d200e VS |
5054 | */ |
5055 | if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, | |
5056 | intel_dp->lane_count)) | |
5057 | return false; | |
5058 | ||
3ee7fab0 JN |
5059 | /* Retrain if link not ok */ |
5060 | return !intel_dp_link_ok(intel_dp, link_status); | |
c85d200e VS |
5061 | } |
5062 | ||
f0617ff0 VS |
5063 | static bool intel_dp_has_connector(struct intel_dp *intel_dp, |
5064 | const struct drm_connector_state *conn_state) | |
5065 | { | |
5066 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5067 | struct intel_encoder *encoder; | |
5068 | enum pipe pipe; | |
5069 | ||
5070 | if (!conn_state->best_encoder) | |
5071 | return false; | |
5072 | ||
5073 | /* SST */ | |
5074 | encoder = &dp_to_dig_port(intel_dp)->base; | |
5075 | if (conn_state->best_encoder == &encoder->base) | |
5076 | return true; | |
5077 | ||
5078 | /* MST */ | |
5079 | for_each_pipe(i915, pipe) { | |
5080 | encoder = &intel_dp->mst_encoders[pipe]->base; | |
5081 | if (conn_state->best_encoder == &encoder->base) | |
5082 | return true; | |
5083 | } | |
5084 | ||
5085 | return false; | |
5086 | } | |
5087 | ||
c598c335 ID |
5088 | int intel_dp_get_active_pipes(struct intel_dp *intel_dp, |
5089 | struct drm_modeset_acquire_ctx *ctx, | |
5090 | u8 *pipe_mask) | |
f0617ff0 VS |
5091 | { |
5092 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5093 | struct drm_connector_list_iter conn_iter; | |
5094 | struct intel_connector *connector; | |
5095 | int ret = 0; | |
5096 | ||
f461ea5d | 5097 | *pipe_mask = 0; |
f0617ff0 | 5098 | |
f0617ff0 VS |
5099 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); |
5100 | for_each_intel_connector_iter(connector, &conn_iter) { | |
5101 | struct drm_connector_state *conn_state = | |
5102 | connector->base.state; | |
5103 | struct intel_crtc_state *crtc_state; | |
5104 | struct intel_crtc *crtc; | |
5105 | ||
5106 | if (!intel_dp_has_connector(intel_dp, conn_state)) | |
5107 | continue; | |
5108 | ||
5109 | crtc = to_intel_crtc(conn_state->crtc); | |
5110 | if (!crtc) | |
5111 | continue; | |
5112 | ||
5113 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
5114 | if (ret) | |
5115 | break; | |
5116 | ||
5117 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
5118 | ||
5119 | drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); | |
5120 | ||
5121 | if (!crtc_state->hw.active) | |
5122 | continue; | |
5123 | ||
199c7d75 ID |
5124 | if (conn_state->commit) |
5125 | drm_WARN_ON(&i915->drm, | |
5126 | !wait_for_completion_timeout(&conn_state->commit->hw_done, | |
5127 | msecs_to_jiffies(5000))); | |
f0617ff0 | 5128 | |
f461ea5d | 5129 | *pipe_mask |= BIT(crtc->pipe); |
f0617ff0 VS |
5130 | } |
5131 | drm_connector_list_iter_end(&conn_iter); | |
5132 | ||
f0617ff0 VS |
5133 | return ret; |
5134 | } | |
5135 | ||
5136 | static bool intel_dp_is_connected(struct intel_dp *intel_dp) | |
5137 | { | |
5138 | struct intel_connector *connector = intel_dp->attached_connector; | |
5139 | ||
5140 | return connector->base.status == connector_status_connected || | |
5141 | intel_dp->is_mst; | |
5142 | } | |
5143 | ||
c85d200e VS |
5144 | int intel_dp_retrain_link(struct intel_encoder *encoder, |
5145 | struct drm_modeset_acquire_ctx *ctx) | |
bfd02b3c | 5146 | { |
bfd02b3c | 5147 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 5148 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
c85d200e | 5149 | struct intel_crtc *crtc; |
f461ea5d | 5150 | u8 pipe_mask; |
c85d200e VS |
5151 | int ret; |
5152 | ||
f0617ff0 | 5153 | if (!intel_dp_is_connected(intel_dp)) |
c85d200e VS |
5154 | return 0; |
5155 | ||
5156 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
5157 | ctx); | |
5158 | if (ret) | |
5159 | return ret; | |
5160 | ||
7e4460c3 ID |
5161 | if (!intel_dp_needs_link_retrain(intel_dp)) |
5162 | return 0; | |
5163 | ||
5164 | ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); | |
c85d200e VS |
5165 | if (ret) |
5166 | return ret; | |
5167 | ||
f461ea5d | 5168 | if (pipe_mask == 0) |
c85d200e | 5169 | return 0; |
7e4460c3 ID |
5170 | |
5171 | if (!intel_dp_needs_link_retrain(intel_dp)) | |
5172 | return 0; | |
c85d200e | 5173 | |
f0617ff0 VS |
5174 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", |
5175 | encoder->base.base.id, encoder->base.name); | |
c85d200e | 5176 | |
f461ea5d | 5177 | for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { |
f0617ff0 VS |
5178 | const struct intel_crtc_state *crtc_state = |
5179 | to_intel_crtc_state(crtc->base.state); | |
bfd02b3c | 5180 | |
f0617ff0 VS |
5181 | /* Suppress underruns caused by re-training */ |
5182 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
5183 | if (crtc_state->has_pch_encoder) | |
5184 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
5185 | intel_crtc_pch_transcoder(crtc), false); | |
5186 | } | |
bfd02b3c | 5187 | |
f461ea5d | 5188 | for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { |
a621860a VS |
5189 | const struct intel_crtc_state *crtc_state = |
5190 | to_intel_crtc_state(crtc->base.state); | |
5191 | ||
5192 | /* retrain on the MST master transcoder */ | |
005e9537 | 5193 | if (DISPLAY_VER(dev_priv) >= 12 && |
a621860a VS |
5194 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && |
5195 | !intel_dp_mst_is_master_trans(crtc_state)) | |
5196 | continue; | |
5197 | ||
4f3dd47a | 5198 | intel_dp_check_frl_training(intel_dp); |
10fec80b | 5199 | intel_dp_pcon_dsc_configure(intel_dp, crtc_state); |
a621860a VS |
5200 | intel_dp_start_link_train(intel_dp, crtc_state); |
5201 | intel_dp_stop_link_train(intel_dp, crtc_state); | |
5202 | break; | |
5203 | } | |
bfd02b3c | 5204 | |
f461ea5d | 5205 | for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { |
f0617ff0 VS |
5206 | const struct intel_crtc_state *crtc_state = |
5207 | to_intel_crtc_state(crtc->base.state); | |
bfd02b3c | 5208 | |
f0617ff0 | 5209 | /* Keep underrun reporting disabled until things are stable */ |
7b06894b | 5210 | intel_crtc_wait_for_next_vblank(crtc); |
f0617ff0 VS |
5211 | |
5212 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
5213 | if (crtc_state->has_pch_encoder) | |
5214 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
5215 | intel_crtc_pch_transcoder(crtc), true); | |
5216 | } | |
c85d200e VS |
5217 | |
5218 | return 0; | |
bfd02b3c VS |
5219 | } |
5220 | ||
193af12c VS |
5221 | static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, |
5222 | struct drm_modeset_acquire_ctx *ctx, | |
f461ea5d | 5223 | u8 *pipe_mask) |
193af12c VS |
5224 | { |
5225 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5226 | struct drm_connector_list_iter conn_iter; | |
5227 | struct intel_connector *connector; | |
5228 | int ret = 0; | |
5229 | ||
f461ea5d | 5230 | *pipe_mask = 0; |
193af12c VS |
5231 | |
5232 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); | |
5233 | for_each_intel_connector_iter(connector, &conn_iter) { | |
5234 | struct drm_connector_state *conn_state = | |
5235 | connector->base.state; | |
5236 | struct intel_crtc_state *crtc_state; | |
5237 | struct intel_crtc *crtc; | |
5238 | ||
5239 | if (!intel_dp_has_connector(intel_dp, conn_state)) | |
5240 | continue; | |
5241 | ||
5242 | crtc = to_intel_crtc(conn_state->crtc); | |
5243 | if (!crtc) | |
5244 | continue; | |
5245 | ||
5246 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
5247 | if (ret) | |
5248 | break; | |
5249 | ||
5250 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
5251 | ||
5252 | drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); | |
5253 | ||
5254 | if (!crtc_state->hw.active) | |
5255 | continue; | |
5256 | ||
5257 | if (conn_state->commit && | |
5258 | !try_wait_for_completion(&conn_state->commit->hw_done)) | |
5259 | continue; | |
5260 | ||
f461ea5d | 5261 | *pipe_mask |= BIT(crtc->pipe); |
193af12c VS |
5262 | } |
5263 | drm_connector_list_iter_end(&conn_iter); | |
5264 | ||
5265 | return ret; | |
5266 | } | |
5267 | ||
5268 | static int intel_dp_do_phy_test(struct intel_encoder *encoder, | |
5269 | struct drm_modeset_acquire_ctx *ctx) | |
5270 | { | |
5271 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
5272 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
a621860a | 5273 | struct intel_crtc *crtc; |
f461ea5d | 5274 | u8 pipe_mask; |
193af12c VS |
5275 | int ret; |
5276 | ||
5277 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
5278 | ctx); | |
5279 | if (ret) | |
5280 | return ret; | |
5281 | ||
f461ea5d | 5282 | ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask); |
193af12c VS |
5283 | if (ret) |
5284 | return ret; | |
5285 | ||
f461ea5d | 5286 | if (pipe_mask == 0) |
193af12c VS |
5287 | return 0; |
5288 | ||
5289 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", | |
5290 | encoder->base.base.id, encoder->base.name); | |
a621860a | 5291 | |
f461ea5d | 5292 | for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { |
a621860a VS |
5293 | const struct intel_crtc_state *crtc_state = |
5294 | to_intel_crtc_state(crtc->base.state); | |
5295 | ||
5296 | /* test on the MST master transcoder */ | |
005e9537 | 5297 | if (DISPLAY_VER(dev_priv) >= 12 && |
a621860a VS |
5298 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && |
5299 | !intel_dp_mst_is_master_trans(crtc_state)) | |
5300 | continue; | |
5301 | ||
5302 | intel_dp_process_phy_request(intel_dp, crtc_state); | |
5303 | break; | |
5304 | } | |
193af12c VS |
5305 | |
5306 | return 0; | |
5307 | } | |
5308 | ||
699390f7 | 5309 | void intel_dp_phy_test(struct intel_encoder *encoder) |
193af12c VS |
5310 | { |
5311 | struct drm_modeset_acquire_ctx ctx; | |
5312 | int ret; | |
5313 | ||
5314 | drm_modeset_acquire_init(&ctx, 0); | |
5315 | ||
5316 | for (;;) { | |
5317 | ret = intel_dp_do_phy_test(encoder, &ctx); | |
5318 | ||
5319 | if (ret == -EDEADLK) { | |
5320 | drm_modeset_backoff(&ctx); | |
5321 | continue; | |
5322 | } | |
5323 | ||
5324 | break; | |
5325 | } | |
5326 | ||
5327 | drm_modeset_drop_locks(&ctx); | |
5328 | drm_modeset_acquire_fini(&ctx); | |
5329 | drm_WARN(encoder->base.dev, ret, | |
5330 | "Acquiring modeset locks failed with %i\n", ret); | |
5331 | } | |
5332 | ||
9488a030 | 5333 | static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) |
9844bc87 | 5334 | { |
af67009c | 5335 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
9844bc87 DP |
5336 | u8 val; |
5337 | ||
5338 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
5339 | return; | |
5340 | ||
5341 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
5342 | DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) | |
5343 | return; | |
5344 | ||
5345 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); | |
5346 | ||
5347 | if (val & DP_AUTOMATED_TEST_REQUEST) | |
5348 | intel_dp_handle_test_request(intel_dp); | |
5349 | ||
342ac601 | 5350 | if (val & DP_CP_IRQ) |
09d56393 | 5351 | intel_hdcp_handle_cp_irq(intel_dp->attached_connector); |
342ac601 R |
5352 | |
5353 | if (val & DP_SINK_SPECIFIC_IRQ) | |
af67009c | 5354 | drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); |
9844bc87 DP |
5355 | } |
5356 | ||
6496dbec | 5357 | static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) |
9488a030 | 5358 | { |
6496dbec ID |
5359 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
5360 | bool reprobe_needed = false; | |
9488a030 SS |
5361 | u8 val; |
5362 | ||
5363 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
6496dbec | 5364 | return false; |
9488a030 SS |
5365 | |
5366 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
b6dfa416 | 5367 | DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) |
6496dbec ID |
5368 | return false; |
5369 | ||
5370 | if ((val & DP_TUNNELING_IRQ) && | |
5371 | drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr, | |
5372 | &intel_dp->aux)) | |
5373 | reprobe_needed = true; | |
9488a030 SS |
5374 | |
5375 | if (drm_dp_dpcd_writeb(&intel_dp->aux, | |
b6dfa416 | 5376 | DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) |
6496dbec | 5377 | return reprobe_needed; |
9488a030 SS |
5378 | |
5379 | if (val & HDMI_LINK_STATUS_CHANGED) | |
5380 | intel_dp_handle_hdmi_link_status_change(intel_dp); | |
6496dbec ID |
5381 | |
5382 | return reprobe_needed; | |
9488a030 SS |
5383 | } |
5384 | ||
a4fc5ed6 KP |
5385 | /* |
5386 | * According to DP spec | |
5387 | * 5.1.2: | |
5388 | * 1. Read DPCD | |
5389 | * 2. Configure link according to Receiver Capabilities | |
5390 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
5391 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
5392 | * |
5393 | * intel_dp_short_pulse - handles short pulse interrupts | |
5394 | * when full detection is not required. | |
5395 | * Returns %true if short pulse is handled and full detection | |
5396 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 5397 | */ |
39ff747b | 5398 | static bool |
5c9114d0 | 5399 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 5400 | { |
de25eb7f | 5401 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
39ff747b | 5402 | u8 old_sink_count = intel_dp->sink_count; |
6496dbec | 5403 | bool reprobe_needed = false; |
39ff747b | 5404 | bool ret; |
5b215bcf | 5405 | |
4df6960e SS |
5406 | /* |
5407 | * Clearing compliance test variables to allow capturing | |
5408 | * of values for next automated test request. | |
5409 | */ | |
c1617abc | 5410 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 5411 | |
39ff747b SS |
5412 | /* |
5413 | * Now read the DPCD to see if it's actually running | |
5414 | * If the current value of sink count doesn't match with | |
5415 | * the value that was stored earlier or dpcd read failed | |
5416 | * we need to do full detection | |
5417 | */ | |
5418 | ret = intel_dp_get_dpcd(intel_dp); | |
5419 | ||
5420 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
5421 | /* No need to proceed if we are going to do full detect */ | |
5422 | return false; | |
59cd09e1 JB |
5423 | } |
5424 | ||
9488a030 | 5425 | intel_dp_check_device_service_irq(intel_dp); |
6496dbec | 5426 | reprobe_needed = intel_dp_check_link_service_irq(intel_dp); |
a60f0e38 | 5427 | |
82e00d11 HV |
5428 | /* Handle CEC interrupts, if any */ |
5429 | drm_dp_cec_irq(&intel_dp->aux); | |
5430 | ||
c85d200e VS |
5431 | /* defer to the hotplug work for link retraining if needed */ |
5432 | if (intel_dp_needs_link_retrain(intel_dp)) | |
5433 | return false; | |
42e5e657 | 5434 | |
cc3054ff JRS |
5435 | intel_psr_short_pulse(intel_dp); |
5436 | ||
193af12c VS |
5437 | switch (intel_dp->compliance.test_type) { |
5438 | case DP_TEST_LINK_TRAINING: | |
bdc6114e WK |
5439 | drm_dbg_kms(&dev_priv->drm, |
5440 | "Link Training Compliance Test requested\n"); | |
da15f7cb | 5441 | /* Send a Hotplug Uevent to userspace to start modeset */ |
2f773477 | 5442 | drm_kms_helper_hotplug_event(&dev_priv->drm); |
193af12c VS |
5443 | break; |
5444 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
5445 | drm_dbg_kms(&dev_priv->drm, | |
5446 | "PHY test pattern Compliance Test requested\n"); | |
5447 | /* | |
5448 | * Schedule long hpd to do the test | |
5449 | * | |
5450 | * FIXME get rid of the ad-hoc phy test modeset code | |
5451 | * and properly incorporate it into the normal modeset. | |
5452 | */ | |
6496dbec | 5453 | reprobe_needed = true; |
da15f7cb | 5454 | } |
39ff747b | 5455 | |
6496dbec | 5456 | return !reprobe_needed; |
a4fc5ed6 | 5457 | } |
a4fc5ed6 | 5458 | |
caf9ab24 | 5459 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 5460 | static enum drm_connector_status |
26d61aad | 5461 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 5462 | { |
af67009c | 5463 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
f542d671 | 5464 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
830de422 JN |
5465 | u8 *dpcd = intel_dp->dpcd; |
5466 | u8 type; | |
caf9ab24 | 5467 | |
4f360482 | 5468 | if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) |
ad5125d6 ID |
5469 | return connector_status_connected; |
5470 | ||
f542d671 | 5471 | lspcon_resume(dig_port); |
e393d0d6 | 5472 | |
caf9ab24 AJ |
5473 | if (!intel_dp_get_dpcd(intel_dp)) |
5474 | return connector_status_disconnected; | |
5475 | ||
2e9720e9 | 5476 | intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); |
20fbb14b | 5477 | |
caf9ab24 | 5478 | /* if there's no downstream port, we're done */ |
c726ad01 | 5479 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 5480 | return connector_status_connected; |
caf9ab24 AJ |
5481 | |
5482 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
693c3ec5 | 5483 | if (intel_dp_has_sink_count(intel_dp) && |
c9ff160b | 5484 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
30d9aa42 SS |
5485 | return intel_dp->sink_count ? |
5486 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
5487 | } |
5488 | ||
2e9720e9 | 5489 | if (intel_dp->mst_detect == DRM_DP_MST) |
c4e3170a VS |
5490 | return connector_status_connected; |
5491 | ||
caf9ab24 | 5492 | /* If no HPD, poke DDC gently */ |
0b99836f | 5493 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 5494 | return connector_status_connected; |
caf9ab24 AJ |
5495 | |
5496 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
5497 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
5498 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
5499 | if (type == DP_DS_PORT_TYPE_VGA || | |
5500 | type == DP_DS_PORT_TYPE_NON_EDID) | |
5501 | return connector_status_unknown; | |
5502 | } else { | |
5503 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
5504 | DP_DWN_STRM_PORT_TYPE_MASK; | |
5505 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
5506 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
5507 | return connector_status_unknown; | |
5508 | } | |
caf9ab24 AJ |
5509 | |
5510 | /* Anything else is out of spec, warn and ignore */ | |
af67009c | 5511 | drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); |
26d61aad | 5512 | return connector_status_disconnected; |
71ba9000 AJ |
5513 | } |
5514 | ||
d410b56d CW |
5515 | static enum drm_connector_status |
5516 | edp_detect(struct intel_dp *intel_dp) | |
5517 | { | |
b93b41af | 5518 | return connector_status_connected; |
d410b56d CW |
5519 | } |
5520 | ||
9210e94a ID |
5521 | void intel_digital_port_lock(struct intel_encoder *encoder) |
5522 | { | |
5523 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); | |
5524 | ||
5525 | if (dig_port->lock) | |
5526 | dig_port->lock(dig_port); | |
5527 | } | |
5528 | ||
5529 | void intel_digital_port_unlock(struct intel_encoder *encoder) | |
5530 | { | |
5531 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); | |
5532 | ||
5533 | if (dig_port->unlock) | |
5534 | dig_port->unlock(dig_port); | |
5535 | } | |
5536 | ||
7e66bcf2 | 5537 | /* |
9210e94a | 5538 | * intel_digital_port_connected_locked - is the specified port connected? |
7533eb4f | 5539 | * @encoder: intel_encoder |
7e66bcf2 | 5540 | * |
39d1e234 PZ |
5541 | * In cases where there's a connector physically connected but it can't be used |
5542 | * by our hardware we also return false, since the rest of the driver should | |
5543 | * pretty much treat the port as disconnected. This is relevant for type-C | |
5544 | * (starting on ICL) where there's ownership involved. | |
5545 | * | |
9210e94a ID |
5546 | * The caller must hold the lock acquired by calling intel_digital_port_lock() |
5547 | * when calling this function. | |
5548 | * | |
7533eb4f | 5549 | * Return %true if port is connected, %false otherwise. |
7e66bcf2 | 5550 | */ |
9210e94a | 5551 | bool intel_digital_port_connected_locked(struct intel_encoder *encoder) |
6cfe7ec0 ID |
5552 | { |
5553 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
edc0e09c | 5554 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2e4b90fb | 5555 | bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); |
96ac0813 | 5556 | bool is_connected = false; |
6cfe7ec0 | 5557 | intel_wakeref_t wakeref; |
6cfe7ec0 | 5558 | |
2e4b90fb ID |
5559 | with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) { |
5560 | unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); | |
5561 | ||
5562 | do { | |
5563 | is_connected = dig_port->connected(encoder); | |
5564 | if (is_connected || is_glitch_free) | |
5565 | break; | |
5566 | usleep_range(10, 30); | |
5567 | } while (time_before(jiffies, wait_expires)); | |
5568 | } | |
6cfe7ec0 ID |
5569 | |
5570 | return is_connected; | |
5571 | } | |
5572 | ||
9210e94a ID |
5573 | bool intel_digital_port_connected(struct intel_encoder *encoder) |
5574 | { | |
5575 | bool ret; | |
5576 | ||
5577 | intel_digital_port_lock(encoder); | |
5578 | ret = intel_digital_port_connected_locked(encoder); | |
5579 | intel_digital_port_unlock(encoder); | |
5580 | ||
5581 | return ret; | |
5582 | } | |
5583 | ||
25fa6b0f | 5584 | static const struct drm_edid * |
beb60608 | 5585 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 5586 | { |
15d045fd JN |
5587 | struct intel_connector *connector = intel_dp->attached_connector; |
5588 | const struct drm_edid *fixed_edid = connector->panel.fixed_edid; | |
d6f24d0f | 5589 | |
15d045fd JN |
5590 | /* Use panel fixed edid if we have one */ |
5591 | if (fixed_edid) { | |
9cd300e0 | 5592 | /* invalid edid */ |
15d045fd | 5593 | if (IS_ERR(fixed_edid)) |
d6f24d0f JB |
5594 | return NULL; |
5595 | ||
15d045fd JN |
5596 | return drm_edid_dup(fixed_edid); |
5597 | } | |
5598 | ||
5599 | return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); | |
beb60608 | 5600 | } |
8c241fef | 5601 | |
beb60608 | 5602 | static void |
181567aa | 5603 | intel_dp_update_dfp(struct intel_dp *intel_dp, |
25fa6b0f | 5604 | const struct drm_edid *drm_edid) |
beb60608 | 5605 | { |
530df3c0 VS |
5606 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
5607 | struct intel_connector *connector = intel_dp->attached_connector; | |
530df3c0 VS |
5608 | |
5609 | intel_dp->dfp.max_bpc = | |
5610 | drm_dp_downstream_max_bpc(intel_dp->dpcd, | |
e2272bfb | 5611 | intel_dp->downstream_ports, drm_edid); |
530df3c0 | 5612 | |
fe7cf496 VS |
5613 | intel_dp->dfp.max_dotclock = |
5614 | drm_dp_downstream_max_dotclock(intel_dp->dpcd, | |
5615 | intel_dp->downstream_ports); | |
5616 | ||
3977cd1c VS |
5617 | intel_dp->dfp.min_tmds_clock = |
5618 | drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, | |
5619 | intel_dp->downstream_ports, | |
e2272bfb | 5620 | drm_edid); |
3977cd1c VS |
5621 | intel_dp->dfp.max_tmds_clock = |
5622 | drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, | |
5623 | intel_dp->downstream_ports, | |
e2272bfb | 5624 | drm_edid); |
3977cd1c | 5625 | |
2f78347e AN |
5626 | intel_dp->dfp.pcon_max_frl_bw = |
5627 | drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, | |
5628 | intel_dp->downstream_ports); | |
5629 | ||
fe7cf496 | 5630 | drm_dbg_kms(&i915->drm, |
2f78347e | 5631 | "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", |
530df3c0 | 5632 | connector->base.base.id, connector->base.name, |
3977cd1c VS |
5633 | intel_dp->dfp.max_bpc, |
5634 | intel_dp->dfp.max_dotclock, | |
5635 | intel_dp->dfp.min_tmds_clock, | |
2f78347e AN |
5636 | intel_dp->dfp.max_tmds_clock, |
5637 | intel_dp->dfp.pcon_max_frl_bw); | |
b9d96dac AN |
5638 | |
5639 | intel_dp_get_pcon_dsc_cap(intel_dp); | |
181567aa VS |
5640 | } |
5641 | ||
68910c2a AN |
5642 | static bool |
5643 | intel_dp_can_ycbcr420(struct intel_dp *intel_dp) | |
5644 | { | |
5645 | if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && | |
5646 | (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) | |
5647 | return true; | |
5648 | ||
5649 | if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && | |
5650 | dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) | |
5651 | return true; | |
5652 | ||
5653 | if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && | |
5654 | dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) | |
5655 | return true; | |
5656 | ||
5657 | return false; | |
5658 | } | |
5659 | ||
181567aa VS |
5660 | static void |
5661 | intel_dp_update_420(struct intel_dp *intel_dp) | |
5662 | { | |
5663 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5664 | struct intel_connector *connector = intel_dp->attached_connector; | |
181567aa | 5665 | |
68910c2a | 5666 | intel_dp->dfp.ycbcr420_passthrough = |
181567aa VS |
5667 | drm_dp_downstream_420_passthrough(intel_dp->dpcd, |
5668 | intel_dp->downstream_ports); | |
ebde5f89 | 5669 | /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ |
68910c2a | 5670 | intel_dp->dfp.ycbcr_444_to_420 = |
ebde5f89 | 5671 | dp_to_dig_port(intel_dp)->lspcon.active || |
181567aa VS |
5672 | drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, |
5673 | intel_dp->downstream_ports); | |
68910c2a AN |
5674 | intel_dp->dfp.rgb_to_ycbcr = |
5675 | drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, | |
5676 | intel_dp->downstream_ports, | |
5677 | DP_DS_HDMI_BT709_RGB_YCBCR_CONV); | |
181567aa | 5678 | |
68910c2a | 5679 | connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); |
181567aa VS |
5680 | |
5681 | drm_dbg_kms(&i915->drm, | |
522508b6 | 5682 | "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", |
181567aa | 5683 | connector->base.base.id, connector->base.name, |
01fabda8 LDM |
5684 | str_yes_no(intel_dp->dfp.rgb_to_ycbcr), |
5685 | str_yes_no(connector->base.ycbcr_420_allowed), | |
5686 | str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); | |
181567aa VS |
5687 | } |
5688 | ||
5689 | static void | |
5690 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
5691 | { | |
d999ad10 | 5692 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); |
181567aa | 5693 | struct intel_connector *connector = intel_dp->attached_connector; |
25fa6b0f | 5694 | const struct drm_edid *drm_edid; |
d999ad10 | 5695 | bool vrr_capable; |
181567aa VS |
5696 | |
5697 | intel_dp_unset_edid(intel_dp); | |
25fa6b0f JN |
5698 | drm_edid = intel_dp_get_edid(intel_dp); |
5699 | connector->detect_edid = drm_edid; | |
5700 | ||
5701 | /* Below we depend on display info having been updated */ | |
5702 | drm_edid_connector_update(&connector->base, drm_edid); | |
181567aa | 5703 | |
51ab3b85 | 5704 | vrr_capable = intel_vrr_is_capable(connector); |
d999ad10 MN |
5705 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", |
5706 | connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); | |
5707 | drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); | |
5708 | ||
25fa6b0f | 5709 | intel_dp_update_dfp(intel_dp, drm_edid); |
181567aa | 5710 | intel_dp_update_420(intel_dp); |
beb60608 | 5711 | |
1bc73448 JN |
5712 | drm_dp_cec_attach(&intel_dp->aux, |
5713 | connector->base.display_info.source_physical_address); | |
8c241fef KP |
5714 | } |
5715 | ||
beb60608 CW |
5716 | static void |
5717 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 5718 | { |
181567aa | 5719 | struct intel_connector *connector = intel_dp->attached_connector; |
8c241fef | 5720 | |
82e00d11 | 5721 | drm_dp_cec_unset_edid(&intel_dp->aux); |
25fa6b0f | 5722 | drm_edid_free(connector->detect_edid); |
181567aa | 5723 | connector->detect_edid = NULL; |
9cd300e0 | 5724 | |
530df3c0 | 5725 | intel_dp->dfp.max_bpc = 0; |
fe7cf496 | 5726 | intel_dp->dfp.max_dotclock = 0; |
3977cd1c VS |
5727 | intel_dp->dfp.min_tmds_clock = 0; |
5728 | intel_dp->dfp.max_tmds_clock = 0; | |
181567aa | 5729 | |
2f78347e AN |
5730 | intel_dp->dfp.pcon_max_frl_bw = 0; |
5731 | ||
181567aa VS |
5732 | intel_dp->dfp.ycbcr_444_to_420 = false; |
5733 | connector->base.ycbcr_420_allowed = false; | |
d999ad10 MN |
5734 | |
5735 | drm_connector_set_vrr_capable_property(&connector->base, | |
5736 | false); | |
beb60608 | 5737 | } |
d6f24d0f | 5738 | |
90780a63 | 5739 | static void |
7389829f | 5740 | intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) |
90780a63 ID |
5741 | { |
5742 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
5743 | ||
5744 | /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ | |
5745 | if (!HAS_DSC(i915)) | |
5746 | return; | |
5747 | ||
5748 | if (intel_dp_is_edp(intel_dp)) | |
5749 | intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], | |
02c8d561 | 5750 | connector); |
90780a63 ID |
5751 | else |
5752 | intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], | |
02c8d561 | 5753 | connector); |
90780a63 ID |
5754 | } |
5755 | ||
6c5ed5ae | 5756 | static int |
cbfa8ac8 DP |
5757 | intel_dp_detect(struct drm_connector *connector, |
5758 | struct drm_modeset_acquire_ctx *ctx, | |
5759 | bool force) | |
a9756bb5 | 5760 | { |
cbfa8ac8 | 5761 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
7389829f ID |
5762 | struct intel_connector *intel_connector = |
5763 | to_intel_connector(connector); | |
5764 | struct intel_dp *intel_dp = intel_attached_dp(intel_connector); | |
337837ac ID |
5765 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5766 | struct intel_encoder *encoder = &dig_port->base; | |
a9756bb5 | 5767 | enum drm_connector_status status; |
e60cff45 | 5768 | int ret; |
a9756bb5 | 5769 | |
bdc6114e WK |
5770 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", |
5771 | connector->base.id, connector->name); | |
eb020ca3 PB |
5772 | drm_WARN_ON(&dev_priv->drm, |
5773 | !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); | |
6c5ed5ae | 5774 | |
fe63ea7c | 5775 | if (!intel_display_device_enabled(dev_priv)) |
b81dddb9 VS |
5776 | return connector_status_disconnected; |
5777 | ||
bab87ef4 ID |
5778 | if (!intel_display_driver_check_access(dev_priv)) |
5779 | return connector->status; | |
5780 | ||
b93b41af | 5781 | /* Can't disconnect eDP */ |
1853a9da | 5782 | if (intel_dp_is_edp(intel_dp)) |
d410b56d | 5783 | status = edp_detect(intel_dp); |
d5acd97f | 5784 | else if (intel_digital_port_connected(encoder)) |
c555a81d | 5785 | status = intel_dp_detect_dpcd(intel_dp); |
a9756bb5 | 5786 | else |
c555a81d ACO |
5787 | status = connector_status_disconnected; |
5788 | ||
5cb651a7 | 5789 | if (status == connector_status_disconnected) { |
c1617abc | 5790 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
7389829f | 5791 | memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); |
b8cf5b5d | 5792 | intel_dp->psr.sink_panel_replay_support = false; |
4df6960e | 5793 | |
0a31ed64 | 5794 | intel_dp_mst_disconnect(intel_dp); |
0e505a08 | 5795 | |
e60cff45 ID |
5796 | intel_dp_tunnel_disconnect(intel_dp); |
5797 | ||
c8c8fb33 | 5798 | goto out; |
4df6960e | 5799 | } |
a9756bb5 | 5800 | |
e60cff45 ID |
5801 | ret = intel_dp_tunnel_detect(intel_dp, ctx); |
5802 | if (ret == -EDEADLK) | |
5803 | return ret; | |
5804 | ||
5805 | if (ret == 1) | |
5806 | intel_connector->base.epoch_counter++; | |
5807 | ||
1cca19bf AM |
5808 | if (!intel_dp_is_edp(intel_dp)) |
5809 | intel_psr_init_dpcd(intel_dp); | |
5810 | ||
7389829f | 5811 | intel_dp_detect_dsc_caps(intel_dp, intel_connector); |
80a8cecf | 5812 | |
2e9720e9 | 5813 | intel_dp_mst_configure(intel_dp); |
80a8cecf ID |
5814 | |
5815 | /* | |
5816 | * TODO: Reset link params when switching to MST mode, until MST | |
5817 | * supports link training fallback params. | |
5818 | */ | |
5819 | if (intel_dp->reset_link_params || intel_dp->is_mst) { | |
9ad87de4 | 5820 | intel_dp_reset_max_link_params(intel_dp); |
d7e8ef02 MN |
5821 | intel_dp->reset_link_params = false; |
5822 | } | |
f482984a | 5823 | |
fe5a66f9 VS |
5824 | intel_dp_print_rates(intel_dp); |
5825 | ||
c4e3170a | 5826 | if (intel_dp->is_mst) { |
f21a2198 SS |
5827 | /* |
5828 | * If we are in MST mode then this connector | |
5829 | * won't appear connected or have anything | |
5830 | * with EDID on it | |
5831 | */ | |
0e32b39c DA |
5832 | status = connector_status_disconnected; |
5833 | goto out; | |
f24f6eb9 DP |
5834 | } |
5835 | ||
5836 | /* | |
5837 | * Some external monitors do not signal loss of link synchronization | |
5838 | * with an IRQ_HPD, so force a link status check. | |
5839 | */ | |
47658556 | 5840 | if (!intel_dp_is_edp(intel_dp)) { |
47658556 | 5841 | ret = intel_dp_retrain_link(encoder, ctx); |
6cfe7ec0 | 5842 | if (ret) |
47658556 | 5843 | return ret; |
47658556 | 5844 | } |
0e32b39c | 5845 | |
4df6960e SS |
5846 | /* |
5847 | * Clearing NACK and defer counts to get their exact values | |
5848 | * while reading EDID which are required by Compliance tests | |
5849 | * 4.2.2.4 and 4.2.2.5 | |
5850 | */ | |
5851 | intel_dp->aux.i2c_nack_count = 0; | |
5852 | intel_dp->aux.i2c_defer_count = 0; | |
5853 | ||
beb60608 | 5854 | intel_dp_set_edid(intel_dp); |
cbfa8ac8 DP |
5855 | if (intel_dp_is_edp(intel_dp) || |
5856 | to_intel_connector(connector)->detect_edid) | |
5cb651a7 | 5857 | status = connector_status_connected; |
c8c8fb33 | 5858 | |
9488a030 | 5859 | intel_dp_check_device_service_irq(intel_dp); |
09b1eb13 | 5860 | |
c8c8fb33 | 5861 | out: |
5cb651a7 | 5862 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 5863 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 5864 | |
fb823134 OV |
5865 | if (!intel_dp_is_edp(intel_dp)) |
5866 | drm_dp_set_subconnector_property(connector, | |
5867 | status, | |
5868 | intel_dp->dpcd, | |
5869 | intel_dp->downstream_ports); | |
5cb651a7 | 5870 | return status; |
f21a2198 SS |
5871 | } |
5872 | ||
beb60608 CW |
5873 | static void |
5874 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 5875 | { |
43a6d19c | 5876 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
337837ac ID |
5877 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5878 | struct intel_encoder *intel_encoder = &dig_port->base; | |
25f78f58 | 5879 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
a4fc5ed6 | 5880 | |
bdc6114e WK |
5881 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", |
5882 | connector->base.id, connector->name); | |
bab87ef4 ID |
5883 | |
5884 | if (!intel_display_driver_check_access(dev_priv)) | |
5885 | return; | |
5886 | ||
beb60608 | 5887 | intel_dp_unset_edid(intel_dp); |
a4fc5ed6 | 5888 | |
beb60608 CW |
5889 | if (connector->status != connector_status_connected) |
5890 | return; | |
671dedd2 | 5891 | |
beb60608 | 5892 | intel_dp_set_edid(intel_dp); |
beb60608 CW |
5893 | } |
5894 | ||
5895 | static int intel_dp_get_modes(struct drm_connector *connector) | |
5896 | { | |
5897 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
25fa6b0f | 5898 | int num_modes; |
beb60608 | 5899 | |
25fa6b0f JN |
5900 | /* drm_edid_connector_update() done in ->detect() or ->force() */ |
5901 | num_modes = drm_edid_connector_add_modes(connector); | |
390a1f8b | 5902 | |
f8862617 | 5903 | /* Also add fixed mode, which may or may not be present in EDID */ |
53f64f3a VS |
5904 | if (intel_dp_is_edp(intel_attached_dp(intel_connector))) |
5905 | num_modes += intel_panel_get_modes(intel_connector); | |
beb60608 | 5906 | |
f8862617 JN |
5907 | if (num_modes) |
5908 | return num_modes; | |
5909 | ||
25fa6b0f | 5910 | if (!intel_connector->detect_edid) { |
4b3bb839 VS |
5911 | struct intel_dp *intel_dp = intel_attached_dp(intel_connector); |
5912 | struct drm_display_mode *mode; | |
5913 | ||
5914 | mode = drm_dp_downstream_mode(connector->dev, | |
5915 | intel_dp->dpcd, | |
5916 | intel_dp->downstream_ports); | |
5917 | if (mode) { | |
5918 | drm_mode_probed_add(connector, mode); | |
f8862617 | 5919 | num_modes++; |
4b3bb839 VS |
5920 | } |
5921 | } | |
5922 | ||
f8862617 | 5923 | return num_modes; |
a4fc5ed6 KP |
5924 | } |
5925 | ||
7a418e34 CW |
5926 | static int |
5927 | intel_dp_connector_register(struct drm_connector *connector) | |
5928 | { | |
af67009c | 5929 | struct drm_i915_private *i915 = to_i915(connector->dev); |
43a6d19c | 5930 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
2e666613 US |
5931 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5932 | struct intel_lspcon *lspcon = &dig_port->lspcon; | |
1ebaa0b9 CW |
5933 | int ret; |
5934 | ||
5935 | ret = intel_connector_register(connector); | |
5936 | if (ret) | |
5937 | return ret; | |
7a418e34 | 5938 | |
af67009c JN |
5939 | drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", |
5940 | intel_dp->aux.name, connector->kdev->kobj.name); | |
7a418e34 CW |
5941 | |
5942 | intel_dp->aux.dev = connector->kdev; | |
82e00d11 HV |
5943 | ret = drm_dp_aux_register(&intel_dp->aux); |
5944 | if (!ret) | |
ae85b0df | 5945 | drm_dp_cec_register_connector(&intel_dp->aux, connector); |
2e666613 | 5946 | |
db5d650f | 5947 | if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) |
2e666613 US |
5948 | return ret; |
5949 | ||
5950 | /* | |
5951 | * ToDo: Clean this up to handle lspcon init and resume more | |
5952 | * efficiently and streamlined. | |
5953 | */ | |
5954 | if (lspcon_init(dig_port)) { | |
5955 | lspcon_detect_hdr_capability(lspcon); | |
5956 | if (lspcon->hdr_supported) | |
e97798e2 | 5957 | drm_connector_attach_hdr_output_metadata_property(connector); |
2e666613 US |
5958 | } |
5959 | ||
82e00d11 | 5960 | return ret; |
7a418e34 CW |
5961 | } |
5962 | ||
c191eca1 CW |
5963 | static void |
5964 | intel_dp_connector_unregister(struct drm_connector *connector) | |
5965 | { | |
43a6d19c | 5966 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); |
82e00d11 HV |
5967 | |
5968 | drm_dp_cec_unregister_connector(&intel_dp->aux); | |
5969 | drm_dp_aux_unregister(&intel_dp->aux); | |
c191eca1 CW |
5970 | intel_connector_unregister(connector); |
5971 | } | |
5972 | ||
a62e1459 ID |
5973 | void intel_dp_connector_sync_state(struct intel_connector *connector, |
5974 | const struct intel_crtc_state *crtc_state) | |
5975 | { | |
5976 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
5977 | ||
5978 | if (crtc_state && crtc_state->dsc.compression_enable) { | |
5979 | drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux); | |
5980 | connector->dp.dsc_decompression_enabled = true; | |
5981 | } else { | |
5982 | connector->dp.dsc_decompression_enabled = false; | |
5983 | } | |
5984 | } | |
5985 | ||
f6bff60e | 5986 | void intel_dp_encoder_flush_work(struct drm_encoder *encoder) |
24d05927 | 5987 | { |
7801f3b7 LDM |
5988 | struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); |
5989 | struct intel_dp *intel_dp = &dig_port->dp; | |
24d05927 | 5990 | |
7801f3b7 | 5991 | intel_dp_mst_encoder_cleanup(dig_port); |
69d93820 | 5992 | |
e60cff45 ID |
5993 | intel_dp_tunnel_destroy(intel_dp); |
5994 | ||
f033d7eb | 5995 | intel_pps_vdd_off_sync(intel_dp); |
99681886 | 5996 | |
36d35716 JN |
5997 | /* |
5998 | * Ensure power off delay is respected on module remove, so that we can | |
5999 | * reduce delays at driver probe. See pps_init_timestamps(). | |
6000 | */ | |
6001 | intel_pps_wait_power_cycle(intel_dp); | |
6002 | ||
99681886 | 6003 | intel_dp_aux_fini(intel_dp); |
f6bff60e ID |
6004 | } |
6005 | ||
bf93ba67 | 6006 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b | 6007 | { |
b7d02c3a | 6008 | struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); |
07f9cd0b | 6009 | |
f033d7eb | 6010 | intel_pps_vdd_off_sync(intel_dp); |
fb687904 ID |
6011 | |
6012 | intel_dp_tunnel_suspend(intel_dp); | |
07f9cd0b ID |
6013 | } |
6014 | ||
e219ef91 | 6015 | void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) |
063348f6 VS |
6016 | { |
6017 | struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); | |
063348f6 | 6018 | |
572a0d30 | 6019 | intel_pps_wait_power_cycle(intel_dp); |
063348f6 VS |
6020 | } |
6021 | ||
e24bcd34 MN |
6022 | static int intel_modeset_tile_group(struct intel_atomic_state *state, |
6023 | int tile_group_id) | |
6024 | { | |
6025 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
6026 | struct drm_connector_list_iter conn_iter; | |
6027 | struct drm_connector *connector; | |
6028 | int ret = 0; | |
6029 | ||
6030 | drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); | |
6031 | drm_for_each_connector_iter(connector, &conn_iter) { | |
6032 | struct drm_connector_state *conn_state; | |
6033 | struct intel_crtc_state *crtc_state; | |
6034 | struct intel_crtc *crtc; | |
6035 | ||
6036 | if (!connector->has_tile || | |
6037 | connector->tile_group->id != tile_group_id) | |
6038 | continue; | |
6039 | ||
6040 | conn_state = drm_atomic_get_connector_state(&state->base, | |
6041 | connector); | |
6042 | if (IS_ERR(conn_state)) { | |
6043 | ret = PTR_ERR(conn_state); | |
6044 | break; | |
6045 | } | |
6046 | ||
6047 | crtc = to_intel_crtc(conn_state->crtc); | |
6048 | ||
6049 | if (!crtc) | |
6050 | continue; | |
6051 | ||
6052 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); | |
6053 | crtc_state->uapi.mode_changed = true; | |
6054 | ||
6055 | ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); | |
6056 | if (ret) | |
6057 | break; | |
6058 | } | |
b7079cbd | 6059 | drm_connector_list_iter_end(&conn_iter); |
e24bcd34 MN |
6060 | |
6061 | return ret; | |
6062 | } | |
6063 | ||
6064 | static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) | |
6065 | { | |
6066 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
6067 | struct intel_crtc *crtc; | |
6068 | ||
6069 | if (transcoders == 0) | |
6070 | return 0; | |
6071 | ||
6072 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
6073 | struct intel_crtc_state *crtc_state; | |
6074 | int ret; | |
6075 | ||
6076 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
6077 | if (IS_ERR(crtc_state)) | |
6078 | return PTR_ERR(crtc_state); | |
6079 | ||
6080 | if (!crtc_state->hw.enable) | |
6081 | continue; | |
6082 | ||
6083 | if (!(transcoders & BIT(crtc_state->cpu_transcoder))) | |
6084 | continue; | |
6085 | ||
6086 | crtc_state->uapi.mode_changed = true; | |
6087 | ||
6088 | ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); | |
6089 | if (ret) | |
6090 | return ret; | |
6091 | ||
6092 | ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); | |
6093 | if (ret) | |
6094 | return ret; | |
6095 | ||
6096 | transcoders &= ~BIT(crtc_state->cpu_transcoder); | |
6097 | } | |
6098 | ||
eb020ca3 | 6099 | drm_WARN_ON(&dev_priv->drm, transcoders != 0); |
e24bcd34 MN |
6100 | |
6101 | return 0; | |
6102 | } | |
6103 | ||
6104 | static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, | |
6105 | struct drm_connector *connector) | |
6106 | { | |
6107 | const struct drm_connector_state *old_conn_state = | |
6108 | drm_atomic_get_old_connector_state(&state->base, connector); | |
6109 | const struct intel_crtc_state *old_crtc_state; | |
6110 | struct intel_crtc *crtc; | |
6111 | u8 transcoders; | |
6112 | ||
6113 | crtc = to_intel_crtc(old_conn_state->crtc); | |
6114 | if (!crtc) | |
6115 | return 0; | |
6116 | ||
6117 | old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); | |
6118 | ||
6119 | if (!old_crtc_state->hw.active) | |
6120 | return 0; | |
6121 | ||
6122 | transcoders = old_crtc_state->sync_mode_slaves_mask; | |
6123 | if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) | |
6124 | transcoders |= BIT(old_crtc_state->master_transcoder); | |
6125 | ||
6126 | return intel_modeset_affected_transcoders(state, | |
6127 | transcoders); | |
6128 | } | |
6129 | ||
6130 | static int intel_dp_connector_atomic_check(struct drm_connector *conn, | |
6131 | struct drm_atomic_state *_state) | |
6132 | { | |
6133 | struct drm_i915_private *dev_priv = to_i915(conn->dev); | |
6134 | struct intel_atomic_state *state = to_intel_atomic_state(_state); | |
a76eb429 LP |
6135 | struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn); |
6136 | struct intel_connector *intel_conn = to_intel_connector(conn); | |
6137 | struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); | |
e24bcd34 MN |
6138 | int ret; |
6139 | ||
6140 | ret = intel_digital_connector_atomic_check(conn, &state->base); | |
6141 | if (ret) | |
6142 | return ret; | |
6143 | ||
a76eb429 LP |
6144 | if (intel_dp_mst_source_support(intel_dp)) { |
6145 | ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); | |
6146 | if (ret) | |
6147 | return ret; | |
6148 | } | |
6149 | ||
a4efae87 ID |
6150 | if (!intel_connector_needs_modeset(state, conn)) |
6151 | return 0; | |
6152 | ||
6153 | ret = intel_dp_tunnel_atomic_check_state(state, | |
6154 | intel_dp, | |
6155 | intel_conn); | |
6156 | if (ret) | |
6157 | return ret; | |
6158 | ||
dc5b8ed5 VS |
6159 | /* |
6160 | * We don't enable port sync on BDW due to missing w/as and | |
6161 | * due to not having adjusted the modeset sequence appropriately. | |
6162 | */ | |
005e9537 | 6163 | if (DISPLAY_VER(dev_priv) < 9) |
e24bcd34 MN |
6164 | return 0; |
6165 | ||
e24bcd34 MN |
6166 | if (conn->has_tile) { |
6167 | ret = intel_modeset_tile_group(state, conn->tile_group->id); | |
6168 | if (ret) | |
6169 | return ret; | |
6170 | } | |
6171 | ||
6172 | return intel_modeset_synced_crtcs(state, conn); | |
6173 | } | |
6174 | ||
fc93835b BA |
6175 | static void intel_dp_oob_hotplug_event(struct drm_connector *connector, |
6176 | enum drm_connector_status hpd_state) | |
4e79e12f HG |
6177 | { |
6178 | struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); | |
6179 | struct drm_i915_private *i915 = to_i915(connector->dev); | |
fc93835b BA |
6180 | bool hpd_high = hpd_state == connector_status_connected; |
6181 | unsigned int hpd_pin = encoder->hpd_pin; | |
6182 | bool need_work = false; | |
4e79e12f HG |
6183 | |
6184 | spin_lock_irq(&i915->irq_lock); | |
fc93835b BA |
6185 | if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) { |
6186 | i915->display.hotplug.event_bits |= BIT(hpd_pin); | |
6187 | ||
6188 | __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high); | |
6189 | need_work = true; | |
6190 | } | |
4e79e12f | 6191 | spin_unlock_irq(&i915->irq_lock); |
fc93835b BA |
6192 | |
6193 | if (need_work) | |
0ea5c948 | 6194 | intel_hpd_schedule_detection(i915); |
4e79e12f HG |
6195 | } |
6196 | ||
a4fc5ed6 | 6197 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
beb60608 | 6198 | .force = intel_dp_force, |
a4fc5ed6 | 6199 | .fill_modes = drm_helper_probe_single_connector_modes, |
8f647a01 ML |
6200 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
6201 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
7a418e34 | 6202 | .late_register = intel_dp_connector_register, |
c191eca1 | 6203 | .early_unregister = intel_dp_connector_unregister, |
d4b26e4f | 6204 | .destroy = intel_connector_destroy, |
c6f95f27 | 6205 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
8f647a01 | 6206 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
4e79e12f | 6207 | .oob_hotplug_event = intel_dp_oob_hotplug_event, |
a4fc5ed6 KP |
6208 | }; |
6209 | ||
6210 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
6c5ed5ae | 6211 | .detect_ctx = intel_dp_detect, |
a4fc5ed6 KP |
6212 | .get_modes = intel_dp_get_modes, |
6213 | .mode_valid = intel_dp_mode_valid, | |
e24bcd34 | 6214 | .atomic_check = intel_dp_connector_atomic_check, |
a4fc5ed6 KP |
6215 | }; |
6216 | ||
b2c5c181 | 6217 | enum irqreturn |
7801f3b7 | 6218 | intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) |
13cf5504 | 6219 | { |
7801f3b7 LDM |
6220 | struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); |
6221 | struct intel_dp *intel_dp = &dig_port->dp; | |
a32f3a95 | 6222 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
1c767b33 | 6223 | |
7801f3b7 | 6224 | if (dig_port->base.type == INTEL_OUTPUT_EDP && |
8f0c1c09 | 6225 | (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) { |
7a7f84cc | 6226 | /* |
13ea6db2 | 6227 | * vdd off can generate a long/short pulse on eDP which |
7a7f84cc VS |
6228 | * would require vdd on to handle it, and thus we |
6229 | * would end up in an endless cycle of | |
13ea6db2 | 6230 | * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." |
7a7f84cc | 6231 | */ |
af67009c JN |
6232 | drm_dbg_kms(&i915->drm, |
6233 | "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", | |
6234 | long_hpd ? "long" : "short", | |
7801f3b7 LDM |
6235 | dig_port->base.base.base.id, |
6236 | dig_port->base.base.name); | |
a8b3d52f | 6237 | return IRQ_HANDLED; |
7a7f84cc VS |
6238 | } |
6239 | ||
af67009c | 6240 | drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", |
7801f3b7 LDM |
6241 | dig_port->base.base.base.id, |
6242 | dig_port->base.base.name, | |
af67009c | 6243 | long_hpd ? "long" : "short"); |
13cf5504 | 6244 | |
a32f3a95 ID |
6245 | /* |
6246 | * TBT DP tunnels require the GFX driver to read out the DPRX caps in | |
6247 | * response to long HPD pulses. The DP hotplug handler does that, | |
6248 | * however the hotplug handler may be blocked by another | |
6249 | * connector's/encoder's hotplug handler. Since the TBT CM may not | |
6250 | * complete the DP tunnel BW request for the latter connector/encoder | |
6251 | * waiting for this encoder's DPRX read, perform a dummy read here. | |
6252 | */ | |
6253 | if (long_hpd) | |
6254 | intel_dp_read_dprx_caps(intel_dp, dpcd); | |
6255 | ||
27d4efc5 | 6256 | if (long_hpd) { |
d7e8ef02 | 6257 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
6258 | return IRQ_NONE; |
6259 | } | |
6260 | ||
27d4efc5 | 6261 | if (intel_dp->is_mst) { |
8d712a7e | 6262 | if (!intel_dp_check_mst_status(intel_dp)) |
6f08ebe7 | 6263 | return IRQ_NONE; |
8d712a7e ID |
6264 | } else if (!intel_dp_short_pulse(intel_dp)) { |
6265 | return IRQ_NONE; | |
0e32b39c | 6266 | } |
b2c5c181 | 6267 | |
6f08ebe7 | 6268 | return IRQ_HANDLED; |
13cf5504 DA |
6269 | } |
6270 | ||
9d4b7af5 VS |
6271 | static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv, |
6272 | const struct intel_bios_encoder_data *devdata, | |
6273 | enum port port) | |
36e83a18 | 6274 | { |
53ce81a7 VS |
6275 | /* |
6276 | * eDP not supported on g4x. so bail out early just | |
6277 | * for a bit extra safety in case the VBT is bonkers. | |
6278 | */ | |
005e9537 | 6279 | if (DISPLAY_VER(dev_priv) < 5) |
53ce81a7 VS |
6280 | return false; |
6281 | ||
005e9537 | 6282 | if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
6283 | return true; |
6284 | ||
9d4b7af5 VS |
6285 | return devdata && intel_bios_encoder_supports_edp(devdata); |
6286 | } | |
6287 | ||
6288 | bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port) | |
6289 | { | |
6290 | const struct intel_bios_encoder_data *devdata = | |
6291 | intel_bios_encoder_data_lookup(i915, port); | |
6292 | ||
6293 | return _intel_dp_is_port_edp(i915, devdata, port); | |
36e83a18 ZY |
6294 | } |
6295 | ||
7e4e0e5c | 6296 | static bool |
db5d650f | 6297 | has_gamut_metadata_dip(struct intel_encoder *encoder) |
7e4e0e5c | 6298 | { |
db5d650f VS |
6299 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
6300 | enum port port = encoder->port; | |
6301 | ||
6302 | if (intel_bios_encoder_is_lspcon(encoder->devdata)) | |
7e4e0e5c US |
6303 | return false; |
6304 | ||
6305 | if (DISPLAY_VER(i915) >= 11) | |
6306 | return true; | |
6307 | ||
6308 | if (port == PORT_A) | |
6309 | return false; | |
6310 | ||
6311 | if (IS_HASWELL(i915) || IS_BROADWELL(i915) || | |
6312 | DISPLAY_VER(i915) >= 9) | |
6313 | return true; | |
6314 | ||
6315 | return false; | |
6316 | } | |
6317 | ||
200819ab | 6318 | static void |
f684960e CW |
6319 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
6320 | { | |
8b45330a | 6321 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
68ec0736 VS |
6322 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
6323 | ||
fb823134 OV |
6324 | if (!intel_dp_is_edp(intel_dp)) |
6325 | drm_connector_attach_dp_subconnector_property(connector); | |
6326 | ||
68ec0736 VS |
6327 | if (!IS_G4X(dev_priv) && port != PORT_A) |
6328 | intel_attach_force_audio_property(connector); | |
8b45330a | 6329 | |
e953fd7b | 6330 | intel_attach_broadcast_rgb_property(connector); |
b2ae318a | 6331 | if (HAS_GMCH(dev_priv)) |
f1a12172 | 6332 | drm_connector_attach_max_bpc_property(connector, 6, 10); |
005e9537 | 6333 | else if (DISPLAY_VER(dev_priv) >= 5) |
f1a12172 | 6334 | drm_connector_attach_max_bpc_property(connector, 6, 12); |
53b41837 | 6335 | |
5d36f2b2 | 6336 | /* Register HDMI colorspace for case of lspcon */ |
db5d650f | 6337 | if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { |
b9836757 | 6338 | drm_connector_attach_content_type_property(connector); |
5d36f2b2 US |
6339 | intel_attach_hdmi_colorspace_property(connector); |
6340 | } else { | |
6341 | intel_attach_dp_colorspace_property(connector); | |
6342 | } | |
9d1bb6f0 | 6343 | |
db5d650f | 6344 | if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) |
e97798e2 | 6345 | drm_connector_attach_hdr_output_metadata_property(connector); |
0299dfa7 | 6346 | |
3dafe8a8 AS |
6347 | if (HAS_VRR(dev_priv)) |
6348 | drm_connector_attach_vrr_capable_property(connector); | |
f684960e CW |
6349 | } |
6350 | ||
e9ebf135 | 6351 | static void |
f6d39f56 | 6352 | intel_edp_add_properties(struct intel_dp *intel_dp) |
e9ebf135 VS |
6353 | { |
6354 | struct intel_connector *connector = intel_dp->attached_connector; | |
6355 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
f6d39f56 VS |
6356 | const struct drm_display_mode *fixed_mode = |
6357 | intel_panel_preferred_fixed_mode(connector); | |
ab6214f3 | 6358 | |
6ac2f04b | 6359 | intel_attach_scaling_mode_property(&connector->base); |
e9ebf135 | 6360 | |
e9ebf135 | 6361 | drm_connector_set_panel_orientation_with_quirk(&connector->base, |
a434689c | 6362 | i915->display.vbt.orientation, |
e9ebf135 VS |
6363 | fixed_mode->hdisplay, |
6364 | fixed_mode->vdisplay); | |
6365 | } | |
6366 | ||
6f7dd8e7 VS |
6367 | static void intel_edp_backlight_setup(struct intel_dp *intel_dp, |
6368 | struct intel_connector *connector) | |
6369 | { | |
6370 | struct drm_i915_private *i915 = dp_to_i915(intel_dp); | |
6371 | enum pipe pipe = INVALID_PIPE; | |
6372 | ||
6373 | if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { | |
6374 | /* | |
6375 | * Figure out the current pipe for the initial backlight setup. | |
6376 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
6377 | * fails just assume pipe A. | |
6378 | */ | |
6379 | pipe = vlv_active_pipe(intel_dp); | |
6380 | ||
6381 | if (pipe != PIPE_A && pipe != PIPE_B) | |
6382 | pipe = intel_dp->pps.pps_pipe; | |
6383 | ||
6384 | if (pipe != PIPE_A && pipe != PIPE_B) | |
6385 | pipe = PIPE_A; | |
6f7dd8e7 VS |
6386 | } |
6387 | ||
6388 | intel_backlight_setup(connector, pipe); | |
6389 | } | |
6390 | ||
ed92f0b2 | 6391 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 6392 | struct intel_connector *intel_connector) |
ed92f0b2 | 6393 | { |
de25eb7f | 6394 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
2f773477 | 6395 | struct drm_connector *connector = &intel_connector->base; |
db10c14a | 6396 | struct drm_display_mode *fixed_mode; |
6434cf63 | 6397 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
ed92f0b2 | 6398 | bool has_dpcd; |
25fa6b0f | 6399 | const struct drm_edid *drm_edid; |
ed92f0b2 | 6400 | |
1853a9da | 6401 | if (!intel_dp_is_edp(intel_dp)) |
ed92f0b2 PZ |
6402 | return true; |
6403 | ||
97a824e1 ID |
6404 | /* |
6405 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
6406 | * driver uses the only internal power sequencer available for both | |
6407 | * eDP and LVDS bail out early in this case to prevent interfering | |
6408 | * with an already powered-on LVDS power sequencer. | |
6409 | */ | |
17be4942 | 6410 | if (intel_get_lvds_encoder(dev_priv)) { |
3703060d | 6411 | drm_WARN_ON(&dev_priv->drm, |
eb020ca3 | 6412 | !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); |
bdc6114e WK |
6413 | drm_info(&dev_priv->drm, |
6414 | "LVDS was detected, not registering eDP\n"); | |
97a824e1 ID |
6415 | |
6416 | return false; | |
6417 | } | |
6418 | ||
3f9ffce5 VS |
6419 | intel_bios_init_panel_early(dev_priv, &intel_connector->panel, |
6420 | encoder->devdata); | |
6421 | ||
ba21bb24 VS |
6422 | if (!intel_pps_init(intel_dp)) { |
6423 | drm_info(&dev_priv->drm, | |
6424 | "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", | |
6425 | encoder->base.base.id, encoder->base.name); | |
6426 | /* | |
6427 | * The BIOS may have still enabled VDD on the PPS even | |
6428 | * though it's unusable. Make sure we turn it back off | |
6429 | * and to release the power domain references/etc. | |
6430 | */ | |
6431 | goto out_vdd_off; | |
6432 | } | |
63635217 | 6433 | |
cfe5bdfb VS |
6434 | /* |
6435 | * Enable HPD sense for live status check. | |
6436 | * intel_hpd_irq_setup() will turn it off again | |
6437 | * if it's no longer needed later. | |
6438 | * | |
6439 | * The DPCD probe below will make sure VDD is on. | |
6440 | */ | |
6441 | intel_hpd_enable_detection(encoder); | |
6442 | ||
ed92f0b2 | 6443 | /* Cache DPCD and EDID for edp. */ |
7389829f | 6444 | has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector); |
ed92f0b2 | 6445 | |
fe5a66f9 | 6446 | if (!has_dpcd) { |
ed92f0b2 | 6447 | /* if this fails, presume the device is a ghost */ |
bdc6114e | 6448 | drm_info(&dev_priv->drm, |
bde544e1 VS |
6449 | "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", |
6450 | encoder->base.base.id, encoder->base.name); | |
b4d06ede | 6451 | goto out_vdd_off; |
ed92f0b2 PZ |
6452 | } |
6453 | ||
cfe5bdfb VS |
6454 | /* |
6455 | * VBT and straps are liars. Also check HPD as that seems | |
6456 | * to be the most reliable piece of information available. | |
70052100 VS |
6457 | * |
6458 | * ... expect on devices that forgot to hook HPD up for eDP | |
6459 | * (eg. Acer Chromebook C710), so we'll check it only if multiple | |
6460 | * ports are attempting to use the same AUX CH, according to VBT. | |
cfe5bdfb | 6461 | */ |
fcd479a7 | 6462 | if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { |
cfe5bdfb VS |
6463 | /* |
6464 | * If this fails, presume the DPCD answer came | |
6465 | * from some other port using the same AUX CH. | |
6466 | * | |
6467 | * FIXME maybe cleaner to check this before the | |
6468 | * DPCD read? Would need sort out the VDD handling... | |
6469 | */ | |
fcd479a7 VS |
6470 | if (!intel_digital_port_connected(encoder)) { |
6471 | drm_info(&dev_priv->drm, | |
6472 | "[ENCODER:%d:%s] HPD is down, disabling eDP\n", | |
6473 | encoder->base.base.id, encoder->base.name); | |
6474 | goto out_vdd_off; | |
6475 | } | |
6476 | ||
6477 | /* | |
6478 | * Unfortunately even the HPD based detection fails on | |
6479 | * eg. Asus B360M-A (CFL+CNP), so as a last resort fall | |
6480 | * back to checking for a VGA branch device. Only do this | |
6481 | * on known affected platforms to minimize false positives. | |
6482 | */ | |
6483 | if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) && | |
6484 | (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == | |
6485 | DP_DWN_STRM_PORT_TYPE_ANALOG) { | |
6486 | drm_info(&dev_priv->drm, | |
6487 | "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", | |
6488 | encoder->base.base.id, encoder->base.name); | |
6489 | goto out_vdd_off; | |
6490 | } | |
cfe5bdfb VS |
6491 | } |
6492 | ||
3703060d | 6493 | mutex_lock(&dev_priv->drm.mode_config.mutex); |
84fd1964 | 6494 | drm_edid = drm_edid_read_ddc(connector, connector->ddc); |
25fa6b0f | 6495 | if (!drm_edid) { |
e35d8762 | 6496 | /* Fallback to EDID from ACPI OpRegion, if any */ |
91ec555f JN |
6497 | drm_edid = intel_opregion_get_edid(intel_connector); |
6498 | if (drm_edid) | |
e35d8762 AA |
6499 | drm_dbg_kms(&dev_priv->drm, |
6500 | "[CONNECTOR:%d:%s] Using OpRegion EDID\n", | |
6501 | connector->base.id, connector->name); | |
25fa6b0f JN |
6502 | } |
6503 | if (drm_edid) { | |
6504 | if (drm_edid_connector_update(connector, drm_edid) || | |
6505 | !drm_edid_connector_add_modes(connector)) { | |
6506 | drm_edid_connector_update(connector, NULL); | |
6507 | drm_edid_free(drm_edid); | |
6508 | drm_edid = ERR_PTR(-EINVAL); | |
ed92f0b2 PZ |
6509 | } |
6510 | } else { | |
25fa6b0f | 6511 | drm_edid = ERR_PTR(-ENOENT); |
ed92f0b2 | 6512 | } |
ed92f0b2 | 6513 | |
25fa6b0f | 6514 | intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, |
c36225a1 | 6515 | IS_ERR(drm_edid) ? NULL : drm_edid); |
3cf05076 | 6516 | |
55cfeecc | 6517 | intel_panel_add_edid_fixed_modes(intel_connector, true); |
ed92f0b2 | 6518 | |
948b0ae6 JN |
6519 | /* MSO requires information from the EDID */ |
6520 | intel_edp_mso_init(intel_dp); | |
6521 | ||
512005d9 | 6522 | /* multiply the mode clock and horizontal timings for MSO */ |
db10c14a VS |
6523 | list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head) |
6524 | intel_edp_mso_mode_fixup(intel_connector, fixed_mode); | |
512005d9 | 6525 | |
ed92f0b2 | 6526 | /* fallback to VBT if available for eDP */ |
db10c14a VS |
6527 | if (!intel_panel_preferred_fixed_mode(intel_connector)) |
6528 | intel_panel_add_vbt_lfp_fixed_mode(intel_connector); | |
6529 | ||
3703060d | 6530 | mutex_unlock(&dev_priv->drm.mode_config.mutex); |
ed92f0b2 | 6531 | |
bde544e1 VS |
6532 | if (!intel_panel_preferred_fixed_mode(intel_connector)) { |
6533 | drm_info(&dev_priv->drm, | |
6534 | "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", | |
6535 | encoder->base.base.id, encoder->base.name); | |
6536 | goto out_vdd_off; | |
6537 | } | |
6538 | ||
15d045fd | 6539 | intel_panel_init(intel_connector, drm_edid); |
db10c14a | 6540 | |
6f7dd8e7 | 6541 | intel_edp_backlight_setup(intel_dp, intel_connector); |
ed92f0b2 | 6542 | |
f6d39f56 | 6543 | intel_edp_add_properties(intel_dp); |
9531221d | 6544 | |
8e75e8f5 VS |
6545 | intel_pps_init_late(intel_dp); |
6546 | ||
ed92f0b2 | 6547 | return true; |
b4d06ede ID |
6548 | |
6549 | out_vdd_off: | |
f033d7eb | 6550 | intel_pps_vdd_off_sync(intel_dp); |
b4d06ede ID |
6551 | |
6552 | return false; | |
ed92f0b2 PZ |
6553 | } |
6554 | ||
9301397a MN |
6555 | static void intel_dp_modeset_retry_work_fn(struct work_struct *work) |
6556 | { | |
6557 | struct intel_connector *intel_connector; | |
6558 | struct drm_connector *connector; | |
6559 | ||
6560 | intel_connector = container_of(work, typeof(*intel_connector), | |
6561 | modeset_retry_work); | |
6562 | connector = &intel_connector->base; | |
9d0bfa7a JN |
6563 | drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id, |
6564 | connector->name); | |
9301397a MN |
6565 | |
6566 | /* Grab the locks before changing connector property*/ | |
6567 | mutex_lock(&connector->dev->mode_config.mutex); | |
6568 | /* Set connector link status to BAD and send a Uevent to notify | |
6569 | * userspace to do a modeset. | |
6570 | */ | |
97e14fbe DV |
6571 | drm_connector_set_link_status_property(connector, |
6572 | DRM_MODE_LINK_STATUS_BAD); | |
9301397a MN |
6573 | mutex_unlock(&connector->dev->mode_config.mutex); |
6574 | /* Send Hotplug uevent so userspace can reprobe */ | |
23c50968 | 6575 | drm_kms_helper_connector_hotplug_event(connector); |
d1e217d4 ID |
6576 | |
6577 | drm_connector_put(connector); | |
6578 | } | |
6579 | ||
6580 | void intel_dp_init_modeset_retry_work(struct intel_connector *connector) | |
6581 | { | |
6582 | INIT_WORK(&connector->modeset_retry_work, | |
6583 | intel_dp_modeset_retry_work_fn); | |
9301397a MN |
6584 | } |
6585 | ||
16c25533 | 6586 | bool |
7801f3b7 | 6587 | intel_dp_init_connector(struct intel_digital_port *dig_port, |
f0fec3f2 | 6588 | struct intel_connector *intel_connector) |
a4fc5ed6 | 6589 | { |
f0fec3f2 | 6590 | struct drm_connector *connector = &intel_connector->base; |
7801f3b7 LDM |
6591 | struct intel_dp *intel_dp = &dig_port->dp; |
6592 | struct intel_encoder *intel_encoder = &dig_port->base; | |
f0fec3f2 | 6593 | struct drm_device *dev = intel_encoder->base.dev; |
fac5e23e | 6594 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 6595 | enum port port = intel_encoder->port; |
7a418e34 | 6596 | int type; |
a4fc5ed6 | 6597 | |
9301397a | 6598 | /* Initialize the work for modeset in case of link train failure */ |
d1e217d4 | 6599 | intel_dp_init_modeset_retry_work(intel_connector); |
9301397a | 6600 | |
7801f3b7 | 6601 | if (drm_WARN(dev, dig_port->max_lanes < 1, |
eb020ca3 | 6602 | "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", |
7801f3b7 | 6603 | dig_port->max_lanes, intel_encoder->base.base.id, |
eb020ca3 | 6604 | intel_encoder->base.name)) |
ccb1a831 VS |
6605 | return false; |
6606 | ||
d7e8ef02 | 6607 | intel_dp->reset_link_params = true; |
45f8a8ce JN |
6608 | intel_dp->pps.pps_pipe = INVALID_PIPE; |
6609 | intel_dp->pps.active_pipe = INVALID_PIPE; | |
a4a5d2f8 | 6610 | |
0767935e | 6611 | /* Preserve the current hw state. */ |
b4e33881 | 6612 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); |
dd06f90e | 6613 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 6614 | |
9d4b7af5 | 6615 | if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { |
4e309baf ID |
6616 | /* |
6617 | * Currently we don't support eDP on TypeC ports, although in | |
6618 | * theory it could work on TypeC legacy ports. | |
6619 | */ | |
7fcf7558 | 6620 | drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder)); |
b329530c | 6621 | type = DRM_MODE_CONNECTOR_eDP; |
6fd5a7c9 MA |
6622 | intel_encoder->type = INTEL_OUTPUT_EDP; |
6623 | ||
6624 | /* eDP only on port B and/or C on vlv/chv */ | |
6625 | if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || | |
6626 | IS_CHERRYVIEW(dev_priv)) && | |
6627 | port != PORT_B && port != PORT_C)) | |
6628 | return false; | |
4e309baf | 6629 | } else { |
3b32a35b | 6630 | type = DRM_MODE_CONNECTOR_DisplayPort; |
4e309baf | 6631 | } |
b329530c | 6632 | |
3f61ef97 | 6633 | intel_dp_set_default_sink_rates(intel_dp); |
bedcadda | 6634 | intel_dp_set_default_max_sink_lane_count(intel_dp); |
6fd5a7c9 | 6635 | |
9f2bdb00 | 6636 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
45f8a8ce | 6637 | intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); |
9f2bdb00 | 6638 | |
84fd1964 | 6639 | intel_dp_aux_init(intel_dp); |
7389829f | 6640 | intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; |
84fd1964 | 6641 | |
bdc6114e WK |
6642 | drm_dbg_kms(&dev_priv->drm, |
6643 | "Adding %s connector on [ENCODER:%d:%s]\n", | |
6644 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
6645 | intel_encoder->base.base.id, intel_encoder->base.name); | |
e7281eab | 6646 | |
84fd1964 VS |
6647 | drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs, |
6648 | type, &intel_dp->aux.ddc); | |
a4fc5ed6 KP |
6649 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6650 | ||
f71c9b7b | 6651 | if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12) |
05021389 | 6652 | connector->interlace_allowed = true; |
a4fc5ed6 | 6653 | |
5fb908eb | 6654 | intel_connector->polled = DRM_CONNECTOR_POLL_HPD; |
289d4180 | 6655 | intel_connector->base.polled = intel_connector->polled; |
5432fcaf | 6656 | |
df0e9248 | 6657 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 6658 | |
4f8036a2 | 6659 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
6660 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6661 | else | |
6662 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
7a51a2aa | 6663 | intel_connector->sync_state = intel_dp_connector_sync_state; |
bcbc889b | 6664 | |
36b5f425 | 6665 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 | 6666 | intel_dp_aux_fini(intel_dp); |
a121f4e5 | 6667 | goto fail; |
b2f246a8 | 6668 | } |
32f9d658 | 6669 | |
f09d2b0b VS |
6670 | intel_dp_set_source_rates(intel_dp); |
6671 | intel_dp_set_common_rates(intel_dp); | |
6672 | intel_dp_reset_max_link_params(intel_dp); | |
6673 | ||
6674 | /* init MST on ports that can support it */ | |
6675 | intel_dp_mst_encoder_init(dig_port, | |
6676 | intel_connector->base.base.id); | |
6677 | ||
f684960e | 6678 | intel_dp_add_properties(intel_dp, connector); |
20f24d77 | 6679 | |
fdddd08c | 6680 | if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { |
b23109c5 | 6681 | int ret = intel_dp_hdcp_init(dig_port, intel_connector); |
20f24d77 | 6682 | if (ret) |
bdc6114e WK |
6683 | drm_dbg_kms(&dev_priv->drm, |
6684 | "HDCP init failed, skipping.\n"); | |
20f24d77 | 6685 | } |
f684960e | 6686 | |
00076671 JH |
6687 | intel_dp->colorimetry_support = |
6688 | intel_dp_get_colorimetry_status(intel_dp); | |
6689 | ||
ced42f2d AN |
6690 | intel_dp->frl.is_trained = false; |
6691 | intel_dp->frl.trained_rate_gbps = 0; | |
6692 | ||
b64d6c51 GM |
6693 | intel_psr_init(intel_dp); |
6694 | ||
16c25533 | 6695 | return true; |
a121f4e5 VS |
6696 | |
6697 | fail: | |
f917130f | 6698 | intel_display_power_flush_work(dev_priv); |
a121f4e5 VS |
6699 | drm_connector_cleanup(connector); |
6700 | ||
6701 | return false; | |
a4fc5ed6 | 6702 | } |
f0fec3f2 | 6703 | |
1a4313d1 | 6704 | void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) |
0e32b39c | 6705 | { |
1a4313d1 VS |
6706 | struct intel_encoder *encoder; |
6707 | ||
5df7bd13 JRS |
6708 | if (!HAS_DISPLAY(dev_priv)) |
6709 | return; | |
6710 | ||
1a4313d1 VS |
6711 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
6712 | struct intel_dp *intel_dp; | |
0e32b39c | 6713 | |
1a4313d1 VS |
6714 | if (encoder->type != INTEL_OUTPUT_DDI) |
6715 | continue; | |
5aa56969 | 6716 | |
b7d02c3a | 6717 | intel_dp = enc_to_intel_dp(encoder); |
5aa56969 | 6718 | |
a94a6d76 | 6719 | if (!intel_dp_mst_source_support(intel_dp)) |
0e32b39c DA |
6720 | continue; |
6721 | ||
1a4313d1 VS |
6722 | if (intel_dp->is_mst) |
6723 | drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); | |
0e32b39c DA |
6724 | } |
6725 | } | |
6726 | ||
1a4313d1 | 6727 | void intel_dp_mst_resume(struct drm_i915_private *dev_priv) |
0e32b39c | 6728 | { |
1a4313d1 | 6729 | struct intel_encoder *encoder; |
0e32b39c | 6730 | |
5df7bd13 JRS |
6731 | if (!HAS_DISPLAY(dev_priv)) |
6732 | return; | |
6733 | ||
1a4313d1 VS |
6734 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
6735 | struct intel_dp *intel_dp; | |
5aa56969 | 6736 | int ret; |
0e32b39c | 6737 | |
1a4313d1 VS |
6738 | if (encoder->type != INTEL_OUTPUT_DDI) |
6739 | continue; | |
6740 | ||
b7d02c3a | 6741 | intel_dp = enc_to_intel_dp(encoder); |
1a4313d1 | 6742 | |
a94a6d76 | 6743 | if (!intel_dp_mst_source_support(intel_dp)) |
5aa56969 | 6744 | continue; |
0e32b39c | 6745 | |
6f85f738 LP |
6746 | ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, |
6747 | true); | |
6be1cf96 LP |
6748 | if (ret) { |
6749 | intel_dp->is_mst = false; | |
6750 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
6751 | false); | |
6752 | } | |
0e32b39c DA |
6753 | } |
6754 | } |