[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_display_device.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2023 Intel Corporation
 */

#ifndef __INTEL_DISPLAY_DEVICE_H__
#define __INTEL_DISPLAY_DEVICE_H__

#include <linux/types.h>

#include "intel_display_limits.h"

struct drm_i915_private;
struct drm_printer;

#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
	/* Keep in alphabetical order */ \
	func(cursor_needs_physical); \
	func(has_cdclk_crawl); \
	func(has_cdclk_squash); \
	func(has_ddi); \
	func(has_dp_mst); \
	func(has_dsb); \
	func(has_fpga_dbg); \
	func(has_gmch); \
	func(has_hotplug); \
	func(has_hti); \
	func(has_ipc); \
	func(has_overlay); \
	func(has_psr); \
	func(has_psr_hw_tracking); \
	func(overlay_needs_physical); \
	func(supports_tv);

#define HAS_4TILE(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)
#define HAS_CDCLK_CRAWL(i915)		(DISPLAY_INFO(i915)->has_cdclk_crawl)
#define HAS_CDCLK_SQUASH(i915)		(DISPLAY_INFO(i915)->has_cdclk_squash)
#define HAS_CUR_FBC(i915)		(!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
#define HAS_DDI(i915)			(DISPLAY_INFO(i915)->has_ddi)
#define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
#define HAS_DMC(i915)			(DISPLAY_RUNTIME_INFO(i915)->has_dmc)
#define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
#define HAS_DP_MST(i915)		(DISPLAY_INFO(i915)->has_dp_mst)
#define HAS_DP20(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)
#define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)
#define HAS_DSC(__i915)			(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
#define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
#define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)
#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) > 2)
#define HAS_GMBUS_IRQ(i915)		(DISPLAY_VER(i915) >= 4)
#define HAS_GMBUS_BURST_READ(i915)	(DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
#define HAS_GMCH(i915)			(DISPLAY_INFO(i915)->has_gmch)
#define HAS_HW_SAGV_WM(i915)		(DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
#define HAS_IPC(i915)			(DISPLAY_INFO(i915)->has_ipc)
#define HAS_IPS(i915)			(IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
#define HAS_LRR(i915)			(DISPLAY_VER(i915) >= 12)
#define HAS_LSPCON(i915)		(IS_DISPLAY_VER(i915, 9, 10))
#define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)
#define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)
#define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)
#define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)
#define HAS_SAGV(i915)			(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
#define HAS_TRANSCODER(i915, trans)	((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
					  BIT(trans)) != 0)
#define HAS_VRR(i915)			(DISPLAY_VER(i915) >= 11)
#define INTEL_NUM_PIPES(i915)		(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915)		(DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915)	(DISPLAY_INFO(i915)->overlay_needs_physical)
#define SUPPORTS_TV(i915)		(DISPLAY_INFO(i915)->supports_tv)

/* Check that device has a display IP version within the specific range. */
#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
	BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
	(DISPLAY_VER_FULL(__i915) >= (from) && \
	 DISPLAY_VER_FULL(__i915) <= (until)))

/*
 * Check if a device has a specific IP version as well as a stepping within the
 * specified range [from, until).  The lower bound is inclusive, the upper
 * bound is exclusive.  The most common use-case of this macro is for checking
 * bounds for workarounds, which usually have a stepping ("from") at which the
 * hardware issue is first present and another stepping ("until") at which a
 * hardware fix is present and the software workaround is no longer necessary.
 * E.g.,
 *
 *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
 *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
 *
 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
 * stepping bound for the specified IP version.
 */
#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
	(IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
	 IS_DISPLAY_STEP((__i915), (from), (until)))

#define DISPLAY_INFO(i915)		((i915)->display.info.__device_info)
#define DISPLAY_RUNTIME_INFO(i915)	(&(i915)->display.info.__runtime_info)

#define DISPLAY_VER(i915)	(DISPLAY_RUNTIME_INFO(i915)->ip.ver)
#define DISPLAY_VER_FULL(i915)	IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
				       DISPLAY_RUNTIME_INFO(i915)->ip.rel)
#define IS_DISPLAY_VER(i915, from, until) \
	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))

struct intel_display_runtime_info {
	struct {
		u16 ver;
		u16 rel;
		u16 step;
	} ip;

	u8 pipe_mask;
	u8 cpu_transcoder_mask;
	u16 port_mask;

	u8 num_sprites[I915_MAX_PIPES];
	u8 num_scalers[I915_MAX_PIPES];

	u8 fbc_mask;

	bool has_hdcp;
	bool has_dmc;
	bool has_dsc;
};

struct intel_display_device_info {
	/* Initial runtime info. */
	const struct intel_display_runtime_info __runtime_defaults;

	u8 abox_mask;

	struct {
		u16 size; /* in blocks */
		u8 slice_mask;
	} dbuf;

#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG

	/* Global register offset for the display engine */
	u32 mmio_offset;

	/* Register offsets for the various display pipes and transcoders */
	u32 pipe_offsets[I915_MAX_TRANSCODERS];
	u32 trans_offsets[I915_MAX_TRANSCODERS];
	u32 cursor_offsets[I915_MAX_PIPES];

	struct {
		u32 degamma_lut_size;
		u32 gamma_lut_size;
		u32 degamma_lut_tests;
		u32 gamma_lut_tests;
	} color;
};

bool intel_display_device_enabled(struct drm_i915_private *i915);
void intel_display_device_probe(struct drm_i915_private *i915);
void intel_display_device_info_runtime_init(struct drm_i915_private *i915);

void intel_display_device_info_print(const struct intel_display_device_info *info,
				     const struct intel_display_runtime_info *runtime,
				     struct drm_printer *p);

#endif
Commit	Line	Data
05aa8e01 MR	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2023 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_DISPLAY_DEVICE_H__
	7	#define __INTEL_DISPLAY_DEVICE_H__
	8
	9	#include <linux/types.h>
	10
5e0bff2b	11	#include "intel_display_limits.h"
05aa8e01	12
12e6f6dc	13	struct drm_i915_private;
4ae7eb92	14	struct drm_printer;
12e6f6dc	15
05aa8e01 MR	16	#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
	17	/* Keep in alphabetical order */ \
	18	func(cursor_needs_physical); \
	19	func(has_cdclk_crawl); \
	20	func(has_cdclk_squash); \
	21	func(has_ddi); \
	22	func(has_dp_mst); \
	23	func(has_dsb); \
	24	func(has_fpga_dbg); \
	25	func(has_gmch); \
	26	func(has_hotplug); \
	27	func(has_hti); \
	28	func(has_ipc); \
	29	func(has_overlay); \
	30	func(has_psr); \
	31	func(has_psr_hw_tracking); \
	32	func(overlay_needs_physical); \
	33	func(supports_tv);
	34
4ebf43d0	35	#define HAS_4TILE(i915) (IS_DG2(i915) \|\| DISPLAY_VER(i915) >= 14)
95c08508 MR	36	#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
	37	#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
	38	#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
	39	#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
	40	#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) \|\| IS_ALDERLAKE_S(i915))
	41	#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
	42	#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
	43	#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
	44	#define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 \|\| IS_BROADWELL(i915))
	45	#define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst)
	46	#define HAS_DP20(i915) (IS_DG2(i915) \|\| DISPLAY_VER(i915) >= 14)
	47	#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
	48	#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
	49	#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
	50	#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
	51	#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
	52	#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
	53	#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
	54	#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 \|\| IS_KABYLAKE(i915))
	55	#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
	56	#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
	57	#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
927a8e38	58	#define HAS_IPS(i915) (IS_HASWELL_ULT(i915) \|\| IS_BROADWELL(i915))
16a93594	59	#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
95c08508 MR	60	#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
	61	#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) \|\| DISPLAY_VER(i915) >= 14)
	62	#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
	63	#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
	64	#define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr)
	65	#define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking)
	66	#define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
	67	#define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
	68	#define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
	69	BIT(trans)) != 0)
	70	#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
	71	#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
	72	#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
	73	#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
	74	#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
	75
213454b3 MR	76	/* Check that device has a display IP version within the specific range. */
	77	#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
	78	BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
	79	(DISPLAY_VER_FULL(__i915) >= (from) && \
	80	DISPLAY_VER_FULL(__i915) <= (until)))
	81
	82	/*
	83	* Check if a device has a specific IP version as well as a stepping within the
	84	* specified range [from, until). The lower bound is inclusive, the upper
	85	* bound is exclusive. The most common use-case of this macro is for checking
	86	* bounds for workarounds, which usually have a stepping ("from") at which the
	87	* hardware issue is first present and another stepping ("until") at which a
	88	* hardware fix is present and the software workaround is no longer necessary.
	89	* E.g.,
	90	*
	91	* IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
	92	* IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
	93	*
	94	* "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
	95	* stepping bound for the specified IP version.
	96	*/
	97	#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
	98	(IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
	99	IS_DISPLAY_STEP((__i915), (from), (until)))
	100
5e72e75d JN	101	#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info)
	102	#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info)
	103
	104	#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
	105	#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
	106	DISPLAY_RUNTIME_INFO(i915)->ip.rel)
	107	#define IS_DISPLAY_VER(i915, from, until) \
	108	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
	109
18e0deee MR	110	struct intel_display_runtime_info {
	111	struct {
	112	u16 ver;
	113	u16 rel;
	114	u16 step;
	115	} ip;
	116
	117	u8 pipe_mask;
	118	u8 cpu_transcoder_mask;
2798e4d1	119	u16 port_mask;
18e0deee MR	120
	121	u8 num_sprites[I915_MAX_PIPES];
	122	u8 num_scalers[I915_MAX_PIPES];
	123
	124	u8 fbc_mask;
	125
	126	bool has_hdcp;
	127	bool has_dmc;
	128	bool has_dsc;
	129	};
	130
05aa8e01	131	struct intel_display_device_info {
18e0deee MR	132	/* Initial runtime info. */
	133	const struct intel_display_runtime_info __runtime_defaults;
	134
05aa8e01 MR	135	u8 abox_mask;
	136
	137	struct {
	138	u16 size; /* in blocks */
	139	u8 slice_mask;
	140	} dbuf;
	141
	142	#define DEFINE_FLAG(name) u8 name:1
	143	DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
	144	#undef DEFINE_FLAG
	145
	146	/* Global register offset for the display engine */
	147	u32 mmio_offset;
	148
	149	/* Register offsets for the various display pipes and transcoders */
	150	u32 pipe_offsets[I915_MAX_TRANSCODERS];
	151	u32 trans_offsets[I915_MAX_TRANSCODERS];
	152	u32 cursor_offsets[I915_MAX_PIPES];
	153
	154	struct {
	155	u32 degamma_lut_size;
	156	u32 gamma_lut_size;
	157	u32 degamma_lut_tests;
	158	u32 gamma_lut_tests;
	159	} color;
	160	};
	161
fe63ea7c	162	bool intel_display_device_enabled(struct drm_i915_private *i915);
6686c30e	163	void intel_display_device_probe(struct drm_i915_private *i915);
2d0cdf60	164	void intel_display_device_info_runtime_init(struct drm_i915_private *i915);
69d43981	165
4ae7eb92 JN	166	void intel_display_device_info_print(const struct intel_display_device_info *info,
	167	const struct intel_display_runtime_info *runtime,
	168	struct drm_printer *p);
	169
05aa8e01	170	#endif