[linux-block.git] / drivers / gpu / drm / i915 / display / intel_display_core.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2022 Intel Corporation
 */

#ifndef __INTEL_DISPLAY_CORE_H__
#define __INTEL_DISPLAY_CORE_H__

#include <linux/list.h>
#include <linux/llist.h>
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/workqueue.h>

#include <drm/drm_connector.h>
#include <drm/drm_modeset_lock.h>

#include "intel_cdclk.h"
#include "intel_display_device.h"
#include "intel_display_limits.h"
#include "intel_display_params.h"
#include "intel_display_power.h"
#include "intel_dpll_mgr.h"
#include "intel_fbc.h"
#include "intel_global_state.h"
#include "intel_gmbus.h"
#include "intel_opregion.h"
#include "intel_dmc_wl.h"
#include "intel_wm_types.h"

struct task_struct;

struct drm_i915_private;
struct drm_property;
struct drm_property_blob;
struct i915_audio_component;
struct i915_hdcp_arbiter;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_funcs;
struct intel_cdclk_vals;
struct intel_color_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dmc;
struct intel_dpll_funcs;
struct intel_dpll_mgr;
struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
struct intel_opregion;
struct intel_overlay;

/* Amount of SAGV/QGV points, BSpec precisely defines this */
#define I915_NUM_QGV_POINTS 8

/* Amount of PSF GV points, BSpec precisely defines this */
#define I915_NUM_PSF_GV_POINTS 3

struct intel_display_funcs {
	/*
	 * Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state.
	 */
	bool (*get_pipe_config)(struct intel_crtc *,
				struct intel_crtc_state *);
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
	bool (*fixup_initial_plane_config)(struct intel_crtc *crtc,
					   const struct intel_initial_plane_config *plane_config);
	void (*crtc_enable)(struct intel_atomic_state *state,
			    struct intel_crtc *crtc);
	void (*crtc_disable)(struct intel_atomic_state *state,
			     struct intel_crtc *crtc);
	void (*commit_modeset_enables)(struct intel_atomic_state *state);
};

/* functions used for watermark calcs for display. */
struct intel_wm_funcs {
	/* update_wm is for legacy wm management */
	void (*update_wm)(struct drm_i915_private *dev_priv);
	int (*compute_pipe_wm)(struct intel_atomic_state *state,
			       struct intel_crtc *crtc);
	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
				       struct intel_crtc *crtc);
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc *crtc);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc *crtc);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc *crtc);
	int (*compute_global_watermarks)(struct intel_atomic_state *state);
	void (*get_hw_state)(struct drm_i915_private *i915);
};

struct intel_audio_state {
	struct intel_encoder *encoder;
	u8 eld[MAX_ELD_BYTES];
};

struct intel_audio {
	/* hda/i915 audio component */
	struct i915_audio_component *component;
	bool component_registered;
	/* mutex for audio/video sync */
	struct mutex mutex;
	int power_refcount;
	u32 freq_cntrl;

	/* current audio state for the audio component hooks */
	struct intel_audio_state state[I915_MAX_TRANSCODERS];

	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int irq;
	} lpe;
};

/*
 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
 * intel_{prepare,enable,disable}_shared_dpll.  Must be global rather than per
 * dpll, because on some platforms plls share registers.
 */
struct intel_dpll {
	struct mutex lock;

	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
	const struct intel_dpll_mgr *mgr;

	struct {
		int nssc;
		int ssc;
	} ref_clks;

	/*
	 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
	 */
	u8 pch_ssc_use;
};

struct intel_frontbuffer_tracking {
	spinlock_t lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

struct intel_hotplug {
	struct delayed_work hotplug_work;

	const u32 *hpd, *pch_hpd;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	u32 retry_bits;
	struct delayed_work reenable_work;

	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

	struct work_struct poll_init_work;
	bool poll_enabled;

	/*
	 * Queuing of hotplug_work, reenable_work and poll_init_work is
	 * enabled. Protected by drm_i915_private::irq_lock.
	 */
	bool detection_work_enabled;

	unsigned int hpd_storm_threshold;
	/* Whether or not to count short HPD IRQs in HPD storms */
	u8 hpd_short_storm_enabled;

	/* Last state reported by oob_hotplug_event for each encoder */
	unsigned long oob_hotplug_last_state;

	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;

	/*
	 * Flag to track if long HPDs need not to be processed
	 *
	 * Some panels generate long HPDs while keep connected to the port.
	 * This can cause issues with CI tests results. In CI systems we
	 * don't expect to disconnect the panels and could ignore the long
	 * HPDs generated from the faulty panels. This flag can be used as
	 * cue to ignore the long HPDs and can be set / unset using debugfs.
	 */
	bool ignore_long_hpd;
};

struct intel_vbt_data {
	/* bdb version */
	u16 version;

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int int_lvds_support:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
	int lvds_ssc_freq;
	enum drm_panel_orientation orientation;

	bool override_afc_startup;
	u8 override_afc_startup_val;

	int crt_ddc_pin;

	struct list_head display_devices;
	struct list_head bdb_blocks;

	struct sdvo_device_mapping {
		u8 initialized;
		u8 dvo_port;
		u8 target_addr;
		u8 dvo_wiring;
		u8 i2c_pin;
		u8 ddc_pin;
	} sdvo_mappings[2];
};

struct intel_wm {
	/*
	 * Raw watermark latency values:
	 * in 0.1us units for WM0,
	 * in 0.5us units for WM1+.
	 */
	/* primary */
	u16 pri_latency[5];
	/* sprite */
	u16 spr_latency[5];
	/* cursor */
	u16 cur_latency[5];
	/*
	 * Raw watermark memory latency values
	 * for SKL for all 8 levels
	 * in 1us units.
	 */
	u16 skl_latency[8];

	/* current hardware state */
	union {
		struct ilk_wm_values hw;
		struct vlv_wm_values vlv;
		struct g4x_wm_values g4x;
	};

	u8 num_levels;

	/*
	 * Should be held around atomic WM register writing; also
	 * protects * intel_crtc->wm.active and
	 * crtc_state->wm.need_postvbl_update.
	 */
	struct mutex wm_mutex;

	bool ipc_enabled;
};

struct intel_display {
	/* drm device backpointer */
	struct drm_device *drm;

	/* Display functions */
	struct {
		/* Top level crtc-ish functions */
		const struct intel_display_funcs *display;

		/* Display CDCLK functions */
		const struct intel_cdclk_funcs *cdclk;

		/* Display pll funcs */
		const struct intel_dpll_funcs *dpll;

		/* irq display functions */
		const struct intel_hotplug_funcs *hotplug;

		/* pm display functions */
		const struct intel_wm_funcs *wm;

		/* fdi display functions */
		const struct intel_fdi_funcs *fdi;

		/* Display internal color functions */
		const struct intel_color_funcs *color;

		/* Display internal audio functions */
		const struct intel_audio_funcs *audio;
	} funcs;

	struct {
		bool any_task_allowed;
		struct task_struct *allowed_task;
	} access;

	struct {
		/* backlight registers and fields in struct intel_panel */
		struct mutex lock;
	} backlight;

	struct {
		struct intel_global_obj obj;

		struct intel_bw_info {
			/* for each QGV point */
			unsigned int deratedbw[I915_NUM_QGV_POINTS];
			/* for each PSF GV point */
			unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
			/* Peak BW for each QGV point */
			unsigned int peakbw[I915_NUM_QGV_POINTS];
			u8 num_qgv_points;
			u8 num_psf_gv_points;
			u8 num_planes;
		} max[6];
	} bw;

	struct {
		/* The current hardware cdclk configuration */
		struct intel_cdclk_config hw;

		/* cdclk, divider, and ratio table from bspec */
		const struct intel_cdclk_vals *table;

		struct intel_global_obj obj;

		unsigned int max_cdclk_freq;
		unsigned int max_dotclk_freq;
		unsigned int skl_preferred_vco_freq;
	} cdclk;

	struct {
		struct drm_property_blob *glk_linear_degamma_lut;
	} color;

	struct {
		/* The current hardware dbuf configuration */
		u8 enabled_slices;

		struct intel_global_obj obj;
	} dbuf;

	struct {
		/*
		 * dkl.phy_lock protects against concurrent access of the
		 * Dekel TypeC PHYs.
		 */
		spinlock_t phy_lock;
	} dkl;

	struct {
		struct intel_dmc *dmc;
		intel_wakeref_t wakeref;
	} dmc;

	struct {
		/* VLV/CHV/BXT/GLK DSI MMIO register base address */
		u32 mmio_base;
	} dsi;

	struct {
		/* list of fbdev register on this device */
		struct intel_fbdev *fbdev;
		struct work_struct suspend_work;
	} fbdev;

	struct {
		unsigned int pll_freq;
		u32 rx_config;
	} fdi;

	struct {
		struct list_head obj_list;
	} global;

	struct {
		/*
		 * Base address of where the gmbus and gpio blocks are located
		 * (either on PCH or on SoC for platforms without PCH).
		 */
		u32 mmio_base;

		/*
		 * gmbus.mutex protects against concurrent usage of the single
		 * hw gmbus controller on different i2c buses.
		 */
		struct mutex mutex;

		struct intel_gmbus *bus[GMBUS_NUM_PINS];

		wait_queue_head_t wait_queue;
	} gmbus;

	struct {
		struct i915_hdcp_arbiter *arbiter;
		bool comp_added;

		/*
		 * HDCP message struct for allocation of memory which can be
		 * reused when sending message to gsc cs.
		 * this is only populated post Meteorlake
		 */
		struct intel_hdcp_gsc_message *hdcp_message;
		/* Mutex to protect the above hdcp related values. */
		struct mutex hdcp_mutex;
	} hdcp;

	struct {
		/*
		 * HTI (aka HDPORT) state read during initial hw readout. Most
		 * platforms don't have HTI, so this will just stay 0. Those
		 * that do will use this later to figure out which PLLs and PHYs
		 * are unavailable for driver usage.
		 */
		u32 state;
	} hti;

	struct {
		/* Access with DISPLAY_INFO() */
		const struct intel_display_device_info *__device_info;

		/* Access with DISPLAY_RUNTIME_INFO() */
		struct intel_display_runtime_info __runtime_info;
	} info;

	struct {
		bool false_color;
	} ips;

	struct {
		bool display_irqs_enabled;

		/* For i915gm/i945gm vblank irq workaround */
		u8 vblank_enabled;

		u32 de_irq_mask[I915_MAX_PIPES];
		u32 pipestat_irq_mask[I915_MAX_PIPES];
	} irq;

	struct {
		wait_queue_head_t waitqueue;

		/* mutex to protect pmdemand programming sequence */
		struct mutex lock;

		struct intel_global_obj obj;
	} pmdemand;

	struct {
		struct i915_power_domains domains;

		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
		u32 chv_phy_control;

		/* perform PHY state sanity checks? */
		bool chv_phy_assert[2];
	} power;

	struct {
		u32 mmio_base;

		/* protects panel power sequencer state */
		struct mutex mutex;
	} pps;

	struct {
		struct drm_property *broadcast_rgb;
		struct drm_property *force_audio;
	} properties;

	struct {
		unsigned long mask;
	} quirks;

	struct {
		/* restore state for suspend/resume and display reset */
		struct drm_atomic_state *modeset_state;
		struct drm_modeset_acquire_ctx reset_ctx;
	} restore;

	struct {
		enum {
			I915_SAGV_UNKNOWN = 0,
			I915_SAGV_DISABLED,
			I915_SAGV_ENABLED,
			I915_SAGV_NOT_CONTROLLED
		} status;

		u32 block_time_us;
	} sagv;

	struct {
		/*
		 * DG2: Mask of PHYs that were not calibrated by the firmware
		 * and should not be used.
		 */
		u8 phy_failed_calibration;
	} snps;

	struct {
		/*
		 * Shadows for CHV DPLL_MD regs to keep the state
		 * checker somewhat working in the presence hardware
		 * crappiness (can't read out DPLL_MD for pipes B & C).
		 */
		u32 chv_dpll_md[I915_MAX_PIPES];
		u32 bxt_phy_grc;
	} state;

	struct {
		/* ordered wq for modesets */
		struct workqueue_struct *modeset;

		/* unbound hipri wq for page flips/plane updates */
		struct workqueue_struct *flip;
	} wq;

	/* Grouping using named structs. Keep sorted. */
	struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
	struct intel_audio audio;
	struct intel_dpll dpll;
	struct intel_fbc *fbc[I915_MAX_FBCS];
	struct intel_frontbuffer_tracking fb_tracking;
	struct intel_hotplug hotplug;
	struct intel_opregion *opregion;
	struct intel_overlay *overlay;
	struct intel_display_params params;
	struct intel_vbt_data vbt;
	struct intel_dmc_wl wl;
	struct intel_wm wm;
};

#endif /* __INTEL_DISPLAY_CORE_H__ */
Commit	Line	Data
3b10f851 JN	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2022 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_DISPLAY_CORE_H__
	7	#define __INTEL_DISPLAY_CORE_H__
	8
a434689c	9	#include <linux/list.h>
a71e7d77	10	#include <linux/llist.h>
203eb5a9	11	#include <linux/mutex.h>
3b10f851	12	#include <linux/types.h>
203eb5a9	13	#include <linux/wait.h>
b3d81daf	14	#include <linux/workqueue.h>
203eb5a9	15
a434689c	16	#include <drm/drm_connector.h>
6af0ffc0	17	#include <drm/drm_modeset_lock.h>
a434689c	18
d51309b4	19	#include "intel_cdclk.h"
e672f9e9	20	#include "intel_display_device.h"
acc855d3	21	#include "intel_display_limits.h"
8015bee0	22	#include "intel_display_params.h"
e3e8148f	23	#include "intel_display_power.h"
36d225f3	24	#include "intel_dpll_mgr.h"
80b3842f	25	#include "intel_fbc.h"
f0acaf9d	26	#include "intel_global_state.h"
203eb5a9	27	#include "intel_gmbus.h"
7249dfcb	28	#include "intel_opregion.h"
765425f5	29	#include "intel_dmc_wl.h"
4923e99f	30	#include "intel_wm_types.h"
3b10f851	31
bd738d85 ID	32	struct task_struct;
bd738d85 ID	33
103472c1	34	struct drm_i915_private;
fe28c7c1	35	struct drm_property;
48205f42	36	struct drm_property_blob;
4be1c12c	37	struct i915_audio_component;
5c8ec987	38	struct i915_hdcp_arbiter;
3b10f851	39	struct intel_atomic_state;
4be1c12c	40	struct intel_audio_funcs;
986531bd	41	struct intel_cdclk_funcs;
d51309b4	42	struct intel_cdclk_vals;
34dc3cc5	43	struct intel_color_funcs;
3b10f851 JN	44	struct intel_crtc;
3b10f851 JN	45	struct intel_crtc_state;
e81a3c12	46	struct intel_dmc;
ae611d17	47	struct intel_dpll_funcs;
36d225f3	48	struct intel_dpll_mgr;
b3d81daf	49	struct intel_fbdev;
06a50913	50	struct intel_fdi_funcs;
5a04eb5b	51	struct intel_hotplug_funcs;
3b10f851	52	struct intel_initial_plane_config;
a52c854a	53	struct intel_opregion;
304ebaeb	54	struct intel_overlay;
3b10f851	55
f0acaf9d JN	56	/* Amount of SAGV/QGV points, BSpec precisely defines this */
	57	#define I915_NUM_QGV_POINTS 8
	58
	59	/* Amount of PSF GV points, BSpec precisely defines this */
	60	#define I915_NUM_PSF_GV_POINTS 3
	61
3b10f851 JN	62	struct intel_display_funcs {
	63	/*
	64	* Returns the active state of the crtc, and if the crtc is active,
	65	* fills out the pipe-config with the hw state.
	66	*/
	67	bool (get_pipe_config)(struct intel_crtc ,
	68	struct intel_crtc_state *);
	69	void (get_initial_plane_config)(struct intel_crtc ,
	70	struct intel_initial_plane_config *);
a8153627 VS	71	bool (fixup_initial_plane_config)(struct intel_crtc crtc,
a8153627 VS	72	const struct intel_initial_plane_config *plane_config);
3b10f851 JN	73	void (crtc_enable)(struct intel_atomic_state state,
	74	struct intel_crtc *crtc);
	75	void (crtc_disable)(struct intel_atomic_state state,
	76	struct intel_crtc *crtc);
	77	void (commit_modeset_enables)(struct intel_atomic_state state);
	78	};
	79
103472c1 JN	80	/* functions used for watermark calcs for display. */
	81	struct intel_wm_funcs {
	82	/* update_wm is for legacy wm management */
	83	void (update_wm)(struct drm_i915_private dev_priv);
	84	int (compute_pipe_wm)(struct intel_atomic_state state,
	85	struct intel_crtc *crtc);
	86	int (compute_intermediate_wm)(struct intel_atomic_state state,
	87	struct intel_crtc *crtc);
	88	void (initial_watermarks)(struct intel_atomic_state state,
	89	struct intel_crtc *crtc);
	90	void (atomic_update_watermarks)(struct intel_atomic_state state,
	91	struct intel_crtc *crtc);
	92	void (optimize_watermarks)(struct intel_atomic_state state,
	93	struct intel_crtc *crtc);
	94	int (compute_global_watermarks)(struct intel_atomic_state state);
0e7a16f9	95	void (get_hw_state)(struct drm_i915_private i915);
103472c1 JN	96	};
103472c1 JN	97
c7104c38 VS	98	struct intel_audio_state {
c7104c38 VS	99	struct intel_encoder *encoder;
5d986635	100	u8 eld[MAX_ELD_BYTES];
c7104c38 VS	101	};
c7104c38 VS	102
4be1c12c JN	103	struct intel_audio {
	104	/* hda/i915 audio component */
	105	struct i915_audio_component *component;
	106	bool component_registered;
	107	/* mutex for audio/video sync */
	108	struct mutex mutex;
	109	int power_refcount;
	110	u32 freq_cntrl;
	111
c7104c38	112	/* current audio state for the audio component hooks */
5eba7426	113	struct intel_audio_state state[I915_MAX_TRANSCODERS];
4be1c12c JN	114
	115	/* necessary resource sharing with HDMI LPE audio driver. */
	116	struct {
	117	struct platform_device *platdev;
	118	int irq;
	119	} lpe;
	120	};
	121
36d225f3 JN	122	/*
	123	* dpll and cdclk state is protected by connection_mutex dpll.lock serializes
	124	* intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
	125	* dpll, because on some platforms plls share registers.
	126	*/
	127	struct intel_dpll {
	128	struct mutex lock;
	129
	130	int num_shared_dpll;
	131	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
	132	const struct intel_dpll_mgr *mgr;
	133
	134	struct {
	135	int nssc;
	136	int ssc;
	137	} ref_clks;
a3f83976 JN	138
	139	/*
	140	* Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id.
	141	*/
	142	u8 pch_ssc_use;
36d225f3 JN	143	};
36d225f3 JN	144
5da6d6c7 JN	145	struct intel_frontbuffer_tracking {
	146	spinlock_t lock;
	147
	148	/*
	149	* Tracking bits for delayed frontbuffer flushing du to gpu activity or
	150	* scheduled flips.
	151	*/
	152	unsigned busy_bits;
	153	unsigned flip_bits;
	154	};
	155
5a4dd6f0 JN	156	struct intel_hotplug {
	157	struct delayed_work hotplug_work;
	158
	159	const u32 hpd, pch_hpd;
	160
	161	struct {
	162	unsigned long last_jiffies;
	163	int count;
	164	enum {
	165	HPD_ENABLED = 0,
	166	HPD_DISABLED = 1,
	167	HPD_MARK_DISABLED = 2
	168	} state;
	169	} stats[HPD_NUM_PINS];
	170	u32 event_bits;
	171	u32 retry_bits;
	172	struct delayed_work reenable_work;
	173
	174	u32 long_port_mask;
	175	u32 short_port_mask;
	176	struct work_struct dig_port_work;
	177
	178	struct work_struct poll_init_work;
	179	bool poll_enabled;
	180
cd572b3b ID	181	/*
	182	* Queuing of hotplug_work, reenable_work and poll_init_work is
	183	* enabled. Protected by drm_i915_private::irq_lock.
	184	*/
	185	bool detection_work_enabled;
	186
5a4dd6f0 JN	187	unsigned int hpd_storm_threshold;
	188	/* Whether or not to count short HPD IRQs in HPD storms */
	189	u8 hpd_short_storm_enabled;
	190
fc93835b BA	191	/* Last state reported by oob_hotplug_event for each encoder */
	192	unsigned long oob_hotplug_last_state;
	193
5a4dd6f0 JN	194	/*
	195	* if we get a HPD irq from DP and a HPD irq from non-DP
	196	* the non-DP HPD could block the workqueue on a mode config
	197	* mutex getting, that userspace may have taken. However
	198	* userspace is waiting on the DP workqueue to run which is
	199	* blocked behind the non-DP one.
	200	*/
	201	struct workqueue_struct *dp_wq;
b0fbef65 VG	202
	203	/*
	204	* Flag to track if long HPDs need not to be processed
	205	*
	206	* Some panels generate long HPDs while keep connected to the port.
	207	* This can cause issues with CI tests results. In CI systems we
	208	* don't expect to disconnect the panels and could ignore the long
	209	* HPDs generated from the faulty panels. This flag can be used as
	210	* cue to ignore the long HPDs and can be set / unset using debugfs.
	211	*/
	212	bool ignore_long_hpd;
5a4dd6f0 JN	213	};
5a4dd6f0 JN	214
a434689c JN	215	struct intel_vbt_data {
	216	/* bdb version */
	217	u16 version;
	218
	219	/* Feature bits */
	220	unsigned int int_tv_support:1;
	221	unsigned int int_crt_support:1;
	222	unsigned int lvds_use_ssc:1;
	223	unsigned int int_lvds_support:1;
	224	unsigned int display_clock_mode:1;
	225	unsigned int fdi_rx_polarity_inverted:1;
	226	int lvds_ssc_freq;
	227	enum drm_panel_orientation orientation;
	228
	229	bool override_afc_startup;
	230	u8 override_afc_startup_val;
	231
	232	int crt_ddc_pin;
	233
	234	struct list_head display_devices;
	235	struct list_head bdb_blocks;
	236
a434689c JN	237	struct sdvo_device_mapping {
	238	u8 initialized;
	239	u8 dvo_port;
bc3ca4d9	240	u8 target_addr;
a434689c JN	241	u8 dvo_wiring;
	242	u8 i2c_pin;
	243	u8 ddc_pin;
	244	} sdvo_mappings[2];
	245	};
	246
a30a6fe9 JN	247	struct intel_wm {
	248	/*
	249	* Raw watermark latency values:
	250	* in 0.1us units for WM0,
	251	* in 0.5us units for WM1+.
	252	*/
	253	/* primary */
	254	u16 pri_latency[5];
	255	/* sprite */
	256	u16 spr_latency[5];
	257	/* cursor */
	258	u16 cur_latency[5];
	259	/*
	260	* Raw watermark memory latency values
	261	* for SKL for all 8 levels
	262	* in 1us units.
	263	*/
	264	u16 skl_latency[8];
	265
	266	/* current hardware state */
	267	union {
	268	struct ilk_wm_values hw;
	269	struct vlv_wm_values vlv;
	270	struct g4x_wm_values g4x;
	271	};
	272
7ee6f99d	273	u8 num_levels;
a30a6fe9 JN	274
	275	/*
	276	* Should be held around atomic WM register writing; also
	277	* protects * intel_crtc->wm.active and
	278	* crtc_state->wm.need_postvbl_update.
	279	*/
	280	struct mutex wm_mutex;
70296670 JN	281
70296670 JN	282	bool ipc_enabled;
a30a6fe9 JN	283	};
a30a6fe9 JN	284
3b10f851	285	struct intel_display {
f02fedd8 JN	286	/* drm device backpointer */
	287	struct drm_device *drm;
	288
3b10f851 JN	289	/* Display functions */
	290	struct {
	291	/* Top level crtc-ish functions */
	292	const struct intel_display_funcs *display;
986531bd JN	293
	294	/* Display CDCLK functions */
	295	const struct intel_cdclk_funcs *cdclk;
ae611d17 JN	296
	297	/* Display pll funcs */
	298	const struct intel_dpll_funcs *dpll;
5a04eb5b JN	299
	300	/* irq display functions */
	301	const struct intel_hotplug_funcs *hotplug;
103472c1 JN	302
	303	/* pm display functions */
	304	const struct intel_wm_funcs *wm;
06a50913 JN	305
	306	/* fdi display functions */
	307	const struct intel_fdi_funcs *fdi;
34dc3cc5 JN	308
	309	/* Display internal color functions */
	310	const struct intel_color_funcs *color;
4be1c12c JN	311
	312	/* Display internal audio functions */
	313	const struct intel_audio_funcs *audio;
3b10f851	314	} funcs;
203eb5a9	315
bd738d85 ID	316	struct {
	317	bool any_task_allowed;
	318	struct task_struct *allowed_task;
	319	} access;
	320
2fee35fc JN	321	struct {
	322	/* backlight registers and fields in struct intel_panel */
	323	struct mutex lock;
	324	} backlight;
	325
f0acaf9d JN	326	struct {
	327	struct intel_global_obj obj;
	328
	329	struct intel_bw_info {
	330	/* for each QGV point */
	331	unsigned int deratedbw[I915_NUM_QGV_POINTS];
	332	/* for each PSF GV point */
	333	unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
88d0ecbd VG	334	/* Peak BW for each QGV point */
88d0ecbd VG	335	unsigned int peakbw[I915_NUM_QGV_POINTS];
f0acaf9d JN	336	u8 num_qgv_points;
	337	u8 num_psf_gv_points;
	338	u8 num_planes;
	339	} max[6];
	340	} bw;
	341
d51309b4 JN	342	struct {
	343	/* The current hardware cdclk configuration */
	344	struct intel_cdclk_config hw;
	345
	346	/* cdclk, divider, and ratio table from bspec */
	347	const struct intel_cdclk_vals *table;
	348
	349	struct intel_global_obj obj;
	350
	351	unsigned int max_cdclk_freq;
8219ab6d	352	unsigned int max_dotclk_freq;
ded402c7	353	unsigned int skl_preferred_vco_freq;
d51309b4 JN	354	} cdclk;
d51309b4 JN	355
48205f42 VS	356	struct {
	357	struct drm_property_blob *glk_linear_degamma_lut;
	358	} color;
	359
b7d15590 JN	360	struct {
	361	/* The current hardware dbuf configuration */
	362	u8 enabled_slices;
	363
	364	struct intel_global_obj obj;
	365	} dbuf;
	366
90b87cf2	367	struct {
89cb0ba4 ID	368	/*
	369	* dkl.phy_lock protects against concurrent access of the
	370	* Dekel TypeC PHYs.
	371	*/
	372	spinlock_t phy_lock;
	373	} dkl;
	374
e81a3c12 JN	375	struct {
	376	struct intel_dmc *dmc;
	377	intel_wakeref_t wakeref;
	378	} dmc;
	379
89cb0ba4	380	struct {
90b87cf2 JN	381	/* VLV/CHV/BXT/GLK DSI MMIO register base address */
	382	u32 mmio_base;
	383	} dsi;
	384
b3d81daf JN	385	struct {
	386	/* list of fbdev register on this device */
	387	struct intel_fbdev *fbdev;
	388	struct work_struct suspend_work;
	389	} fbdev;
	390
20478b88 JN	391	struct {
	392	unsigned int pll_freq;
	393	u32 rx_config;
	394	} fdi;
e2925e19 JN	395
	396	struct {
	397	struct list_head obj_list;
	398	} global;
20478b88	399
203eb5a9 JN	400	struct {
	401	/*
	402	* Base address of where the gmbus and gpio blocks are located
	403	* (either on PCH or on SoC for platforms without PCH).
	404	*/
	405	u32 mmio_base;
	406
	407	/*
	408	* gmbus.mutex protects against concurrent usage of the single
	409	* hw gmbus controller on different i2c buses.
	410	*/
	411	struct mutex mutex;
	412
	413	struct intel_gmbus *bus[GMBUS_NUM_PINS];
	414
	415	wait_queue_head_t wait_queue;
	416	} gmbus;
12dc5082	417
eb11eabc	418	struct {
5c8ec987	419	struct i915_hdcp_arbiter *arbiter;
eb11eabc JN	420	bool comp_added;
eb11eabc JN	421
18fd7f8a SK	422	/*
	423	* HDCP message struct for allocation of memory which can be
	424	* reused when sending message to gsc cs.
	425	* this is only populated post Meteorlake
	426	*/
	427	struct intel_hdcp_gsc_message *hdcp_message;
3e36c490 SK	428	/* Mutex to protect the above hdcp related values. */
3e36c490 SK	429	struct mutex hdcp_mutex;
eb11eabc JN	430	} hdcp;
eb11eabc JN	431
62749912 JN	432	struct {
	433	/*
	434	* HTI (aka HDPORT) state read during initial hw readout. Most
	435	* platforms don't have HTI, so this will just stay 0. Those
	436	* that do will use this later to figure out which PLLs and PHYs
	437	* are unavailable for driver usage.
	438	*/
	439	u32 state;
	440	} hti;
	441
e672f9e9 JN	442	struct {
	443	/* Access with DISPLAY_INFO() */
	444	const struct intel_display_device_info *__device_info;
	445
	446	/* Access with DISPLAY_RUNTIME_INFO() */
	447	struct intel_display_runtime_info __runtime_info;
	448	} info;
	449
42b4c479 VS	450	struct {
	451	bool false_color;
	452	} ips;
	453
53e8de10	454	struct {
9aad7329 JN	455	bool display_irqs_enabled;
9aad7329 JN	456
53e8de10 JN	457	/* For i915gm/i945gm vblank irq workaround */
53e8de10 JN	458	u8 vblank_enabled;
f25ae90f JN	459
f25ae90f JN	460	u32 de_irq_mask[I915_MAX_PIPES];
860cefce	461	u32 pipestat_irq_mask[I915_MAX_PIPES];
53e8de10 JN	462	} irq;
53e8de10 JN	463
9a626c1f JN	464	struct {
	465	wait_queue_head_t waitqueue;
	466
	467	/* mutex to protect pmdemand programming sequence */
	468	struct mutex lock;
	469
	470	struct intel_global_obj obj;
	471	} pmdemand;
	472
e3e8148f JN	473	struct {
	474	struct i915_power_domains domains;
	475
	476	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
	477	u32 chv_phy_control;
	478
	479	/* perform PHY state sanity checks? */
	480	bool chv_phy_assert[2];
	481	} power;
	482
12dc5082 JN	483	struct {
	484	u32 mmio_base;
	485
	486	/* protects panel power sequencer state */
	487	struct mutex mutex;
	488	} pps;
6c77055a	489
fe28c7c1 JN	490	struct {
	491	struct drm_property *broadcast_rgb;
	492	struct drm_property *force_audio;
	493	} properties;
	494
6493d4a9 JN	495	struct {
	496	unsigned long mask;
	497	} quirks;
	498
6af0ffc0 JN	499	struct {
	500	/* restore state for suspend/resume and display reset */
	501	struct drm_atomic_state *modeset_state;
	502	struct drm_modeset_acquire_ctx reset_ctx;
	503	} restore;
	504
c3704f19 JN	505	struct {
	506	enum {
	507	I915_SAGV_UNKNOWN = 0,
	508	I915_SAGV_DISABLED,
	509	I915_SAGV_ENABLED,
	510	I915_SAGV_NOT_CONTROLLED
	511	} status;
	512
	513	u32 block_time_us;
	514	} sagv;
	515
3a7e2d58 JN	516	struct {
	517	/*
	518	* DG2: Mask of PHYs that were not calibrated by the firmware
	519	* and should not be used.
	520	*/
	521	u8 phy_failed_calibration;
	522	} snps;
	523
e2855f8e JN	524	struct {
	525	/*
	526	* Shadows for CHV DPLL_MD regs to keep the state
	527	* checker somewhat working in the presence hardware
	528	* crappiness (can't read out DPLL_MD for pipes B & C).
	529	*/
	530	u32 chv_dpll_md[I915_MAX_PIPES];
	531	u32 bxt_phy_grc;
	532	} state;
	533
b202ab61 JN	534	struct {
	535	/* ordered wq for modesets */
	536	struct workqueue_struct *modeset;
	537
	538	/* unbound hipri wq for page flips/plane updates */
	539	struct workqueue_struct *flip;
	540	} wq;
	541
6c77055a	542	/* Grouping using named structs. Keep sorted. */
91888b5b	543	struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
4be1c12c	544	struct intel_audio audio;
36d225f3	545	struct intel_dpll dpll;
80b3842f	546	struct intel_fbc *fbc[I915_MAX_FBCS];
5da6d6c7	547	struct intel_frontbuffer_tracking fb_tracking;
5a4dd6f0	548	struct intel_hotplug hotplug;
a52c854a	549	struct intel_opregion *opregion;
304ebaeb	550	struct intel_overlay *overlay;
8015bee0	551	struct intel_display_params params;
a434689c	552	struct intel_vbt_data vbt;
765425f5	553	struct intel_dmc_wl wl;
a30a6fe9	554	struct intel_wm wm;
3b10f851 JN	555	};
	556
	557	#endif /* __INTEL_DISPLAY_CORE_H__ */