Commit | Line | Data |
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09a28bd9 | 1 | /* |
5b6030da | 2 | * Copyright © 2006-2019 Intel Corporation |
09a28bd9 MW |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DISPLAY_H_ | |
26 | #define _INTEL_DISPLAY_H_ | |
27 | ||
d78aa650 | 28 | #include <drm/drm_util.h> |
8605a136 | 29 | #include <drm/i915_drm.h> |
d78aa650 | 30 | |
3e187625 JN |
31 | enum link_m_n_set; |
32 | struct dpll; | |
33 | struct drm_connector; | |
34 | struct drm_device; | |
2d20411e | 35 | struct drm_display_mode; |
3e187625 JN |
36 | struct drm_encoder; |
37 | struct drm_file; | |
d1d23d7f | 38 | struct drm_format_info; |
3e187625 JN |
39 | struct drm_framebuffer; |
40 | struct drm_i915_error_state_buf; | |
41 | struct drm_i915_gem_object; | |
46034d2b | 42 | struct drm_i915_private; |
3e187625 JN |
43 | struct drm_modeset_acquire_ctx; |
44 | struct drm_plane; | |
45 | struct drm_plane_state; | |
46 | struct i915_ggtt_view; | |
47 | struct intel_crtc; | |
48 | struct intel_crtc_state; | |
49 | struct intel_digital_port; | |
50 | struct intel_dp; | |
51 | struct intel_encoder; | |
52 | struct intel_load_detect_pipe; | |
53 | struct intel_plane; | |
54d4d719 | 54 | struct intel_plane_state; |
3e187625 JN |
55 | struct intel_remapped_info; |
56 | struct intel_rotation_info; | |
46034d2b | 57 | |
dce88879 LDM |
58 | enum i915_gpio { |
59 | GPIOA, | |
60 | GPIOB, | |
61 | GPIOC, | |
62 | GPIOD, | |
63 | GPIOE, | |
64 | GPIOF, | |
65 | GPIOG, | |
66 | GPIOH, | |
67 | __GPIOI_UNUSED, | |
68 | GPIOJ, | |
69 | GPIOK, | |
70 | GPIOL, | |
71 | GPIOM, | |
3fd53262 MK |
72 | GPION, |
73 | GPIOO, | |
dce88879 LDM |
74 | }; |
75 | ||
8f78df90 ID |
76 | /* |
77 | * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the | |
78 | * rest have consecutive values and match the enum values of transcoders | |
79 | * with a 1:1 transcoder -> pipe mapping. | |
80 | */ | |
09a28bd9 MW |
81 | enum pipe { |
82 | INVALID_PIPE = -1, | |
83 | ||
84 | PIPE_A = 0, | |
85 | PIPE_B, | |
86 | PIPE_C, | |
f1f1d4fa | 87 | PIPE_D, |
09a28bd9 MW |
88 | _PIPE_EDP, |
89 | ||
90 | I915_MAX_PIPES = _PIPE_EDP | |
91 | }; | |
92 | ||
93 | #define pipe_name(p) ((p) + 'A') | |
94 | ||
95 | enum transcoder { | |
8f78df90 ID |
96 | /* |
97 | * The following transcoders have a 1:1 transcoder -> pipe mapping, | |
98 | * keep their values fixed: the code assumes that TRANSCODER_A=0, the | |
99 | * rest have consecutive values and match the enum values of the pipes | |
100 | * they map to. | |
101 | */ | |
102 | TRANSCODER_A = PIPE_A, | |
103 | TRANSCODER_B = PIPE_B, | |
104 | TRANSCODER_C = PIPE_C, | |
f1f1d4fa | 105 | TRANSCODER_D = PIPE_D, |
8f78df90 ID |
106 | |
107 | /* | |
108 | * The following transcoders can map to any pipe, their enum value | |
109 | * doesn't need to stay fixed. | |
110 | */ | |
09a28bd9 | 111 | TRANSCODER_EDP, |
ca8fc99f MC |
112 | TRANSCODER_DSI_0, |
113 | TRANSCODER_DSI_1, | |
114 | TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */ | |
115 | TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */ | |
09a28bd9 MW |
116 | |
117 | I915_MAX_TRANSCODERS | |
118 | }; | |
119 | ||
120 | static inline const char *transcoder_name(enum transcoder transcoder) | |
121 | { | |
122 | switch (transcoder) { | |
123 | case TRANSCODER_A: | |
124 | return "A"; | |
125 | case TRANSCODER_B: | |
126 | return "B"; | |
127 | case TRANSCODER_C: | |
128 | return "C"; | |
f1f1d4fa LDM |
129 | case TRANSCODER_D: |
130 | return "D"; | |
09a28bd9 MW |
131 | case TRANSCODER_EDP: |
132 | return "EDP"; | |
133 | case TRANSCODER_DSI_A: | |
134 | return "DSI A"; | |
135 | case TRANSCODER_DSI_C: | |
136 | return "DSI C"; | |
137 | default: | |
138 | return "<invalid>"; | |
139 | } | |
140 | } | |
141 | ||
142 | static inline bool transcoder_is_dsi(enum transcoder transcoder) | |
143 | { | |
144 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
145 | } | |
146 | ||
147 | /* | |
148 | * Global legacy plane identifier. Valid only for primary/sprite | |
149 | * planes on pre-g4x, and only for primary planes on g4x-bdw. | |
150 | */ | |
151 | enum i9xx_plane_id { | |
152 | PLANE_A, | |
153 | PLANE_B, | |
154 | PLANE_C, | |
155 | }; | |
156 | ||
157 | #define plane_name(p) ((p) + 'A') | |
0258404f | 158 | #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') |
09a28bd9 MW |
159 | |
160 | /* | |
161 | * Per-pipe plane identifier. | |
162 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) | |
163 | * number of planes per CRTC. Not all platforms really have this many planes, | |
164 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
165 | * between the topmost sprite plane and the cursor plane. | |
166 | * | |
167 | * This is expected to be passed to various register macros | |
168 | * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. | |
169 | */ | |
170 | enum plane_id { | |
171 | PLANE_PRIMARY, | |
172 | PLANE_SPRITE0, | |
173 | PLANE_SPRITE1, | |
174 | PLANE_SPRITE2, | |
6711bd73 ML |
175 | PLANE_SPRITE3, |
176 | PLANE_SPRITE4, | |
177 | PLANE_SPRITE5, | |
09a28bd9 MW |
178 | PLANE_CURSOR, |
179 | ||
180 | I915_MAX_PLANES, | |
181 | }; | |
182 | ||
183 | #define for_each_plane_id_on_crtc(__crtc, __p) \ | |
184 | for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ | |
185 | for_each_if((__crtc)->plane_ids_mask & BIT(__p)) | |
186 | ||
5b6030da R |
187 | enum port { |
188 | PORT_NONE = -1, | |
189 | ||
190 | PORT_A = 0, | |
191 | PORT_B, | |
192 | PORT_C, | |
193 | PORT_D, | |
194 | PORT_E, | |
195 | PORT_F, | |
196 | PORT_G, | |
197 | PORT_H, | |
198 | PORT_I, | |
199 | ||
200 | I915_MAX_PORTS | |
201 | }; | |
202 | ||
203 | #define port_name(p) ((p) + 'A') | |
204 | ||
9c229127 NA |
205 | /* |
206 | * Ports identifier referenced from other drivers. | |
207 | * Expected to remain stable over time | |
208 | */ | |
209 | static inline const char *port_identifier(enum port port) | |
210 | { | |
211 | switch (port) { | |
212 | case PORT_A: | |
213 | return "Port A"; | |
214 | case PORT_B: | |
215 | return "Port B"; | |
216 | case PORT_C: | |
217 | return "Port C"; | |
218 | case PORT_D: | |
219 | return "Port D"; | |
220 | case PORT_E: | |
221 | return "Port E"; | |
222 | case PORT_F: | |
223 | return "Port F"; | |
6c8337da VK |
224 | case PORT_G: |
225 | return "Port G"; | |
226 | case PORT_H: | |
227 | return "Port H"; | |
228 | case PORT_I: | |
229 | return "Port I"; | |
9c229127 NA |
230 | default: |
231 | return "<invalid>"; | |
232 | } | |
233 | } | |
234 | ||
ac213c1b PZ |
235 | enum tc_port { |
236 | PORT_TC_NONE = -1, | |
237 | ||
238 | PORT_TC1 = 0, | |
239 | PORT_TC2, | |
240 | PORT_TC3, | |
241 | PORT_TC4, | |
6c8337da VK |
242 | PORT_TC5, |
243 | PORT_TC6, | |
ac213c1b PZ |
244 | |
245 | I915_MAX_TC_PORTS | |
246 | }; | |
247 | ||
e9b7e142 ID |
248 | enum tc_port_mode { |
249 | TC_PORT_TBT_ALT, | |
250 | TC_PORT_DP_ALT, | |
6075546f PZ |
251 | TC_PORT_LEGACY, |
252 | }; | |
253 | ||
09a28bd9 MW |
254 | enum dpio_channel { |
255 | DPIO_CH0, | |
256 | DPIO_CH1 | |
257 | }; | |
258 | ||
259 | enum dpio_phy { | |
260 | DPIO_PHY0, | |
261 | DPIO_PHY1, | |
262 | DPIO_PHY2, | |
263 | }; | |
264 | ||
265 | #define I915_NUM_PHYS_VLV 2 | |
266 | ||
bdabdb63 VS |
267 | enum aux_ch { |
268 | AUX_CH_A, | |
269 | AUX_CH_B, | |
270 | AUX_CH_C, | |
271 | AUX_CH_D, | |
bb187e93 | 272 | AUX_CH_E, /* ICL+ */ |
bdabdb63 | 273 | AUX_CH_F, |
eb8de23c | 274 | AUX_CH_G, |
bdabdb63 VS |
275 | }; |
276 | ||
277 | #define aux_ch_name(a) ((a) + 'A') | |
278 | ||
09a28bd9 MW |
279 | /* Used by dp and fdi links */ |
280 | struct intel_link_m_n { | |
281 | u32 tu; | |
282 | u32 gmch_m; | |
283 | u32 gmch_n; | |
284 | u32 link_m; | |
285 | u32 link_n; | |
286 | }; | |
287 | ||
358633e7 MR |
288 | enum phy { |
289 | PHY_NONE = -1, | |
290 | ||
291 | PHY_A = 0, | |
292 | PHY_B, | |
293 | PHY_C, | |
294 | PHY_D, | |
295 | PHY_E, | |
296 | PHY_F, | |
5c719708 LDM |
297 | PHY_G, |
298 | PHY_H, | |
299 | PHY_I, | |
358633e7 MR |
300 | |
301 | I915_MAX_PHYS | |
302 | }; | |
303 | ||
304 | #define phy_name(a) ((a) + 'A') | |
305 | ||
0caf6257 AS |
306 | enum phy_fia { |
307 | FIA1, | |
308 | FIA2, | |
309 | FIA3, | |
310 | }; | |
311 | ||
09a28bd9 | 312 | #define for_each_pipe(__dev_priv, __p) \ |
24977870 | 313 | for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) |
09a28bd9 MW |
314 | |
315 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ | |
24977870 | 316 | for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \ |
09a28bd9 MW |
317 | for_each_if((__mask) & BIT(__p)) |
318 | ||
e04f7ece VS |
319 | #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ |
320 | for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ | |
321 | for_each_if ((__mask) & (1 << (__t))) | |
322 | ||
09a28bd9 MW |
323 | #define for_each_universal_plane(__dev_priv, __pipe, __p) \ |
324 | for ((__p) = 0; \ | |
0258404f | 325 | (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ |
09a28bd9 MW |
326 | (__p)++) |
327 | ||
328 | #define for_each_sprite(__dev_priv, __p, __s) \ | |
329 | for ((__s) = 0; \ | |
0258404f | 330 | (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ |
09a28bd9 MW |
331 | (__s)++) |
332 | ||
333 | #define for_each_port_masked(__port, __ports_mask) \ | |
334 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
335 | for_each_if((__ports_mask) & BIT(__port)) | |
336 | ||
dc867bc7 MR |
337 | #define for_each_phy_masked(__phy, __phys_mask) \ |
338 | for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ | |
339 | for_each_if((__phys_mask) & BIT(__phy)) | |
340 | ||
09a28bd9 MW |
341 | #define for_each_crtc(dev, crtc) \ |
342 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) | |
343 | ||
344 | #define for_each_intel_plane(dev, intel_plane) \ | |
345 | list_for_each_entry(intel_plane, \ | |
346 | &(dev)->mode_config.plane_list, \ | |
347 | base.head) | |
348 | ||
349 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ | |
350 | list_for_each_entry(intel_plane, \ | |
351 | &(dev)->mode_config.plane_list, \ | |
352 | base.head) \ | |
353 | for_each_if((plane_mask) & \ | |
9a3a41df | 354 | drm_plane_mask(&intel_plane->base)) |
09a28bd9 MW |
355 | |
356 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ | |
357 | list_for_each_entry(intel_plane, \ | |
358 | &(dev)->mode_config.plane_list, \ | |
359 | base.head) \ | |
360 | for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) | |
361 | ||
362 | #define for_each_intel_crtc(dev, intel_crtc) \ | |
363 | list_for_each_entry(intel_crtc, \ | |
364 | &(dev)->mode_config.crtc_list, \ | |
365 | base.head) | |
366 | ||
367 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ | |
368 | list_for_each_entry(intel_crtc, \ | |
369 | &(dev)->mode_config.crtc_list, \ | |
370 | base.head) \ | |
40560e26 | 371 | for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base)) |
09a28bd9 MW |
372 | |
373 | #define for_each_intel_encoder(dev, intel_encoder) \ | |
374 | list_for_each_entry(intel_encoder, \ | |
375 | &(dev)->mode_config.encoder_list, \ | |
376 | base.head) | |
377 | ||
14aa521c VS |
378 | #define for_each_intel_dp(dev, intel_encoder) \ |
379 | for_each_intel_encoder(dev, intel_encoder) \ | |
380 | for_each_if(intel_encoder_is_dp(intel_encoder)) | |
381 | ||
09a28bd9 MW |
382 | #define for_each_intel_connector_iter(intel_connector, iter) \ |
383 | while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) | |
384 | ||
385 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ | |
386 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
387 | for_each_if((intel_encoder)->base.crtc == (__crtc)) | |
388 | ||
389 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ | |
390 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
391 | for_each_if((intel_connector)->base.encoder == (__encoder)) | |
392 | ||
0dd14be3 VS |
393 | #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ |
394 | for ((__i) = 0; \ | |
395 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
396 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
397 | (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ | |
398 | (__i)++) \ | |
399 | for_each_if(plane) | |
400 | ||
09a28bd9 MW |
401 | #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ |
402 | for ((__i) = 0; \ | |
403 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
404 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
405 | (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ | |
406 | (__i)++) \ | |
407 | for_each_if(plane) | |
408 | ||
409 | #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ | |
410 | for ((__i) = 0; \ | |
411 | (__i) < (__state)->base.dev->mode_config.num_crtc && \ | |
412 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
413 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
414 | (__i)++) \ | |
415 | for_each_if(crtc) | |
416 | ||
417 | #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ | |
418 | for ((__i) = 0; \ | |
419 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
420 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
421 | (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ | |
422 | (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ | |
423 | (__i)++) \ | |
424 | for_each_if(plane) | |
425 | ||
ff43bc37 VS |
426 | #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ |
427 | for ((__i) = 0; \ | |
428 | (__i) < (__state)->base.dev->mode_config.num_crtc && \ | |
429 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
430 | (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ | |
431 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
432 | (__i)++) \ | |
433 | for_each_if(crtc) | |
434 | ||
0456417e JRS |
435 | #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ |
436 | for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ | |
437 | (__i) >= 0 && \ | |
438 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
439 | (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ | |
440 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
441 | (__i)--) \ | |
442 | for_each_if(crtc) | |
443 | ||
af9fbfa6 ML |
444 | #define intel_atomic_crtc_state_for_each_plane_state( \ |
445 | plane, plane_state, \ | |
446 | crtc_state) \ | |
447 | for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \ | |
448 | ((crtc_state)->base.plane_mask)) \ | |
449 | for_each_if ((plane_state = \ | |
450 | to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state, &plane->base)))) | |
451 | ||
a4a15777 | 452 | void intel_link_compute_m_n(u16 bpp, int nlanes, |
09a28bd9 MW |
453 | int pixel_clock, int link_clock, |
454 | struct intel_link_m_n *m_n, | |
ed06efb8 | 455 | bool constant_n, bool fec_enable); |
63eaf9ac | 456 | bool is_ccs_modifier(u64 modifier); |
46034d2b | 457 | void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv); |
aa5ca8b7 VS |
458 | u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, |
459 | u32 pixel_format, u64 modifier); | |
54d4d719 | 460 | bool intel_plane_can_remap(const struct intel_plane_state *plane_state); |
2d20411e VS |
461 | enum drm_mode_status |
462 | intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, | |
463 | const struct drm_display_mode *mode); | |
358633e7 | 464 | enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); |
46034d2b | 465 | |
3e187625 JN |
466 | void intel_plane_destroy(struct drm_plane *plane); |
467 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); | |
468 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); | |
469 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); | |
470 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); | |
471 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, | |
472 | const char *name, u32 reg, int ref_freq); | |
473 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
474 | const char *name, u32 reg); | |
475 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); | |
476 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv); | |
477 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); | |
478 | unsigned int intel_fb_xy_to_linear(int x, int y, | |
479 | const struct intel_plane_state *state, | |
480 | int plane); | |
481 | unsigned int intel_fb_align_height(const struct drm_framebuffer *fb, | |
482 | int color_plane, unsigned int height); | |
483 | void intel_add_fb_offsets(int *x, int *y, | |
484 | const struct intel_plane_state *state, int plane); | |
485 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); | |
486 | unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); | |
487 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); | |
488 | int intel_display_suspend(struct drm_device *dev); | |
489 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv); | |
490 | void intel_encoder_destroy(struct drm_encoder *encoder); | |
491 | struct drm_display_mode * | |
492 | intel_encoder_current_mode(struct intel_encoder *encoder); | |
493 | bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); | |
494 | bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); | |
495 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, | |
496 | enum port port); | |
497 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, | |
498 | struct drm_file *file_priv); | |
499 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, | |
500 | enum pipe pipe); | |
501 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); | |
502 | ||
503 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); | |
504 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, | |
505 | struct intel_digital_port *dport, | |
506 | unsigned int expected_mask); | |
507 | int intel_get_load_detect_pipe(struct drm_connector *connector, | |
508 | const struct drm_display_mode *mode, | |
509 | struct intel_load_detect_pipe *old, | |
510 | struct drm_modeset_acquire_ctx *ctx); | |
511 | void intel_release_load_detect_pipe(struct drm_connector *connector, | |
512 | struct intel_load_detect_pipe *old, | |
513 | struct drm_modeset_acquire_ctx *ctx); | |
514 | struct i915_vma * | |
515 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, | |
516 | const struct i915_ggtt_view *view, | |
517 | bool uses_fence, | |
518 | unsigned long *out_flags); | |
519 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); | |
520 | struct drm_framebuffer * | |
521 | intel_framebuffer_create(struct drm_i915_gem_object *obj, | |
522 | struct drm_mode_fb_cmd2 *mode_cmd); | |
523 | int intel_prepare_plane_fb(struct drm_plane *plane, | |
524 | struct drm_plane_state *new_state); | |
525 | void intel_cleanup_plane_fb(struct drm_plane *plane, | |
526 | struct drm_plane_state *old_state); | |
527 | ||
528 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, | |
529 | enum pipe pipe); | |
530 | ||
531 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, | |
532 | const struct dpll *dpll); | |
533 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); | |
534 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); | |
535 | bool intel_fuzzy_clock_check(int clock1, int clock2); | |
536 | ||
537 | void intel_prepare_reset(struct drm_i915_private *dev_priv); | |
538 | void intel_finish_reset(struct drm_i915_private *dev_priv); | |
539 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
540 | struct intel_crtc_state *pipe_config); | |
541 | void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, | |
542 | enum link_m_n_set m_n); | |
3e187625 JN |
543 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
544 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, | |
545 | struct dpll *best_clock); | |
546 | int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); | |
547 | ||
548 | bool intel_crtc_active(struct intel_crtc *crtc); | |
549 | bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); | |
550 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state); | |
551 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state); | |
552 | enum intel_display_power_domain intel_port_to_power_domain(enum port port); | |
553 | enum intel_display_power_domain | |
554 | intel_aux_power_domain(struct intel_digital_port *dig_port); | |
555 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, | |
556 | struct intel_crtc_state *pipe_config); | |
557 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, | |
558 | struct intel_crtc_state *crtc_state); | |
559 | ||
560 | u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center); | |
561 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); | |
562 | int skl_max_scale(const struct intel_crtc_state *crtc_state, | |
d1d23d7f | 563 | const struct drm_format_info *format); |
3e187625 JN |
564 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
565 | const struct intel_plane_state *plane_state); | |
566 | u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state); | |
567 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, | |
568 | const struct intel_plane_state *plane_state); | |
569 | u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state); | |
570 | u32 skl_plane_stride(const struct intel_plane_state *plane_state, | |
571 | int plane); | |
572 | int skl_check_plane_surface(struct intel_plane_state *plane_state); | |
573 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state); | |
574 | int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); | |
575 | unsigned int i9xx_plane_max_stride(struct intel_plane *plane, | |
576 | u32 pixel_format, u64 modifier, | |
577 | unsigned int rotation); | |
578 | int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); | |
579 | ||
580 | struct intel_display_error_state * | |
581 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
582 | void intel_display_print_error_state(struct drm_i915_error_state_buf *e, | |
583 | struct intel_display_error_state *error); | |
584 | ||
585 | /* modesetting */ | |
6cd02e77 JN |
586 | void intel_modeset_init_hw(struct drm_i915_private *i915); |
587 | int intel_modeset_init(struct drm_i915_private *i915); | |
9980c3c1 | 588 | void intel_modeset_driver_remove(struct drm_i915_private *i915); |
3e187625 | 589 | void intel_display_resume(struct drm_device *dev); |
3e187625 JN |
590 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv); |
591 | ||
592 | /* modesetting asserts */ | |
593 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, | |
594 | enum pipe pipe); | |
595 | void assert_pll(struct drm_i915_private *dev_priv, | |
596 | enum pipe pipe, bool state); | |
597 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
598 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
599 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); | |
600 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
601 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
602 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
603 | enum pipe pipe, bool state); | |
604 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
605 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
606 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); | |
607 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
608 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
609 | ||
0a2ecbe5 JN |
610 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
611 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
612 | * which may not necessarily be a user visible problem. This will either | |
613 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
614 | * enable distros and users to tailor their preferred amount of i915 abrt | |
615 | * spam. | |
616 | */ | |
617 | #define I915_STATE_WARN(condition, format...) ({ \ | |
618 | int __ret_warn_on = !!(condition); \ | |
619 | if (unlikely(__ret_warn_on)) \ | |
620 | if (!WARN(i915_modparams.verbose_state_checks, format)) \ | |
621 | DRM_ERROR(format); \ | |
622 | unlikely(__ret_warn_on); \ | |
623 | }) | |
624 | ||
625 | #define I915_STATE_WARN_ON(x) \ | |
626 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
627 | ||
09a28bd9 | 628 | #endif |