Commit | Line | Data |
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09a28bd9 | 1 | /* |
5b6030da | 2 | * Copyright © 2006-2019 Intel Corporation |
09a28bd9 MW |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DISPLAY_H_ | |
26 | #define _INTEL_DISPLAY_H_ | |
27 | ||
d78aa650 DV |
28 | #include <drm/drm_util.h> |
29 | ||
a68819cc | 30 | #include "i915_reg_defs.h" |
acc855d3 | 31 | #include "intel_display_limits.h" |
a68819cc | 32 | |
cc2396ff | 33 | enum drm_scaling_filter; |
3e187625 | 34 | struct dpll; |
3dadb4a1 | 35 | struct drm_atomic_state; |
3e187625 JN |
36 | struct drm_connector; |
37 | struct drm_device; | |
2d20411e | 38 | struct drm_display_mode; |
3e187625 JN |
39 | struct drm_encoder; |
40 | struct drm_file; | |
d1d23d7f | 41 | struct drm_format_info; |
3e187625 | 42 | struct drm_framebuffer; |
3e187625 | 43 | struct drm_i915_gem_object; |
46034d2b | 44 | struct drm_i915_private; |
83d2bdb6 | 45 | struct drm_mode_fb_cmd2; |
3e187625 JN |
46 | struct drm_modeset_acquire_ctx; |
47 | struct drm_plane; | |
48 | struct drm_plane_state; | |
33e7a975 | 49 | struct i915_address_space; |
3bb6a442 | 50 | struct i915_gtt_view; |
aac97871 | 51 | struct intel_atomic_state; |
3e187625 JN |
52 | struct intel_crtc; |
53 | struct intel_crtc_state; | |
54 | struct intel_digital_port; | |
55 | struct intel_dp; | |
56 | struct intel_encoder; | |
46d12f91 | 57 | struct intel_initial_plane_config; |
6398acf3 | 58 | struct intel_link_m_n; |
3e187625 | 59 | struct intel_plane; |
54d4d719 | 60 | struct intel_plane_state; |
2c7676b6 | 61 | struct intel_power_domain_mask; |
3e187625 JN |
62 | struct intel_remapped_info; |
63 | struct intel_rotation_info; | |
96db1443 | 64 | struct pci_dev; |
40053823 | 65 | struct work_struct; |
46034d2b | 66 | |
09a28bd9 MW |
67 | |
68 | #define pipe_name(p) ((p) + 'A') | |
69 | ||
09a28bd9 MW |
70 | static inline const char *transcoder_name(enum transcoder transcoder) |
71 | { | |
72 | switch (transcoder) { | |
73 | case TRANSCODER_A: | |
74 | return "A"; | |
75 | case TRANSCODER_B: | |
76 | return "B"; | |
77 | case TRANSCODER_C: | |
78 | return "C"; | |
f1f1d4fa LDM |
79 | case TRANSCODER_D: |
80 | return "D"; | |
09a28bd9 MW |
81 | case TRANSCODER_EDP: |
82 | return "EDP"; | |
83 | case TRANSCODER_DSI_A: | |
84 | return "DSI A"; | |
85 | case TRANSCODER_DSI_C: | |
86 | return "DSI C"; | |
87 | default: | |
88 | return "<invalid>"; | |
89 | } | |
90 | } | |
91 | ||
92 | static inline bool transcoder_is_dsi(enum transcoder transcoder) | |
93 | { | |
94 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
95 | } | |
96 | ||
97 | /* | |
98 | * Global legacy plane identifier. Valid only for primary/sprite | |
99 | * planes on pre-g4x, and only for primary planes on g4x-bdw. | |
100 | */ | |
101 | enum i9xx_plane_id { | |
102 | PLANE_A, | |
103 | PLANE_B, | |
104 | PLANE_C, | |
105 | }; | |
106 | ||
107 | #define plane_name(p) ((p) + 'A') | |
0258404f | 108 | #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') |
09a28bd9 | 109 | |
09a28bd9 MW |
110 | #define for_each_plane_id_on_crtc(__crtc, __p) \ |
111 | for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ | |
112 | for_each_if((__crtc)->plane_ids_mask & BIT(__p)) | |
113 | ||
b88da660 | 114 | #define for_each_dbuf_slice(__dev_priv, __slice) \ |
8435576b | 115 | for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ |
04155815 | 116 | for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice)) |
8435576b | 117 | |
b88da660 VS |
118 | #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ |
119 | for_each_dbuf_slice((__dev_priv), (__slice)) \ | |
120 | for_each_if((__mask) & BIT(__slice)) | |
8435576b | 121 | |
5b6030da R |
122 | #define port_name(p) ((p) + 'A') |
123 | ||
9c229127 NA |
124 | /* |
125 | * Ports identifier referenced from other drivers. | |
126 | * Expected to remain stable over time | |
127 | */ | |
128 | static inline const char *port_identifier(enum port port) | |
129 | { | |
130 | switch (port) { | |
131 | case PORT_A: | |
132 | return "Port A"; | |
133 | case PORT_B: | |
134 | return "Port B"; | |
135 | case PORT_C: | |
136 | return "Port C"; | |
137 | case PORT_D: | |
138 | return "Port D"; | |
139 | case PORT_E: | |
140 | return "Port E"; | |
141 | case PORT_F: | |
142 | return "Port F"; | |
6c8337da VK |
143 | case PORT_G: |
144 | return "Port G"; | |
145 | case PORT_H: | |
146 | return "Port H"; | |
147 | case PORT_I: | |
148 | return "Port I"; | |
9c229127 NA |
149 | default: |
150 | return "<invalid>"; | |
151 | } | |
152 | } | |
153 | ||
ac213c1b | 154 | enum tc_port { |
320c670c VS |
155 | TC_PORT_NONE = -1, |
156 | ||
157 | TC_PORT_1 = 0, | |
158 | TC_PORT_2, | |
159 | TC_PORT_3, | |
160 | TC_PORT_4, | |
161 | TC_PORT_5, | |
162 | TC_PORT_6, | |
ac213c1b PZ |
163 | |
164 | I915_MAX_TC_PORTS | |
165 | }; | |
166 | ||
bdabdb63 | 167 | enum aux_ch { |
bb45217f VS |
168 | AUX_CH_NONE = -1, |
169 | ||
bdabdb63 VS |
170 | AUX_CH_A, |
171 | AUX_CH_B, | |
172 | AUX_CH_C, | |
173 | AUX_CH_D, | |
bb187e93 | 174 | AUX_CH_E, /* ICL+ */ |
bdabdb63 | 175 | AUX_CH_F, |
eb8de23c | 176 | AUX_CH_G, |
5526fa0b VS |
177 | AUX_CH_H, |
178 | AUX_CH_I, | |
df034b97 VS |
179 | |
180 | /* tgl+ */ | |
181 | AUX_CH_USBC1 = AUX_CH_D, | |
182 | AUX_CH_USBC2, | |
183 | AUX_CH_USBC3, | |
184 | AUX_CH_USBC4, | |
185 | AUX_CH_USBC5, | |
186 | AUX_CH_USBC6, | |
ed2615a8 MR |
187 | |
188 | /* XE_LPD repositions D/E offsets and bitfields */ | |
189 | AUX_CH_D_XELPD = AUX_CH_USBC5, | |
190 | AUX_CH_E_XELPD, | |
bdabdb63 VS |
191 | }; |
192 | ||
193 | #define aux_ch_name(a) ((a) + 'A') | |
194 | ||
358633e7 MR |
195 | enum phy { |
196 | PHY_NONE = -1, | |
197 | ||
198 | PHY_A = 0, | |
199 | PHY_B, | |
200 | PHY_C, | |
201 | PHY_D, | |
202 | PHY_E, | |
203 | PHY_F, | |
5c719708 LDM |
204 | PHY_G, |
205 | PHY_H, | |
206 | PHY_I, | |
358633e7 MR |
207 | |
208 | I915_MAX_PHYS | |
209 | }; | |
210 | ||
211 | #define phy_name(a) ((a) + 'A') | |
212 | ||
0caf6257 AS |
213 | enum phy_fia { |
214 | FIA1, | |
215 | FIA2, | |
216 | FIA3, | |
217 | }; | |
218 | ||
5734c177 JN |
219 | #define for_each_hpd_pin(__pin) \ |
220 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
221 | ||
09a28bd9 | 222 | #define for_each_pipe(__dev_priv, __p) \ |
b8b65ccd | 223 | for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ |
00c6cbfd | 224 | for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p)) |
09a28bd9 MW |
225 | |
226 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ | |
b8b65ccd | 227 | for_each_pipe(__dev_priv, __p) \ |
09a28bd9 MW |
228 | for_each_if((__mask) & BIT(__p)) |
229 | ||
10cf8e75 | 230 | #define for_each_cpu_transcoder(__dev_priv, __t) \ |
e04f7ece | 231 | for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ |
00c6cbfd | 232 | for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t)) |
10cf8e75 VS |
233 | |
234 | #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ | |
235 | for_each_cpu_transcoder(__dev_priv, __t) \ | |
236 | for_each_if ((__mask) & BIT(__t)) | |
e04f7ece | 237 | |
09a28bd9 MW |
238 | #define for_each_sprite(__dev_priv, __p, __s) \ |
239 | for ((__s) = 0; \ | |
0258404f | 240 | (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \ |
09a28bd9 MW |
241 | (__s)++) |
242 | ||
c4a774c4 JN |
243 | #define for_each_port(__port) \ |
244 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) | |
245 | ||
246 | #define for_each_port_masked(__port, __ports_mask) \ | |
247 | for_each_port(__port) \ | |
09a28bd9 MW |
248 | for_each_if((__ports_mask) & BIT(__port)) |
249 | ||
dc867bc7 MR |
250 | #define for_each_phy_masked(__phy, __phys_mask) \ |
251 | for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ | |
252 | for_each_if((__phys_mask) & BIT(__phy)) | |
253 | ||
09a28bd9 MW |
254 | #define for_each_crtc(dev, crtc) \ |
255 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) | |
256 | ||
257 | #define for_each_intel_plane(dev, intel_plane) \ | |
258 | list_for_each_entry(intel_plane, \ | |
259 | &(dev)->mode_config.plane_list, \ | |
260 | base.head) | |
261 | ||
262 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ | |
263 | list_for_each_entry(intel_plane, \ | |
264 | &(dev)->mode_config.plane_list, \ | |
265 | base.head) \ | |
266 | for_each_if((plane_mask) & \ | |
9a3a41df | 267 | drm_plane_mask(&intel_plane->base)) |
09a28bd9 MW |
268 | |
269 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ | |
270 | list_for_each_entry(intel_plane, \ | |
271 | &(dev)->mode_config.plane_list, \ | |
272 | base.head) \ | |
273 | for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) | |
274 | ||
275 | #define for_each_intel_crtc(dev, intel_crtc) \ | |
276 | list_for_each_entry(intel_crtc, \ | |
277 | &(dev)->mode_config.crtc_list, \ | |
278 | base.head) | |
279 | ||
f461ea5d | 280 | #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ |
09a28bd9 MW |
281 | list_for_each_entry(intel_crtc, \ |
282 | &(dev)->mode_config.crtc_list, \ | |
283 | base.head) \ | |
f461ea5d | 284 | for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) |
09a28bd9 MW |
285 | |
286 | #define for_each_intel_encoder(dev, intel_encoder) \ | |
287 | list_for_each_entry(intel_encoder, \ | |
288 | &(dev)->mode_config.encoder_list, \ | |
289 | base.head) | |
290 | ||
ca851c22 VS |
291 | #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \ |
292 | list_for_each_entry(intel_encoder, \ | |
293 | &(dev)->mode_config.encoder_list, \ | |
294 | base.head) \ | |
295 | for_each_if((encoder_mask) & \ | |
296 | drm_encoder_mask(&intel_encoder->base)) | |
297 | ||
a22af61d | 298 | #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ |
b64d6c51 GM |
299 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
300 | for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ | |
301 | intel_encoder_can_psr(intel_encoder)) | |
302 | ||
14aa521c VS |
303 | #define for_each_intel_dp(dev, intel_encoder) \ |
304 | for_each_intel_encoder(dev, intel_encoder) \ | |
305 | for_each_if(intel_encoder_is_dp(intel_encoder)) | |
306 | ||
a22af61d | 307 | #define for_each_intel_encoder_with_psr(dev, intel_encoder) \ |
b64d6c51 GM |
308 | for_each_intel_encoder((dev), (intel_encoder)) \ |
309 | for_each_if(intel_encoder_can_psr(intel_encoder)) | |
310 | ||
09a28bd9 MW |
311 | #define for_each_intel_connector_iter(intel_connector, iter) \ |
312 | while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) | |
313 | ||
314 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ | |
315 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
316 | for_each_if((intel_encoder)->base.crtc == (__crtc)) | |
317 | ||
0dd14be3 VS |
318 | #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \ |
319 | for ((__i) = 0; \ | |
320 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
321 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
322 | (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \ | |
323 | (__i)++) \ | |
324 | for_each_if(plane) | |
325 | ||
efb2b57e VS |
326 | #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ |
327 | for ((__i) = 0; \ | |
328 | (__i) < (__state)->base.dev->mode_config.num_crtc && \ | |
329 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
330 | (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ | |
331 | (__i)++) \ | |
332 | for_each_if(crtc) | |
333 | ||
09a28bd9 MW |
334 | #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ |
335 | for ((__i) = 0; \ | |
336 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
337 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
338 | (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ | |
339 | (__i)++) \ | |
340 | for_each_if(plane) | |
341 | ||
342 | #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ | |
343 | for ((__i) = 0; \ | |
344 | (__i) < (__state)->base.dev->mode_config.num_crtc && \ | |
345 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
346 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
347 | (__i)++) \ | |
348 | for_each_if(crtc) | |
349 | ||
350 | #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ | |
351 | for ((__i) = 0; \ | |
352 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
353 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
354 | (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \ | |
355 | (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ | |
356 | (__i)++) \ | |
357 | for_each_if(plane) | |
358 | ||
ff43bc37 VS |
359 | #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ |
360 | for ((__i) = 0; \ | |
361 | (__i) < (__state)->base.dev->mode_config.num_crtc && \ | |
362 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
363 | (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ | |
364 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
365 | (__i)++) \ | |
366 | for_each_if(crtc) | |
367 | ||
0456417e JRS |
368 | #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ |
369 | for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ | |
370 | (__i) >= 0 && \ | |
371 | ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ | |
372 | (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ | |
373 | (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ | |
374 | (__i)--) \ | |
375 | for_each_if(crtc) | |
376 | ||
af9fbfa6 ML |
377 | #define intel_atomic_crtc_state_for_each_plane_state( \ |
378 | plane, plane_state, \ | |
379 | crtc_state) \ | |
2b808b3a ML |
380 | for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \ |
381 | ((crtc_state)->uapi.plane_mask)) \ | |
af9fbfa6 | 382 | for_each_if ((plane_state = \ |
2b808b3a | 383 | to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base)))) |
af9fbfa6 | 384 | |
74e8cd5b JRS |
385 | #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \ |
386 | for ((__i) = 0; \ | |
387 | (__i) < (__state)->base.num_connector; \ | |
388 | (__i)++) \ | |
389 | for_each_if ((__state)->base.connectors[__i].ptr && \ | |
390 | ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ | |
391 | (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) | |
392 | ||
3dadb4a1 | 393 | int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); |
9e363c82 VS |
394 | int intel_atomic_add_affected_planes(struct intel_atomic_state *state, |
395 | struct intel_crtc *crtc); | |
aac97871 VS |
396 | u8 intel_calc_active_pipes(struct intel_atomic_state *state, |
397 | u8 active_pipes); | |
a4a15777 | 398 | void intel_link_compute_m_n(u16 bpp, int nlanes, |
09a28bd9 MW |
399 | int pixel_clock, int link_clock, |
400 | struct intel_link_m_n *m_n, | |
c46af562 | 401 | bool fec_enable); |
aa5ca8b7 VS |
402 | u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, |
403 | u32 pixel_format, u64 modifier); | |
2d20411e VS |
404 | enum drm_mode_status |
405 | intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, | |
63dc014e ML |
406 | const struct drm_display_mode *mode, |
407 | bool bigjoiner); | |
358633e7 | 408 | enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); |
bfb926e3 | 409 | bool is_trans_port_sync_mode(const struct intel_crtc_state *state); |
df529053 VS |
410 | bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); |
411 | bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); | |
a6e7a006 VS |
412 | u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); |
413 | struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); | |
df17ff62 JN |
414 | bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); |
415 | bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, | |
416 | const struct intel_crtc_state *pipe_config, | |
417 | bool fastset); | |
46034d2b | 418 | |
3e187625 | 419 | void intel_plane_destroy(struct drm_plane *plane); |
3cdcdc34 VS |
420 | void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); |
421 | void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); | |
8c66081b VS |
422 | void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); |
423 | void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); | |
3e187625 JN |
424 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); |
425 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); | |
3e187625 JN |
426 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); |
427 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, | |
428 | const char *name, u32 reg, int ref_freq); | |
429 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
430 | const char *name, u32 reg); | |
3e187625 JN |
431 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
432 | unsigned int intel_fb_xy_to_linear(int x, int y, | |
433 | const struct intel_plane_state *state, | |
434 | int plane); | |
3e187625 JN |
435 | void intel_add_fb_offsets(int *x, int *y, |
436 | const struct intel_plane_state *state, int plane); | |
437 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); | |
438 | unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); | |
439 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); | |
3e187625 JN |
440 | void intel_encoder_destroy(struct drm_encoder *encoder); |
441 | struct drm_display_mode * | |
442 | intel_encoder_current_mode(struct intel_encoder *encoder); | |
df17ff62 JN |
443 | void intel_encoder_get_config(struct intel_encoder *encoder, |
444 | struct intel_crtc_state *crtc_state); | |
3e187625 JN |
445 | bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); |
446 | bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); | |
fdc0b946 | 447 | bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); |
3e187625 JN |
448 | enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, |
449 | enum port port); | |
450 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, | |
451 | struct drm_file *file_priv); | |
3e187625 | 452 | |
9eae5e27 | 453 | int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); |
3e187625 | 454 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
7801f3b7 | 455 | struct intel_digital_port *dig_port, |
3e187625 | 456 | unsigned int expected_mask); |
3e187625 JN |
457 | struct drm_framebuffer * |
458 | intel_framebuffer_create(struct drm_i915_gem_object *obj, | |
459 | struct drm_mode_fb_cmd2 *mode_cmd); | |
3e187625 | 460 | |
3e187625 JN |
461 | bool intel_fuzzy_clock_check(int clock1, int clock2); |
462 | ||
1d06c820 | 463 | void intel_zero_m_n(struct intel_link_m_n *m_n); |
a68819cc VS |
464 | void intel_set_m_n(struct drm_i915_private *i915, |
465 | const struct intel_link_m_n *m_n, | |
466 | i915_reg_t data_m_reg, i915_reg_t data_n_reg, | |
467 | i915_reg_t link_m_reg, i915_reg_t link_n_reg); | |
468 | void intel_get_m_n(struct drm_i915_private *i915, | |
469 | struct intel_link_m_n *m_n, | |
470 | i915_reg_t data_m_reg, i915_reg_t data_n_reg, | |
471 | i915_reg_t link_m_reg, i915_reg_t link_n_reg); | |
1d06c820 VS |
472 | bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, |
473 | enum transcoder transcoder); | |
0adc41de VS |
474 | void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, |
475 | enum transcoder cpu_transcoder, | |
be0c94ee | 476 | const struct intel_link_m_n *m_n); |
0adc41de VS |
477 | void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, |
478 | enum transcoder cpu_transcoder, | |
be0c94ee | 479 | const struct intel_link_m_n *m_n); |
5cd06644 VS |
480 | void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, |
481 | enum transcoder cpu_transcoder, | |
482 | struct intel_link_m_n *m_n); | |
483 | void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, | |
484 | enum transcoder cpu_transcoder, | |
485 | struct intel_link_m_n *m_n); | |
7d9ae633 VS |
486 | void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
487 | struct intel_crtc_state *pipe_config); | |
3e187625 | 488 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
623411c2 | 489 | int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config); |
979e1b32 | 490 | enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port); |
3e187625 JN |
491 | enum intel_display_power_domain |
492 | intel_aux_power_domain(struct intel_digital_port *dig_port); | |
3e187625 JN |
493 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
494 | struct intel_crtc_state *crtc_state); | |
9eae5e27 | 495 | void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); |
46d12f91 | 496 | |
c640f6c5 | 497 | int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc); |
5331889b | 498 | unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); |
3e187625 | 499 | |
2f9a995a | 500 | bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); |
4941f35b | 501 | |
8cf41f31 DA |
502 | struct intel_encoder * |
503 | intel_get_crtc_new_encoder(const struct intel_atomic_state *state, | |
504 | const struct intel_crtc_state *crtc_state); | |
1cd967c6 DA |
505 | void intel_plane_disable_noatomic(struct intel_crtc *crtc, |
506 | struct intel_plane *plane); | |
2c7676b6 JN |
507 | void intel_set_plane_visible(struct intel_crtc_state *crtc_state, |
508 | struct intel_plane_state *plane_state, | |
509 | bool visible); | |
510 | void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); | |
99ce270a | 511 | |
2c7676b6 JN |
512 | void intel_update_watermarks(struct drm_i915_private *i915); |
513 | ||
3e187625 | 514 | /* modesetting */ |
0c316114 VS |
515 | int intel_modeset_all_pipes(struct intel_atomic_state *state, |
516 | const char *reason); | |
2c7676b6 JN |
517 | void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, |
518 | struct intel_power_domain_mask *old_domains); | |
519 | void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, | |
520 | struct intel_power_domain_mask *domains); | |
3e187625 | 521 | |
40053823 JN |
522 | /* interface for intel_display_driver.c */ |
523 | void intel_setup_outputs(struct drm_i915_private *i915); | |
524 | int intel_initial_commit(struct drm_device *dev); | |
525 | void intel_panel_sanitize_ssc(struct drm_i915_private *i915); | |
526 | void intel_update_czclk(struct drm_i915_private *i915); | |
527 | void intel_atomic_helper_free_state_worker(struct work_struct *work); | |
528 | enum drm_mode_status intel_mode_valid(struct drm_device *dev, | |
529 | const struct drm_display_mode *mode); | |
530 | int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, | |
531 | bool nonblock); | |
532 | ||
533 | void intel_hpd_poll_fini(struct drm_i915_private *i915); | |
534 | ||
3e187625 | 535 | /* modesetting asserts */ |
8c66081b VS |
536 | void assert_transcoder(struct drm_i915_private *dev_priv, |
537 | enum transcoder cpu_transcoder, bool state); | |
538 | #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) | |
539 | #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) | |
3e187625 | 540 | |
b8e6185b JN |
541 | /* |
542 | * Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity | |
543 | * checks to check for unexpected conditions which may not necessarily be a user | |
544 | * visible problem. This will either WARN() or DRM_ERROR() depending on the | |
545 | * verbose_state_checks module param, to enable distros and users to tailor | |
546 | * their preferred amount of i915 abrt spam. | |
0a2ecbe5 JN |
547 | */ |
548 | #define I915_STATE_WARN(condition, format...) ({ \ | |
549 | int __ret_warn_on = !!(condition); \ | |
550 | if (unlikely(__ret_warn_on)) \ | |
551 | if (!WARN(i915_modparams.verbose_state_checks, format)) \ | |
552 | DRM_ERROR(format); \ | |
553 | unlikely(__ret_warn_on); \ | |
554 | }) | |
555 | ||
a7f46d5b TU |
556 | bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); |
557 | ||
09a28bd9 | 558 | #endif |