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51390cc0 RS |
1 | // SPDX-License-Identifier: MIT |
2 | /* | |
3 | * Copyright © 2023 Intel Corporation | |
4 | */ | |
5 | ||
234fcb97 CT |
6 | #include <linux/log2.h> |
7 | #include <linux/math64.h> | |
51390cc0 RS |
8 | #include "i915_reg.h" |
9 | #include "intel_cx0_phy.h" | |
10 | #include "intel_cx0_phy_regs.h" | |
ea8af87a MK |
11 | #include "intel_ddi.h" |
12 | #include "intel_ddi_buf_trans.h" | |
51390cc0 RS |
13 | #include "intel_de.h" |
14 | #include "intel_display_types.h" | |
15 | #include "intel_dp.h" | |
929f527a | 16 | #include "intel_hdmi.h" |
51390cc0 RS |
17 | #include "intel_panel.h" |
18 | #include "intel_psr.h" | |
19 | #include "intel_tc.h" | |
20 | ||
21 | #define MB_WRITE_COMMITTED true | |
22 | #define MB_WRITE_UNCOMMITTED false | |
23 | ||
24 | #define for_each_cx0_lane_in_mask(__lane_mask, __lane) \ | |
25 | for ((__lane) = 0; (__lane) < 2; (__lane)++) \ | |
26 | for_each_if((__lane_mask) & BIT(__lane)) | |
27 | ||
28 | #define INTEL_CX0_LANE0 BIT(0) | |
29 | #define INTEL_CX0_LANE1 BIT(1) | |
30 | #define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0) | |
31 | ||
32 | bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy) | |
33 | { | |
34 | if (IS_METEORLAKE(i915) && (phy < PHY_C)) | |
35 | return true; | |
36 | ||
37 | return false; | |
38 | } | |
39 | ||
40 | static int lane_mask_to_lane(u8 lane_mask) | |
41 | { | |
42 | if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) || | |
43 | hweight8(lane_mask) != 1)) | |
44 | return 0; | |
45 | ||
46 | return ilog2(lane_mask); | |
47 | } | |
48 | ||
49 | static void | |
50 | assert_dc_off(struct drm_i915_private *i915) | |
51 | { | |
52 | bool enabled; | |
53 | ||
54 | enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF); | |
55 | drm_WARN_ON(&i915->drm, !enabled); | |
56 | } | |
57 | ||
58 | /* | |
59 | * Prepare HW for CX0 phy transactions. | |
60 | * | |
61 | * It is required that PSR and DC5/6 are disabled before any CX0 message | |
62 | * bus transaction is executed. | |
63 | */ | |
64 | static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) | |
65 | { | |
66 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
67 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
68 | ||
69 | intel_psr_pause(intel_dp); | |
70 | return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF); | |
71 | } | |
72 | ||
73 | static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) | |
74 | { | |
75 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
76 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
77 | ||
78 | intel_psr_resume(intel_dp); | |
79 | intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref); | |
80 | } | |
81 | ||
82 | static void intel_clear_response_ready_flag(struct drm_i915_private *i915, | |
83 | enum port port, int lane) | |
84 | { | |
85 | intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), | |
86 | 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); | |
87 | } | |
88 | ||
89 | static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane) | |
90 | { | |
91 | enum phy phy = intel_port_to_phy(i915, port); | |
92 | ||
93 | intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
94 | XELPDP_PORT_M2P_TRANSACTION_RESET); | |
95 | ||
96 | if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
97 | XELPDP_PORT_M2P_TRANSACTION_RESET, | |
98 | XELPDP_MSGBUS_TIMEOUT_SLOW)) { | |
99 | drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); | |
100 | return; | |
101 | } | |
102 | ||
103 | intel_clear_response_ready_flag(i915, port, lane); | |
104 | } | |
105 | ||
106 | static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, | |
107 | int command, int lane, u32 *val) | |
108 | { | |
109 | enum phy phy = intel_port_to_phy(i915, port); | |
110 | ||
111 | if (__intel_de_wait_for_register(i915, | |
112 | XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), | |
113 | XELPDP_PORT_P2M_RESPONSE_READY, | |
114 | XELPDP_PORT_P2M_RESPONSE_READY, | |
115 | XELPDP_MSGBUS_TIMEOUT_FAST_US, | |
116 | XELPDP_MSGBUS_TIMEOUT_SLOW, val)) { | |
117 | drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", | |
118 | phy_name(phy), *val); | |
d4b62a1a | 119 | intel_cx0_bus_reset(i915, port, lane); |
51390cc0 RS |
120 | return -ETIMEDOUT; |
121 | } | |
122 | ||
123 | if (*val & XELPDP_PORT_P2M_ERROR_SET) { | |
124 | drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), | |
125 | command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val); | |
126 | intel_cx0_bus_reset(i915, port, lane); | |
127 | return -EINVAL; | |
128 | } | |
129 | ||
130 | if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) { | |
131 | drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), | |
132 | command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val); | |
133 | intel_cx0_bus_reset(i915, port, lane); | |
134 | return -EINVAL; | |
135 | } | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port, | |
141 | int lane, u16 addr) | |
142 | { | |
143 | enum phy phy = intel_port_to_phy(i915, port); | |
144 | int ack; | |
145 | u32 val; | |
146 | ||
147 | if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
148 | XELPDP_PORT_M2P_TRANSACTION_PENDING, | |
149 | XELPDP_MSGBUS_TIMEOUT_SLOW)) { | |
150 | drm_dbg_kms(&i915->drm, | |
151 | "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy)); | |
152 | intel_cx0_bus_reset(i915, port, lane); | |
153 | return -ETIMEDOUT; | |
154 | } | |
155 | ||
156 | intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
157 | XELPDP_PORT_M2P_TRANSACTION_PENDING | | |
158 | XELPDP_PORT_M2P_COMMAND_READ | | |
159 | XELPDP_PORT_M2P_ADDRESS(addr)); | |
160 | ||
161 | ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val); | |
d4b62a1a | 162 | if (ack < 0) |
51390cc0 | 163 | return ack; |
51390cc0 RS |
164 | |
165 | intel_clear_response_ready_flag(i915, port, lane); | |
166 | ||
167 | return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val); | |
168 | } | |
169 | ||
170 | static u8 __intel_cx0_read(struct drm_i915_private *i915, enum port port, | |
171 | int lane, u16 addr) | |
172 | { | |
173 | enum phy phy = intel_port_to_phy(i915, port); | |
174 | int i, status; | |
175 | ||
176 | assert_dc_off(i915); | |
177 | ||
178 | /* 3 tries is assumed to be enough to read successfully */ | |
179 | for (i = 0; i < 3; i++) { | |
180 | status = __intel_cx0_read_once(i915, port, lane, addr); | |
181 | ||
182 | if (status >= 0) | |
183 | return status; | |
184 | } | |
185 | ||
186 | drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", | |
187 | phy_name(phy), addr, i); | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
192 | static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port, | |
193 | u8 lane_mask, u16 addr) | |
194 | { | |
195 | int lane = lane_mask_to_lane(lane_mask); | |
196 | ||
197 | return __intel_cx0_read(i915, port, lane, addr); | |
198 | } | |
199 | ||
200 | static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port, | |
201 | int lane, u16 addr, u8 data, bool committed) | |
202 | { | |
203 | enum phy phy = intel_port_to_phy(i915, port); | |
d4b62a1a | 204 | int ack; |
51390cc0 RS |
205 | u32 val; |
206 | ||
207 | if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
208 | XELPDP_PORT_M2P_TRANSACTION_PENDING, | |
209 | XELPDP_MSGBUS_TIMEOUT_SLOW)) { | |
210 | drm_dbg_kms(&i915->drm, | |
211 | "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy)); | |
212 | intel_cx0_bus_reset(i915, port, lane); | |
213 | return -ETIMEDOUT; | |
214 | } | |
215 | ||
216 | intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
217 | XELPDP_PORT_M2P_TRANSACTION_PENDING | | |
218 | (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED : | |
219 | XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) | | |
220 | XELPDP_PORT_M2P_DATA(data) | | |
221 | XELPDP_PORT_M2P_ADDRESS(addr)); | |
222 | ||
223 | if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
224 | XELPDP_PORT_M2P_TRANSACTION_PENDING, | |
225 | XELPDP_MSGBUS_TIMEOUT_SLOW)) { | |
226 | drm_dbg_kms(&i915->drm, | |
227 | "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy)); | |
228 | intel_cx0_bus_reset(i915, port, lane); | |
229 | return -ETIMEDOUT; | |
230 | } | |
231 | ||
232 | if (committed) { | |
d4b62a1a MK |
233 | ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val); |
234 | if (ack < 0) | |
235 | return ack; | |
51390cc0 RS |
236 | } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) & |
237 | XELPDP_PORT_P2M_ERROR_SET)) { | |
238 | drm_dbg_kms(&i915->drm, | |
239 | "PHY %c Error occurred during write command.\n", phy_name(phy)); | |
240 | intel_cx0_bus_reset(i915, port, lane); | |
241 | return -EINVAL; | |
242 | } | |
243 | ||
244 | intel_clear_response_ready_flag(i915, port, lane); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static void __intel_cx0_write(struct drm_i915_private *i915, enum port port, | |
250 | int lane, u16 addr, u8 data, bool committed) | |
251 | { | |
252 | enum phy phy = intel_port_to_phy(i915, port); | |
253 | int i, status; | |
254 | ||
255 | assert_dc_off(i915); | |
256 | ||
257 | /* 3 tries is assumed to be enough to write successfully */ | |
258 | for (i = 0; i < 3; i++) { | |
259 | status = __intel_cx0_write_once(i915, port, lane, addr, data, committed); | |
260 | ||
261 | if (status == 0) | |
262 | return; | |
263 | } | |
264 | ||
265 | drm_err_once(&i915->drm, | |
266 | "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i); | |
267 | } | |
268 | ||
269 | static void intel_cx0_write(struct drm_i915_private *i915, enum port port, | |
270 | u8 lane_mask, u16 addr, u8 data, bool committed) | |
271 | { | |
272 | int lane; | |
273 | ||
274 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
275 | __intel_cx0_write(i915, port, lane, addr, data, committed); | |
276 | } | |
277 | ||
62618c7f MK |
278 | static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port, |
279 | int lane, u16 addr, u16 data) | |
280 | { | |
281 | assert_dc_off(i915); | |
282 | ||
283 | intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); | |
284 | intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); | |
285 | ||
286 | intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0); | |
287 | intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); | |
288 | } | |
289 | ||
929f527a MK |
290 | static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port port, |
291 | int lane, u16 addr) | |
292 | { | |
293 | u16 val; | |
294 | ||
295 | assert_dc_off(i915); | |
296 | ||
297 | intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); | |
298 | intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); | |
299 | ||
300 | val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H); | |
301 | val <<= 8; | |
302 | val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L); | |
303 | ||
304 | return val; | |
305 | } | |
306 | ||
51390cc0 RS |
307 | static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port, |
308 | int lane, u16 addr, u8 clear, u8 set, bool committed) | |
309 | { | |
310 | u8 old, val; | |
311 | ||
312 | old = __intel_cx0_read(i915, port, lane, addr); | |
313 | val = (old & ~clear) | set; | |
314 | ||
315 | if (val != old) | |
316 | __intel_cx0_write(i915, port, lane, addr, val, committed); | |
317 | } | |
318 | ||
319 | static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port, | |
320 | u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed) | |
321 | { | |
322 | u8 lane; | |
323 | ||
324 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
325 | __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed); | |
326 | } | |
327 | ||
ea8af87a MK |
328 | static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state) |
329 | { | |
330 | if (intel_crtc_has_dp_encoder(crtc_state)) { | |
331 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && | |
332 | (crtc_state->port_clock == 540000 || | |
333 | crtc_state->port_clock == 810000)) | |
334 | return 5; | |
335 | else | |
336 | return 4; | |
337 | } else { | |
338 | return 5; | |
339 | } | |
340 | } | |
341 | ||
342 | static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state) | |
343 | { | |
344 | if (intel_crtc_has_dp_encoder(crtc_state)) { | |
345 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && | |
346 | (crtc_state->port_clock == 540000 || | |
347 | crtc_state->port_clock == 810000)) | |
348 | return 5; | |
349 | else | |
350 | return 2; | |
351 | } else { | |
352 | return 6; | |
353 | } | |
354 | } | |
355 | ||
356 | void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, | |
357 | const struct intel_crtc_state *crtc_state) | |
358 | { | |
359 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
360 | const struct intel_ddi_buf_trans *trans; | |
361 | enum phy phy = intel_port_to_phy(i915, encoder->port); | |
362 | intel_wakeref_t wakeref; | |
363 | int n_entries, ln; | |
364 | ||
365 | wakeref = intel_cx0_phy_transaction_begin(encoder); | |
366 | ||
367 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); | |
368 | if (drm_WARN_ON_ONCE(&i915->drm, !trans)) { | |
369 | intel_cx0_phy_transaction_end(encoder, wakeref); | |
370 | return; | |
371 | } | |
372 | ||
373 | if (intel_is_c10phy(i915, phy)) { | |
374 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), | |
375 | 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); | |
376 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3), | |
377 | C10_CMN3_TXVBOOST_MASK, | |
378 | C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)), | |
379 | MB_WRITE_UNCOMMITTED); | |
380 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1), | |
381 | C10_TX1_TERMCTL_MASK, | |
382 | C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)), | |
383 | MB_WRITE_COMMITTED); | |
384 | } | |
385 | ||
386 | for (ln = 0; ln < crtc_state->lane_count; ln++) { | |
387 | int level = intel_ddi_level(encoder, crtc_state, ln); | |
388 | int lane, tx; | |
389 | ||
390 | lane = ln / 2; | |
391 | tx = ln % 2; | |
392 | ||
393 | intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0), | |
394 | C10_PHY_OVRD_LEVEL_MASK, | |
395 | C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), | |
396 | MB_WRITE_COMMITTED); | |
397 | intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1), | |
398 | C10_PHY_OVRD_LEVEL_MASK, | |
399 | C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), | |
400 | MB_WRITE_COMMITTED); | |
401 | intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2), | |
402 | C10_PHY_OVRD_LEVEL_MASK, | |
403 | C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), | |
404 | MB_WRITE_COMMITTED); | |
405 | } | |
406 | ||
407 | /* Write Override enables in 0xD71 */ | |
408 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD, | |
409 | 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, | |
410 | MB_WRITE_COMMITTED); | |
411 | ||
412 | if (intel_is_c10phy(i915, phy)) | |
413 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), | |
414 | 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); | |
415 | ||
416 | intel_cx0_phy_transaction_end(encoder, wakeref); | |
417 | } | |
418 | ||
51390cc0 RS |
419 | /* |
420 | * Basic DP link rates with 38.4 MHz reference clock. | |
421 | * Note: The tables below are with SSC. In non-ssc | |
422 | * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be | |
423 | * programmed 0. | |
424 | */ | |
425 | ||
426 | static const struct intel_c10pll_state mtl_c10_dp_rbr = { | |
427 | .clock = 162000, | |
428 | .tx = 0x10, | |
429 | .cmn = 0x21, | |
430 | .pll[0] = 0xB4, | |
431 | .pll[1] = 0, | |
432 | .pll[2] = 0x30, | |
433 | .pll[3] = 0x1, | |
434 | .pll[4] = 0x26, | |
435 | .pll[5] = 0x0C, | |
436 | .pll[6] = 0x98, | |
437 | .pll[7] = 0x46, | |
438 | .pll[8] = 0x1, | |
439 | .pll[9] = 0x1, | |
440 | .pll[10] = 0, | |
441 | .pll[11] = 0, | |
442 | .pll[12] = 0xC0, | |
443 | .pll[13] = 0, | |
444 | .pll[14] = 0, | |
445 | .pll[15] = 0x2, | |
446 | .pll[16] = 0x84, | |
447 | .pll[17] = 0x4F, | |
448 | .pll[18] = 0xE5, | |
449 | .pll[19] = 0x23, | |
450 | }; | |
451 | ||
452 | static const struct intel_c10pll_state mtl_c10_edp_r216 = { | |
453 | .clock = 216000, | |
454 | .tx = 0x10, | |
455 | .cmn = 0x21, | |
456 | .pll[0] = 0x4, | |
457 | .pll[1] = 0, | |
458 | .pll[2] = 0xA2, | |
459 | .pll[3] = 0x1, | |
460 | .pll[4] = 0x33, | |
461 | .pll[5] = 0x10, | |
462 | .pll[6] = 0x75, | |
463 | .pll[7] = 0xB3, | |
464 | .pll[8] = 0x1, | |
465 | .pll[9] = 0x1, | |
466 | .pll[10] = 0, | |
467 | .pll[11] = 0, | |
468 | .pll[12] = 0, | |
469 | .pll[13] = 0, | |
470 | .pll[14] = 0, | |
471 | .pll[15] = 0x2, | |
472 | .pll[16] = 0x85, | |
473 | .pll[17] = 0x0F, | |
474 | .pll[18] = 0xE6, | |
475 | .pll[19] = 0x23, | |
476 | }; | |
477 | ||
478 | static const struct intel_c10pll_state mtl_c10_edp_r243 = { | |
479 | .clock = 243000, | |
480 | .tx = 0x10, | |
481 | .cmn = 0x21, | |
482 | .pll[0] = 0x34, | |
483 | .pll[1] = 0, | |
484 | .pll[2] = 0xDA, | |
485 | .pll[3] = 0x1, | |
486 | .pll[4] = 0x39, | |
487 | .pll[5] = 0x12, | |
488 | .pll[6] = 0xE3, | |
489 | .pll[7] = 0xE9, | |
490 | .pll[8] = 0x1, | |
491 | .pll[9] = 0x1, | |
492 | .pll[10] = 0, | |
493 | .pll[11] = 0, | |
494 | .pll[12] = 0x20, | |
495 | .pll[13] = 0, | |
496 | .pll[14] = 0, | |
497 | .pll[15] = 0x2, | |
498 | .pll[16] = 0x85, | |
499 | .pll[17] = 0x8F, | |
500 | .pll[18] = 0xE6, | |
501 | .pll[19] = 0x23, | |
502 | }; | |
503 | ||
504 | static const struct intel_c10pll_state mtl_c10_dp_hbr1 = { | |
505 | .clock = 270000, | |
506 | .tx = 0x10, | |
507 | .cmn = 0x21, | |
508 | .pll[0] = 0xF4, | |
509 | .pll[1] = 0, | |
510 | .pll[2] = 0xF8, | |
511 | .pll[3] = 0x0, | |
512 | .pll[4] = 0x20, | |
513 | .pll[5] = 0x0A, | |
514 | .pll[6] = 0x29, | |
515 | .pll[7] = 0x10, | |
516 | .pll[8] = 0x1, /* Verify */ | |
517 | .pll[9] = 0x1, | |
518 | .pll[10] = 0, | |
519 | .pll[11] = 0, | |
520 | .pll[12] = 0xA0, | |
521 | .pll[13] = 0, | |
522 | .pll[14] = 0, | |
523 | .pll[15] = 0x1, | |
524 | .pll[16] = 0x84, | |
525 | .pll[17] = 0x4F, | |
526 | .pll[18] = 0xE5, | |
527 | .pll[19] = 0x23, | |
528 | }; | |
529 | ||
530 | static const struct intel_c10pll_state mtl_c10_edp_r324 = { | |
531 | .clock = 324000, | |
532 | .tx = 0x10, | |
533 | .cmn = 0x21, | |
534 | .pll[0] = 0xB4, | |
535 | .pll[1] = 0, | |
536 | .pll[2] = 0x30, | |
537 | .pll[3] = 0x1, | |
538 | .pll[4] = 0x26, | |
539 | .pll[5] = 0x0C, | |
540 | .pll[6] = 0x98, | |
541 | .pll[7] = 0x46, | |
542 | .pll[8] = 0x1, | |
543 | .pll[9] = 0x1, | |
544 | .pll[10] = 0, | |
545 | .pll[11] = 0, | |
546 | .pll[12] = 0xC0, | |
547 | .pll[13] = 0, | |
548 | .pll[14] = 0, | |
549 | .pll[15] = 0x1, | |
550 | .pll[16] = 0x85, | |
551 | .pll[17] = 0x4F, | |
552 | .pll[18] = 0xE6, | |
553 | .pll[19] = 0x23, | |
554 | }; | |
555 | ||
556 | static const struct intel_c10pll_state mtl_c10_edp_r432 = { | |
557 | .clock = 432000, | |
558 | .tx = 0x10, | |
559 | .cmn = 0x21, | |
560 | .pll[0] = 0x4, | |
561 | .pll[1] = 0, | |
562 | .pll[2] = 0xA2, | |
563 | .pll[3] = 0x1, | |
564 | .pll[4] = 0x33, | |
565 | .pll[5] = 0x10, | |
566 | .pll[6] = 0x75, | |
567 | .pll[7] = 0xB3, | |
568 | .pll[8] = 0x1, | |
569 | .pll[9] = 0x1, | |
570 | .pll[10] = 0, | |
571 | .pll[11] = 0, | |
572 | .pll[12] = 0, | |
573 | .pll[13] = 0, | |
574 | .pll[14] = 0, | |
575 | .pll[15] = 0x1, | |
576 | .pll[16] = 0x85, | |
577 | .pll[17] = 0x0F, | |
578 | .pll[18] = 0xE6, | |
579 | .pll[19] = 0x23, | |
580 | }; | |
581 | ||
582 | static const struct intel_c10pll_state mtl_c10_dp_hbr2 = { | |
583 | .clock = 540000, | |
584 | .tx = 0x10, | |
585 | .cmn = 0x21, | |
586 | .pll[0] = 0xF4, | |
587 | .pll[1] = 0, | |
588 | .pll[2] = 0xF8, | |
589 | .pll[3] = 0, | |
590 | .pll[4] = 0x20, | |
591 | .pll[5] = 0x0A, | |
592 | .pll[6] = 0x29, | |
593 | .pll[7] = 0x10, | |
594 | .pll[8] = 0x1, | |
595 | .pll[9] = 0x1, | |
596 | .pll[10] = 0, | |
597 | .pll[11] = 0, | |
598 | .pll[12] = 0xA0, | |
599 | .pll[13] = 0, | |
600 | .pll[14] = 0, | |
601 | .pll[15] = 0, | |
602 | .pll[16] = 0x84, | |
603 | .pll[17] = 0x4F, | |
604 | .pll[18] = 0xE5, | |
605 | .pll[19] = 0x23, | |
606 | }; | |
607 | ||
608 | static const struct intel_c10pll_state mtl_c10_edp_r675 = { | |
609 | .clock = 675000, | |
610 | .tx = 0x10, | |
611 | .cmn = 0x21, | |
612 | .pll[0] = 0xB4, | |
613 | .pll[1] = 0, | |
614 | .pll[2] = 0x3E, | |
615 | .pll[3] = 0x1, | |
616 | .pll[4] = 0xA8, | |
617 | .pll[5] = 0x0C, | |
618 | .pll[6] = 0x33, | |
619 | .pll[7] = 0x54, | |
620 | .pll[8] = 0x1, | |
621 | .pll[9] = 0x1, | |
622 | .pll[10] = 0, | |
623 | .pll[11] = 0, | |
624 | .pll[12] = 0xC8, | |
625 | .pll[13] = 0, | |
626 | .pll[14] = 0, | |
627 | .pll[15] = 0, | |
628 | .pll[16] = 0x85, | |
629 | .pll[17] = 0x8F, | |
630 | .pll[18] = 0xE6, | |
631 | .pll[19] = 0x23, | |
632 | }; | |
633 | ||
634 | static const struct intel_c10pll_state mtl_c10_dp_hbr3 = { | |
635 | .clock = 810000, | |
636 | .tx = 0x10, | |
637 | .cmn = 0x21, | |
638 | .pll[0] = 0x34, | |
639 | .pll[1] = 0, | |
640 | .pll[2] = 0x84, | |
641 | .pll[3] = 0x1, | |
642 | .pll[4] = 0x30, | |
643 | .pll[5] = 0x0F, | |
644 | .pll[6] = 0x3D, | |
645 | .pll[7] = 0x98, | |
646 | .pll[8] = 0x1, | |
647 | .pll[9] = 0x1, | |
648 | .pll[10] = 0, | |
649 | .pll[11] = 0, | |
650 | .pll[12] = 0xF0, | |
651 | .pll[13] = 0, | |
652 | .pll[14] = 0, | |
653 | .pll[15] = 0, | |
654 | .pll[16] = 0x84, | |
655 | .pll[17] = 0x0F, | |
656 | .pll[18] = 0xE5, | |
657 | .pll[19] = 0x23, | |
658 | }; | |
659 | ||
660 | static const struct intel_c10pll_state * const mtl_c10_dp_tables[] = { | |
661 | &mtl_c10_dp_rbr, | |
662 | &mtl_c10_dp_hbr1, | |
663 | &mtl_c10_dp_hbr2, | |
664 | &mtl_c10_dp_hbr3, | |
665 | NULL, | |
666 | }; | |
667 | ||
668 | static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = { | |
669 | &mtl_c10_dp_rbr, | |
670 | &mtl_c10_edp_r216, | |
671 | &mtl_c10_edp_r243, | |
672 | &mtl_c10_dp_hbr1, | |
673 | &mtl_c10_edp_r324, | |
674 | &mtl_c10_edp_r432, | |
675 | &mtl_c10_dp_hbr2, | |
676 | &mtl_c10_edp_r675, | |
677 | &mtl_c10_dp_hbr3, | |
678 | NULL, | |
679 | }; | |
680 | ||
929f527a MK |
681 | /* C20 basic DP 1.4 tables */ |
682 | static const struct intel_c20pll_state mtl_c20_dp_rbr = { | |
683 | .link_bit_rate = 162000, | |
684 | .clock = 162000, | |
685 | .tx = { 0xbe88, /* tx cfg0 */ | |
686 | 0x5800, /* tx cfg1 */ | |
687 | 0x0000, /* tx cfg2 */ | |
688 | }, | |
689 | .cmn = {0x0500, /* cmn cfg0*/ | |
690 | 0x0005, /* cmn cfg1 */ | |
691 | 0x0000, /* cmn cfg2 */ | |
692 | 0x0000, /* cmn cfg3 */ | |
693 | }, | |
694 | .mpllb = { 0x50a8, /* mpllb cfg0 */ | |
695 | 0x2120, /* mpllb cfg1 */ | |
696 | 0xcd9a, /* mpllb cfg2 */ | |
697 | 0xbfc1, /* mpllb cfg3 */ | |
698 | 0x5ab8, /* mpllb cfg4 */ | |
699 | 0x4c34, /* mpllb cfg5 */ | |
700 | 0x2000, /* mpllb cfg6 */ | |
701 | 0x0001, /* mpllb cfg7 */ | |
702 | 0x6000, /* mpllb cfg8 */ | |
703 | 0x0000, /* mpllb cfg9 */ | |
704 | 0x0000, /* mpllb cfg10 */ | |
705 | }, | |
706 | }; | |
707 | ||
708 | static const struct intel_c20pll_state mtl_c20_dp_hbr1 = { | |
709 | .link_bit_rate = 270000, | |
710 | .clock = 270000, | |
711 | .tx = { 0xbe88, /* tx cfg0 */ | |
712 | 0x4800, /* tx cfg1 */ | |
713 | 0x0000, /* tx cfg2 */ | |
714 | }, | |
715 | .cmn = {0x0500, /* cmn cfg0*/ | |
716 | 0x0005, /* cmn cfg1 */ | |
717 | 0x0000, /* cmn cfg2 */ | |
718 | 0x0000, /* cmn cfg3 */ | |
719 | }, | |
720 | .mpllb = { 0x308c, /* mpllb cfg0 */ | |
721 | 0x2110, /* mpllb cfg1 */ | |
722 | 0xcc9c, /* mpllb cfg2 */ | |
723 | 0xbfc1, /* mpllb cfg3 */ | |
724 | 0x4b9a, /* mpllb cfg4 */ | |
725 | 0x3f81, /* mpllb cfg5 */ | |
726 | 0x2000, /* mpllb cfg6 */ | |
727 | 0x0001, /* mpllb cfg7 */ | |
728 | 0x5000, /* mpllb cfg8 */ | |
729 | 0x0000, /* mpllb cfg9 */ | |
730 | 0x0000, /* mpllb cfg10 */ | |
731 | }, | |
732 | }; | |
733 | ||
734 | static const struct intel_c20pll_state mtl_c20_dp_hbr2 = { | |
735 | .link_bit_rate = 540000, | |
736 | .clock = 540000, | |
737 | .tx = { 0xbe88, /* tx cfg0 */ | |
738 | 0x4800, /* tx cfg1 */ | |
739 | 0x0000, /* tx cfg2 */ | |
740 | }, | |
741 | .cmn = {0x0500, /* cmn cfg0*/ | |
742 | 0x0005, /* cmn cfg1 */ | |
743 | 0x0000, /* cmn cfg2 */ | |
744 | 0x0000, /* cmn cfg3 */ | |
745 | }, | |
746 | .mpllb = { 0x108c, /* mpllb cfg0 */ | |
747 | 0x2108, /* mpllb cfg1 */ | |
748 | 0xcc9c, /* mpllb cfg2 */ | |
749 | 0xbfc1, /* mpllb cfg3 */ | |
750 | 0x4b9a, /* mpllb cfg4 */ | |
751 | 0x3f81, /* mpllb cfg5 */ | |
752 | 0x2000, /* mpllb cfg6 */ | |
753 | 0x0001, /* mpllb cfg7 */ | |
754 | 0x5000, /* mpllb cfg8 */ | |
755 | 0x0000, /* mpllb cfg9 */ | |
756 | 0x0000, /* mpllb cfg10 */ | |
757 | }, | |
758 | }; | |
759 | ||
760 | static const struct intel_c20pll_state mtl_c20_dp_hbr3 = { | |
761 | .link_bit_rate = 810000, | |
762 | .clock = 810000, | |
763 | .tx = { 0xbe88, /* tx cfg0 */ | |
764 | 0x4800, /* tx cfg1 */ | |
765 | 0x0000, /* tx cfg2 */ | |
766 | }, | |
767 | .cmn = {0x0500, /* cmn cfg0*/ | |
768 | 0x0005, /* cmn cfg1 */ | |
769 | 0x0000, /* cmn cfg2 */ | |
770 | 0x0000, /* cmn cfg3 */ | |
771 | }, | |
772 | .mpllb = { 0x10d2, /* mpllb cfg0 */ | |
773 | 0x2108, /* mpllb cfg1 */ | |
774 | 0x8d98, /* mpllb cfg2 */ | |
775 | 0xbfc1, /* mpllb cfg3 */ | |
776 | 0x7166, /* mpllb cfg4 */ | |
777 | 0x5f42, /* mpllb cfg5 */ | |
778 | 0x2000, /* mpllb cfg6 */ | |
779 | 0x0001, /* mpllb cfg7 */ | |
780 | 0x7800, /* mpllb cfg8 */ | |
781 | 0x0000, /* mpllb cfg9 */ | |
782 | 0x0000, /* mpllb cfg10 */ | |
783 | }, | |
784 | }; | |
785 | ||
786 | /* C20 basic DP 2.0 tables */ | |
787 | static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = { | |
788 | .link_bit_rate = 1000000, /* 10 Gbps */ | |
789 | .clock = 312500, | |
790 | .tx = { 0xbe21, /* tx cfg0 */ | |
791 | 0x4800, /* tx cfg1 */ | |
792 | 0x0000, /* tx cfg2 */ | |
793 | }, | |
794 | .cmn = {0x0500, /* cmn cfg0*/ | |
795 | 0x0005, /* cmn cfg1 */ | |
796 | 0x0000, /* cmn cfg2 */ | |
797 | 0x0000, /* cmn cfg3 */ | |
798 | }, | |
799 | .mplla = { 0x3104, /* mplla cfg0 */ | |
800 | 0xd105, /* mplla cfg1 */ | |
801 | 0xc025, /* mplla cfg2 */ | |
802 | 0xc025, /* mplla cfg3 */ | |
803 | 0x8c00, /* mplla cfg4 */ | |
804 | 0x759a, /* mplla cfg5 */ | |
805 | 0x4000, /* mplla cfg6 */ | |
806 | 0x0003, /* mplla cfg7 */ | |
807 | 0x3555, /* mplla cfg8 */ | |
808 | 0x0001, /* mplla cfg9 */ | |
809 | }, | |
810 | }; | |
811 | ||
812 | static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = { | |
813 | .link_bit_rate = 1350000, /* 13.5 Gbps */ | |
814 | .clock = 421875, | |
815 | .tx = { 0xbea0, /* tx cfg0 */ | |
816 | 0x4800, /* tx cfg1 */ | |
817 | 0x0000, /* tx cfg2 */ | |
818 | }, | |
819 | .cmn = {0x0500, /* cmn cfg0*/ | |
820 | 0x0005, /* cmn cfg1 */ | |
821 | 0x0000, /* cmn cfg2 */ | |
822 | 0x0000, /* cmn cfg3 */ | |
823 | }, | |
824 | .mpllb = { 0x015f, /* mpllb cfg0 */ | |
825 | 0x2205, /* mpllb cfg1 */ | |
826 | 0x1b17, /* mpllb cfg2 */ | |
827 | 0xffc1, /* mpllb cfg3 */ | |
828 | 0xe100, /* mpllb cfg4 */ | |
829 | 0xbd00, /* mpllb cfg5 */ | |
830 | 0x2000, /* mpllb cfg6 */ | |
831 | 0x0001, /* mpllb cfg7 */ | |
832 | 0x4800, /* mpllb cfg8 */ | |
833 | 0x0000, /* mpllb cfg9 */ | |
834 | 0x0000, /* mpllb cfg10 */ | |
835 | }, | |
836 | }; | |
837 | ||
838 | static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = { | |
839 | .link_bit_rate = 2000000, /* 20 Gbps */ | |
840 | .clock = 625000, | |
841 | .tx = { 0xbe20, /* tx cfg0 */ | |
842 | 0x4800, /* tx cfg1 */ | |
843 | 0x0000, /* tx cfg2 */ | |
844 | }, | |
845 | .cmn = {0x0500, /* cmn cfg0*/ | |
846 | 0x0005, /* cmn cfg1 */ | |
847 | 0x0000, /* cmn cfg2 */ | |
848 | 0x0000, /* cmn cfg3 */ | |
849 | }, | |
850 | .mplla = { 0x3104, /* mplla cfg0 */ | |
851 | 0xd105, /* mplla cfg1 */ | |
852 | 0xc025, /* mplla cfg2 */ | |
853 | 0xc025, /* mplla cfg3 */ | |
854 | 0xa6ab, /* mplla cfg4 */ | |
855 | 0x8c00, /* mplla cfg5 */ | |
856 | 0x4000, /* mplla cfg6 */ | |
857 | 0x0003, /* mplla cfg7 */ | |
858 | 0x3555, /* mplla cfg8 */ | |
859 | 0x0001, /* mplla cfg9 */ | |
860 | }, | |
861 | }; | |
862 | ||
863 | static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = { | |
864 | &mtl_c20_dp_rbr, | |
865 | &mtl_c20_dp_hbr1, | |
866 | &mtl_c20_dp_hbr2, | |
867 | &mtl_c20_dp_hbr3, | |
868 | &mtl_c20_dp_uhbr10, | |
869 | &mtl_c20_dp_uhbr13_5, | |
870 | &mtl_c20_dp_uhbr20, | |
871 | NULL, | |
872 | }; | |
873 | ||
5836bc5f RS |
874 | /* |
875 | * HDMI link rates with 38.4 MHz reference clock. | |
876 | */ | |
877 | ||
878 | static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = { | |
879 | .clock = 25200, | |
880 | .tx = 0x10, | |
881 | .cmn = 0x1, | |
882 | .pll[0] = 0x4, | |
883 | .pll[1] = 0, | |
884 | .pll[2] = 0xB2, | |
885 | .pll[3] = 0, | |
886 | .pll[4] = 0, | |
887 | .pll[5] = 0, | |
888 | .pll[6] = 0, | |
889 | .pll[7] = 0, | |
890 | .pll[8] = 0x20, | |
891 | .pll[9] = 0x1, | |
892 | .pll[10] = 0, | |
893 | .pll[11] = 0, | |
894 | .pll[12] = 0, | |
895 | .pll[13] = 0, | |
896 | .pll[14] = 0, | |
897 | .pll[15] = 0xD, | |
898 | .pll[16] = 0x6, | |
899 | .pll[17] = 0x8F, | |
900 | .pll[18] = 0x84, | |
901 | .pll[19] = 0x23, | |
902 | }; | |
903 | ||
904 | static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = { | |
905 | .clock = 27000, | |
906 | .tx = 0x10, | |
907 | .cmn = 0x1, | |
908 | .pll[0] = 0x34, | |
909 | .pll[1] = 0, | |
910 | .pll[2] = 0xC0, | |
911 | .pll[3] = 0, | |
912 | .pll[4] = 0, | |
913 | .pll[5] = 0, | |
914 | .pll[6] = 0, | |
915 | .pll[7] = 0, | |
916 | .pll[8] = 0x20, | |
917 | .pll[9] = 0x1, | |
918 | .pll[10] = 0, | |
919 | .pll[11] = 0, | |
920 | .pll[12] = 0x80, | |
921 | .pll[13] = 0, | |
922 | .pll[14] = 0, | |
923 | .pll[15] = 0xD, | |
924 | .pll[16] = 0x6, | |
925 | .pll[17] = 0xCF, | |
926 | .pll[18] = 0x84, | |
927 | .pll[19] = 0x23, | |
928 | }; | |
929 | ||
930 | static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = { | |
931 | .clock = 74250, | |
932 | .tx = 0x10, | |
933 | .cmn = 0x1, | |
934 | .pll[0] = 0xF4, | |
935 | .pll[1] = 0, | |
936 | .pll[2] = 0x7A, | |
937 | .pll[3] = 0, | |
938 | .pll[4] = 0, | |
939 | .pll[5] = 0, | |
940 | .pll[6] = 0, | |
941 | .pll[7] = 0, | |
942 | .pll[8] = 0x20, | |
943 | .pll[9] = 0x1, | |
944 | .pll[10] = 0, | |
945 | .pll[11] = 0, | |
946 | .pll[12] = 0x58, | |
947 | .pll[13] = 0, | |
948 | .pll[14] = 0, | |
949 | .pll[15] = 0xB, | |
950 | .pll[16] = 0x6, | |
951 | .pll[17] = 0xF, | |
952 | .pll[18] = 0x85, | |
953 | .pll[19] = 0x23, | |
954 | }; | |
955 | ||
956 | static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = { | |
957 | .clock = 148500, | |
958 | .tx = 0x10, | |
959 | .cmn = 0x1, | |
960 | .pll[0] = 0xF4, | |
961 | .pll[1] = 0, | |
962 | .pll[2] = 0x7A, | |
963 | .pll[3] = 0, | |
964 | .pll[4] = 0, | |
965 | .pll[5] = 0, | |
966 | .pll[6] = 0, | |
967 | .pll[7] = 0, | |
968 | .pll[8] = 0x20, | |
969 | .pll[9] = 0x1, | |
970 | .pll[10] = 0, | |
971 | .pll[11] = 0, | |
972 | .pll[12] = 0x58, | |
973 | .pll[13] = 0, | |
974 | .pll[14] = 0, | |
975 | .pll[15] = 0xA, | |
976 | .pll[16] = 0x6, | |
977 | .pll[17] = 0xF, | |
978 | .pll[18] = 0x85, | |
979 | .pll[19] = 0x23, | |
980 | }; | |
981 | ||
982 | static const struct intel_c10pll_state mtl_c10_hdmi_594 = { | |
983 | .clock = 594000, | |
984 | .tx = 0x10, | |
985 | .cmn = 0x1, | |
986 | .pll[0] = 0xF4, | |
987 | .pll[1] = 0, | |
988 | .pll[2] = 0x7A, | |
989 | .pll[3] = 0, | |
990 | .pll[4] = 0, | |
991 | .pll[5] = 0, | |
992 | .pll[6] = 0, | |
993 | .pll[7] = 0, | |
994 | .pll[8] = 0x20, | |
995 | .pll[9] = 0x1, | |
996 | .pll[10] = 0, | |
997 | .pll[11] = 0, | |
998 | .pll[12] = 0x58, | |
999 | .pll[13] = 0, | |
1000 | .pll[14] = 0, | |
1001 | .pll[15] = 0x8, | |
1002 | .pll[16] = 0x6, | |
1003 | .pll[17] = 0xF, | |
1004 | .pll[18] = 0x85, | |
1005 | .pll[19] = 0x23, | |
1006 | }; | |
1007 | ||
1008 | /* Precomputed C10 HDMI PLL tables */ | |
1009 | static const struct intel_c10pll_state mtl_c10_hdmi_27027 = { | |
1010 | .clock = 27027, | |
1011 | .tx = 0x10, | |
1012 | .cmn = 0x1, | |
1013 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00, | |
1014 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1015 | .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC, | |
1016 | .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1017 | }; | |
1018 | ||
1019 | static const struct intel_c10pll_state mtl_c10_hdmi_28320 = { | |
1020 | .clock = 28320, | |
1021 | .tx = 0x10, | |
1022 | .cmn = 0x1, | |
1023 | .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00, | |
1024 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1025 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, | |
1026 | .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1027 | }; | |
1028 | ||
1029 | static const struct intel_c10pll_state mtl_c10_hdmi_30240 = { | |
1030 | .clock = 30240, | |
1031 | .tx = 0x10, | |
1032 | .cmn = 0x1, | |
1033 | .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00, | |
1034 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1035 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, | |
1036 | .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1037 | }; | |
1038 | ||
1039 | static const struct intel_c10pll_state mtl_c10_hdmi_31500 = { | |
1040 | .clock = 31500, | |
1041 | .tx = 0x10, | |
1042 | .cmn = 0x1, | |
1043 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00, | |
1044 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1045 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00, | |
1046 | .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1047 | }; | |
1048 | ||
1049 | static const struct intel_c10pll_state mtl_c10_hdmi_36000 = { | |
1050 | .clock = 36000, | |
1051 | .tx = 0x10, | |
1052 | .cmn = 0x1, | |
1053 | .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00, | |
1054 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1055 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00, | |
1056 | .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1057 | }; | |
1058 | ||
1059 | static const struct intel_c10pll_state mtl_c10_hdmi_40000 = { | |
1060 | .clock = 40000, | |
1061 | .tx = 0x10, | |
1062 | .cmn = 0x1, | |
1063 | .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00, | |
1064 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1065 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55, | |
1066 | .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1067 | }; | |
1068 | ||
1069 | static const struct intel_c10pll_state mtl_c10_hdmi_49500 = { | |
1070 | .clock = 49500, | |
1071 | .tx = 0x10, | |
1072 | .cmn = 0x1, | |
1073 | .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, | |
1074 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1075 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, | |
1076 | .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1077 | }; | |
1078 | ||
1079 | static const struct intel_c10pll_state mtl_c10_hdmi_50000 = { | |
1080 | .clock = 50000, | |
1081 | .tx = 0x10, | |
1082 | .cmn = 0x1, | |
1083 | .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00, | |
1084 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1085 | .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA, | |
1086 | .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1087 | }; | |
1088 | ||
1089 | static const struct intel_c10pll_state mtl_c10_hdmi_57284 = { | |
1090 | .clock = 57284, | |
1091 | .tx = 0x10, | |
1092 | .cmn = 0x1, | |
1093 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00, | |
1094 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1095 | .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77, | |
1096 | .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1097 | }; | |
1098 | ||
1099 | static const struct intel_c10pll_state mtl_c10_hdmi_58000 = { | |
1100 | .clock = 58000, | |
1101 | .tx = 0x10, | |
1102 | .cmn = 0x1, | |
1103 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00, | |
1104 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1105 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55, | |
1106 | .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1107 | }; | |
1108 | ||
1109 | static const struct intel_c10pll_state mtl_c10_hdmi_65000 = { | |
1110 | .clock = 65000, | |
1111 | .tx = 0x10, | |
1112 | .cmn = 0x1, | |
1113 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00, | |
1114 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1115 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55, | |
1116 | .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1117 | }; | |
1118 | ||
1119 | static const struct intel_c10pll_state mtl_c10_hdmi_71000 = { | |
1120 | .clock = 71000, | |
1121 | .tx = 0x10, | |
1122 | .cmn = 0x1, | |
1123 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00, | |
1124 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1125 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55, | |
1126 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1127 | }; | |
1128 | ||
1129 | static const struct intel_c10pll_state mtl_c10_hdmi_74176 = { | |
1130 | .clock = 74176, | |
1131 | .tx = 0x10, | |
1132 | .cmn = 0x1, | |
1133 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, | |
1134 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1135 | .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44, | |
1136 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1137 | }; | |
1138 | ||
1139 | static const struct intel_c10pll_state mtl_c10_hdmi_75000 = { | |
1140 | .clock = 75000, | |
1141 | .tx = 0x10, | |
1142 | .cmn = 0x1, | |
1143 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00, | |
1144 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1145 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, | |
1146 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1147 | }; | |
1148 | ||
1149 | static const struct intel_c10pll_state mtl_c10_hdmi_78750 = { | |
1150 | .clock = 78750, | |
1151 | .tx = 0x10, | |
1152 | .cmn = 0x1, | |
1153 | .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00, | |
1154 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1155 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00, | |
1156 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1157 | }; | |
1158 | ||
1159 | static const struct intel_c10pll_state mtl_c10_hdmi_85500 = { | |
1160 | .clock = 85500, | |
1161 | .tx = 0x10, | |
1162 | .cmn = 0x1, | |
1163 | .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00, | |
1164 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1165 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00, | |
1166 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1167 | }; | |
1168 | ||
1169 | static const struct intel_c10pll_state mtl_c10_hdmi_88750 = { | |
1170 | .clock = 88750, | |
1171 | .tx = 0x10, | |
1172 | .cmn = 0x1, | |
1173 | .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00, | |
1174 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1175 | .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA, | |
1176 | .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1177 | }; | |
1178 | ||
1179 | static const struct intel_c10pll_state mtl_c10_hdmi_106500 = { | |
1180 | .clock = 106500, | |
1181 | .tx = 0x10, | |
1182 | .cmn = 0x1, | |
1183 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00, | |
1184 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1185 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00, | |
1186 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1187 | }; | |
1188 | ||
1189 | static const struct intel_c10pll_state mtl_c10_hdmi_108000 = { | |
1190 | .clock = 108000, | |
1191 | .tx = 0x10, | |
1192 | .cmn = 0x1, | |
1193 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00, | |
1194 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1195 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00, | |
1196 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1197 | }; | |
1198 | ||
1199 | static const struct intel_c10pll_state mtl_c10_hdmi_115500 = { | |
1200 | .clock = 115500, | |
1201 | .tx = 0x10, | |
1202 | .cmn = 0x1, | |
1203 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00, | |
1204 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1205 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00, | |
1206 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1207 | }; | |
1208 | ||
1209 | static const struct intel_c10pll_state mtl_c10_hdmi_119000 = { | |
1210 | .clock = 119000, | |
1211 | .tx = 0x10, | |
1212 | .cmn = 0x1, | |
1213 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00, | |
1214 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1215 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55, | |
1216 | .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1217 | }; | |
1218 | ||
1219 | static const struct intel_c10pll_state mtl_c10_hdmi_135000 = { | |
1220 | .clock = 135000, | |
1221 | .tx = 0x10, | |
1222 | .cmn = 0x1, | |
1223 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00, | |
1224 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1225 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00, | |
1226 | .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1227 | }; | |
1228 | ||
1229 | static const struct intel_c10pll_state mtl_c10_hdmi_138500 = { | |
1230 | .clock = 138500, | |
1231 | .tx = 0x10, | |
1232 | .cmn = 0x1, | |
1233 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00, | |
1234 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1235 | .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA, | |
1236 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1237 | }; | |
1238 | ||
1239 | static const struct intel_c10pll_state mtl_c10_hdmi_147160 = { | |
1240 | .clock = 147160, | |
1241 | .tx = 0x10, | |
1242 | .cmn = 0x1, | |
1243 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00, | |
1244 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1245 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55, | |
1246 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1247 | }; | |
1248 | ||
1249 | static const struct intel_c10pll_state mtl_c10_hdmi_148352 = { | |
1250 | .clock = 148352, | |
1251 | .tx = 0x10, | |
1252 | .cmn = 0x1, | |
1253 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, | |
1254 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1255 | .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44, | |
1256 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1257 | }; | |
1258 | ||
1259 | static const struct intel_c10pll_state mtl_c10_hdmi_154000 = { | |
1260 | .clock = 154000, | |
1261 | .tx = 0x10, | |
1262 | .cmn = 0x1, | |
1263 | .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00, | |
1264 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1265 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55, | |
1266 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1267 | }; | |
1268 | ||
1269 | static const struct intel_c10pll_state mtl_c10_hdmi_162000 = { | |
1270 | .clock = 162000, | |
1271 | .tx = 0x10, | |
1272 | .cmn = 0x1, | |
1273 | .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00, | |
1274 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1275 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00, | |
1276 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1277 | }; | |
1278 | ||
1279 | static const struct intel_c10pll_state mtl_c10_hdmi_167000 = { | |
1280 | .clock = 167000, | |
1281 | .tx = 0x10, | |
1282 | .cmn = 0x1, | |
1283 | .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00, | |
1284 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1285 | .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA, | |
1286 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1287 | }; | |
1288 | ||
1289 | static const struct intel_c10pll_state mtl_c10_hdmi_197802 = { | |
1290 | .clock = 197802, | |
1291 | .tx = 0x10, | |
1292 | .cmn = 0x1, | |
1293 | .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, | |
1294 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1295 | .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99, | |
1296 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1297 | }; | |
1298 | ||
1299 | static const struct intel_c10pll_state mtl_c10_hdmi_198000 = { | |
1300 | .clock = 198000, | |
1301 | .tx = 0x10, | |
1302 | .cmn = 0x1, | |
1303 | .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00, | |
1304 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1305 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00, | |
1306 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1307 | }; | |
1308 | ||
1309 | static const struct intel_c10pll_state mtl_c10_hdmi_209800 = { | |
1310 | .clock = 209800, | |
1311 | .tx = 0x10, | |
1312 | .cmn = 0x1, | |
1313 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00, | |
1314 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1315 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55, | |
1316 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1317 | }; | |
1318 | ||
1319 | static const struct intel_c10pll_state mtl_c10_hdmi_241500 = { | |
1320 | .clock = 241500, | |
1321 | .tx = 0x10, | |
1322 | .cmn = 0x1, | |
1323 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00, | |
1324 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1325 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00, | |
1326 | .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1327 | }; | |
1328 | ||
1329 | static const struct intel_c10pll_state mtl_c10_hdmi_262750 = { | |
1330 | .clock = 262750, | |
1331 | .tx = 0x10, | |
1332 | .cmn = 0x1, | |
1333 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00, | |
1334 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1335 | .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA, | |
1336 | .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1337 | }; | |
1338 | ||
1339 | static const struct intel_c10pll_state mtl_c10_hdmi_268500 = { | |
1340 | .clock = 268500, | |
1341 | .tx = 0x10, | |
1342 | .cmn = 0x1, | |
1343 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00, | |
1344 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1345 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00, | |
1346 | .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1347 | }; | |
1348 | ||
1349 | static const struct intel_c10pll_state mtl_c10_hdmi_296703 = { | |
1350 | .clock = 296703, | |
1351 | .tx = 0x10, | |
1352 | .cmn = 0x1, | |
1353 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, | |
1354 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1355 | .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33, | |
1356 | .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1357 | }; | |
1358 | ||
1359 | static const struct intel_c10pll_state mtl_c10_hdmi_297000 = { | |
1360 | .clock = 297000, | |
1361 | .tx = 0x10, | |
1362 | .cmn = 0x1, | |
1363 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, | |
1364 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1365 | .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00, | |
1366 | .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1367 | }; | |
1368 | ||
1369 | static const struct intel_c10pll_state mtl_c10_hdmi_319750 = { | |
1370 | .clock = 319750, | |
1371 | .tx = 0x10, | |
1372 | .cmn = 0x1, | |
1373 | .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00, | |
1374 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1375 | .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA, | |
1376 | .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1377 | }; | |
1378 | ||
1379 | static const struct intel_c10pll_state mtl_c10_hdmi_497750 = { | |
1380 | .clock = 497750, | |
1381 | .tx = 0x10, | |
1382 | .cmn = 0x1, | |
1383 | .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00, | |
1384 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1385 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55, | |
1386 | .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23, | |
1387 | }; | |
1388 | ||
1389 | static const struct intel_c10pll_state mtl_c10_hdmi_592000 = { | |
1390 | .clock = 592000, | |
1391 | .tx = 0x10, | |
1392 | .cmn = 0x1, | |
1393 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, | |
1394 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1395 | .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55, | |
1396 | .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1397 | }; | |
1398 | ||
1399 | static const struct intel_c10pll_state mtl_c10_hdmi_593407 = { | |
1400 | .clock = 593407, | |
1401 | .tx = 0x10, | |
1402 | .cmn = 0x1, | |
1403 | .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00, | |
1404 | .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF, | |
1405 | .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB, | |
1406 | .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23, | |
1407 | }; | |
1408 | ||
1409 | static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = { | |
1410 | &mtl_c10_hdmi_25_2, /* Consolidated Table */ | |
1411 | &mtl_c10_hdmi_27_0, /* Consolidated Table */ | |
1412 | &mtl_c10_hdmi_27027, | |
1413 | &mtl_c10_hdmi_28320, | |
1414 | &mtl_c10_hdmi_30240, | |
1415 | &mtl_c10_hdmi_31500, | |
1416 | &mtl_c10_hdmi_36000, | |
1417 | &mtl_c10_hdmi_40000, | |
1418 | &mtl_c10_hdmi_49500, | |
1419 | &mtl_c10_hdmi_50000, | |
1420 | &mtl_c10_hdmi_57284, | |
1421 | &mtl_c10_hdmi_58000, | |
1422 | &mtl_c10_hdmi_65000, | |
1423 | &mtl_c10_hdmi_71000, | |
1424 | &mtl_c10_hdmi_74176, | |
1425 | &mtl_c10_hdmi_74_25, /* Consolidated Table */ | |
1426 | &mtl_c10_hdmi_75000, | |
1427 | &mtl_c10_hdmi_78750, | |
1428 | &mtl_c10_hdmi_85500, | |
1429 | &mtl_c10_hdmi_88750, | |
1430 | &mtl_c10_hdmi_106500, | |
1431 | &mtl_c10_hdmi_108000, | |
1432 | &mtl_c10_hdmi_115500, | |
1433 | &mtl_c10_hdmi_119000, | |
1434 | &mtl_c10_hdmi_135000, | |
1435 | &mtl_c10_hdmi_138500, | |
1436 | &mtl_c10_hdmi_147160, | |
1437 | &mtl_c10_hdmi_148352, | |
1438 | &mtl_c10_hdmi_148_5, /* Consolidated Table */ | |
1439 | &mtl_c10_hdmi_154000, | |
1440 | &mtl_c10_hdmi_162000, | |
1441 | &mtl_c10_hdmi_167000, | |
1442 | &mtl_c10_hdmi_197802, | |
1443 | &mtl_c10_hdmi_198000, | |
1444 | &mtl_c10_hdmi_209800, | |
1445 | &mtl_c10_hdmi_241500, | |
1446 | &mtl_c10_hdmi_262750, | |
1447 | &mtl_c10_hdmi_268500, | |
1448 | &mtl_c10_hdmi_296703, | |
1449 | &mtl_c10_hdmi_297000, | |
1450 | &mtl_c10_hdmi_319750, | |
1451 | &mtl_c10_hdmi_497750, | |
1452 | &mtl_c10_hdmi_592000, | |
1453 | &mtl_c10_hdmi_593407, | |
1454 | &mtl_c10_hdmi_594, /* Consolidated Table */ | |
1455 | NULL, | |
1456 | }; | |
1457 | ||
929f527a MK |
1458 | static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = { |
1459 | .link_bit_rate = 25175, | |
1460 | .clock = 25175, | |
1461 | .tx = { 0xbe88, /* tx cfg0 */ | |
1462 | 0x9800, /* tx cfg1 */ | |
1463 | 0x0000, /* tx cfg2 */ | |
1464 | }, | |
1465 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1466 | 0x0005, /* cmn cfg1 */ | |
1467 | 0x0000, /* cmn cfg2 */ | |
1468 | 0x0000, /* cmn cfg3 */ | |
1469 | }, | |
1470 | .mpllb = { 0xa0d2, /* mpllb cfg0 */ | |
1471 | 0x7d80, /* mpllb cfg1 */ | |
1472 | 0x0906, /* mpllb cfg2 */ | |
1473 | 0xbe40, /* mpllb cfg3 */ | |
1474 | 0x0000, /* mpllb cfg4 */ | |
1475 | 0x0000, /* mpllb cfg5 */ | |
1476 | 0x0200, /* mpllb cfg6 */ | |
1477 | 0x0001, /* mpllb cfg7 */ | |
1478 | 0x0000, /* mpllb cfg8 */ | |
1479 | 0x0000, /* mpllb cfg9 */ | |
1480 | 0x0001, /* mpllb cfg10 */ | |
1481 | }, | |
1482 | }; | |
1483 | ||
1484 | static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = { | |
1485 | .link_bit_rate = 27000, | |
1486 | .clock = 27000, | |
1487 | .tx = { 0xbe88, /* tx cfg0 */ | |
1488 | 0x9800, /* tx cfg1 */ | |
1489 | 0x0000, /* tx cfg2 */ | |
1490 | }, | |
1491 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1492 | 0x0005, /* cmn cfg1 */ | |
1493 | 0x0000, /* cmn cfg2 */ | |
1494 | 0x0000, /* cmn cfg3 */ | |
1495 | }, | |
1496 | .mpllb = { 0xa0e0, /* mpllb cfg0 */ | |
1497 | 0x7d80, /* mpllb cfg1 */ | |
1498 | 0x0906, /* mpllb cfg2 */ | |
1499 | 0xbe40, /* mpllb cfg3 */ | |
1500 | 0x0000, /* mpllb cfg4 */ | |
1501 | 0x0000, /* mpllb cfg5 */ | |
1502 | 0x2200, /* mpllb cfg6 */ | |
1503 | 0x0001, /* mpllb cfg7 */ | |
1504 | 0x8000, /* mpllb cfg8 */ | |
1505 | 0x0000, /* mpllb cfg9 */ | |
1506 | 0x0001, /* mpllb cfg10 */ | |
1507 | }, | |
1508 | }; | |
1509 | ||
1510 | static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = { | |
1511 | .link_bit_rate = 74250, | |
1512 | .clock = 74250, | |
1513 | .tx = { 0xbe88, /* tx cfg0 */ | |
1514 | 0x9800, /* tx cfg1 */ | |
1515 | 0x0000, /* tx cfg2 */ | |
1516 | }, | |
1517 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1518 | 0x0005, /* cmn cfg1 */ | |
1519 | 0x0000, /* cmn cfg2 */ | |
1520 | 0x0000, /* cmn cfg3 */ | |
1521 | }, | |
1522 | .mpllb = { 0x609a, /* mpllb cfg0 */ | |
1523 | 0x7d40, /* mpllb cfg1 */ | |
1524 | 0xca06, /* mpllb cfg2 */ | |
1525 | 0xbe40, /* mpllb cfg3 */ | |
1526 | 0x0000, /* mpllb cfg4 */ | |
1527 | 0x0000, /* mpllb cfg5 */ | |
1528 | 0x2200, /* mpllb cfg6 */ | |
1529 | 0x0001, /* mpllb cfg7 */ | |
1530 | 0x5800, /* mpllb cfg8 */ | |
1531 | 0x0000, /* mpllb cfg9 */ | |
1532 | 0x0001, /* mpllb cfg10 */ | |
1533 | }, | |
1534 | }; | |
1535 | ||
1536 | static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = { | |
1537 | .link_bit_rate = 148500, | |
1538 | .clock = 148500, | |
1539 | .tx = { 0xbe88, /* tx cfg0 */ | |
1540 | 0x9800, /* tx cfg1 */ | |
1541 | 0x0000, /* tx cfg2 */ | |
1542 | }, | |
1543 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1544 | 0x0005, /* cmn cfg1 */ | |
1545 | 0x0000, /* cmn cfg2 */ | |
1546 | 0x0000, /* cmn cfg3 */ | |
1547 | }, | |
1548 | .mpllb = { 0x409a, /* mpllb cfg0 */ | |
1549 | 0x7d20, /* mpllb cfg1 */ | |
1550 | 0xca06, /* mpllb cfg2 */ | |
1551 | 0xbe40, /* mpllb cfg3 */ | |
1552 | 0x0000, /* mpllb cfg4 */ | |
1553 | 0x0000, /* mpllb cfg5 */ | |
1554 | 0x2200, /* mpllb cfg6 */ | |
1555 | 0x0001, /* mpllb cfg7 */ | |
1556 | 0x5800, /* mpllb cfg8 */ | |
1557 | 0x0000, /* mpllb cfg9 */ | |
1558 | 0x0001, /* mpllb cfg10 */ | |
1559 | }, | |
1560 | }; | |
1561 | ||
1562 | static const struct intel_c20pll_state mtl_c20_hdmi_594 = { | |
1563 | .link_bit_rate = 594000, | |
1564 | .clock = 594000, | |
1565 | .tx = { 0xbe88, /* tx cfg0 */ | |
1566 | 0x9800, /* tx cfg1 */ | |
1567 | 0x0000, /* tx cfg2 */ | |
1568 | }, | |
1569 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1570 | 0x0005, /* cmn cfg1 */ | |
1571 | 0x0000, /* cmn cfg2 */ | |
1572 | 0x0000, /* cmn cfg3 */ | |
1573 | }, | |
1574 | .mpllb = { 0x009a, /* mpllb cfg0 */ | |
1575 | 0x7d08, /* mpllb cfg1 */ | |
1576 | 0xca06, /* mpllb cfg2 */ | |
1577 | 0xbe40, /* mpllb cfg3 */ | |
1578 | 0x0000, /* mpllb cfg4 */ | |
1579 | 0x0000, /* mpllb cfg5 */ | |
1580 | 0x2200, /* mpllb cfg6 */ | |
1581 | 0x0001, /* mpllb cfg7 */ | |
1582 | 0x5800, /* mpllb cfg8 */ | |
1583 | 0x0000, /* mpllb cfg9 */ | |
1584 | 0x0001, /* mpllb cfg10 */ | |
1585 | }, | |
1586 | }; | |
1587 | ||
1588 | static const struct intel_c20pll_state mtl_c20_hdmi_300 = { | |
1589 | .link_bit_rate = 3000000, | |
1590 | .clock = 166670, | |
1591 | .tx = { 0xbe98, /* tx cfg0 */ | |
1592 | 0x9800, /* tx cfg1 */ | |
1593 | 0x0000, /* tx cfg2 */ | |
1594 | }, | |
1595 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1596 | 0x0005, /* cmn cfg1 */ | |
1597 | 0x0000, /* cmn cfg2 */ | |
1598 | 0x0000, /* cmn cfg3 */ | |
1599 | }, | |
1600 | .mpllb = { 0x209c, /* mpllb cfg0 */ | |
1601 | 0x7d10, /* mpllb cfg1 */ | |
1602 | 0xca06, /* mpllb cfg2 */ | |
1603 | 0xbe40, /* mpllb cfg3 */ | |
1604 | 0x0000, /* mpllb cfg4 */ | |
1605 | 0x0000, /* mpllb cfg5 */ | |
1606 | 0x2200, /* mpllb cfg6 */ | |
1607 | 0x0001, /* mpllb cfg7 */ | |
1608 | 0x2000, /* mpllb cfg8 */ | |
1609 | 0x0000, /* mpllb cfg9 */ | |
1610 | 0x0004, /* mpllb cfg10 */ | |
1611 | }, | |
1612 | }; | |
1613 | ||
1614 | static const struct intel_c20pll_state mtl_c20_hdmi_600 = { | |
1615 | .link_bit_rate = 6000000, | |
1616 | .clock = 333330, | |
1617 | .tx = { 0xbe98, /* tx cfg0 */ | |
1618 | 0x9800, /* tx cfg1 */ | |
1619 | 0x0000, /* tx cfg2 */ | |
1620 | }, | |
1621 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1622 | 0x0005, /* cmn cfg1 */ | |
1623 | 0x0000, /* cmn cfg2 */ | |
1624 | 0x0000, /* cmn cfg3 */ | |
1625 | }, | |
1626 | .mpllb = { 0x009c, /* mpllb cfg0 */ | |
1627 | 0x7d08, /* mpllb cfg1 */ | |
1628 | 0xca06, /* mpllb cfg2 */ | |
1629 | 0xbe40, /* mpllb cfg3 */ | |
1630 | 0x0000, /* mpllb cfg4 */ | |
1631 | 0x0000, /* mpllb cfg5 */ | |
1632 | 0x2200, /* mpllb cfg6 */ | |
1633 | 0x0001, /* mpllb cfg7 */ | |
1634 | 0x2000, /* mpllb cfg8 */ | |
1635 | 0x0000, /* mpllb cfg9 */ | |
1636 | 0x0004, /* mpllb cfg10 */ | |
1637 | }, | |
1638 | }; | |
1639 | ||
1640 | static const struct intel_c20pll_state mtl_c20_hdmi_800 = { | |
1641 | .link_bit_rate = 8000000, | |
1642 | .clock = 444440, | |
1643 | .tx = { 0xbe98, /* tx cfg0 */ | |
1644 | 0x9800, /* tx cfg1 */ | |
1645 | 0x0000, /* tx cfg2 */ | |
1646 | }, | |
1647 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1648 | 0x0005, /* cmn cfg1 */ | |
1649 | 0x0000, /* cmn cfg2 */ | |
1650 | 0x0000, /* cmn cfg3 */ | |
1651 | }, | |
1652 | .mpllb = { 0x00d0, /* mpllb cfg0 */ | |
1653 | 0x7d08, /* mpllb cfg1 */ | |
1654 | 0x4a06, /* mpllb cfg2 */ | |
1655 | 0xbe40, /* mpllb cfg3 */ | |
1656 | 0x0000, /* mpllb cfg4 */ | |
1657 | 0x0000, /* mpllb cfg5 */ | |
1658 | 0x2200, /* mpllb cfg6 */ | |
1659 | 0x0003, /* mpllb cfg7 */ | |
1660 | 0x2aaa, /* mpllb cfg8 */ | |
1661 | 0x0002, /* mpllb cfg9 */ | |
1662 | 0x0004, /* mpllb cfg10 */ | |
1663 | }, | |
1664 | }; | |
1665 | ||
1666 | static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { | |
1667 | .link_bit_rate = 10000000, | |
1668 | .clock = 555560, | |
1669 | .tx = { 0xbe98, /* tx cfg0 */ | |
1670 | 0x9800, /* tx cfg1 */ | |
1671 | 0x0000, /* tx cfg2 */ | |
1672 | }, | |
1673 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1674 | 0x0005, /* cmn cfg1 */ | |
1675 | 0x0000, /* cmn cfg2 */ | |
1676 | 0x0000, /* cmn cfg3 */ | |
1677 | }, | |
1678 | .mpllb = { 0x1104, /* mpllb cfg0 */ | |
1679 | 0x7d08, /* mpllb cfg1 */ | |
1680 | 0x0a06, /* mpllb cfg2 */ | |
1681 | 0xbe40, /* mpllb cfg3 */ | |
1682 | 0x0000, /* mpllb cfg4 */ | |
1683 | 0x0000, /* mpllb cfg5 */ | |
1684 | 0x2200, /* mpllb cfg6 */ | |
1685 | 0x0003, /* mpllb cfg7 */ | |
1686 | 0x3555, /* mpllb cfg8 */ | |
1687 | 0x0001, /* mpllb cfg9 */ | |
1688 | 0x0004, /* mpllb cfg10 */ | |
1689 | }, | |
1690 | }; | |
1691 | ||
1692 | static const struct intel_c20pll_state mtl_c20_hdmi_1200 = { | |
1693 | .link_bit_rate = 12000000, | |
1694 | .clock = 666670, | |
1695 | .tx = { 0xbe98, /* tx cfg0 */ | |
1696 | 0x9800, /* tx cfg1 */ | |
1697 | 0x0000, /* tx cfg2 */ | |
1698 | }, | |
1699 | .cmn = { 0x0500, /* cmn cfg0*/ | |
1700 | 0x0005, /* cmn cfg1 */ | |
1701 | 0x0000, /* cmn cfg2 */ | |
1702 | 0x0000, /* cmn cfg3 */ | |
1703 | }, | |
1704 | .mpllb = { 0x0138, /* mpllb cfg0 */ | |
1705 | 0x7d08, /* mpllb cfg1 */ | |
1706 | 0x5486, /* mpllb cfg2 */ | |
1707 | 0xfe40, /* mpllb cfg3 */ | |
1708 | 0x0000, /* mpllb cfg4 */ | |
1709 | 0x0000, /* mpllb cfg5 */ | |
1710 | 0x2200, /* mpllb cfg6 */ | |
1711 | 0x0001, /* mpllb cfg7 */ | |
1712 | 0x4000, /* mpllb cfg8 */ | |
1713 | 0x0000, /* mpllb cfg9 */ | |
1714 | 0x0004, /* mpllb cfg10 */ | |
1715 | }, | |
1716 | }; | |
1717 | ||
1718 | static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = { | |
1719 | &mtl_c20_hdmi_25_175, | |
1720 | &mtl_c20_hdmi_27_0, | |
1721 | &mtl_c20_hdmi_74_25, | |
1722 | &mtl_c20_hdmi_148_5, | |
1723 | &mtl_c20_hdmi_594, | |
1724 | &mtl_c20_hdmi_300, | |
1725 | &mtl_c20_hdmi_600, | |
1726 | &mtl_c20_hdmi_800, | |
1727 | &mtl_c20_hdmi_1000, | |
1728 | &mtl_c20_hdmi_1200, | |
1729 | NULL, | |
1730 | }; | |
1731 | ||
1732 | static int intel_c10_phy_check_hdmi_link_rate(int clock) | |
5836bc5f RS |
1733 | { |
1734 | const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables; | |
1735 | int i; | |
1736 | ||
1737 | for (i = 0; tables[i]; i++) { | |
1738 | if (clock == tables[i]->clock) | |
1739 | return MODE_OK; | |
1740 | } | |
1741 | ||
1742 | return MODE_CLOCK_RANGE; | |
1743 | } | |
1744 | ||
51390cc0 RS |
1745 | static const struct intel_c10pll_state * const * |
1746 | intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, | |
1747 | struct intel_encoder *encoder) | |
1748 | { | |
1749 | if (intel_crtc_has_dp_encoder(crtc_state)) { | |
1750 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) | |
1751 | return mtl_c10_edp_tables; | |
1752 | else | |
1753 | return mtl_c10_dp_tables; | |
5836bc5f RS |
1754 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
1755 | return mtl_c10_hdmi_tables; | |
51390cc0 RS |
1756 | } |
1757 | ||
51390cc0 RS |
1758 | MISSING_CASE(encoder->type); |
1759 | return NULL; | |
1760 | } | |
1761 | ||
1762 | static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state, | |
1763 | struct intel_encoder *encoder) | |
1764 | { | |
1765 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
1766 | struct intel_cx0pll_state *pll_state = &crtc_state->cx0pll_state; | |
1767 | int i; | |
1768 | ||
1769 | if (intel_crtc_has_dp_encoder(crtc_state)) { | |
1770 | if (intel_panel_use_ssc(i915)) { | |
1771 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1772 | ||
1773 | pll_state->ssc_enabled = | |
1774 | (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); | |
1775 | } | |
1776 | } | |
1777 | ||
1778 | if (pll_state->ssc_enabled) | |
1779 | return; | |
1780 | ||
1781 | drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); | |
1782 | for (i = 4; i < 9; i++) | |
1783 | pll_state->c10.pll[i] = 0; | |
1784 | } | |
1785 | ||
1786 | static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, | |
1787 | struct intel_encoder *encoder) | |
1788 | { | |
1789 | const struct intel_c10pll_state * const *tables; | |
1790 | int i; | |
1791 | ||
1792 | tables = intel_c10pll_tables_get(crtc_state, encoder); | |
1793 | if (!tables) | |
1794 | return -EINVAL; | |
1795 | ||
1796 | for (i = 0; tables[i]; i++) { | |
1797 | if (crtc_state->port_clock == tables[i]->clock) { | |
1798 | crtc_state->cx0pll_state.c10 = *tables[i]; | |
1799 | intel_c10pll_update_pll(crtc_state, encoder); | |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | } | |
1804 | ||
1805 | return -EINVAL; | |
1806 | } | |
1807 | ||
51390cc0 RS |
1808 | void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, |
1809 | struct intel_c10pll_state *pll_state) | |
1810 | { | |
1811 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
1812 | u8 lane = INTEL_CX0_LANE0; | |
1813 | intel_wakeref_t wakeref; | |
1814 | int i; | |
1815 | ||
1816 | wakeref = intel_cx0_phy_transaction_begin(encoder); | |
1817 | ||
1818 | /* | |
1819 | * According to C10 VDR Register programming Sequence we need | |
1820 | * to do this to read PHY internal registers from MsgBus. | |
1821 | */ | |
1822 | intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), | |
1823 | 0, C10_VDR_CTRL_MSGBUS_ACCESS, | |
1824 | MB_WRITE_COMMITTED); | |
1825 | ||
1826 | for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) | |
1827 | pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane, | |
1828 | PHY_C10_VDR_PLL(i)); | |
1829 | ||
1830 | pll_state->cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0)); | |
1831 | pll_state->tx = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0)); | |
1832 | ||
1833 | intel_cx0_phy_transaction_end(encoder, wakeref); | |
1834 | } | |
1835 | ||
1836 | static void intel_c10_pll_program(struct drm_i915_private *i915, | |
1837 | const struct intel_crtc_state *crtc_state, | |
1838 | struct intel_encoder *encoder) | |
1839 | { | |
1840 | const struct intel_c10pll_state *pll_state = &crtc_state->cx0pll_state.c10; | |
1841 | int i; | |
1842 | ||
1843 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), | |
1844 | 0, C10_VDR_CTRL_MSGBUS_ACCESS, | |
1845 | MB_WRITE_COMMITTED); | |
5836bc5f | 1846 | |
51390cc0 RS |
1847 | /* Custom width needs to be programmed to 0 for both the phy lanes */ |
1848 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, | |
1849 | C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10, | |
1850 | MB_WRITE_COMMITTED); | |
1851 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), | |
1852 | 0, C10_VDR_CTRL_UPDATE_CFG, | |
1853 | MB_WRITE_COMMITTED); | |
1854 | ||
1855 | /* Program the pll values only for the master lane */ | |
1856 | for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) | |
1857 | intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i), | |
1858 | pll_state->pll[i], | |
1859 | (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED); | |
1860 | ||
1861 | intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); | |
1862 | intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); | |
1863 | ||
1864 | intel_cx0_rmw(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), | |
1865 | 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, | |
1866 | MB_WRITE_COMMITTED); | |
1867 | } | |
1868 | ||
1869 | void intel_c10pll_dump_hw_state(struct drm_i915_private *i915, | |
1870 | const struct intel_c10pll_state *hw_state) | |
1871 | { | |
1872 | bool fracen; | |
1873 | int i; | |
1874 | unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; | |
1875 | unsigned int multiplier, tx_clk_div; | |
1876 | ||
1877 | fracen = hw_state->pll[0] & C10_PLL0_FRACEN; | |
1878 | drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ", | |
1879 | str_yes_no(fracen)); | |
1880 | ||
1881 | if (fracen) { | |
1882 | frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; | |
1883 | frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; | |
1884 | frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; | |
1885 | drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n", | |
1886 | frac_quot, frac_rem, frac_den); | |
1887 | } | |
1888 | ||
1889 | multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | | |
1890 | hw_state->pll[2]) / 2 + 16; | |
1891 | tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); | |
1892 | drm_dbg_kms(&i915->drm, | |
1893 | "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div); | |
1894 | ||
1895 | drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:"); | |
1896 | drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); | |
1897 | ||
1898 | BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); | |
1899 | for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) | |
1900 | drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", | |
1901 | i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], | |
1902 | i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); | |
1903 | } | |
1904 | ||
234fcb97 CT |
1905 | static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state) |
1906 | { | |
1907 | u64 datarate; | |
1908 | u64 mpll_tx_clk_div; | |
1909 | u64 vco_freq_shift; | |
1910 | u64 vco_freq; | |
1911 | u64 multiplier; | |
1912 | u64 mpll_multiplier; | |
1913 | u64 mpll_fracn_quot; | |
1914 | u64 mpll_fracn_rem; | |
1915 | u8 mpllb_ana_freq_vco; | |
1916 | u8 mpll_div_multiplier; | |
1917 | ||
1918 | if (pixel_clock < 25175 || pixel_clock > 600000) | |
1919 | return -EINVAL; | |
1920 | ||
1921 | datarate = ((u64)pixel_clock * 1000) * 10; | |
1922 | mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate)); | |
1923 | vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate)); | |
1924 | vco_freq = (datarate << vco_freq_shift) >> 8; | |
1925 | multiplier = div64_u64((vco_freq << 28), (REFCLK_38_4_MHZ >> 4)); | |
1926 | mpll_multiplier = 2 * (multiplier >> 32); | |
1927 | ||
1928 | mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; | |
1929 | mpll_fracn_rem = multiplier & 0xFFFF; | |
1930 | ||
1931 | mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), | |
1932 | datarate), 255); | |
1933 | ||
1934 | if (vco_freq <= DATARATE_3000000000) | |
1935 | mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3; | |
1936 | else if (vco_freq <= DATARATE_3500000000) | |
1937 | mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_2; | |
1938 | else if (vco_freq <= DATARATE_4000000000) | |
1939 | mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_1; | |
1940 | else | |
1941 | mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0; | |
1942 | ||
1943 | pll_state->link_bit_rate = pixel_clock; | |
1944 | pll_state->clock = pixel_clock; | |
1945 | pll_state->tx[0] = 0xbe88; | |
1946 | pll_state->tx[1] = 0x9800; | |
1947 | pll_state->tx[2] = 0x0000; | |
1948 | pll_state->cmn[0] = 0x0500; | |
1949 | pll_state->cmn[1] = 0x0005; | |
1950 | pll_state->cmn[2] = 0x0000; | |
1951 | pll_state->cmn[3] = 0x0000; | |
1952 | pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | | |
1953 | MPLL_MULTIPLIER(mpll_multiplier)); | |
1954 | pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | | |
1955 | WORD_CLK_DIV | | |
1956 | MPLL_DIV_MULTIPLIER(mpll_div_multiplier)); | |
1957 | pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | | |
1958 | CP_PROP(CP_PROP_20) | | |
1959 | CP_INT(CP_INT_6)); | |
1960 | pll_state->mpllb[3] = (V2I(V2I_2) | | |
1961 | CP_PROP_GS(CP_PROP_GS_30) | | |
1962 | CP_INT_GS(CP_INT_GS_28)); | |
1963 | pll_state->mpllb[4] = 0x0000; | |
1964 | pll_state->mpllb[5] = 0x0000; | |
1965 | pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); | |
1966 | pll_state->mpllb[7] = MPLL_FRACN_DEN; | |
1967 | pll_state->mpllb[8] = mpll_fracn_quot; | |
1968 | pll_state->mpllb[9] = mpll_fracn_rem; | |
1969 | pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1); | |
1970 | ||
1971 | return 0; | |
1972 | } | |
1973 | ||
929f527a MK |
1974 | static int intel_c20_phy_check_hdmi_link_rate(int clock) |
1975 | { | |
1976 | const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables; | |
1977 | int i; | |
1978 | ||
1979 | for (i = 0; tables[i]; i++) { | |
1980 | if (clock == tables[i]->link_bit_rate) | |
1981 | return MODE_OK; | |
1982 | } | |
1983 | ||
234fcb97 CT |
1984 | if (clock >= 25175 && clock <= 594000) |
1985 | return MODE_OK; | |
1986 | ||
929f527a MK |
1987 | return MODE_CLOCK_RANGE; |
1988 | } | |
1989 | ||
1990 | int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock) | |
1991 | { | |
1992 | struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi); | |
1993 | struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi); | |
1994 | enum phy phy = intel_port_to_phy(i915, dig_port->base.port); | |
1995 | ||
1996 | if (intel_is_c10phy(i915, phy)) | |
1997 | return intel_c10_phy_check_hdmi_link_rate(clock); | |
1998 | return intel_c20_phy_check_hdmi_link_rate(clock); | |
1999 | } | |
2000 | ||
2001 | static const struct intel_c20pll_state * const * | |
2002 | intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, | |
2003 | struct intel_encoder *encoder) | |
2004 | { | |
2005 | if (intel_crtc_has_dp_encoder(crtc_state)) | |
2006 | return mtl_c20_dp_tables; | |
2007 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
2008 | return mtl_c20_hdmi_tables; | |
2009 | ||
2010 | MISSING_CASE(encoder->type); | |
2011 | return NULL; | |
2012 | } | |
2013 | ||
2014 | static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, | |
2015 | struct intel_encoder *encoder) | |
2016 | { | |
2017 | const struct intel_c20pll_state * const *tables; | |
2018 | int i; | |
2019 | ||
234fcb97 CT |
2020 | /* try computed C20 HDMI tables before using consolidated tables */ |
2021 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { | |
2022 | if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, | |
2023 | &crtc_state->cx0pll_state.c20) == 0) | |
2024 | return 0; | |
2025 | } | |
2026 | ||
929f527a MK |
2027 | tables = intel_c20_pll_tables_get(crtc_state, encoder); |
2028 | if (!tables) | |
2029 | return -EINVAL; | |
2030 | ||
2031 | for (i = 0; tables[i]; i++) { | |
2032 | if (crtc_state->port_clock == tables[i]->link_bit_rate) { | |
2033 | crtc_state->cx0pll_state.c20 = *tables[i]; | |
2034 | return 0; | |
2035 | } | |
2036 | } | |
2037 | ||
2038 | return -EINVAL; | |
2039 | } | |
2040 | ||
2041 | int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, | |
2042 | struct intel_encoder *encoder) | |
2043 | { | |
2044 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2045 | enum phy phy = intel_port_to_phy(i915, encoder->port); | |
2046 | ||
2047 | if (intel_is_c10phy(i915, phy)) | |
2048 | return intel_c10pll_calc_state(crtc_state, encoder); | |
2049 | return intel_c20pll_calc_state(crtc_state, encoder); | |
2050 | } | |
2051 | ||
62618c7f MK |
2052 | static bool intel_c20_use_mplla(u32 clock) |
2053 | { | |
2054 | /* 10G and 20G rates use MPLLA */ | |
2055 | if (clock == 312500 || clock == 625000) | |
2056 | return true; | |
2057 | ||
2058 | return false; | |
2059 | } | |
2060 | ||
929f527a MK |
2061 | void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, |
2062 | struct intel_c20pll_state *pll_state) | |
2063 | { | |
2064 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2065 | bool cntx; | |
2066 | intel_wakeref_t wakeref; | |
2067 | int i; | |
2068 | ||
2069 | wakeref = intel_cx0_phy_transaction_begin(encoder); | |
2070 | ||
2071 | /* 1. Read current context selection */ | |
2072 | cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; | |
2073 | ||
2074 | /* Read Tx configuration */ | |
2075 | for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { | |
2076 | if (cntx) | |
2077 | pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2078 | PHY_C20_B_TX_CNTX_CFG(i)); | |
2079 | else | |
2080 | pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2081 | PHY_C20_A_TX_CNTX_CFG(i)); | |
2082 | } | |
2083 | ||
2084 | /* Read common configuration */ | |
2085 | for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { | |
2086 | if (cntx) | |
2087 | pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2088 | PHY_C20_B_CMN_CNTX_CFG(i)); | |
2089 | else | |
2090 | pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2091 | PHY_C20_A_CMN_CNTX_CFG(i)); | |
2092 | } | |
2093 | ||
2094 | if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { | |
2095 | /* MPLLB configuration */ | |
2096 | for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { | |
2097 | if (cntx) | |
2098 | pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2099 | PHY_C20_B_MPLLB_CNTX_CFG(i)); | |
2100 | else | |
2101 | pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2102 | PHY_C20_A_MPLLB_CNTX_CFG(i)); | |
2103 | } | |
2104 | } else { | |
2105 | /* MPLLA configuration */ | |
2106 | for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { | |
2107 | if (cntx) | |
2108 | pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2109 | PHY_C20_B_MPLLA_CNTX_CFG(i)); | |
2110 | else | |
2111 | pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, | |
2112 | PHY_C20_A_MPLLA_CNTX_CFG(i)); | |
2113 | } | |
2114 | } | |
2115 | ||
2116 | intel_cx0_phy_transaction_end(encoder, wakeref); | |
2117 | } | |
2118 | ||
f968a253 MK |
2119 | void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, |
2120 | const struct intel_c20pll_state *hw_state) | |
2121 | { | |
2122 | int i; | |
2123 | ||
2124 | drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); | |
2125 | drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", | |
2126 | hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); | |
2127 | drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", | |
2128 | hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); | |
2129 | ||
2130 | if (intel_c20_use_mplla(hw_state->clock)) { | |
2131 | for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) | |
2132 | drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); | |
2133 | } else { | |
2134 | for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) | |
2135 | drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); | |
2136 | } | |
2137 | } | |
2138 | ||
62618c7f MK |
2139 | static u8 intel_c20_get_dp_rate(u32 clock) |
2140 | { | |
2141 | switch (clock) { | |
2142 | case 162000: /* 1.62 Gbps DP1.4 */ | |
2143 | return 0; | |
2144 | case 270000: /* 2.7 Gbps DP1.4 */ | |
2145 | return 1; | |
2146 | case 540000: /* 5.4 Gbps DP 1.4 */ | |
2147 | return 2; | |
2148 | case 810000: /* 8.1 Gbps DP1.4 */ | |
2149 | return 3; | |
2150 | case 216000: /* 2.16 Gbps eDP */ | |
2151 | return 4; | |
2152 | case 243000: /* 2.43 Gbps eDP */ | |
2153 | return 5; | |
2154 | case 324000: /* 3.24 Gbps eDP */ | |
2155 | return 6; | |
2156 | case 432000: /* 4.32 Gbps eDP */ | |
2157 | return 7; | |
2158 | case 312500: /* 10 Gbps DP2.0 */ | |
2159 | return 8; | |
2160 | case 421875: /* 13.5 Gbps DP2.0 */ | |
2161 | return 9; | |
2162 | case 625000: /* 20 Gbps DP2.0*/ | |
2163 | return 10; | |
2164 | case 648000: /* 6.48 Gbps eDP*/ | |
2165 | return 11; | |
2166 | case 675000: /* 6.75 Gbps eDP*/ | |
2167 | return 12; | |
2168 | default: | |
2169 | MISSING_CASE(clock); | |
2170 | return 0; | |
2171 | } | |
2172 | } | |
2173 | ||
2174 | static u8 intel_c20_get_hdmi_rate(u32 clock) | |
2175 | { | |
234fcb97 | 2176 | if (clock >= 25175 && clock <= 600000) |
62618c7f | 2177 | return 0; |
234fcb97 CT |
2178 | |
2179 | switch (clock) { | |
62618c7f MK |
2180 | case 166670: /* 3 Gbps */ |
2181 | case 333330: /* 6 Gbps */ | |
2182 | case 666670: /* 12 Gbps */ | |
2183 | return 1; | |
2184 | case 444440: /* 8 Gbps */ | |
2185 | return 2; | |
2186 | case 555560: /* 10 Gbps */ | |
2187 | return 3; | |
2188 | default: | |
2189 | MISSING_CASE(clock); | |
2190 | return 0; | |
2191 | } | |
2192 | } | |
2193 | ||
2194 | static bool is_dp2(u32 clock) | |
2195 | { | |
2196 | /* DP2.0 clock rates */ | |
2197 | if (clock == 312500 || clock == 421875 || clock == 625000) | |
2198 | return true; | |
2199 | ||
2200 | return false; | |
2201 | } | |
2202 | ||
2203 | static bool is_hdmi_frl(u32 clock) | |
2204 | { | |
2205 | switch (clock) { | |
2206 | case 166670: /* 3 Gbps */ | |
2207 | case 333330: /* 6 Gbps */ | |
2208 | case 444440: /* 8 Gbps */ | |
2209 | case 555560: /* 10 Gbps */ | |
2210 | case 666670: /* 12 Gbps */ | |
2211 | return true; | |
2212 | default: | |
2213 | return false; | |
2214 | } | |
2215 | } | |
2216 | ||
2217 | static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) | |
2218 | { | |
2219 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
2220 | ||
2221 | /* banks should not be cleared for DPALT/USB4/TBT modes */ | |
2222 | /* TODO: optimize re-calibration in legacy mode */ | |
2223 | return intel_tc_port_in_legacy_mode(intel_dig_port); | |
2224 | } | |
2225 | ||
2226 | static int intel_get_c20_custom_width(u32 clock, bool dp) | |
2227 | { | |
2228 | if (dp && is_dp2(clock)) | |
2229 | return 2; | |
2230 | else if (is_hdmi_frl(clock)) | |
2231 | return 1; | |
2232 | else | |
2233 | return 0; | |
2234 | } | |
2235 | ||
2236 | static void intel_c20_pll_program(struct drm_i915_private *i915, | |
2237 | const struct intel_crtc_state *crtc_state, | |
2238 | struct intel_encoder *encoder) | |
2239 | { | |
2240 | const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; | |
2241 | bool dp = false; | |
2242 | int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; | |
2243 | bool cntx; | |
2244 | int i; | |
2245 | ||
2246 | if (intel_crtc_has_dp_encoder(crtc_state)) | |
2247 | dp = true; | |
2248 | ||
2249 | /* 1. Read current context selection */ | |
2250 | cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); | |
2251 | ||
2252 | /* | |
2253 | * 2. If there is a protocol switch from HDMI to DP or vice versa, clear | |
2254 | * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. | |
2255 | * Protocol switch is only applicable for MPLLA | |
2256 | */ | |
2257 | if (intel_c20_protocol_switch_valid(encoder)) { | |
2258 | for (i = 0; i < 4; i++) | |
2259 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); | |
2260 | usleep_range(4000, 4100); | |
2261 | } | |
2262 | ||
2263 | /* 3. Write SRAM configuration context. If A in use, write configuration to B context */ | |
2264 | /* 3.1 Tx configuration */ | |
2265 | for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { | |
2266 | if (cntx) | |
2267 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]); | |
2268 | else | |
2269 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]); | |
2270 | } | |
2271 | ||
2272 | /* 3.2 common configuration */ | |
2273 | for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { | |
2274 | if (cntx) | |
2275 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]); | |
2276 | else | |
2277 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]); | |
2278 | } | |
2279 | ||
2280 | /* 3.3 mpllb or mplla configuration */ | |
2281 | if (intel_c20_use_mplla(pll_state->clock)) { | |
2282 | for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { | |
2283 | if (cntx) | |
2284 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, | |
2285 | PHY_C20_A_MPLLA_CNTX_CFG(i), | |
2286 | pll_state->mplla[i]); | |
2287 | else | |
2288 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, | |
2289 | PHY_C20_B_MPLLA_CNTX_CFG(i), | |
2290 | pll_state->mplla[i]); | |
2291 | } | |
2292 | } else { | |
2293 | for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { | |
2294 | if (cntx) | |
2295 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, | |
2296 | PHY_C20_A_MPLLB_CNTX_CFG(i), | |
2297 | pll_state->mpllb[i]); | |
2298 | else | |
2299 | intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, | |
2300 | PHY_C20_B_MPLLB_CNTX_CFG(i), | |
2301 | pll_state->mpllb[i]); | |
2302 | } | |
2303 | } | |
2304 | ||
2305 | /* 4. Program custom width to match the link protocol */ | |
2306 | intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH, | |
2307 | PHY_C20_CUSTOM_WIDTH_MASK, | |
2308 | PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(pll_state->clock, dp)), | |
2309 | MB_WRITE_COMMITTED); | |
2310 | ||
2311 | /* 5. For DP or 6. For HDMI */ | |
2312 | if (dp) { | |
2313 | intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, | |
2314 | BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, | |
2315 | BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)), | |
2316 | MB_WRITE_COMMITTED); | |
2317 | } else { | |
2318 | intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, | |
2319 | BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, | |
2320 | is_hdmi_frl(pll_state->clock) ? BIT(7) : 0, | |
2321 | MB_WRITE_COMMITTED); | |
2322 | ||
2323 | intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, | |
2324 | intel_c20_get_hdmi_rate(pll_state->clock), | |
2325 | MB_WRITE_COMMITTED); | |
2326 | } | |
2327 | ||
2328 | /* | |
2329 | * 7. Write Vendor specific registers to toggle context setting to load | |
2330 | * the updated programming toggle context bit | |
2331 | */ | |
2332 | intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, | |
2333 | BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); | |
2334 | } | |
2335 | ||
51390cc0 RS |
2336 | int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, |
2337 | const struct intel_c10pll_state *pll_state) | |
2338 | { | |
2339 | unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; | |
5836bc5f RS |
2340 | unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; |
2341 | int tmpclk = 0; | |
51390cc0 RS |
2342 | |
2343 | if (pll_state->pll[0] & C10_PLL0_FRACEN) { | |
2344 | frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; | |
2345 | frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; | |
2346 | frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; | |
2347 | } | |
2348 | ||
2349 | multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | | |
2350 | pll_state->pll[2]) / 2 + 16; | |
2351 | ||
2352 | tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); | |
5836bc5f | 2353 | hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); |
51390cc0 | 2354 | |
5836bc5f | 2355 | tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + |
51390cc0 RS |
2356 | DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), |
2357 | 10 << (tx_clk_div + 16)); | |
5836bc5f RS |
2358 | tmpclk *= (hdmi_div ? 2 : 1); |
2359 | ||
2360 | return tmpclk; | |
51390cc0 RS |
2361 | } |
2362 | ||
f1f9e627 MK |
2363 | int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, |
2364 | const struct intel_c20pll_state *pll_state) | |
2365 | { | |
2366 | unsigned int frac, frac_en, frac_quot, frac_rem, frac_den; | |
2367 | unsigned int multiplier, refclk = 38400; | |
2368 | unsigned int tx_clk_div; | |
2369 | unsigned int ref_clk_mpllb_div; | |
2370 | unsigned int fb_clk_div4_en; | |
2371 | unsigned int ref, vco; | |
2372 | unsigned int tx_rate_mult; | |
2373 | unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); | |
2374 | ||
2375 | if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { | |
2376 | tx_rate_mult = 1; | |
2377 | frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); | |
2378 | frac_quot = pll_state->mpllb[8]; | |
2379 | frac_rem = pll_state->mpllb[9]; | |
2380 | frac_den = pll_state->mpllb[7]; | |
2381 | multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); | |
2382 | tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); | |
2383 | ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); | |
2384 | fb_clk_div4_en = 0; | |
2385 | } else { | |
2386 | tx_rate_mult = 2; | |
2387 | frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); | |
2388 | frac_quot = pll_state->mplla[8]; | |
2389 | frac_rem = pll_state->mplla[9]; | |
2390 | frac_den = pll_state->mplla[7]; | |
2391 | multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); | |
2392 | tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); | |
2393 | ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); | |
2394 | fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); | |
2395 | } | |
2396 | ||
2397 | if (frac_en) | |
2398 | frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den); | |
2399 | else | |
2400 | frac = 0; | |
2401 | ||
2402 | ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); | |
2403 | vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); | |
2404 | ||
2405 | return vco << tx_rate_mult >> tx_clk_div >> tx_rate; | |
2406 | } | |
2407 | ||
51390cc0 RS |
2408 | static void intel_program_port_clock_ctl(struct intel_encoder *encoder, |
2409 | const struct intel_crtc_state *crtc_state, | |
2410 | bool lane_reversal) | |
2411 | { | |
2412 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2413 | u32 val = 0; | |
2414 | ||
2415 | intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL, | |
2416 | lane_reversal ? XELPDP_PORT_REVERSAL : 0); | |
2417 | ||
2418 | if (lane_reversal) | |
2419 | val |= XELPDP_LANE1_PHY_CLOCK_SELECT; | |
2420 | ||
2421 | val |= XELPDP_FORWARD_CLOCK_UNGATE; | |
62618c7f MK |
2422 | |
2423 | if (is_hdmi_frl(crtc_state->port_clock)) | |
2424 | val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK); | |
2425 | else | |
2426 | val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); | |
51390cc0 RS |
2427 | |
2428 | /* TODO: HDMI FRL */ | |
237e7be0 MK |
2429 | /* DP2.0 10G and 20G rates enable MPLLA*/ |
2430 | if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) | |
2431 | val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; | |
2432 | else | |
2433 | val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; | |
51390cc0 RS |
2434 | |
2435 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
ea8af87a | 2436 | XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | |
7e8d87e2 RS |
2437 | XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA | |
2438 | XELPDP_SSC_ENABLE_PLLB, val); | |
51390cc0 RS |
2439 | } |
2440 | ||
2441 | static u32 intel_cx0_get_powerdown_update(u8 lane_mask) | |
2442 | { | |
2443 | u32 val = 0; | |
2444 | int lane = 0; | |
2445 | ||
2446 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
2447 | val |= XELPDP_LANE_POWERDOWN_UPDATE(lane); | |
2448 | ||
2449 | return val; | |
2450 | } | |
2451 | ||
2452 | static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state) | |
2453 | { | |
2454 | u32 val = 0; | |
2455 | int lane = 0; | |
2456 | ||
2457 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
2458 | val |= XELPDP_LANE_POWERDOWN_NEW_STATE(lane, state); | |
2459 | ||
2460 | return val; | |
2461 | } | |
2462 | ||
2463 | static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915, | |
2464 | enum port port, | |
2465 | u8 lane_mask, u8 state) | |
2466 | { | |
2467 | enum phy phy = intel_port_to_phy(i915, port); | |
2468 | int lane; | |
2469 | ||
2470 | intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), | |
2471 | intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK), | |
2472 | intel_cx0_get_powerdown_state(lane_mask, state)); | |
2473 | ||
2474 | /* Wait for pending transactions.*/ | |
2475 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
2476 | if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane), | |
2477 | XELPDP_PORT_M2P_TRANSACTION_PENDING, | |
2478 | XELPDP_MSGBUS_TIMEOUT_SLOW)) { | |
2479 | drm_dbg_kms(&i915->drm, | |
2480 | "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n", | |
2481 | phy_name(phy)); | |
2482 | intel_cx0_bus_reset(i915, port, lane); | |
2483 | } | |
2484 | ||
2485 | intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), | |
2486 | intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES), | |
2487 | intel_cx0_get_powerdown_update(lane_mask)); | |
2488 | ||
2489 | /* Update Timeout Value */ | |
2490 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port), | |
2491 | intel_cx0_get_powerdown_update(lane_mask), 0, | |
2492 | XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) | |
2493 | drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", | |
2494 | phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); | |
2495 | } | |
2496 | ||
2497 | static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port) | |
2498 | { | |
2499 | intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), | |
2500 | XELPDP_POWER_STATE_READY_MASK, | |
2501 | XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY)); | |
2502 | intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port), | |
2503 | XELPDP_POWER_STATE_ACTIVE_MASK | | |
2504 | XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, | |
2505 | XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) | | |
2506 | XELPDP_PLL_LANE_STAGGERING_DELAY(0)); | |
2507 | } | |
2508 | ||
2509 | static u32 intel_cx0_get_pclk_refclk_request(u8 lane_mask) | |
2510 | { | |
2511 | u32 val = 0; | |
2512 | int lane = 0; | |
2513 | ||
2514 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
2515 | val |= XELPDP_LANE_PCLK_REFCLK_REQUEST(lane); | |
2516 | ||
2517 | return val; | |
2518 | } | |
2519 | ||
2520 | static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask) | |
2521 | { | |
2522 | u32 val = 0; | |
2523 | int lane = 0; | |
2524 | ||
2525 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
2526 | val |= XELPDP_LANE_PCLK_REFCLK_ACK(lane); | |
2527 | ||
2528 | return val; | |
2529 | } | |
2530 | ||
619a06db MK |
2531 | static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, |
2532 | struct intel_encoder *encoder, | |
51390cc0 RS |
2533 | bool lane_reversal) |
2534 | { | |
619a06db | 2535 | enum port port = encoder->port; |
51390cc0 | 2536 | enum phy phy = intel_port_to_phy(i915, port); |
619a06db | 2537 | bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2; |
51390cc0 RS |
2538 | u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : |
2539 | INTEL_CX0_LANE0; | |
619a06db MK |
2540 | u32 lane_pipe_reset = both_lanes ? |
2541 | XELPDP_LANE_PIPE_RESET(0) | | |
2542 | XELPDP_LANE_PIPE_RESET(1) : | |
2543 | XELPDP_LANE_PIPE_RESET(0); | |
2544 | u32 lane_phy_current_status = both_lanes ? | |
2545 | XELPDP_LANE_PHY_CURRENT_STATUS(0) | | |
2546 | XELPDP_LANE_PHY_CURRENT_STATUS(1) : | |
2547 | XELPDP_LANE_PHY_CURRENT_STATUS(0); | |
51390cc0 RS |
2548 | |
2549 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port), | |
2550 | XELPDP_PORT_BUF_SOC_PHY_READY, | |
2551 | XELPDP_PORT_BUF_SOC_PHY_READY, | |
2552 | XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) | |
2553 | drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n", | |
2554 | phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US); | |
2555 | ||
5e4c16fe | 2556 | intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, |
619a06db | 2557 | lane_pipe_reset); |
51390cc0 RS |
2558 | |
2559 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port), | |
619a06db | 2560 | lane_phy_current_status, lane_phy_current_status, |
51390cc0 RS |
2561 | XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) |
2562 | drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", | |
2563 | phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US); | |
2564 | ||
2565 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port), | |
619a06db MK |
2566 | intel_cx0_get_pclk_refclk_request(both_lanes ? |
2567 | INTEL_CX0_BOTH_LANES : | |
2568 | INTEL_CX0_LANE0), | |
51390cc0 RS |
2569 | intel_cx0_get_pclk_refclk_request(lane_mask)); |
2570 | ||
2571 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port), | |
619a06db MK |
2572 | intel_cx0_get_pclk_refclk_ack(both_lanes ? |
2573 | INTEL_CX0_BOTH_LANES : | |
2574 | INTEL_CX0_LANE0), | |
51390cc0 RS |
2575 | intel_cx0_get_pclk_refclk_ack(lane_mask), |
2576 | XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) | |
2577 | drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n", | |
2578 | phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US); | |
2579 | ||
2580 | intel_cx0_powerdown_change_sequence(i915, port, INTEL_CX0_BOTH_LANES, | |
2581 | CX0_P2_STATE_RESET); | |
2582 | intel_cx0_setup_powerdown(i915, port); | |
2583 | ||
619a06db | 2584 | intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0); |
51390cc0 | 2585 | |
619a06db | 2586 | if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status, |
51390cc0 RS |
2587 | XELPDP_PORT_RESET_END_TIMEOUT)) |
2588 | drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n", | |
2589 | phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT); | |
2590 | } | |
2591 | ||
62618c7f | 2592 | static void intel_cx0_program_phy_lane(struct drm_i915_private *i915, |
51390cc0 RS |
2593 | struct intel_encoder *encoder, int lane_count, |
2594 | bool lane_reversal) | |
2595 | { | |
2596 | u8 l0t1, l0t2, l1t1, l1t2; | |
2597 | bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); | |
2598 | enum port port = encoder->port; | |
2599 | ||
62618c7f MK |
2600 | if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) |
2601 | intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, | |
2602 | PHY_C10_VDR_CONTROL(1), 0, | |
2603 | C10_VDR_CTRL_MSGBUS_ACCESS, | |
2604 | MB_WRITE_COMMITTED); | |
51390cc0 RS |
2605 | |
2606 | /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */ | |
2607 | l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2)); | |
2608 | l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2)); | |
2609 | l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2)); | |
2610 | l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2)); | |
2611 | ||
2612 | l0t1 |= CONTROL2_DISABLE_SINGLE_TX; | |
2613 | l0t2 |= CONTROL2_DISABLE_SINGLE_TX; | |
2614 | l1t1 |= CONTROL2_DISABLE_SINGLE_TX; | |
2615 | l1t2 |= CONTROL2_DISABLE_SINGLE_TX; | |
2616 | ||
2617 | if (lane_reversal) { | |
2618 | switch (lane_count) { | |
2619 | case 4: | |
2620 | l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2621 | fallthrough; | |
2622 | case 3: | |
2623 | l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2624 | fallthrough; | |
2625 | case 2: | |
2626 | l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2627 | fallthrough; | |
2628 | case 1: | |
2629 | l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2630 | break; | |
2631 | default: | |
2632 | MISSING_CASE(lane_count); | |
2633 | } | |
2634 | } else { | |
2635 | switch (lane_count) { | |
2636 | case 4: | |
2637 | l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2638 | fallthrough; | |
2639 | case 3: | |
2640 | l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2641 | fallthrough; | |
2642 | case 2: | |
2643 | l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2644 | l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2645 | break; | |
2646 | case 1: | |
2647 | if (dp_alt_mode) | |
2648 | l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2649 | else | |
2650 | l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX; | |
2651 | break; | |
2652 | default: | |
2653 | MISSING_CASE(lane_count); | |
2654 | } | |
2655 | } | |
2656 | ||
2657 | /* disable MLs */ | |
2658 | intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2), | |
2659 | l0t1, MB_WRITE_COMMITTED); | |
2660 | intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2), | |
2661 | l0t2, MB_WRITE_COMMITTED); | |
2662 | intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2), | |
2663 | l1t1, MB_WRITE_COMMITTED); | |
2664 | intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2), | |
2665 | l1t2, MB_WRITE_COMMITTED); | |
2666 | ||
62618c7f MK |
2667 | if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) |
2668 | intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, | |
2669 | PHY_C10_VDR_CONTROL(1), 0, | |
2670 | C10_VDR_CTRL_UPDATE_CFG, | |
2671 | MB_WRITE_COMMITTED); | |
51390cc0 RS |
2672 | } |
2673 | ||
2674 | static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) | |
2675 | { | |
2676 | u32 val = 0; | |
2677 | int lane = 0; | |
2678 | ||
2679 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
2680 | val |= XELPDP_LANE_PCLK_PLL_REQUEST(lane); | |
2681 | ||
2682 | return val; | |
2683 | } | |
2684 | ||
2685 | static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask) | |
2686 | { | |
2687 | u32 val = 0; | |
2688 | int lane = 0; | |
2689 | ||
2690 | for_each_cx0_lane_in_mask(lane_mask, lane) | |
2691 | val |= XELPDP_LANE_PCLK_PLL_ACK(lane); | |
2692 | ||
2693 | return val; | |
2694 | } | |
2695 | ||
73fc3abc MK |
2696 | static void intel_cx0pll_enable(struct intel_encoder *encoder, |
2697 | const struct intel_crtc_state *crtc_state) | |
51390cc0 RS |
2698 | { |
2699 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2700 | enum phy phy = intel_port_to_phy(i915, encoder->port); | |
2701 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); | |
2702 | bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; | |
2703 | u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : | |
2704 | INTEL_CX0_LANE0; | |
62618c7f | 2705 | intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); |
51390cc0 RS |
2706 | |
2707 | /* | |
2708 | * 1. Program PORT_CLOCK_CTL REGISTER to configure | |
2709 | * clock muxes, gating and SSC | |
2710 | */ | |
2711 | intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal); | |
2712 | ||
2713 | /* 2. Bring PHY out of reset. */ | |
619a06db | 2714 | intel_cx0_phy_lane_reset(i915, encoder, lane_reversal); |
51390cc0 RS |
2715 | |
2716 | /* | |
2717 | * 3. Change Phy power state to Ready. | |
2718 | * TODO: For DP alt mode use only one lane. | |
2719 | */ | |
2720 | intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES, | |
2721 | CX0_P2_STATE_READY); | |
2722 | ||
2723 | /* 4. Program PHY internal PLL internal registers. */ | |
62618c7f MK |
2724 | if (intel_is_c10phy(i915, phy)) |
2725 | intel_c10_pll_program(i915, crtc_state, encoder); | |
2726 | else | |
2727 | intel_c20_pll_program(i915, crtc_state, encoder); | |
51390cc0 RS |
2728 | |
2729 | /* | |
2730 | * 5. Program the enabled and disabled owned PHY lane | |
2731 | * transmitters over message bus | |
2732 | */ | |
62618c7f | 2733 | intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal); |
51390cc0 RS |
2734 | |
2735 | /* | |
2736 | * 6. Follow the Display Voltage Frequency Switching - Sequence | |
2737 | * Before Frequency Change. We handle this step in bxt_set_cdclk(). | |
2738 | */ | |
2739 | ||
2740 | /* | |
2741 | * 7. Program DDI_CLK_VALFREQ to match intended DDI | |
2742 | * clock frequency. | |
2743 | */ | |
2744 | intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), | |
2745 | crtc_state->port_clock); | |
2746 | ||
2747 | /* | |
2748 | * 8. Set PORT_CLOCK_CTL register PCLK PLL Request | |
2749 | * LN<Lane for maxPCLK> to "1" to enable PLL. | |
2750 | */ | |
2751 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2752 | intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES), | |
2753 | intel_cx0_get_pclk_pll_request(maxpclk_lane)); | |
2754 | ||
2755 | /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ | |
2756 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2757 | intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES), | |
2758 | intel_cx0_get_pclk_pll_ack(maxpclk_lane), | |
2759 | XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) | |
2760 | drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n", | |
2761 | phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US); | |
2762 | ||
2763 | /* | |
2764 | * 10. Follow the Display Voltage Frequency Switching Sequence After | |
2765 | * Frequency Change. We handle this step in bxt_set_cdclk(). | |
2766 | */ | |
51390cc0 RS |
2767 | |
2768 | /* TODO: enable TBT-ALT mode */ | |
2769 | intel_cx0_phy_transaction_end(encoder, wakeref); | |
2770 | } | |
2771 | ||
7dee06bc MK |
2772 | int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) |
2773 | { | |
2774 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2775 | u32 clock; | |
2776 | u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); | |
2777 | ||
2778 | clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); | |
2779 | ||
2780 | drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); | |
2781 | drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); | |
2782 | drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK)); | |
2783 | ||
2784 | switch (clock) { | |
2785 | case XELPDP_DDI_CLOCK_SELECT_TBT_162: | |
2786 | return 162000; | |
2787 | case XELPDP_DDI_CLOCK_SELECT_TBT_270: | |
2788 | return 270000; | |
2789 | case XELPDP_DDI_CLOCK_SELECT_TBT_540: | |
2790 | return 540000; | |
2791 | case XELPDP_DDI_CLOCK_SELECT_TBT_810: | |
2792 | return 810000; | |
2793 | default: | |
2794 | MISSING_CASE(clock); | |
2795 | return 162000; | |
2796 | } | |
2797 | } | |
2798 | ||
73fc3abc MK |
2799 | static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock) |
2800 | { | |
2801 | switch (clock) { | |
2802 | case 162000: | |
2803 | return XELPDP_DDI_CLOCK_SELECT_TBT_162; | |
2804 | case 270000: | |
2805 | return XELPDP_DDI_CLOCK_SELECT_TBT_270; | |
2806 | case 540000: | |
2807 | return XELPDP_DDI_CLOCK_SELECT_TBT_540; | |
2808 | case 810000: | |
2809 | return XELPDP_DDI_CLOCK_SELECT_TBT_810; | |
2810 | default: | |
2811 | MISSING_CASE(clock); | |
2812 | return XELPDP_DDI_CLOCK_SELECT_TBT_162; | |
2813 | } | |
2814 | } | |
2815 | ||
2816 | static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, | |
2817 | const struct intel_crtc_state *crtc_state) | |
2818 | { | |
2819 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2820 | enum phy phy = intel_port_to_phy(i915, encoder->port); | |
2821 | u32 val = 0; | |
2822 | ||
2823 | /* | |
2824 | * 1. Program PORT_CLOCK_CTL REGISTER to configure | |
2825 | * clock muxes, gating and SSC | |
2826 | */ | |
2827 | val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock)); | |
2828 | val |= XELPDP_FORWARD_CLOCK_UNGATE; | |
2829 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2830 | XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val); | |
2831 | ||
2832 | /* 2. Read back PORT_CLOCK_CTL REGISTER */ | |
2833 | val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); | |
2834 | ||
2835 | /* | |
2836 | * 3. Follow the Display Voltage Frequency Switching - Sequence | |
2837 | * Before Frequency Change. We handle this step in bxt_set_cdclk(). | |
2838 | */ | |
2839 | ||
2840 | /* | |
2841 | * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. | |
2842 | */ | |
2843 | val |= XELPDP_TBT_CLOCK_REQUEST; | |
2844 | intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val); | |
2845 | ||
2846 | /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */ | |
2847 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2848 | XELPDP_TBT_CLOCK_ACK, | |
2849 | XELPDP_TBT_CLOCK_ACK, | |
2850 | 100, 0, NULL)) | |
2851 | drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n", | |
2852 | encoder->base.base.id, encoder->base.name, phy_name(phy)); | |
2853 | ||
2854 | /* | |
2855 | * 6. Follow the Display Voltage Frequency Switching Sequence After | |
2856 | * Frequency Change. We handle this step in bxt_set_cdclk(). | |
2857 | */ | |
2858 | ||
2859 | /* | |
2860 | * 7. Program DDI_CLK_VALFREQ to match intended DDI | |
2861 | * clock frequency. | |
2862 | */ | |
2863 | intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), | |
2864 | crtc_state->port_clock); | |
2865 | } | |
2866 | ||
2867 | void intel_mtl_pll_enable(struct intel_encoder *encoder, | |
2868 | const struct intel_crtc_state *crtc_state) | |
2869 | { | |
2870 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); | |
2871 | ||
2872 | if (intel_tc_port_in_tbt_alt_mode(dig_port)) | |
2873 | intel_mtl_tbt_pll_enable(encoder, crtc_state); | |
2874 | else | |
2875 | intel_cx0pll_enable(encoder, crtc_state); | |
2876 | } | |
2877 | ||
2878 | static void intel_cx0pll_disable(struct intel_encoder *encoder) | |
51390cc0 RS |
2879 | { |
2880 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2881 | enum phy phy = intel_port_to_phy(i915, encoder->port); | |
62618c7f MK |
2882 | bool is_c10 = intel_is_c10phy(i915, phy); |
2883 | intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); | |
51390cc0 RS |
2884 | |
2885 | /* 1. Change owned PHY lane power to Disable state. */ | |
2886 | intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES, | |
62618c7f MK |
2887 | is_c10 ? CX0_P2PG_STATE_DISABLE : |
2888 | CX0_P4PG_STATE_DISABLE); | |
51390cc0 RS |
2889 | |
2890 | /* | |
2891 | * 2. Follow the Display Voltage Frequency Switching Sequence Before | |
2892 | * Frequency Change. We handle this step in bxt_set_cdclk(). | |
2893 | */ | |
2894 | ||
2895 | /* | |
2896 | * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> | |
2897 | * to "0" to disable PLL. | |
2898 | */ | |
2899 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2900 | intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) | | |
2901 | intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); | |
2902 | ||
2903 | /* 4. Program DDI_CLK_VALFREQ to 0. */ | |
2904 | intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); | |
2905 | ||
2906 | /* | |
2907 | * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". | |
2908 | */ | |
2909 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2910 | intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) | | |
2911 | intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, | |
2912 | XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) | |
2913 | drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n", | |
2914 | phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US); | |
2915 | ||
2916 | /* | |
2917 | * 6. Follow the Display Voltage Frequency Switching Sequence After | |
2918 | * Frequency Change. We handle this step in bxt_set_cdclk(). | |
2919 | */ | |
2920 | ||
2921 | /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */ | |
2922 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
ea8af87a MK |
2923 | XELPDP_DDI_CLOCK_SELECT_MASK, 0); |
2924 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
51390cc0 | 2925 | XELPDP_FORWARD_CLOCK_UNGATE, 0); |
51390cc0 | 2926 | |
51390cc0 RS |
2927 | intel_cx0_phy_transaction_end(encoder, wakeref); |
2928 | } | |
2929 | ||
73fc3abc MK |
2930 | static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) |
2931 | { | |
2932 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2933 | enum phy phy = intel_port_to_phy(i915, encoder->port); | |
2934 | ||
2935 | /* | |
2936 | * 1. Follow the Display Voltage Frequency Switching Sequence Before | |
2937 | * Frequency Change. We handle this step in bxt_set_cdclk(). | |
2938 | */ | |
2939 | ||
2940 | /* | |
2941 | * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. | |
2942 | */ | |
2943 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2944 | XELPDP_TBT_CLOCK_REQUEST, 0); | |
2945 | ||
2946 | /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ | |
2947 | if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
615ed9ec | 2948 | XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) |
73fc3abc MK |
2949 | drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", |
2950 | encoder->base.base.id, encoder->base.name, phy_name(phy)); | |
2951 | ||
2952 | /* | |
2953 | * 4. Follow the Display Voltage Frequency Switching Sequence After | |
2954 | * Frequency Change. We handle this step in bxt_set_cdclk(). | |
2955 | */ | |
2956 | ||
2957 | /* | |
2958 | * 5. Program PORT CLOCK CTRL register to disable and gate clocks | |
2959 | */ | |
2960 | intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), | |
2961 | XELPDP_DDI_CLOCK_SELECT_MASK | | |
2962 | XELPDP_FORWARD_CLOCK_UNGATE, 0); | |
2963 | ||
2964 | /* 6. Program DDI_CLK_VALFREQ to 0. */ | |
2965 | intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); | |
2966 | } | |
2967 | ||
2968 | void intel_mtl_pll_disable(struct intel_encoder *encoder) | |
2969 | { | |
2970 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); | |
2971 | ||
2972 | if (intel_tc_port_in_tbt_alt_mode(dig_port)) | |
2973 | intel_mtl_tbt_pll_disable(encoder); | |
2974 | else | |
2975 | intel_cx0pll_disable(encoder); | |
2976 | } | |
2977 | ||
6f0423b0 MK |
2978 | enum icl_port_dpll_id |
2979 | intel_mtl_port_pll_type(struct intel_encoder *encoder, | |
2980 | const struct intel_crtc_state *crtc_state) | |
2981 | { | |
2982 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2983 | /* | |
2984 | * TODO: Determine the PLL type from the SW state, once MTL PLL | |
2985 | * handling is done via the standard shared DPLL framework. | |
2986 | */ | |
2987 | u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port)); | |
2988 | u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val); | |
2989 | ||
2990 | if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK || | |
2991 | clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK) | |
2992 | return ICL_PORT_DPLL_MG_PHY; | |
2993 | else | |
2994 | return ICL_PORT_DPLL_DEFAULT; | |
2995 | } | |
2996 | ||
51390cc0 RS |
2997 | void intel_c10pll_state_verify(struct intel_atomic_state *state, |
2998 | struct intel_crtc_state *new_crtc_state) | |
2999 | { | |
3000 | struct drm_i915_private *i915 = to_i915(state->base.dev); | |
3001 | struct intel_c10pll_state mpllb_hw_state = { 0 }; | |
3002 | struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10; | |
3003 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); | |
3004 | struct intel_encoder *encoder; | |
3005 | enum phy phy; | |
3006 | int i; | |
3007 | ||
3008 | if (DISPLAY_VER(i915) < 14) | |
3009 | return; | |
3010 | ||
3011 | if (!new_crtc_state->hw.active) | |
3012 | return; | |
3013 | ||
e920aabf VS |
3014 | /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ |
3015 | if (!intel_crtc_needs_modeset(new_crtc_state) && | |
3016 | !intel_crtc_needs_fastset(new_crtc_state)) | |
3017 | return; | |
3018 | ||
51390cc0 RS |
3019 | encoder = intel_get_crtc_new_encoder(state, new_crtc_state); |
3020 | phy = intel_port_to_phy(i915, encoder->port); | |
3021 | ||
3022 | if (!intel_is_c10phy(i915, phy)) | |
3023 | return; | |
3024 | ||
3025 | intel_c10pll_readout_hw_state(encoder, &mpllb_hw_state); | |
3026 | ||
3027 | for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { | |
3028 | u8 expected = mpllb_sw_state->pll[i]; | |
3029 | ||
6b9bd7c3 | 3030 | I915_STATE_WARN(i915, mpllb_hw_state.pll[i] != expected, |
51390cc0 | 3031 | "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", |
6b9bd7c3 JN |
3032 | crtc->base.base.id, crtc->base.name, i, |
3033 | expected, mpllb_hw_state.pll[i]); | |
51390cc0 RS |
3034 | } |
3035 | ||
6b9bd7c3 | 3036 | I915_STATE_WARN(i915, mpllb_hw_state.tx != mpllb_sw_state->tx, |
51390cc0 RS |
3037 | "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", |
3038 | crtc->base.base.id, crtc->base.name, | |
3039 | mpllb_sw_state->tx, mpllb_hw_state.tx); | |
3040 | ||
6b9bd7c3 | 3041 | I915_STATE_WARN(i915, mpllb_hw_state.cmn != mpllb_sw_state->cmn, |
51390cc0 RS |
3042 | "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", |
3043 | crtc->base.base.id, crtc->base.name, | |
3044 | mpllb_sw_state->cmn, mpllb_hw_state.cmn); | |
3045 | } |