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99ce270a DA |
1 | // SPDX-License-Identifier: MIT |
2 | /* | |
3 | * Copyright © 2020 Intel Corporation | |
4 | */ | |
5 | #include <linux/kernel.h> | |
6 | ||
7 | #include <drm/drm_atomic_helper.h> | |
8 | #include <drm/drm_atomic_uapi.h> | |
90bb087f | 9 | #include <drm/drm_blend.h> |
99ce270a | 10 | #include <drm/drm_damage_helper.h> |
99ce270a DA |
11 | #include <drm/drm_fourcc.h> |
12 | ||
801543b2 | 13 | #include "i915_reg.h" |
99ce270a DA |
14 | #include "intel_atomic.h" |
15 | #include "intel_atomic_plane.h" | |
16 | #include "intel_cursor.h" | |
7785ae0b | 17 | #include "intel_de.h" |
99ce270a | 18 | #include "intel_display.h" |
801543b2 | 19 | #include "intel_display_types.h" |
3cee6269 | 20 | #include "intel_fb.h" |
814c8757 | 21 | #include "intel_fb_pin.h" |
99ce270a | 22 | #include "intel_frontbuffer.h" |
99ce270a | 23 | #include "intel_psr.h" |
b1f5279b | 24 | #include "intel_psr_regs.h" |
1de63528 | 25 | #include "intel_vblank.h" |
42a0d256 | 26 | #include "skl_watermark.h" |
99ce270a | 27 | |
7054b551 ML |
28 | #include "gem/i915_gem_object.h" |
29 | ||
99ce270a DA |
30 | /* Cursor formats */ |
31 | static const u32 intel_cursor_formats[] = { | |
32 | DRM_FORMAT_ARGB8888, | |
33 | }; | |
34 | ||
99ce270a DA |
35 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
36 | { | |
37 | struct drm_i915_private *dev_priv = | |
38 | to_i915(plane_state->uapi.plane->dev); | |
99ce270a DA |
39 | u32 base; |
40 | ||
5af5169d | 41 | if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) |
582dc04b | 42 | base = plane_state->phys_dma_addr; |
99ce270a DA |
43 | else |
44 | base = intel_plane_ggtt_offset(plane_state); | |
45 | ||
61169987 | 46 | return base + plane_state->view.color_plane[0].offset; |
99ce270a DA |
47 | } |
48 | ||
7f85883e JH |
49 | static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state, |
50 | const struct intel_plane_state *plane_state, | |
51 | bool early_tpt) | |
99ce270a DA |
52 | { |
53 | int x = plane_state->uapi.dst.x1; | |
54 | int y = plane_state->uapi.dst.y1; | |
55 | u32 pos = 0; | |
56 | ||
7f85883e JH |
57 | /* |
58 | * Formula from Bspec: | |
59 | * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode | |
60 | * select setting> + 1, CUR_POS Y Position - Update region Y position | |
61 | */ | |
62 | if (early_tpt) | |
63 | y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1, | |
64 | y - crtc_state->psr2_su_area.y1); | |
65 | ||
99ce270a | 66 | if (x < 0) { |
348abd4c | 67 | pos |= CURSOR_POS_X_SIGN; |
99ce270a DA |
68 | x = -x; |
69 | } | |
348abd4c | 70 | pos |= CURSOR_POS_X(x); |
99ce270a DA |
71 | |
72 | if (y < 0) { | |
348abd4c | 73 | pos |= CURSOR_POS_Y_SIGN; |
99ce270a DA |
74 | y = -y; |
75 | } | |
348abd4c | 76 | pos |= CURSOR_POS_Y(y); |
99ce270a DA |
77 | |
78 | return pos; | |
79 | } | |
80 | ||
81 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) | |
82 | { | |
83 | const struct drm_mode_config *config = | |
84 | &plane_state->uapi.plane->dev->mode_config; | |
85 | int width = drm_rect_width(&plane_state->uapi.dst); | |
86 | int height = drm_rect_height(&plane_state->uapi.dst); | |
87 | ||
88 | return width > 0 && width <= config->cursor_width && | |
89 | height > 0 && height <= config->cursor_height; | |
90 | } | |
91 | ||
92 | static int intel_cursor_check_surface(struct intel_plane_state *plane_state) | |
93 | { | |
94 | struct drm_i915_private *dev_priv = | |
95 | to_i915(plane_state->uapi.plane->dev); | |
96 | unsigned int rotation = plane_state->hw.rotation; | |
97 | int src_x, src_y; | |
98 | u32 offset; | |
99 | int ret; | |
100 | ||
101 | ret = intel_plane_compute_gtt(plane_state); | |
102 | if (ret) | |
103 | return ret; | |
104 | ||
105 | if (!plane_state->uapi.visible) | |
106 | return 0; | |
107 | ||
108 | src_x = plane_state->uapi.src.x1 >> 16; | |
109 | src_y = plane_state->uapi.src.y1 >> 16; | |
110 | ||
111 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
112 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, | |
113 | plane_state, 0); | |
114 | ||
115 | if (src_x != 0 || src_y != 0) { | |
116 | drm_dbg_kms(&dev_priv->drm, | |
117 | "Arbitrary cursor panning not supported\n"); | |
118 | return -EINVAL; | |
119 | } | |
120 | ||
121 | /* | |
122 | * Put the final coordinates back so that the src | |
123 | * coordinate checks will see the right values. | |
124 | */ | |
125 | drm_rect_translate_to(&plane_state->uapi.src, | |
126 | src_x << 16, src_y << 16); | |
127 | ||
128 | /* ILK+ do this automagically in hardware */ | |
129 | if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { | |
130 | const struct drm_framebuffer *fb = plane_state->hw.fb; | |
131 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; | |
132 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; | |
133 | ||
134 | offset += (src_h * src_w - 1) * fb->format->cpp[0]; | |
135 | } | |
136 | ||
61169987 ID |
137 | plane_state->view.color_plane[0].offset = offset; |
138 | plane_state->view.color_plane[0].x = src_x; | |
139 | plane_state->view.color_plane[0].y = src_y; | |
99ce270a DA |
140 | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, | |
145 | struct intel_plane_state *plane_state) | |
146 | { | |
147 | const struct drm_framebuffer *fb = plane_state->hw.fb; | |
148 | struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); | |
149 | const struct drm_rect src = plane_state->uapi.src; | |
150 | const struct drm_rect dst = plane_state->uapi.dst; | |
151 | int ret; | |
152 | ||
153 | if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
154 | drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); | |
155 | return -EINVAL; | |
156 | } | |
157 | ||
158 | ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, | |
cce32e4e TZ |
159 | DRM_PLANE_NO_SCALING, |
160 | DRM_PLANE_NO_SCALING, | |
99ce270a DA |
161 | true); |
162 | if (ret) | |
163 | return ret; | |
164 | ||
165 | /* Use the unclipped src/dst rectangles, which we program to hw */ | |
166 | plane_state->uapi.src = src; | |
167 | plane_state->uapi.dst = dst; | |
8d8b2dd3 VS |
168 | |
169 | /* final plane coordinates will be relative to the plane's pipe */ | |
170 | drm_rect_translate(&plane_state->uapi.dst, | |
171 | -crtc_state->pipe_src.x1, | |
172 | -crtc_state->pipe_src.y1); | |
99ce270a DA |
173 | |
174 | ret = intel_cursor_check_surface(plane_state); | |
175 | if (ret) | |
176 | return ret; | |
177 | ||
178 | if (!plane_state->uapi.visible) | |
179 | return 0; | |
180 | ||
181 | ret = intel_plane_check_src_coordinates(plane_state); | |
182 | if (ret) | |
183 | return ret; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static unsigned int | |
189 | i845_cursor_max_stride(struct intel_plane *plane, | |
190 | u32 pixel_format, u64 modifier, | |
191 | unsigned int rotation) | |
192 | { | |
193 | return 2048; | |
194 | } | |
195 | ||
196 | static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) | |
197 | { | |
198 | u32 cntl = 0; | |
199 | ||
200 | if (crtc_state->gamma_enable) | |
348abd4c | 201 | cntl |= CURSOR_PIPE_GAMMA_ENABLE; |
99ce270a DA |
202 | |
203 | return cntl; | |
204 | } | |
205 | ||
206 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, | |
207 | const struct intel_plane_state *plane_state) | |
208 | { | |
209 | return CURSOR_ENABLE | | |
210 | CURSOR_FORMAT_ARGB | | |
be6c1dd5 | 211 | CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride); |
99ce270a DA |
212 | } |
213 | ||
214 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) | |
215 | { | |
216 | int width = drm_rect_width(&plane_state->uapi.dst); | |
217 | ||
218 | /* | |
219 | * 845g/865g are only limited by the width of their cursors, | |
220 | * the height is arbitrary up to the precision of the register. | |
221 | */ | |
222 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); | |
223 | } | |
224 | ||
225 | static int i845_check_cursor(struct intel_crtc_state *crtc_state, | |
226 | struct intel_plane_state *plane_state) | |
227 | { | |
228 | const struct drm_framebuffer *fb = plane_state->hw.fb; | |
229 | struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); | |
230 | int ret; | |
231 | ||
232 | ret = intel_check_cursor(crtc_state, plane_state); | |
233 | if (ret) | |
234 | return ret; | |
235 | ||
236 | /* if we want to turn off the cursor ignore width and height */ | |
237 | if (!fb) | |
238 | return 0; | |
239 | ||
240 | /* Check for which cursor types we support */ | |
241 | if (!i845_cursor_size_ok(plane_state)) { | |
242 | drm_dbg_kms(&i915->drm, | |
243 | "Cursor dimension %dx%d not supported\n", | |
244 | drm_rect_width(&plane_state->uapi.dst), | |
245 | drm_rect_height(&plane_state->uapi.dst)); | |
246 | return -EINVAL; | |
247 | } | |
248 | ||
249 | drm_WARN_ON(&i915->drm, plane_state->uapi.visible && | |
be6c1dd5 | 250 | plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); |
99ce270a DA |
251 | |
252 | switch (fb->pitches[0]) { | |
253 | case 256: | |
254 | case 512: | |
255 | case 1024: | |
256 | case 2048: | |
257 | break; | |
258 | default: | |
259 | drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", | |
260 | fb->pitches[0]); | |
261 | return -EINVAL; | |
262 | } | |
263 | ||
264 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
8ac80733 VS |
269 | /* TODO: split into noarm+arm pair */ |
270 | static void i845_cursor_update_arm(struct intel_plane *plane, | |
271 | const struct intel_crtc_state *crtc_state, | |
272 | const struct intel_plane_state *plane_state) | |
99ce270a DA |
273 | { |
274 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
275 | u32 cntl = 0, base = 0, pos = 0, size = 0; | |
99ce270a DA |
276 | |
277 | if (plane_state && plane_state->uapi.visible) { | |
278 | unsigned int width = drm_rect_width(&plane_state->uapi.dst); | |
279 | unsigned int height = drm_rect_height(&plane_state->uapi.dst); | |
280 | ||
281 | cntl = plane_state->ctl | | |
282 | i845_cursor_ctl_crtc(crtc_state); | |
283 | ||
348abd4c | 284 | size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width); |
99ce270a DA |
285 | |
286 | base = intel_cursor_base(plane_state); | |
7f85883e | 287 | pos = intel_cursor_position(crtc_state, plane_state, false); |
99ce270a DA |
288 | } |
289 | ||
99ce270a DA |
290 | /* On these chipsets we can only modify the base/size/stride |
291 | * whilst the cursor is disabled. | |
292 | */ | |
293 | if (plane->cursor.base != base || | |
294 | plane->cursor.size != size || | |
295 | plane->cursor.cntl != cntl) { | |
296 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); | |
297 | intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); | |
348abd4c | 298 | intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); |
99ce270a DA |
299 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); |
300 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); | |
301 | ||
302 | plane->cursor.base = base; | |
303 | plane->cursor.size = size; | |
304 | plane->cursor.cntl = cntl; | |
305 | } else { | |
306 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); | |
307 | } | |
99ce270a DA |
308 | } |
309 | ||
8ac80733 VS |
310 | static void i845_cursor_disable_arm(struct intel_plane *plane, |
311 | const struct intel_crtc_state *crtc_state) | |
99ce270a | 312 | { |
8ac80733 | 313 | i845_cursor_update_arm(plane, crtc_state, NULL); |
99ce270a DA |
314 | } |
315 | ||
316 | static bool i845_cursor_get_hw_state(struct intel_plane *plane, | |
317 | enum pipe *pipe) | |
318 | { | |
319 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
320 | enum intel_display_power_domain power_domain; | |
321 | intel_wakeref_t wakeref; | |
322 | bool ret; | |
323 | ||
324 | power_domain = POWER_DOMAIN_PIPE(PIPE_A); | |
325 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
326 | if (!wakeref) | |
327 | return false; | |
328 | ||
329 | ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; | |
330 | ||
331 | *pipe = PIPE_A; | |
332 | ||
333 | intel_display_power_put(dev_priv, power_domain, wakeref); | |
334 | ||
335 | return ret; | |
336 | } | |
337 | ||
338 | static unsigned int | |
339 | i9xx_cursor_max_stride(struct intel_plane *plane, | |
340 | u32 pixel_format, u64 modifier, | |
341 | unsigned int rotation) | |
342 | { | |
343 | return plane->base.dev->mode_config.cursor_width * 4; | |
344 | } | |
345 | ||
346 | static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) | |
347 | { | |
348 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
349 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
350 | u32 cntl = 0; | |
351 | ||
005e9537 | 352 | if (DISPLAY_VER(dev_priv) >= 11) |
99ce270a DA |
353 | return cntl; |
354 | ||
355 | if (crtc_state->gamma_enable) | |
348abd4c | 356 | cntl = MCURSOR_PIPE_GAMMA_ENABLE; |
99ce270a DA |
357 | |
358 | if (crtc_state->csc_enable) | |
359 | cntl |= MCURSOR_PIPE_CSC_ENABLE; | |
360 | ||
005e9537 | 361 | if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) |
348abd4c | 362 | cntl |= MCURSOR_PIPE_SEL(crtc->pipe); |
99ce270a DA |
363 | |
364 | return cntl; | |
365 | } | |
366 | ||
367 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, | |
368 | const struct intel_plane_state *plane_state) | |
369 | { | |
370 | struct drm_i915_private *dev_priv = | |
371 | to_i915(plane_state->uapi.plane->dev); | |
372 | u32 cntl = 0; | |
373 | ||
d47d29a6 | 374 | if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) |
99ce270a DA |
375 | cntl |= MCURSOR_TRICKLE_FEED_DISABLE; |
376 | ||
377 | switch (drm_rect_width(&plane_state->uapi.dst)) { | |
378 | case 64: | |
379 | cntl |= MCURSOR_MODE_64_ARGB_AX; | |
380 | break; | |
381 | case 128: | |
382 | cntl |= MCURSOR_MODE_128_ARGB_AX; | |
383 | break; | |
384 | case 256: | |
385 | cntl |= MCURSOR_MODE_256_ARGB_AX; | |
386 | break; | |
387 | default: | |
388 | MISSING_CASE(drm_rect_width(&plane_state->uapi.dst)); | |
389 | return 0; | |
390 | } | |
391 | ||
392 | if (plane_state->hw.rotation & DRM_MODE_ROTATE_180) | |
393 | cntl |= MCURSOR_ROTATE_180; | |
394 | ||
1d2b8fd9 | 395 | /* Wa_22012358565:adl-p */ |
0b86952d VS |
396 | if (DISPLAY_VER(dev_priv) == 13) |
397 | cntl |= MCURSOR_ARB_SLOTS(1); | |
398 | ||
99ce270a DA |
399 | return cntl; |
400 | } | |
401 | ||
402 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) | |
403 | { | |
404 | struct drm_i915_private *dev_priv = | |
405 | to_i915(plane_state->uapi.plane->dev); | |
406 | int width = drm_rect_width(&plane_state->uapi.dst); | |
407 | int height = drm_rect_height(&plane_state->uapi.dst); | |
408 | ||
409 | if (!intel_cursor_size_ok(plane_state)) | |
410 | return false; | |
411 | ||
412 | /* Cursor width is limited to a few power-of-two sizes */ | |
413 | switch (width) { | |
414 | case 256: | |
415 | case 128: | |
416 | case 64: | |
417 | break; | |
418 | default: | |
419 | return false; | |
420 | } | |
421 | ||
422 | /* | |
423 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
424 | * height from 8 lines up to the cursor width, when the | |
425 | * cursor is not rotated. Everything else requires square | |
426 | * cursors. | |
427 | */ | |
428 | if (HAS_CUR_FBC(dev_priv) && | |
429 | plane_state->hw.rotation & DRM_MODE_ROTATE_0) { | |
430 | if (height < 8 || height > width) | |
431 | return false; | |
432 | } else { | |
433 | if (height != width) | |
434 | return false; | |
435 | } | |
436 | ||
437 | return true; | |
438 | } | |
439 | ||
440 | static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, | |
441 | struct intel_plane_state *plane_state) | |
442 | { | |
443 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); | |
444 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
445 | const struct drm_framebuffer *fb = plane_state->hw.fb; | |
446 | enum pipe pipe = plane->pipe; | |
447 | int ret; | |
448 | ||
449 | ret = intel_check_cursor(crtc_state, plane_state); | |
450 | if (ret) | |
451 | return ret; | |
452 | ||
453 | /* if we want to turn off the cursor ignore width and height */ | |
454 | if (!fb) | |
455 | return 0; | |
456 | ||
457 | /* Check for which cursor types we support */ | |
458 | if (!i9xx_cursor_size_ok(plane_state)) { | |
459 | drm_dbg(&dev_priv->drm, | |
460 | "Cursor dimension %dx%d not supported\n", | |
461 | drm_rect_width(&plane_state->uapi.dst), | |
462 | drm_rect_height(&plane_state->uapi.dst)); | |
463 | return -EINVAL; | |
464 | } | |
465 | ||
466 | drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && | |
be6c1dd5 | 467 | plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); |
99ce270a DA |
468 | |
469 | if (fb->pitches[0] != | |
470 | drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { | |
471 | drm_dbg_kms(&dev_priv->drm, | |
472 | "Invalid cursor stride (%u) (cursor width %d)\n", | |
473 | fb->pitches[0], | |
474 | drm_rect_width(&plane_state->uapi.dst)); | |
475 | return -EINVAL; | |
476 | } | |
477 | ||
478 | /* | |
479 | * There's something wrong with the cursor on CHV pipe C. | |
480 | * If it straddles the left edge of the screen then | |
481 | * moving it away from the edge or disabling it often | |
482 | * results in a pipe underrun, and often that can lead to | |
483 | * dead pipe (constant underrun reported, and it scans | |
484 | * out just a solid color). To recover from that, the | |
485 | * display power well must be turned off and on again. | |
486 | * Refuse the put the cursor into that compromised position. | |
487 | */ | |
488 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
489 | plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { | |
490 | drm_dbg_kms(&dev_priv->drm, | |
491 | "CHV cursor C not allowed to straddle the left screen edge\n"); | |
492 | return -EINVAL; | |
493 | } | |
494 | ||
495 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
a4f477e6 JH |
500 | static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane, |
501 | const struct intel_crtc_state *crtc_state) | |
b1f5279b | 502 | { |
a4f477e6 | 503 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b1f5279b JH |
504 | enum pipe pipe = plane->pipe; |
505 | ||
506 | if (!crtc_state->enable_psr2_sel_fetch) | |
507 | return; | |
508 | ||
a4f477e6 | 509 | intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); |
b1f5279b JH |
510 | } |
511 | ||
a4f477e6 JH |
512 | static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, |
513 | const struct intel_crtc_state *crtc_state, | |
514 | const struct intel_plane_state *plane_state) | |
b1f5279b | 515 | { |
7f85883e | 516 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b1f5279b JH |
517 | enum pipe pipe = plane->pipe; |
518 | ||
519 | if (!crtc_state->enable_psr2_sel_fetch) | |
520 | return; | |
521 | ||
7f85883e JH |
522 | if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) { |
523 | if (crtc_state->enable_psr2_su_region_et) { | |
524 | u32 val = intel_cursor_position(crtc_state, plane_state, | |
525 | true); | |
526 | intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val); | |
527 | } | |
528 | ||
529 | intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), | |
a4f477e6 | 530 | plane_state->ctl); |
7f85883e | 531 | } else { |
a4f477e6 | 532 | i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state); |
7f85883e | 533 | } |
b1f5279b JH |
534 | } |
535 | ||
8ac80733 VS |
536 | /* TODO: split into noarm+arm pair */ |
537 | static void i9xx_cursor_update_arm(struct intel_plane *plane, | |
538 | const struct intel_crtc_state *crtc_state, | |
539 | const struct intel_plane_state *plane_state) | |
99ce270a DA |
540 | { |
541 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
542 | enum pipe pipe = plane->pipe; | |
543 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; | |
99ce270a DA |
544 | |
545 | if (plane_state && plane_state->uapi.visible) { | |
4e25ccde VS |
546 | int width = drm_rect_width(&plane_state->uapi.dst); |
547 | int height = drm_rect_height(&plane_state->uapi.dst); | |
99ce270a DA |
548 | |
549 | cntl = plane_state->ctl | | |
550 | i9xx_cursor_ctl_crtc(crtc_state); | |
551 | ||
552 | if (width != height) | |
348abd4c | 553 | fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1); |
99ce270a DA |
554 | |
555 | base = intel_cursor_base(plane_state); | |
7f85883e | 556 | pos = intel_cursor_position(crtc_state, plane_state, false); |
99ce270a DA |
557 | } |
558 | ||
99ce270a DA |
559 | /* |
560 | * On some platforms writing CURCNTR first will also | |
561 | * cause CURPOS to be armed by the CURBASE write. | |
562 | * Without the CURCNTR write the CURPOS write would | |
563 | * arm itself. Thus we always update CURCNTR before | |
564 | * CURPOS. | |
565 | * | |
566 | * On other platforms CURPOS always requires the | |
567 | * CURBASE write to arm the update. Additonally | |
568 | * a write to any of the cursor register will cancel | |
569 | * an already armed cursor update. Thus leaving out | |
570 | * the CURBASE write after CURPOS could lead to a | |
571 | * cursor that doesn't appear to move, or even change | |
572 | * shape. Thus we always write CURBASE. | |
573 | * | |
4e25ccde | 574 | * The other registers are armed by the CURBASE write |
99ce270a DA |
575 | * except when the plane is getting enabled at which time |
576 | * the CURCNTR write arms the update. | |
577 | */ | |
578 | ||
005e9537 | 579 | if (DISPLAY_VER(dev_priv) >= 9) |
99ce270a DA |
580 | skl_write_cursor_wm(plane, crtc_state); |
581 | ||
73262db6 | 582 | if (plane_state) |
b1f5279b JH |
583 | i9xx_cursor_update_sel_fetch_arm(plane, crtc_state, |
584 | plane_state); | |
73262db6 | 585 | else |
b1f5279b | 586 | i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state); |
99ce270a DA |
587 | |
588 | if (plane->cursor.base != base || | |
589 | plane->cursor.size != fbc_ctl || | |
590 | plane->cursor.cntl != cntl) { | |
591 | if (HAS_CUR_FBC(dev_priv)) | |
592 | intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), | |
593 | fbc_ctl); | |
594 | intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); | |
595 | intel_de_write_fw(dev_priv, CURPOS(pipe), pos); | |
596 | intel_de_write_fw(dev_priv, CURBASE(pipe), base); | |
597 | ||
598 | plane->cursor.base = base; | |
599 | plane->cursor.size = fbc_ctl; | |
600 | plane->cursor.cntl = cntl; | |
601 | } else { | |
602 | intel_de_write_fw(dev_priv, CURPOS(pipe), pos); | |
603 | intel_de_write_fw(dev_priv, CURBASE(pipe), base); | |
604 | } | |
99ce270a DA |
605 | } |
606 | ||
8ac80733 VS |
607 | static void i9xx_cursor_disable_arm(struct intel_plane *plane, |
608 | const struct intel_crtc_state *crtc_state) | |
99ce270a | 609 | { |
8ac80733 | 610 | i9xx_cursor_update_arm(plane, crtc_state, NULL); |
99ce270a DA |
611 | } |
612 | ||
613 | static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, | |
614 | enum pipe *pipe) | |
615 | { | |
616 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
617 | enum intel_display_power_domain power_domain; | |
618 | intel_wakeref_t wakeref; | |
619 | bool ret; | |
620 | u32 val; | |
621 | ||
622 | /* | |
623 | * Not 100% correct for planes that can move between pipes, | |
624 | * but that's only the case for gen2-3 which don't have any | |
625 | * display power wells. | |
626 | */ | |
627 | power_domain = POWER_DOMAIN_PIPE(plane->pipe); | |
628 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); | |
629 | if (!wakeref) | |
630 | return false; | |
631 | ||
632 | val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); | |
633 | ||
348abd4c | 634 | ret = val & MCURSOR_MODE_MASK; |
99ce270a | 635 | |
005e9537 | 636 | if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) |
99ce270a DA |
637 | *pipe = plane->pipe; |
638 | else | |
348abd4c | 639 | *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); |
99ce270a DA |
640 | |
641 | intel_display_power_put(dev_priv, power_domain, wakeref); | |
642 | ||
643 | return ret; | |
644 | } | |
645 | ||
646 | static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, | |
647 | u32 format, u64 modifier) | |
648 | { | |
e2b83294 ID |
649 | if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) |
650 | return false; | |
651 | ||
652 | return format == DRM_FORMAT_ARGB8888; | |
99ce270a DA |
653 | } |
654 | ||
655 | static int | |
656 | intel_legacy_cursor_update(struct drm_plane *_plane, | |
657 | struct drm_crtc *_crtc, | |
658 | struct drm_framebuffer *fb, | |
659 | int crtc_x, int crtc_y, | |
660 | unsigned int crtc_w, unsigned int crtc_h, | |
661 | u32 src_x, u32 src_y, | |
662 | u32 src_w, u32 src_h, | |
663 | struct drm_modeset_acquire_ctx *ctx) | |
664 | { | |
665 | struct intel_plane *plane = to_intel_plane(_plane); | |
666 | struct intel_crtc *crtc = to_intel_crtc(_crtc); | |
1de63528 | 667 | struct drm_i915_private *i915 = to_i915(plane->base.dev); |
99ce270a DA |
668 | struct intel_plane_state *old_plane_state = |
669 | to_intel_plane_state(plane->base.state); | |
670 | struct intel_plane_state *new_plane_state; | |
671 | struct intel_crtc_state *crtc_state = | |
672 | to_intel_crtc_state(crtc->base.state); | |
673 | struct intel_crtc_state *new_crtc_state; | |
1de63528 | 674 | struct intel_vblank_evade_ctx evade; |
99ce270a DA |
675 | int ret; |
676 | ||
677 | /* | |
678 | * When crtc is inactive or there is a modeset pending, | |
6bdab0e5 JRS |
679 | * wait for it to complete in the slowpath. |
680 | * PSR2 selective fetch also requires the slow path as | |
681 | * PSR2 plane and transcoder registers can only be updated during | |
682 | * vblank. | |
99ce270a DA |
683 | * |
684 | * FIXME bigjoiner fastpath would be good | |
685 | */ | |
52a90349 VS |
686 | if (!crtc_state->hw.active || |
687 | intel_crtc_needs_modeset(crtc_state) || | |
688 | intel_crtc_needs_fastset(crtc_state) || | |
689 | crtc_state->bigjoiner_pipes) | |
99ce270a DA |
690 | goto slow; |
691 | ||
692 | /* | |
693 | * Don't do an async update if there is an outstanding commit modifying | |
694 | * the plane. This prevents our async update's changes from getting | |
695 | * overridden by a previous synchronous update's state. | |
696 | */ | |
697 | if (old_plane_state->uapi.commit && | |
698 | !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) | |
699 | goto slow; | |
700 | ||
701 | /* | |
702 | * If any parameters change that may affect watermarks, | |
703 | * take the slowpath. Only changing fb or position should be | |
704 | * in the fastpath. | |
705 | */ | |
706 | if (old_plane_state->uapi.crtc != &crtc->base || | |
707 | old_plane_state->uapi.src_w != src_w || | |
708 | old_plane_state->uapi.src_h != src_h || | |
709 | old_plane_state->uapi.crtc_w != crtc_w || | |
710 | old_plane_state->uapi.crtc_h != crtc_h || | |
711 | !old_plane_state->uapi.fb != !fb) | |
712 | goto slow; | |
713 | ||
714 | new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base)); | |
715 | if (!new_plane_state) | |
716 | return -ENOMEM; | |
717 | ||
718 | new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base)); | |
719 | if (!new_crtc_state) { | |
720 | ret = -ENOMEM; | |
721 | goto out_free; | |
722 | } | |
723 | ||
724 | drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); | |
725 | ||
726 | new_plane_state->uapi.src_x = src_x; | |
727 | new_plane_state->uapi.src_y = src_y; | |
728 | new_plane_state->uapi.src_w = src_w; | |
729 | new_plane_state->uapi.src_h = src_h; | |
730 | new_plane_state->uapi.crtc_x = crtc_x; | |
731 | new_plane_state->uapi.crtc_y = crtc_y; | |
732 | new_plane_state->uapi.crtc_w = crtc_w; | |
733 | new_plane_state->uapi.crtc_h = crtc_h; | |
734 | ||
735 | intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc); | |
736 | ||
737 | ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, | |
738 | old_plane_state, new_plane_state); | |
739 | if (ret) | |
740 | goto out_free; | |
741 | ||
742 | ret = intel_plane_pin_fb(new_plane_state); | |
743 | if (ret) | |
744 | goto out_free; | |
745 | ||
746 | intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), | |
ef39826c | 747 | ORIGIN_CURSOR_UPDATE); |
99ce270a DA |
748 | intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), |
749 | to_intel_frontbuffer(new_plane_state->hw.fb), | |
750 | plane->frontbuffer_bit); | |
751 | ||
752 | /* Swap plane state */ | |
753 | plane->base.state = &new_plane_state->uapi; | |
754 | ||
755 | /* | |
756 | * We cannot swap crtc_state as it may be in use by an atomic commit or | |
757 | * page flip that's running simultaneously. If we swap crtc_state and | |
758 | * destroy the old state, we will cause a use-after-free there. | |
759 | * | |
760 | * Only update active_planes, which is needed for our internal | |
761 | * bookkeeping. Either value will do the right thing when updating | |
762 | * planes atomically. If the cursor was part of the atomic update then | |
763 | * we would have taken the slowpath. | |
764 | */ | |
765 | crtc_state->active_planes = new_crtc_state->active_planes; | |
766 | ||
1de63528 VS |
767 | intel_vblank_evade_init(crtc_state, crtc_state, &evade); |
768 | ||
769 | intel_psr_lock(crtc_state); | |
770 | ||
771 | if (!drm_WARN_ON(&i915->drm, drm_crtc_vblank_get(&crtc->base))) { | |
772 | /* | |
773 | * TODO: maybe check if we're still in PSR | |
774 | * and skip the vblank evasion entirely? | |
775 | */ | |
776 | intel_psr_wait_for_idle_locked(crtc_state); | |
777 | ||
778 | local_irq_disable(); | |
779 | ||
780 | intel_vblank_evade(&evade); | |
781 | ||
782 | drm_crtc_vblank_put(&crtc->base); | |
783 | } else { | |
784 | local_irq_disable(); | |
785 | } | |
0225a909 | 786 | |
8ac80733 VS |
787 | if (new_plane_state->uapi.visible) { |
788 | intel_plane_update_noarm(plane, crtc_state, new_plane_state); | |
789 | intel_plane_update_arm(plane, crtc_state, new_plane_state); | |
790 | } else { | |
791 | intel_plane_disable_arm(plane, crtc_state); | |
792 | } | |
99ce270a | 793 | |
0225a909 VS |
794 | local_irq_enable(); |
795 | ||
1de63528 VS |
796 | intel_psr_unlock(crtc_state); |
797 | ||
99ce270a DA |
798 | intel_plane_unpin_fb(old_plane_state); |
799 | ||
800 | out_free: | |
801 | if (new_crtc_state) | |
802 | intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); | |
803 | if (ret) | |
804 | intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); | |
805 | else | |
806 | intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); | |
807 | return ret; | |
808 | ||
809 | slow: | |
810 | return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, | |
811 | crtc_x, crtc_y, crtc_w, crtc_h, | |
812 | src_x, src_y, src_w, src_h, ctx); | |
813 | } | |
814 | ||
815 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
816 | .update_plane = intel_legacy_cursor_update, | |
817 | .disable_plane = drm_atomic_helper_disable_plane, | |
818 | .destroy = intel_plane_destroy, | |
819 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
820 | .atomic_destroy_state = intel_plane_destroy_state, | |
821 | .format_mod_supported = intel_cursor_format_mod_supported, | |
822 | }; | |
823 | ||
824 | struct intel_plane * | |
825 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, | |
826 | enum pipe pipe) | |
827 | { | |
828 | struct intel_plane *cursor; | |
829 | int ret, zpos; | |
e2b83294 | 830 | u64 *modifiers; |
99ce270a DA |
831 | |
832 | cursor = intel_plane_alloc(); | |
833 | if (IS_ERR(cursor)) | |
834 | return cursor; | |
835 | ||
836 | cursor->pipe = pipe; | |
837 | cursor->i9xx_plane = (enum i9xx_plane_id) pipe; | |
838 | cursor->id = PLANE_CURSOR; | |
839 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); | |
840 | ||
841 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
842 | cursor->max_stride = i845_cursor_max_stride; | |
8ac80733 VS |
843 | cursor->update_arm = i845_cursor_update_arm; |
844 | cursor->disable_arm = i845_cursor_disable_arm; | |
99ce270a DA |
845 | cursor->get_hw_state = i845_cursor_get_hw_state; |
846 | cursor->check_plane = i845_check_cursor; | |
847 | } else { | |
848 | cursor->max_stride = i9xx_cursor_max_stride; | |
8ac80733 VS |
849 | cursor->update_arm = i9xx_cursor_update_arm; |
850 | cursor->disable_arm = i9xx_cursor_disable_arm; | |
99ce270a DA |
851 | cursor->get_hw_state = i9xx_cursor_get_hw_state; |
852 | cursor->check_plane = i9xx_check_cursor; | |
853 | } | |
854 | ||
855 | cursor->cursor.base = ~0; | |
856 | cursor->cursor.cntl = ~0; | |
857 | ||
858 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
859 | cursor->cursor.size = ~0; | |
860 | ||
10a657dd | 861 | modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE); |
e2b83294 | 862 | |
99ce270a DA |
863 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
864 | 0, &intel_cursor_plane_funcs, | |
865 | intel_cursor_formats, | |
866 | ARRAY_SIZE(intel_cursor_formats), | |
e2b83294 | 867 | modifiers, |
99ce270a DA |
868 | DRM_PLANE_TYPE_CURSOR, |
869 | "cursor %c", pipe_name(pipe)); | |
e2b83294 ID |
870 | |
871 | kfree(modifiers); | |
872 | ||
99ce270a DA |
873 | if (ret) |
874 | goto fail; | |
875 | ||
005e9537 | 876 | if (DISPLAY_VER(dev_priv) >= 4) |
99ce270a DA |
877 | drm_plane_create_rotation_property(&cursor->base, |
878 | DRM_MODE_ROTATE_0, | |
879 | DRM_MODE_ROTATE_0 | | |
880 | DRM_MODE_ROTATE_180); | |
881 | ||
18e0deee | 882 | zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; |
99ce270a DA |
883 | drm_plane_create_zpos_immutable_property(&cursor->base, zpos); |
884 | ||
005e9537 | 885 | if (DISPLAY_VER(dev_priv) >= 12) |
99ce270a DA |
886 | drm_plane_enable_fb_damage_clips(&cursor->base); |
887 | ||
d372ba42 | 888 | intel_plane_helper_add(cursor); |
99ce270a DA |
889 | |
890 | return cursor; | |
891 | ||
892 | fail: | |
893 | intel_plane_free(cursor); | |
894 | ||
895 | return ERR_PTR(ret); | |
896 | } |