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drm/i915/guc: Expand guc_info debugfs with more information
[linux-block.git] / drivers / gpu / drm / i915 / display / intel_cdclk.c
CommitLineData
7ff89ca2
VS		 1/*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cd191546 24#include <linux/time.h>
cac91e67 25
fe4709a8 26#include "intel_atomic.h"
cac91e67 27#include "intel_bw.h"
e7674ef6 28#include "intel_cdclk.h"
1d455f8d 29#include "intel_display_types.h"
56c5098f 30#include "intel_sideband.h"
7ff89ca2
VS		 31
32/**
33 * DOC: CDCLK / RAWCLK
34 *
35 * The display engine uses several different clocks to do its work. There
36 * are two main clocks involved that aren't directly related to the actual
37 * pixel clock or any symbol/bit clock of the actual output port. These
38 * are the core display clock (CDCLK) and RAWCLK.
39 *
40 * CDCLK clocks most of the display pipe logic, and thus its frequency
41 * must be high enough to support the rate at which pixels are flowing
42 * through the pipes. Downscaling must also be accounted as that increases
43 * the effective pixel rate.
44 *
45 * On several platforms the CDCLK frequency can be changed dynamically
46 * to minimize power consumption for a given display configuration.
47 * Typically changes to the CDCLK frequency require all the display pipes
48 * to be shut down while the frequency is being changed.
49 *
50 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
51 * DMC will not change the active CDCLK frequency however, so that part
52 * will still be performed by the driver directly.
53 *
54 * RAWCLK is a fixed frequency clock, often used by various auxiliary
55 * blocks such as AUX CH or backlight PWM. Hence the only thing we
56 * really need to know about RAWCLK is its frequency so that various
57 * dividers can be programmed correctly.
58 */
59
49cd97a3 60static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 61 struct intel_cdclk_config *cdclk_config)
7ff89ca2 62{
0bb94e03 63 cdclk_config->cdclk = 133333;
7ff89ca2
VS		 64}
65
49cd97a3 66static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 67 struct intel_cdclk_config *cdclk_config)
7ff89ca2 68{
0bb94e03 69 cdclk_config->cdclk = 200000;
7ff89ca2
VS		 70}
71
49cd97a3 72static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 73 struct intel_cdclk_config *cdclk_config)
7ff89ca2 74{
0bb94e03 75 cdclk_config->cdclk = 266667;
7ff89ca2
VS		 76}
77
49cd97a3 78static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 79 struct intel_cdclk_config *cdclk_config)
7ff89ca2 80{
0bb94e03 81 cdclk_config->cdclk = 333333;
7ff89ca2
VS		 82}
83
49cd97a3 84static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 85 struct intel_cdclk_config *cdclk_config)
7ff89ca2 86{
0bb94e03 87 cdclk_config->cdclk = 400000;
7ff89ca2
VS		 88}
89
49cd97a3 90static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 91 struct intel_cdclk_config *cdclk_config)
7ff89ca2 92{
0bb94e03 93 cdclk_config->cdclk = 450000;
7ff89ca2
VS		 94}
95
49cd97a3 96static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 97 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 98{
99 struct pci_dev *pdev = dev_priv->drm.pdev;
100 u16 hpllcc = 0;
101
102 /*
103 * 852GM/852GMV only supports 133 MHz and the HPLLCC
104 * encoding is different :(
105 * FIXME is this the right way to detect 852GM/852GMV?
106 */
49cd97a3 107 if (pdev->revision == 0x1) {
0bb94e03 108 cdclk_config->cdclk = 133333;
49cd97a3
VS		 109 return;
110 }
7ff89ca2
VS		 111
112 pci_bus_read_config_word(pdev->bus,
113 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
114
115 /* Assume that the hardware is in the high speed state. This
116 * should be the default.
117 */
118 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
119 case GC_CLOCK_133_200:
120 case GC_CLOCK_133_200_2:
121 case GC_CLOCK_100_200:
0bb94e03 122 cdclk_config->cdclk = 200000;
49cd97a3 123 break;
7ff89ca2 124 case GC_CLOCK_166_250:
0bb94e03 125 cdclk_config->cdclk = 250000;
49cd97a3 126 break;
7ff89ca2 127 case GC_CLOCK_100_133:
0bb94e03 128 cdclk_config->cdclk = 133333;
49cd97a3 129 break;
7ff89ca2
VS		 130 case GC_CLOCK_133_266:
131 case GC_CLOCK_133_266_2:
132 case GC_CLOCK_166_266:
0bb94e03 133 cdclk_config->cdclk = 266667;
49cd97a3 134 break;
7ff89ca2 135 }
7ff89ca2
VS		 136}
137
49cd97a3 138static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 139 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 140{
141 struct pci_dev *pdev = dev_priv->drm.pdev;
142 u16 gcfgc = 0;
143
144 pci_read_config_word(pdev, GCFGC, &gcfgc);
145
49cd97a3 146 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
0bb94e03 147 cdclk_config->cdclk = 133333;
49cd97a3
VS		 148 return;
149 }
7ff89ca2
VS		 150
151 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
152 case GC_DISPLAY_CLOCK_333_320_MHZ:
0bb94e03 153 cdclk_config->cdclk = 333333;
49cd97a3 154 break;
7ff89ca2
VS		 155 default:
156 case GC_DISPLAY_CLOCK_190_200_MHZ:
0bb94e03 157 cdclk_config->cdclk = 190000;
49cd97a3 158 break;
7ff89ca2
VS		 159 }
160}
161
49cd97a3 162static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 163 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 164{
165 struct pci_dev *pdev = dev_priv->drm.pdev;
166 u16 gcfgc = 0;
167
168 pci_read_config_word(pdev, GCFGC, &gcfgc);
169
49cd97a3 170 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
0bb94e03 171 cdclk_config->cdclk = 133333;
49cd97a3
VS		 172 return;
173 }
7ff89ca2
VS		 174
175 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
176 case GC_DISPLAY_CLOCK_333_320_MHZ:
0bb94e03 177 cdclk_config->cdclk = 320000;
49cd97a3 178 break;
7ff89ca2
VS		 179 default:
180 case GC_DISPLAY_CLOCK_190_200_MHZ:
0bb94e03 181 cdclk_config->cdclk = 200000;
49cd97a3 182 break;
7ff89ca2
VS		 183 }
184}
185
186static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
187{
188 static const unsigned int blb_vco[8] = {
189 [0] = 3200000,
190 [1] = 4000000,
191 [2] = 5333333,
192 [3] = 4800000,
193 [4] = 6400000,
194 };
195 static const unsigned int pnv_vco[8] = {
196 [0] = 3200000,
197 [1] = 4000000,
198 [2] = 5333333,
199 [3] = 4800000,
200 [4] = 2666667,
201 };
202 static const unsigned int cl_vco[8] = {
203 [0] = 3200000,
204 [1] = 4000000,
205 [2] = 5333333,
206 [3] = 6400000,
207 [4] = 3333333,
208 [5] = 3566667,
209 [6] = 4266667,
210 };
211 static const unsigned int elk_vco[8] = {
212 [0] = 3200000,
213 [1] = 4000000,
214 [2] = 5333333,
215 [3] = 4800000,
216 };
217 static const unsigned int ctg_vco[8] = {
218 [0] = 3200000,
219 [1] = 4000000,
220 [2] = 5333333,
221 [3] = 6400000,
222 [4] = 2666667,
223 [5] = 4266667,
224 };
225 const unsigned int *vco_table;
226 unsigned int vco;
cbe974fb 227 u8 tmp = 0;
7ff89ca2
VS		 228
229 /* FIXME other chipsets? */
230 if (IS_GM45(dev_priv))
231 vco_table = ctg_vco;
6b9e441d 232 else if (IS_G45(dev_priv))
7ff89ca2
VS		 233 vco_table = elk_vco;
234 else if (IS_I965GM(dev_priv))
235 vco_table = cl_vco;
236 else if (IS_PINEVIEW(dev_priv))
237 vco_table = pnv_vco;
238 else if (IS_G33(dev_priv))
239 vco_table = blb_vco;
240 else
241 return 0;
242
3e9f55df
JN		 243 tmp = intel_de_read(dev_priv,
244 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7ff89ca2
VS		 245
246 vco = vco_table[tmp & 0x7];
247 if (vco == 0)
23194610
WK		 248 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
249 tmp);
7ff89ca2 250 else
23194610 251 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
7ff89ca2
VS		 252
253 return vco;
254}
255
49cd97a3 256static void g33_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 257 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 258{
259 struct pci_dev *pdev = dev_priv->drm.pdev;
cbe974fb
JN		 260 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
261 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
262 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
263 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
264 const u8 *div_table;
49cd97a3 265 unsigned int cdclk_sel;
cbe974fb 266 u16 tmp = 0;
7ff89ca2 267
0bb94e03 268 cdclk_config->vco = intel_hpll_vco(dev_priv);
49cd97a3 269
7ff89ca2
VS		 270 pci_read_config_word(pdev, GCFGC, &tmp);
271
272 cdclk_sel = (tmp >> 4) & 0x7;
273
274 if (cdclk_sel >= ARRAY_SIZE(div_3200))
275 goto fail;
276
0bb94e03 277 switch (cdclk_config->vco) {
7ff89ca2
VS		 278 case 3200000:
279 div_table = div_3200;
280 break;
281 case 4000000:
282 div_table = div_4000;
283 break;
284 case 4800000:
285 div_table = div_4800;
286 break;
287 case 5333333:
288 div_table = div_5333;
289 break;
290 default:
291 goto fail;
292 }
293
0bb94e03
VS		 294 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
295 div_table[cdclk_sel]);
49cd97a3 296 return;
7ff89ca2
VS		 297
298fail:
23194610
WK		 299 drm_err(&dev_priv->drm,
300 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
0bb94e03
VS		 301 cdclk_config->vco, tmp);
302 cdclk_config->cdclk = 190476;
7ff89ca2
VS		 303}
304
49cd97a3 305static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 306 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 307{
308 struct pci_dev *pdev = dev_priv->drm.pdev;
309 u16 gcfgc = 0;
310
311 pci_read_config_word(pdev, GCFGC, &gcfgc);
312
313 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
314 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
0bb94e03 315 cdclk_config->cdclk = 266667;
49cd97a3 316 break;
7ff89ca2 317 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
0bb94e03 318 cdclk_config->cdclk = 333333;
49cd97a3 319 break;
7ff89ca2 320 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
0bb94e03 321 cdclk_config->cdclk = 444444;
49cd97a3 322 break;
7ff89ca2 323 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
0bb94e03 324 cdclk_config->cdclk = 200000;
49cd97a3 325 break;
7ff89ca2 326 default:
23194610
WK		 327 drm_err(&dev_priv->drm,
328 "Unknown pnv display core clock 0x%04x\n", gcfgc);
f0d759f0 329 /* fall through */
7ff89ca2 330 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
0bb94e03 331 cdclk_config->cdclk = 133333;
49cd97a3 332 break;
7ff89ca2 333 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
0bb94e03 334 cdclk_config->cdclk = 166667;
49cd97a3 335 break;
7ff89ca2
VS		 336 }
337}
338
49cd97a3 339static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 340 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 341{
342 struct pci_dev *pdev = dev_priv->drm.pdev;
cbe974fb
JN		 343 static const u8 div_3200[] = { 16, 10, 8 };
344 static const u8 div_4000[] = { 20, 12, 10 };
345 static const u8 div_5333[] = { 24, 16, 14 };
346 const u8 *div_table;
49cd97a3 347 unsigned int cdclk_sel;
cbe974fb 348 u16 tmp = 0;
7ff89ca2 349
0bb94e03 350 cdclk_config->vco = intel_hpll_vco(dev_priv);
49cd97a3 351
7ff89ca2
VS		 352 pci_read_config_word(pdev, GCFGC, &tmp);
353
354 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
355
356 if (cdclk_sel >= ARRAY_SIZE(div_3200))
357 goto fail;
358
0bb94e03 359 switch (cdclk_config->vco) {
7ff89ca2
VS		 360 case 3200000:
361 div_table = div_3200;
362 break;
363 case 4000000:
364 div_table = div_4000;
365 break;
366 case 5333333:
367 div_table = div_5333;
368 break;
369 default:
370 goto fail;
371 }
372
0bb94e03
VS		 373 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
374 div_table[cdclk_sel]);
49cd97a3 375 return;
7ff89ca2
VS		 376
377fail:
23194610
WK		 378 drm_err(&dev_priv->drm,
379 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
0bb94e03
VS		 380 cdclk_config->vco, tmp);
381 cdclk_config->cdclk = 200000;
7ff89ca2
VS		 382}
383
49cd97a3 384static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 385 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 386{
387 struct pci_dev *pdev = dev_priv->drm.pdev;
49cd97a3 388 unsigned int cdclk_sel;
cbe974fb 389 u16 tmp = 0;
7ff89ca2 390
0bb94e03 391 cdclk_config->vco = intel_hpll_vco(dev_priv);
49cd97a3 392
7ff89ca2
VS		 393 pci_read_config_word(pdev, GCFGC, &tmp);
394
395 cdclk_sel = (tmp >> 12) & 0x1;
396
0bb94e03 397 switch (cdclk_config->vco) {
7ff89ca2
VS		 398 case 2666667:
399 case 4000000:
400 case 5333333:
0bb94e03 401 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
49cd97a3 402 break;
7ff89ca2 403 case 3200000:
0bb94e03 404 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
49cd97a3 405 break;
7ff89ca2 406 default:
23194610
WK		 407 drm_err(&dev_priv->drm,
408 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
0bb94e03
VS		 409 cdclk_config->vco, tmp);
410 cdclk_config->cdclk = 222222;
49cd97a3 411 break;
7ff89ca2
VS		 412 }
413}
414
49cd97a3 415static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 416 struct intel_cdclk_config *cdclk_config)
7ff89ca2 417{
3e9f55df 418 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
cbe974fb 419 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
7ff89ca2
VS		 420
421 if (lcpll & LCPLL_CD_SOURCE_FCLK)
0bb94e03 422 cdclk_config->cdclk = 800000;
3e9f55df 423 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
0bb94e03 424 cdclk_config->cdclk = 450000;
7ff89ca2 425 else if (freq == LCPLL_CLK_FREQ_450)
0bb94e03 426 cdclk_config->cdclk = 450000;
7ff89ca2 427 else if (IS_HSW_ULT(dev_priv))
0bb94e03 428 cdclk_config->cdclk = 337500;
7ff89ca2 429 else
0bb94e03 430 cdclk_config->cdclk = 540000;
7ff89ca2
VS		 431}
432
d305e061 433static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
7ff89ca2
VS		 434{
435 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
436 333333 : 320000;
7ff89ca2
VS		 437
438 /*
439 * We seem to get an unstable or solid color picture at 200MHz.
440 * Not sure what's wrong. For now use 200MHz only when all pipes
441 * are off.
442 */
d305e061 443 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
7ff89ca2 444 return 400000;
d305e061 445 else if (min_cdclk > 266667)
7ff89ca2 446 return freq_320;
d305e061 447 else if (min_cdclk > 0)
7ff89ca2
VS		 448 return 266667;
449 else
450 return 200000;
451}
452
999c5766
VS		 453static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
454{
455 if (IS_VALLEYVIEW(dev_priv)) {
456 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
457 return 2;
458 else if (cdclk >= 266667)
459 return 1;
460 else
461 return 0;
462 } else {
463 /*
464 * Specs are full of misinformation, but testing on actual
465 * hardware has shown that we just need to write the desired
466 * CCK divider into the Punit register.
467 */
468 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
469 }
470}
471
49cd97a3 472static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 473 struct intel_cdclk_config *cdclk_config)
7ff89ca2 474{
999c5766
VS		 475 u32 val;
476
337fa6e0
CW		 477 vlv_iosf_sb_get(dev_priv,
478 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
479
0bb94e03
VS		 480 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
481 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
482 CCK_DISPLAY_CLOCK_CONTROL,
483 cdclk_config->vco);
999c5766 484
c11b813f 485 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
337fa6e0
CW		 486
487 vlv_iosf_sb_put(dev_priv,
488 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
999c5766
VS		 489
490 if (IS_VALLEYVIEW(dev_priv))
0bb94e03 491 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
999c5766
VS		 492 DSPFREQGUAR_SHIFT;
493 else
0bb94e03 494 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
999c5766 495 DSPFREQGUAR_SHIFT_CHV;
7ff89ca2
VS		 496}
497
498static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
499{
500 unsigned int credits, default_credits;
501
502 if (IS_CHERRYVIEW(dev_priv))
503 default_credits = PFI_CREDIT(12);
504 else
505 default_credits = PFI_CREDIT(8);
506
49cd97a3 507 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
7ff89ca2
VS		 508 /* CHV suggested value is 31 or 63 */
509 if (IS_CHERRYVIEW(dev_priv))
510 credits = PFI_CREDIT_63;
511 else
512 credits = PFI_CREDIT(15);
513 } else {
514 credits = default_credits;
515 }
516
517 /*
518 * WA - write default credits before re-programming
519 * FIXME: should we also set the resend bit here?
520 */
3e9f55df
JN		 521 intel_de_write(dev_priv, GCI_CONTROL,
522 VGA_FAST_MODE_DISABLE | default_credits);
7ff89ca2 523
3e9f55df
JN		 524 intel_de_write(dev_priv, GCI_CONTROL,
525 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
7ff89ca2
VS		 526
527 /*
528 * FIXME is this guaranteed to clear
529 * immediately or should we poll for it?
530 */
aff35110
PB		 531 drm_WARN_ON(&dev_priv->drm,
532 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
7ff89ca2
VS		 533}
534
83c5fda7 535static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 536 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 537 enum pipe pipe)
7ff89ca2 538{
0bb94e03
VS		 539 int cdclk = cdclk_config->cdclk;
540 u32 val, cmd = cdclk_config->voltage_level;
0e6e0be4 541 intel_wakeref_t wakeref;
7ff89ca2 542
0c9f353f
VS		 543 switch (cdclk) {
544 case 400000:
545 case 333333:
546 case 320000:
547 case 266667:
548 case 200000:
549 break;
550 default:
551 MISSING_CASE(cdclk);
552 return;
553 }
554
886015a0
GKB		 555 /* There are cases where we can end up here with power domains
556 * off and a CDCLK frequency other than the minimum, like when
557 * issuing a modeset without actually changing any display after
13ce6092 558 * a system suspend. So grab the display core domain, which covers
886015a0
GKB		 559 * the HW blocks needed for the following programming.
560 */
13ce6092 561 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
886015a0 562
337fa6e0
CW		 563 vlv_iosf_sb_get(dev_priv,
564 BIT(VLV_IOSF_SB_CCK) |
565 BIT(VLV_IOSF_SB_BUNIT) |
566 BIT(VLV_IOSF_SB_PUNIT));
567
c11b813f 568 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
7ff89ca2
VS		 569 val &= ~DSPFREQGUAR_MASK;
570 val |= (cmd << DSPFREQGUAR_SHIFT);
c11b813f
VS		 571 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
572 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
7ff89ca2
VS		 573 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
574 50)) {
23194610
WK		 575 drm_err(&dev_priv->drm,
576 "timed out waiting for CDclk change\n");
7ff89ca2 577 }
7ff89ca2 578
7ff89ca2
VS		 579 if (cdclk == 400000) {
580 u32 divider;
581
582 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
583 cdclk) - 1;
584
585 /* adjust cdclk divider */
586 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
587 val &= ~CCK_FREQUENCY_VALUES;
588 val |= divider;
589 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
590
591 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
592 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
593 50))
23194610
WK		 594 drm_err(&dev_priv->drm,
595 "timed out waiting for CDclk change\n");
7ff89ca2
VS		 596 }
597
598 /* adjust self-refresh exit latency value */
599 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
600 val &= ~0x7f;
601
602 /*
603 * For high bandwidth configs, we set a higher latency in the bunit
604 * so that the core display fetch happens in time to avoid underruns.
605 */
606 if (cdclk == 400000)
607 val |= 4500 / 250; /* 4.5 usec */
608 else
609 val |= 3000 / 250; /* 3.0 usec */
610 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
611
221c7862 612 vlv_iosf_sb_put(dev_priv,
337fa6e0
CW		 613 BIT(VLV_IOSF_SB_CCK) |
614 BIT(VLV_IOSF_SB_BUNIT) |
615 BIT(VLV_IOSF_SB_PUNIT));
7ff89ca2
VS		 616
617 intel_update_cdclk(dev_priv);
1a5301a5
VS		 618
619 vlv_program_pfi_credits(dev_priv);
886015a0 620
13ce6092 621 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
7ff89ca2
VS		 622}
623
83c5fda7 624static void chv_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 625 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 626 enum pipe pipe)
7ff89ca2 627{
0bb94e03
VS		 628 int cdclk = cdclk_config->cdclk;
629 u32 val, cmd = cdclk_config->voltage_level;
0e6e0be4 630 intel_wakeref_t wakeref;
7ff89ca2 631
7ff89ca2
VS		 632 switch (cdclk) {
633 case 333333:
634 case 320000:
635 case 266667:
636 case 200000:
637 break;
638 default:
639 MISSING_CASE(cdclk);
640 return;
641 }
642
886015a0
GKB		 643 /* There are cases where we can end up here with power domains
644 * off and a CDCLK frequency other than the minimum, like when
645 * issuing a modeset without actually changing any display after
13ce6092 646 * a system suspend. So grab the display core domain, which covers
886015a0
GKB		 647 * the HW blocks needed for the following programming.
648 */
13ce6092 649 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
886015a0 650
337fa6e0 651 vlv_punit_get(dev_priv);
c11b813f 652 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
7ff89ca2
VS		 653 val &= ~DSPFREQGUAR_MASK_CHV;
654 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
c11b813f
VS		 655 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
656 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
7ff89ca2
VS		 657 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
658 50)) {
23194610
WK		 659 drm_err(&dev_priv->drm,
660 "timed out waiting for CDclk change\n");
7ff89ca2 661 }
337fa6e0
CW		 662
663 vlv_punit_put(dev_priv);
7ff89ca2
VS		 664
665 intel_update_cdclk(dev_priv);
1a5301a5
VS		 666
667 vlv_program_pfi_credits(dev_priv);
886015a0 668
13ce6092 669 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
7ff89ca2
VS		 670}
671
d305e061 672static int bdw_calc_cdclk(int min_cdclk)
7ff89ca2 673{
d305e061 674 if (min_cdclk > 540000)
7ff89ca2 675 return 675000;
d305e061 676 else if (min_cdclk > 450000)
7ff89ca2 677 return 540000;
d305e061 678 else if (min_cdclk > 337500)
7ff89ca2
VS		 679 return 450000;
680 else
681 return 337500;
682}
683
d7ffaeef
VS		 684static u8 bdw_calc_voltage_level(int cdclk)
685{
686 switch (cdclk) {
687 default:
688 case 337500:
689 return 2;
690 case 450000:
691 return 0;
692 case 540000:
693 return 1;
694 case 675000:
695 return 3;
696 }
697}
698
49cd97a3 699static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 700 struct intel_cdclk_config *cdclk_config)
7ff89ca2 701{
3e9f55df 702 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
cbe974fb 703 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
7ff89ca2
VS		 704
705 if (lcpll & LCPLL_CD_SOURCE_FCLK)
0bb94e03 706 cdclk_config->cdclk = 800000;
3e9f55df 707 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
0bb94e03 708 cdclk_config->cdclk = 450000;
7ff89ca2 709 else if (freq == LCPLL_CLK_FREQ_450)
0bb94e03 710 cdclk_config->cdclk = 450000;
7ff89ca2 711 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
0bb94e03 712 cdclk_config->cdclk = 540000;
7ff89ca2 713 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
0bb94e03 714 cdclk_config->cdclk = 337500;
7ff89ca2 715 else
0bb94e03 716 cdclk_config->cdclk = 675000;
d7ffaeef
VS		 717
718 /*
719 * Can't read this out :( Let's assume it's
720 * at least what the CDCLK frequency requires.
721 */
0bb94e03
VS		 722 cdclk_config->voltage_level =
723 bdw_calc_voltage_level(cdclk_config->cdclk);
7ff89ca2
VS		 724}
725
83c5fda7 726static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 727 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 728 enum pipe pipe)
7ff89ca2 729{
0bb94e03 730 int cdclk = cdclk_config->cdclk;
cbe974fb 731 u32 val;
7ff89ca2
VS		 732 int ret;
733
aff35110
PB		 734 if (drm_WARN(&dev_priv->drm,
735 (intel_de_read(dev_priv, LCPLL_CTL) &
736 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
737 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
738 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
739 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
740 "trying to change cdclk frequency with cdclk not enabled\n"))
7ff89ca2
VS		 741 return;
742
7ff89ca2
VS		 743 ret = sandybridge_pcode_write(dev_priv,
744 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
7ff89ca2 745 if (ret) {
23194610
WK		 746 drm_err(&dev_priv->drm,
747 "failed to inform pcode about cdclk change\n");
7ff89ca2
VS		 748 return;
749 }
750
3e9f55df 751 val = intel_de_read(dev_priv, LCPLL_CTL);
7ff89ca2 752 val |= LCPLL_CD_SOURCE_FCLK;
3e9f55df 753 intel_de_write(dev_priv, LCPLL_CTL, val);
7ff89ca2 754
3164888a
ML		 755 /*
756 * According to the spec, it should be enough to poll for this 1 us.
757 * However, extensive testing shows that this can take longer.
758 */
3e9f55df 759 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
3164888a 760 LCPLL_CD_SOURCE_FCLK_DONE, 100))
23194610 761 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
7ff89ca2 762
3e9f55df 763 val = intel_de_read(dev_priv, LCPLL_CTL);
7ff89ca2
VS		 764 val &= ~LCPLL_CLK_FREQ_MASK;
765
766 switch (cdclk) {
2b58417f
VS		 767 default:
768 MISSING_CASE(cdclk);
769 /* fall through */
770 case 337500:
771 val |= LCPLL_CLK_FREQ_337_5_BDW;
2b58417f 772 break;
7ff89ca2
VS		 773 case 450000:
774 val |= LCPLL_CLK_FREQ_450;
7ff89ca2
VS		 775 break;
776 case 540000:
777 val |= LCPLL_CLK_FREQ_54O_BDW;
7ff89ca2 778 break;
7ff89ca2
VS		 779 case 675000:
780 val |= LCPLL_CLK_FREQ_675_BDW;
7ff89ca2 781 break;
7ff89ca2
VS		 782 }
783
3e9f55df 784 intel_de_write(dev_priv, LCPLL_CTL, val);
7ff89ca2 785
3e9f55df 786 val = intel_de_read(dev_priv, LCPLL_CTL);
7ff89ca2 787 val &= ~LCPLL_CD_SOURCE_FCLK;
3e9f55df 788 intel_de_write(dev_priv, LCPLL_CTL, val);
7ff89ca2 789
3e9f55df
JN		 790 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
791 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
23194610 792 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
7ff89ca2 793
d7ffaeef 794 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
0bb94e03 795 cdclk_config->voltage_level);
7ff89ca2 796
3e9f55df
JN		 797 intel_de_write(dev_priv, CDCLK_FREQ,
798 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
7ff89ca2
VS		 799
800 intel_update_cdclk(dev_priv);
7ff89ca2
VS		 801}
802
d305e061 803static int skl_calc_cdclk(int min_cdclk, int vco)
7ff89ca2
VS		 804{
805 if (vco == 8640000) {
d305e061 806 if (min_cdclk > 540000)
7ff89ca2 807 return 617143;
d305e061 808 else if (min_cdclk > 432000)
7ff89ca2 809 return 540000;
d305e061 810 else if (min_cdclk > 308571)
7ff89ca2
VS		 811 return 432000;
812 else
813 return 308571;
814 } else {
d305e061 815 if (min_cdclk > 540000)
7ff89ca2 816 return 675000;
d305e061 817 else if (min_cdclk > 450000)
7ff89ca2 818 return 540000;
d305e061 819 else if (min_cdclk > 337500)
7ff89ca2
VS		 820 return 450000;
821 else
822 return 337500;
823 }
824}
825
2aa97491
VS		 826static u8 skl_calc_voltage_level(int cdclk)
827{
522d47cf 828 if (cdclk > 540000)
2aa97491 829 return 3;
522d47cf
LDM		 830 else if (cdclk > 450000)
831 return 2;
832 else if (cdclk > 337500)
833 return 1;
834 else
835 return 0;
2aa97491
VS		 836}
837
49cd97a3 838static void skl_dpll0_update(struct drm_i915_private *dev_priv,
0bb94e03 839 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 840{
841 u32 val;
842
0bb94e03
VS		 843 cdclk_config->ref = 24000;
844 cdclk_config->vco = 0;
7ff89ca2 845
3e9f55df 846 val = intel_de_read(dev_priv, LCPLL1_CTL);
7ff89ca2
VS		 847 if ((val & LCPLL_PLL_ENABLE) == 0)
848 return;
849
aff35110 850 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
7ff89ca2
VS		 851 return;
852
3e9f55df 853 val = intel_de_read(dev_priv, DPLL_CTRL1);
7ff89ca2 854
aff35110
PB		 855 if (drm_WARN_ON(&dev_priv->drm,
856 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
857 DPLL_CTRL1_SSC(SKL_DPLL0) |
858 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
859 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
7ff89ca2
VS		 860 return;
861
862 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
863 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
864 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
865 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
866 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
0bb94e03 867 cdclk_config->vco = 8100000;
7ff89ca2
VS		 868 break;
869 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
870 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
0bb94e03 871 cdclk_config->vco = 8640000;
7ff89ca2
VS		 872 break;
873 default:
874 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
875 break;
876 }
877}
878
49cd97a3 879static void skl_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 880 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 881{
882 u32 cdctl;
883
0bb94e03 884 skl_dpll0_update(dev_priv, cdclk_config);
7ff89ca2 885
0bb94e03 886 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
49cd97a3 887
0bb94e03 888 if (cdclk_config->vco == 0)
2aa97491 889 goto out;
7ff89ca2 890
3e9f55df 891 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
7ff89ca2 892
0bb94e03 893 if (cdclk_config->vco == 8640000) {
7ff89ca2
VS		 894 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
895 case CDCLK_FREQ_450_432:
0bb94e03 896 cdclk_config->cdclk = 432000;
49cd97a3 897 break;
7ff89ca2 898 case CDCLK_FREQ_337_308:
0bb94e03 899 cdclk_config->cdclk = 308571;
49cd97a3 900 break;
7ff89ca2 901 case CDCLK_FREQ_540:
0bb94e03 902 cdclk_config->cdclk = 540000;
49cd97a3 903 break;
7ff89ca2 904 case CDCLK_FREQ_675_617:
0bb94e03 905 cdclk_config->cdclk = 617143;
49cd97a3 906 break;
7ff89ca2
VS		 907 default:
908 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 909 break;
7ff89ca2
VS		 910 }
911 } else {
912 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
913 case CDCLK_FREQ_450_432:
0bb94e03 914 cdclk_config->cdclk = 450000;
49cd97a3 915 break;
7ff89ca2 916 case CDCLK_FREQ_337_308:
0bb94e03 917 cdclk_config->cdclk = 337500;
49cd97a3 918 break;
7ff89ca2 919 case CDCLK_FREQ_540:
0bb94e03 920 cdclk_config->cdclk = 540000;
49cd97a3 921 break;
7ff89ca2 922 case CDCLK_FREQ_675_617:
0bb94e03 923 cdclk_config->cdclk = 675000;
49cd97a3 924 break;
7ff89ca2
VS		 925 default:
926 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 927 break;
7ff89ca2
VS		 928 }
929 }
2aa97491
VS		 930
931 out:
932 /*
933 * Can't read this out :( Let's assume it's
934 * at least what the CDCLK frequency requires.
935 */
0bb94e03
VS		 936 cdclk_config->voltage_level =
937 skl_calc_voltage_level(cdclk_config->cdclk);
7ff89ca2
VS		 938}
939
940/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
941static int skl_cdclk_decimal(int cdclk)
942{
943 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
944}
945
946static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
947 int vco)
948{
949 bool changed = dev_priv->skl_preferred_vco_freq != vco;
950
951 dev_priv->skl_preferred_vco_freq = vco;
952
953 if (changed)
954 intel_update_max_cdclk(dev_priv);
955}
956
957static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
958{
7ff89ca2
VS		 959 u32 val;
960
aff35110 961 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
7ff89ca2 962
7ff89ca2
VS		 963 /*
964 * We always enable DPLL0 with the lowest link rate possible, but still
965 * taking into account the VCO required to operate the eDP panel at the
966 * desired frequency. The usual DP link rates operate with a VCO of
967 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
968 * The modeset code is responsible for the selection of the exact link
969 * rate later on, with the constraint of choosing a frequency that
970 * works with vco.
971 */
3e9f55df 972 val = intel_de_read(dev_priv, DPLL_CTRL1);
7ff89ca2
VS		 973
974 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
975 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
976 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
977 if (vco == 8640000)
978 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
979 SKL_DPLL0);
980 else
981 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
982 SKL_DPLL0);
983
3e9f55df
JN		 984 intel_de_write(dev_priv, DPLL_CTRL1, val);
985 intel_de_posting_read(dev_priv, DPLL_CTRL1);
7ff89ca2 986
3e9f55df
JN		 987 intel_de_write(dev_priv, LCPLL1_CTL,
988 intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE);
7ff89ca2 989
4cb3b44d 990 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
23194610 991 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
7ff89ca2 992
49cd97a3 993 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 994
995 /* We'll want to keep using the current vco from now on. */
996 skl_set_preferred_cdclk_vco(dev_priv, vco);
997}
998
999static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
1000{
3e9f55df
JN		 1001 intel_de_write(dev_priv, LCPLL1_CTL,
1002 intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
4cb3b44d 1003 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
23194610 1004 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
7ff89ca2 1005
49cd97a3 1006 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 1007}
1008
1009static void skl_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1010 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 1011 enum pipe pipe)
7ff89ca2 1012{
0bb94e03
VS		 1013 int cdclk = cdclk_config->cdclk;
1014 int vco = cdclk_config->vco;
53421c2f 1015 u32 freq_select, cdclk_ctl;
7ff89ca2
VS		 1016 int ret;
1017
602a9de5
ID		 1018 /*
1019 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1020 * unsupported on SKL. In theory this should never happen since only
1021 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1022 * supported on SKL either, see the above WA. WARN whenever trying to
1023 * use the corresponding VCO freq as that always leads to using the
1024 * minimum 308MHz CDCLK.
1025 */
aff35110
PB		 1026 drm_WARN_ON_ONCE(&dev_priv->drm,
1027 IS_SKYLAKE(dev_priv) && vco == 8640000);
602a9de5 1028
7ff89ca2
VS		 1029 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1030 SKL_CDCLK_PREPARE_FOR_CHANGE,
1031 SKL_CDCLK_READY_FOR_CHANGE,
1032 SKL_CDCLK_READY_FOR_CHANGE, 3);
7ff89ca2 1033 if (ret) {
23194610
WK		 1034 drm_err(&dev_priv->drm,
1035 "Failed to inform PCU about cdclk change (%d)\n", ret);
7ff89ca2
VS		 1036 return;
1037 }
1038
53421c2f 1039 /* Choose frequency for this cdclk */
7ff89ca2 1040 switch (cdclk) {
2b58417f 1041 default:
aff35110
PB		 1042 drm_WARN_ON(&dev_priv->drm,
1043 cdclk != dev_priv->cdclk.hw.bypass);
1044 drm_WARN_ON(&dev_priv->drm, vco != 0);
2b58417f
VS		 1045 /* fall through */
1046 case 308571:
1047 case 337500:
1048 freq_select = CDCLK_FREQ_337_308;
2b58417f 1049 break;
7ff89ca2
VS		 1050 case 450000:
1051 case 432000:
1052 freq_select = CDCLK_FREQ_450_432;
7ff89ca2
VS		 1053 break;
1054 case 540000:
1055 freq_select = CDCLK_FREQ_540;
7ff89ca2 1056 break;
7ff89ca2
VS		 1057 case 617143:
1058 case 675000:
1059 freq_select = CDCLK_FREQ_675_617;
7ff89ca2
VS		 1060 break;
1061 }
1062
49cd97a3
VS		 1063 if (dev_priv->cdclk.hw.vco != 0 &&
1064 dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1065 skl_dpll0_disable(dev_priv);
1066
3e9f55df 1067 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
53421c2f
LDM		 1068
1069 if (dev_priv->cdclk.hw.vco != vco) {
1070 /* Wa Display #1183: skl,kbl,cfl */
1071 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1072 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
3e9f55df 1073 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
53421c2f
LDM		 1074 }
1075
1076 /* Wa Display #1183: skl,kbl,cfl */
1077 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
3e9f55df
JN		 1078 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1079 intel_de_posting_read(dev_priv, CDCLK_CTL);
53421c2f 1080
49cd97a3 1081 if (dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1082 skl_dpll0_enable(dev_priv, vco);
1083
53421c2f
LDM		 1084 /* Wa Display #1183: skl,kbl,cfl */
1085 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
3e9f55df 1086 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
53421c2f
LDM		 1087
1088 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
3e9f55df 1089 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
53421c2f
LDM		 1090
1091 /* Wa Display #1183: skl,kbl,cfl */
1092 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
3e9f55df
JN		 1093 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1094 intel_de_posting_read(dev_priv, CDCLK_CTL);
7ff89ca2
VS		 1095
1096 /* inform PCU of the change */
2aa97491 1097 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
0bb94e03 1098 cdclk_config->voltage_level);
7ff89ca2
VS		 1099
1100 intel_update_cdclk(dev_priv);
1101}
1102
1103static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1104{
cbe974fb 1105 u32 cdctl, expected;
7ff89ca2
VS		 1106
1107 /*
1108 * check if the pre-os initialized the display
1109 * There is SWF18 scratchpad register defined which is set by the
1110 * pre-os which can be used by the OS drivers to check the status
1111 */
3e9f55df 1112 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
7ff89ca2
VS		 1113 goto sanitize;
1114
1115 intel_update_cdclk(dev_priv);
0bb94e03 1116 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
cfddadc9 1117
7ff89ca2 1118 /* Is PLL enabled and locked ? */
49cd97a3 1119 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1120 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1121 goto sanitize;
1122
1123 /* DPLL okay; verify the cdclock
1124 *
1125 * Noticed in some instances that the freq selection is correct but
1126 * decimal part is programmed wrong from BIOS where pre-os does not
1127 * enable display. Verify the same as well.
1128 */
3e9f55df 1129 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
7ff89ca2 1130 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
49cd97a3 1131 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
7ff89ca2
VS		 1132 if (cdctl == expected)
1133 /* All well; nothing to sanitize */
1134 return;
1135
1136sanitize:
23194610 1137 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
7ff89ca2
VS		 1138
1139 /* force cdclk programming */
49cd97a3 1140 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2 1141 /* force full PLL disable + enable */
49cd97a3 1142 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1143}
1144
ed645eee 1145static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1146{
0bb94e03 1147 struct intel_cdclk_config cdclk_config;
7ff89ca2
VS		 1148
1149 skl_sanitize_cdclk(dev_priv);
1150
49cd97a3
VS		 1151 if (dev_priv->cdclk.hw.cdclk != 0 &&
1152 dev_priv->cdclk.hw.vco != 0) {
7ff89ca2
VS		 1153 /*
1154 * Use the current vco as our initial
1155 * guess as to what the preferred vco is.
1156 */
1157 if (dev_priv->skl_preferred_vco_freq == 0)
1158 skl_set_preferred_cdclk_vco(dev_priv,
49cd97a3 1159 dev_priv->cdclk.hw.vco);
7ff89ca2
VS		 1160 return;
1161 }
1162
0bb94e03 1163 cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1164
0bb94e03
VS		 1165 cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1166 if (cdclk_config.vco == 0)
1167 cdclk_config.vco = 8100000;
1168 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1169 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
7ff89ca2 1170
0bb94e03 1171 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
7ff89ca2
VS		 1172}
1173
ed645eee 1174static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1175{
0bb94e03 1176 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1177
0bb94e03
VS		 1178 cdclk_config.cdclk = cdclk_config.bypass;
1179 cdclk_config.vco = 0;
1180 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
83c5fda7 1181
0bb94e03 1182 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
7ff89ca2
VS		 1183}
1184
736da811
MR		 1185static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1186 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1187 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1188 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1189 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1190 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1191 {}
1192};
1193
1194static const struct intel_cdclk_vals glk_cdclk_table[] = {
1195 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1196 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1197 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1198 {}
1199};
1200
1201static const struct intel_cdclk_vals cnl_cdclk_table[] = {
1202 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
1203 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
1204 { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
1205
1206 { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
1207 { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
1208 { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
1209 {}
1210};
1211
1212static const struct intel_cdclk_vals icl_cdclk_table[] = {
1213 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1214 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1215 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1216 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1217 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1218 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1219
1220 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1221 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1222 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1223 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1224 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1225 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1226
1227 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1228 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1229 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1230 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1231 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1232 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1233 {}
1234};
1235
1236static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1237{
1238 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1239 int i;
1240
1241 for (i = 0; table[i].refclk; i++)
1242 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1243 table[i].cdclk >= min_cdclk)
1244 return table[i].cdclk;
1245
aff35110
PB		 1246 drm_WARN(&dev_priv->drm, 1,
1247 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1248 min_cdclk, dev_priv->cdclk.hw.ref);
736da811 1249 return 0;
7ff89ca2
VS		 1250}
1251
736da811 1252static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
7ff89ca2 1253{
736da811
MR		 1254 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1255 int i;
1256
1257 if (cdclk == dev_priv->cdclk.hw.bypass)
1258 return 0;
1259
1260 for (i = 0; table[i].refclk; i++)
1261 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1262 table[i].cdclk == cdclk)
1263 return dev_priv->cdclk.hw.ref * table[i].ratio;
1264
aff35110
PB		 1265 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1266 cdclk, dev_priv->cdclk.hw.ref);
736da811 1267 return 0;
7ff89ca2
VS		 1268}
1269
2123f442
VS		 1270static u8 bxt_calc_voltage_level(int cdclk)
1271{
1272 return DIV_ROUND_UP(cdclk, 25000);
1273}
1274
71dc367e
MR		 1275static u8 cnl_calc_voltage_level(int cdclk)
1276{
1277 if (cdclk > 336000)
1278 return 2;
1279 else if (cdclk > 168000)
1280 return 1;
1281 else
1282 return 0;
1283}
1284
1285static u8 icl_calc_voltage_level(int cdclk)
1286{
1287 if (cdclk > 556800)
1288 return 2;
1289 else if (cdclk > 312000)
1290 return 1;
1291 else
1292 return 0;
1293}
1294
1295static u8 ehl_calc_voltage_level(int cdclk)
1296{
d1474838
MR		 1297 if (cdclk > 326400)
1298 return 3;
1299 else if (cdclk > 312000)
71dc367e
MR		 1300 return 2;
1301 else if (cdclk > 180000)
1302 return 1;
1303 else
1304 return 0;
1305}
1306
0fde0b1d
MR		 1307static u8 tgl_calc_voltage_level(int cdclk)
1308{
1309 if (cdclk > 556800)
1310 return 3;
1311 else if (cdclk > 326400)
1312 return 2;
1313 else if (cdclk > 312000)
1314 return 1;
1315 else
1316 return 0;
1317}
1318
71dc367e 1319static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
0bb94e03 1320 struct intel_cdclk_config *cdclk_config)
7ff89ca2 1321{
3e9f55df 1322 if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
0bb94e03 1323 cdclk_config->ref = 24000;
71dc367e 1324 else
0bb94e03 1325 cdclk_config->ref = 19200;
71dc367e 1326}
7ff89ca2 1327
71dc367e 1328static void icl_readout_refclk(struct drm_i915_private *dev_priv,
0bb94e03 1329 struct intel_cdclk_config *cdclk_config)
71dc367e 1330{
3e9f55df 1331 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
71dc367e
MR		 1332
1333 switch (dssm) {
1334 default:
1335 MISSING_CASE(dssm);
1336 /* fall through */
1337 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
0bb94e03 1338 cdclk_config->ref = 24000;
71dc367e
MR		 1339 break;
1340 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
0bb94e03 1341 cdclk_config->ref = 19200;
71dc367e
MR		 1342 break;
1343 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
0bb94e03 1344 cdclk_config->ref = 38400;
71dc367e
MR		 1345 break;
1346 }
1347}
1348
1349static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
0bb94e03 1350 struct intel_cdclk_config *cdclk_config)
71dc367e
MR		 1351{
1352 u32 val, ratio;
1353
1354 if (INTEL_GEN(dev_priv) >= 11)
0bb94e03 1355 icl_readout_refclk(dev_priv, cdclk_config);
71dc367e 1356 else if (IS_CANNONLAKE(dev_priv))
0bb94e03 1357 cnl_readout_refclk(dev_priv, cdclk_config);
71dc367e 1358 else
0bb94e03 1359 cdclk_config->ref = 19200;
7ff89ca2 1360
3e9f55df 1361 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
71dc367e
MR		 1362 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1363 (val & BXT_DE_PLL_LOCK) == 0) {
1364 /*
1365 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1366 * setting it to zero is a way to signal that.
1367 */
0bb94e03 1368 cdclk_config->vco = 0;
7ff89ca2 1369 return;
71dc367e 1370 }
7ff89ca2 1371
71dc367e
MR		 1372 /*
1373 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
1374 * it in a separate PLL control register.
1375 */
1376 if (INTEL_GEN(dev_priv) >= 10)
1377 ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
1378 else
3e9f55df 1379 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
7ff89ca2 1380
0bb94e03 1381 cdclk_config->vco = ratio * cdclk_config->ref;
7ff89ca2
VS		 1382}
1383
49cd97a3 1384static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1385 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 1386{
1387 u32 divider;
49cd97a3 1388 int div;
7ff89ca2 1389
0bb94e03 1390 bxt_de_pll_readout(dev_priv, cdclk_config);
74689ddf 1391
71dc367e 1392 if (INTEL_GEN(dev_priv) >= 12)
0bb94e03 1393 cdclk_config->bypass = cdclk_config->ref / 2;
71dc367e 1394 else if (INTEL_GEN(dev_priv) >= 11)
0bb94e03 1395 cdclk_config->bypass = 50000;
71dc367e 1396 else
0bb94e03 1397 cdclk_config->bypass = cdclk_config->ref;
49cd97a3 1398
0bb94e03
VS		 1399 if (cdclk_config->vco == 0) {
1400 cdclk_config->cdclk = cdclk_config->bypass;
2123f442 1401 goto out;
71dc367e 1402 }
7ff89ca2 1403
3e9f55df 1404 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7ff89ca2
VS		 1405
1406 switch (divider) {
1407 case BXT_CDCLK_CD2X_DIV_SEL_1:
1408 div = 2;
1409 break;
1410 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
aff35110
PB		 1411 drm_WARN(&dev_priv->drm,
1412 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1413 "Unsupported divider\n");
7ff89ca2
VS		 1414 div = 3;
1415 break;
1416 case BXT_CDCLK_CD2X_DIV_SEL_2:
1417 div = 4;
1418 break;
1419 case BXT_CDCLK_CD2X_DIV_SEL_4:
aff35110
PB		 1420 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
1421 "Unsupported divider\n");
7ff89ca2
VS		 1422 div = 8;
1423 break;
1424 default:
1425 MISSING_CASE(divider);
49cd97a3 1426 return;
7ff89ca2
VS		 1427 }
1428
0bb94e03 1429 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
2123f442
VS		 1430
1431 out:
1432 /*
1433 * Can't read this out :( Let's assume it's
1434 * at least what the CDCLK frequency requires.
1435 */
0bb94e03
VS		 1436 cdclk_config->voltage_level =
1437 dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
7ff89ca2
VS		 1438}
1439
1440static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1441{
3e9f55df 1442 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
7ff89ca2
VS		 1443
1444 /* Timeout 200us */
4cb3b44d
DCS		 1445 if (intel_de_wait_for_clear(dev_priv,
1446 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
23194610 1447 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
7ff89ca2 1448
49cd97a3 1449 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 1450}
1451
1452static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1453{
49cd97a3 1454 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
7ff89ca2
VS		 1455 u32 val;
1456
3e9f55df 1457 val = intel_de_read(dev_priv, BXT_DE_PLL_CTL);
7ff89ca2
VS		 1458 val &= ~BXT_DE_PLL_RATIO_MASK;
1459 val |= BXT_DE_PLL_RATIO(ratio);
3e9f55df 1460 intel_de_write(dev_priv, BXT_DE_PLL_CTL, val);
7ff89ca2 1461
3e9f55df 1462 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
7ff89ca2
VS		 1463
1464 /* Timeout 200us */
4cb3b44d
DCS		 1465 if (intel_de_wait_for_set(dev_priv,
1466 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
23194610 1467 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
7ff89ca2 1468
49cd97a3 1469 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 1470}
1471
1cbcd3b4
MR		 1472static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1473{
1474 u32 val;
1475
3e9f55df 1476 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1cbcd3b4 1477 val &= ~BXT_DE_PLL_PLL_ENABLE;
3e9f55df 1478 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1cbcd3b4
MR		 1479
1480 /* Timeout 200us */
3e9f55df 1481 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
23194610
WK		 1482 drm_err(&dev_priv->drm,
1483 "timeout waiting for CDCLK PLL unlock\n");
1cbcd3b4
MR		 1484
1485 dev_priv->cdclk.hw.vco = 0;
1486}
1487
1488static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1489{
1490 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1491 u32 val;
1492
1493 val = CNL_CDCLK_PLL_RATIO(ratio);
3e9f55df 1494 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1cbcd3b4
MR		 1495
1496 val |= BXT_DE_PLL_PLL_ENABLE;
3e9f55df 1497 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1cbcd3b4
MR		 1498
1499 /* Timeout 200us */
3e9f55df 1500 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
23194610
WK		 1501 drm_err(&dev_priv->drm,
1502 "timeout waiting for CDCLK PLL lock\n");
1cbcd3b4
MR		 1503
1504 dev_priv->cdclk.hw.vco = vco;
1505}
1506
0a12e437
VS		 1507static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1508{
1509 if (INTEL_GEN(dev_priv) >= 12) {
1510 if (pipe == INVALID_PIPE)
1511 return TGL_CDCLK_CD2X_PIPE_NONE;
1512 else
1513 return TGL_CDCLK_CD2X_PIPE(pipe);
1514 } else if (INTEL_GEN(dev_priv) >= 11) {
1515 if (pipe == INVALID_PIPE)
1516 return ICL_CDCLK_CD2X_PIPE_NONE;
1517 else
1518 return ICL_CDCLK_CD2X_PIPE(pipe);
1519 } else {
1520 if (pipe == INVALID_PIPE)
1521 return BXT_CDCLK_CD2X_PIPE_NONE;
1522 else
1523 return BXT_CDCLK_CD2X_PIPE(pipe);
1524 }
1525}
1526
8f0cfa4d 1527static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1528 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 1529 enum pipe pipe)
7ff89ca2 1530{
0bb94e03
VS		 1531 int cdclk = cdclk_config->cdclk;
1532 int vco = cdclk_config->vco;
7ff89ca2 1533 u32 val, divider;
8f0cfa4d 1534 int ret;
7ff89ca2 1535
1cbcd3b4
MR		 1536 /* Inform power controller of upcoming frequency change. */
1537 if (INTEL_GEN(dev_priv) >= 10)
1538 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1539 SKL_CDCLK_PREPARE_FOR_CHANGE,
1540 SKL_CDCLK_READY_FOR_CHANGE,
1541 SKL_CDCLK_READY_FOR_CHANGE, 3);
1542 else
1543 /*
1544 * BSpec requires us to wait up to 150usec, but that leads to
1545 * timeouts; the 2ms used here is based on experiment.
1546 */
1547 ret = sandybridge_pcode_write_timeout(dev_priv,
1548 HSW_PCODE_DE_WRITE_FREQ_REQ,
1549 0x80000000, 150, 2);
1550
1551 if (ret) {
23194610
WK		 1552 drm_err(&dev_priv->drm,
1553 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1554 ret, cdclk);
1cbcd3b4
MR		 1555 return;
1556 }
1557
7ff89ca2
VS		 1558 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1559 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
2b58417f 1560 default:
aff35110
PB		 1561 drm_WARN_ON(&dev_priv->drm,
1562 cdclk != dev_priv->cdclk.hw.bypass);
1563 drm_WARN_ON(&dev_priv->drm, vco != 0);
2b58417f
VS		 1564 /* fall through */
1565 case 2:
1566 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
7ff89ca2
VS		 1567 break;
1568 case 3:
aff35110
PB		 1569 drm_WARN(&dev_priv->drm,
1570 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1571 "Unsupported divider\n");
7ff89ca2
VS		 1572 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1573 break;
2b58417f
VS		 1574 case 4:
1575 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
7ff89ca2 1576 break;
2b58417f 1577 case 8:
aff35110
PB		 1578 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10,
1579 "Unsupported divider\n");
2b58417f 1580 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
7ff89ca2
VS		 1581 break;
1582 }
1583
1cbcd3b4
MR		 1584 if (INTEL_GEN(dev_priv) >= 10) {
1585 if (dev_priv->cdclk.hw.vco != 0 &&
1586 dev_priv->cdclk.hw.vco != vco)
1587 cnl_cdclk_pll_disable(dev_priv);
7ff89ca2 1588
1cbcd3b4
MR		 1589 if (dev_priv->cdclk.hw.vco != vco)
1590 cnl_cdclk_pll_enable(dev_priv, vco);
7ff89ca2 1591
1cbcd3b4
MR		 1592 } else {
1593 if (dev_priv->cdclk.hw.vco != 0 &&
1594 dev_priv->cdclk.hw.vco != vco)
1595 bxt_de_pll_disable(dev_priv);
1596
1597 if (dev_priv->cdclk.hw.vco != vco)
1598 bxt_de_pll_enable(dev_priv, vco);
1599 }
7ff89ca2 1600
0a12e437
VS		 1601 val = divider | skl_cdclk_decimal(cdclk) |
1602 bxt_cdclk_cd2x_pipe(dev_priv, pipe);
1cbcd3b4 1603
7ff89ca2
VS		 1604 /*
1605 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1606 * enable otherwise.
1607 */
1cbcd3b4 1608 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000)
7ff89ca2 1609 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
3e9f55df 1610 intel_de_write(dev_priv, CDCLK_CTL, val);
7ff89ca2 1611
59f9e9ca
VS		 1612 if (pipe != INVALID_PIPE)
1613 intel_wait_for_vblank(dev_priv, pipe);
1614
1cbcd3b4
MR		 1615 if (INTEL_GEN(dev_priv) >= 10) {
1616 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
0bb94e03 1617 cdclk_config->voltage_level);
1cbcd3b4
MR		 1618 } else {
1619 /*
1620 * The timeout isn't specified, the 2ms used here is based on
1621 * experiment.
1622 * FIXME: Waiting for the request completion could be delayed
1623 * until the next PCODE request based on BSpec.
1624 */
1625 ret = sandybridge_pcode_write_timeout(dev_priv,
1626 HSW_PCODE_DE_WRITE_FREQ_REQ,
0bb94e03 1627 cdclk_config->voltage_level,
1cbcd3b4
MR		 1628 150, 2);
1629 }
1630
7ff89ca2 1631 if (ret) {
23194610
WK		 1632 drm_err(&dev_priv->drm,
1633 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
1634 ret, cdclk);
7ff89ca2
VS		 1635 return;
1636 }
1637
1638 intel_update_cdclk(dev_priv);
1cbcd3b4
MR		 1639
1640 if (INTEL_GEN(dev_priv) >= 10)
1641 /*
1642 * Can't read out the voltage level :(
1643 * Let's just assume everything is as expected.
1644 */
0bb94e03 1645 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
7ff89ca2
VS		 1646}
1647
1648static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1649{
1650 u32 cdctl, expected;
8f9f717d 1651 int cdclk, vco;
7ff89ca2
VS		 1652
1653 intel_update_cdclk(dev_priv);
0bb94e03 1654 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
7ff89ca2 1655
49cd97a3 1656 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1657 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1658 goto sanitize;
1659
1660 /* DPLL okay; verify the cdclock
1661 *
1662 * Some BIOS versions leave an incorrect decimal frequency value and
1663 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1664 * so sanitize this register.
1665 */
3e9f55df 1666 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
7ff89ca2
VS		 1667 /*
1668 * Let's ignore the pipe field, since BIOS could have configured the
1669 * dividers both synching to an active pipe, or asynchronously
1670 * (PIPE_NONE).
1671 */
0a12e437 1672 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
7ff89ca2 1673
8f9f717d
MR		 1674 /* Make sure this is a legal cdclk value for the platform */
1675 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
1676 if (cdclk != dev_priv->cdclk.hw.cdclk)
1677 goto sanitize;
1678
1679 /* Make sure the VCO is correct for the cdclk */
1680 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
1681 if (vco != dev_priv->cdclk.hw.vco)
1682 goto sanitize;
1683
1684 expected = skl_cdclk_decimal(cdclk);
1685
1686 /* Figure out what CD2X divider we should be using for this cdclk */
1687 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
1688 dev_priv->cdclk.hw.cdclk)) {
1689 case 2:
1690 expected |= BXT_CDCLK_CD2X_DIV_SEL_1;
1691 break;
1692 case 3:
1693 expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5;
1694 break;
1695 case 4:
1696 expected |= BXT_CDCLK_CD2X_DIV_SEL_2;
1697 break;
1698 case 8:
1699 expected |= BXT_CDCLK_CD2X_DIV_SEL_4;
1700 break;
1701 default:
1702 goto sanitize;
1703 }
1704
7ff89ca2
VS		 1705 /*
1706 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1707 * enable otherwise.
1708 */
5dac256b 1709 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)
7ff89ca2
VS		 1710 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1711
1712 if (cdctl == expected)
1713 /* All well; nothing to sanitize */
1714 return;
1715
1716sanitize:
23194610 1717 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
7ff89ca2
VS		 1718
1719 /* force cdclk programming */
49cd97a3 1720 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2
VS		 1721
1722 /* force full PLL disable + enable */
49cd97a3 1723 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1724}
1725
ed645eee 1726static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1727{
0bb94e03 1728 struct intel_cdclk_config cdclk_config;
7ff89ca2
VS		 1729
1730 bxt_sanitize_cdclk(dev_priv);
1731
49cd97a3
VS		 1732 if (dev_priv->cdclk.hw.cdclk != 0 &&
1733 dev_priv->cdclk.hw.vco != 0)
7ff89ca2
VS		 1734 return;
1735
0bb94e03 1736 cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1737
7ff89ca2
VS		 1738 /*
1739 * FIXME:
1740 * - The initial CDCLK needs to be read from VBT.
1741 * Need to make this change after VBT has changes for BXT.
1742 */
0bb94e03
VS		 1743 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
1744 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
1745 cdclk_config.voltage_level =
1746 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
7ff89ca2 1747
0bb94e03 1748 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
7ff89ca2
VS		 1749}
1750
ed645eee 1751static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1752{
0bb94e03 1753 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1754
0bb94e03
VS		 1755 cdclk_config.cdclk = cdclk_config.bypass;
1756 cdclk_config.vco = 0;
1757 cdclk_config.voltage_level =
1758 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
83c5fda7 1759
0bb94e03 1760 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
49cd97a3
VS		 1761}
1762
93a643f2 1763/**
ed645eee 1764 * intel_cdclk_init_hw - Initialize CDCLK hardware
93a643f2
JN		 1765 * @i915: i915 device
1766 *
1767 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1768 * sanitizing the state of the hardware if needed. This is generally done only
1769 * during the display core initialization sequence, after which the DMC will
1770 * take care of turning CDCLK off/on as needed.
1771 */
ed645eee 1772void intel_cdclk_init_hw(struct drm_i915_private *i915)
93a643f2 1773{
0c1279b5 1774 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
ed645eee 1775 bxt_cdclk_init_hw(i915);
93a643f2 1776 else if (IS_GEN9_BC(i915))
ed645eee 1777 skl_cdclk_init_hw(i915);
93a643f2
JN		 1778}
1779
1780/**
ed645eee 1781 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
93a643f2
JN		 1782 * @i915: i915 device
1783 *
1784 * Uninitialize CDCLK. This is done only during the display core
1785 * uninitialization sequence.
1786 */
ed645eee 1787void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
93a643f2 1788{
751a93a1 1789 if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
ed645eee 1790 bxt_cdclk_uninit_hw(i915);
93a643f2 1791 else if (IS_GEN9_BC(i915))
ed645eee 1792 skl_cdclk_uninit_hw(i915);
93a643f2
JN		 1793}
1794
49cd97a3 1795/**
0bb94e03
VS		 1796 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
1797 * configurations requires a modeset on all pipes
1798 * @a: first CDCLK configuration
1799 * @b: second CDCLK configuration
49cd97a3
VS		 1800 *
1801 * Returns:
0bb94e03
VS		 1802 * True if changing between the two CDCLK configurations
1803 * requires all pipes to be off, false if not.
49cd97a3 1804 */
0bb94e03
VS		 1805bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
1806 const struct intel_cdclk_config *b)
49cd97a3 1807{
64600bd5
VS		 1808 return a->cdclk != b->cdclk ||
1809 a->vco != b->vco ||
1810 a->ref != b->ref;
1811}
1812
59f9e9ca 1813/**
0bb94e03
VS		 1814 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
1815 * configurations requires only a cd2x divider update
1816 * @dev_priv: i915 device
1817 * @a: first CDCLK configuration
1818 * @b: second CDCLK configuration
59f9e9ca
VS		 1819 *
1820 * Returns:
0bb94e03
VS		 1821 * True if changing between the two CDCLK configurations
1822 * can be done with just a cd2x divider update, false if not.
59f9e9ca 1823 */
65c88a86 1824static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
0bb94e03
VS		 1825 const struct intel_cdclk_config *a,
1826 const struct intel_cdclk_config *b)
59f9e9ca
VS		 1827{
1828 /* Older hw doesn't have the capability */
1829 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
1830 return false;
1831
1832 return a->cdclk != b->cdclk &&
1833 a->vco == b->vco &&
1834 a->ref == b->ref;
1835}
1836
64600bd5 1837/**
0bb94e03
VS		 1838 * intel_cdclk_changed - Determine if two CDCLK configurations are different
1839 * @a: first CDCLK configuration
1840 * @b: second CDCLK configuration
64600bd5
VS		 1841 *
1842 * Returns:
0bb94e03 1843 * True if the CDCLK configurations don't match, false if they do.
64600bd5 1844 */
0bb94e03
VS		 1845static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
1846 const struct intel_cdclk_config *b)
64600bd5
VS		 1847{
1848 return intel_cdclk_needs_modeset(a, b) ||
1849 a->voltage_level != b->voltage_level;
7ff89ca2
VS		 1850}
1851
0bb94e03
VS		 1852void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
1853 const char *context)
cfddadc9 1854{
b6c51c3e 1855 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
0bb94e03
VS		 1856 context, cdclk_config->cdclk, cdclk_config->vco,
1857 cdclk_config->ref, cdclk_config->bypass,
1858 cdclk_config->voltage_level);
cfddadc9
VS		 1859}
1860
b0587e4d 1861/**
0bb94e03 1862 * intel_set_cdclk - Push the CDCLK configuration to the hardware
b0587e4d 1863 * @dev_priv: i915 device
0bb94e03 1864 * @cdclk_config: new CDCLK configuration
59f9e9ca 1865 * @pipe: pipe with which to synchronize the update
b0587e4d
VS		 1866 *
1867 * Program the hardware based on the passed in CDCLK state,
1868 * if necessary.
1869 */
59f9e9ca 1870static void intel_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1871 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 1872 enum pipe pipe)
b0587e4d 1873{
bb9ca240
VS		 1874 struct intel_encoder *encoder;
1875
0bb94e03 1876 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
b0587e4d
VS		 1877 return;
1878
aff35110 1879 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
b0587e4d
VS		 1880 return;
1881
0bb94e03 1882 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
b0587e4d 1883
bb9ca240
VS		 1884 /*
1885 * Lock aux/gmbus while we change cdclk in case those
1886 * functions use cdclk. Not all platforms/ports do,
1887 * but we'll lock them all for simplicity.
1888 */
1889 mutex_lock(&dev_priv->gmbus_mutex);
1890 for_each_intel_dp(&dev_priv->drm, encoder) {
1891 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1892
1893 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
1894 &dev_priv->gmbus_mutex);
1895 }
1896
0bb94e03 1897 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
cfddadc9 1898
bb9ca240
VS		 1899 for_each_intel_dp(&dev_priv->drm, encoder) {
1900 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1901
1902 mutex_unlock(&intel_dp->aux.hw_mutex);
1903 }
1904 mutex_unlock(&dev_priv->gmbus_mutex);
1905
aff35110
PB		 1906 if (drm_WARN(&dev_priv->drm,
1907 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
1908 "cdclk state doesn't match!\n")) {
0bb94e03
VS		 1909 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
1910 intel_dump_cdclk_config(cdclk_config, "[sw state]");
cfddadc9 1911 }
b0587e4d
VS		 1912}
1913
59f9e9ca 1914/**
5604e9ce
VS		 1915 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
1916 * @state: intel atomic state
59f9e9ca 1917 *
5604e9ce
VS		 1918 * Program the hardware before updating the HW plane state based on the
1919 * new CDCLK state, if necessary.
59f9e9ca
VS		 1920 */
1921void
5604e9ce 1922intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
59f9e9ca 1923{
5604e9ce 1924 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
28a30b45
VS		 1925 const struct intel_cdclk_state *old_cdclk_state =
1926 intel_atomic_get_old_cdclk_state(state);
1927 const struct intel_cdclk_state *new_cdclk_state =
1928 intel_atomic_get_new_cdclk_state(state);
4c029c49 1929 enum pipe pipe = new_cdclk_state->pipe;
5604e9ce 1930
28a30b45
VS		 1931 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1932 &new_cdclk_state->actual))
1933 return;
1934
1965de63 1935 if (pipe == INVALID_PIPE ||
28a30b45 1936 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
aff35110 1937 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
28a30b45 1938
1965de63 1939 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
28a30b45 1940 }
59f9e9ca
VS		 1941}
1942
1943/**
5604e9ce
VS		 1944 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
1945 * @state: intel atomic state
59f9e9ca 1946 *
0b02f97f 1947 * Program the hardware after updating the HW plane state based on the
5604e9ce 1948 * new CDCLK state, if necessary.
59f9e9ca
VS		 1949 */
1950void
5604e9ce 1951intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
59f9e9ca 1952{
5604e9ce 1953 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
28a30b45
VS		 1954 const struct intel_cdclk_state *old_cdclk_state =
1955 intel_atomic_get_old_cdclk_state(state);
1956 const struct intel_cdclk_state *new_cdclk_state =
1957 intel_atomic_get_new_cdclk_state(state);
4c029c49 1958 enum pipe pipe = new_cdclk_state->pipe;
5604e9ce 1959
28a30b45
VS		 1960 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1961 &new_cdclk_state->actual))
1962 return;
1963
1965de63 1964 if (pipe != INVALID_PIPE &&
28a30b45 1965 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
aff35110 1966 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
28a30b45 1967
1965de63 1968 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
28a30b45 1969 }
59f9e9ca
VS		 1970}
1971
3e30d708 1972static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
d305e061 1973{
2225f3c6 1974 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3e30d708
VS		 1975 int pixel_rate = crtc_state->pixel_rate;
1976
42882336 1977 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 1978 return DIV_ROUND_UP(pixel_rate, 2);
cf819eff 1979 else if (IS_GEN(dev_priv, 9) ||
d305e061
VS		 1980 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1981 return pixel_rate;
1982 else if (IS_CHERRYVIEW(dev_priv))
1983 return DIV_ROUND_UP(pixel_rate * 100, 95);
3e30d708
VS		 1984 else if (crtc_state->double_wide)
1985 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
d305e061
VS		 1986 else
1987 return DIV_ROUND_UP(pixel_rate * 100, 90);
1988}
1989
bb6ae9e6
VS		 1990static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
1991{
2225f3c6 1992 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
bb6ae9e6
VS		 1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1994 struct intel_plane *plane;
1995 int min_cdclk = 0;
1996
1997 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1998 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
1999
2000 return min_cdclk;
2001}
2002
d305e061 2003int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
7ff89ca2
VS		 2004{
2005 struct drm_i915_private *dev_priv =
2225f3c6 2006 to_i915(crtc_state->uapi.crtc->dev);
d305e061
VS		 2007 int min_cdclk;
2008
1326a92c 2009 if (!crtc_state->hw.enable)
d305e061
VS		 2010 return 0;
2011
3e30d708 2012 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
7ff89ca2
VS		 2013
2014 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
24f28450 2015 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
d305e061 2016 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
7ff89ca2 2017
78cfa580
PD		 2018 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2019 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2020 * there may be audio corruption or screen corruption." This cdclk
d305e061 2021 * restriction for GLK is 316.8 MHz.
7ff89ca2
VS		 2022 */
2023 if (intel_crtc_has_dp_encoder(crtc_state) &&
2024 crtc_state->has_audio &&
2025 crtc_state->port_clock >= 540000 &&
78cfa580 2026 crtc_state->lane_count == 4) {
d305e061
VS		 2027 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2028 /* Display WA #1145: glk,cnl */
2029 min_cdclk = max(316800, min_cdclk);
cf819eff 2030 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
d305e061
VS		 2031 /* Display WA #1144: skl,bxt */
2032 min_cdclk = max(432000, min_cdclk);
2033 }
78cfa580 2034 }
7ff89ca2 2035
904e1b1f
AK		 2036 /*
2037 * According to BSpec, "The CD clock frequency must be at least twice
8cbeb06d 2038 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
8cbeb06d 2039 */
905801fe 2040 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
d305e061 2041 min_cdclk = max(2 * 96000, min_cdclk);
8cbeb06d 2042
bffb31f7
VS		 2043 /*
2044 * "For DP audio configuration, cdclk frequency shall be set to
2045 * meet the following requirements:
2046 * DP Link Frequency(MHz) | Cdclk frequency(MHz)
2047 * 270 | 320 or higher
2048 * 162 | 200 or higher"
2049 */
2050 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2051 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2052 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2053
c8dae55a
HG		 2054 /*
2055 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2056 * than 320000KHz.
2057 */
2058 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2059 IS_VALLEYVIEW(dev_priv))
2060 min_cdclk = max(320000, min_cdclk);
2061
beb29980
SL		 2062 /*
2063 * On Geminilake once the CDCLK gets as low as 79200
2064 * picture gets unstable, despite that values are
2065 * correct for DSI PLL and DE PLL.
2066 */
2067 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2068 IS_GEMINILAKE(dev_priv))
2069 min_cdclk = max(158400, min_cdclk);
2070
bb6ae9e6
VS		 2071 /* Account for additional needs from the planes */
2072 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2073
46d53e27
SL		 2074 /*
2075 * HACK. Currently for TGL platforms we calculate
2076 * min_cdclk initially based on pixel_rate divided
2077 * by 2, accounting for also plane requirements,
2078 * however in some cases the lowest possible CDCLK
2079 * doesn't work and causing the underruns.
2080 * Explicitly stating here that this seems to be currently
2081 * rather a Hack, than final solution.
2082 */
2083 if (IS_TIGERLAKE(dev_priv))
2084 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
2085
9c61de4c 2086 if (min_cdclk > dev_priv->max_cdclk_freq) {
23194610
WK		 2087 drm_dbg_kms(&dev_priv->drm,
2088 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2089 min_cdclk, dev_priv->max_cdclk_freq);
9c61de4c
VS		 2090 return -EINVAL;
2091 }
2092
d305e061 2093 return min_cdclk;
7ff89ca2
VS		 2094}
2095
28a30b45 2096static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2097{
28a30b45 2098 struct intel_atomic_state *state = cdclk_state->base.state;
19aefbc7
SL		 2099 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2100 struct intel_bw_state *bw_state = NULL;
d305e061 2101 struct intel_crtc *crtc;
7ff89ca2 2102 struct intel_crtc_state *crtc_state;
9c61de4c 2103 int min_cdclk, i;
19aefbc7 2104 enum pipe pipe;
7ff89ca2 2105
8b67896e 2106 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1d5a95b5
VS		 2107 int ret;
2108
9c61de4c
VS		 2109 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2110 if (min_cdclk < 0)
2111 return min_cdclk;
2112
19aefbc7
SL		 2113 bw_state = intel_atomic_get_bw_state(state);
2114 if (IS_ERR(bw_state))
2115 return PTR_ERR(bw_state);
2116
1965de63 2117 if (cdclk_state->min_cdclk[i] == min_cdclk)
1d5a95b5
VS		 2118 continue;
2119
1965de63 2120 cdclk_state->min_cdclk[i] = min_cdclk;
1d5a95b5 2121
28a30b45 2122 ret = intel_atomic_lock_global_state(&cdclk_state->base);
1d5a95b5
VS		 2123 if (ret)
2124 return ret;
9c61de4c 2125 }
7ff89ca2 2126
1965de63 2127 min_cdclk = cdclk_state->force_min_cdclk;
19aefbc7
SL		 2128 for_each_pipe(dev_priv, pipe) {
2129 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
cd191546 2130
19aefbc7
SL		 2131 if (!bw_state)
2132 continue;
cd191546
SL		 2133
2134 min_cdclk = max(bw_state->min_cdclk, min_cdclk);
2135 }
7ff89ca2 2136
d305e061 2137 return min_cdclk;
7ff89ca2
VS		 2138}
2139
53e9bf5e 2140/*
933122cc
VS		 2141 * Account for port clock min voltage level requirements.
2142 * This only really does something on CNL+ but can be
2143 * called on earlier platforms as well.
2144 *
53e9bf5e
VS		 2145 * Note that this functions assumes that 0 is
2146 * the lowest voltage value, and higher values
2147 * correspond to increasingly higher voltages.
2148 *
2149 * Should that relationship no longer hold on
2150 * future platforms this code will need to be
2151 * adjusted.
2152 */
28a30b45 2153static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
53e9bf5e 2154{
28a30b45 2155 struct intel_atomic_state *state = cdclk_state->base.state;
53e9bf5e
VS		 2156 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2157 struct intel_crtc *crtc;
2158 struct intel_crtc_state *crtc_state;
2159 u8 min_voltage_level;
2160 int i;
2161 enum pipe pipe;
2162
53e9bf5e 2163 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1d5a95b5
VS		 2164 int ret;
2165
1326a92c 2166 if (crtc_state->hw.enable)
1d5a95b5 2167 min_voltage_level = crtc_state->min_voltage_level;
53e9bf5e 2168 else
1d5a95b5
VS		 2169 min_voltage_level = 0;
2170
1965de63 2171 if (cdclk_state->min_voltage_level[i] == min_voltage_level)
1d5a95b5
VS		 2172 continue;
2173
1965de63 2174 cdclk_state->min_voltage_level[i] = min_voltage_level;
1d5a95b5 2175
28a30b45 2176 ret = intel_atomic_lock_global_state(&cdclk_state->base);
1d5a95b5
VS		 2177 if (ret)
2178 return ret;
53e9bf5e
VS		 2179 }
2180
2181 min_voltage_level = 0;
2182 for_each_pipe(dev_priv, pipe)
1965de63 2183 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
53e9bf5e
VS		 2184 min_voltage_level);
2185
2186 return min_voltage_level;
2187}
2188
28a30b45 2189static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2190{
28a30b45 2191 struct intel_atomic_state *state = cdclk_state->base.state;
8b67896e 2192 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9c61de4c 2193 int min_cdclk, cdclk;
bb0f4aab 2194
28a30b45 2195 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2196 if (min_cdclk < 0)
2197 return min_cdclk;
7ff89ca2 2198
9c61de4c 2199 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
7ff89ca2 2200
1965de63
VS		 2201 cdclk_state->logical.cdclk = cdclk;
2202 cdclk_state->logical.voltage_level =
999c5766 2203 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab 2204
0c2d5512 2205 if (!cdclk_state->active_pipes) {
1965de63 2206 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
bb0f4aab 2207
1965de63
VS		 2208 cdclk_state->actual.cdclk = cdclk;
2209 cdclk_state->actual.voltage_level =
999c5766 2210 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab 2211 } else {
1965de63 2212 cdclk_state->actual = cdclk_state->logical;
bb0f4aab 2213 }
7ff89ca2
VS		 2214
2215 return 0;
2216}
2217
28a30b45 2218static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2219{
9c61de4c
VS		 2220 int min_cdclk, cdclk;
2221
28a30b45 2222 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2223 if (min_cdclk < 0)
2224 return min_cdclk;
7ff89ca2
VS		 2225
2226 /*
2227 * FIXME should also account for plane ratio
2228 * once 64bpp pixel formats are supported.
2229 */
d305e061 2230 cdclk = bdw_calc_cdclk(min_cdclk);
7ff89ca2 2231
1965de63
VS		 2232 cdclk_state->logical.cdclk = cdclk;
2233 cdclk_state->logical.voltage_level =
d7ffaeef 2234 bdw_calc_voltage_level(cdclk);
bb0f4aab 2235
0c2d5512 2236 if (!cdclk_state->active_pipes) {
1965de63 2237 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
bb0f4aab 2238
1965de63
VS		 2239 cdclk_state->actual.cdclk = cdclk;
2240 cdclk_state->actual.voltage_level =
d7ffaeef 2241 bdw_calc_voltage_level(cdclk);
bb0f4aab 2242 } else {
1965de63 2243 cdclk_state->actual = cdclk_state->logical;
bb0f4aab 2244 }
7ff89ca2
VS		 2245
2246 return 0;
2247}
2248
28a30b45 2249static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
3297234a 2250{
28a30b45 2251 struct intel_atomic_state *state = cdclk_state->base.state;
8b67896e 2252 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3297234a
RV		 2253 struct intel_crtc *crtc;
2254 struct intel_crtc_state *crtc_state;
2255 int vco, i;
2256
1965de63 2257 vco = cdclk_state->logical.vco;
3297234a
RV		 2258 if (!vco)
2259 vco = dev_priv->skl_preferred_vco_freq;
2260
8b67896e 2261 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1326a92c 2262 if (!crtc_state->hw.enable)
3297234a
RV		 2263 continue;
2264
2265 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2266 continue;
2267
2268 /*
2269 * DPLL0 VCO may need to be adjusted to get the correct
2270 * clock for eDP. This will affect cdclk as well.
2271 */
2272 switch (crtc_state->port_clock / 2) {
2273 case 108000:
2274 case 216000:
2275 vco = 8640000;
2276 break;
2277 default:
2278 vco = 8100000;
2279 break;
2280 }
2281 }
2282
2283 return vco;
2284}
2285
28a30b45 2286static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2287{
9c61de4c
VS		 2288 int min_cdclk, cdclk, vco;
2289
28a30b45 2290 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2291 if (min_cdclk < 0)
2292 return min_cdclk;
bb0f4aab 2293
28a30b45 2294 vco = skl_dpll0_vco(cdclk_state);
7ff89ca2
VS		 2295
2296 /*
2297 * FIXME should also account for plane ratio
2298 * once 64bpp pixel formats are supported.
2299 */
d305e061 2300 cdclk = skl_calc_cdclk(min_cdclk, vco);
7ff89ca2 2301
1965de63
VS		 2302 cdclk_state->logical.vco = vco;
2303 cdclk_state->logical.cdclk = cdclk;
2304 cdclk_state->logical.voltage_level =
2aa97491 2305 skl_calc_voltage_level(cdclk);
bb0f4aab 2306
0c2d5512 2307 if (!cdclk_state->active_pipes) {
1965de63 2308 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
bb0f4aab 2309
1965de63
VS		 2310 cdclk_state->actual.vco = vco;
2311 cdclk_state->actual.cdclk = cdclk;
2312 cdclk_state->actual.voltage_level =
2aa97491 2313 skl_calc_voltage_level(cdclk);
bb0f4aab 2314 } else {
1965de63 2315 cdclk_state->actual = cdclk_state->logical;
bb0f4aab 2316 }
7ff89ca2
VS		 2317
2318 return 0;
2319}
2320
28a30b45 2321static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2322{
28a30b45 2323 struct intel_atomic_state *state = cdclk_state->base.state;
8b67896e 2324 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1d5a95b5 2325 int min_cdclk, min_voltage_level, cdclk, vco;
9c61de4c 2326
28a30b45 2327 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2328 if (min_cdclk < 0)
2329 return min_cdclk;
7ff89ca2 2330
28a30b45 2331 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
1d5a95b5
VS		 2332 if (min_voltage_level < 0)
2333 return min_voltage_level;
2334
736da811
MR		 2335 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2336 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
bb0f4aab 2337
1965de63
VS		 2338 cdclk_state->logical.vco = vco;
2339 cdclk_state->logical.cdclk = cdclk;
2340 cdclk_state->logical.voltage_level =
1d5a95b5
VS		 2341 max_t(int, min_voltage_level,
2342 dev_priv->display.calc_voltage_level(cdclk));
186a277e 2343
0c2d5512 2344 if (!cdclk_state->active_pipes) {
1965de63 2345 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
736da811 2346 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
186a277e 2347
1965de63
VS		 2348 cdclk_state->actual.vco = vco;
2349 cdclk_state->actual.cdclk = cdclk;
2350 cdclk_state->actual.voltage_level =
d2f429eb 2351 dev_priv->display.calc_voltage_level(cdclk);
186a277e 2352 } else {
1965de63 2353 cdclk_state->actual = cdclk_state->logical;
186a277e
PZ		 2354 }
2355
2356 return 0;
2357}
2358
fe4709a8
VS		 2359static int intel_modeset_all_pipes(struct intel_atomic_state *state)
2360{
2361 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2362 struct intel_crtc *crtc;
2363
2364 /*
2365 * Add all pipes to the state, and force
2366 * a modeset on all the active ones.
2367 */
2368 for_each_intel_crtc(&dev_priv->drm, crtc) {
2369 struct intel_crtc_state *crtc_state;
2370 int ret;
2371
2372 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2373 if (IS_ERR(crtc_state))
2374 return PTR_ERR(crtc_state);
2375
1326a92c 2376 if (!crtc_state->hw.active ||
2225f3c6 2377 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
fe4709a8
VS		 2378 continue;
2379
2225f3c6 2380 crtc_state->uapi.mode_changed = true;
fe4709a8
VS		 2381
2382 ret = drm_atomic_add_affected_connectors(&state->base,
2383 &crtc->base);
2384 if (ret)
2385 return ret;
2386
2387 ret = drm_atomic_add_affected_planes(&state->base,
2388 &crtc->base);
2389 if (ret)
2390 return ret;
2391
2392 crtc_state->update_planes |= crtc_state->active_planes;
2393 }
2394
2395 return 0;
2396}
2397
28a30b45 2398static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3e30d708
VS		 2399{
2400 int min_cdclk;
2401
2402 /*
2403 * We can't change the cdclk frequency, but we still want to
2404 * check that the required minimum frequency doesn't exceed
2405 * the actual cdclk frequency.
2406 */
28a30b45 2407 min_cdclk = intel_compute_min_cdclk(cdclk_state);
3e30d708
VS		 2408 if (min_cdclk < 0)
2409 return min_cdclk;
2410
2411 return 0;
2412}
2413
28a30b45
VS		 2414static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
2415{
2416 struct intel_cdclk_state *cdclk_state;
2417
2418 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
2419 if (!cdclk_state)
2420 return NULL;
2421
2422 cdclk_state->force_min_cdclk_changed = false;
2423 cdclk_state->pipe = INVALID_PIPE;
2424
2425 return &cdclk_state->base;
2426}
2427
2428static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
2429 struct intel_global_state *state)
2430{
2431 kfree(state);
2432}
2433
2434static const struct intel_global_state_funcs intel_cdclk_funcs = {
2435 .atomic_duplicate_state = intel_cdclk_duplicate_state,
2436 .atomic_destroy_state = intel_cdclk_destroy_state,
2437};
2438
2439struct intel_cdclk_state *
2440intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
2441{
2442 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2443 struct intel_global_state *cdclk_state;
2444
2445 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
2446 if (IS_ERR(cdclk_state))
2447 return ERR_CAST(cdclk_state);
2448
2449 return to_intel_cdclk_state(cdclk_state);
2450}
2451
2452int intel_cdclk_init(struct drm_i915_private *dev_priv)
2453{
2454 struct intel_cdclk_state *cdclk_state;
2455
2456 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
2457 if (!cdclk_state)
2458 return -ENOMEM;
2459
2460 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
2461 &cdclk_state->base, &intel_cdclk_funcs);
2462
2463 return 0;
2464}
2465
fe4709a8
VS		 2466int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
2467{
2468 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
28a30b45
VS		 2469 const struct intel_cdclk_state *old_cdclk_state;
2470 struct intel_cdclk_state *new_cdclk_state;
fe4709a8
VS		 2471 enum pipe pipe;
2472 int ret;
2473
28a30b45
VS		 2474 new_cdclk_state = intel_atomic_get_cdclk_state(state);
2475 if (IS_ERR(new_cdclk_state))
2476 return PTR_ERR(new_cdclk_state);
54f09d23 2477
28a30b45 2478 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
54f09d23 2479
0c2d5512
VS		 2480 new_cdclk_state->active_pipes =
2481 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
2482
28a30b45 2483 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
fe4709a8
VS		 2484 if (ret)
2485 return ret;
2486
1965de63
VS		 2487 if (intel_cdclk_changed(&old_cdclk_state->actual,
2488 &new_cdclk_state->actual)) {
1d5a95b5
VS		 2489 /*
2490 * Also serialize commits across all crtcs
2491 * if the actual hw needs to be poked.
2492 */
28a30b45 2493 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
1d5a95b5
VS		 2494 if (ret)
2495 return ret;
0c2d5512
VS		 2496 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
2497 intel_cdclk_changed(&old_cdclk_state->logical,
1965de63 2498 &new_cdclk_state->logical)) {
28a30b45 2499 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
1d5a95b5 2500 if (ret)
fe4709a8 2501 return ret;
1d5a95b5
VS		 2502 } else {
2503 return 0;
fe4709a8
VS		 2504 }
2505
0c2d5512 2506 if (is_power_of_2(new_cdclk_state->active_pipes) &&
65c88a86 2507 intel_cdclk_can_cd2x_update(dev_priv,
1965de63
VS		 2508 &old_cdclk_state->actual,
2509 &new_cdclk_state->actual)) {
fe4709a8
VS		 2510 struct intel_crtc *crtc;
2511 struct intel_crtc_state *crtc_state;
2512
0c2d5512 2513 pipe = ilog2(new_cdclk_state->active_pipes);
fe4709a8 2514 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1d5a95b5
VS		 2515
2516 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2517 if (IS_ERR(crtc_state))
2518 return PTR_ERR(crtc_state);
2519
2225f3c6 2520 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
fe4709a8
VS		 2521 pipe = INVALID_PIPE;
2522 } else {
2523 pipe = INVALID_PIPE;
2524 }
2525
1d5a95b5 2526 if (pipe != INVALID_PIPE) {
1965de63 2527 new_cdclk_state->pipe = pipe;
6c066f4c 2528
23194610
WK		 2529 drm_dbg_kms(&dev_priv->drm,
2530 "Can change cdclk with pipe %c active\n",
2531 pipe_name(pipe));
1965de63
VS		 2532 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
2533 &new_cdclk_state->actual)) {
1d5a95b5 2534 /* All pipes must be switched off while we change the cdclk. */
fe4709a8
VS		 2535 ret = intel_modeset_all_pipes(state);
2536 if (ret)
2537 return ret;
2538
1965de63 2539 new_cdclk_state->pipe = INVALID_PIPE;
6c066f4c 2540
23194610
WK		 2541 drm_dbg_kms(&dev_priv->drm,
2542 "Modeset required for cdclk change\n");
fe4709a8
VS		 2543 }
2544
23194610
WK		 2545 drm_dbg_kms(&dev_priv->drm,
2546 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
1965de63
VS		 2547 new_cdclk_state->logical.cdclk,
2548 new_cdclk_state->actual.cdclk);
23194610
WK		 2549 drm_dbg_kms(&dev_priv->drm,
2550 "New voltage level calculated to be logical %u, actual %u\n",
1965de63
VS		 2551 new_cdclk_state->logical.voltage_level,
2552 new_cdclk_state->actual.voltage_level);
fe4709a8
VS		 2553
2554 return 0;
2555}
2556
7ff89ca2
VS		 2557static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2558{
2559 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2560
42882336 2561 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 2562 return 2 * max_cdclk_freq;
cf819eff 2563 else if (IS_GEN(dev_priv, 9) ||
d305e061 2564 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7ff89ca2
VS		 2565 return max_cdclk_freq;
2566 else if (IS_CHERRYVIEW(dev_priv))
2567 return max_cdclk_freq*95/100;
c56b89f1 2568 else if (INTEL_GEN(dev_priv) < 4)
7ff89ca2
VS		 2569 return 2*max_cdclk_freq*90/100;
2570 else
2571 return max_cdclk_freq*90/100;
2572}
2573
2574/**
2575 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2576 * @dev_priv: i915 device
2577 *
2578 * Determine the maximum CDCLK frequency the platform supports, and also
2579 * derive the maximum dot clock frequency the maximum CDCLK frequency
2580 * allows.
2581 */
2582void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2583{
6e63790e
JRS		 2584 if (IS_ELKHARTLAKE(dev_priv)) {
2585 if (dev_priv->cdclk.hw.ref == 24000)
2586 dev_priv->max_cdclk_freq = 552000;
2587 else
2588 dev_priv->max_cdclk_freq = 556800;
2589 } else if (INTEL_GEN(dev_priv) >= 11) {
186a277e
PZ		 2590 if (dev_priv->cdclk.hw.ref == 24000)
2591 dev_priv->max_cdclk_freq = 648000;
2592 else
2593 dev_priv->max_cdclk_freq = 652800;
2594 } else if (IS_CANNONLAKE(dev_priv)) {
d1999e9e
RV		 2595 dev_priv->max_cdclk_freq = 528000;
2596 } else if (IS_GEN9_BC(dev_priv)) {
3e9f55df 2597 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
7ff89ca2
VS		 2598 int max_cdclk, vco;
2599
2600 vco = dev_priv->skl_preferred_vco_freq;
aff35110 2601 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
7ff89ca2
VS		 2602
2603 /*
2604 * Use the lower (vco 8640) cdclk values as a
2605 * first guess. skl_calc_cdclk() will correct it
2606 * if the preferred vco is 8100 instead.
2607 */
2608 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2609 max_cdclk = 617143;
2610 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2611 max_cdclk = 540000;
2612 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2613 max_cdclk = 432000;
2614 else
2615 max_cdclk = 308571;
2616
2617 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2618 } else if (IS_GEMINILAKE(dev_priv)) {
2619 dev_priv->max_cdclk_freq = 316800;
2620 } else if (IS_BROXTON(dev_priv)) {
2621 dev_priv->max_cdclk_freq = 624000;
2622 } else if (IS_BROADWELL(dev_priv)) {
2623 /*
2624 * FIXME with extra cooling we can allow
2625 * 540 MHz for ULX and 675 Mhz for ULT.
2626 * How can we know if extra cooling is
2627 * available? PCI ID, VTB, something else?
2628 */
3e9f55df 2629 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
7ff89ca2
VS		 2630 dev_priv->max_cdclk_freq = 450000;
2631 else if (IS_BDW_ULX(dev_priv))
2632 dev_priv->max_cdclk_freq = 450000;
2633 else if (IS_BDW_ULT(dev_priv))
2634 dev_priv->max_cdclk_freq = 540000;
2635 else
2636 dev_priv->max_cdclk_freq = 675000;
2637 } else if (IS_CHERRYVIEW(dev_priv)) {
2638 dev_priv->max_cdclk_freq = 320000;
2639 } else if (IS_VALLEYVIEW(dev_priv)) {
2640 dev_priv->max_cdclk_freq = 400000;
2641 } else {
2642 /* otherwise assume cdclk is fixed */
49cd97a3 2643 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
7ff89ca2
VS		 2644 }
2645
2646 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2647
23194610
WK		 2648 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
2649 dev_priv->max_cdclk_freq);
7ff89ca2 2650
23194610
WK		 2651 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
2652 dev_priv->max_dotclk_freq);
7ff89ca2
VS		 2653}
2654
2655/**
2656 * intel_update_cdclk - Determine the current CDCLK frequency
2657 * @dev_priv: i915 device
2658 *
2659 * Determine the current CDCLK frequency.
2660 */
2661void intel_update_cdclk(struct drm_i915_private *dev_priv)
2662{
49cd97a3 2663 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
7ff89ca2 2664
7ff89ca2
VS		 2665 /*
2666 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2667 * Programmng [sic] note: bit[9:2] should be programmed to the number
2668 * of cdclk that generates 4MHz reference clock freq which is used to
2669 * generate GMBus clock. This will vary with the cdclk freq.
2670 */
2671 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3e9f55df
JN		 2672 intel_de_write(dev_priv, GMBUSFREQ_VLV,
2673 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
7ff89ca2
VS		 2674}
2675
9d81a997
RV		 2676static int cnp_rawclk(struct drm_i915_private *dev_priv)
2677{
2678 u32 rawclk;
2679 int divider, fraction;
2680
3e9f55df 2681 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
9d81a997
RV		 2682 /* 24 MHz */
2683 divider = 24000;
2684 fraction = 0;
2685 } else {
2686 /* 19.2 MHz */
2687 divider = 19000;
2688 fraction = 200;
2689 }
2690
af4de6ad 2691 rawclk = CNP_RAWCLK_DIV(divider / 1000);
704e504b
PZ		 2692 if (fraction) {
2693 int numerator = 1;
9d81a997 2694
704e504b
PZ		 2695 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2696 fraction) - 1);
29b43ae2 2697 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
704e504b 2698 rawclk |= ICP_RAWCLK_NUM(numerator);
4ef99abd
AS		 2699 }
2700
3e9f55df 2701 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
704e504b 2702 return divider + fraction;
4ef99abd
AS		 2703}
2704
7ff89ca2
VS		 2705static int pch_rawclk(struct drm_i915_private *dev_priv)
2706{
3e9f55df 2707 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
7ff89ca2
VS		 2708}
2709
2710static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2711{
2712 /* RAWCLK_FREQ_VLV register updated from power well code */
2713 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2714 CCK_DISPLAY_REF_CLOCK_CONTROL);
2715}
2716
488e0179 2717static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
7ff89ca2 2718{
cbe974fb 2719 u32 clkcfg;
7ff89ca2 2720
42ab3305
VS		 2721 /*
2722 * hrawclock is 1/4 the FSB frequency
2723 *
2724 * Note that this only reads the state of the FSB
2725 * straps, not the actual FSB frequency. Some BIOSen
2726 * let you configure each independently. Ideally we'd
2727 * read out the actual FSB frequency but sadly we
2728 * don't know which registers have that information,
2729 * and all the relevant docs have gone to bit heaven :(
2730 */
6f62bda1
VS		 2731 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
2732
488e0179
VS		 2733 if (IS_MOBILE(dev_priv)) {
2734 switch (clkcfg) {
2735 case CLKCFG_FSB_400:
2736 return 100000;
2737 case CLKCFG_FSB_533:
2738 return 133333;
2739 case CLKCFG_FSB_667:
2740 return 166667;
2741 case CLKCFG_FSB_800:
2742 return 200000;
2743 case CLKCFG_FSB_1067:
2744 return 266667;
2745 case CLKCFG_FSB_1333:
2746 return 333333;
2747 default:
2748 MISSING_CASE(clkcfg);
2749 return 133333;
2750 }
2751 } else {
2752 switch (clkcfg) {
2753 case CLKCFG_FSB_400_ALT:
2754 return 100000;
2755 case CLKCFG_FSB_533:
2756 return 133333;
2757 case CLKCFG_FSB_667:
2758 return 166667;
2759 case CLKCFG_FSB_800:
2760 return 200000;
2761 case CLKCFG_FSB_1067_ALT:
2762 return 266667;
2763 case CLKCFG_FSB_1333_ALT:
2764 return 333333;
2765 case CLKCFG_FSB_1600_ALT:
2766 return 400000;
2767 default:
2768 return 133333;
2769 }
7ff89ca2
VS		 2770 }
2771}
2772
2773/**
b04002f4 2774 * intel_read_rawclk - Determine the current RAWCLK frequency
7ff89ca2
VS		 2775 * @dev_priv: i915 device
2776 *
2777 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2778 * frequency clock so this needs to done only once.
2779 */
b04002f4 2780u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
7ff89ca2 2781{
b04002f4
CW		 2782 u32 freq;
2783
c6c30b91 2784 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
b04002f4 2785 freq = cnp_rawclk(dev_priv);
9d81a997 2786 else if (HAS_PCH_SPLIT(dev_priv))
b04002f4 2787 freq = pch_rawclk(dev_priv);
7ff89ca2 2788 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
b04002f4 2789 freq = vlv_hrawclk(dev_priv);
488e0179
VS		 2790 else if (INTEL_GEN(dev_priv) >= 3)
2791 freq = i9xx_hrawclk(dev_priv);
7ff89ca2
VS		 2792 else
2793 /* no rawclk on other platforms, or no need to know it */
b04002f4 2794 return 0;
7ff89ca2 2795
b04002f4 2796 return freq;
7ff89ca2
VS		 2797}
2798
2799/**
2800 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2801 * @dev_priv: i915 device
2802 */
2803void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2804{
0fde0b1d
MR		 2805 if (INTEL_GEN(dev_priv) >= 12) {
2806 dev_priv->display.set_cdclk = bxt_set_cdclk;
cd191546 2807 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
0fde0b1d
MR		 2808 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2809 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2810 dev_priv->cdclk.table = icl_cdclk_table;
2811 } else if (IS_ELKHARTLAKE(dev_priv)) {
d2f429eb 2812 dev_priv->display.set_cdclk = bxt_set_cdclk;
cd191546 2813 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
933122cc 2814 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb
MR		 2815 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
2816 dev_priv->cdclk.table = icl_cdclk_table;
2817 } else if (INTEL_GEN(dev_priv) >= 11) {
1cbcd3b4 2818 dev_priv->display.set_cdclk = bxt_set_cdclk;
cd191546 2819 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
933122cc 2820 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb 2821 dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
736da811 2822 dev_priv->cdclk.table = icl_cdclk_table;
993298af 2823 } else if (IS_CANNONLAKE(dev_priv)) {
cd191546 2824 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
1cbcd3b4 2825 dev_priv->display.set_cdclk = bxt_set_cdclk;
933122cc 2826 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb 2827 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
736da811 2828 dev_priv->cdclk.table = cnl_cdclk_table;
7ff89ca2 2829 } else if (IS_GEN9_LP(dev_priv)) {
cd191546 2830 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
b0587e4d 2831 dev_priv->display.set_cdclk = bxt_set_cdclk;
3d51b48f 2832 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb 2833 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
43ed2275
CW		 2834 if (IS_GEMINILAKE(dev_priv))
2835 dev_priv->cdclk.table = glk_cdclk_table;
2836 else
2837 dev_priv->cdclk.table = bxt_cdclk_table;
7ff89ca2 2838 } else if (IS_GEN9_BC(dev_priv)) {
cd191546 2839 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
b0587e4d 2840 dev_priv->display.set_cdclk = skl_set_cdclk;
3d51b48f 2841 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
993298af 2842 } else if (IS_BROADWELL(dev_priv)) {
cd191546 2843 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
993298af 2844 dev_priv->display.set_cdclk = bdw_set_cdclk;
3d51b48f 2845 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
993298af 2846 } else if (IS_CHERRYVIEW(dev_priv)) {
cd191546 2847 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
993298af 2848 dev_priv->display.set_cdclk = chv_set_cdclk;
3d51b48f 2849 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
993298af 2850 } else if (IS_VALLEYVIEW(dev_priv)) {
cd191546 2851 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
993298af 2852 dev_priv->display.set_cdclk = vlv_set_cdclk;
3d51b48f 2853 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
3e30d708 2854 } else {
cd191546 2855 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
3e30d708 2856 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
7ff89ca2
VS		 2857 }
2858
71dc367e 2859 if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
7ff89ca2 2860 dev_priv->display.get_cdclk = bxt_get_cdclk;
993298af
RV		 2861 else if (IS_GEN9_BC(dev_priv))
2862 dev_priv->display.get_cdclk = skl_get_cdclk;
7ff89ca2
VS		 2863 else if (IS_BROADWELL(dev_priv))
2864 dev_priv->display.get_cdclk = bdw_get_cdclk;
2865 else if (IS_HASWELL(dev_priv))
2866 dev_priv->display.get_cdclk = hsw_get_cdclk;
2867 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2868 dev_priv->display.get_cdclk = vlv_get_cdclk;
cf819eff 2869 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
7ff89ca2 2870 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
cf819eff 2871 else if (IS_GEN(dev_priv, 5))
7ff89ca2
VS		 2872 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2873 else if (IS_GM45(dev_priv))
2874 dev_priv->display.get_cdclk = gm45_get_cdclk;
6b9e441d 2875 else if (IS_G45(dev_priv))
7ff89ca2
VS		 2876 dev_priv->display.get_cdclk = g33_get_cdclk;
2877 else if (IS_I965GM(dev_priv))
2878 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2879 else if (IS_I965G(dev_priv))
2880 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2881 else if (IS_PINEVIEW(dev_priv))
2882 dev_priv->display.get_cdclk = pnv_get_cdclk;
2883 else if (IS_G33(dev_priv))
2884 dev_priv->display.get_cdclk = g33_get_cdclk;
2885 else if (IS_I945GM(dev_priv))
2886 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2887 else if (IS_I945G(dev_priv))
2888 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2889 else if (IS_I915GM(dev_priv))
2890 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2891 else if (IS_I915G(dev_priv))
2892 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2893 else if (IS_I865G(dev_priv))
2894 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2895 else if (IS_I85X(dev_priv))
2896 dev_priv->display.get_cdclk = i85x_get_cdclk;
2897 else if (IS_I845G(dev_priv))
2898 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2899 else { /* 830 */
aff35110
PB		 2900 drm_WARN(&dev_priv->drm, !IS_I830(dev_priv),
2901 "Unknown platform. Assuming 133 MHz CDCLK\n");
7ff89ca2
VS		 2902 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2903 }
2904}
Linux 6.x block layer and io_uring tree(s)