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drm/i915/ehl: Update port clock voltage level requirements
[linux-block.git] / drivers / gpu / drm / i915 / display / intel_cdclk.c
CommitLineData
7ff89ca2
VS		 1/*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
fe4709a8 24#include "intel_atomic.h"
e7674ef6 25#include "intel_cdclk.h"
1d455f8d 26#include "intel_display_types.h"
56c5098f 27#include "intel_sideband.h"
7ff89ca2
VS		 28
29/**
30 * DOC: CDCLK / RAWCLK
31 *
32 * The display engine uses several different clocks to do its work. There
33 * are two main clocks involved that aren't directly related to the actual
34 * pixel clock or any symbol/bit clock of the actual output port. These
35 * are the core display clock (CDCLK) and RAWCLK.
36 *
37 * CDCLK clocks most of the display pipe logic, and thus its frequency
38 * must be high enough to support the rate at which pixels are flowing
39 * through the pipes. Downscaling must also be accounted as that increases
40 * the effective pixel rate.
41 *
42 * On several platforms the CDCLK frequency can be changed dynamically
43 * to minimize power consumption for a given display configuration.
44 * Typically changes to the CDCLK frequency require all the display pipes
45 * to be shut down while the frequency is being changed.
46 *
47 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
48 * DMC will not change the active CDCLK frequency however, so that part
49 * will still be performed by the driver directly.
50 *
51 * RAWCLK is a fixed frequency clock, often used by various auxiliary
52 * blocks such as AUX CH or backlight PWM. Hence the only thing we
53 * really need to know about RAWCLK is its frequency so that various
54 * dividers can be programmed correctly.
55 */
56
49cd97a3 57static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 58 struct intel_cdclk_config *cdclk_config)
7ff89ca2 59{
0bb94e03 60 cdclk_config->cdclk = 133333;
7ff89ca2
VS		 61}
62
49cd97a3 63static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 64 struct intel_cdclk_config *cdclk_config)
7ff89ca2 65{
0bb94e03 66 cdclk_config->cdclk = 200000;
7ff89ca2
VS		 67}
68
49cd97a3 69static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 70 struct intel_cdclk_config *cdclk_config)
7ff89ca2 71{
0bb94e03 72 cdclk_config->cdclk = 266667;
7ff89ca2
VS		 73}
74
49cd97a3 75static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 76 struct intel_cdclk_config *cdclk_config)
7ff89ca2 77{
0bb94e03 78 cdclk_config->cdclk = 333333;
7ff89ca2
VS		 79}
80
49cd97a3 81static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 82 struct intel_cdclk_config *cdclk_config)
7ff89ca2 83{
0bb94e03 84 cdclk_config->cdclk = 400000;
7ff89ca2
VS		 85}
86
49cd97a3 87static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 88 struct intel_cdclk_config *cdclk_config)
7ff89ca2 89{
0bb94e03 90 cdclk_config->cdclk = 450000;
7ff89ca2
VS		 91}
92
49cd97a3 93static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 94 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 95{
96 struct pci_dev *pdev = dev_priv->drm.pdev;
97 u16 hpllcc = 0;
98
99 /*
100 * 852GM/852GMV only supports 133 MHz and the HPLLCC
101 * encoding is different :(
102 * FIXME is this the right way to detect 852GM/852GMV?
103 */
49cd97a3 104 if (pdev->revision == 0x1) {
0bb94e03 105 cdclk_config->cdclk = 133333;
49cd97a3
VS		 106 return;
107 }
7ff89ca2
VS		 108
109 pci_bus_read_config_word(pdev->bus,
110 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
111
112 /* Assume that the hardware is in the high speed state. This
113 * should be the default.
114 */
115 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
116 case GC_CLOCK_133_200:
117 case GC_CLOCK_133_200_2:
118 case GC_CLOCK_100_200:
0bb94e03 119 cdclk_config->cdclk = 200000;
49cd97a3 120 break;
7ff89ca2 121 case GC_CLOCK_166_250:
0bb94e03 122 cdclk_config->cdclk = 250000;
49cd97a3 123 break;
7ff89ca2 124 case GC_CLOCK_100_133:
0bb94e03 125 cdclk_config->cdclk = 133333;
49cd97a3 126 break;
7ff89ca2
VS		 127 case GC_CLOCK_133_266:
128 case GC_CLOCK_133_266_2:
129 case GC_CLOCK_166_266:
0bb94e03 130 cdclk_config->cdclk = 266667;
49cd97a3 131 break;
7ff89ca2 132 }
7ff89ca2
VS		 133}
134
49cd97a3 135static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 136 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 137{
138 struct pci_dev *pdev = dev_priv->drm.pdev;
139 u16 gcfgc = 0;
140
141 pci_read_config_word(pdev, GCFGC, &gcfgc);
142
49cd97a3 143 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
0bb94e03 144 cdclk_config->cdclk = 133333;
49cd97a3
VS		 145 return;
146 }
7ff89ca2
VS		 147
148 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
149 case GC_DISPLAY_CLOCK_333_320_MHZ:
0bb94e03 150 cdclk_config->cdclk = 333333;
49cd97a3 151 break;
7ff89ca2
VS		 152 default:
153 case GC_DISPLAY_CLOCK_190_200_MHZ:
0bb94e03 154 cdclk_config->cdclk = 190000;
49cd97a3 155 break;
7ff89ca2
VS		 156 }
157}
158
49cd97a3 159static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 160 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 161{
162 struct pci_dev *pdev = dev_priv->drm.pdev;
163 u16 gcfgc = 0;
164
165 pci_read_config_word(pdev, GCFGC, &gcfgc);
166
49cd97a3 167 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
0bb94e03 168 cdclk_config->cdclk = 133333;
49cd97a3
VS		 169 return;
170 }
7ff89ca2
VS		 171
172 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
173 case GC_DISPLAY_CLOCK_333_320_MHZ:
0bb94e03 174 cdclk_config->cdclk = 320000;
49cd97a3 175 break;
7ff89ca2
VS		 176 default:
177 case GC_DISPLAY_CLOCK_190_200_MHZ:
0bb94e03 178 cdclk_config->cdclk = 200000;
49cd97a3 179 break;
7ff89ca2
VS		 180 }
181}
182
183static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
184{
185 static const unsigned int blb_vco[8] = {
186 [0] = 3200000,
187 [1] = 4000000,
188 [2] = 5333333,
189 [3] = 4800000,
190 [4] = 6400000,
191 };
192 static const unsigned int pnv_vco[8] = {
193 [0] = 3200000,
194 [1] = 4000000,
195 [2] = 5333333,
196 [3] = 4800000,
197 [4] = 2666667,
198 };
199 static const unsigned int cl_vco[8] = {
200 [0] = 3200000,
201 [1] = 4000000,
202 [2] = 5333333,
203 [3] = 6400000,
204 [4] = 3333333,
205 [5] = 3566667,
206 [6] = 4266667,
207 };
208 static const unsigned int elk_vco[8] = {
209 [0] = 3200000,
210 [1] = 4000000,
211 [2] = 5333333,
212 [3] = 4800000,
213 };
214 static const unsigned int ctg_vco[8] = {
215 [0] = 3200000,
216 [1] = 4000000,
217 [2] = 5333333,
218 [3] = 6400000,
219 [4] = 2666667,
220 [5] = 4266667,
221 };
222 const unsigned int *vco_table;
223 unsigned int vco;
cbe974fb 224 u8 tmp = 0;
7ff89ca2
VS		 225
226 /* FIXME other chipsets? */
227 if (IS_GM45(dev_priv))
228 vco_table = ctg_vco;
6b9e441d 229 else if (IS_G45(dev_priv))
7ff89ca2
VS		 230 vco_table = elk_vco;
231 else if (IS_I965GM(dev_priv))
232 vco_table = cl_vco;
233 else if (IS_PINEVIEW(dev_priv))
234 vco_table = pnv_vco;
235 else if (IS_G33(dev_priv))
236 vco_table = blb_vco;
237 else
238 return 0;
239
3e9f55df
JN		 240 tmp = intel_de_read(dev_priv,
241 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
7ff89ca2
VS		 242
243 vco = vco_table[tmp & 0x7];
244 if (vco == 0)
23194610
WK		 245 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
246 tmp);
7ff89ca2 247 else
23194610 248 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
7ff89ca2
VS		 249
250 return vco;
251}
252
49cd97a3 253static void g33_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 254 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 255{
256 struct pci_dev *pdev = dev_priv->drm.pdev;
cbe974fb
JN		 257 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
258 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
259 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
260 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
261 const u8 *div_table;
49cd97a3 262 unsigned int cdclk_sel;
cbe974fb 263 u16 tmp = 0;
7ff89ca2 264
0bb94e03 265 cdclk_config->vco = intel_hpll_vco(dev_priv);
49cd97a3 266
7ff89ca2
VS		 267 pci_read_config_word(pdev, GCFGC, &tmp);
268
269 cdclk_sel = (tmp >> 4) & 0x7;
270
271 if (cdclk_sel >= ARRAY_SIZE(div_3200))
272 goto fail;
273
0bb94e03 274 switch (cdclk_config->vco) {
7ff89ca2
VS		 275 case 3200000:
276 div_table = div_3200;
277 break;
278 case 4000000:
279 div_table = div_4000;
280 break;
281 case 4800000:
282 div_table = div_4800;
283 break;
284 case 5333333:
285 div_table = div_5333;
286 break;
287 default:
288 goto fail;
289 }
290
0bb94e03
VS		 291 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
292 div_table[cdclk_sel]);
49cd97a3 293 return;
7ff89ca2
VS		 294
295fail:
23194610
WK		 296 drm_err(&dev_priv->drm,
297 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
0bb94e03
VS		 298 cdclk_config->vco, tmp);
299 cdclk_config->cdclk = 190476;
7ff89ca2
VS		 300}
301
49cd97a3 302static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 303 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 304{
305 struct pci_dev *pdev = dev_priv->drm.pdev;
306 u16 gcfgc = 0;
307
308 pci_read_config_word(pdev, GCFGC, &gcfgc);
309
310 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
311 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
0bb94e03 312 cdclk_config->cdclk = 266667;
49cd97a3 313 break;
7ff89ca2 314 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
0bb94e03 315 cdclk_config->cdclk = 333333;
49cd97a3 316 break;
7ff89ca2 317 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
0bb94e03 318 cdclk_config->cdclk = 444444;
49cd97a3 319 break;
7ff89ca2 320 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
0bb94e03 321 cdclk_config->cdclk = 200000;
49cd97a3 322 break;
7ff89ca2 323 default:
23194610
WK		 324 drm_err(&dev_priv->drm,
325 "Unknown pnv display core clock 0x%04x\n", gcfgc);
f0d759f0 326 /* fall through */
7ff89ca2 327 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
0bb94e03 328 cdclk_config->cdclk = 133333;
49cd97a3 329 break;
7ff89ca2 330 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
0bb94e03 331 cdclk_config->cdclk = 166667;
49cd97a3 332 break;
7ff89ca2
VS		 333 }
334}
335
49cd97a3 336static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 337 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 338{
339 struct pci_dev *pdev = dev_priv->drm.pdev;
cbe974fb
JN		 340 static const u8 div_3200[] = { 16, 10, 8 };
341 static const u8 div_4000[] = { 20, 12, 10 };
342 static const u8 div_5333[] = { 24, 16, 14 };
343 const u8 *div_table;
49cd97a3 344 unsigned int cdclk_sel;
cbe974fb 345 u16 tmp = 0;
7ff89ca2 346
0bb94e03 347 cdclk_config->vco = intel_hpll_vco(dev_priv);
49cd97a3 348
7ff89ca2
VS		 349 pci_read_config_word(pdev, GCFGC, &tmp);
350
351 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
352
353 if (cdclk_sel >= ARRAY_SIZE(div_3200))
354 goto fail;
355
0bb94e03 356 switch (cdclk_config->vco) {
7ff89ca2
VS		 357 case 3200000:
358 div_table = div_3200;
359 break;
360 case 4000000:
361 div_table = div_4000;
362 break;
363 case 5333333:
364 div_table = div_5333;
365 break;
366 default:
367 goto fail;
368 }
369
0bb94e03
VS		 370 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
371 div_table[cdclk_sel]);
49cd97a3 372 return;
7ff89ca2
VS		 373
374fail:
23194610
WK		 375 drm_err(&dev_priv->drm,
376 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
0bb94e03
VS		 377 cdclk_config->vco, tmp);
378 cdclk_config->cdclk = 200000;
7ff89ca2
VS		 379}
380
49cd97a3 381static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 382 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 383{
384 struct pci_dev *pdev = dev_priv->drm.pdev;
49cd97a3 385 unsigned int cdclk_sel;
cbe974fb 386 u16 tmp = 0;
7ff89ca2 387
0bb94e03 388 cdclk_config->vco = intel_hpll_vco(dev_priv);
49cd97a3 389
7ff89ca2
VS		 390 pci_read_config_word(pdev, GCFGC, &tmp);
391
392 cdclk_sel = (tmp >> 12) & 0x1;
393
0bb94e03 394 switch (cdclk_config->vco) {
7ff89ca2
VS		 395 case 2666667:
396 case 4000000:
397 case 5333333:
0bb94e03 398 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
49cd97a3 399 break;
7ff89ca2 400 case 3200000:
0bb94e03 401 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
49cd97a3 402 break;
7ff89ca2 403 default:
23194610
WK		 404 drm_err(&dev_priv->drm,
405 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
0bb94e03
VS		 406 cdclk_config->vco, tmp);
407 cdclk_config->cdclk = 222222;
49cd97a3 408 break;
7ff89ca2
VS		 409 }
410}
411
49cd97a3 412static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 413 struct intel_cdclk_config *cdclk_config)
7ff89ca2 414{
3e9f55df 415 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
cbe974fb 416 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
7ff89ca2
VS		 417
418 if (lcpll & LCPLL_CD_SOURCE_FCLK)
0bb94e03 419 cdclk_config->cdclk = 800000;
3e9f55df 420 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
0bb94e03 421 cdclk_config->cdclk = 450000;
7ff89ca2 422 else if (freq == LCPLL_CLK_FREQ_450)
0bb94e03 423 cdclk_config->cdclk = 450000;
7ff89ca2 424 else if (IS_HSW_ULT(dev_priv))
0bb94e03 425 cdclk_config->cdclk = 337500;
7ff89ca2 426 else
0bb94e03 427 cdclk_config->cdclk = 540000;
7ff89ca2
VS		 428}
429
d305e061 430static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
7ff89ca2
VS		 431{
432 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
433 333333 : 320000;
7ff89ca2
VS		 434
435 /*
436 * We seem to get an unstable or solid color picture at 200MHz.
437 * Not sure what's wrong. For now use 200MHz only when all pipes
438 * are off.
439 */
d305e061 440 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
7ff89ca2 441 return 400000;
d305e061 442 else if (min_cdclk > 266667)
7ff89ca2 443 return freq_320;
d305e061 444 else if (min_cdclk > 0)
7ff89ca2
VS		 445 return 266667;
446 else
447 return 200000;
448}
449
999c5766
VS		 450static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
451{
452 if (IS_VALLEYVIEW(dev_priv)) {
453 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
454 return 2;
455 else if (cdclk >= 266667)
456 return 1;
457 else
458 return 0;
459 } else {
460 /*
461 * Specs are full of misinformation, but testing on actual
462 * hardware has shown that we just need to write the desired
463 * CCK divider into the Punit register.
464 */
465 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
466 }
467}
468
49cd97a3 469static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 470 struct intel_cdclk_config *cdclk_config)
7ff89ca2 471{
999c5766
VS		 472 u32 val;
473
337fa6e0
CW		 474 vlv_iosf_sb_get(dev_priv,
475 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
476
0bb94e03
VS		 477 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
478 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
479 CCK_DISPLAY_CLOCK_CONTROL,
480 cdclk_config->vco);
999c5766 481
c11b813f 482 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
337fa6e0
CW		 483
484 vlv_iosf_sb_put(dev_priv,
485 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
999c5766
VS		 486
487 if (IS_VALLEYVIEW(dev_priv))
0bb94e03 488 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
999c5766
VS		 489 DSPFREQGUAR_SHIFT;
490 else
0bb94e03 491 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
999c5766 492 DSPFREQGUAR_SHIFT_CHV;
7ff89ca2
VS		 493}
494
495static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
496{
497 unsigned int credits, default_credits;
498
499 if (IS_CHERRYVIEW(dev_priv))
500 default_credits = PFI_CREDIT(12);
501 else
502 default_credits = PFI_CREDIT(8);
503
49cd97a3 504 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
7ff89ca2
VS		 505 /* CHV suggested value is 31 or 63 */
506 if (IS_CHERRYVIEW(dev_priv))
507 credits = PFI_CREDIT_63;
508 else
509 credits = PFI_CREDIT(15);
510 } else {
511 credits = default_credits;
512 }
513
514 /*
515 * WA - write default credits before re-programming
516 * FIXME: should we also set the resend bit here?
517 */
3e9f55df
JN		 518 intel_de_write(dev_priv, GCI_CONTROL,
519 VGA_FAST_MODE_DISABLE | default_credits);
7ff89ca2 520
3e9f55df
JN		 521 intel_de_write(dev_priv, GCI_CONTROL,
522 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
7ff89ca2
VS		 523
524 /*
525 * FIXME is this guaranteed to clear
526 * immediately or should we poll for it?
527 */
3e9f55df 528 WARN_ON(intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
7ff89ca2
VS		 529}
530
83c5fda7 531static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 532 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 533 enum pipe pipe)
7ff89ca2 534{
0bb94e03
VS		 535 int cdclk = cdclk_config->cdclk;
536 u32 val, cmd = cdclk_config->voltage_level;
0e6e0be4 537 intel_wakeref_t wakeref;
7ff89ca2 538
0c9f353f
VS		 539 switch (cdclk) {
540 case 400000:
541 case 333333:
542 case 320000:
543 case 266667:
544 case 200000:
545 break;
546 default:
547 MISSING_CASE(cdclk);
548 return;
549 }
550
886015a0
GKB		 551 /* There are cases where we can end up here with power domains
552 * off and a CDCLK frequency other than the minimum, like when
553 * issuing a modeset without actually changing any display after
13ce6092 554 * a system suspend. So grab the display core domain, which covers
886015a0
GKB		 555 * the HW blocks needed for the following programming.
556 */
13ce6092 557 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
886015a0 558
337fa6e0
CW		 559 vlv_iosf_sb_get(dev_priv,
560 BIT(VLV_IOSF_SB_CCK) |
561 BIT(VLV_IOSF_SB_BUNIT) |
562 BIT(VLV_IOSF_SB_PUNIT));
563
c11b813f 564 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
7ff89ca2
VS		 565 val &= ~DSPFREQGUAR_MASK;
566 val |= (cmd << DSPFREQGUAR_SHIFT);
c11b813f
VS		 567 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
568 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
7ff89ca2
VS		 569 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
570 50)) {
23194610
WK		 571 drm_err(&dev_priv->drm,
572 "timed out waiting for CDclk change\n");
7ff89ca2 573 }
7ff89ca2 574
7ff89ca2
VS		 575 if (cdclk == 400000) {
576 u32 divider;
577
578 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
579 cdclk) - 1;
580
581 /* adjust cdclk divider */
582 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
583 val &= ~CCK_FREQUENCY_VALUES;
584 val |= divider;
585 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
586
587 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
588 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
589 50))
23194610
WK		 590 drm_err(&dev_priv->drm,
591 "timed out waiting for CDclk change\n");
7ff89ca2
VS		 592 }
593
594 /* adjust self-refresh exit latency value */
595 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
596 val &= ~0x7f;
597
598 /*
599 * For high bandwidth configs, we set a higher latency in the bunit
600 * so that the core display fetch happens in time to avoid underruns.
601 */
602 if (cdclk == 400000)
603 val |= 4500 / 250; /* 4.5 usec */
604 else
605 val |= 3000 / 250; /* 3.0 usec */
606 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
607
221c7862 608 vlv_iosf_sb_put(dev_priv,
337fa6e0
CW		 609 BIT(VLV_IOSF_SB_CCK) |
610 BIT(VLV_IOSF_SB_BUNIT) |
611 BIT(VLV_IOSF_SB_PUNIT));
7ff89ca2
VS		 612
613 intel_update_cdclk(dev_priv);
1a5301a5
VS		 614
615 vlv_program_pfi_credits(dev_priv);
886015a0 616
13ce6092 617 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
7ff89ca2
VS		 618}
619
83c5fda7 620static void chv_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 621 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 622 enum pipe pipe)
7ff89ca2 623{
0bb94e03
VS		 624 int cdclk = cdclk_config->cdclk;
625 u32 val, cmd = cdclk_config->voltage_level;
0e6e0be4 626 intel_wakeref_t wakeref;
7ff89ca2 627
7ff89ca2
VS		 628 switch (cdclk) {
629 case 333333:
630 case 320000:
631 case 266667:
632 case 200000:
633 break;
634 default:
635 MISSING_CASE(cdclk);
636 return;
637 }
638
886015a0
GKB		 639 /* There are cases where we can end up here with power domains
640 * off and a CDCLK frequency other than the minimum, like when
641 * issuing a modeset without actually changing any display after
13ce6092 642 * a system suspend. So grab the display core domain, which covers
886015a0
GKB		 643 * the HW blocks needed for the following programming.
644 */
13ce6092 645 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
886015a0 646
337fa6e0 647 vlv_punit_get(dev_priv);
c11b813f 648 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
7ff89ca2
VS		 649 val &= ~DSPFREQGUAR_MASK_CHV;
650 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
c11b813f
VS		 651 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
652 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
7ff89ca2
VS		 653 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
654 50)) {
23194610
WK		 655 drm_err(&dev_priv->drm,
656 "timed out waiting for CDclk change\n");
7ff89ca2 657 }
337fa6e0
CW		 658
659 vlv_punit_put(dev_priv);
7ff89ca2
VS		 660
661 intel_update_cdclk(dev_priv);
1a5301a5
VS		 662
663 vlv_program_pfi_credits(dev_priv);
886015a0 664
13ce6092 665 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
7ff89ca2
VS		 666}
667
d305e061 668static int bdw_calc_cdclk(int min_cdclk)
7ff89ca2 669{
d305e061 670 if (min_cdclk > 540000)
7ff89ca2 671 return 675000;
d305e061 672 else if (min_cdclk > 450000)
7ff89ca2 673 return 540000;
d305e061 674 else if (min_cdclk > 337500)
7ff89ca2
VS		 675 return 450000;
676 else
677 return 337500;
678}
679
d7ffaeef
VS		 680static u8 bdw_calc_voltage_level(int cdclk)
681{
682 switch (cdclk) {
683 default:
684 case 337500:
685 return 2;
686 case 450000:
687 return 0;
688 case 540000:
689 return 1;
690 case 675000:
691 return 3;
692 }
693}
694
49cd97a3 695static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 696 struct intel_cdclk_config *cdclk_config)
7ff89ca2 697{
3e9f55df 698 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
cbe974fb 699 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
7ff89ca2
VS		 700
701 if (lcpll & LCPLL_CD_SOURCE_FCLK)
0bb94e03 702 cdclk_config->cdclk = 800000;
3e9f55df 703 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
0bb94e03 704 cdclk_config->cdclk = 450000;
7ff89ca2 705 else if (freq == LCPLL_CLK_FREQ_450)
0bb94e03 706 cdclk_config->cdclk = 450000;
7ff89ca2 707 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
0bb94e03 708 cdclk_config->cdclk = 540000;
7ff89ca2 709 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
0bb94e03 710 cdclk_config->cdclk = 337500;
7ff89ca2 711 else
0bb94e03 712 cdclk_config->cdclk = 675000;
d7ffaeef
VS		 713
714 /*
715 * Can't read this out :( Let's assume it's
716 * at least what the CDCLK frequency requires.
717 */
0bb94e03
VS		 718 cdclk_config->voltage_level =
719 bdw_calc_voltage_level(cdclk_config->cdclk);
7ff89ca2
VS		 720}
721
83c5fda7 722static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 723 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 724 enum pipe pipe)
7ff89ca2 725{
0bb94e03 726 int cdclk = cdclk_config->cdclk;
cbe974fb 727 u32 val;
7ff89ca2
VS		 728 int ret;
729
3e9f55df 730 if (WARN((intel_de_read(dev_priv, LCPLL_CTL) &
7ff89ca2
VS		 731 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
732 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
733 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
734 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
735 "trying to change cdclk frequency with cdclk not enabled\n"))
736 return;
737
7ff89ca2
VS		 738 ret = sandybridge_pcode_write(dev_priv,
739 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
7ff89ca2 740 if (ret) {
23194610
WK		 741 drm_err(&dev_priv->drm,
742 "failed to inform pcode about cdclk change\n");
7ff89ca2
VS		 743 return;
744 }
745
3e9f55df 746 val = intel_de_read(dev_priv, LCPLL_CTL);
7ff89ca2 747 val |= LCPLL_CD_SOURCE_FCLK;
3e9f55df 748 intel_de_write(dev_priv, LCPLL_CTL, val);
7ff89ca2 749
3164888a
ML		 750 /*
751 * According to the spec, it should be enough to poll for this 1 us.
752 * However, extensive testing shows that this can take longer.
753 */
3e9f55df 754 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
3164888a 755 LCPLL_CD_SOURCE_FCLK_DONE, 100))
23194610 756 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
7ff89ca2 757
3e9f55df 758 val = intel_de_read(dev_priv, LCPLL_CTL);
7ff89ca2
VS		 759 val &= ~LCPLL_CLK_FREQ_MASK;
760
761 switch (cdclk) {
2b58417f
VS		 762 default:
763 MISSING_CASE(cdclk);
764 /* fall through */
765 case 337500:
766 val |= LCPLL_CLK_FREQ_337_5_BDW;
2b58417f 767 break;
7ff89ca2
VS		 768 case 450000:
769 val |= LCPLL_CLK_FREQ_450;
7ff89ca2
VS		 770 break;
771 case 540000:
772 val |= LCPLL_CLK_FREQ_54O_BDW;
7ff89ca2 773 break;
7ff89ca2
VS		 774 case 675000:
775 val |= LCPLL_CLK_FREQ_675_BDW;
7ff89ca2 776 break;
7ff89ca2
VS		 777 }
778
3e9f55df 779 intel_de_write(dev_priv, LCPLL_CTL, val);
7ff89ca2 780
3e9f55df 781 val = intel_de_read(dev_priv, LCPLL_CTL);
7ff89ca2 782 val &= ~LCPLL_CD_SOURCE_FCLK;
3e9f55df 783 intel_de_write(dev_priv, LCPLL_CTL, val);
7ff89ca2 784
3e9f55df
JN		 785 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
786 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
23194610 787 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
7ff89ca2 788
d7ffaeef 789 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
0bb94e03 790 cdclk_config->voltage_level);
7ff89ca2 791
3e9f55df
JN		 792 intel_de_write(dev_priv, CDCLK_FREQ,
793 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
7ff89ca2
VS		 794
795 intel_update_cdclk(dev_priv);
7ff89ca2
VS		 796}
797
d305e061 798static int skl_calc_cdclk(int min_cdclk, int vco)
7ff89ca2
VS		 799{
800 if (vco == 8640000) {
d305e061 801 if (min_cdclk > 540000)
7ff89ca2 802 return 617143;
d305e061 803 else if (min_cdclk > 432000)
7ff89ca2 804 return 540000;
d305e061 805 else if (min_cdclk > 308571)
7ff89ca2
VS		 806 return 432000;
807 else
808 return 308571;
809 } else {
d305e061 810 if (min_cdclk > 540000)
7ff89ca2 811 return 675000;
d305e061 812 else if (min_cdclk > 450000)
7ff89ca2 813 return 540000;
d305e061 814 else if (min_cdclk > 337500)
7ff89ca2
VS		 815 return 450000;
816 else
817 return 337500;
818 }
819}
820
2aa97491
VS		 821static u8 skl_calc_voltage_level(int cdclk)
822{
522d47cf 823 if (cdclk > 540000)
2aa97491 824 return 3;
522d47cf
LDM		 825 else if (cdclk > 450000)
826 return 2;
827 else if (cdclk > 337500)
828 return 1;
829 else
830 return 0;
2aa97491
VS		 831}
832
49cd97a3 833static void skl_dpll0_update(struct drm_i915_private *dev_priv,
0bb94e03 834 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 835{
836 u32 val;
837
0bb94e03
VS		 838 cdclk_config->ref = 24000;
839 cdclk_config->vco = 0;
7ff89ca2 840
3e9f55df 841 val = intel_de_read(dev_priv, LCPLL1_CTL);
7ff89ca2
VS		 842 if ((val & LCPLL_PLL_ENABLE) == 0)
843 return;
844
845 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
846 return;
847
3e9f55df 848 val = intel_de_read(dev_priv, DPLL_CTRL1);
7ff89ca2
VS		 849
850 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
851 DPLL_CTRL1_SSC(SKL_DPLL0) |
852 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
853 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
854 return;
855
856 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
857 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
858 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
859 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
860 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
0bb94e03 861 cdclk_config->vco = 8100000;
7ff89ca2
VS		 862 break;
863 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
864 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
0bb94e03 865 cdclk_config->vco = 8640000;
7ff89ca2
VS		 866 break;
867 default:
868 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
869 break;
870 }
871}
872
49cd97a3 873static void skl_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 874 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 875{
876 u32 cdctl;
877
0bb94e03 878 skl_dpll0_update(dev_priv, cdclk_config);
7ff89ca2 879
0bb94e03 880 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
49cd97a3 881
0bb94e03 882 if (cdclk_config->vco == 0)
2aa97491 883 goto out;
7ff89ca2 884
3e9f55df 885 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
7ff89ca2 886
0bb94e03 887 if (cdclk_config->vco == 8640000) {
7ff89ca2
VS		 888 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
889 case CDCLK_FREQ_450_432:
0bb94e03 890 cdclk_config->cdclk = 432000;
49cd97a3 891 break;
7ff89ca2 892 case CDCLK_FREQ_337_308:
0bb94e03 893 cdclk_config->cdclk = 308571;
49cd97a3 894 break;
7ff89ca2 895 case CDCLK_FREQ_540:
0bb94e03 896 cdclk_config->cdclk = 540000;
49cd97a3 897 break;
7ff89ca2 898 case CDCLK_FREQ_675_617:
0bb94e03 899 cdclk_config->cdclk = 617143;
49cd97a3 900 break;
7ff89ca2
VS		 901 default:
902 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 903 break;
7ff89ca2
VS		 904 }
905 } else {
906 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
907 case CDCLK_FREQ_450_432:
0bb94e03 908 cdclk_config->cdclk = 450000;
49cd97a3 909 break;
7ff89ca2 910 case CDCLK_FREQ_337_308:
0bb94e03 911 cdclk_config->cdclk = 337500;
49cd97a3 912 break;
7ff89ca2 913 case CDCLK_FREQ_540:
0bb94e03 914 cdclk_config->cdclk = 540000;
49cd97a3 915 break;
7ff89ca2 916 case CDCLK_FREQ_675_617:
0bb94e03 917 cdclk_config->cdclk = 675000;
49cd97a3 918 break;
7ff89ca2
VS		 919 default:
920 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
49cd97a3 921 break;
7ff89ca2
VS		 922 }
923 }
2aa97491
VS		 924
925 out:
926 /*
927 * Can't read this out :( Let's assume it's
928 * at least what the CDCLK frequency requires.
929 */
0bb94e03
VS		 930 cdclk_config->voltage_level =
931 skl_calc_voltage_level(cdclk_config->cdclk);
7ff89ca2
VS		 932}
933
934/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
935static int skl_cdclk_decimal(int cdclk)
936{
937 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
938}
939
940static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
941 int vco)
942{
943 bool changed = dev_priv->skl_preferred_vco_freq != vco;
944
945 dev_priv->skl_preferred_vco_freq = vco;
946
947 if (changed)
948 intel_update_max_cdclk(dev_priv);
949}
950
951static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
952{
7ff89ca2
VS		 953 u32 val;
954
955 WARN_ON(vco != 8100000 && vco != 8640000);
956
7ff89ca2
VS		 957 /*
958 * We always enable DPLL0 with the lowest link rate possible, but still
959 * taking into account the VCO required to operate the eDP panel at the
960 * desired frequency. The usual DP link rates operate with a VCO of
961 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
962 * The modeset code is responsible for the selection of the exact link
963 * rate later on, with the constraint of choosing a frequency that
964 * works with vco.
965 */
3e9f55df 966 val = intel_de_read(dev_priv, DPLL_CTRL1);
7ff89ca2
VS		 967
968 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
969 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
970 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
971 if (vco == 8640000)
972 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
973 SKL_DPLL0);
974 else
975 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
976 SKL_DPLL0);
977
3e9f55df
JN		 978 intel_de_write(dev_priv, DPLL_CTRL1, val);
979 intel_de_posting_read(dev_priv, DPLL_CTRL1);
7ff89ca2 980
3e9f55df
JN		 981 intel_de_write(dev_priv, LCPLL1_CTL,
982 intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE);
7ff89ca2 983
4cb3b44d 984 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
23194610 985 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
7ff89ca2 986
49cd97a3 987 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 988
989 /* We'll want to keep using the current vco from now on. */
990 skl_set_preferred_cdclk_vco(dev_priv, vco);
991}
992
993static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
994{
3e9f55df
JN		 995 intel_de_write(dev_priv, LCPLL1_CTL,
996 intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
4cb3b44d 997 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
23194610 998 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
7ff89ca2 999
49cd97a3 1000 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 1001}
1002
1003static void skl_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1004 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 1005 enum pipe pipe)
7ff89ca2 1006{
0bb94e03
VS		 1007 int cdclk = cdclk_config->cdclk;
1008 int vco = cdclk_config->vco;
53421c2f 1009 u32 freq_select, cdclk_ctl;
7ff89ca2
VS		 1010 int ret;
1011
602a9de5
ID		 1012 /*
1013 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1014 * unsupported on SKL. In theory this should never happen since only
1015 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1016 * supported on SKL either, see the above WA. WARN whenever trying to
1017 * use the corresponding VCO freq as that always leads to using the
1018 * minimum 308MHz CDCLK.
1019 */
1020 WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1021
7ff89ca2
VS		 1022 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1023 SKL_CDCLK_PREPARE_FOR_CHANGE,
1024 SKL_CDCLK_READY_FOR_CHANGE,
1025 SKL_CDCLK_READY_FOR_CHANGE, 3);
7ff89ca2 1026 if (ret) {
23194610
WK		 1027 drm_err(&dev_priv->drm,
1028 "Failed to inform PCU about cdclk change (%d)\n", ret);
7ff89ca2
VS		 1029 return;
1030 }
1031
53421c2f 1032 /* Choose frequency for this cdclk */
7ff89ca2 1033 switch (cdclk) {
2b58417f 1034 default:
b6c51c3e 1035 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
2b58417f
VS		 1036 WARN_ON(vco != 0);
1037 /* fall through */
1038 case 308571:
1039 case 337500:
1040 freq_select = CDCLK_FREQ_337_308;
2b58417f 1041 break;
7ff89ca2
VS		 1042 case 450000:
1043 case 432000:
1044 freq_select = CDCLK_FREQ_450_432;
7ff89ca2
VS		 1045 break;
1046 case 540000:
1047 freq_select = CDCLK_FREQ_540;
7ff89ca2 1048 break;
7ff89ca2
VS		 1049 case 617143:
1050 case 675000:
1051 freq_select = CDCLK_FREQ_675_617;
7ff89ca2
VS		 1052 break;
1053 }
1054
49cd97a3
VS		 1055 if (dev_priv->cdclk.hw.vco != 0 &&
1056 dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1057 skl_dpll0_disable(dev_priv);
1058
3e9f55df 1059 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
53421c2f
LDM		 1060
1061 if (dev_priv->cdclk.hw.vco != vco) {
1062 /* Wa Display #1183: skl,kbl,cfl */
1063 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1064 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
3e9f55df 1065 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
53421c2f
LDM		 1066 }
1067
1068 /* Wa Display #1183: skl,kbl,cfl */
1069 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
3e9f55df
JN		 1070 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1071 intel_de_posting_read(dev_priv, CDCLK_CTL);
53421c2f 1072
49cd97a3 1073 if (dev_priv->cdclk.hw.vco != vco)
7ff89ca2
VS		 1074 skl_dpll0_enable(dev_priv, vco);
1075
53421c2f
LDM		 1076 /* Wa Display #1183: skl,kbl,cfl */
1077 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
3e9f55df 1078 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
53421c2f
LDM		 1079
1080 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
3e9f55df 1081 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
53421c2f
LDM		 1082
1083 /* Wa Display #1183: skl,kbl,cfl */
1084 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
3e9f55df
JN		 1085 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1086 intel_de_posting_read(dev_priv, CDCLK_CTL);
7ff89ca2
VS		 1087
1088 /* inform PCU of the change */
2aa97491 1089 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
0bb94e03 1090 cdclk_config->voltage_level);
7ff89ca2
VS		 1091
1092 intel_update_cdclk(dev_priv);
1093}
1094
1095static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1096{
cbe974fb 1097 u32 cdctl, expected;
7ff89ca2
VS		 1098
1099 /*
1100 * check if the pre-os initialized the display
1101 * There is SWF18 scratchpad register defined which is set by the
1102 * pre-os which can be used by the OS drivers to check the status
1103 */
3e9f55df 1104 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
7ff89ca2
VS		 1105 goto sanitize;
1106
1107 intel_update_cdclk(dev_priv);
0bb94e03 1108 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
cfddadc9 1109
7ff89ca2 1110 /* Is PLL enabled and locked ? */
49cd97a3 1111 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1112 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1113 goto sanitize;
1114
1115 /* DPLL okay; verify the cdclock
1116 *
1117 * Noticed in some instances that the freq selection is correct but
1118 * decimal part is programmed wrong from BIOS where pre-os does not
1119 * enable display. Verify the same as well.
1120 */
3e9f55df 1121 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
7ff89ca2 1122 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
49cd97a3 1123 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
7ff89ca2
VS		 1124 if (cdctl == expected)
1125 /* All well; nothing to sanitize */
1126 return;
1127
1128sanitize:
23194610 1129 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
7ff89ca2
VS		 1130
1131 /* force cdclk programming */
49cd97a3 1132 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2 1133 /* force full PLL disable + enable */
49cd97a3 1134 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1135}
1136
ed645eee 1137static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1138{
0bb94e03 1139 struct intel_cdclk_config cdclk_config;
7ff89ca2
VS		 1140
1141 skl_sanitize_cdclk(dev_priv);
1142
49cd97a3
VS		 1143 if (dev_priv->cdclk.hw.cdclk != 0 &&
1144 dev_priv->cdclk.hw.vco != 0) {
7ff89ca2
VS		 1145 /*
1146 * Use the current vco as our initial
1147 * guess as to what the preferred vco is.
1148 */
1149 if (dev_priv->skl_preferred_vco_freq == 0)
1150 skl_set_preferred_cdclk_vco(dev_priv,
49cd97a3 1151 dev_priv->cdclk.hw.vco);
7ff89ca2
VS		 1152 return;
1153 }
1154
0bb94e03 1155 cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1156
0bb94e03
VS		 1157 cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1158 if (cdclk_config.vco == 0)
1159 cdclk_config.vco = 8100000;
1160 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1161 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
7ff89ca2 1162
0bb94e03 1163 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
7ff89ca2
VS		 1164}
1165
ed645eee 1166static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1167{
0bb94e03 1168 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1169
0bb94e03
VS		 1170 cdclk_config.cdclk = cdclk_config.bypass;
1171 cdclk_config.vco = 0;
1172 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
83c5fda7 1173
0bb94e03 1174 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
7ff89ca2
VS		 1175}
1176
736da811
MR		 1177static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1178 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1179 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1180 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1181 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1182 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1183 {}
1184};
1185
1186static const struct intel_cdclk_vals glk_cdclk_table[] = {
1187 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1188 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1189 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1190 {}
1191};
1192
1193static const struct intel_cdclk_vals cnl_cdclk_table[] = {
1194 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
1195 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
1196 { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
1197
1198 { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
1199 { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
1200 { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
1201 {}
1202};
1203
1204static const struct intel_cdclk_vals icl_cdclk_table[] = {
1205 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1206 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1207 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1208 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1209 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1210 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1211
1212 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1213 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1214 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1215 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1216 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1217 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1218
1219 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1220 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1221 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1222 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1223 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1224 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1225 {}
1226};
1227
1228static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1229{
1230 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1231 int i;
1232
1233 for (i = 0; table[i].refclk; i++)
1234 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1235 table[i].cdclk >= min_cdclk)
1236 return table[i].cdclk;
1237
1238 WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n",
1239 min_cdclk, dev_priv->cdclk.hw.ref);
1240 return 0;
7ff89ca2
VS		 1241}
1242
736da811 1243static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
7ff89ca2 1244{
736da811
MR		 1245 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1246 int i;
1247
1248 if (cdclk == dev_priv->cdclk.hw.bypass)
1249 return 0;
1250
1251 for (i = 0; table[i].refclk; i++)
1252 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1253 table[i].cdclk == cdclk)
1254 return dev_priv->cdclk.hw.ref * table[i].ratio;
1255
1256 WARN(1, "cdclk %d not valid for refclk %u\n",
1257 cdclk, dev_priv->cdclk.hw.ref);
1258 return 0;
7ff89ca2
VS		 1259}
1260
2123f442
VS		 1261static u8 bxt_calc_voltage_level(int cdclk)
1262{
1263 return DIV_ROUND_UP(cdclk, 25000);
1264}
1265
71dc367e
MR		 1266static u8 cnl_calc_voltage_level(int cdclk)
1267{
1268 if (cdclk > 336000)
1269 return 2;
1270 else if (cdclk > 168000)
1271 return 1;
1272 else
1273 return 0;
1274}
1275
1276static u8 icl_calc_voltage_level(int cdclk)
1277{
1278 if (cdclk > 556800)
1279 return 2;
1280 else if (cdclk > 312000)
1281 return 1;
1282 else
1283 return 0;
1284}
1285
1286static u8 ehl_calc_voltage_level(int cdclk)
1287{
d1474838
MR		 1288 if (cdclk > 326400)
1289 return 3;
1290 else if (cdclk > 312000)
71dc367e
MR		 1291 return 2;
1292 else if (cdclk > 180000)
1293 return 1;
1294 else
1295 return 0;
1296}
1297
71dc367e 1298static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
0bb94e03 1299 struct intel_cdclk_config *cdclk_config)
7ff89ca2 1300{
3e9f55df 1301 if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
0bb94e03 1302 cdclk_config->ref = 24000;
71dc367e 1303 else
0bb94e03 1304 cdclk_config->ref = 19200;
71dc367e 1305}
7ff89ca2 1306
71dc367e 1307static void icl_readout_refclk(struct drm_i915_private *dev_priv,
0bb94e03 1308 struct intel_cdclk_config *cdclk_config)
71dc367e 1309{
3e9f55df 1310 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
71dc367e
MR		 1311
1312 switch (dssm) {
1313 default:
1314 MISSING_CASE(dssm);
1315 /* fall through */
1316 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
0bb94e03 1317 cdclk_config->ref = 24000;
71dc367e
MR		 1318 break;
1319 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
0bb94e03 1320 cdclk_config->ref = 19200;
71dc367e
MR		 1321 break;
1322 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
0bb94e03 1323 cdclk_config->ref = 38400;
71dc367e
MR		 1324 break;
1325 }
1326}
1327
1328static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
0bb94e03 1329 struct intel_cdclk_config *cdclk_config)
71dc367e
MR		 1330{
1331 u32 val, ratio;
1332
1333 if (INTEL_GEN(dev_priv) >= 11)
0bb94e03 1334 icl_readout_refclk(dev_priv, cdclk_config);
71dc367e 1335 else if (IS_CANNONLAKE(dev_priv))
0bb94e03 1336 cnl_readout_refclk(dev_priv, cdclk_config);
71dc367e 1337 else
0bb94e03 1338 cdclk_config->ref = 19200;
7ff89ca2 1339
3e9f55df 1340 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
71dc367e
MR		 1341 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1342 (val & BXT_DE_PLL_LOCK) == 0) {
1343 /*
1344 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1345 * setting it to zero is a way to signal that.
1346 */
0bb94e03 1347 cdclk_config->vco = 0;
7ff89ca2 1348 return;
71dc367e 1349 }
7ff89ca2 1350
71dc367e
MR		 1351 /*
1352 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
1353 * it in a separate PLL control register.
1354 */
1355 if (INTEL_GEN(dev_priv) >= 10)
1356 ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
1357 else
3e9f55df 1358 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
7ff89ca2 1359
0bb94e03 1360 cdclk_config->vco = ratio * cdclk_config->ref;
7ff89ca2
VS		 1361}
1362
49cd97a3 1363static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1364 struct intel_cdclk_config *cdclk_config)
7ff89ca2
VS		 1365{
1366 u32 divider;
49cd97a3 1367 int div;
7ff89ca2 1368
0bb94e03 1369 bxt_de_pll_readout(dev_priv, cdclk_config);
74689ddf 1370
71dc367e 1371 if (INTEL_GEN(dev_priv) >= 12)
0bb94e03 1372 cdclk_config->bypass = cdclk_config->ref / 2;
71dc367e 1373 else if (INTEL_GEN(dev_priv) >= 11)
0bb94e03 1374 cdclk_config->bypass = 50000;
71dc367e 1375 else
0bb94e03 1376 cdclk_config->bypass = cdclk_config->ref;
49cd97a3 1377
0bb94e03
VS		 1378 if (cdclk_config->vco == 0) {
1379 cdclk_config->cdclk = cdclk_config->bypass;
2123f442 1380 goto out;
71dc367e 1381 }
7ff89ca2 1382
3e9f55df 1383 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7ff89ca2
VS		 1384
1385 switch (divider) {
1386 case BXT_CDCLK_CD2X_DIV_SEL_1:
1387 div = 2;
1388 break;
1389 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
71dc367e
MR		 1390 WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1391 "Unsupported divider\n");
7ff89ca2
VS		 1392 div = 3;
1393 break;
1394 case BXT_CDCLK_CD2X_DIV_SEL_2:
1395 div = 4;
1396 break;
1397 case BXT_CDCLK_CD2X_DIV_SEL_4:
71dc367e 1398 WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");
7ff89ca2
VS		 1399 div = 8;
1400 break;
1401 default:
1402 MISSING_CASE(divider);
49cd97a3 1403 return;
7ff89ca2
VS		 1404 }
1405
0bb94e03 1406 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
2123f442
VS		 1407
1408 out:
1409 /*
1410 * Can't read this out :( Let's assume it's
1411 * at least what the CDCLK frequency requires.
1412 */
0bb94e03
VS		 1413 cdclk_config->voltage_level =
1414 dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
7ff89ca2
VS		 1415}
1416
1417static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1418{
3e9f55df 1419 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
7ff89ca2
VS		 1420
1421 /* Timeout 200us */
4cb3b44d
DCS		 1422 if (intel_de_wait_for_clear(dev_priv,
1423 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
23194610 1424 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
7ff89ca2 1425
49cd97a3 1426 dev_priv->cdclk.hw.vco = 0;
7ff89ca2
VS		 1427}
1428
1429static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1430{
49cd97a3 1431 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
7ff89ca2
VS		 1432 u32 val;
1433
3e9f55df 1434 val = intel_de_read(dev_priv, BXT_DE_PLL_CTL);
7ff89ca2
VS		 1435 val &= ~BXT_DE_PLL_RATIO_MASK;
1436 val |= BXT_DE_PLL_RATIO(ratio);
3e9f55df 1437 intel_de_write(dev_priv, BXT_DE_PLL_CTL, val);
7ff89ca2 1438
3e9f55df 1439 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
7ff89ca2
VS		 1440
1441 /* Timeout 200us */
4cb3b44d
DCS		 1442 if (intel_de_wait_for_set(dev_priv,
1443 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
23194610 1444 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
7ff89ca2 1445
49cd97a3 1446 dev_priv->cdclk.hw.vco = vco;
7ff89ca2
VS		 1447}
1448
1cbcd3b4
MR		 1449static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1450{
1451 u32 val;
1452
3e9f55df 1453 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1cbcd3b4 1454 val &= ~BXT_DE_PLL_PLL_ENABLE;
3e9f55df 1455 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1cbcd3b4
MR		 1456
1457 /* Timeout 200us */
3e9f55df 1458 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
23194610
WK		 1459 drm_err(&dev_priv->drm,
1460 "timeout waiting for CDCLK PLL unlock\n");
1cbcd3b4
MR		 1461
1462 dev_priv->cdclk.hw.vco = 0;
1463}
1464
1465static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1466{
1467 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1468 u32 val;
1469
1470 val = CNL_CDCLK_PLL_RATIO(ratio);
3e9f55df 1471 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1cbcd3b4
MR		 1472
1473 val |= BXT_DE_PLL_PLL_ENABLE;
3e9f55df 1474 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1cbcd3b4
MR		 1475
1476 /* Timeout 200us */
3e9f55df 1477 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
23194610
WK		 1478 drm_err(&dev_priv->drm,
1479 "timeout waiting for CDCLK PLL lock\n");
1cbcd3b4
MR		 1480
1481 dev_priv->cdclk.hw.vco = vco;
1482}
1483
0a12e437
VS		 1484static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1485{
1486 if (INTEL_GEN(dev_priv) >= 12) {
1487 if (pipe == INVALID_PIPE)
1488 return TGL_CDCLK_CD2X_PIPE_NONE;
1489 else
1490 return TGL_CDCLK_CD2X_PIPE(pipe);
1491 } else if (INTEL_GEN(dev_priv) >= 11) {
1492 if (pipe == INVALID_PIPE)
1493 return ICL_CDCLK_CD2X_PIPE_NONE;
1494 else
1495 return ICL_CDCLK_CD2X_PIPE(pipe);
1496 } else {
1497 if (pipe == INVALID_PIPE)
1498 return BXT_CDCLK_CD2X_PIPE_NONE;
1499 else
1500 return BXT_CDCLK_CD2X_PIPE(pipe);
1501 }
1502}
1503
8f0cfa4d 1504static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1505 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 1506 enum pipe pipe)
7ff89ca2 1507{
0bb94e03
VS		 1508 int cdclk = cdclk_config->cdclk;
1509 int vco = cdclk_config->vco;
7ff89ca2 1510 u32 val, divider;
8f0cfa4d 1511 int ret;
7ff89ca2 1512
1cbcd3b4
MR		 1513 /* Inform power controller of upcoming frequency change. */
1514 if (INTEL_GEN(dev_priv) >= 10)
1515 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1516 SKL_CDCLK_PREPARE_FOR_CHANGE,
1517 SKL_CDCLK_READY_FOR_CHANGE,
1518 SKL_CDCLK_READY_FOR_CHANGE, 3);
1519 else
1520 /*
1521 * BSpec requires us to wait up to 150usec, but that leads to
1522 * timeouts; the 2ms used here is based on experiment.
1523 */
1524 ret = sandybridge_pcode_write_timeout(dev_priv,
1525 HSW_PCODE_DE_WRITE_FREQ_REQ,
1526 0x80000000, 150, 2);
1527
1528 if (ret) {
23194610
WK		 1529 drm_err(&dev_priv->drm,
1530 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1531 ret, cdclk);
1cbcd3b4
MR		 1532 return;
1533 }
1534
7ff89ca2
VS		 1535 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1536 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
2b58417f 1537 default:
b6c51c3e 1538 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
2b58417f
VS		 1539 WARN_ON(vco != 0);
1540 /* fall through */
1541 case 2:
1542 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
7ff89ca2
VS		 1543 break;
1544 case 3:
1cbcd3b4
MR		 1545 WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10,
1546 "Unsupported divider\n");
7ff89ca2
VS		 1547 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1548 break;
2b58417f
VS		 1549 case 4:
1550 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
7ff89ca2 1551 break;
2b58417f 1552 case 8:
1cbcd3b4 1553 WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n");
2b58417f 1554 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
7ff89ca2
VS		 1555 break;
1556 }
1557
1cbcd3b4
MR		 1558 if (INTEL_GEN(dev_priv) >= 10) {
1559 if (dev_priv->cdclk.hw.vco != 0 &&
1560 dev_priv->cdclk.hw.vco != vco)
1561 cnl_cdclk_pll_disable(dev_priv);
7ff89ca2 1562
1cbcd3b4
MR		 1563 if (dev_priv->cdclk.hw.vco != vco)
1564 cnl_cdclk_pll_enable(dev_priv, vco);
7ff89ca2 1565
1cbcd3b4
MR		 1566 } else {
1567 if (dev_priv->cdclk.hw.vco != 0 &&
1568 dev_priv->cdclk.hw.vco != vco)
1569 bxt_de_pll_disable(dev_priv);
1570
1571 if (dev_priv->cdclk.hw.vco != vco)
1572 bxt_de_pll_enable(dev_priv, vco);
1573 }
7ff89ca2 1574
0a12e437
VS		 1575 val = divider | skl_cdclk_decimal(cdclk) |
1576 bxt_cdclk_cd2x_pipe(dev_priv, pipe);
1cbcd3b4 1577
7ff89ca2
VS		 1578 /*
1579 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1580 * enable otherwise.
1581 */
1cbcd3b4 1582 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000)
7ff89ca2 1583 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
3e9f55df 1584 intel_de_write(dev_priv, CDCLK_CTL, val);
7ff89ca2 1585
59f9e9ca
VS		 1586 if (pipe != INVALID_PIPE)
1587 intel_wait_for_vblank(dev_priv, pipe);
1588
1cbcd3b4
MR		 1589 if (INTEL_GEN(dev_priv) >= 10) {
1590 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
0bb94e03 1591 cdclk_config->voltage_level);
1cbcd3b4
MR		 1592 } else {
1593 /*
1594 * The timeout isn't specified, the 2ms used here is based on
1595 * experiment.
1596 * FIXME: Waiting for the request completion could be delayed
1597 * until the next PCODE request based on BSpec.
1598 */
1599 ret = sandybridge_pcode_write_timeout(dev_priv,
1600 HSW_PCODE_DE_WRITE_FREQ_REQ,
0bb94e03 1601 cdclk_config->voltage_level,
1cbcd3b4
MR		 1602 150, 2);
1603 }
1604
7ff89ca2 1605 if (ret) {
23194610
WK		 1606 drm_err(&dev_priv->drm,
1607 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
1608 ret, cdclk);
7ff89ca2
VS		 1609 return;
1610 }
1611
1612 intel_update_cdclk(dev_priv);
1cbcd3b4
MR		 1613
1614 if (INTEL_GEN(dev_priv) >= 10)
1615 /*
1616 * Can't read out the voltage level :(
1617 * Let's just assume everything is as expected.
1618 */
0bb94e03 1619 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
7ff89ca2
VS		 1620}
1621
1622static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1623{
1624 u32 cdctl, expected;
8f9f717d 1625 int cdclk, vco;
7ff89ca2
VS		 1626
1627 intel_update_cdclk(dev_priv);
0bb94e03 1628 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
7ff89ca2 1629
49cd97a3 1630 if (dev_priv->cdclk.hw.vco == 0 ||
b6c51c3e 1631 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
7ff89ca2
VS		 1632 goto sanitize;
1633
1634 /* DPLL okay; verify the cdclock
1635 *
1636 * Some BIOS versions leave an incorrect decimal frequency value and
1637 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1638 * so sanitize this register.
1639 */
3e9f55df 1640 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
7ff89ca2
VS		 1641 /*
1642 * Let's ignore the pipe field, since BIOS could have configured the
1643 * dividers both synching to an active pipe, or asynchronously
1644 * (PIPE_NONE).
1645 */
0a12e437 1646 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
7ff89ca2 1647
8f9f717d
MR		 1648 /* Make sure this is a legal cdclk value for the platform */
1649 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
1650 if (cdclk != dev_priv->cdclk.hw.cdclk)
1651 goto sanitize;
1652
1653 /* Make sure the VCO is correct for the cdclk */
1654 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
1655 if (vco != dev_priv->cdclk.hw.vco)
1656 goto sanitize;
1657
1658 expected = skl_cdclk_decimal(cdclk);
1659
1660 /* Figure out what CD2X divider we should be using for this cdclk */
1661 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco,
1662 dev_priv->cdclk.hw.cdclk)) {
1663 case 2:
1664 expected |= BXT_CDCLK_CD2X_DIV_SEL_1;
1665 break;
1666 case 3:
1667 expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5;
1668 break;
1669 case 4:
1670 expected |= BXT_CDCLK_CD2X_DIV_SEL_2;
1671 break;
1672 case 8:
1673 expected |= BXT_CDCLK_CD2X_DIV_SEL_4;
1674 break;
1675 default:
1676 goto sanitize;
1677 }
1678
7ff89ca2
VS		 1679 /*
1680 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1681 * enable otherwise.
1682 */
5dac256b 1683 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)
7ff89ca2
VS		 1684 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1685
1686 if (cdctl == expected)
1687 /* All well; nothing to sanitize */
1688 return;
1689
1690sanitize:
23194610 1691 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
7ff89ca2
VS		 1692
1693 /* force cdclk programming */
49cd97a3 1694 dev_priv->cdclk.hw.cdclk = 0;
7ff89ca2
VS		 1695
1696 /* force full PLL disable + enable */
49cd97a3 1697 dev_priv->cdclk.hw.vco = -1;
7ff89ca2
VS		 1698}
1699
ed645eee 1700static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1701{
0bb94e03 1702 struct intel_cdclk_config cdclk_config;
7ff89ca2
VS		 1703
1704 bxt_sanitize_cdclk(dev_priv);
1705
49cd97a3
VS		 1706 if (dev_priv->cdclk.hw.cdclk != 0 &&
1707 dev_priv->cdclk.hw.vco != 0)
7ff89ca2
VS		 1708 return;
1709
0bb94e03 1710 cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1711
7ff89ca2
VS		 1712 /*
1713 * FIXME:
1714 * - The initial CDCLK needs to be read from VBT.
1715 * Need to make this change after VBT has changes for BXT.
1716 */
0bb94e03
VS		 1717 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
1718 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
1719 cdclk_config.voltage_level =
1720 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
7ff89ca2 1721
0bb94e03 1722 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
7ff89ca2
VS		 1723}
1724
ed645eee 1725static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
7ff89ca2 1726{
0bb94e03 1727 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
83c5fda7 1728
0bb94e03
VS		 1729 cdclk_config.cdclk = cdclk_config.bypass;
1730 cdclk_config.vco = 0;
1731 cdclk_config.voltage_level =
1732 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
83c5fda7 1733
0bb94e03 1734 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
49cd97a3
VS		 1735}
1736
93a643f2 1737/**
ed645eee 1738 * intel_cdclk_init_hw - Initialize CDCLK hardware
93a643f2
JN		 1739 * @i915: i915 device
1740 *
1741 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1742 * sanitizing the state of the hardware if needed. This is generally done only
1743 * during the display core initialization sequence, after which the DMC will
1744 * take care of turning CDCLK off/on as needed.
1745 */
ed645eee 1746void intel_cdclk_init_hw(struct drm_i915_private *i915)
93a643f2 1747{
0c1279b5 1748 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
ed645eee 1749 bxt_cdclk_init_hw(i915);
93a643f2 1750 else if (IS_GEN9_BC(i915))
ed645eee 1751 skl_cdclk_init_hw(i915);
93a643f2
JN		 1752}
1753
1754/**
ed645eee 1755 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
93a643f2
JN		 1756 * @i915: i915 device
1757 *
1758 * Uninitialize CDCLK. This is done only during the display core
1759 * uninitialization sequence.
1760 */
ed645eee 1761void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
93a643f2 1762{
751a93a1 1763 if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915))
ed645eee 1764 bxt_cdclk_uninit_hw(i915);
93a643f2 1765 else if (IS_GEN9_BC(i915))
ed645eee 1766 skl_cdclk_uninit_hw(i915);
93a643f2
JN		 1767}
1768
49cd97a3 1769/**
0bb94e03
VS		 1770 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
1771 * configurations requires a modeset on all pipes
1772 * @a: first CDCLK configuration
1773 * @b: second CDCLK configuration
49cd97a3
VS		 1774 *
1775 * Returns:
0bb94e03
VS		 1776 * True if changing between the two CDCLK configurations
1777 * requires all pipes to be off, false if not.
49cd97a3 1778 */
0bb94e03
VS		 1779bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
1780 const struct intel_cdclk_config *b)
49cd97a3 1781{
64600bd5
VS		 1782 return a->cdclk != b->cdclk ||
1783 a->vco != b->vco ||
1784 a->ref != b->ref;
1785}
1786
59f9e9ca 1787/**
0bb94e03
VS		 1788 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
1789 * configurations requires only a cd2x divider update
1790 * @dev_priv: i915 device
1791 * @a: first CDCLK configuration
1792 * @b: second CDCLK configuration
59f9e9ca
VS		 1793 *
1794 * Returns:
0bb94e03
VS		 1795 * True if changing between the two CDCLK configurations
1796 * can be done with just a cd2x divider update, false if not.
59f9e9ca 1797 */
65c88a86 1798static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
0bb94e03
VS		 1799 const struct intel_cdclk_config *a,
1800 const struct intel_cdclk_config *b)
59f9e9ca
VS		 1801{
1802 /* Older hw doesn't have the capability */
1803 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
1804 return false;
1805
1806 return a->cdclk != b->cdclk &&
1807 a->vco == b->vco &&
1808 a->ref == b->ref;
1809}
1810
64600bd5 1811/**
0bb94e03
VS		 1812 * intel_cdclk_changed - Determine if two CDCLK configurations are different
1813 * @a: first CDCLK configuration
1814 * @b: second CDCLK configuration
64600bd5
VS		 1815 *
1816 * Returns:
0bb94e03 1817 * True if the CDCLK configurations don't match, false if they do.
64600bd5 1818 */
0bb94e03
VS		 1819static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
1820 const struct intel_cdclk_config *b)
64600bd5
VS		 1821{
1822 return intel_cdclk_needs_modeset(a, b) ||
1823 a->voltage_level != b->voltage_level;
7ff89ca2
VS		 1824}
1825
0bb94e03
VS		 1826void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
1827 const char *context)
cfddadc9 1828{
b6c51c3e 1829 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
0bb94e03
VS		 1830 context, cdclk_config->cdclk, cdclk_config->vco,
1831 cdclk_config->ref, cdclk_config->bypass,
1832 cdclk_config->voltage_level);
cfddadc9
VS		 1833}
1834
b0587e4d 1835/**
0bb94e03 1836 * intel_set_cdclk - Push the CDCLK configuration to the hardware
b0587e4d 1837 * @dev_priv: i915 device
0bb94e03 1838 * @cdclk_config: new CDCLK configuration
59f9e9ca 1839 * @pipe: pipe with which to synchronize the update
b0587e4d
VS		 1840 *
1841 * Program the hardware based on the passed in CDCLK state,
1842 * if necessary.
1843 */
59f9e9ca 1844static void intel_set_cdclk(struct drm_i915_private *dev_priv,
0bb94e03 1845 const struct intel_cdclk_config *cdclk_config,
59f9e9ca 1846 enum pipe pipe)
b0587e4d 1847{
0bb94e03 1848 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
b0587e4d
VS		 1849 return;
1850
1851 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1852 return;
1853
0bb94e03 1854 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
b0587e4d 1855
0bb94e03 1856 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
cfddadc9 1857
0bb94e03 1858 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
cfddadc9 1859 "cdclk state doesn't match!\n")) {
0bb94e03
VS		 1860 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
1861 intel_dump_cdclk_config(cdclk_config, "[sw state]");
cfddadc9 1862 }
b0587e4d
VS		 1863}
1864
59f9e9ca 1865/**
5604e9ce
VS		 1866 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
1867 * @state: intel atomic state
59f9e9ca 1868 *
5604e9ce
VS		 1869 * Program the hardware before updating the HW plane state based on the
1870 * new CDCLK state, if necessary.
59f9e9ca
VS		 1871 */
1872void
5604e9ce 1873intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
59f9e9ca 1874{
5604e9ce 1875 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
28a30b45
VS		 1876 const struct intel_cdclk_state *old_cdclk_state =
1877 intel_atomic_get_old_cdclk_state(state);
1878 const struct intel_cdclk_state *new_cdclk_state =
1879 intel_atomic_get_new_cdclk_state(state);
4c029c49 1880 enum pipe pipe = new_cdclk_state->pipe;
5604e9ce 1881
28a30b45
VS		 1882 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1883 &new_cdclk_state->actual))
1884 return;
1885
1965de63 1886 if (pipe == INVALID_PIPE ||
28a30b45
VS		 1887 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
1888 WARN_ON(!new_cdclk_state->base.changed);
1889
1965de63 1890 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
28a30b45 1891 }
59f9e9ca
VS		 1892}
1893
1894/**
5604e9ce
VS		 1895 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
1896 * @state: intel atomic state
59f9e9ca 1897 *
5604e9ce
VS		 1898 * Program the hardware before updating the HW plane state based on the
1899 * new CDCLK state, if necessary.
59f9e9ca
VS		 1900 */
1901void
5604e9ce 1902intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
59f9e9ca 1903{
5604e9ce 1904 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
28a30b45
VS		 1905 const struct intel_cdclk_state *old_cdclk_state =
1906 intel_atomic_get_old_cdclk_state(state);
1907 const struct intel_cdclk_state *new_cdclk_state =
1908 intel_atomic_get_new_cdclk_state(state);
4c029c49 1909 enum pipe pipe = new_cdclk_state->pipe;
5604e9ce 1910
28a30b45
VS		 1911 if (!intel_cdclk_changed(&old_cdclk_state->actual,
1912 &new_cdclk_state->actual))
1913 return;
1914
1965de63 1915 if (pipe != INVALID_PIPE &&
28a30b45
VS		 1916 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
1917 WARN_ON(!new_cdclk_state->base.changed);
1918
1965de63 1919 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
28a30b45 1920 }
59f9e9ca
VS		 1921}
1922
3e30d708 1923static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
d305e061 1924{
2225f3c6 1925 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3e30d708
VS		 1926 int pixel_rate = crtc_state->pixel_rate;
1927
42882336 1928 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 1929 return DIV_ROUND_UP(pixel_rate, 2);
cf819eff 1930 else if (IS_GEN(dev_priv, 9) ||
d305e061
VS		 1931 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1932 return pixel_rate;
1933 else if (IS_CHERRYVIEW(dev_priv))
1934 return DIV_ROUND_UP(pixel_rate * 100, 95);
3e30d708
VS		 1935 else if (crtc_state->double_wide)
1936 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
d305e061
VS		 1937 else
1938 return DIV_ROUND_UP(pixel_rate * 100, 90);
1939}
1940
bb6ae9e6
VS		 1941static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
1942{
2225f3c6 1943 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
bb6ae9e6
VS		 1944 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1945 struct intel_plane *plane;
1946 int min_cdclk = 0;
1947
1948 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1949 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
1950
1951 return min_cdclk;
1952}
1953
d305e061 1954int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
7ff89ca2
VS		 1955{
1956 struct drm_i915_private *dev_priv =
2225f3c6 1957 to_i915(crtc_state->uapi.crtc->dev);
d305e061
VS		 1958 int min_cdclk;
1959
1326a92c 1960 if (!crtc_state->hw.enable)
d305e061
VS		 1961 return 0;
1962
3e30d708 1963 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
7ff89ca2
VS		 1964
1965 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
24f28450 1966 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
d305e061 1967 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
7ff89ca2 1968
78cfa580
PD		 1969 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1970 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1971 * there may be audio corruption or screen corruption." This cdclk
d305e061 1972 * restriction for GLK is 316.8 MHz.
7ff89ca2
VS		 1973 */
1974 if (intel_crtc_has_dp_encoder(crtc_state) &&
1975 crtc_state->has_audio &&
1976 crtc_state->port_clock >= 540000 &&
78cfa580 1977 crtc_state->lane_count == 4) {
d305e061
VS		 1978 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
1979 /* Display WA #1145: glk,cnl */
1980 min_cdclk = max(316800, min_cdclk);
cf819eff 1981 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
d305e061
VS		 1982 /* Display WA #1144: skl,bxt */
1983 min_cdclk = max(432000, min_cdclk);
1984 }
78cfa580 1985 }
7ff89ca2 1986
904e1b1f
AK		 1987 /*
1988 * According to BSpec, "The CD clock frequency must be at least twice
8cbeb06d 1989 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
8cbeb06d 1990 */
905801fe 1991 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
d305e061 1992 min_cdclk = max(2 * 96000, min_cdclk);
8cbeb06d 1993
bffb31f7
VS		 1994 /*
1995 * "For DP audio configuration, cdclk frequency shall be set to
1996 * meet the following requirements:
1997 * DP Link Frequency(MHz) | Cdclk frequency(MHz)
1998 * 270 | 320 or higher
1999 * 162 | 200 or higher"
2000 */
2001 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2002 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2003 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2004
c8dae55a
HG		 2005 /*
2006 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2007 * than 320000KHz.
2008 */
2009 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2010 IS_VALLEYVIEW(dev_priv))
2011 min_cdclk = max(320000, min_cdclk);
2012
beb29980
SL		 2013 /*
2014 * On Geminilake once the CDCLK gets as low as 79200
2015 * picture gets unstable, despite that values are
2016 * correct for DSI PLL and DE PLL.
2017 */
2018 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2019 IS_GEMINILAKE(dev_priv))
2020 min_cdclk = max(158400, min_cdclk);
2021
bb6ae9e6
VS		 2022 /* Account for additional needs from the planes */
2023 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2024
d5848c44
SL		 2025 /*
2026 * HACK. Currently for TGL platforms we calculate
2027 * min_cdclk initially based on pixel_rate divided
2028 * by 2, accounting for also plane requirements,
2029 * however in some cases the lowest possible CDCLK
2030 * doesn't work and causing the underruns.
2031 * Explicitly stating here that this seems to be currently
2032 * rather a Hack, than final solution.
2033 */
2034 if (IS_TIGERLAKE(dev_priv))
2035 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
2036
9c61de4c 2037 if (min_cdclk > dev_priv->max_cdclk_freq) {
23194610
WK		 2038 drm_dbg_kms(&dev_priv->drm,
2039 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2040 min_cdclk, dev_priv->max_cdclk_freq);
9c61de4c
VS		 2041 return -EINVAL;
2042 }
2043
d305e061 2044 return min_cdclk;
7ff89ca2
VS		 2045}
2046
28a30b45 2047static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2048{
28a30b45 2049 struct intel_atomic_state *state = cdclk_state->base.state;
8b67896e 2050 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
d305e061 2051 struct intel_crtc *crtc;
7ff89ca2 2052 struct intel_crtc_state *crtc_state;
9c61de4c 2053 int min_cdclk, i;
7ff89ca2
VS		 2054 enum pipe pipe;
2055
8b67896e 2056 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1d5a95b5
VS		 2057 int ret;
2058
9c61de4c
VS		 2059 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2060 if (min_cdclk < 0)
2061 return min_cdclk;
2062
1965de63 2063 if (cdclk_state->min_cdclk[i] == min_cdclk)
1d5a95b5
VS		 2064 continue;
2065
1965de63 2066 cdclk_state->min_cdclk[i] = min_cdclk;
1d5a95b5 2067
28a30b45 2068 ret = intel_atomic_lock_global_state(&cdclk_state->base);
1d5a95b5
VS		 2069 if (ret)
2070 return ret;
9c61de4c 2071 }
7ff89ca2 2072
1965de63 2073 min_cdclk = cdclk_state->force_min_cdclk;
7ff89ca2 2074 for_each_pipe(dev_priv, pipe)
1965de63 2075 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
7ff89ca2 2076
d305e061 2077 return min_cdclk;
7ff89ca2
VS		 2078}
2079
53e9bf5e 2080/*
933122cc
VS		 2081 * Account for port clock min voltage level requirements.
2082 * This only really does something on CNL+ but can be
2083 * called on earlier platforms as well.
2084 *
53e9bf5e
VS		 2085 * Note that this functions assumes that 0 is
2086 * the lowest voltage value, and higher values
2087 * correspond to increasingly higher voltages.
2088 *
2089 * Should that relationship no longer hold on
2090 * future platforms this code will need to be
2091 * adjusted.
2092 */
28a30b45 2093static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
53e9bf5e 2094{
28a30b45 2095 struct intel_atomic_state *state = cdclk_state->base.state;
53e9bf5e
VS		 2096 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2097 struct intel_crtc *crtc;
2098 struct intel_crtc_state *crtc_state;
2099 u8 min_voltage_level;
2100 int i;
2101 enum pipe pipe;
2102
53e9bf5e 2103 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1d5a95b5
VS		 2104 int ret;
2105
1326a92c 2106 if (crtc_state->hw.enable)
1d5a95b5 2107 min_voltage_level = crtc_state->min_voltage_level;
53e9bf5e 2108 else
1d5a95b5
VS		 2109 min_voltage_level = 0;
2110
1965de63 2111 if (cdclk_state->min_voltage_level[i] == min_voltage_level)
1d5a95b5
VS		 2112 continue;
2113
1965de63 2114 cdclk_state->min_voltage_level[i] = min_voltage_level;
1d5a95b5 2115
28a30b45 2116 ret = intel_atomic_lock_global_state(&cdclk_state->base);
1d5a95b5
VS		 2117 if (ret)
2118 return ret;
53e9bf5e
VS		 2119 }
2120
2121 min_voltage_level = 0;
2122 for_each_pipe(dev_priv, pipe)
1965de63 2123 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
53e9bf5e
VS		 2124 min_voltage_level);
2125
2126 return min_voltage_level;
2127}
2128
28a30b45 2129static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2130{
28a30b45 2131 struct intel_atomic_state *state = cdclk_state->base.state;
8b67896e 2132 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
9c61de4c 2133 int min_cdclk, cdclk;
bb0f4aab 2134
28a30b45 2135 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2136 if (min_cdclk < 0)
2137 return min_cdclk;
7ff89ca2 2138
9c61de4c 2139 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
7ff89ca2 2140
1965de63
VS		 2141 cdclk_state->logical.cdclk = cdclk;
2142 cdclk_state->logical.voltage_level =
999c5766 2143 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab 2144
0c2d5512 2145 if (!cdclk_state->active_pipes) {
1965de63 2146 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
bb0f4aab 2147
1965de63
VS		 2148 cdclk_state->actual.cdclk = cdclk;
2149 cdclk_state->actual.voltage_level =
999c5766 2150 vlv_calc_voltage_level(dev_priv, cdclk);
bb0f4aab 2151 } else {
1965de63 2152 cdclk_state->actual = cdclk_state->logical;
bb0f4aab 2153 }
7ff89ca2
VS		 2154
2155 return 0;
2156}
2157
28a30b45 2158static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2159{
9c61de4c
VS		 2160 int min_cdclk, cdclk;
2161
28a30b45 2162 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2163 if (min_cdclk < 0)
2164 return min_cdclk;
7ff89ca2
VS		 2165
2166 /*
2167 * FIXME should also account for plane ratio
2168 * once 64bpp pixel formats are supported.
2169 */
d305e061 2170 cdclk = bdw_calc_cdclk(min_cdclk);
7ff89ca2 2171
1965de63
VS		 2172 cdclk_state->logical.cdclk = cdclk;
2173 cdclk_state->logical.voltage_level =
d7ffaeef 2174 bdw_calc_voltage_level(cdclk);
bb0f4aab 2175
0c2d5512 2176 if (!cdclk_state->active_pipes) {
1965de63 2177 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
bb0f4aab 2178
1965de63
VS		 2179 cdclk_state->actual.cdclk = cdclk;
2180 cdclk_state->actual.voltage_level =
d7ffaeef 2181 bdw_calc_voltage_level(cdclk);
bb0f4aab 2182 } else {
1965de63 2183 cdclk_state->actual = cdclk_state->logical;
bb0f4aab 2184 }
7ff89ca2
VS		 2185
2186 return 0;
2187}
2188
28a30b45 2189static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
3297234a 2190{
28a30b45 2191 struct intel_atomic_state *state = cdclk_state->base.state;
8b67896e 2192 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3297234a
RV		 2193 struct intel_crtc *crtc;
2194 struct intel_crtc_state *crtc_state;
2195 int vco, i;
2196
1965de63 2197 vco = cdclk_state->logical.vco;
3297234a
RV		 2198 if (!vco)
2199 vco = dev_priv->skl_preferred_vco_freq;
2200
8b67896e 2201 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1326a92c 2202 if (!crtc_state->hw.enable)
3297234a
RV		 2203 continue;
2204
2205 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2206 continue;
2207
2208 /*
2209 * DPLL0 VCO may need to be adjusted to get the correct
2210 * clock for eDP. This will affect cdclk as well.
2211 */
2212 switch (crtc_state->port_clock / 2) {
2213 case 108000:
2214 case 216000:
2215 vco = 8640000;
2216 break;
2217 default:
2218 vco = 8100000;
2219 break;
2220 }
2221 }
2222
2223 return vco;
2224}
2225
28a30b45 2226static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2227{
9c61de4c
VS		 2228 int min_cdclk, cdclk, vco;
2229
28a30b45 2230 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2231 if (min_cdclk < 0)
2232 return min_cdclk;
bb0f4aab 2233
28a30b45 2234 vco = skl_dpll0_vco(cdclk_state);
7ff89ca2
VS		 2235
2236 /*
2237 * FIXME should also account for plane ratio
2238 * once 64bpp pixel formats are supported.
2239 */
d305e061 2240 cdclk = skl_calc_cdclk(min_cdclk, vco);
7ff89ca2 2241
1965de63
VS		 2242 cdclk_state->logical.vco = vco;
2243 cdclk_state->logical.cdclk = cdclk;
2244 cdclk_state->logical.voltage_level =
2aa97491 2245 skl_calc_voltage_level(cdclk);
bb0f4aab 2246
0c2d5512 2247 if (!cdclk_state->active_pipes) {
1965de63 2248 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
bb0f4aab 2249
1965de63
VS		 2250 cdclk_state->actual.vco = vco;
2251 cdclk_state->actual.cdclk = cdclk;
2252 cdclk_state->actual.voltage_level =
2aa97491 2253 skl_calc_voltage_level(cdclk);
bb0f4aab 2254 } else {
1965de63 2255 cdclk_state->actual = cdclk_state->logical;
bb0f4aab 2256 }
7ff89ca2
VS		 2257
2258 return 0;
2259}
2260
28a30b45 2261static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
7ff89ca2 2262{
28a30b45 2263 struct intel_atomic_state *state = cdclk_state->base.state;
8b67896e 2264 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1d5a95b5 2265 int min_cdclk, min_voltage_level, cdclk, vco;
9c61de4c 2266
28a30b45 2267 min_cdclk = intel_compute_min_cdclk(cdclk_state);
9c61de4c
VS		 2268 if (min_cdclk < 0)
2269 return min_cdclk;
7ff89ca2 2270
28a30b45 2271 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
1d5a95b5
VS		 2272 if (min_voltage_level < 0)
2273 return min_voltage_level;
2274
736da811
MR		 2275 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2276 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
bb0f4aab 2277
1965de63
VS		 2278 cdclk_state->logical.vco = vco;
2279 cdclk_state->logical.cdclk = cdclk;
2280 cdclk_state->logical.voltage_level =
1d5a95b5
VS		 2281 max_t(int, min_voltage_level,
2282 dev_priv->display.calc_voltage_level(cdclk));
186a277e 2283
0c2d5512 2284 if (!cdclk_state->active_pipes) {
1965de63 2285 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
736da811 2286 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
186a277e 2287
1965de63
VS		 2288 cdclk_state->actual.vco = vco;
2289 cdclk_state->actual.cdclk = cdclk;
2290 cdclk_state->actual.voltage_level =
d2f429eb 2291 dev_priv->display.calc_voltage_level(cdclk);
186a277e 2292 } else {
1965de63 2293 cdclk_state->actual = cdclk_state->logical;
186a277e
PZ		 2294 }
2295
2296 return 0;
2297}
2298
fe4709a8
VS		 2299static int intel_modeset_all_pipes(struct intel_atomic_state *state)
2300{
2301 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2302 struct intel_crtc *crtc;
2303
2304 /*
2305 * Add all pipes to the state, and force
2306 * a modeset on all the active ones.
2307 */
2308 for_each_intel_crtc(&dev_priv->drm, crtc) {
2309 struct intel_crtc_state *crtc_state;
2310 int ret;
2311
2312 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2313 if (IS_ERR(crtc_state))
2314 return PTR_ERR(crtc_state);
2315
1326a92c 2316 if (!crtc_state->hw.active ||
2225f3c6 2317 drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
fe4709a8
VS		 2318 continue;
2319
2225f3c6 2320 crtc_state->uapi.mode_changed = true;
fe4709a8
VS		 2321
2322 ret = drm_atomic_add_affected_connectors(&state->base,
2323 &crtc->base);
2324 if (ret)
2325 return ret;
2326
2327 ret = drm_atomic_add_affected_planes(&state->base,
2328 &crtc->base);
2329 if (ret)
2330 return ret;
2331
2332 crtc_state->update_planes |= crtc_state->active_planes;
2333 }
2334
2335 return 0;
2336}
2337
28a30b45 2338static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3e30d708
VS		 2339{
2340 int min_cdclk;
2341
2342 /*
2343 * We can't change the cdclk frequency, but we still want to
2344 * check that the required minimum frequency doesn't exceed
2345 * the actual cdclk frequency.
2346 */
28a30b45 2347 min_cdclk = intel_compute_min_cdclk(cdclk_state);
3e30d708
VS		 2348 if (min_cdclk < 0)
2349 return min_cdclk;
2350
2351 return 0;
2352}
2353
28a30b45
VS		 2354static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
2355{
2356 struct intel_cdclk_state *cdclk_state;
2357
2358 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
2359 if (!cdclk_state)
2360 return NULL;
2361
2362 cdclk_state->force_min_cdclk_changed = false;
2363 cdclk_state->pipe = INVALID_PIPE;
2364
2365 return &cdclk_state->base;
2366}
2367
2368static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
2369 struct intel_global_state *state)
2370{
2371 kfree(state);
2372}
2373
2374static const struct intel_global_state_funcs intel_cdclk_funcs = {
2375 .atomic_duplicate_state = intel_cdclk_duplicate_state,
2376 .atomic_destroy_state = intel_cdclk_destroy_state,
2377};
2378
2379struct intel_cdclk_state *
2380intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
2381{
2382 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2383 struct intel_global_state *cdclk_state;
2384
2385 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
2386 if (IS_ERR(cdclk_state))
2387 return ERR_CAST(cdclk_state);
2388
2389 return to_intel_cdclk_state(cdclk_state);
2390}
2391
2392int intel_cdclk_init(struct drm_i915_private *dev_priv)
2393{
2394 struct intel_cdclk_state *cdclk_state;
2395
2396 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
2397 if (!cdclk_state)
2398 return -ENOMEM;
2399
2400 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
2401 &cdclk_state->base, &intel_cdclk_funcs);
2402
2403 return 0;
2404}
2405
fe4709a8
VS		 2406int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
2407{
2408 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
28a30b45
VS		 2409 const struct intel_cdclk_state *old_cdclk_state;
2410 struct intel_cdclk_state *new_cdclk_state;
fe4709a8
VS		 2411 enum pipe pipe;
2412 int ret;
2413
28a30b45
VS		 2414 new_cdclk_state = intel_atomic_get_cdclk_state(state);
2415 if (IS_ERR(new_cdclk_state))
2416 return PTR_ERR(new_cdclk_state);
54f09d23 2417
28a30b45 2418 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
54f09d23 2419
0c2d5512
VS		 2420 new_cdclk_state->active_pipes =
2421 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
2422
28a30b45 2423 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
fe4709a8
VS		 2424 if (ret)
2425 return ret;
2426
1965de63
VS		 2427 if (intel_cdclk_changed(&old_cdclk_state->actual,
2428 &new_cdclk_state->actual)) {
1d5a95b5
VS		 2429 /*
2430 * Also serialize commits across all crtcs
2431 * if the actual hw needs to be poked.
2432 */
28a30b45 2433 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
1d5a95b5
VS		 2434 if (ret)
2435 return ret;
0c2d5512
VS		 2436 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
2437 intel_cdclk_changed(&old_cdclk_state->logical,
1965de63 2438 &new_cdclk_state->logical)) {
28a30b45 2439 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
1d5a95b5 2440 if (ret)
fe4709a8 2441 return ret;
1d5a95b5
VS		 2442 } else {
2443 return 0;
fe4709a8
VS		 2444 }
2445
0c2d5512 2446 if (is_power_of_2(new_cdclk_state->active_pipes) &&
65c88a86 2447 intel_cdclk_can_cd2x_update(dev_priv,
1965de63
VS		 2448 &old_cdclk_state->actual,
2449 &new_cdclk_state->actual)) {
fe4709a8
VS		 2450 struct intel_crtc *crtc;
2451 struct intel_crtc_state *crtc_state;
2452
0c2d5512 2453 pipe = ilog2(new_cdclk_state->active_pipes);
fe4709a8 2454 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1d5a95b5
VS		 2455
2456 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2457 if (IS_ERR(crtc_state))
2458 return PTR_ERR(crtc_state);
2459
2225f3c6 2460 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
fe4709a8
VS		 2461 pipe = INVALID_PIPE;
2462 } else {
2463 pipe = INVALID_PIPE;
2464 }
2465
1d5a95b5 2466 if (pipe != INVALID_PIPE) {
1965de63 2467 new_cdclk_state->pipe = pipe;
6c066f4c 2468
23194610
WK		 2469 drm_dbg_kms(&dev_priv->drm,
2470 "Can change cdclk with pipe %c active\n",
2471 pipe_name(pipe));
1965de63
VS		 2472 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
2473 &new_cdclk_state->actual)) {
1d5a95b5 2474 /* All pipes must be switched off while we change the cdclk. */
fe4709a8
VS		 2475 ret = intel_modeset_all_pipes(state);
2476 if (ret)
2477 return ret;
2478
1965de63 2479 new_cdclk_state->pipe = INVALID_PIPE;
6c066f4c 2480
23194610
WK		 2481 drm_dbg_kms(&dev_priv->drm,
2482 "Modeset required for cdclk change\n");
fe4709a8
VS		 2483 }
2484
23194610
WK		 2485 drm_dbg_kms(&dev_priv->drm,
2486 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
1965de63
VS		 2487 new_cdclk_state->logical.cdclk,
2488 new_cdclk_state->actual.cdclk);
23194610
WK		 2489 drm_dbg_kms(&dev_priv->drm,
2490 "New voltage level calculated to be logical %u, actual %u\n",
1965de63
VS		 2491 new_cdclk_state->logical.voltage_level,
2492 new_cdclk_state->actual.voltage_level);
fe4709a8
VS		 2493
2494 return 0;
2495}
2496
7ff89ca2
VS		 2497static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2498{
2499 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2500
42882336 2501 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
43037c86 2502 return 2 * max_cdclk_freq;
cf819eff 2503 else if (IS_GEN(dev_priv, 9) ||
d305e061 2504 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7ff89ca2
VS		 2505 return max_cdclk_freq;
2506 else if (IS_CHERRYVIEW(dev_priv))
2507 return max_cdclk_freq*95/100;
c56b89f1 2508 else if (INTEL_GEN(dev_priv) < 4)
7ff89ca2
VS		 2509 return 2*max_cdclk_freq*90/100;
2510 else
2511 return max_cdclk_freq*90/100;
2512}
2513
2514/**
2515 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2516 * @dev_priv: i915 device
2517 *
2518 * Determine the maximum CDCLK frequency the platform supports, and also
2519 * derive the maximum dot clock frequency the maximum CDCLK frequency
2520 * allows.
2521 */
2522void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2523{
6e63790e
JRS		 2524 if (IS_ELKHARTLAKE(dev_priv)) {
2525 if (dev_priv->cdclk.hw.ref == 24000)
2526 dev_priv->max_cdclk_freq = 552000;
2527 else
2528 dev_priv->max_cdclk_freq = 556800;
2529 } else if (INTEL_GEN(dev_priv) >= 11) {
186a277e
PZ		 2530 if (dev_priv->cdclk.hw.ref == 24000)
2531 dev_priv->max_cdclk_freq = 648000;
2532 else
2533 dev_priv->max_cdclk_freq = 652800;
2534 } else if (IS_CANNONLAKE(dev_priv)) {
d1999e9e
RV		 2535 dev_priv->max_cdclk_freq = 528000;
2536 } else if (IS_GEN9_BC(dev_priv)) {
3e9f55df 2537 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
7ff89ca2
VS		 2538 int max_cdclk, vco;
2539
2540 vco = dev_priv->skl_preferred_vco_freq;
2541 WARN_ON(vco != 8100000 && vco != 8640000);
2542
2543 /*
2544 * Use the lower (vco 8640) cdclk values as a
2545 * first guess. skl_calc_cdclk() will correct it
2546 * if the preferred vco is 8100 instead.
2547 */
2548 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2549 max_cdclk = 617143;
2550 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2551 max_cdclk = 540000;
2552 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2553 max_cdclk = 432000;
2554 else
2555 max_cdclk = 308571;
2556
2557 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2558 } else if (IS_GEMINILAKE(dev_priv)) {
2559 dev_priv->max_cdclk_freq = 316800;
2560 } else if (IS_BROXTON(dev_priv)) {
2561 dev_priv->max_cdclk_freq = 624000;
2562 } else if (IS_BROADWELL(dev_priv)) {
2563 /*
2564 * FIXME with extra cooling we can allow
2565 * 540 MHz for ULX and 675 Mhz for ULT.
2566 * How can we know if extra cooling is
2567 * available? PCI ID, VTB, something else?
2568 */
3e9f55df 2569 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
7ff89ca2
VS		 2570 dev_priv->max_cdclk_freq = 450000;
2571 else if (IS_BDW_ULX(dev_priv))
2572 dev_priv->max_cdclk_freq = 450000;
2573 else if (IS_BDW_ULT(dev_priv))
2574 dev_priv->max_cdclk_freq = 540000;
2575 else
2576 dev_priv->max_cdclk_freq = 675000;
2577 } else if (IS_CHERRYVIEW(dev_priv)) {
2578 dev_priv->max_cdclk_freq = 320000;
2579 } else if (IS_VALLEYVIEW(dev_priv)) {
2580 dev_priv->max_cdclk_freq = 400000;
2581 } else {
2582 /* otherwise assume cdclk is fixed */
49cd97a3 2583 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
7ff89ca2
VS		 2584 }
2585
2586 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2587
23194610
WK		 2588 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
2589 dev_priv->max_cdclk_freq);
7ff89ca2 2590
23194610
WK		 2591 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
2592 dev_priv->max_dotclk_freq);
7ff89ca2
VS		 2593}
2594
2595/**
2596 * intel_update_cdclk - Determine the current CDCLK frequency
2597 * @dev_priv: i915 device
2598 *
2599 * Determine the current CDCLK frequency.
2600 */
2601void intel_update_cdclk(struct drm_i915_private *dev_priv)
2602{
49cd97a3 2603 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
7ff89ca2 2604
7ff89ca2
VS		 2605 /*
2606 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2607 * Programmng [sic] note: bit[9:2] should be programmed to the number
2608 * of cdclk that generates 4MHz reference clock freq which is used to
2609 * generate GMBus clock. This will vary with the cdclk freq.
2610 */
2611 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3e9f55df
JN		 2612 intel_de_write(dev_priv, GMBUSFREQ_VLV,
2613 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
7ff89ca2
VS		 2614}
2615
9d81a997
RV		 2616static int cnp_rawclk(struct drm_i915_private *dev_priv)
2617{
2618 u32 rawclk;
2619 int divider, fraction;
2620
3e9f55df 2621 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
9d81a997
RV		 2622 /* 24 MHz */
2623 divider = 24000;
2624 fraction = 0;
2625 } else {
2626 /* 19.2 MHz */
2627 divider = 19000;
2628 fraction = 200;
2629 }
2630
af4de6ad 2631 rawclk = CNP_RAWCLK_DIV(divider / 1000);
704e504b
PZ		 2632 if (fraction) {
2633 int numerator = 1;
9d81a997 2634
704e504b
PZ		 2635 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2636 fraction) - 1);
29b43ae2 2637 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
704e504b 2638 rawclk |= ICP_RAWCLK_NUM(numerator);
4ef99abd
AS		 2639 }
2640
3e9f55df 2641 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
704e504b 2642 return divider + fraction;
4ef99abd
AS		 2643}
2644
7ff89ca2
VS		 2645static int pch_rawclk(struct drm_i915_private *dev_priv)
2646{
3e9f55df 2647 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
7ff89ca2
VS		 2648}
2649
2650static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2651{
2652 /* RAWCLK_FREQ_VLV register updated from power well code */
2653 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2654 CCK_DISPLAY_REF_CLOCK_CONTROL);
2655}
2656
2657static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2658{
cbe974fb 2659 u32 clkcfg;
7ff89ca2
VS		 2660
2661 /* hrawclock is 1/4 the FSB frequency */
3e9f55df 2662 clkcfg = intel_de_read(dev_priv, CLKCFG);
7ff89ca2
VS		 2663 switch (clkcfg & CLKCFG_FSB_MASK) {
2664 case CLKCFG_FSB_400:
2665 return 100000;
2666 case CLKCFG_FSB_533:
2667 return 133333;
2668 case CLKCFG_FSB_667:
2669 return 166667;
2670 case CLKCFG_FSB_800:
2671 return 200000;
2672 case CLKCFG_FSB_1067:
6f38123e 2673 case CLKCFG_FSB_1067_ALT:
7ff89ca2
VS		 2674 return 266667;
2675 case CLKCFG_FSB_1333:
6f38123e 2676 case CLKCFG_FSB_1333_ALT:
7ff89ca2 2677 return 333333;
7ff89ca2
VS		 2678 default:
2679 return 133333;
2680 }
2681}
2682
2683/**
2684 * intel_update_rawclk - Determine the current RAWCLK frequency
2685 * @dev_priv: i915 device
2686 *
2687 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2688 * frequency clock so this needs to done only once.
2689 */
2690void intel_update_rawclk(struct drm_i915_private *dev_priv)
2691{
c6c30b91 2692 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
9d81a997
RV		 2693 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2694 else if (HAS_PCH_SPLIT(dev_priv))
7ff89ca2
VS		 2695 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2696 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2697 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2698 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2699 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2700 else
2701 /* no rawclk on other platforms, or no need to know it */
2702 return;
2703
23194610
WK		 2704 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n",
2705 dev_priv->rawclk_freq);
7ff89ca2
VS		 2706}
2707
2708/**
2709 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2710 * @dev_priv: i915 device
2711 */
2712void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2713{
d2f429eb
MR		 2714 if (IS_ELKHARTLAKE(dev_priv)) {
2715 dev_priv->display.set_cdclk = bxt_set_cdclk;
933122cc 2716 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb
MR		 2717 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
2718 dev_priv->cdclk.table = icl_cdclk_table;
2719 } else if (INTEL_GEN(dev_priv) >= 11) {
1cbcd3b4 2720 dev_priv->display.set_cdclk = bxt_set_cdclk;
933122cc 2721 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb 2722 dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
736da811 2723 dev_priv->cdclk.table = icl_cdclk_table;
993298af 2724 } else if (IS_CANNONLAKE(dev_priv)) {
1cbcd3b4 2725 dev_priv->display.set_cdclk = bxt_set_cdclk;
933122cc 2726 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb 2727 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
736da811 2728 dev_priv->cdclk.table = cnl_cdclk_table;
7ff89ca2 2729 } else if (IS_GEN9_LP(dev_priv)) {
b0587e4d 2730 dev_priv->display.set_cdclk = bxt_set_cdclk;
3d51b48f 2731 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
d2f429eb 2732 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
43ed2275
CW		 2733 if (IS_GEMINILAKE(dev_priv))
2734 dev_priv->cdclk.table = glk_cdclk_table;
2735 else
2736 dev_priv->cdclk.table = bxt_cdclk_table;
7ff89ca2 2737 } else if (IS_GEN9_BC(dev_priv)) {
b0587e4d 2738 dev_priv->display.set_cdclk = skl_set_cdclk;
3d51b48f 2739 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
993298af
RV		 2740 } else if (IS_BROADWELL(dev_priv)) {
2741 dev_priv->display.set_cdclk = bdw_set_cdclk;
3d51b48f 2742 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
993298af
RV		 2743 } else if (IS_CHERRYVIEW(dev_priv)) {
2744 dev_priv->display.set_cdclk = chv_set_cdclk;
3d51b48f 2745 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
993298af
RV		 2746 } else if (IS_VALLEYVIEW(dev_priv)) {
2747 dev_priv->display.set_cdclk = vlv_set_cdclk;
3d51b48f 2748 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
3e30d708
VS		 2749 } else {
2750 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
7ff89ca2
VS		 2751 }
2752
71dc367e 2753 if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))
7ff89ca2 2754 dev_priv->display.get_cdclk = bxt_get_cdclk;
993298af
RV		 2755 else if (IS_GEN9_BC(dev_priv))
2756 dev_priv->display.get_cdclk = skl_get_cdclk;
7ff89ca2
VS		 2757 else if (IS_BROADWELL(dev_priv))
2758 dev_priv->display.get_cdclk = bdw_get_cdclk;
2759 else if (IS_HASWELL(dev_priv))
2760 dev_priv->display.get_cdclk = hsw_get_cdclk;
2761 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2762 dev_priv->display.get_cdclk = vlv_get_cdclk;
cf819eff 2763 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
7ff89ca2 2764 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
cf819eff 2765 else if (IS_GEN(dev_priv, 5))
7ff89ca2
VS		 2766 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2767 else if (IS_GM45(dev_priv))
2768 dev_priv->display.get_cdclk = gm45_get_cdclk;
6b9e441d 2769 else if (IS_G45(dev_priv))
7ff89ca2
VS		 2770 dev_priv->display.get_cdclk = g33_get_cdclk;
2771 else if (IS_I965GM(dev_priv))
2772 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2773 else if (IS_I965G(dev_priv))
2774 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2775 else if (IS_PINEVIEW(dev_priv))
2776 dev_priv->display.get_cdclk = pnv_get_cdclk;
2777 else if (IS_G33(dev_priv))
2778 dev_priv->display.get_cdclk = g33_get_cdclk;
2779 else if (IS_I945GM(dev_priv))
2780 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2781 else if (IS_I945G(dev_priv))
2782 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2783 else if (IS_I915GM(dev_priv))
2784 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2785 else if (IS_I915G(dev_priv))
2786 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2787 else if (IS_I865G(dev_priv))
2788 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2789 else if (IS_I85X(dev_priv))
2790 dev_priv->display.get_cdclk = i85x_get_cdclk;
2791 else if (IS_I845G(dev_priv))
2792 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2793 else { /* 830 */
2794 WARN(!IS_I830(dev_priv),
2795 "Unknown platform. Assuming 133 MHz CDCLK\n");
2796 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2797 }
2798}
Linux 6.x block layer and io_uring tree(s)