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7ff89ca2 VS |
1 | /* |
2 | * Copyright © 2006-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
fe4709a8 | 24 | #include "intel_atomic.h" |
e7674ef6 | 25 | #include "intel_cdclk.h" |
1d455f8d | 26 | #include "intel_display_types.h" |
56c5098f | 27 | #include "intel_sideband.h" |
7ff89ca2 VS |
28 | |
29 | /** | |
30 | * DOC: CDCLK / RAWCLK | |
31 | * | |
32 | * The display engine uses several different clocks to do its work. There | |
33 | * are two main clocks involved that aren't directly related to the actual | |
34 | * pixel clock or any symbol/bit clock of the actual output port. These | |
35 | * are the core display clock (CDCLK) and RAWCLK. | |
36 | * | |
37 | * CDCLK clocks most of the display pipe logic, and thus its frequency | |
38 | * must be high enough to support the rate at which pixels are flowing | |
39 | * through the pipes. Downscaling must also be accounted as that increases | |
40 | * the effective pixel rate. | |
41 | * | |
42 | * On several platforms the CDCLK frequency can be changed dynamically | |
43 | * to minimize power consumption for a given display configuration. | |
44 | * Typically changes to the CDCLK frequency require all the display pipes | |
45 | * to be shut down while the frequency is being changed. | |
46 | * | |
47 | * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. | |
48 | * DMC will not change the active CDCLK frequency however, so that part | |
49 | * will still be performed by the driver directly. | |
50 | * | |
51 | * RAWCLK is a fixed frequency clock, often used by various auxiliary | |
52 | * blocks such as AUX CH or backlight PWM. Hence the only thing we | |
53 | * really need to know about RAWCLK is its frequency so that various | |
54 | * dividers can be programmed correctly. | |
55 | */ | |
56 | ||
49cd97a3 VS |
57 | static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, |
58 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 59 | { |
49cd97a3 | 60 | cdclk_state->cdclk = 133333; |
7ff89ca2 VS |
61 | } |
62 | ||
49cd97a3 VS |
63 | static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, |
64 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 65 | { |
49cd97a3 | 66 | cdclk_state->cdclk = 200000; |
7ff89ca2 VS |
67 | } |
68 | ||
49cd97a3 VS |
69 | static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, |
70 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 71 | { |
49cd97a3 | 72 | cdclk_state->cdclk = 266667; |
7ff89ca2 VS |
73 | } |
74 | ||
49cd97a3 VS |
75 | static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, |
76 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 77 | { |
49cd97a3 | 78 | cdclk_state->cdclk = 333333; |
7ff89ca2 VS |
79 | } |
80 | ||
49cd97a3 VS |
81 | static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, |
82 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 83 | { |
49cd97a3 | 84 | cdclk_state->cdclk = 400000; |
7ff89ca2 VS |
85 | } |
86 | ||
49cd97a3 VS |
87 | static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, |
88 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 89 | { |
49cd97a3 | 90 | cdclk_state->cdclk = 450000; |
7ff89ca2 VS |
91 | } |
92 | ||
49cd97a3 VS |
93 | static void i85x_get_cdclk(struct drm_i915_private *dev_priv, |
94 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
95 | { |
96 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
97 | u16 hpllcc = 0; | |
98 | ||
99 | /* | |
100 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
101 | * encoding is different :( | |
102 | * FIXME is this the right way to detect 852GM/852GMV? | |
103 | */ | |
49cd97a3 VS |
104 | if (pdev->revision == 0x1) { |
105 | cdclk_state->cdclk = 133333; | |
106 | return; | |
107 | } | |
7ff89ca2 VS |
108 | |
109 | pci_bus_read_config_word(pdev->bus, | |
110 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
111 | ||
112 | /* Assume that the hardware is in the high speed state. This | |
113 | * should be the default. | |
114 | */ | |
115 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
116 | case GC_CLOCK_133_200: | |
117 | case GC_CLOCK_133_200_2: | |
118 | case GC_CLOCK_100_200: | |
49cd97a3 VS |
119 | cdclk_state->cdclk = 200000; |
120 | break; | |
7ff89ca2 | 121 | case GC_CLOCK_166_250: |
49cd97a3 VS |
122 | cdclk_state->cdclk = 250000; |
123 | break; | |
7ff89ca2 | 124 | case GC_CLOCK_100_133: |
49cd97a3 VS |
125 | cdclk_state->cdclk = 133333; |
126 | break; | |
7ff89ca2 VS |
127 | case GC_CLOCK_133_266: |
128 | case GC_CLOCK_133_266_2: | |
129 | case GC_CLOCK_166_266: | |
49cd97a3 VS |
130 | cdclk_state->cdclk = 266667; |
131 | break; | |
7ff89ca2 | 132 | } |
7ff89ca2 VS |
133 | } |
134 | ||
49cd97a3 VS |
135 | static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, |
136 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
137 | { |
138 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
139 | u16 gcfgc = 0; | |
140 | ||
141 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
142 | ||
49cd97a3 VS |
143 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
144 | cdclk_state->cdclk = 133333; | |
145 | return; | |
146 | } | |
7ff89ca2 VS |
147 | |
148 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
149 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
150 | cdclk_state->cdclk = 333333; |
151 | break; | |
7ff89ca2 VS |
152 | default: |
153 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
154 | cdclk_state->cdclk = 190000; |
155 | break; | |
7ff89ca2 VS |
156 | } |
157 | } | |
158 | ||
49cd97a3 VS |
159 | static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, |
160 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
161 | { |
162 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
163 | u16 gcfgc = 0; | |
164 | ||
165 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
166 | ||
49cd97a3 VS |
167 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { |
168 | cdclk_state->cdclk = 133333; | |
169 | return; | |
170 | } | |
7ff89ca2 VS |
171 | |
172 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
173 | case GC_DISPLAY_CLOCK_333_320_MHZ: | |
49cd97a3 VS |
174 | cdclk_state->cdclk = 320000; |
175 | break; | |
7ff89ca2 VS |
176 | default: |
177 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
49cd97a3 VS |
178 | cdclk_state->cdclk = 200000; |
179 | break; | |
7ff89ca2 VS |
180 | } |
181 | } | |
182 | ||
183 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) | |
184 | { | |
185 | static const unsigned int blb_vco[8] = { | |
186 | [0] = 3200000, | |
187 | [1] = 4000000, | |
188 | [2] = 5333333, | |
189 | [3] = 4800000, | |
190 | [4] = 6400000, | |
191 | }; | |
192 | static const unsigned int pnv_vco[8] = { | |
193 | [0] = 3200000, | |
194 | [1] = 4000000, | |
195 | [2] = 5333333, | |
196 | [3] = 4800000, | |
197 | [4] = 2666667, | |
198 | }; | |
199 | static const unsigned int cl_vco[8] = { | |
200 | [0] = 3200000, | |
201 | [1] = 4000000, | |
202 | [2] = 5333333, | |
203 | [3] = 6400000, | |
204 | [4] = 3333333, | |
205 | [5] = 3566667, | |
206 | [6] = 4266667, | |
207 | }; | |
208 | static const unsigned int elk_vco[8] = { | |
209 | [0] = 3200000, | |
210 | [1] = 4000000, | |
211 | [2] = 5333333, | |
212 | [3] = 4800000, | |
213 | }; | |
214 | static const unsigned int ctg_vco[8] = { | |
215 | [0] = 3200000, | |
216 | [1] = 4000000, | |
217 | [2] = 5333333, | |
218 | [3] = 6400000, | |
219 | [4] = 2666667, | |
220 | [5] = 4266667, | |
221 | }; | |
222 | const unsigned int *vco_table; | |
223 | unsigned int vco; | |
cbe974fb | 224 | u8 tmp = 0; |
7ff89ca2 VS |
225 | |
226 | /* FIXME other chipsets? */ | |
227 | if (IS_GM45(dev_priv)) | |
228 | vco_table = ctg_vco; | |
6b9e441d | 229 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
230 | vco_table = elk_vco; |
231 | else if (IS_I965GM(dev_priv)) | |
232 | vco_table = cl_vco; | |
233 | else if (IS_PINEVIEW(dev_priv)) | |
234 | vco_table = pnv_vco; | |
235 | else if (IS_G33(dev_priv)) | |
236 | vco_table = blb_vco; | |
237 | else | |
238 | return 0; | |
239 | ||
4677faf6 VS |
240 | tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? |
241 | HPLLVCO_MOBILE : HPLLVCO); | |
7ff89ca2 VS |
242 | |
243 | vco = vco_table[tmp & 0x7]; | |
244 | if (vco == 0) | |
245 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
246 | else | |
247 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
248 | ||
249 | return vco; | |
250 | } | |
251 | ||
49cd97a3 VS |
252 | static void g33_get_cdclk(struct drm_i915_private *dev_priv, |
253 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
254 | { |
255 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
cbe974fb JN |
256 | static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
257 | static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
258 | static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
259 | static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
260 | const u8 *div_table; | |
49cd97a3 | 261 | unsigned int cdclk_sel; |
cbe974fb | 262 | u16 tmp = 0; |
7ff89ca2 | 263 | |
49cd97a3 VS |
264 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
265 | ||
7ff89ca2 VS |
266 | pci_read_config_word(pdev, GCFGC, &tmp); |
267 | ||
268 | cdclk_sel = (tmp >> 4) & 0x7; | |
269 | ||
270 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
271 | goto fail; | |
272 | ||
49cd97a3 | 273 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
274 | case 3200000: |
275 | div_table = div_3200; | |
276 | break; | |
277 | case 4000000: | |
278 | div_table = div_4000; | |
279 | break; | |
280 | case 4800000: | |
281 | div_table = div_4800; | |
282 | break; | |
283 | case 5333333: | |
284 | div_table = div_5333; | |
285 | break; | |
286 | default: | |
287 | goto fail; | |
288 | } | |
289 | ||
49cd97a3 VS |
290 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
291 | div_table[cdclk_sel]); | |
292 | return; | |
7ff89ca2 VS |
293 | |
294 | fail: | |
295 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", | |
49cd97a3 VS |
296 | cdclk_state->vco, tmp); |
297 | cdclk_state->cdclk = 190476; | |
7ff89ca2 VS |
298 | } |
299 | ||
49cd97a3 VS |
300 | static void pnv_get_cdclk(struct drm_i915_private *dev_priv, |
301 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
302 | { |
303 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
304 | u16 gcfgc = 0; | |
305 | ||
306 | pci_read_config_word(pdev, GCFGC, &gcfgc); | |
307 | ||
308 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
309 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
49cd97a3 VS |
310 | cdclk_state->cdclk = 266667; |
311 | break; | |
7ff89ca2 | 312 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
49cd97a3 VS |
313 | cdclk_state->cdclk = 333333; |
314 | break; | |
7ff89ca2 | 315 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
49cd97a3 VS |
316 | cdclk_state->cdclk = 444444; |
317 | break; | |
7ff89ca2 | 318 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
49cd97a3 VS |
319 | cdclk_state->cdclk = 200000; |
320 | break; | |
7ff89ca2 VS |
321 | default: |
322 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
f0d759f0 | 323 | /* fall through */ |
7ff89ca2 | 324 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: |
49cd97a3 VS |
325 | cdclk_state->cdclk = 133333; |
326 | break; | |
7ff89ca2 | 327 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
49cd97a3 VS |
328 | cdclk_state->cdclk = 166667; |
329 | break; | |
7ff89ca2 VS |
330 | } |
331 | } | |
332 | ||
49cd97a3 VS |
333 | static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, |
334 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
335 | { |
336 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
cbe974fb JN |
337 | static const u8 div_3200[] = { 16, 10, 8 }; |
338 | static const u8 div_4000[] = { 20, 12, 10 }; | |
339 | static const u8 div_5333[] = { 24, 16, 14 }; | |
340 | const u8 *div_table; | |
49cd97a3 | 341 | unsigned int cdclk_sel; |
cbe974fb | 342 | u16 tmp = 0; |
7ff89ca2 | 343 | |
49cd97a3 VS |
344 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
345 | ||
7ff89ca2 VS |
346 | pci_read_config_word(pdev, GCFGC, &tmp); |
347 | ||
348 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
349 | ||
350 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
351 | goto fail; | |
352 | ||
49cd97a3 | 353 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
354 | case 3200000: |
355 | div_table = div_3200; | |
356 | break; | |
357 | case 4000000: | |
358 | div_table = div_4000; | |
359 | break; | |
360 | case 5333333: | |
361 | div_table = div_5333; | |
362 | break; | |
363 | default: | |
364 | goto fail; | |
365 | } | |
366 | ||
49cd97a3 VS |
367 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, |
368 | div_table[cdclk_sel]); | |
369 | return; | |
7ff89ca2 VS |
370 | |
371 | fail: | |
372 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", | |
49cd97a3 VS |
373 | cdclk_state->vco, tmp); |
374 | cdclk_state->cdclk = 200000; | |
7ff89ca2 VS |
375 | } |
376 | ||
49cd97a3 VS |
377 | static void gm45_get_cdclk(struct drm_i915_private *dev_priv, |
378 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
379 | { |
380 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
49cd97a3 | 381 | unsigned int cdclk_sel; |
cbe974fb | 382 | u16 tmp = 0; |
7ff89ca2 | 383 | |
49cd97a3 VS |
384 | cdclk_state->vco = intel_hpll_vco(dev_priv); |
385 | ||
7ff89ca2 VS |
386 | pci_read_config_word(pdev, GCFGC, &tmp); |
387 | ||
388 | cdclk_sel = (tmp >> 12) & 0x1; | |
389 | ||
49cd97a3 | 390 | switch (cdclk_state->vco) { |
7ff89ca2 VS |
391 | case 2666667: |
392 | case 4000000: | |
393 | case 5333333: | |
49cd97a3 VS |
394 | cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; |
395 | break; | |
7ff89ca2 | 396 | case 3200000: |
49cd97a3 VS |
397 | cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; |
398 | break; | |
7ff89ca2 VS |
399 | default: |
400 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", | |
49cd97a3 VS |
401 | cdclk_state->vco, tmp); |
402 | cdclk_state->cdclk = 222222; | |
403 | break; | |
7ff89ca2 VS |
404 | } |
405 | } | |
406 | ||
49cd97a3 VS |
407 | static void hsw_get_cdclk(struct drm_i915_private *dev_priv, |
408 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 409 | { |
cbe974fb JN |
410 | u32 lcpll = I915_READ(LCPLL_CTL); |
411 | u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7ff89ca2 VS |
412 | |
413 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 414 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 415 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 416 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 417 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 418 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 419 | else if (IS_HSW_ULT(dev_priv)) |
49cd97a3 | 420 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 421 | else |
49cd97a3 | 422 | cdclk_state->cdclk = 540000; |
7ff89ca2 VS |
423 | } |
424 | ||
d305e061 | 425 | static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) |
7ff89ca2 VS |
426 | { |
427 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? | |
428 | 333333 : 320000; | |
7ff89ca2 VS |
429 | |
430 | /* | |
431 | * We seem to get an unstable or solid color picture at 200MHz. | |
432 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
433 | * are off. | |
434 | */ | |
d305e061 | 435 | if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) |
7ff89ca2 | 436 | return 400000; |
d305e061 | 437 | else if (min_cdclk > 266667) |
7ff89ca2 | 438 | return freq_320; |
d305e061 | 439 | else if (min_cdclk > 0) |
7ff89ca2 VS |
440 | return 266667; |
441 | else | |
442 | return 200000; | |
443 | } | |
444 | ||
999c5766 VS |
445 | static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) |
446 | { | |
447 | if (IS_VALLEYVIEW(dev_priv)) { | |
448 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ | |
449 | return 2; | |
450 | else if (cdclk >= 266667) | |
451 | return 1; | |
452 | else | |
453 | return 0; | |
454 | } else { | |
455 | /* | |
456 | * Specs are full of misinformation, but testing on actual | |
457 | * hardware has shown that we just need to write the desired | |
458 | * CCK divider into the Punit register. | |
459 | */ | |
460 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
461 | } | |
462 | } | |
463 | ||
49cd97a3 VS |
464 | static void vlv_get_cdclk(struct drm_i915_private *dev_priv, |
465 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 466 | { |
999c5766 VS |
467 | u32 val; |
468 | ||
337fa6e0 CW |
469 | vlv_iosf_sb_get(dev_priv, |
470 | BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); | |
471 | ||
49cd97a3 VS |
472 | cdclk_state->vco = vlv_get_hpll_vco(dev_priv); |
473 | cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", | |
474 | CCK_DISPLAY_CLOCK_CONTROL, | |
475 | cdclk_state->vco); | |
999c5766 | 476 | |
c11b813f | 477 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); |
337fa6e0 CW |
478 | |
479 | vlv_iosf_sb_put(dev_priv, | |
480 | BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); | |
999c5766 VS |
481 | |
482 | if (IS_VALLEYVIEW(dev_priv)) | |
483 | cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> | |
484 | DSPFREQGUAR_SHIFT; | |
485 | else | |
486 | cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> | |
487 | DSPFREQGUAR_SHIFT_CHV; | |
7ff89ca2 VS |
488 | } |
489 | ||
490 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) | |
491 | { | |
492 | unsigned int credits, default_credits; | |
493 | ||
494 | if (IS_CHERRYVIEW(dev_priv)) | |
495 | default_credits = PFI_CREDIT(12); | |
496 | else | |
497 | default_credits = PFI_CREDIT(8); | |
498 | ||
49cd97a3 | 499 | if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { |
7ff89ca2 VS |
500 | /* CHV suggested value is 31 or 63 */ |
501 | if (IS_CHERRYVIEW(dev_priv)) | |
502 | credits = PFI_CREDIT_63; | |
503 | else | |
504 | credits = PFI_CREDIT(15); | |
505 | } else { | |
506 | credits = default_credits; | |
507 | } | |
508 | ||
509 | /* | |
510 | * WA - write default credits before re-programming | |
511 | * FIXME: should we also set the resend bit here? | |
512 | */ | |
513 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
514 | default_credits); | |
515 | ||
516 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
517 | credits | PFI_CREDIT_RESEND); | |
518 | ||
519 | /* | |
520 | * FIXME is this guaranteed to clear | |
521 | * immediately or should we poll for it? | |
522 | */ | |
523 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
524 | } | |
525 | ||
83c5fda7 | 526 | static void vlv_set_cdclk(struct drm_i915_private *dev_priv, |
59f9e9ca VS |
527 | const struct intel_cdclk_state *cdclk_state, |
528 | enum pipe pipe) | |
7ff89ca2 | 529 | { |
83c5fda7 | 530 | int cdclk = cdclk_state->cdclk; |
999c5766 | 531 | u32 val, cmd = cdclk_state->voltage_level; |
0e6e0be4 | 532 | intel_wakeref_t wakeref; |
7ff89ca2 | 533 | |
0c9f353f VS |
534 | switch (cdclk) { |
535 | case 400000: | |
536 | case 333333: | |
537 | case 320000: | |
538 | case 266667: | |
539 | case 200000: | |
540 | break; | |
541 | default: | |
542 | MISSING_CASE(cdclk); | |
543 | return; | |
544 | } | |
545 | ||
886015a0 GKB |
546 | /* There are cases where we can end up here with power domains |
547 | * off and a CDCLK frequency other than the minimum, like when | |
548 | * issuing a modeset without actually changing any display after | |
13ce6092 | 549 | * a system suspend. So grab the display core domain, which covers |
886015a0 GKB |
550 | * the HW blocks needed for the following programming. |
551 | */ | |
13ce6092 | 552 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); |
886015a0 | 553 | |
337fa6e0 CW |
554 | vlv_iosf_sb_get(dev_priv, |
555 | BIT(VLV_IOSF_SB_CCK) | | |
556 | BIT(VLV_IOSF_SB_BUNIT) | | |
557 | BIT(VLV_IOSF_SB_PUNIT)); | |
558 | ||
c11b813f | 559 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); |
7ff89ca2 VS |
560 | val &= ~DSPFREQGUAR_MASK; |
561 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
c11b813f VS |
562 | vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); |
563 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & | |
7ff89ca2 VS |
564 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), |
565 | 50)) { | |
566 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
567 | } | |
7ff89ca2 | 568 | |
7ff89ca2 VS |
569 | if (cdclk == 400000) { |
570 | u32 divider; | |
571 | ||
572 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, | |
573 | cdclk) - 1; | |
574 | ||
575 | /* adjust cdclk divider */ | |
576 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
577 | val &= ~CCK_FREQUENCY_VALUES; | |
578 | val |= divider; | |
579 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
580 | ||
581 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
582 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
583 | 50)) | |
584 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
585 | } | |
586 | ||
587 | /* adjust self-refresh exit latency value */ | |
588 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
589 | val &= ~0x7f; | |
590 | ||
591 | /* | |
592 | * For high bandwidth configs, we set a higher latency in the bunit | |
593 | * so that the core display fetch happens in time to avoid underruns. | |
594 | */ | |
595 | if (cdclk == 400000) | |
596 | val |= 4500 / 250; /* 4.5 usec */ | |
597 | else | |
598 | val |= 3000 / 250; /* 3.0 usec */ | |
599 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
600 | ||
221c7862 | 601 | vlv_iosf_sb_put(dev_priv, |
337fa6e0 CW |
602 | BIT(VLV_IOSF_SB_CCK) | |
603 | BIT(VLV_IOSF_SB_BUNIT) | | |
604 | BIT(VLV_IOSF_SB_PUNIT)); | |
7ff89ca2 VS |
605 | |
606 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
607 | |
608 | vlv_program_pfi_credits(dev_priv); | |
886015a0 | 609 | |
13ce6092 | 610 | intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); |
7ff89ca2 VS |
611 | } |
612 | ||
83c5fda7 | 613 | static void chv_set_cdclk(struct drm_i915_private *dev_priv, |
59f9e9ca VS |
614 | const struct intel_cdclk_state *cdclk_state, |
615 | enum pipe pipe) | |
7ff89ca2 | 616 | { |
83c5fda7 | 617 | int cdclk = cdclk_state->cdclk; |
999c5766 | 618 | u32 val, cmd = cdclk_state->voltage_level; |
0e6e0be4 | 619 | intel_wakeref_t wakeref; |
7ff89ca2 | 620 | |
7ff89ca2 VS |
621 | switch (cdclk) { |
622 | case 333333: | |
623 | case 320000: | |
624 | case 266667: | |
625 | case 200000: | |
626 | break; | |
627 | default: | |
628 | MISSING_CASE(cdclk); | |
629 | return; | |
630 | } | |
631 | ||
886015a0 GKB |
632 | /* There are cases where we can end up here with power domains |
633 | * off and a CDCLK frequency other than the minimum, like when | |
634 | * issuing a modeset without actually changing any display after | |
13ce6092 | 635 | * a system suspend. So grab the display core domain, which covers |
886015a0 GKB |
636 | * the HW blocks needed for the following programming. |
637 | */ | |
13ce6092 | 638 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); |
886015a0 | 639 | |
337fa6e0 | 640 | vlv_punit_get(dev_priv); |
c11b813f | 641 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); |
7ff89ca2 VS |
642 | val &= ~DSPFREQGUAR_MASK_CHV; |
643 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
c11b813f VS |
644 | vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); |
645 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & | |
7ff89ca2 VS |
646 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), |
647 | 50)) { | |
648 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
649 | } | |
337fa6e0 CW |
650 | |
651 | vlv_punit_put(dev_priv); | |
7ff89ca2 VS |
652 | |
653 | intel_update_cdclk(dev_priv); | |
1a5301a5 VS |
654 | |
655 | vlv_program_pfi_credits(dev_priv); | |
886015a0 | 656 | |
13ce6092 | 657 | intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); |
7ff89ca2 VS |
658 | } |
659 | ||
d305e061 | 660 | static int bdw_calc_cdclk(int min_cdclk) |
7ff89ca2 | 661 | { |
d305e061 | 662 | if (min_cdclk > 540000) |
7ff89ca2 | 663 | return 675000; |
d305e061 | 664 | else if (min_cdclk > 450000) |
7ff89ca2 | 665 | return 540000; |
d305e061 | 666 | else if (min_cdclk > 337500) |
7ff89ca2 VS |
667 | return 450000; |
668 | else | |
669 | return 337500; | |
670 | } | |
671 | ||
d7ffaeef VS |
672 | static u8 bdw_calc_voltage_level(int cdclk) |
673 | { | |
674 | switch (cdclk) { | |
675 | default: | |
676 | case 337500: | |
677 | return 2; | |
678 | case 450000: | |
679 | return 0; | |
680 | case 540000: | |
681 | return 1; | |
682 | case 675000: | |
683 | return 3; | |
684 | } | |
685 | } | |
686 | ||
49cd97a3 VS |
687 | static void bdw_get_cdclk(struct drm_i915_private *dev_priv, |
688 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 689 | { |
cbe974fb JN |
690 | u32 lcpll = I915_READ(LCPLL_CTL); |
691 | u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7ff89ca2 VS |
692 | |
693 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
49cd97a3 | 694 | cdclk_state->cdclk = 800000; |
7ff89ca2 | 695 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
49cd97a3 | 696 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 697 | else if (freq == LCPLL_CLK_FREQ_450) |
49cd97a3 | 698 | cdclk_state->cdclk = 450000; |
7ff89ca2 | 699 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) |
49cd97a3 | 700 | cdclk_state->cdclk = 540000; |
7ff89ca2 | 701 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) |
49cd97a3 | 702 | cdclk_state->cdclk = 337500; |
7ff89ca2 | 703 | else |
49cd97a3 | 704 | cdclk_state->cdclk = 675000; |
d7ffaeef VS |
705 | |
706 | /* | |
707 | * Can't read this out :( Let's assume it's | |
708 | * at least what the CDCLK frequency requires. | |
709 | */ | |
710 | cdclk_state->voltage_level = | |
711 | bdw_calc_voltage_level(cdclk_state->cdclk); | |
7ff89ca2 VS |
712 | } |
713 | ||
83c5fda7 | 714 | static void bdw_set_cdclk(struct drm_i915_private *dev_priv, |
59f9e9ca VS |
715 | const struct intel_cdclk_state *cdclk_state, |
716 | enum pipe pipe) | |
7ff89ca2 | 717 | { |
83c5fda7 | 718 | int cdclk = cdclk_state->cdclk; |
cbe974fb | 719 | u32 val; |
7ff89ca2 VS |
720 | int ret; |
721 | ||
722 | if (WARN((I915_READ(LCPLL_CTL) & | |
723 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
724 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
725 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
726 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
727 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
728 | return; | |
729 | ||
7ff89ca2 VS |
730 | ret = sandybridge_pcode_write(dev_priv, |
731 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
7ff89ca2 VS |
732 | if (ret) { |
733 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
734 | return; | |
735 | } | |
736 | ||
737 | val = I915_READ(LCPLL_CTL); | |
738 | val |= LCPLL_CD_SOURCE_FCLK; | |
739 | I915_WRITE(LCPLL_CTL, val); | |
740 | ||
3164888a ML |
741 | /* |
742 | * According to the spec, it should be enough to poll for this 1 us. | |
743 | * However, extensive testing shows that this can take longer. | |
744 | */ | |
7ff89ca2 | 745 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
3164888a | 746 | LCPLL_CD_SOURCE_FCLK_DONE, 100)) |
7ff89ca2 VS |
747 | DRM_ERROR("Switching to FCLK failed\n"); |
748 | ||
749 | val = I915_READ(LCPLL_CTL); | |
750 | val &= ~LCPLL_CLK_FREQ_MASK; | |
751 | ||
752 | switch (cdclk) { | |
2b58417f VS |
753 | default: |
754 | MISSING_CASE(cdclk); | |
755 | /* fall through */ | |
756 | case 337500: | |
757 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
2b58417f | 758 | break; |
7ff89ca2 VS |
759 | case 450000: |
760 | val |= LCPLL_CLK_FREQ_450; | |
7ff89ca2 VS |
761 | break; |
762 | case 540000: | |
763 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
7ff89ca2 | 764 | break; |
7ff89ca2 VS |
765 | case 675000: |
766 | val |= LCPLL_CLK_FREQ_675_BDW; | |
7ff89ca2 | 767 | break; |
7ff89ca2 VS |
768 | } |
769 | ||
770 | I915_WRITE(LCPLL_CTL, val); | |
771 | ||
772 | val = I915_READ(LCPLL_CTL); | |
773 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
774 | I915_WRITE(LCPLL_CTL, val); | |
775 | ||
776 | if (wait_for_us((I915_READ(LCPLL_CTL) & | |
777 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
778 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
779 | ||
d7ffaeef VS |
780 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
781 | cdclk_state->voltage_level); | |
7ff89ca2 VS |
782 | |
783 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); | |
784 | ||
785 | intel_update_cdclk(dev_priv); | |
7ff89ca2 VS |
786 | } |
787 | ||
d305e061 | 788 | static int skl_calc_cdclk(int min_cdclk, int vco) |
7ff89ca2 VS |
789 | { |
790 | if (vco == 8640000) { | |
d305e061 | 791 | if (min_cdclk > 540000) |
7ff89ca2 | 792 | return 617143; |
d305e061 | 793 | else if (min_cdclk > 432000) |
7ff89ca2 | 794 | return 540000; |
d305e061 | 795 | else if (min_cdclk > 308571) |
7ff89ca2 VS |
796 | return 432000; |
797 | else | |
798 | return 308571; | |
799 | } else { | |
d305e061 | 800 | if (min_cdclk > 540000) |
7ff89ca2 | 801 | return 675000; |
d305e061 | 802 | else if (min_cdclk > 450000) |
7ff89ca2 | 803 | return 540000; |
d305e061 | 804 | else if (min_cdclk > 337500) |
7ff89ca2 VS |
805 | return 450000; |
806 | else | |
807 | return 337500; | |
808 | } | |
809 | } | |
810 | ||
2aa97491 VS |
811 | static u8 skl_calc_voltage_level(int cdclk) |
812 | { | |
522d47cf | 813 | if (cdclk > 540000) |
2aa97491 | 814 | return 3; |
522d47cf LDM |
815 | else if (cdclk > 450000) |
816 | return 2; | |
817 | else if (cdclk > 337500) | |
818 | return 1; | |
819 | else | |
820 | return 0; | |
2aa97491 VS |
821 | } |
822 | ||
49cd97a3 VS |
823 | static void skl_dpll0_update(struct drm_i915_private *dev_priv, |
824 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
825 | { |
826 | u32 val; | |
827 | ||
49cd97a3 VS |
828 | cdclk_state->ref = 24000; |
829 | cdclk_state->vco = 0; | |
7ff89ca2 VS |
830 | |
831 | val = I915_READ(LCPLL1_CTL); | |
832 | if ((val & LCPLL_PLL_ENABLE) == 0) | |
833 | return; | |
834 | ||
835 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) | |
836 | return; | |
837 | ||
838 | val = I915_READ(DPLL_CTRL1); | |
839 | ||
840 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | | |
841 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
842 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
843 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
844 | return; | |
845 | ||
846 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { | |
847 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
848 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
849 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
850 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
49cd97a3 | 851 | cdclk_state->vco = 8100000; |
7ff89ca2 VS |
852 | break; |
853 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
854 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
49cd97a3 | 855 | cdclk_state->vco = 8640000; |
7ff89ca2 VS |
856 | break; |
857 | default: | |
858 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
859 | break; | |
860 | } | |
861 | } | |
862 | ||
49cd97a3 VS |
863 | static void skl_get_cdclk(struct drm_i915_private *dev_priv, |
864 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
865 | { |
866 | u32 cdctl; | |
867 | ||
49cd97a3 | 868 | skl_dpll0_update(dev_priv, cdclk_state); |
7ff89ca2 | 869 | |
b6c51c3e | 870 | cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; |
49cd97a3 VS |
871 | |
872 | if (cdclk_state->vco == 0) | |
2aa97491 | 873 | goto out; |
7ff89ca2 VS |
874 | |
875 | cdctl = I915_READ(CDCLK_CTL); | |
876 | ||
49cd97a3 | 877 | if (cdclk_state->vco == 8640000) { |
7ff89ca2 VS |
878 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
879 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
880 | cdclk_state->cdclk = 432000; |
881 | break; | |
7ff89ca2 | 882 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
883 | cdclk_state->cdclk = 308571; |
884 | break; | |
7ff89ca2 | 885 | case CDCLK_FREQ_540: |
49cd97a3 VS |
886 | cdclk_state->cdclk = 540000; |
887 | break; | |
7ff89ca2 | 888 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
889 | cdclk_state->cdclk = 617143; |
890 | break; | |
7ff89ca2 VS |
891 | default: |
892 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 893 | break; |
7ff89ca2 VS |
894 | } |
895 | } else { | |
896 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
897 | case CDCLK_FREQ_450_432: | |
49cd97a3 VS |
898 | cdclk_state->cdclk = 450000; |
899 | break; | |
7ff89ca2 | 900 | case CDCLK_FREQ_337_308: |
49cd97a3 VS |
901 | cdclk_state->cdclk = 337500; |
902 | break; | |
7ff89ca2 | 903 | case CDCLK_FREQ_540: |
49cd97a3 VS |
904 | cdclk_state->cdclk = 540000; |
905 | break; | |
7ff89ca2 | 906 | case CDCLK_FREQ_675_617: |
49cd97a3 VS |
907 | cdclk_state->cdclk = 675000; |
908 | break; | |
7ff89ca2 VS |
909 | default: |
910 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); | |
49cd97a3 | 911 | break; |
7ff89ca2 VS |
912 | } |
913 | } | |
2aa97491 VS |
914 | |
915 | out: | |
916 | /* | |
917 | * Can't read this out :( Let's assume it's | |
918 | * at least what the CDCLK frequency requires. | |
919 | */ | |
920 | cdclk_state->voltage_level = | |
921 | skl_calc_voltage_level(cdclk_state->cdclk); | |
7ff89ca2 VS |
922 | } |
923 | ||
924 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
925 | static int skl_cdclk_decimal(int cdclk) | |
926 | { | |
927 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
928 | } | |
929 | ||
930 | static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, | |
931 | int vco) | |
932 | { | |
933 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
934 | ||
935 | dev_priv->skl_preferred_vco_freq = vco; | |
936 | ||
937 | if (changed) | |
938 | intel_update_max_cdclk(dev_priv); | |
939 | } | |
940 | ||
941 | static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) | |
942 | { | |
7ff89ca2 VS |
943 | u32 val; |
944 | ||
945 | WARN_ON(vco != 8100000 && vco != 8640000); | |
946 | ||
7ff89ca2 VS |
947 | /* |
948 | * We always enable DPLL0 with the lowest link rate possible, but still | |
949 | * taking into account the VCO required to operate the eDP panel at the | |
950 | * desired frequency. The usual DP link rates operate with a VCO of | |
951 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
952 | * The modeset code is responsible for the selection of the exact link | |
953 | * rate later on, with the constraint of choosing a frequency that | |
954 | * works with vco. | |
955 | */ | |
956 | val = I915_READ(DPLL_CTRL1); | |
957 | ||
958 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
959 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
960 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
961 | if (vco == 8640000) | |
962 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
963 | SKL_DPLL0); | |
964 | else | |
965 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
966 | SKL_DPLL0); | |
967 | ||
968 | I915_WRITE(DPLL_CTRL1, val); | |
969 | POSTING_READ(DPLL_CTRL1); | |
970 | ||
971 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
972 | ||
4cb3b44d | 973 | if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) |
7ff89ca2 VS |
974 | DRM_ERROR("DPLL0 not locked\n"); |
975 | ||
49cd97a3 | 976 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
977 | |
978 | /* We'll want to keep using the current vco from now on. */ | |
979 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
980 | } | |
981 | ||
982 | static void skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
983 | { | |
984 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
4cb3b44d | 985 | if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) |
7ff89ca2 VS |
986 | DRM_ERROR("Couldn't disable DPLL0\n"); |
987 | ||
49cd97a3 | 988 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
989 | } |
990 | ||
991 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, | |
59f9e9ca VS |
992 | const struct intel_cdclk_state *cdclk_state, |
993 | enum pipe pipe) | |
7ff89ca2 | 994 | { |
83c5fda7 VS |
995 | int cdclk = cdclk_state->cdclk; |
996 | int vco = cdclk_state->vco; | |
53421c2f | 997 | u32 freq_select, cdclk_ctl; |
7ff89ca2 VS |
998 | int ret; |
999 | ||
602a9de5 ID |
1000 | /* |
1001 | * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are | |
1002 | * unsupported on SKL. In theory this should never happen since only | |
1003 | * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not | |
1004 | * supported on SKL either, see the above WA. WARN whenever trying to | |
1005 | * use the corresponding VCO freq as that always leads to using the | |
1006 | * minimum 308MHz CDCLK. | |
1007 | */ | |
1008 | WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); | |
1009 | ||
7ff89ca2 VS |
1010 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
1011 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
1012 | SKL_CDCLK_READY_FOR_CHANGE, | |
1013 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
7ff89ca2 VS |
1014 | if (ret) { |
1015 | DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", | |
1016 | ret); | |
1017 | return; | |
1018 | } | |
1019 | ||
53421c2f | 1020 | /* Choose frequency for this cdclk */ |
7ff89ca2 | 1021 | switch (cdclk) { |
2b58417f | 1022 | default: |
b6c51c3e | 1023 | WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); |
2b58417f VS |
1024 | WARN_ON(vco != 0); |
1025 | /* fall through */ | |
1026 | case 308571: | |
1027 | case 337500: | |
1028 | freq_select = CDCLK_FREQ_337_308; | |
2b58417f | 1029 | break; |
7ff89ca2 VS |
1030 | case 450000: |
1031 | case 432000: | |
1032 | freq_select = CDCLK_FREQ_450_432; | |
7ff89ca2 VS |
1033 | break; |
1034 | case 540000: | |
1035 | freq_select = CDCLK_FREQ_540; | |
7ff89ca2 | 1036 | break; |
7ff89ca2 VS |
1037 | case 617143: |
1038 | case 675000: | |
1039 | freq_select = CDCLK_FREQ_675_617; | |
7ff89ca2 VS |
1040 | break; |
1041 | } | |
1042 | ||
49cd97a3 VS |
1043 | if (dev_priv->cdclk.hw.vco != 0 && |
1044 | dev_priv->cdclk.hw.vco != vco) | |
7ff89ca2 VS |
1045 | skl_dpll0_disable(dev_priv); |
1046 | ||
53421c2f LDM |
1047 | cdclk_ctl = I915_READ(CDCLK_CTL); |
1048 | ||
1049 | if (dev_priv->cdclk.hw.vco != vco) { | |
1050 | /* Wa Display #1183: skl,kbl,cfl */ | |
1051 | cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); | |
1052 | cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); | |
1053 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1054 | } | |
1055 | ||
1056 | /* Wa Display #1183: skl,kbl,cfl */ | |
1057 | cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; | |
1058 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1059 | POSTING_READ(CDCLK_CTL); | |
1060 | ||
49cd97a3 | 1061 | if (dev_priv->cdclk.hw.vco != vco) |
7ff89ca2 VS |
1062 | skl_dpll0_enable(dev_priv, vco); |
1063 | ||
53421c2f LDM |
1064 | /* Wa Display #1183: skl,kbl,cfl */ |
1065 | cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); | |
1066 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1067 | ||
1068 | cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); | |
1069 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
1070 | ||
1071 | /* Wa Display #1183: skl,kbl,cfl */ | |
1072 | cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; | |
1073 | I915_WRITE(CDCLK_CTL, cdclk_ctl); | |
7ff89ca2 VS |
1074 | POSTING_READ(CDCLK_CTL); |
1075 | ||
1076 | /* inform PCU of the change */ | |
2aa97491 VS |
1077 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, |
1078 | cdclk_state->voltage_level); | |
7ff89ca2 VS |
1079 | |
1080 | intel_update_cdclk(dev_priv); | |
1081 | } | |
1082 | ||
1083 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1084 | { | |
cbe974fb | 1085 | u32 cdctl, expected; |
7ff89ca2 VS |
1086 | |
1087 | /* | |
1088 | * check if the pre-os initialized the display | |
1089 | * There is SWF18 scratchpad register defined which is set by the | |
1090 | * pre-os which can be used by the OS drivers to check the status | |
1091 | */ | |
1092 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
1093 | goto sanitize; | |
1094 | ||
1095 | intel_update_cdclk(dev_priv); | |
cfddadc9 VS |
1096 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); |
1097 | ||
7ff89ca2 | 1098 | /* Is PLL enabled and locked ? */ |
49cd97a3 | 1099 | if (dev_priv->cdclk.hw.vco == 0 || |
b6c51c3e | 1100 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) |
7ff89ca2 VS |
1101 | goto sanitize; |
1102 | ||
1103 | /* DPLL okay; verify the cdclock | |
1104 | * | |
1105 | * Noticed in some instances that the freq selection is correct but | |
1106 | * decimal part is programmed wrong from BIOS where pre-os does not | |
1107 | * enable display. Verify the same as well. | |
1108 | */ | |
1109 | cdctl = I915_READ(CDCLK_CTL); | |
1110 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
49cd97a3 | 1111 | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); |
7ff89ca2 VS |
1112 | if (cdctl == expected) |
1113 | /* All well; nothing to sanitize */ | |
1114 | return; | |
1115 | ||
1116 | sanitize: | |
1117 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1118 | ||
1119 | /* force cdclk programming */ | |
49cd97a3 | 1120 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 | 1121 | /* force full PLL disable + enable */ |
49cd97a3 | 1122 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1123 | } |
1124 | ||
93a643f2 | 1125 | static void skl_init_cdclk(struct drm_i915_private *dev_priv) |
7ff89ca2 | 1126 | { |
83c5fda7 | 1127 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1128 | |
1129 | skl_sanitize_cdclk(dev_priv); | |
1130 | ||
49cd97a3 VS |
1131 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1132 | dev_priv->cdclk.hw.vco != 0) { | |
7ff89ca2 VS |
1133 | /* |
1134 | * Use the current vco as our initial | |
1135 | * guess as to what the preferred vco is. | |
1136 | */ | |
1137 | if (dev_priv->skl_preferred_vco_freq == 0) | |
1138 | skl_set_preferred_cdclk_vco(dev_priv, | |
49cd97a3 | 1139 | dev_priv->cdclk.hw.vco); |
7ff89ca2 VS |
1140 | return; |
1141 | } | |
1142 | ||
83c5fda7 VS |
1143 | cdclk_state = dev_priv->cdclk.hw; |
1144 | ||
1145 | cdclk_state.vco = dev_priv->skl_preferred_vco_freq; | |
1146 | if (cdclk_state.vco == 0) | |
1147 | cdclk_state.vco = 8100000; | |
1148 | cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); | |
2aa97491 | 1149 | cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); |
7ff89ca2 | 1150 | |
59f9e9ca | 1151 | skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); |
7ff89ca2 VS |
1152 | } |
1153 | ||
93a643f2 | 1154 | static void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
7ff89ca2 | 1155 | { |
83c5fda7 VS |
1156 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1157 | ||
b6c51c3e | 1158 | cdclk_state.cdclk = cdclk_state.bypass; |
83c5fda7 | 1159 | cdclk_state.vco = 0; |
2aa97491 | 1160 | cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); |
83c5fda7 | 1161 | |
59f9e9ca | 1162 | skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); |
7ff89ca2 VS |
1163 | } |
1164 | ||
736da811 MR |
1165 | static const struct intel_cdclk_vals bxt_cdclk_table[] = { |
1166 | { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, | |
1167 | { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, | |
1168 | { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, | |
1169 | { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, | |
1170 | { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, | |
1171 | {} | |
1172 | }; | |
1173 | ||
1174 | static const struct intel_cdclk_vals glk_cdclk_table[] = { | |
1175 | { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, | |
1176 | { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, | |
1177 | { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, | |
1178 | {} | |
1179 | }; | |
1180 | ||
1181 | static const struct intel_cdclk_vals cnl_cdclk_table[] = { | |
1182 | { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 }, | |
1183 | { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 }, | |
1184 | { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 }, | |
1185 | ||
1186 | { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 }, | |
1187 | { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 }, | |
1188 | { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 }, | |
1189 | {} | |
1190 | }; | |
1191 | ||
1192 | static const struct intel_cdclk_vals icl_cdclk_table[] = { | |
1193 | { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, | |
1194 | { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, | |
1195 | { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, | |
1196 | { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, | |
1197 | { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, | |
1198 | { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, | |
1199 | ||
1200 | { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, | |
1201 | { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, | |
1202 | { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, | |
1203 | { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, | |
1204 | { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, | |
1205 | { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, | |
1206 | ||
1207 | { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, | |
1208 | { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, | |
1209 | { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, | |
1210 | { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, | |
1211 | { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, | |
1212 | { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, | |
1213 | {} | |
1214 | }; | |
1215 | ||
1216 | static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) | |
1217 | { | |
1218 | const struct intel_cdclk_vals *table = dev_priv->cdclk.table; | |
1219 | int i; | |
1220 | ||
1221 | for (i = 0; table[i].refclk; i++) | |
1222 | if (table[i].refclk == dev_priv->cdclk.hw.ref && | |
1223 | table[i].cdclk >= min_cdclk) | |
1224 | return table[i].cdclk; | |
1225 | ||
1226 | WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n", | |
1227 | min_cdclk, dev_priv->cdclk.hw.ref); | |
1228 | return 0; | |
7ff89ca2 VS |
1229 | } |
1230 | ||
736da811 | 1231 | static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
7ff89ca2 | 1232 | { |
736da811 MR |
1233 | const struct intel_cdclk_vals *table = dev_priv->cdclk.table; |
1234 | int i; | |
1235 | ||
1236 | if (cdclk == dev_priv->cdclk.hw.bypass) | |
1237 | return 0; | |
1238 | ||
1239 | for (i = 0; table[i].refclk; i++) | |
1240 | if (table[i].refclk == dev_priv->cdclk.hw.ref && | |
1241 | table[i].cdclk == cdclk) | |
1242 | return dev_priv->cdclk.hw.ref * table[i].ratio; | |
1243 | ||
1244 | WARN(1, "cdclk %d not valid for refclk %u\n", | |
1245 | cdclk, dev_priv->cdclk.hw.ref); | |
1246 | return 0; | |
7ff89ca2 VS |
1247 | } |
1248 | ||
2123f442 VS |
1249 | static u8 bxt_calc_voltage_level(int cdclk) |
1250 | { | |
1251 | return DIV_ROUND_UP(cdclk, 25000); | |
1252 | } | |
1253 | ||
71dc367e MR |
1254 | static u8 cnl_calc_voltage_level(int cdclk) |
1255 | { | |
1256 | if (cdclk > 336000) | |
1257 | return 2; | |
1258 | else if (cdclk > 168000) | |
1259 | return 1; | |
1260 | else | |
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | static u8 icl_calc_voltage_level(int cdclk) | |
1265 | { | |
1266 | if (cdclk > 556800) | |
1267 | return 2; | |
1268 | else if (cdclk > 312000) | |
1269 | return 1; | |
1270 | else | |
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | static u8 ehl_calc_voltage_level(int cdclk) | |
1275 | { | |
1276 | if (cdclk > 312000) | |
1277 | return 2; | |
1278 | else if (cdclk > 180000) | |
1279 | return 1; | |
1280 | else | |
1281 | return 0; | |
1282 | } | |
1283 | ||
71dc367e MR |
1284 | static void cnl_readout_refclk(struct drm_i915_private *dev_priv, |
1285 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 | 1286 | { |
71dc367e MR |
1287 | if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) |
1288 | cdclk_state->ref = 24000; | |
1289 | else | |
1290 | cdclk_state->ref = 19200; | |
1291 | } | |
7ff89ca2 | 1292 | |
71dc367e MR |
1293 | static void icl_readout_refclk(struct drm_i915_private *dev_priv, |
1294 | struct intel_cdclk_state *cdclk_state) | |
1295 | { | |
1296 | u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; | |
1297 | ||
1298 | switch (dssm) { | |
1299 | default: | |
1300 | MISSING_CASE(dssm); | |
1301 | /* fall through */ | |
1302 | case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: | |
1303 | cdclk_state->ref = 24000; | |
1304 | break; | |
1305 | case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: | |
1306 | cdclk_state->ref = 19200; | |
1307 | break; | |
1308 | case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: | |
1309 | cdclk_state->ref = 38400; | |
1310 | break; | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, | |
1315 | struct intel_cdclk_state *cdclk_state) | |
1316 | { | |
1317 | u32 val, ratio; | |
1318 | ||
1319 | if (INTEL_GEN(dev_priv) >= 11) | |
1320 | icl_readout_refclk(dev_priv, cdclk_state); | |
1321 | else if (IS_CANNONLAKE(dev_priv)) | |
1322 | cnl_readout_refclk(dev_priv, cdclk_state); | |
1323 | else | |
1324 | cdclk_state->ref = 19200; | |
7ff89ca2 VS |
1325 | |
1326 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
71dc367e MR |
1327 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || |
1328 | (val & BXT_DE_PLL_LOCK) == 0) { | |
1329 | /* | |
1330 | * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but | |
1331 | * setting it to zero is a way to signal that. | |
1332 | */ | |
1333 | cdclk_state->vco = 0; | |
7ff89ca2 | 1334 | return; |
71dc367e | 1335 | } |
7ff89ca2 | 1336 | |
71dc367e MR |
1337 | /* |
1338 | * CNL+ have the ratio directly in the PLL enable register, gen9lp had | |
1339 | * it in a separate PLL control register. | |
1340 | */ | |
1341 | if (INTEL_GEN(dev_priv) >= 10) | |
1342 | ratio = val & CNL_CDCLK_PLL_RATIO_MASK; | |
1343 | else | |
1344 | ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
7ff89ca2 | 1345 | |
71dc367e | 1346 | cdclk_state->vco = ratio * cdclk_state->ref; |
7ff89ca2 VS |
1347 | } |
1348 | ||
49cd97a3 VS |
1349 | static void bxt_get_cdclk(struct drm_i915_private *dev_priv, |
1350 | struct intel_cdclk_state *cdclk_state) | |
7ff89ca2 VS |
1351 | { |
1352 | u32 divider; | |
49cd97a3 | 1353 | int div; |
7ff89ca2 | 1354 | |
74689ddf VS |
1355 | bxt_de_pll_readout(dev_priv, cdclk_state); |
1356 | ||
71dc367e MR |
1357 | if (INTEL_GEN(dev_priv) >= 12) |
1358 | cdclk_state->bypass = cdclk_state->ref / 2; | |
1359 | else if (INTEL_GEN(dev_priv) >= 11) | |
1360 | cdclk_state->bypass = 50000; | |
1361 | else | |
1362 | cdclk_state->bypass = cdclk_state->ref; | |
49cd97a3 | 1363 | |
71dc367e MR |
1364 | if (cdclk_state->vco == 0) { |
1365 | cdclk_state->cdclk = cdclk_state->bypass; | |
2123f442 | 1366 | goto out; |
71dc367e | 1367 | } |
7ff89ca2 VS |
1368 | |
1369 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
1370 | ||
1371 | switch (divider) { | |
1372 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
1373 | div = 2; | |
1374 | break; | |
1375 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
71dc367e MR |
1376 | WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, |
1377 | "Unsupported divider\n"); | |
7ff89ca2 VS |
1378 | div = 3; |
1379 | break; | |
1380 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
1381 | div = 4; | |
1382 | break; | |
1383 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
71dc367e | 1384 | WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n"); |
7ff89ca2 VS |
1385 | div = 8; |
1386 | break; | |
1387 | default: | |
1388 | MISSING_CASE(divider); | |
49cd97a3 | 1389 | return; |
7ff89ca2 VS |
1390 | } |
1391 | ||
49cd97a3 | 1392 | cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); |
2123f442 VS |
1393 | |
1394 | out: | |
1395 | /* | |
1396 | * Can't read this out :( Let's assume it's | |
1397 | * at least what the CDCLK frequency requires. | |
1398 | */ | |
d2f429eb MR |
1399 | cdclk_state->voltage_level = |
1400 | dev_priv->display.calc_voltage_level(cdclk_state->cdclk); | |
7ff89ca2 VS |
1401 | } |
1402 | ||
1403 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) | |
1404 | { | |
1405 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
1406 | ||
1407 | /* Timeout 200us */ | |
4cb3b44d DCS |
1408 | if (intel_de_wait_for_clear(dev_priv, |
1409 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) | |
7ff89ca2 VS |
1410 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
1411 | ||
49cd97a3 | 1412 | dev_priv->cdclk.hw.vco = 0; |
7ff89ca2 VS |
1413 | } |
1414 | ||
1415 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1416 | { | |
49cd97a3 | 1417 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); |
7ff89ca2 VS |
1418 | u32 val; |
1419 | ||
1420 | val = I915_READ(BXT_DE_PLL_CTL); | |
1421 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
1422 | val |= BXT_DE_PLL_RATIO(ratio); | |
1423 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
1424 | ||
1425 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
1426 | ||
1427 | /* Timeout 200us */ | |
4cb3b44d DCS |
1428 | if (intel_de_wait_for_set(dev_priv, |
1429 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) | |
7ff89ca2 VS |
1430 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
1431 | ||
49cd97a3 | 1432 | dev_priv->cdclk.hw.vco = vco; |
7ff89ca2 VS |
1433 | } |
1434 | ||
1cbcd3b4 MR |
1435 | static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) |
1436 | { | |
1437 | u32 val; | |
1438 | ||
1439 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1440 | val &= ~BXT_DE_PLL_PLL_ENABLE; | |
1441 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1442 | ||
1443 | /* Timeout 200us */ | |
1444 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) | |
1445 | DRM_ERROR("timeout waiting for CDCLK PLL unlock\n"); | |
1446 | ||
1447 | dev_priv->cdclk.hw.vco = 0; | |
1448 | } | |
1449 | ||
1450 | static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) | |
1451 | { | |
1452 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); | |
1453 | u32 val; | |
1454 | ||
1455 | val = CNL_CDCLK_PLL_RATIO(ratio); | |
1456 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1457 | ||
1458 | val |= BXT_DE_PLL_PLL_ENABLE; | |
1459 | I915_WRITE(BXT_DE_PLL_ENABLE, val); | |
1460 | ||
1461 | /* Timeout 200us */ | |
1462 | if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) | |
1463 | DRM_ERROR("timeout waiting for CDCLK PLL lock\n"); | |
1464 | ||
1465 | dev_priv->cdclk.hw.vco = vco; | |
1466 | } | |
1467 | ||
0a12e437 VS |
1468 | static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
1469 | { | |
1470 | if (INTEL_GEN(dev_priv) >= 12) { | |
1471 | if (pipe == INVALID_PIPE) | |
1472 | return TGL_CDCLK_CD2X_PIPE_NONE; | |
1473 | else | |
1474 | return TGL_CDCLK_CD2X_PIPE(pipe); | |
1475 | } else if (INTEL_GEN(dev_priv) >= 11) { | |
1476 | if (pipe == INVALID_PIPE) | |
1477 | return ICL_CDCLK_CD2X_PIPE_NONE; | |
1478 | else | |
1479 | return ICL_CDCLK_CD2X_PIPE(pipe); | |
1480 | } else { | |
1481 | if (pipe == INVALID_PIPE) | |
1482 | return BXT_CDCLK_CD2X_PIPE_NONE; | |
1483 | else | |
1484 | return BXT_CDCLK_CD2X_PIPE(pipe); | |
1485 | } | |
1486 | } | |
1487 | ||
8f0cfa4d | 1488 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, |
59f9e9ca VS |
1489 | const struct intel_cdclk_state *cdclk_state, |
1490 | enum pipe pipe) | |
7ff89ca2 | 1491 | { |
83c5fda7 VS |
1492 | int cdclk = cdclk_state->cdclk; |
1493 | int vco = cdclk_state->vco; | |
7ff89ca2 | 1494 | u32 val, divider; |
8f0cfa4d | 1495 | int ret; |
7ff89ca2 | 1496 | |
1cbcd3b4 MR |
1497 | /* Inform power controller of upcoming frequency change. */ |
1498 | if (INTEL_GEN(dev_priv) >= 10) | |
1499 | ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
1500 | SKL_CDCLK_PREPARE_FOR_CHANGE, | |
1501 | SKL_CDCLK_READY_FOR_CHANGE, | |
1502 | SKL_CDCLK_READY_FOR_CHANGE, 3); | |
1503 | else | |
1504 | /* | |
1505 | * BSpec requires us to wait up to 150usec, but that leads to | |
1506 | * timeouts; the 2ms used here is based on experiment. | |
1507 | */ | |
1508 | ret = sandybridge_pcode_write_timeout(dev_priv, | |
1509 | HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1510 | 0x80000000, 150, 2); | |
1511 | ||
1512 | if (ret) { | |
1513 | DRM_ERROR("Failed to inform PCU about cdclk change (err %d, freq %d)\n", | |
1514 | ret, cdclk); | |
1515 | return; | |
1516 | } | |
1517 | ||
7ff89ca2 VS |
1518 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ |
1519 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
2b58417f | 1520 | default: |
b6c51c3e | 1521 | WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); |
2b58417f VS |
1522 | WARN_ON(vco != 0); |
1523 | /* fall through */ | |
1524 | case 2: | |
1525 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
7ff89ca2 VS |
1526 | break; |
1527 | case 3: | |
1cbcd3b4 MR |
1528 | WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, |
1529 | "Unsupported divider\n"); | |
7ff89ca2 VS |
1530 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
1531 | break; | |
2b58417f VS |
1532 | case 4: |
1533 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
7ff89ca2 | 1534 | break; |
2b58417f | 1535 | case 8: |
1cbcd3b4 | 1536 | WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n"); |
2b58417f | 1537 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
7ff89ca2 VS |
1538 | break; |
1539 | } | |
1540 | ||
1cbcd3b4 MR |
1541 | if (INTEL_GEN(dev_priv) >= 10) { |
1542 | if (dev_priv->cdclk.hw.vco != 0 && | |
1543 | dev_priv->cdclk.hw.vco != vco) | |
1544 | cnl_cdclk_pll_disable(dev_priv); | |
7ff89ca2 | 1545 | |
1cbcd3b4 MR |
1546 | if (dev_priv->cdclk.hw.vco != vco) |
1547 | cnl_cdclk_pll_enable(dev_priv, vco); | |
7ff89ca2 | 1548 | |
1cbcd3b4 MR |
1549 | } else { |
1550 | if (dev_priv->cdclk.hw.vco != 0 && | |
1551 | dev_priv->cdclk.hw.vco != vco) | |
1552 | bxt_de_pll_disable(dev_priv); | |
1553 | ||
1554 | if (dev_priv->cdclk.hw.vco != vco) | |
1555 | bxt_de_pll_enable(dev_priv, vco); | |
1556 | } | |
7ff89ca2 | 1557 | |
0a12e437 VS |
1558 | val = divider | skl_cdclk_decimal(cdclk) | |
1559 | bxt_cdclk_cd2x_pipe(dev_priv, pipe); | |
1cbcd3b4 | 1560 | |
7ff89ca2 VS |
1561 | /* |
1562 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1563 | * enable otherwise. | |
1564 | */ | |
1cbcd3b4 | 1565 | if (IS_GEN9_LP(dev_priv) && cdclk >= 500000) |
7ff89ca2 VS |
1566 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
1567 | I915_WRITE(CDCLK_CTL, val); | |
1568 | ||
59f9e9ca VS |
1569 | if (pipe != INVALID_PIPE) |
1570 | intel_wait_for_vblank(dev_priv, pipe); | |
1571 | ||
1cbcd3b4 MR |
1572 | if (INTEL_GEN(dev_priv) >= 10) { |
1573 | ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, | |
1574 | cdclk_state->voltage_level); | |
1575 | } else { | |
1576 | /* | |
1577 | * The timeout isn't specified, the 2ms used here is based on | |
1578 | * experiment. | |
1579 | * FIXME: Waiting for the request completion could be delayed | |
1580 | * until the next PCODE request based on BSpec. | |
1581 | */ | |
1582 | ret = sandybridge_pcode_write_timeout(dev_priv, | |
1583 | HSW_PCODE_DE_WRITE_FREQ_REQ, | |
1584 | cdclk_state->voltage_level, | |
1585 | 150, 2); | |
1586 | } | |
1587 | ||
7ff89ca2 VS |
1588 | if (ret) { |
1589 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
1590 | ret, cdclk); | |
1591 | return; | |
1592 | } | |
1593 | ||
1594 | intel_update_cdclk(dev_priv); | |
1cbcd3b4 MR |
1595 | |
1596 | if (INTEL_GEN(dev_priv) >= 10) | |
1597 | /* | |
1598 | * Can't read out the voltage level :( | |
1599 | * Let's just assume everything is as expected. | |
1600 | */ | |
1601 | dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; | |
7ff89ca2 VS |
1602 | } |
1603 | ||
1604 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) | |
1605 | { | |
1606 | u32 cdctl, expected; | |
8f9f717d | 1607 | int cdclk, vco; |
7ff89ca2 VS |
1608 | |
1609 | intel_update_cdclk(dev_priv); | |
cfddadc9 | 1610 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); |
7ff89ca2 | 1611 | |
49cd97a3 | 1612 | if (dev_priv->cdclk.hw.vco == 0 || |
b6c51c3e | 1613 | dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) |
7ff89ca2 VS |
1614 | goto sanitize; |
1615 | ||
1616 | /* DPLL okay; verify the cdclock | |
1617 | * | |
1618 | * Some BIOS versions leave an incorrect decimal frequency value and | |
1619 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
1620 | * so sanitize this register. | |
1621 | */ | |
1622 | cdctl = I915_READ(CDCLK_CTL); | |
1623 | /* | |
1624 | * Let's ignore the pipe field, since BIOS could have configured the | |
1625 | * dividers both synching to an active pipe, or asynchronously | |
1626 | * (PIPE_NONE). | |
1627 | */ | |
0a12e437 | 1628 | cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); |
7ff89ca2 | 1629 | |
8f9f717d MR |
1630 | /* Make sure this is a legal cdclk value for the platform */ |
1631 | cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); | |
1632 | if (cdclk != dev_priv->cdclk.hw.cdclk) | |
1633 | goto sanitize; | |
1634 | ||
1635 | /* Make sure the VCO is correct for the cdclk */ | |
1636 | vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); | |
1637 | if (vco != dev_priv->cdclk.hw.vco) | |
1638 | goto sanitize; | |
1639 | ||
1640 | expected = skl_cdclk_decimal(cdclk); | |
1641 | ||
1642 | /* Figure out what CD2X divider we should be using for this cdclk */ | |
1643 | switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco, | |
1644 | dev_priv->cdclk.hw.cdclk)) { | |
1645 | case 2: | |
1646 | expected |= BXT_CDCLK_CD2X_DIV_SEL_1; | |
1647 | break; | |
1648 | case 3: | |
1649 | expected |= BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
1650 | break; | |
1651 | case 4: | |
1652 | expected |= BXT_CDCLK_CD2X_DIV_SEL_2; | |
1653 | break; | |
1654 | case 8: | |
1655 | expected |= BXT_CDCLK_CD2X_DIV_SEL_4; | |
1656 | break; | |
1657 | default: | |
1658 | goto sanitize; | |
1659 | } | |
1660 | ||
7ff89ca2 VS |
1661 | /* |
1662 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
1663 | * enable otherwise. | |
1664 | */ | |
5dac256b | 1665 | if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000) |
7ff89ca2 VS |
1666 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
1667 | ||
1668 | if (cdctl == expected) | |
1669 | /* All well; nothing to sanitize */ | |
1670 | return; | |
1671 | ||
1672 | sanitize: | |
1673 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
1674 | ||
1675 | /* force cdclk programming */ | |
49cd97a3 | 1676 | dev_priv->cdclk.hw.cdclk = 0; |
7ff89ca2 VS |
1677 | |
1678 | /* force full PLL disable + enable */ | |
49cd97a3 | 1679 | dev_priv->cdclk.hw.vco = -1; |
7ff89ca2 VS |
1680 | } |
1681 | ||
93a643f2 | 1682 | static void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
7ff89ca2 | 1683 | { |
83c5fda7 | 1684 | struct intel_cdclk_state cdclk_state; |
7ff89ca2 VS |
1685 | |
1686 | bxt_sanitize_cdclk(dev_priv); | |
1687 | ||
49cd97a3 VS |
1688 | if (dev_priv->cdclk.hw.cdclk != 0 && |
1689 | dev_priv->cdclk.hw.vco != 0) | |
7ff89ca2 VS |
1690 | return; |
1691 | ||
83c5fda7 VS |
1692 | cdclk_state = dev_priv->cdclk.hw; |
1693 | ||
7ff89ca2 VS |
1694 | /* |
1695 | * FIXME: | |
1696 | * - The initial CDCLK needs to be read from VBT. | |
1697 | * Need to make this change after VBT has changes for BXT. | |
1698 | */ | |
736da811 MR |
1699 | cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0); |
1700 | cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); | |
d2f429eb MR |
1701 | cdclk_state.voltage_level = |
1702 | dev_priv->display.calc_voltage_level(cdclk_state.cdclk); | |
7ff89ca2 | 1703 | |
59f9e9ca | 1704 | bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); |
7ff89ca2 VS |
1705 | } |
1706 | ||
93a643f2 | 1707 | static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
7ff89ca2 | 1708 | { |
83c5fda7 VS |
1709 | struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; |
1710 | ||
b6c51c3e | 1711 | cdclk_state.cdclk = cdclk_state.bypass; |
83c5fda7 | 1712 | cdclk_state.vco = 0; |
d2f429eb MR |
1713 | cdclk_state.voltage_level = |
1714 | dev_priv->display.calc_voltage_level(cdclk_state.cdclk); | |
83c5fda7 | 1715 | |
59f9e9ca | 1716 | bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); |
49cd97a3 VS |
1717 | } |
1718 | ||
93a643f2 JN |
1719 | /** |
1720 | * intel_cdclk_init - Initialize CDCLK | |
1721 | * @i915: i915 device | |
1722 | * | |
1723 | * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and | |
1724 | * sanitizing the state of the hardware if needed. This is generally done only | |
1725 | * during the display core initialization sequence, after which the DMC will | |
1726 | * take care of turning CDCLK off/on as needed. | |
1727 | */ | |
1728 | void intel_cdclk_init(struct drm_i915_private *i915) | |
1729 | { | |
0c1279b5 MR |
1730 | if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) |
1731 | bxt_init_cdclk(i915); | |
93a643f2 JN |
1732 | else if (IS_GEN9_BC(i915)) |
1733 | skl_init_cdclk(i915); | |
93a643f2 JN |
1734 | } |
1735 | ||
1736 | /** | |
1737 | * intel_cdclk_uninit - Uninitialize CDCLK | |
1738 | * @i915: i915 device | |
1739 | * | |
1740 | * Uninitialize CDCLK. This is done only during the display core | |
1741 | * uninitialization sequence. | |
1742 | */ | |
1743 | void intel_cdclk_uninit(struct drm_i915_private *i915) | |
1744 | { | |
751a93a1 MR |
1745 | if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915)) |
1746 | bxt_uninit_cdclk(i915); | |
93a643f2 JN |
1747 | else if (IS_GEN9_BC(i915)) |
1748 | skl_uninit_cdclk(i915); | |
93a643f2 JN |
1749 | } |
1750 | ||
49cd97a3 | 1751 | /** |
64600bd5 | 1752 | * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes |
49cd97a3 VS |
1753 | * @a: first CDCLK state |
1754 | * @b: second CDCLK state | |
1755 | * | |
1756 | * Returns: | |
64600bd5 | 1757 | * True if the CDCLK states require pipes to be off during reprogramming, false if not. |
49cd97a3 | 1758 | */ |
64600bd5 | 1759 | bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, |
49cd97a3 VS |
1760 | const struct intel_cdclk_state *b) |
1761 | { | |
64600bd5 VS |
1762 | return a->cdclk != b->cdclk || |
1763 | a->vco != b->vco || | |
1764 | a->ref != b->ref; | |
1765 | } | |
1766 | ||
59f9e9ca VS |
1767 | /** |
1768 | * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update | |
8fb44c1d | 1769 | * @dev_priv: Not a CDCLK state, it's the drm_i915_private! |
59f9e9ca VS |
1770 | * @a: first CDCLK state |
1771 | * @b: second CDCLK state | |
1772 | * | |
1773 | * Returns: | |
1774 | * True if the CDCLK states require just a cd2x divider update, false if not. | |
1775 | */ | |
fe4709a8 VS |
1776 | static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, |
1777 | const struct intel_cdclk_state *a, | |
1778 | const struct intel_cdclk_state *b) | |
59f9e9ca VS |
1779 | { |
1780 | /* Older hw doesn't have the capability */ | |
1781 | if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) | |
1782 | return false; | |
1783 | ||
1784 | return a->cdclk != b->cdclk && | |
1785 | a->vco == b->vco && | |
1786 | a->ref == b->ref; | |
1787 | } | |
1788 | ||
64600bd5 VS |
1789 | /** |
1790 | * intel_cdclk_changed - Determine if two CDCLK states are different | |
1791 | * @a: first CDCLK state | |
1792 | * @b: second CDCLK state | |
1793 | * | |
1794 | * Returns: | |
1795 | * True if the CDCLK states don't match, false if they do. | |
1796 | */ | |
fe4709a8 VS |
1797 | static bool intel_cdclk_changed(const struct intel_cdclk_state *a, |
1798 | const struct intel_cdclk_state *b) | |
64600bd5 VS |
1799 | { |
1800 | return intel_cdclk_needs_modeset(a, b) || | |
1801 | a->voltage_level != b->voltage_level; | |
7ff89ca2 VS |
1802 | } |
1803 | ||
48d9f87d ID |
1804 | /** |
1805 | * intel_cdclk_swap_state - make atomic CDCLK configuration effective | |
1806 | * @state: atomic state | |
1807 | * | |
1808 | * This is the CDCLK version of drm_atomic_helper_swap_state() since the | |
1809 | * helper does not handle driver-specific global state. | |
1810 | * | |
1811 | * Similarly to the atomic helpers this function does a complete swap, | |
1812 | * i.e. it also puts the old state into @state. This is used by the commit | |
1813 | * code to determine how CDCLK has changed (for instance did it increase or | |
1814 | * decrease). | |
1815 | */ | |
1816 | void intel_cdclk_swap_state(struct intel_atomic_state *state) | |
1817 | { | |
1818 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
1819 | ||
1820 | swap(state->cdclk.logical, dev_priv->cdclk.logical); | |
1821 | swap(state->cdclk.actual, dev_priv->cdclk.actual); | |
1822 | } | |
1823 | ||
cfddadc9 VS |
1824 | void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, |
1825 | const char *context) | |
1826 | { | |
b6c51c3e | 1827 | DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", |
cfddadc9 | 1828 | context, cdclk_state->cdclk, cdclk_state->vco, |
b6c51c3e ID |
1829 | cdclk_state->ref, cdclk_state->bypass, |
1830 | cdclk_state->voltage_level); | |
cfddadc9 VS |
1831 | } |
1832 | ||
b0587e4d VS |
1833 | /** |
1834 | * intel_set_cdclk - Push the CDCLK state to the hardware | |
1835 | * @dev_priv: i915 device | |
1836 | * @cdclk_state: new CDCLK state | |
59f9e9ca | 1837 | * @pipe: pipe with which to synchronize the update |
b0587e4d VS |
1838 | * |
1839 | * Program the hardware based on the passed in CDCLK state, | |
1840 | * if necessary. | |
1841 | */ | |
59f9e9ca VS |
1842 | static void intel_set_cdclk(struct drm_i915_private *dev_priv, |
1843 | const struct intel_cdclk_state *cdclk_state, | |
1844 | enum pipe pipe) | |
b0587e4d | 1845 | { |
64600bd5 | 1846 | if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) |
b0587e4d VS |
1847 | return; |
1848 | ||
1849 | if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) | |
1850 | return; | |
1851 | ||
cfddadc9 | 1852 | intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); |
b0587e4d | 1853 | |
59f9e9ca | 1854 | dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe); |
cfddadc9 VS |
1855 | |
1856 | if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), | |
1857 | "cdclk state doesn't match!\n")) { | |
1858 | intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); | |
1859 | intel_dump_cdclk_state(cdclk_state, "[sw state]"); | |
1860 | } | |
b0587e4d VS |
1861 | } |
1862 | ||
59f9e9ca VS |
1863 | /** |
1864 | * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware | |
1865 | * @dev_priv: i915 device | |
1866 | * @old_state: old CDCLK state | |
1867 | * @new_state: new CDCLK state | |
1868 | * @pipe: pipe with which to synchronize the update | |
1869 | * | |
1870 | * Program the hardware before updating the HW plane state based on the passed | |
1871 | * in CDCLK state, if necessary. | |
1872 | */ | |
1873 | void | |
1874 | intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, | |
1875 | const struct intel_cdclk_state *old_state, | |
1876 | const struct intel_cdclk_state *new_state, | |
1877 | enum pipe pipe) | |
1878 | { | |
1879 | if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) | |
1880 | intel_set_cdclk(dev_priv, new_state, pipe); | |
1881 | } | |
1882 | ||
1883 | /** | |
1884 | * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware | |
1885 | * @dev_priv: i915 device | |
1886 | * @old_state: old CDCLK state | |
1887 | * @new_state: new CDCLK state | |
1888 | * @pipe: pipe with which to synchronize the update | |
1889 | * | |
1890 | * Program the hardware after updating the HW plane state based on the passed | |
1891 | * in CDCLK state, if necessary. | |
1892 | */ | |
1893 | void | |
1894 | intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, | |
1895 | const struct intel_cdclk_state *old_state, | |
1896 | const struct intel_cdclk_state *new_state, | |
1897 | enum pipe pipe) | |
1898 | { | |
1899 | if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) | |
1900 | intel_set_cdclk(dev_priv, new_state, pipe); | |
1901 | } | |
1902 | ||
3e30d708 | 1903 | static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) |
d305e061 | 1904 | { |
3e30d708 VS |
1905 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
1906 | int pixel_rate = crtc_state->pixel_rate; | |
1907 | ||
42882336 | 1908 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
43037c86 | 1909 | return DIV_ROUND_UP(pixel_rate, 2); |
cf819eff | 1910 | else if (IS_GEN(dev_priv, 9) || |
d305e061 VS |
1911 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) |
1912 | return pixel_rate; | |
1913 | else if (IS_CHERRYVIEW(dev_priv)) | |
1914 | return DIV_ROUND_UP(pixel_rate * 100, 95); | |
3e30d708 VS |
1915 | else if (crtc_state->double_wide) |
1916 | return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); | |
d305e061 VS |
1917 | else |
1918 | return DIV_ROUND_UP(pixel_rate * 100, 90); | |
1919 | } | |
1920 | ||
1921 | int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) | |
7ff89ca2 VS |
1922 | { |
1923 | struct drm_i915_private *dev_priv = | |
1924 | to_i915(crtc_state->base.crtc->dev); | |
d305e061 VS |
1925 | int min_cdclk; |
1926 | ||
1927 | if (!crtc_state->base.enable) | |
1928 | return 0; | |
1929 | ||
3e30d708 | 1930 | min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); |
7ff89ca2 VS |
1931 | |
1932 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
24f28450 | 1933 | if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) |
d305e061 | 1934 | min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); |
7ff89ca2 | 1935 | |
78cfa580 PD |
1936 | /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, |
1937 | * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else | |
1938 | * there may be audio corruption or screen corruption." This cdclk | |
d305e061 | 1939 | * restriction for GLK is 316.8 MHz. |
7ff89ca2 VS |
1940 | */ |
1941 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
1942 | crtc_state->has_audio && | |
1943 | crtc_state->port_clock >= 540000 && | |
78cfa580 | 1944 | crtc_state->lane_count == 4) { |
d305e061 VS |
1945 | if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { |
1946 | /* Display WA #1145: glk,cnl */ | |
1947 | min_cdclk = max(316800, min_cdclk); | |
cf819eff | 1948 | } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { |
d305e061 VS |
1949 | /* Display WA #1144: skl,bxt */ |
1950 | min_cdclk = max(432000, min_cdclk); | |
1951 | } | |
78cfa580 | 1952 | } |
7ff89ca2 | 1953 | |
904e1b1f AK |
1954 | /* |
1955 | * According to BSpec, "The CD clock frequency must be at least twice | |
8cbeb06d | 1956 | * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. |
8cbeb06d | 1957 | */ |
905801fe | 1958 | if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) |
d305e061 | 1959 | min_cdclk = max(2 * 96000, min_cdclk); |
8cbeb06d | 1960 | |
bffb31f7 VS |
1961 | /* |
1962 | * "For DP audio configuration, cdclk frequency shall be set to | |
1963 | * meet the following requirements: | |
1964 | * DP Link Frequency(MHz) | Cdclk frequency(MHz) | |
1965 | * 270 | 320 or higher | |
1966 | * 162 | 200 or higher" | |
1967 | */ | |
1968 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && | |
1969 | intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) | |
1970 | min_cdclk = max(crtc_state->port_clock, min_cdclk); | |
1971 | ||
c8dae55a HG |
1972 | /* |
1973 | * On Valleyview some DSI panels lose (v|h)sync when the clock is lower | |
1974 | * than 320000KHz. | |
1975 | */ | |
1976 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && | |
1977 | IS_VALLEYVIEW(dev_priv)) | |
1978 | min_cdclk = max(320000, min_cdclk); | |
1979 | ||
beb29980 SL |
1980 | /* |
1981 | * On Geminilake once the CDCLK gets as low as 79200 | |
1982 | * picture gets unstable, despite that values are | |
1983 | * correct for DSI PLL and DE PLL. | |
1984 | */ | |
1985 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && | |
1986 | IS_GEMINILAKE(dev_priv)) | |
1987 | min_cdclk = max(158400, min_cdclk); | |
1988 | ||
9c61de4c VS |
1989 | if (min_cdclk > dev_priv->max_cdclk_freq) { |
1990 | DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", | |
1991 | min_cdclk, dev_priv->max_cdclk_freq); | |
1992 | return -EINVAL; | |
1993 | } | |
1994 | ||
d305e061 | 1995 | return min_cdclk; |
7ff89ca2 VS |
1996 | } |
1997 | ||
8b67896e | 1998 | static int intel_compute_min_cdclk(struct intel_atomic_state *state) |
7ff89ca2 | 1999 | { |
8b67896e | 2000 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
d305e061 | 2001 | struct intel_crtc *crtc; |
7ff89ca2 | 2002 | struct intel_crtc_state *crtc_state; |
9c61de4c | 2003 | int min_cdclk, i; |
7ff89ca2 VS |
2004 | enum pipe pipe; |
2005 | ||
8b67896e VS |
2006 | memcpy(state->min_cdclk, dev_priv->min_cdclk, |
2007 | sizeof(state->min_cdclk)); | |
7ff89ca2 | 2008 | |
8b67896e | 2009 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { |
9c61de4c VS |
2010 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); |
2011 | if (min_cdclk < 0) | |
2012 | return min_cdclk; | |
2013 | ||
8b67896e | 2014 | state->min_cdclk[i] = min_cdclk; |
9c61de4c | 2015 | } |
7ff89ca2 | 2016 | |
8b67896e | 2017 | min_cdclk = state->cdclk.force_min_cdclk; |
7ff89ca2 | 2018 | for_each_pipe(dev_priv, pipe) |
8b67896e | 2019 | min_cdclk = max(state->min_cdclk[pipe], min_cdclk); |
7ff89ca2 | 2020 | |
d305e061 | 2021 | return min_cdclk; |
7ff89ca2 VS |
2022 | } |
2023 | ||
53e9bf5e | 2024 | /* |
933122cc VS |
2025 | * Account for port clock min voltage level requirements. |
2026 | * This only really does something on CNL+ but can be | |
2027 | * called on earlier platforms as well. | |
2028 | * | |
53e9bf5e VS |
2029 | * Note that this functions assumes that 0 is |
2030 | * the lowest voltage value, and higher values | |
2031 | * correspond to increasingly higher voltages. | |
2032 | * | |
2033 | * Should that relationship no longer hold on | |
2034 | * future platforms this code will need to be | |
2035 | * adjusted. | |
2036 | */ | |
933122cc | 2037 | static u8 bxt_compute_min_voltage_level(struct intel_atomic_state *state) |
53e9bf5e VS |
2038 | { |
2039 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
2040 | struct intel_crtc *crtc; | |
2041 | struct intel_crtc_state *crtc_state; | |
2042 | u8 min_voltage_level; | |
2043 | int i; | |
2044 | enum pipe pipe; | |
2045 | ||
2046 | memcpy(state->min_voltage_level, dev_priv->min_voltage_level, | |
2047 | sizeof(state->min_voltage_level)); | |
2048 | ||
2049 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { | |
2050 | if (crtc_state->base.enable) | |
2051 | state->min_voltage_level[i] = | |
2052 | crtc_state->min_voltage_level; | |
2053 | else | |
2054 | state->min_voltage_level[i] = 0; | |
2055 | } | |
2056 | ||
2057 | min_voltage_level = 0; | |
2058 | for_each_pipe(dev_priv, pipe) | |
2059 | min_voltage_level = max(state->min_voltage_level[pipe], | |
2060 | min_voltage_level); | |
2061 | ||
2062 | return min_voltage_level; | |
2063 | } | |
2064 | ||
8b67896e | 2065 | static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) |
7ff89ca2 | 2066 | { |
8b67896e | 2067 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
9c61de4c | 2068 | int min_cdclk, cdclk; |
bb0f4aab | 2069 | |
9c61de4c VS |
2070 | min_cdclk = intel_compute_min_cdclk(state); |
2071 | if (min_cdclk < 0) | |
2072 | return min_cdclk; | |
7ff89ca2 | 2073 | |
9c61de4c | 2074 | cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); |
7ff89ca2 | 2075 | |
8b67896e VS |
2076 | state->cdclk.logical.cdclk = cdclk; |
2077 | state->cdclk.logical.voltage_level = | |
999c5766 | 2078 | vlv_calc_voltage_level(dev_priv, cdclk); |
bb0f4aab | 2079 | |
d06a79d3 | 2080 | if (!state->active_pipes) { |
8b67896e | 2081 | cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); |
bb0f4aab | 2082 | |
8b67896e VS |
2083 | state->cdclk.actual.cdclk = cdclk; |
2084 | state->cdclk.actual.voltage_level = | |
999c5766 | 2085 | vlv_calc_voltage_level(dev_priv, cdclk); |
bb0f4aab | 2086 | } else { |
8b67896e | 2087 | state->cdclk.actual = state->cdclk.logical; |
bb0f4aab | 2088 | } |
7ff89ca2 VS |
2089 | |
2090 | return 0; | |
2091 | } | |
2092 | ||
8b67896e | 2093 | static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) |
7ff89ca2 | 2094 | { |
9c61de4c VS |
2095 | int min_cdclk, cdclk; |
2096 | ||
2097 | min_cdclk = intel_compute_min_cdclk(state); | |
2098 | if (min_cdclk < 0) | |
2099 | return min_cdclk; | |
7ff89ca2 VS |
2100 | |
2101 | /* | |
2102 | * FIXME should also account for plane ratio | |
2103 | * once 64bpp pixel formats are supported. | |
2104 | */ | |
d305e061 | 2105 | cdclk = bdw_calc_cdclk(min_cdclk); |
7ff89ca2 | 2106 | |
8b67896e VS |
2107 | state->cdclk.logical.cdclk = cdclk; |
2108 | state->cdclk.logical.voltage_level = | |
d7ffaeef | 2109 | bdw_calc_voltage_level(cdclk); |
bb0f4aab | 2110 | |
d06a79d3 | 2111 | if (!state->active_pipes) { |
8b67896e | 2112 | cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk); |
bb0f4aab | 2113 | |
8b67896e VS |
2114 | state->cdclk.actual.cdclk = cdclk; |
2115 | state->cdclk.actual.voltage_level = | |
d7ffaeef | 2116 | bdw_calc_voltage_level(cdclk); |
bb0f4aab | 2117 | } else { |
8b67896e | 2118 | state->cdclk.actual = state->cdclk.logical; |
bb0f4aab | 2119 | } |
7ff89ca2 VS |
2120 | |
2121 | return 0; | |
2122 | } | |
2123 | ||
8b67896e | 2124 | static int skl_dpll0_vco(struct intel_atomic_state *state) |
3297234a | 2125 | { |
8b67896e | 2126 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
3297234a RV |
2127 | struct intel_crtc *crtc; |
2128 | struct intel_crtc_state *crtc_state; | |
2129 | int vco, i; | |
2130 | ||
8b67896e | 2131 | vco = state->cdclk.logical.vco; |
3297234a RV |
2132 | if (!vco) |
2133 | vco = dev_priv->skl_preferred_vco_freq; | |
2134 | ||
8b67896e | 2135 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { |
3297234a RV |
2136 | if (!crtc_state->base.enable) |
2137 | continue; | |
2138 | ||
2139 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) | |
2140 | continue; | |
2141 | ||
2142 | /* | |
2143 | * DPLL0 VCO may need to be adjusted to get the correct | |
2144 | * clock for eDP. This will affect cdclk as well. | |
2145 | */ | |
2146 | switch (crtc_state->port_clock / 2) { | |
2147 | case 108000: | |
2148 | case 216000: | |
2149 | vco = 8640000; | |
2150 | break; | |
2151 | default: | |
2152 | vco = 8100000; | |
2153 | break; | |
2154 | } | |
2155 | } | |
2156 | ||
2157 | return vco; | |
2158 | } | |
2159 | ||
8b67896e | 2160 | static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) |
7ff89ca2 | 2161 | { |
9c61de4c VS |
2162 | int min_cdclk, cdclk, vco; |
2163 | ||
2164 | min_cdclk = intel_compute_min_cdclk(state); | |
2165 | if (min_cdclk < 0) | |
2166 | return min_cdclk; | |
bb0f4aab | 2167 | |
8b67896e | 2168 | vco = skl_dpll0_vco(state); |
7ff89ca2 VS |
2169 | |
2170 | /* | |
2171 | * FIXME should also account for plane ratio | |
2172 | * once 64bpp pixel formats are supported. | |
2173 | */ | |
d305e061 | 2174 | cdclk = skl_calc_cdclk(min_cdclk, vco); |
7ff89ca2 | 2175 | |
8b67896e VS |
2176 | state->cdclk.logical.vco = vco; |
2177 | state->cdclk.logical.cdclk = cdclk; | |
2178 | state->cdclk.logical.voltage_level = | |
2aa97491 | 2179 | skl_calc_voltage_level(cdclk); |
bb0f4aab | 2180 | |
d06a79d3 | 2181 | if (!state->active_pipes) { |
8b67896e | 2182 | cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco); |
bb0f4aab | 2183 | |
8b67896e VS |
2184 | state->cdclk.actual.vco = vco; |
2185 | state->cdclk.actual.cdclk = cdclk; | |
2186 | state->cdclk.actual.voltage_level = | |
2aa97491 | 2187 | skl_calc_voltage_level(cdclk); |
bb0f4aab | 2188 | } else { |
8b67896e | 2189 | state->cdclk.actual = state->cdclk.logical; |
bb0f4aab | 2190 | } |
7ff89ca2 VS |
2191 | |
2192 | return 0; | |
2193 | } | |
2194 | ||
8b67896e | 2195 | static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) |
7ff89ca2 | 2196 | { |
8b67896e | 2197 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); |
9c61de4c VS |
2198 | int min_cdclk, cdclk, vco; |
2199 | ||
2200 | min_cdclk = intel_compute_min_cdclk(state); | |
2201 | if (min_cdclk < 0) | |
2202 | return min_cdclk; | |
7ff89ca2 | 2203 | |
736da811 MR |
2204 | cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); |
2205 | vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); | |
bb0f4aab | 2206 | |
8b67896e VS |
2207 | state->cdclk.logical.vco = vco; |
2208 | state->cdclk.logical.cdclk = cdclk; | |
d2f429eb MR |
2209 | state->cdclk.logical.voltage_level = |
2210 | max(dev_priv->display.calc_voltage_level(cdclk), | |
933122cc | 2211 | bxt_compute_min_voltage_level(state)); |
186a277e | 2212 | |
d06a79d3 | 2213 | if (!state->active_pipes) { |
736da811 MR |
2214 | cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); |
2215 | vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); | |
186a277e | 2216 | |
8b67896e VS |
2217 | state->cdclk.actual.vco = vco; |
2218 | state->cdclk.actual.cdclk = cdclk; | |
d2f429eb MR |
2219 | state->cdclk.actual.voltage_level = |
2220 | dev_priv->display.calc_voltage_level(cdclk); | |
186a277e | 2221 | } else { |
8b67896e | 2222 | state->cdclk.actual = state->cdclk.logical; |
186a277e PZ |
2223 | } |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
fe4709a8 VS |
2228 | static int intel_lock_all_pipes(struct intel_atomic_state *state) |
2229 | { | |
2230 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
2231 | struct intel_crtc *crtc; | |
2232 | ||
2233 | /* Add all pipes to the state */ | |
2234 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
2235 | struct intel_crtc_state *crtc_state; | |
2236 | ||
2237 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
2238 | if (IS_ERR(crtc_state)) | |
2239 | return PTR_ERR(crtc_state); | |
2240 | } | |
2241 | ||
2242 | return 0; | |
2243 | } | |
2244 | ||
2245 | static int intel_modeset_all_pipes(struct intel_atomic_state *state) | |
2246 | { | |
2247 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
2248 | struct intel_crtc *crtc; | |
2249 | ||
2250 | /* | |
2251 | * Add all pipes to the state, and force | |
2252 | * a modeset on all the active ones. | |
2253 | */ | |
2254 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
2255 | struct intel_crtc_state *crtc_state; | |
2256 | int ret; | |
2257 | ||
2258 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); | |
2259 | if (IS_ERR(crtc_state)) | |
2260 | return PTR_ERR(crtc_state); | |
2261 | ||
2262 | if (!crtc_state->base.active || | |
2263 | drm_atomic_crtc_needs_modeset(&crtc_state->base)) | |
2264 | continue; | |
2265 | ||
2266 | crtc_state->base.mode_changed = true; | |
2267 | ||
2268 | ret = drm_atomic_add_affected_connectors(&state->base, | |
2269 | &crtc->base); | |
2270 | if (ret) | |
2271 | return ret; | |
2272 | ||
2273 | ret = drm_atomic_add_affected_planes(&state->base, | |
2274 | &crtc->base); | |
2275 | if (ret) | |
2276 | return ret; | |
2277 | ||
2278 | crtc_state->update_planes |= crtc_state->active_planes; | |
2279 | } | |
2280 | ||
2281 | return 0; | |
2282 | } | |
2283 | ||
3e30d708 VS |
2284 | static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) |
2285 | { | |
2286 | int min_cdclk; | |
2287 | ||
2288 | /* | |
2289 | * We can't change the cdclk frequency, but we still want to | |
2290 | * check that the required minimum frequency doesn't exceed | |
2291 | * the actual cdclk frequency. | |
2292 | */ | |
2293 | min_cdclk = intel_compute_min_cdclk(state); | |
2294 | if (min_cdclk < 0) | |
2295 | return min_cdclk; | |
2296 | ||
2297 | return 0; | |
2298 | } | |
2299 | ||
fe4709a8 VS |
2300 | int intel_modeset_calc_cdclk(struct intel_atomic_state *state) |
2301 | { | |
2302 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
2303 | enum pipe pipe; | |
2304 | int ret; | |
2305 | ||
fe4709a8 VS |
2306 | ret = dev_priv->display.modeset_calc_cdclk(state); |
2307 | if (ret) | |
2308 | return ret; | |
2309 | ||
2310 | /* | |
2311 | * Writes to dev_priv->cdclk.logical must protected by | |
2312 | * holding all the crtc locks, even if we don't end up | |
2313 | * touching the hardware | |
2314 | */ | |
2315 | if (intel_cdclk_changed(&dev_priv->cdclk.logical, | |
2316 | &state->cdclk.logical)) { | |
2317 | ret = intel_lock_all_pipes(state); | |
2318 | if (ret < 0) | |
2319 | return ret; | |
2320 | } | |
2321 | ||
2322 | if (is_power_of_2(state->active_pipes)) { | |
2323 | struct intel_crtc *crtc; | |
2324 | struct intel_crtc_state *crtc_state; | |
2325 | ||
2326 | pipe = ilog2(state->active_pipes); | |
2327 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
2328 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); | |
2329 | if (crtc_state && | |
2330 | drm_atomic_crtc_needs_modeset(&crtc_state->base)) | |
2331 | pipe = INVALID_PIPE; | |
2332 | } else { | |
2333 | pipe = INVALID_PIPE; | |
2334 | } | |
2335 | ||
2336 | /* All pipes must be switched off while we change the cdclk. */ | |
2337 | if (pipe != INVALID_PIPE && | |
2338 | intel_cdclk_needs_cd2x_update(dev_priv, | |
2339 | &dev_priv->cdclk.actual, | |
2340 | &state->cdclk.actual)) { | |
2341 | ret = intel_lock_all_pipes(state); | |
2342 | if (ret) | |
2343 | return ret; | |
2344 | ||
2345 | state->cdclk.pipe = pipe; | |
6c066f4c VS |
2346 | |
2347 | DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n", | |
2348 | pipe_name(pipe)); | |
fe4709a8 VS |
2349 | } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual, |
2350 | &state->cdclk.actual)) { | |
2351 | ret = intel_modeset_all_pipes(state); | |
2352 | if (ret) | |
2353 | return ret; | |
2354 | ||
2355 | state->cdclk.pipe = INVALID_PIPE; | |
6c066f4c VS |
2356 | |
2357 | DRM_DEBUG_KMS("Modeset required for cdclk change\n"); | |
fe4709a8 VS |
2358 | } |
2359 | ||
2360 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", | |
2361 | state->cdclk.logical.cdclk, | |
2362 | state->cdclk.actual.cdclk); | |
2363 | DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n", | |
2364 | state->cdclk.logical.voltage_level, | |
2365 | state->cdclk.actual.voltage_level); | |
2366 | ||
2367 | return 0; | |
2368 | } | |
2369 | ||
7ff89ca2 VS |
2370 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
2371 | { | |
2372 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
2373 | ||
42882336 | 2374 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
43037c86 | 2375 | return 2 * max_cdclk_freq; |
cf819eff | 2376 | else if (IS_GEN(dev_priv, 9) || |
d305e061 | 2377 | IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) |
7ff89ca2 VS |
2378 | return max_cdclk_freq; |
2379 | else if (IS_CHERRYVIEW(dev_priv)) | |
2380 | return max_cdclk_freq*95/100; | |
c56b89f1 | 2381 | else if (INTEL_GEN(dev_priv) < 4) |
7ff89ca2 VS |
2382 | return 2*max_cdclk_freq*90/100; |
2383 | else | |
2384 | return max_cdclk_freq*90/100; | |
2385 | } | |
2386 | ||
2387 | /** | |
2388 | * intel_update_max_cdclk - Determine the maximum support CDCLK frequency | |
2389 | * @dev_priv: i915 device | |
2390 | * | |
2391 | * Determine the maximum CDCLK frequency the platform supports, and also | |
2392 | * derive the maximum dot clock frequency the maximum CDCLK frequency | |
2393 | * allows. | |
2394 | */ | |
2395 | void intel_update_max_cdclk(struct drm_i915_private *dev_priv) | |
2396 | { | |
6e63790e JRS |
2397 | if (IS_ELKHARTLAKE(dev_priv)) { |
2398 | if (dev_priv->cdclk.hw.ref == 24000) | |
2399 | dev_priv->max_cdclk_freq = 552000; | |
2400 | else | |
2401 | dev_priv->max_cdclk_freq = 556800; | |
2402 | } else if (INTEL_GEN(dev_priv) >= 11) { | |
186a277e PZ |
2403 | if (dev_priv->cdclk.hw.ref == 24000) |
2404 | dev_priv->max_cdclk_freq = 648000; | |
2405 | else | |
2406 | dev_priv->max_cdclk_freq = 652800; | |
2407 | } else if (IS_CANNONLAKE(dev_priv)) { | |
d1999e9e RV |
2408 | dev_priv->max_cdclk_freq = 528000; |
2409 | } else if (IS_GEN9_BC(dev_priv)) { | |
7ff89ca2 VS |
2410 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
2411 | int max_cdclk, vco; | |
2412 | ||
2413 | vco = dev_priv->skl_preferred_vco_freq; | |
2414 | WARN_ON(vco != 8100000 && vco != 8640000); | |
2415 | ||
2416 | /* | |
2417 | * Use the lower (vco 8640) cdclk values as a | |
2418 | * first guess. skl_calc_cdclk() will correct it | |
2419 | * if the preferred vco is 8100 instead. | |
2420 | */ | |
2421 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
2422 | max_cdclk = 617143; | |
2423 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
2424 | max_cdclk = 540000; | |
2425 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
2426 | max_cdclk = 432000; | |
2427 | else | |
2428 | max_cdclk = 308571; | |
2429 | ||
2430 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
2431 | } else if (IS_GEMINILAKE(dev_priv)) { | |
2432 | dev_priv->max_cdclk_freq = 316800; | |
2433 | } else if (IS_BROXTON(dev_priv)) { | |
2434 | dev_priv->max_cdclk_freq = 624000; | |
2435 | } else if (IS_BROADWELL(dev_priv)) { | |
2436 | /* | |
2437 | * FIXME with extra cooling we can allow | |
2438 | * 540 MHz for ULX and 675 Mhz for ULT. | |
2439 | * How can we know if extra cooling is | |
2440 | * available? PCI ID, VTB, something else? | |
2441 | */ | |
2442 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
2443 | dev_priv->max_cdclk_freq = 450000; | |
2444 | else if (IS_BDW_ULX(dev_priv)) | |
2445 | dev_priv->max_cdclk_freq = 450000; | |
2446 | else if (IS_BDW_ULT(dev_priv)) | |
2447 | dev_priv->max_cdclk_freq = 540000; | |
2448 | else | |
2449 | dev_priv->max_cdclk_freq = 675000; | |
2450 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
2451 | dev_priv->max_cdclk_freq = 320000; | |
2452 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
2453 | dev_priv->max_cdclk_freq = 400000; | |
2454 | } else { | |
2455 | /* otherwise assume cdclk is fixed */ | |
49cd97a3 | 2456 | dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; |
7ff89ca2 VS |
2457 | } |
2458 | ||
2459 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); | |
2460 | ||
2461 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", | |
2462 | dev_priv->max_cdclk_freq); | |
2463 | ||
2464 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
2465 | dev_priv->max_dotclk_freq); | |
2466 | } | |
2467 | ||
2468 | /** | |
2469 | * intel_update_cdclk - Determine the current CDCLK frequency | |
2470 | * @dev_priv: i915 device | |
2471 | * | |
2472 | * Determine the current CDCLK frequency. | |
2473 | */ | |
2474 | void intel_update_cdclk(struct drm_i915_private *dev_priv) | |
2475 | { | |
49cd97a3 | 2476 | dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); |
7ff89ca2 | 2477 | |
7ff89ca2 VS |
2478 | /* |
2479 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): | |
2480 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
2481 | * of cdclk that generates 4MHz reference clock freq which is used to | |
2482 | * generate GMBus clock. This will vary with the cdclk freq. | |
2483 | */ | |
2484 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2485 | I915_WRITE(GMBUSFREQ_VLV, | |
49cd97a3 | 2486 | DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); |
7ff89ca2 VS |
2487 | } |
2488 | ||
9d81a997 RV |
2489 | static int cnp_rawclk(struct drm_i915_private *dev_priv) |
2490 | { | |
2491 | u32 rawclk; | |
2492 | int divider, fraction; | |
2493 | ||
2494 | if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { | |
2495 | /* 24 MHz */ | |
2496 | divider = 24000; | |
2497 | fraction = 0; | |
2498 | } else { | |
2499 | /* 19.2 MHz */ | |
2500 | divider = 19000; | |
2501 | fraction = 200; | |
2502 | } | |
2503 | ||
af4de6ad | 2504 | rawclk = CNP_RAWCLK_DIV(divider / 1000); |
704e504b PZ |
2505 | if (fraction) { |
2506 | int numerator = 1; | |
9d81a997 | 2507 | |
704e504b PZ |
2508 | rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, |
2509 | fraction) - 1); | |
29b43ae2 | 2510 | if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) |
704e504b | 2511 | rawclk |= ICP_RAWCLK_NUM(numerator); |
4ef99abd AS |
2512 | } |
2513 | ||
4ef99abd | 2514 | I915_WRITE(PCH_RAWCLK_FREQ, rawclk); |
704e504b | 2515 | return divider + fraction; |
4ef99abd AS |
2516 | } |
2517 | ||
7ff89ca2 VS |
2518 | static int pch_rawclk(struct drm_i915_private *dev_priv) |
2519 | { | |
2520 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; | |
2521 | } | |
2522 | ||
2523 | static int vlv_hrawclk(struct drm_i915_private *dev_priv) | |
2524 | { | |
2525 | /* RAWCLK_FREQ_VLV register updated from power well code */ | |
2526 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", | |
2527 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
2528 | } | |
2529 | ||
2530 | static int g4x_hrawclk(struct drm_i915_private *dev_priv) | |
2531 | { | |
cbe974fb | 2532 | u32 clkcfg; |
7ff89ca2 VS |
2533 | |
2534 | /* hrawclock is 1/4 the FSB frequency */ | |
2535 | clkcfg = I915_READ(CLKCFG); | |
2536 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
2537 | case CLKCFG_FSB_400: | |
2538 | return 100000; | |
2539 | case CLKCFG_FSB_533: | |
2540 | return 133333; | |
2541 | case CLKCFG_FSB_667: | |
2542 | return 166667; | |
2543 | case CLKCFG_FSB_800: | |
2544 | return 200000; | |
2545 | case CLKCFG_FSB_1067: | |
6f38123e | 2546 | case CLKCFG_FSB_1067_ALT: |
7ff89ca2 VS |
2547 | return 266667; |
2548 | case CLKCFG_FSB_1333: | |
6f38123e | 2549 | case CLKCFG_FSB_1333_ALT: |
7ff89ca2 | 2550 | return 333333; |
7ff89ca2 VS |
2551 | default: |
2552 | return 133333; | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | /** | |
2557 | * intel_update_rawclk - Determine the current RAWCLK frequency | |
2558 | * @dev_priv: i915 device | |
2559 | * | |
2560 | * Determine the current RAWCLK frequency. RAWCLK is a fixed | |
2561 | * frequency clock so this needs to done only once. | |
2562 | */ | |
2563 | void intel_update_rawclk(struct drm_i915_private *dev_priv) | |
2564 | { | |
c6c30b91 | 2565 | if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) |
9d81a997 RV |
2566 | dev_priv->rawclk_freq = cnp_rawclk(dev_priv); |
2567 | else if (HAS_PCH_SPLIT(dev_priv)) | |
7ff89ca2 VS |
2568 | dev_priv->rawclk_freq = pch_rawclk(dev_priv); |
2569 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2570 | dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); | |
2571 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
2572 | dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); | |
2573 | else | |
2574 | /* no rawclk on other platforms, or no need to know it */ | |
2575 | return; | |
2576 | ||
2577 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
2578 | } | |
2579 | ||
2580 | /** | |
2581 | * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks | |
2582 | * @dev_priv: i915 device | |
2583 | */ | |
2584 | void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) | |
2585 | { | |
d2f429eb MR |
2586 | if (IS_ELKHARTLAKE(dev_priv)) { |
2587 | dev_priv->display.set_cdclk = bxt_set_cdclk; | |
933122cc | 2588 | dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; |
d2f429eb MR |
2589 | dev_priv->display.calc_voltage_level = ehl_calc_voltage_level; |
2590 | dev_priv->cdclk.table = icl_cdclk_table; | |
2591 | } else if (INTEL_GEN(dev_priv) >= 11) { | |
1cbcd3b4 | 2592 | dev_priv->display.set_cdclk = bxt_set_cdclk; |
933122cc | 2593 | dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; |
d2f429eb | 2594 | dev_priv->display.calc_voltage_level = icl_calc_voltage_level; |
736da811 | 2595 | dev_priv->cdclk.table = icl_cdclk_table; |
993298af | 2596 | } else if (IS_CANNONLAKE(dev_priv)) { |
1cbcd3b4 | 2597 | dev_priv->display.set_cdclk = bxt_set_cdclk; |
933122cc | 2598 | dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; |
d2f429eb | 2599 | dev_priv->display.calc_voltage_level = cnl_calc_voltage_level; |
736da811 | 2600 | dev_priv->cdclk.table = cnl_cdclk_table; |
7ff89ca2 | 2601 | } else if (IS_GEN9_LP(dev_priv)) { |
b0587e4d | 2602 | dev_priv->display.set_cdclk = bxt_set_cdclk; |
3d51b48f | 2603 | dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; |
d2f429eb | 2604 | dev_priv->display.calc_voltage_level = bxt_calc_voltage_level; |
43ed2275 CW |
2605 | if (IS_GEMINILAKE(dev_priv)) |
2606 | dev_priv->cdclk.table = glk_cdclk_table; | |
2607 | else | |
2608 | dev_priv->cdclk.table = bxt_cdclk_table; | |
7ff89ca2 | 2609 | } else if (IS_GEN9_BC(dev_priv)) { |
b0587e4d | 2610 | dev_priv->display.set_cdclk = skl_set_cdclk; |
3d51b48f | 2611 | dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; |
993298af RV |
2612 | } else if (IS_BROADWELL(dev_priv)) { |
2613 | dev_priv->display.set_cdclk = bdw_set_cdclk; | |
3d51b48f | 2614 | dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; |
993298af RV |
2615 | } else if (IS_CHERRYVIEW(dev_priv)) { |
2616 | dev_priv->display.set_cdclk = chv_set_cdclk; | |
3d51b48f | 2617 | dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; |
993298af RV |
2618 | } else if (IS_VALLEYVIEW(dev_priv)) { |
2619 | dev_priv->display.set_cdclk = vlv_set_cdclk; | |
3d51b48f | 2620 | dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; |
3e30d708 VS |
2621 | } else { |
2622 | dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk; | |
7ff89ca2 VS |
2623 | } |
2624 | ||
71dc367e | 2625 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)) |
7ff89ca2 | 2626 | dev_priv->display.get_cdclk = bxt_get_cdclk; |
993298af RV |
2627 | else if (IS_GEN9_BC(dev_priv)) |
2628 | dev_priv->display.get_cdclk = skl_get_cdclk; | |
7ff89ca2 VS |
2629 | else if (IS_BROADWELL(dev_priv)) |
2630 | dev_priv->display.get_cdclk = bdw_get_cdclk; | |
2631 | else if (IS_HASWELL(dev_priv)) | |
2632 | dev_priv->display.get_cdclk = hsw_get_cdclk; | |
2633 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
2634 | dev_priv->display.get_cdclk = vlv_get_cdclk; | |
cf819eff | 2635 | else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) |
7ff89ca2 | 2636 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; |
cf819eff | 2637 | else if (IS_GEN(dev_priv, 5)) |
7ff89ca2 VS |
2638 | dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; |
2639 | else if (IS_GM45(dev_priv)) | |
2640 | dev_priv->display.get_cdclk = gm45_get_cdclk; | |
6b9e441d | 2641 | else if (IS_G45(dev_priv)) |
7ff89ca2 VS |
2642 | dev_priv->display.get_cdclk = g33_get_cdclk; |
2643 | else if (IS_I965GM(dev_priv)) | |
2644 | dev_priv->display.get_cdclk = i965gm_get_cdclk; | |
2645 | else if (IS_I965G(dev_priv)) | |
2646 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2647 | else if (IS_PINEVIEW(dev_priv)) | |
2648 | dev_priv->display.get_cdclk = pnv_get_cdclk; | |
2649 | else if (IS_G33(dev_priv)) | |
2650 | dev_priv->display.get_cdclk = g33_get_cdclk; | |
2651 | else if (IS_I945GM(dev_priv)) | |
2652 | dev_priv->display.get_cdclk = i945gm_get_cdclk; | |
2653 | else if (IS_I945G(dev_priv)) | |
2654 | dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; | |
2655 | else if (IS_I915GM(dev_priv)) | |
2656 | dev_priv->display.get_cdclk = i915gm_get_cdclk; | |
2657 | else if (IS_I915G(dev_priv)) | |
2658 | dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; | |
2659 | else if (IS_I865G(dev_priv)) | |
2660 | dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; | |
2661 | else if (IS_I85X(dev_priv)) | |
2662 | dev_priv->display.get_cdclk = i85x_get_cdclk; | |
2663 | else if (IS_I845G(dev_priv)) | |
2664 | dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; | |
2665 | else { /* 830 */ | |
2666 | WARN(!IS_I830(dev_priv), | |
2667 | "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
2668 | dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; | |
2669 | } | |
2670 | } |