[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_bw.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2019 Intel Corporation
 */

#ifndef __INTEL_BW_H__
#define __INTEL_BW_H__

#include <drm/drm_atomic.h>

#include "intel_display.h"
#include "intel_display_power.h"
#include "intel_global_state.h"

struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc_state;

struct intel_dbuf_bw {
	int used_bw[I915_MAX_DBUF_SLICES];
};

struct intel_bw_state {
	struct intel_global_state base;
	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];

	/*
	 * Contains a bit mask, used to determine, whether correspondent
	 * pipe allows SAGV or not.
	 */
	u8 pipe_sagv_reject;

	/*
	 * Current QGV points mask, which restricts
	 * some particular SAGV states, not to confuse
	 * with pipe_sagv_mask.
	 */
	u8 qgv_points_mask;

	unsigned int data_rate[I915_MAX_PIPES];
	u8 num_active_planes[I915_MAX_PIPES];

	/* bitmask of active pipes */
	u8 active_pipes;

	int min_cdclk;
};

#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)

struct intel_bw_state *
intel_atomic_get_old_bw_state(struct intel_atomic_state *state);

struct intel_bw_state *
intel_atomic_get_new_bw_state(struct intel_atomic_state *state);

struct intel_bw_state *
intel_atomic_get_bw_state(struct intel_atomic_state *state);

void intel_bw_init_hw(struct drm_i915_private *dev_priv);
int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
			  const struct intel_crtc_state *crtc_state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
				  u32 points_mask);
int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);

#endif /* __INTEL_BW_H__ */
Commit	Line	Data
c457d9cf VS	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_BW_H__
	7	#define __INTEL_BW_H__
	8
	9	#include <drm/drm_atomic.h>
	10
c457d9cf	11	#include "intel_display.h"
cd191546	12	#include "intel_display_power.h"
cac91e67	13	#include "intel_global_state.h"
c457d9cf VS	14
	15	struct drm_i915_private;
	16	struct intel_atomic_state;
	17	struct intel_crtc_state;
	18
cd191546 SL	19	struct intel_dbuf_bw {
	20	int used_bw[I915_MAX_DBUF_SLICES];
	21	};
	22
c457d9cf	23	struct intel_bw_state {
fd1a9bba	24	struct intel_global_state base;
cd191546	25	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
c457d9cf	26
9728889f SL	27	/*
	28	* Contains a bit mask, used to determine, whether correspondent
	29	* pipe allows SAGV or not.
	30	*/
	31	u8 pipe_sagv_reject;
	32
20f505f2 SL	33	/*
	34	* Current QGV points mask, which restricts
	35	* some particular SAGV states, not to confuse
	36	* with pipe_sagv_mask.
	37	*/
	38	u8 qgv_points_mask;
	39
c457d9cf VS	40	unsigned int data_rate[I915_MAX_PIPES];
c457d9cf VS	41	u8 num_active_planes[I915_MAX_PIPES];
ecab0f3d SL	42
	43	/* bitmask of active pipes */
	44	u8 active_pipes;
cd191546 SL	45
cd191546 SL	46	int min_cdclk;
c457d9cf VS	47	};
	48
	49	#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
	50
442e7ee8 SL	51	struct intel_bw_state *
	52	intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
	53
	54	struct intel_bw_state *
	55	intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
	56
	57	struct intel_bw_state *
	58	intel_atomic_get_bw_state(struct intel_atomic_state *state);
	59
c457d9cf VS	60	void intel_bw_init_hw(struct drm_i915_private *dev_priv);
	61	int intel_bw_init(struct drm_i915_private *dev_priv);
	62	int intel_bw_atomic_check(struct intel_atomic_state *state);
	63	void intel_bw_crtc_update(struct intel_bw_state *bw_state,
	64	const struct intel_crtc_state *crtc_state);
20f505f2 SL	65	int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
20f505f2 SL	66	u32 points_mask);
cd191546 SL	67	int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
cd191546 SL	68	int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
c457d9cf VS	69
c457d9cf VS	70	#endif /* __INTEL_BW_H__ */