Linux 5.9-rc2
[linux-2.6-block.git] / drivers / gpu / drm / i915 / display / intel_bios.c
CommitLineData
79e53945 1/*
39507259 2 * Copyright © 2006 Intel Corporation
79e53945
JB
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
b30581a4 27
9f0e7ff4 28#include <drm/drm_dp_helper.h>
3ce2ea65 29
d8fe2ab6 30#include "display/intel_display.h"
1bf2f3bf 31#include "display/intel_display_types.h"
379bc100
JN
32#include "display/intel_gmbus.h"
33
79e53945 34#include "i915_drv.h"
72341af4
JN
35
36#define _INTEL_BIOS_PRIVATE
37#include "intel_vbt_defs.h"
79e53945 38
dd97950a
JN
39/**
40 * DOC: Video BIOS Table (VBT)
41 *
42 * The Video BIOS Table, or VBT, provides platform and board specific
43 * configuration information to the driver that is not discoverable or available
44 * through other means. The configuration is mostly related to display
45 * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in
46 * the PCI ROM.
47 *
48 * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB
49 * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that
50 * contain the actual configuration information. The VBT Header, and thus the
51 * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the
52 * BDB Header. The data blocks are concatenated after the BDB Header. The data
53 * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of
54 * data. (Block 53, the MIPI Sequence Block is an exception.)
55 *
56 * The driver parses the VBT during load. The relevant information is stored in
57 * driver private data for ease of use, and the actual VBT is not read after
58 * that.
59 */
60
0d9ef19b
JN
61/* Wrapper for VBT child device config */
62struct display_device_data {
63 struct child_device_config child;
6e0d46e9 64 struct dsc_compression_parameters_entry *dsc;
0d9ef19b
JN
65 struct list_head node;
66};
67
9b9d172d 68#define SLAVE_ADDR1 0x70
69#define SLAVE_ADDR2 0x72
79e53945 70
08c0888b
JN
71/* Get BDB block size given a pointer to Block ID. */
72static u32 _get_blocksize(const u8 *block_base)
73{
74 /* The MIPI Sequence Block v3+ has a separate size field. */
75 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3)
76 return *((const u32 *)(block_base + 4));
77 else
78 return *((const u16 *)(block_base + 1));
79}
80
81/* Get BDB block size give a pointer to data after Block ID and Block Size. */
82static u32 get_blocksize(const void *block_data)
83{
84 return _get_blocksize(block_data - 3);
85}
86
e8ef3b4c 87static const void *
f41c6153 88find_section(const void *_bdb, enum bdb_block_id section_id)
79e53945 89{
e8ef3b4c
JN
90 const struct bdb_header *bdb = _bdb;
91 const u8 *base = _bdb;
79e53945 92 int index = 0;
cd67d226 93 u32 total, current_size;
f41c6153 94 enum bdb_block_id current_id;
79e53945
JB
95
96 /* skip to first section */
97 index += bdb->header_size;
98 total = bdb->bdb_size;
99
100 /* walk the sections looking for section_id */
d1f13fd2 101 while (index + 3 < total) {
79e53945 102 current_id = *(base + index);
08c0888b
JN
103 current_size = _get_blocksize(base + index);
104 index += 3;
cd67d226 105
d1f13fd2
CW
106 if (index + current_size > total)
107 return NULL;
108
79e53945
JB
109 if (current_id == section_id)
110 return base + index;
d1f13fd2 111
79e53945
JB
112 index += current_size;
113 }
114
115 return NULL;
116}
117
79e53945 118static void
88631706 119fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
99834ea4 120 const struct lvds_dvo_timing *dvo_timing)
88631706
ML
121{
122 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
123 dvo_timing->hactive_lo;
124 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
125 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
126 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
ce2e87b4
VT
127 ((dvo_timing->hsync_pulse_width_hi << 8) |
128 dvo_timing->hsync_pulse_width_lo);
88631706
ML
129 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
130 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
131
132 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
133 dvo_timing->vactive_lo;
134 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
ce2e87b4 135 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
88631706 136 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
ce2e87b4
VT
137 ((dvo_timing->vsync_pulse_width_hi << 4) |
138 dvo_timing->vsync_pulse_width_lo);
88631706
ML
139 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
140 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
141 panel_fixed_mode->clock = dvo_timing->clock * 10;
142 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
143
9bc35499
AJ
144 if (dvo_timing->hsync_positive)
145 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
146 else
147 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
148
149 if (dvo_timing->vsync_positive)
150 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
151 else
152 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
153
df457245
VS
154 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) |
155 dvo_timing->himage_lo;
156 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
157 dvo_timing->vimage_lo;
158
88631706
ML
159 /* Some VBTs have bogus h/vtotal values */
160 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
161 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
162 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
163 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
164
165 drm_mode_set_name(panel_fixed_mode);
166}
167
99834ea4
CW
168static const struct lvds_dvo_timing *
169get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
170 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
171 int index)
172{
173 /*
174 * the size of fp_timing varies on the different platform.
175 * So calculate the DVO timing relative offset in LVDS data
176 * entry to get the DVO timing entry
177 */
178
179 int lfp_data_size =
180 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
181 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
182 int dvo_timing_offset =
183 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
184 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
185 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
186
187 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
188}
189
b0354385
TI
190/* get lvds_fp_timing entry
191 * this function may return NULL if the corresponding entry is invalid
192 */
193static const struct lvds_fp_timing *
194get_lvds_fp_timing(const struct bdb_header *bdb,
195 const struct bdb_lvds_lfp_data *data,
196 const struct bdb_lvds_lfp_data_ptrs *ptrs,
197 int index)
198{
199 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
200 u16 data_size = ((const u16 *)data)[-1]; /* stored in header */
201 size_t ofs;
202
203 if (index >= ARRAY_SIZE(ptrs->ptr))
204 return NULL;
205 ofs = ptrs->ptr[index].fp_timing_offset;
206 if (ofs < data_ofs ||
207 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
208 return NULL;
209 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
210}
211
9e7ecedf 212/* Parse general panel options */
88631706 213static void
9e7ecedf
MR
214parse_panel_options(struct drm_i915_private *dev_priv,
215 const struct bdb_header *bdb)
79e53945 216{
99834ea4 217 const struct bdb_lvds_options *lvds_options;
3e845c7a 218 int panel_type;
c329a4ec 219 int drrs_mode;
a0562819 220 int ret;
79e53945 221
79e53945
JB
222 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
223 if (!lvds_options)
224 return;
225
41aa3448 226 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
a0562819 227
6f9f4b7a 228 ret = intel_opregion_get_panel_type(dev_priv);
a0562819 229 if (ret >= 0) {
f4224a4c 230 drm_WARN_ON(&dev_priv->drm, ret > 0xf);
a0562819 231 panel_type = ret;
e92cbf38
WK
232 drm_dbg_kms(&dev_priv->drm, "Panel type: %d (OpRegion)\n",
233 panel_type);
a0562819
VS
234 } else {
235 if (lvds_options->panel_type > 0xf) {
e92cbf38
WK
236 drm_dbg_kms(&dev_priv->drm,
237 "Invalid VBT panel type 0x%x\n",
238 lvds_options->panel_type);
a0562819
VS
239 return;
240 }
241 panel_type = lvds_options->panel_type;
e92cbf38
WK
242 drm_dbg_kms(&dev_priv->drm, "Panel type: %d (VBT)\n",
243 panel_type);
eeeebea6 244 }
6a04002b 245
3e845c7a 246 dev_priv->vbt.panel_type = panel_type;
79e53945 247
83a7280e
PB
248 drrs_mode = (lvds_options->dps_panel_type_bits
249 >> (panel_type * 2)) & MODE_MASK;
250 /*
251 * VBT has static DRRS = 0 and seamless DRRS = 2.
252 * The below piece of code is required to adjust vbt.drrs_type
253 * to match the enum drrs_support_type.
254 */
255 switch (drrs_mode) {
256 case 0:
257 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
e92cbf38 258 drm_dbg_kms(&dev_priv->drm, "DRRS supported mode is static\n");
83a7280e
PB
259 break;
260 case 2:
261 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
e92cbf38
WK
262 drm_dbg_kms(&dev_priv->drm,
263 "DRRS supported mode is seamless\n");
83a7280e
PB
264 break;
265 default:
266 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
e92cbf38
WK
267 drm_dbg_kms(&dev_priv->drm,
268 "DRRS not supported (VBT input)\n");
83a7280e
PB
269 break;
270 }
9e7ecedf
MR
271}
272
273/* Try to find integrated panel timing data */
274static void
275parse_lfp_panel_dtd(struct drm_i915_private *dev_priv,
276 const struct bdb_header *bdb)
277{
278 const struct bdb_lvds_lfp_data *lvds_lfp_data;
279 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
280 const struct lvds_dvo_timing *panel_dvo_timing;
281 const struct lvds_fp_timing *fp_timing;
282 struct drm_display_mode *panel_fixed_mode;
283 int panel_type = dev_priv->vbt.panel_type;
83a7280e 284
79e53945
JB
285 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
286 if (!lvds_lfp_data)
287 return;
288
1b16de0b
JB
289 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
290 if (!lvds_lfp_data_ptrs)
291 return;
292
99834ea4
CW
293 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
294 lvds_lfp_data_ptrs,
3e845c7a 295 panel_type);
79e53945 296
9a298b2a 297 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
6edc3242
CW
298 if (!panel_fixed_mode)
299 return;
79e53945 300
99834ea4 301 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
79e53945 302
41aa3448 303 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
79e53945 304
e92cbf38
WK
305 drm_dbg_kms(&dev_priv->drm,
306 "Found panel mode in BIOS VBT legacy lfp table:\n");
88631706 307 drm_mode_debug_printmodeline(panel_fixed_mode);
37df9673 308
b0354385
TI
309 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
310 lvds_lfp_data_ptrs,
3e845c7a 311 panel_type);
b0354385
TI
312 if (fp_timing) {
313 /* check the resolution, just to be sure */
314 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
315 fp_timing->y_res == panel_fixed_mode->vdisplay) {
41aa3448 316 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
e92cbf38
WK
317 drm_dbg_kms(&dev_priv->drm,
318 "VBT initial LVDS value %x\n",
319 dev_priv->vbt.bios_lvds_val);
b0354385
TI
320 }
321 }
88631706
ML
322}
323
33ef6d4f
MR
324static void
325parse_generic_dtd(struct drm_i915_private *dev_priv,
326 const struct bdb_header *bdb)
327{
328 const struct bdb_generic_dtd *generic_dtd;
329 const struct generic_dtd_entry *dtd;
330 struct drm_display_mode *panel_fixed_mode;
331 int num_dtd;
332
333 generic_dtd = find_section(bdb, BDB_GENERIC_DTD);
334 if (!generic_dtd)
335 return;
336
337 if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) {
e92cbf38
WK
338 drm_err(&dev_priv->drm, "GDTD size %u is too small.\n",
339 generic_dtd->gdtd_size);
33ef6d4f
MR
340 return;
341 } else if (generic_dtd->gdtd_size !=
342 sizeof(struct generic_dtd_entry)) {
e92cbf38
WK
343 drm_err(&dev_priv->drm, "Unexpected GDTD size %u\n",
344 generic_dtd->gdtd_size);
33ef6d4f
MR
345 /* DTD has unknown fields, but keep going */
346 }
347
348 num_dtd = (get_blocksize(generic_dtd) -
349 sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
8c8a854d 350 if (dev_priv->vbt.panel_type >= num_dtd) {
e92cbf38
WK
351 drm_err(&dev_priv->drm,
352 "Panel type %d not found in table of %d DTD's\n",
353 dev_priv->vbt.panel_type, num_dtd);
33ef6d4f
MR
354 return;
355 }
356
357 dtd = &generic_dtd->dtd[dev_priv->vbt.panel_type];
358
359 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
360 if (!panel_fixed_mode)
361 return;
362
363 panel_fixed_mode->hdisplay = dtd->hactive;
364 panel_fixed_mode->hsync_start =
365 panel_fixed_mode->hdisplay + dtd->hfront_porch;
366 panel_fixed_mode->hsync_end =
367 panel_fixed_mode->hsync_start + dtd->hsync;
ad278f35
VK
368 panel_fixed_mode->htotal =
369 panel_fixed_mode->hdisplay + dtd->hblank;
33ef6d4f
MR
370
371 panel_fixed_mode->vdisplay = dtd->vactive;
372 panel_fixed_mode->vsync_start =
373 panel_fixed_mode->vdisplay + dtd->vfront_porch;
374 panel_fixed_mode->vsync_end =
375 panel_fixed_mode->vsync_start + dtd->vsync;
ad278f35
VK
376 panel_fixed_mode->vtotal =
377 panel_fixed_mode->vdisplay + dtd->vblank;
33ef6d4f
MR
378
379 panel_fixed_mode->clock = dtd->pixel_clock;
380 panel_fixed_mode->width_mm = dtd->width_mm;
381 panel_fixed_mode->height_mm = dtd->height_mm;
382
383 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
384 drm_mode_set_name(panel_fixed_mode);
385
386 if (dtd->hsync_positive_polarity)
387 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
388 else
389 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
390
391 if (dtd->vsync_positive_polarity)
392 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
393 else
394 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
395
e92cbf38
WK
396 drm_dbg_kms(&dev_priv->drm,
397 "Found panel mode in BIOS VBT generic dtd table:\n");
33ef6d4f
MR
398 drm_mode_debug_printmodeline(panel_fixed_mode);
399
400 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
401}
402
403static void
404parse_panel_dtd(struct drm_i915_private *dev_priv,
405 const struct bdb_header *bdb)
406{
407 /*
408 * Older VBTs provided provided DTD information for internal displays
409 * through the "LFP panel DTD" block (42). As of VBT revision 229,
410 * that block is now deprecated and DTD information should be provided
411 * via a newer "generic DTD" block (58). Just to be safe, we'll
412 * try the new generic DTD block first on VBT >= 229, but still fall
413 * back to trying the old LFP block if that fails.
414 */
415 if (bdb->version >= 229)
416 parse_generic_dtd(dev_priv, bdb);
417 if (!dev_priv->vbt.lfp_lvds_vbt_mode)
418 parse_lfp_panel_dtd(dev_priv, bdb);
419}
420
f00076d2 421static void
dcb58a40
JN
422parse_lfp_backlight(struct drm_i915_private *dev_priv,
423 const struct bdb_header *bdb)
f00076d2
JN
424{
425 const struct bdb_lfp_backlight_data *backlight_data;
f87f6599 426 const struct lfp_backlight_data_entry *entry;
3e845c7a 427 int panel_type = dev_priv->vbt.panel_type;
f00076d2
JN
428
429 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
430 if (!backlight_data)
431 return;
432
433 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
e92cbf38
WK
434 drm_dbg_kms(&dev_priv->drm,
435 "Unsupported backlight data entry size %u\n",
436 backlight_data->entry_size);
f00076d2
JN
437 return;
438 }
439
440 entry = &backlight_data->data[panel_type];
441
39fbc9c8
JN
442 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
443 if (!dev_priv->vbt.backlight.present) {
e92cbf38
WK
444 drm_dbg_kms(&dev_priv->drm,
445 "PWM backlight not present in VBT (type %u)\n",
446 entry->type);
39fbc9c8
JN
447 return;
448 }
449
9a41e17d
D
450 dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
451 if (bdb->version >= 191 &&
452 get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
f87f6599 453 const struct lfp_backlight_control_method *method;
9a41e17d
D
454
455 method = &backlight_data->backlight_control[panel_type];
456 dev_priv->vbt.backlight.type = method->type;
add03379 457 dev_priv->vbt.backlight.controller = method->controller;
9a41e17d
D
458 }
459
f00076d2
JN
460 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
461 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
1de6068e 462 dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
e92cbf38
WK
463 drm_dbg_kms(&dev_priv->drm,
464 "VBT backlight PWM modulation frequency %u Hz, "
465 "active %s, min brightness %u, level %u, controller %u\n",
466 dev_priv->vbt.backlight.pwm_freq_hz,
467 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
468 dev_priv->vbt.backlight.min_brightness,
469 backlight_data->level[panel_type],
470 dev_priv->vbt.backlight.controller);
f00076d2
JN
471}
472
88631706
ML
473/* Try to find sdvo panel data */
474static void
475parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
dcb58a40 476 const struct bdb_header *bdb)
88631706 477{
f87f6599 478 const struct bdb_sdvo_panel_dtds *dtds;
88631706 479 struct drm_display_mode *panel_fixed_mode;
5a1e5b6c 480 int index;
79e53945 481
8a25c4be 482 index = dev_priv->params.vbt_sdvo_panel_type;
c10e408a 483 if (index == -2) {
e92cbf38
WK
484 drm_dbg_kms(&dev_priv->drm,
485 "Ignore SDVO panel mode from BIOS VBT tables.\n");
c10e408a
MF
486 return;
487 }
488
5a1e5b6c 489 if (index == -1) {
e8ef3b4c 490 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
5a1e5b6c
CW
491
492 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
493 if (!sdvo_lvds_options)
494 return;
495
496 index = sdvo_lvds_options->panel_type;
497 }
88631706 498
f87f6599
JN
499 dtds = find_section(bdb, BDB_SDVO_PANEL_DTDS);
500 if (!dtds)
88631706
ML
501 return;
502
9a298b2a 503 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
88631706
ML
504 if (!panel_fixed_mode)
505 return;
506
f87f6599 507 fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]);
88631706 508
41aa3448 509 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
79e53945 510
e92cbf38
WK
511 drm_dbg_kms(&dev_priv->drm,
512 "Found SDVO panel mode in BIOS VBT tables:\n");
5a1e5b6c 513 drm_mode_debug_printmodeline(panel_fixed_mode);
79e53945
JB
514}
515
98f3a1dc 516static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
9a4114ff
BF
517 bool alternate)
518{
c56b89f1 519 switch (INTEL_GEN(dev_priv)) {
9a4114ff 520 case 2:
e91e941b 521 return alternate ? 66667 : 48000;
9a4114ff
BF
522 case 3:
523 case 4:
e91e941b 524 return alternate ? 100000 : 96000;
9a4114ff 525 default:
e91e941b 526 return alternate ? 100000 : 120000;
9a4114ff
BF
527 }
528}
529
79e53945
JB
530static void
531parse_general_features(struct drm_i915_private *dev_priv,
dcb58a40 532 const struct bdb_header *bdb)
79e53945 533{
e8ef3b4c 534 const struct bdb_general_features *general;
79e53945 535
79e53945 536 general = find_section(bdb, BDB_GENERAL_FEATURES);
34957e8c
JN
537 if (!general)
538 return;
539
540 dev_priv->vbt.int_tv_support = general->int_tv_support;
541 /* int_crt_support can't be trusted on earlier platforms */
542 if (bdb->version >= 155 &&
543 (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
544 dev_priv->vbt.int_crt_support = general->int_crt_support;
545 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
546 dev_priv->vbt.lvds_ssc_freq =
547 intel_bios_ssc_frequency(dev_priv, general->ssc_freq);
548 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
549 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
c1cd5b24
VS
550 if (bdb->version >= 181) {
551 dev_priv->vbt.orientation = general->rotate_180 ?
552 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP :
553 DRM_MODE_PANEL_ORIENTATION_NORMAL;
554 } else {
555 dev_priv->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
556 }
e92cbf38
WK
557 drm_dbg_kms(&dev_priv->drm,
558 "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
559 dev_priv->vbt.int_tv_support,
560 dev_priv->vbt.int_crt_support,
561 dev_priv->vbt.lvds_use_ssc,
562 dev_priv->vbt.lvds_ssc_freq,
563 dev_priv->vbt.display_clock_mode,
564 dev_priv->vbt.fdi_rx_polarity_inverted);
79e53945
JB
565}
566
cc998589 567static const struct child_device_config *
e192839e 568child_device_ptr(const struct bdb_general_definitions *defs, int i)
90e4f159 569{
e192839e 570 return (const void *) &defs->devices[i * defs->child_dev_size];
90e4f159
VS
571}
572
9b9d172d 573static void
0ead5f81 574parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
9b9d172d 575{
e192839e 576 struct sdvo_device_mapping *mapping;
0d9ef19b 577 const struct display_device_data *devdata;
cc998589 578 const struct child_device_config *child;
0d9ef19b 579 int count = 0;
6cc38aca
JN
580
581 /*
0ebdabe6
JN
582 * Only parse SDVO mappings on gens that could have SDVO. This isn't
583 * accurate and doesn't have to be, as long as it's not too strict.
9b9d172d 584 */
00690008 585 if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
e92cbf38 586 drm_dbg_kms(&dev_priv->drm, "Skipping SDVO device mapping\n");
9b9d172d 587 return;
588 }
0ebdabe6 589
0d9ef19b
JN
590 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
591 child = &devdata->child;
0ebdabe6 592
6cc38aca
JN
593 if (child->slave_addr != SLAVE_ADDR1 &&
594 child->slave_addr != SLAVE_ADDR2) {
9b9d172d 595 /*
596 * If the slave address is neither 0x70 nor 0x72,
597 * it is not a SDVO device. Skip it.
598 */
599 continue;
600 }
6cc38aca
JN
601 if (child->dvo_port != DEVICE_PORT_DVOB &&
602 child->dvo_port != DEVICE_PORT_DVOC) {
9b9d172d 603 /* skip the incorrect SDVO port */
e92cbf38
WK
604 drm_dbg_kms(&dev_priv->drm,
605 "Incorrect SDVO port. Skip it\n");
9b9d172d 606 continue;
607 }
e92cbf38
WK
608 drm_dbg_kms(&dev_priv->drm,
609 "the SDVO device with slave addr %2x is found on"
610 " %s port\n",
611 child->slave_addr,
612 (child->dvo_port == DEVICE_PORT_DVOB) ?
613 "SDVOB" : "SDVOC");
e192839e
JN
614 mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1];
615 if (!mapping->initialized) {
616 mapping->dvo_port = child->dvo_port;
617 mapping->slave_addr = child->slave_addr;
618 mapping->dvo_wiring = child->dvo_wiring;
619 mapping->ddc_pin = child->ddc_pin;
620 mapping->i2c_pin = child->i2c_pin;
621 mapping->initialized = 1;
e92cbf38
WK
622 drm_dbg_kms(&dev_priv->drm,
623 "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
624 mapping->dvo_port, mapping->slave_addr,
625 mapping->dvo_wiring, mapping->ddc_pin,
626 mapping->i2c_pin);
9b9d172d 627 } else {
e92cbf38
WK
628 drm_dbg_kms(&dev_priv->drm,
629 "Maybe one SDVO port is shared by "
630 "two SDVO device.\n");
9b9d172d 631 }
6cc38aca 632 if (child->slave2_addr) {
9b9d172d 633 /* Maybe this is a SDVO device with multiple inputs */
634 /* And the mapping info is not added */
e92cbf38
WK
635 drm_dbg_kms(&dev_priv->drm,
636 "there exists the slave2_addr. Maybe this"
637 " is a SDVO device with multiple inputs.\n");
9b9d172d 638 }
639 count++;
640 }
641
642 if (!count) {
643 /* No SDVO device info is found */
e92cbf38
WK
644 drm_dbg_kms(&dev_priv->drm,
645 "No SDVO device info is found in VBT\n");
9b9d172d 646 }
9b9d172d 647}
32f9d658
ZW
648
649static void
650parse_driver_features(struct drm_i915_private *dev_priv,
dcb58a40 651 const struct bdb_header *bdb)
32f9d658 652{
e8ef3b4c 653 const struct bdb_driver_features *driver;
32f9d658 654
32f9d658 655 driver = find_section(bdb, BDB_DRIVER_FEATURES);
652c393a
JB
656 if (!driver)
657 return;
658
ca3b3fa3
VS
659 if (INTEL_GEN(dev_priv) >= 5) {
660 /*
661 * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS
662 * to mean "eDP". The VBT spec doesn't agree with that
663 * interpretation, but real world VBTs seem to.
664 */
665 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)
666 dev_priv->vbt.int_lvds_support = 0;
667 } else {
668 /*
669 * FIXME it's not clear which BDB version has the LVDS config
670 * bits defined. Revision history in the VBT spec says:
671 * "0.92 | Add two definitions for VBT value of LVDS Active
672 * Config (00b and 11b values defined) | 06/13/2005"
673 * but does not the specify the BDB version.
674 *
675 * So far version 134 (on i945gm) is the oldest VBT observed
676 * in the wild with the bits correctly populated. Version
677 * 108 (on i85x) does not have the bits correctly populated.
678 */
679 if (bdb->version >= 134 &&
680 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&
681 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
682 dev_priv->vbt.int_lvds_support = 0;
683 }
652c393a 684
551fb93d 685 if (bdb->version < 228) {
e92cbf38
WK
686 drm_dbg_kms(&dev_priv->drm, "DRRS State Enabled:%d\n",
687 driver->drrs_enabled);
551fb93d
JRS
688 /*
689 * If DRRS is not supported, drrs_type has to be set to 0.
690 * This is because, VBT is configured in such a way that
691 * static DRRS is 0 and DRRS not supported is represented by
692 * driver->drrs_enabled=false
693 */
694 if (!driver->drrs_enabled)
695 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
696
697 dev_priv->vbt.psr.enable = driver->psr_enabled;
698 }
699}
700
701static void
702parse_power_conservation_features(struct drm_i915_private *dev_priv,
703 const struct bdb_header *bdb)
704{
705 const struct bdb_lfp_power *power;
706 u8 panel_type = dev_priv->vbt.panel_type;
707
708 if (bdb->version < 228)
709 return;
710
4ec5abe9 711 power = find_section(bdb, BDB_LFP_POWER);
551fb93d
JRS
712 if (!power)
713 return;
714
715 dev_priv->vbt.psr.enable = power->psr & BIT(panel_type);
716
83a7280e
PB
717 /*
718 * If DRRS is not supported, drrs_type has to be set to 0.
719 * This is because, VBT is configured in such a way that
720 * static DRRS is 0 and DRRS not supported is represented by
551fb93d 721 * power->drrs & BIT(panel_type)=false
83a7280e 722 */
551fb93d 723 if (!(power->drrs & BIT(panel_type)))
83a7280e 724 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
f615cb6a
JRS
725
726 if (bdb->version >= 232)
727 dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type);
32f9d658
ZW
728}
729
500a8cc4 730static void
dcb58a40 731parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
500a8cc4 732{
e8ef3b4c
JN
733 const struct bdb_edp *edp;
734 const struct edp_power_seq *edp_pps;
058727ee 735 const struct edp_fast_link_params *edp_link_params;
3e845c7a 736 int panel_type = dev_priv->vbt.panel_type;
500a8cc4
ZW
737
738 edp = find_section(bdb, BDB_EDP);
5255e2f8 739 if (!edp)
500a8cc4 740 return;
500a8cc4
ZW
741
742 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
743 case EDP_18BPP:
6aa23e65 744 dev_priv->vbt.edp.bpp = 18;
500a8cc4
ZW
745 break;
746 case EDP_24BPP:
6aa23e65 747 dev_priv->vbt.edp.bpp = 24;
500a8cc4
ZW
748 break;
749 case EDP_30BPP:
6aa23e65 750 dev_priv->vbt.edp.bpp = 30;
500a8cc4
ZW
751 break;
752 }
5ceb0f9b 753
9f0e7ff4
JB
754 /* Get the eDP sequencing and link info */
755 edp_pps = &edp->power_seqs[panel_type];
058727ee 756 edp_link_params = &edp->fast_link_params[panel_type];
5ceb0f9b 757
6aa23e65 758 dev_priv->vbt.edp.pps = *edp_pps;
5ceb0f9b 759
e13e2b2c
JN
760 switch (edp_link_params->rate) {
761 case EDP_RATE_1_62:
6aa23e65 762 dev_priv->vbt.edp.rate = DP_LINK_BW_1_62;
e13e2b2c
JN
763 break;
764 case EDP_RATE_2_7:
6aa23e65 765 dev_priv->vbt.edp.rate = DP_LINK_BW_2_7;
e13e2b2c
JN
766 break;
767 default:
e92cbf38
WK
768 drm_dbg_kms(&dev_priv->drm,
769 "VBT has unknown eDP link rate value %u\n",
770 edp_link_params->rate);
e13e2b2c
JN
771 break;
772 }
773
9f0e7ff4 774 switch (edp_link_params->lanes) {
e13e2b2c 775 case EDP_LANE_1:
6aa23e65 776 dev_priv->vbt.edp.lanes = 1;
9f0e7ff4 777 break;
e13e2b2c 778 case EDP_LANE_2:
6aa23e65 779 dev_priv->vbt.edp.lanes = 2;
9f0e7ff4 780 break;
e13e2b2c 781 case EDP_LANE_4:
6aa23e65 782 dev_priv->vbt.edp.lanes = 4;
9f0e7ff4 783 break;
e13e2b2c 784 default:
e92cbf38
WK
785 drm_dbg_kms(&dev_priv->drm,
786 "VBT has unknown eDP lane count value %u\n",
787 edp_link_params->lanes);
e13e2b2c 788 break;
9f0e7ff4 789 }
e13e2b2c 790
9f0e7ff4 791 switch (edp_link_params->preemphasis) {
e13e2b2c 792 case EDP_PREEMPHASIS_NONE:
6aa23e65 793 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
9f0e7ff4 794 break;
e13e2b2c 795 case EDP_PREEMPHASIS_3_5dB:
6aa23e65 796 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
9f0e7ff4 797 break;
e13e2b2c 798 case EDP_PREEMPHASIS_6dB:
6aa23e65 799 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
9f0e7ff4 800 break;
e13e2b2c 801 case EDP_PREEMPHASIS_9_5dB:
6aa23e65 802 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
9f0e7ff4 803 break;
e13e2b2c 804 default:
e92cbf38
WK
805 drm_dbg_kms(&dev_priv->drm,
806 "VBT has unknown eDP pre-emphasis value %u\n",
807 edp_link_params->preemphasis);
e13e2b2c 808 break;
9f0e7ff4 809 }
e13e2b2c 810
9f0e7ff4 811 switch (edp_link_params->vswing) {
e13e2b2c 812 case EDP_VSWING_0_4V:
6aa23e65 813 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
9f0e7ff4 814 break;
e13e2b2c 815 case EDP_VSWING_0_6V:
6aa23e65 816 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
9f0e7ff4 817 break;
e13e2b2c 818 case EDP_VSWING_0_8V:
6aa23e65 819 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
9f0e7ff4 820 break;
e13e2b2c 821 case EDP_VSWING_1_2V:
6aa23e65 822 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
9f0e7ff4 823 break;
e13e2b2c 824 default:
e92cbf38
WK
825 drm_dbg_kms(&dev_priv->drm,
826 "VBT has unknown eDP voltage swing value %u\n",
827 edp_link_params->vswing);
e13e2b2c 828 break;
9f0e7ff4 829 }
9a57f5bb
SJ
830
831 if (bdb->version >= 173) {
0ede0141 832 u8 vswing;
9a57f5bb 833
9e458034 834 /* Don't read from VBT if module parameter has valid value*/
8a25c4be 835 if (dev_priv->params.edp_vswing) {
4f044a88 836 dev_priv->vbt.edp.low_vswing =
8a25c4be 837 dev_priv->params.edp_vswing == 1;
9e458034
SJ
838 } else {
839 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
06411f08 840 dev_priv->vbt.edp.low_vswing = vswing == 0;
9e458034 841 }
9a57f5bb 842 }
500a8cc4
ZW
843}
844
bfd7ebda 845static void
dcb58a40 846parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
bfd7ebda 847{
e8ef3b4c
JN
848 const struct bdb_psr *psr;
849 const struct psr_table *psr_table;
3e845c7a 850 int panel_type = dev_priv->vbt.panel_type;
bfd7ebda
RV
851
852 psr = find_section(bdb, BDB_PSR);
853 if (!psr) {
e92cbf38 854 drm_dbg_kms(&dev_priv->drm, "No PSR BDB found.\n");
bfd7ebda
RV
855 return;
856 }
857
858 psr_table = &psr->psr_table[panel_type];
859
860 dev_priv->vbt.psr.full_link = psr_table->full_link;
861 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
862
863 /* Allowed VBT values goes from 0 to 15 */
864 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
865 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
866
867 switch (psr_table->lines_to_wait) {
868 case 0:
869 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
870 break;
871 case 1:
872 dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
873 break;
874 case 2:
875 dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
876 break;
877 case 3:
878 dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
879 break;
880 default:
e92cbf38
WK
881 drm_dbg_kms(&dev_priv->drm,
882 "VBT has unknown PSR lines to wait %u\n",
883 psr_table->lines_to_wait);
bfd7ebda
RV
884 break;
885 }
886
77312ae8
VN
887 /*
888 * New psr options 0=500us, 1=100us, 2=2500us, 3=0us
889 * Old decimal value is wake up time in multiples of 100 us.
890 */
0fdb3f75
VN
891 if (bdb->version >= 205 &&
892 (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
893 INTEL_GEN(dev_priv) >= 10)) {
77312ae8
VN
894 switch (psr_table->tp1_wakeup_time) {
895 case 0:
896 dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
897 break;
898 case 1:
899 dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
900 break;
901 case 3:
902 dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
903 break;
904 default:
e92cbf38
WK
905 drm_dbg_kms(&dev_priv->drm,
906 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
907 psr_table->tp1_wakeup_time);
77312ae8
VN
908 /* fallthrough */
909 case 2:
910 dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
911 break;
912 }
913
914 switch (psr_table->tp2_tp3_wakeup_time) {
915 case 0:
916 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
917 break;
918 case 1:
919 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
920 break;
921 case 3:
c238ad62 922 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0;
77312ae8
VN
923 break;
924 default:
e92cbf38
WK
925 drm_dbg_kms(&dev_priv->drm,
926 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
927 psr_table->tp2_tp3_wakeup_time);
77312ae8
VN
928 /* fallthrough */
929 case 2:
930 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
931 break;
932 }
933 } else {
934 dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
935 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
936 }
88a0d960
JRS
937
938 if (bdb->version >= 226) {
b5ea9c93 939 u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
88a0d960
JRS
940
941 wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
942 switch (wakeup_time) {
943 case 0:
944 wakeup_time = 500;
945 break;
946 case 1:
947 wakeup_time = 100;
948 break;
949 case 3:
950 wakeup_time = 50;
951 break;
952 default:
953 case 2:
954 wakeup_time = 2500;
955 break;
956 }
957 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
958 } else {
959 /* Reusing PSR1 wakeup time for PSR2 in older VBTs */
960 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;
961 }
bfd7ebda
RV
962}
963
46e58320
MC
964static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
965 u16 version, enum port port)
966{
967 if (!dev_priv->vbt.dsi.config->dual_link || version < 197) {
968 dev_priv->vbt.dsi.bl_ports = BIT(port);
969 if (dev_priv->vbt.dsi.config->cabc_supported)
970 dev_priv->vbt.dsi.cabc_ports = BIT(port);
971
46e58320
MC
972 return;
973 }
974
975 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
976 case DL_DCS_PORT_A:
977 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);
978 break;
979 case DL_DCS_PORT_C:
980 dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);
981 break;
982 default:
983 case DL_DCS_PORT_A_AND_C:
984 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
985 break;
986 }
987
988 if (!dev_priv->vbt.dsi.config->cabc_supported)
989 return;
990
991 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
992 case DL_DCS_PORT_A:
993 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);
994 break;
995 case DL_DCS_PORT_C:
996 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);
997 break;
998 default:
999 case DL_DCS_PORT_A_AND_C:
1000 dev_priv->vbt.dsi.cabc_ports =
1001 BIT(PORT_A) | BIT(PORT_C);
1002 break;
1003 }
1004}
1005
d17c5443 1006static void
0f8689f5
JN
1007parse_mipi_config(struct drm_i915_private *dev_priv,
1008 const struct bdb_header *bdb)
d17c5443 1009{
e8ef3b4c 1010 const struct bdb_mipi_config *start;
e8ef3b4c
JN
1011 const struct mipi_config *config;
1012 const struct mipi_pps_data *pps;
3e845c7a 1013 int panel_type = dev_priv->vbt.panel_type;
46e58320 1014 enum port port;
d3b542fc 1015
3e6bd011 1016 /* parse MIPI blocks only if LFP type is MIPI */
46e58320 1017 if (!intel_bios_is_dsi_present(dev_priv, &port))
3e6bd011
SK
1018 return;
1019
d3b542fc
SK
1020 /* Initialize this to undefined indicating no generic MIPI support */
1021 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
1022
1023 /* Block #40 is already parsed and panel_fixed_mode is
1024 * stored in dev_priv->lfp_lvds_vbt_mode
1025 * resuse this when needed
1026 */
d17c5443 1027
d3b542fc
SK
1028 /* Parse #52 for panel index used from panel_type already
1029 * parsed
1030 */
1031 start = find_section(bdb, BDB_MIPI_CONFIG);
1032 if (!start) {
e92cbf38 1033 drm_dbg_kms(&dev_priv->drm, "No MIPI config BDB found");
d17c5443
SK
1034 return;
1035 }
1036
e92cbf38
WK
1037 drm_dbg(&dev_priv->drm, "Found MIPI Config block, panel index = %d\n",
1038 panel_type);
d3b542fc
SK
1039
1040 /*
1041 * get hold of the correct configuration block and pps data as per
1042 * the panel_type as index
1043 */
1044 config = &start->config[panel_type];
1045 pps = &start->pps[panel_type];
1046
1047 /* store as of now full data. Trim when we realise all is not needed */
1048 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
1049 if (!dev_priv->vbt.dsi.config)
1050 return;
1051
1052 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
1053 if (!dev_priv->vbt.dsi.pps) {
1054 kfree(dev_priv->vbt.dsi.config);
1055 return;
1056 }
1057
46e58320 1058 parse_dsi_backlight_ports(dev_priv, bdb->version, port);
9f7c5b17 1059
c1cd5b24
VS
1060 /* FIXME is the 90 vs. 270 correct? */
1061 switch (config->rotation) {
1062 case ENABLE_ROTATION_0:
1063 /*
1064 * Most (all?) VBTs claim 0 degrees despite having
1065 * an upside down panel, thus we do not trust this.
1066 */
1067 dev_priv->vbt.dsi.orientation =
1068 DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1069 break;
1070 case ENABLE_ROTATION_90:
1071 dev_priv->vbt.dsi.orientation =
1072 DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
1073 break;
1074 case ENABLE_ROTATION_180:
1075 dev_priv->vbt.dsi.orientation =
1076 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1077 break;
1078 case ENABLE_ROTATION_270:
1079 dev_priv->vbt.dsi.orientation =
1080 DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
1081 break;
1082 }
1083
d3b542fc 1084 /* We have mandatory mipi config blocks. Initialize as generic panel */
ea9a6baf 1085 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
0f8689f5
JN
1086}
1087
5db72099
JN
1088/* Find the sequence block and size for the given panel. */
1089static const u8 *
1090find_panel_sequence_block(const struct bdb_mipi_sequence *sequence,
2a33d934 1091 u16 panel_id, u32 *seq_size)
5db72099
JN
1092{
1093 u32 total = get_blocksize(sequence);
1094 const u8 *data = &sequence->data[0];
1095 u8 current_id;
2a33d934
JN
1096 u32 current_size;
1097 int header_size = sequence->version >= 3 ? 5 : 3;
5db72099
JN
1098 int index = 0;
1099 int i;
1100
2a33d934
JN
1101 /* skip new block size */
1102 if (sequence->version >= 3)
1103 data += 4;
1104
1105 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) {
1106 if (index + header_size > total) {
1107 DRM_ERROR("Invalid sequence block (header)\n");
1108 return NULL;
1109 }
1110
5db72099 1111 current_id = *(data + index);
2a33d934
JN
1112 if (sequence->version >= 3)
1113 current_size = *((const u32 *)(data + index + 1));
1114 else
1115 current_size = *((const u16 *)(data + index + 1));
5db72099 1116
2a33d934 1117 index += header_size;
5db72099
JN
1118
1119 if (index + current_size > total) {
1120 DRM_ERROR("Invalid sequence block\n");
1121 return NULL;
1122 }
1123
1124 if (current_id == panel_id) {
1125 *seq_size = current_size;
1126 return data + index;
1127 }
1128
1129 index += current_size;
1130 }
1131
1132 DRM_ERROR("Sequence block detected but no valid configuration\n");
1133
1134 return NULL;
1135}
1136
8d3ed2f3
JN
1137static int goto_next_sequence(const u8 *data, int index, int total)
1138{
1139 u16 len;
1140
1141 /* Skip Sequence Byte. */
1142 for (index = index + 1; index < total; index += len) {
1143 u8 operation_byte = *(data + index);
1144 index++;
1145
1146 switch (operation_byte) {
1147 case MIPI_SEQ_ELEM_END:
1148 return index;
1149 case MIPI_SEQ_ELEM_SEND_PKT:
1150 if (index + 4 > total)
1151 return 0;
1152
1153 len = *((const u16 *)(data + index + 2)) + 4;
1154 break;
1155 case MIPI_SEQ_ELEM_DELAY:
1156 len = 4;
1157 break;
1158 case MIPI_SEQ_ELEM_GPIO:
1159 len = 2;
1160 break;
f4d64936
JN
1161 case MIPI_SEQ_ELEM_I2C:
1162 if (index + 7 > total)
1163 return 0;
1164 len = *(data + index + 6) + 7;
1165 break;
8d3ed2f3
JN
1166 default:
1167 DRM_ERROR("Unknown operation byte\n");
1168 return 0;
1169 }
1170 }
1171
1172 return 0;
1173}
1174
2a33d934
JN
1175static int goto_next_sequence_v3(const u8 *data, int index, int total)
1176{
1177 int seq_end;
1178 u16 len;
6765bd6d 1179 u32 size_of_sequence;
2a33d934
JN
1180
1181 /*
1182 * Could skip sequence based on Size of Sequence alone, but also do some
1183 * checking on the structure.
1184 */
1185 if (total < 5) {
1186 DRM_ERROR("Too small sequence size\n");
1187 return 0;
1188 }
1189
6765bd6d
JN
1190 /* Skip Sequence Byte. */
1191 index++;
1192
1193 /*
1194 * Size of Sequence. Excludes the Sequence Byte and the size itself,
1195 * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END
1196 * byte.
1197 */
0ede0141 1198 size_of_sequence = *((const u32 *)(data + index));
6765bd6d
JN
1199 index += 4;
1200
1201 seq_end = index + size_of_sequence;
2a33d934
JN
1202 if (seq_end > total) {
1203 DRM_ERROR("Invalid sequence size\n");
1204 return 0;
1205 }
1206
6765bd6d 1207 for (; index < total; index += len) {
2a33d934
JN
1208 u8 operation_byte = *(data + index);
1209 index++;
1210
1211 if (operation_byte == MIPI_SEQ_ELEM_END) {
1212 if (index != seq_end) {
1213 DRM_ERROR("Invalid element structure\n");
1214 return 0;
1215 }
1216 return index;
1217 }
1218
1219 len = *(data + index);
1220 index++;
1221
1222 /*
1223 * FIXME: Would be nice to check elements like for v1/v2 in
1224 * goto_next_sequence() above.
1225 */
1226 switch (operation_byte) {
1227 case MIPI_SEQ_ELEM_SEND_PKT:
1228 case MIPI_SEQ_ELEM_DELAY:
1229 case MIPI_SEQ_ELEM_GPIO:
1230 case MIPI_SEQ_ELEM_I2C:
1231 case MIPI_SEQ_ELEM_SPI:
1232 case MIPI_SEQ_ELEM_PMIC:
1233 break;
1234 default:
1235 DRM_ERROR("Unknown operation byte %u\n",
1236 operation_byte);
1237 break;
1238 }
1239 }
1240
1241 return 0;
1242}
1243
fb38e7ad
HG
1244/*
1245 * Get len of pre-fixed deassert fragment from a v1 init OTP sequence,
1246 * skip all delay + gpio operands and stop at the first DSI packet op.
1247 */
1248static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv)
1249{
1250 const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1251 int index, len;
1252
f4224a4c
PB
1253 if (drm_WARN_ON(&dev_priv->drm,
1254 !data || dev_priv->vbt.dsi.seq_version != 1))
fb38e7ad
HG
1255 return 0;
1256
1257 /* index = 1 to skip sequence byte */
1258 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {
1259 switch (data[index]) {
1260 case MIPI_SEQ_ELEM_SEND_PKT:
1261 return index == 1 ? 0 : index;
1262 case MIPI_SEQ_ELEM_DELAY:
1263 len = 5; /* 1 byte for operand + uint32 */
1264 break;
1265 case MIPI_SEQ_ELEM_GPIO:
1266 len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */
1267 break;
1268 default:
1269 return 0;
1270 }
1271 }
1272
1273 return 0;
1274}
1275
1276/*
1277 * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence.
1278 * The deassert must be done before calling intel_dsi_device_ready, so for
1279 * these devices we split the init OTP sequence into a deassert sequence and
1280 * the actual init OTP part.
1281 */
1282static void fixup_mipi_sequences(struct drm_i915_private *dev_priv)
1283{
1284 u8 *init_otp;
1285 int len;
1286
1287 /* Limit this to VLV for now. */
1288 if (!IS_VALLEYVIEW(dev_priv))
1289 return;
1290
1291 /* Limit this to v1 vid-mode sequences */
1292 if (dev_priv->vbt.dsi.config->is_cmd_mode ||
1293 dev_priv->vbt.dsi.seq_version != 1)
1294 return;
1295
1296 /* Only do this if there are otp and assert seqs and no deassert seq */
1297 if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
1298 !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
1299 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
1300 return;
1301
1302 /* The deassert-sequence ends at the first DSI packet */
1303 len = get_init_otp_deassert_fragment_len(dev_priv);
1304 if (!len)
1305 return;
1306
e92cbf38
WK
1307 drm_dbg_kms(&dev_priv->drm,
1308 "Using init OTP fragment to deassert reset\n");
fb38e7ad
HG
1309
1310 /* Copy the fragment, update seq byte and terminate it */
1311 init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1312 dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
1313 if (!dev_priv->vbt.dsi.deassert_seq)
1314 return;
1315 dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
1316 dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
1317 /* Use the copy for deassert */
1318 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
1319 dev_priv->vbt.dsi.deassert_seq;
1320 /* Replace the last byte of the fragment with init OTP seq byte */
1321 init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
1322 /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */
1323 dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
1324}
1325
0f8689f5
JN
1326static void
1327parse_mipi_sequence(struct drm_i915_private *dev_priv,
1328 const struct bdb_header *bdb)
1329{
3e845c7a 1330 int panel_type = dev_priv->vbt.panel_type;
0f8689f5
JN
1331 const struct bdb_mipi_sequence *sequence;
1332 const u8 *seq_data;
2a33d934 1333 u32 seq_size;
0f8689f5 1334 u8 *data;
8d3ed2f3 1335 int index = 0;
0f8689f5
JN
1336
1337 /* Only our generic panel driver uses the sequence block. */
1338 if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
1339 return;
d3b542fc 1340
d3b542fc
SK
1341 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
1342 if (!sequence) {
e92cbf38
WK
1343 drm_dbg_kms(&dev_priv->drm,
1344 "No MIPI Sequence found, parsing complete\n");
d3b542fc
SK
1345 return;
1346 }
1347
cd67d226 1348 /* Fail gracefully for forward incompatible sequence block. */
2a33d934 1349 if (sequence->version >= 4) {
e92cbf38
WK
1350 drm_err(&dev_priv->drm,
1351 "Unable to parse MIPI Sequence Block v%u\n",
1352 sequence->version);
cd67d226
JN
1353 return;
1354 }
1355
e92cbf38
WK
1356 drm_dbg(&dev_priv->drm, "Found MIPI sequence block v%u\n",
1357 sequence->version);
d3b542fc 1358
5db72099
JN
1359 seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size);
1360 if (!seq_data)
d3b542fc 1361 return;
d3b542fc 1362
8d3ed2f3
JN
1363 data = kmemdup(seq_data, seq_size, GFP_KERNEL);
1364 if (!data)
d3b542fc
SK
1365 return;
1366
8d3ed2f3
JN
1367 /* Parse the sequences, store pointers to each sequence. */
1368 for (;;) {
1369 u8 seq_id = *(data + index);
1370 if (seq_id == MIPI_SEQ_END)
1371 break;
d3b542fc 1372
8d3ed2f3 1373 if (seq_id >= MIPI_SEQ_MAX) {
e92cbf38
WK
1374 drm_err(&dev_priv->drm, "Unknown sequence %u\n",
1375 seq_id);
d3b542fc
SK
1376 goto err;
1377 }
1378
4b4f497e
JN
1379 /* Log about presence of sequences we won't run. */
1380 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF)
e92cbf38
WK
1381 drm_dbg_kms(&dev_priv->drm,
1382 "Unsupported sequence %u\n", seq_id);
4b4f497e 1383
8d3ed2f3 1384 dev_priv->vbt.dsi.sequence[seq_id] = data + index;
d3b542fc 1385
2a33d934
JN
1386 if (sequence->version >= 3)
1387 index = goto_next_sequence_v3(data, index, seq_size);
1388 else
1389 index = goto_next_sequence(data, index, seq_size);
8d3ed2f3 1390 if (!index) {
e92cbf38
WK
1391 drm_err(&dev_priv->drm, "Invalid sequence %u\n",
1392 seq_id);
d3b542fc
SK
1393 goto err;
1394 }
d3b542fc
SK
1395 }
1396
8d3ed2f3
JN
1397 dev_priv->vbt.dsi.data = data;
1398 dev_priv->vbt.dsi.size = seq_size;
1399 dev_priv->vbt.dsi.seq_version = sequence->version;
1400
fb38e7ad
HG
1401 fixup_mipi_sequences(dev_priv);
1402
e92cbf38 1403 drm_dbg(&dev_priv->drm, "MIPI related VBT parsing complete\n");
d3b542fc 1404 return;
d3b542fc 1405
8d3ed2f3
JN
1406err:
1407 kfree(data);
ed3b6679 1408 memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
d17c5443
SK
1409}
1410
6e0d46e9
JN
1411static void
1412parse_compression_parameters(struct drm_i915_private *i915,
1413 const struct bdb_header *bdb)
1414{
1415 const struct bdb_compression_parameters *params;
1416 struct display_device_data *devdata;
1417 const struct child_device_config *child;
1418 u16 block_size;
1419 int index;
1420
1421 if (bdb->version < 198)
1422 return;
1423
1424 params = find_section(bdb, BDB_COMPRESSION_PARAMETERS);
1425 if (params) {
1426 /* Sanity checks */
1427 if (params->entry_size != sizeof(params->data[0])) {
e92cbf38
WK
1428 drm_dbg_kms(&i915->drm,
1429 "VBT: unsupported compression param entry size\n");
6e0d46e9
JN
1430 return;
1431 }
1432
1433 block_size = get_blocksize(params);
1434 if (block_size < sizeof(*params)) {
e92cbf38
WK
1435 drm_dbg_kms(&i915->drm,
1436 "VBT: expected 16 compression param entries\n");
6e0d46e9
JN
1437 return;
1438 }
1439 }
1440
1441 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
1442 child = &devdata->child;
1443
1444 if (!child->compression_enable)
1445 continue;
1446
1447 if (!params) {
e92cbf38
WK
1448 drm_dbg_kms(&i915->drm,
1449 "VBT: compression params not available\n");
6e0d46e9
JN
1450 continue;
1451 }
1452
1453 if (child->compression_method_cps) {
e92cbf38
WK
1454 drm_dbg_kms(&i915->drm,
1455 "VBT: CPS compression not supported\n");
6e0d46e9
JN
1456 continue;
1457 }
1458
1459 index = child->compression_structure_index;
1460
1461 devdata->dsc = kmemdup(&params->data[index],
1462 sizeof(*devdata->dsc), GFP_KERNEL);
1463 }
1464}
1465
75067dde
AK
1466static u8 translate_iboost(u8 val)
1467{
1468 static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
1469
1470 if (val >= ARRAY_SIZE(mapping)) {
1471 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
1472 return 0;
1473 }
1474 return mapping[val];
1475}
1476
cc21f011
JN
1477static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
1478{
1479 const struct ddi_vbt_port_info *info;
1480 enum port port;
1481
c4a774c4 1482 for_each_port(port) {
cc21f011
JN
1483 info = &i915->vbt.ddi_port_info[port];
1484
1485 if (info->child && ddc_pin == info->alternate_ddc_pin)
1486 return port;
1487 }
1488
1489 return PORT_NONE;
1490}
1491
9454fa87
VS
1492static void sanitize_ddc_pin(struct drm_i915_private *dev_priv,
1493 enum port port)
1494{
36a0f920 1495 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
9454fa87
VS
1496 enum port p;
1497
1498 if (!info->alternate_ddc_pin)
1499 return;
1500
cc21f011
JN
1501 p = get_port_by_ddc_pin(dev_priv, info->alternate_ddc_pin);
1502 if (p != PORT_NONE) {
e92cbf38
WK
1503 drm_dbg_kms(&dev_priv->drm,
1504 "port %c trying to use the same DDC pin (0x%x) as port %c, "
1505 "disabling port %c DVI/HDMI support\n",
1506 port_name(port), info->alternate_ddc_pin,
1507 port_name(p), port_name(p));
9454fa87
VS
1508
1509 /*
1510 * If we have multiple ports supposedly sharing the
1511 * pin, then dvi/hdmi couldn't exist on the shared
1512 * port. Otherwise they share the same ddc bin and
1513 * system couldn't communicate with them separately.
1514 *
41e35ffb
VS
1515 * Give inverse child device order the priority,
1516 * last one wins. Yes, there are real machines
1517 * (eg. Asrock B250M-HDV) where VBT has both
1518 * port A and port E with the same AUX ch and
1519 * we must pick port E :(
9454fa87 1520 */
41e35ffb
VS
1521 info = &dev_priv->vbt.ddi_port_info[p];
1522
36a0f920
JN
1523 info->supports_dvi = false;
1524 info->supports_hdmi = false;
1525 info->alternate_ddc_pin = 0;
9454fa87
VS
1526 }
1527}
1528
cc21f011
JN
1529static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
1530{
1531 const struct ddi_vbt_port_info *info;
1532 enum port port;
1533
c4a774c4 1534 for_each_port(port) {
cc21f011
JN
1535 info = &i915->vbt.ddi_port_info[port];
1536
1537 if (info->child && aux_ch == info->alternate_aux_channel)
1538 return port;
1539 }
1540
1541 return PORT_NONE;
1542}
1543
9454fa87
VS
1544static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
1545 enum port port)
1546{
36a0f920 1547 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
9454fa87
VS
1548 enum port p;
1549
1550 if (!info->alternate_aux_channel)
1551 return;
1552
cc21f011
JN
1553 p = get_port_by_aux_ch(dev_priv, info->alternate_aux_channel);
1554 if (p != PORT_NONE) {
e92cbf38
WK
1555 drm_dbg_kms(&dev_priv->drm,
1556 "port %c trying to use the same AUX CH (0x%x) as port %c, "
1557 "disabling port %c DP support\n",
1558 port_name(port), info->alternate_aux_channel,
1559 port_name(p), port_name(p));
9454fa87
VS
1560
1561 /*
1562 * If we have multiple ports supposedlt sharing the
1563 * aux channel, then DP couldn't exist on the shared
1564 * port. Otherwise they share the same aux channel
1565 * and system couldn't communicate with them separately.
1566 *
41e35ffb
VS
1567 * Give inverse child device order the priority,
1568 * last one wins. Yes, there are real machines
1569 * (eg. Asrock B250M-HDV) where VBT has both
1570 * port A and port E with the same AUX ch and
1571 * we must pick port E :(
9454fa87 1572 */
41e35ffb
VS
1573 info = &dev_priv->vbt.ddi_port_info[p];
1574
36a0f920
JN
1575 info->supports_dp = false;
1576 info->alternate_aux_channel = 0;
9454fa87
VS
1577 }
1578}
1579
9c3b2689 1580static const u8 cnp_ddc_pin_map[] = {
3393ce1e 1581 [0] = 0, /* N/A */
9c3b2689
RV
1582 [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
1583 [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
1584 [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */
1585 [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */
1586};
1587
3937eb1a 1588static const u8 icp_ddc_pin_map[] = {
d757535e
MK
1589 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
1590 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
1591 [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
1592 [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
1593 [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
1594 [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
1595 [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
1596 [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
1597 [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
1598};
1599
9c3b2689
RV
1600static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
1601{
3937eb1a
RS
1602 const u8 *ddc_pin_map;
1603 int n_entries;
1604
5a6b7ef6 1605 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
3937eb1a
RS
1606 ddc_pin_map = icp_ddc_pin_map;
1607 n_entries = ARRAY_SIZE(icp_ddc_pin_map);
1608 } else if (HAS_PCH_CNP(dev_priv)) {
1609 ddc_pin_map = cnp_ddc_pin_map;
1610 n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
1611 } else {
1612 /* Assuming direct map */
1613 return vbt_pin;
a8e6f388 1614 }
9c3b2689 1615
3937eb1a
RS
1616 if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
1617 return ddc_pin_map[vbt_pin];
1618
e92cbf38
WK
1619 drm_dbg_kms(&dev_priv->drm,
1620 "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",
1621 vbt_pin);
3937eb1a 1622 return 0;
9c3b2689
RV
1623}
1624
4628142a
LDM
1625static enum port __dvo_port_to_port(int n_ports, int n_dvo,
1626 const int port_mapping[][3], u8 dvo_port)
6acab15a 1627{
b024ab9b
JN
1628 enum port port;
1629 int i;
6acab15a 1630
4628142a
LDM
1631 for (port = PORT_A; port < n_ports; port++) {
1632 for (i = 0; i < n_dvo; i++) {
1633 if (port_mapping[port][i] == -1)
6acab15a
PZ
1634 break;
1635
4628142a 1636 if (dvo_port == port_mapping[port][i])
b024ab9b 1637 return port;
6acab15a
PZ
1638 }
1639 }
b024ab9b
JN
1640
1641 return PORT_NONE;
1642}
1643
4628142a
LDM
1644static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
1645 u8 dvo_port)
1646{
1647 /*
1648 * Each DDI port can have more than one value on the "DVO Port" field,
1649 * so look for all the possible values for each port.
1650 */
1651 static const int port_mapping[][3] = {
1652 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
1653 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
1654 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
1655 [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
8c1a8f12 1656 [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT },
4628142a
LDM
1657 [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
1658 [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
1659 };
1660 /*
1661 * Bspec lists the ports as A, B, C, D - however internally in our
1662 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
1663 * registers in Display Engine match the right offsets. Apply the
1664 * mapping here to translate from VBT to internal convention.
1665 */
1666 static const int rkl_port_mapping[][3] = {
1667 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
1668 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
1669 [PORT_C] = { -1 },
1670 [PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
1671 [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
1672 };
1673
1674 if (IS_ROCKETLAKE(dev_priv))
1675 return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
1676 ARRAY_SIZE(rkl_port_mapping[0]),
1677 rkl_port_mapping,
1678 dvo_port);
1679 else
1680 return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
1681 ARRAY_SIZE(port_mapping[0]),
1682 port_mapping,
1683 dvo_port);
1684}
1685
b024ab9b 1686static void parse_ddi_port(struct drm_i915_private *dev_priv,
d1dad6f4 1687 struct display_device_data *devdata,
b024ab9b
JN
1688 u8 bdb_version)
1689{
d1dad6f4 1690 const struct child_device_config *child = &devdata->child;
b024ab9b
JN
1691 struct ddi_vbt_port_info *info;
1692 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
1693 enum port port;
1694
4628142a 1695 port = dvo_port_to_port(dev_priv, child->dvo_port);
b024ab9b
JN
1696 if (port == PORT_NONE)
1697 return;
1698
1699 info = &dev_priv->vbt.ddi_port_info[port];
1700
7679f9b8 1701 if (info->child) {
e92cbf38
WK
1702 drm_dbg_kms(&dev_priv->drm,
1703 "More than one child device for port %c in VBT, using the first.\n",
1704 port_name(port));
6acab15a 1705 return;
b024ab9b
JN
1706 }
1707
cc998589
JN
1708 is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
1709 is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
1710 is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT;
1711 is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
1712 is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
554d6af5 1713
523e0cc8 1714 if (port == PORT_A && is_dvi && INTEL_GEN(dev_priv) < 12) {
e92cbf38
WK
1715 drm_dbg_kms(&dev_priv->drm,
1716 "VBT claims port A supports DVI%s, ignoring\n",
1717 is_hdmi ? "/HDMI" : "");
2ba7d7e0
JN
1718 is_dvi = false;
1719 is_hdmi = false;
1720 }
1721
311a2094
PZ
1722 info->supports_dvi = is_dvi;
1723 info->supports_hdmi = is_hdmi;
1724 info->supports_dp = is_dp;
a98d9c1d 1725 info->supports_edp = is_edp;
311a2094 1726
38b3416f
ID
1727 if (bdb_version >= 195)
1728 info->supports_typec_usb = child->dp_usb_type_c;
1729
1730 if (bdb_version >= 209)
1731 info->supports_tbt = child->tbt;
1732
e92cbf38
WK
1733 drm_dbg_kms(&dev_priv->drm,
1734 "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
1735 port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
1736 HAS_LSPCON(dev_priv) && child->lspcon,
1737 info->supports_typec_usb, info->supports_tbt,
1738 devdata->dsc != NULL);
554d6af5 1739
6bf19e7c 1740 if (is_dvi) {
e53a1058
JN
1741 u8 ddc_pin;
1742
f212bf9a
JN
1743 ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin);
1744 if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) {
1745 info->alternate_ddc_pin = ddc_pin;
1746 sanitize_ddc_pin(dev_priv, port);
1747 } else {
e92cbf38
WK
1748 drm_dbg_kms(&dev_priv->drm,
1749 "Port %c has invalid DDC pin %d, "
1750 "sticking to defaults\n",
1751 port_name(port), ddc_pin);
f212bf9a 1752 }
6bf19e7c
PZ
1753 }
1754
1755 if (is_dp) {
e53a1058 1756 info->alternate_aux_channel = child->aux_channel;
9454fa87
VS
1757
1758 sanitize_aux_ch(dev_priv, port);
6bf19e7c
PZ
1759 }
1760
0ead5f81 1761 if (bdb_version >= 158) {
6acab15a 1762 /* The VBT HDMI level shift values match the table we have. */
e53a1058 1763 u8 hdmi_level_shift = child->hdmi_level_shifter_value;
e92cbf38
WK
1764 drm_dbg_kms(&dev_priv->drm,
1765 "VBT HDMI level shift for port %c: %d\n",
1766 port_name(port),
1767 hdmi_level_shift);
ce4dd49e 1768 info->hdmi_level_shift = hdmi_level_shift;
7a0073d6 1769 info->hdmi_level_shift_set = true;
6acab15a 1770 }
75067dde 1771
d6038611
VS
1772 if (bdb_version >= 204) {
1773 int max_tmds_clock;
1774
1775 switch (child->hdmi_max_data_rate) {
1776 default:
1777 MISSING_CASE(child->hdmi_max_data_rate);
1778 /* fall through */
1779 case HDMI_MAX_DATA_RATE_PLATFORM:
1780 max_tmds_clock = 0;
1781 break;
1782 case HDMI_MAX_DATA_RATE_297:
1783 max_tmds_clock = 297000;
1784 break;
1785 case HDMI_MAX_DATA_RATE_165:
1786 max_tmds_clock = 165000;
1787 break;
1788 }
1789
1790 if (max_tmds_clock)
e92cbf38
WK
1791 drm_dbg_kms(&dev_priv->drm,
1792 "VBT HDMI max TMDS clock for port %c: %d kHz\n",
1793 port_name(port), max_tmds_clock);
d6038611
VS
1794 info->max_tmds_clock = max_tmds_clock;
1795 }
1796
75067dde 1797 /* Parse the I_boost config for SKL and above */
0ead5f81 1798 if (bdb_version >= 196 && child->iboost) {
f22bb358 1799 info->dp_boost_level = translate_iboost(child->dp_iboost_level);
e92cbf38
WK
1800 drm_dbg_kms(&dev_priv->drm,
1801 "VBT (e)DP boost level for port %c: %d\n",
1802 port_name(port), info->dp_boost_level);
f22bb358 1803 info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level);
e92cbf38
WK
1804 drm_dbg_kms(&dev_priv->drm,
1805 "VBT HDMI boost level for port %c: %d\n",
1806 port_name(port), info->hdmi_boost_level);
75067dde 1807 }
99b91bda
JN
1808
1809 /* DP max link rate for CNL+ */
1810 if (bdb_version >= 216) {
1811 switch (child->dp_max_link_rate) {
1812 default:
1813 case VBT_DP_MAX_LINK_RATE_HBR3:
1814 info->dp_max_link_rate = 810000;
1815 break;
1816 case VBT_DP_MAX_LINK_RATE_HBR2:
1817 info->dp_max_link_rate = 540000;
1818 break;
1819 case VBT_DP_MAX_LINK_RATE_HBR:
1820 info->dp_max_link_rate = 270000;
1821 break;
1822 case VBT_DP_MAX_LINK_RATE_LBR:
1823 info->dp_max_link_rate = 162000;
1824 break;
1825 }
e92cbf38
WK
1826 drm_dbg_kms(&dev_priv->drm,
1827 "VBT DP max link rate for port %c: %d\n",
1828 port_name(port), info->dp_max_link_rate);
99b91bda 1829 }
7679f9b8
JN
1830
1831 info->child = child;
6acab15a
PZ
1832}
1833
0ead5f81 1834static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
6acab15a 1835{
d1dad6f4 1836 struct display_device_data *devdata;
6acab15a 1837
348e4058 1838 if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6acab15a
PZ
1839 return;
1840
0ead5f81 1841 if (bdb_version < 155)
6acab15a
PZ
1842 return;
1843
0d9ef19b 1844 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
d1dad6f4 1845 parse_ddi_port(dev_priv, devdata, bdb_version);
6acab15a
PZ
1846}
1847
6363ee6f 1848static void
b3ca1f43
JN
1849parse_general_definitions(struct drm_i915_private *dev_priv,
1850 const struct bdb_header *bdb)
6363ee6f 1851{
e192839e 1852 const struct bdb_general_definitions *defs;
0d9ef19b 1853 struct display_device_data *devdata;
e192839e 1854 const struct child_device_config *child;
0d9ef19b 1855 int i, child_device_num;
e2d6cf7f
DW
1856 u8 expected_size;
1857 u16 block_size;
b3ca1f43 1858 int bus_pin;
6363ee6f 1859
e192839e
JN
1860 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1861 if (!defs) {
e92cbf38
WK
1862 drm_dbg_kms(&dev_priv->drm,
1863 "No general definition block is found, no devices defined.\n");
6363ee6f
ZY
1864 return;
1865 }
b3ca1f43
JN
1866
1867 block_size = get_blocksize(defs);
1868 if (block_size < sizeof(*defs)) {
e92cbf38
WK
1869 drm_dbg_kms(&dev_priv->drm,
1870 "General definitions block too small (%u)\n",
1871 block_size);
b3ca1f43
JN
1872 return;
1873 }
1874
1875 bus_pin = defs->crt_ddc_gmbus_pin;
e92cbf38 1876 drm_dbg_kms(&dev_priv->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
b3ca1f43
JN
1877 if (intel_gmbus_is_valid_pin(dev_priv, bus_pin))
1878 dev_priv->vbt.crt_ddc_pin = bus_pin;
1879
7244f309
VS
1880 if (bdb->version < 106) {
1881 expected_size = 22;
fa05178c 1882 } else if (bdb->version < 111) {
52b69c84
VS
1883 expected_size = 27;
1884 } else if (bdb->version < 195) {
21907e72 1885 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
e2d6cf7f
DW
1886 } else if (bdb->version == 195) {
1887 expected_size = 37;
c4fb60b9 1888 } else if (bdb->version <= 215) {
e2d6cf7f 1889 expected_size = 38;
3aec2c6a 1890 } else if (bdb->version <= 229) {
c4fb60b9 1891 expected_size = 39;
e2d6cf7f 1892 } else {
c4fb60b9
JN
1893 expected_size = sizeof(*child);
1894 BUILD_BUG_ON(sizeof(*child) < 39);
e92cbf38
WK
1895 drm_dbg(&dev_priv->drm,
1896 "Expected child device config size for VBT version %u not known; assuming %u\n",
1897 bdb->version, expected_size);
e2d6cf7f
DW
1898 }
1899
e2d6cf7f 1900 /* Flag an error for unexpected size, but continue anyway. */
e192839e 1901 if (defs->child_dev_size != expected_size)
e92cbf38
WK
1902 drm_err(&dev_priv->drm,
1903 "Unexpected child device config size %u (expected %u for VBT version %u)\n",
1904 defs->child_dev_size, expected_size, bdb->version);
e2d6cf7f 1905
52b69c84 1906 /* The legacy sized child device config is the minimum we need. */
e192839e 1907 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
e92cbf38
WK
1908 drm_dbg_kms(&dev_priv->drm,
1909 "Child device config size %u is too small.\n",
1910 defs->child_dev_size);
52b69c84
VS
1911 return;
1912 }
1913
6363ee6f 1914 /* get the number of child device */
e192839e 1915 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
6363ee6f 1916
6363ee6f 1917 for (i = 0; i < child_device_num; i++) {
e192839e 1918 child = child_device_ptr(defs, i);
53f6b243 1919 if (!child->device_type)
6363ee6f 1920 continue;
3e6bd011 1921
e92cbf38
WK
1922 drm_dbg_kms(&dev_priv->drm,
1923 "Found VBT child device with type 0x%x\n",
1924 child->device_type);
bdeb18db 1925
0d9ef19b
JN
1926 devdata = kzalloc(sizeof(*devdata), GFP_KERNEL);
1927 if (!devdata)
1928 break;
1929
e2d6cf7f
DW
1930 /*
1931 * Copy as much as we know (sizeof) and is available
0d9ef19b
JN
1932 * (child_dev_size) of the child device config. Accessing the
1933 * data must depend on VBT version.
e2d6cf7f 1934 */
0d9ef19b 1935 memcpy(&devdata->child, child,
e192839e 1936 min_t(size_t, defs->child_dev_size, sizeof(*child)));
0d9ef19b
JN
1937
1938 list_add_tail(&devdata->node, &dev_priv->vbt.display_devices);
6363ee6f 1939 }
0d9ef19b
JN
1940
1941 if (list_empty(&dev_priv->vbt.display_devices))
e92cbf38
WK
1942 drm_dbg_kms(&dev_priv->drm,
1943 "no child dev is parsed from VBT\n");
6363ee6f 1944}
44834a67 1945
bb1d1329 1946/* Common defaults which may be overridden by VBT. */
6a04002b
SQ
1947static void
1948init_vbt_defaults(struct drm_i915_private *dev_priv)
1949{
988c7015 1950 dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
6a04002b 1951
56c4b63a
JN
1952 /* Default to having backlight */
1953 dev_priv->vbt.backlight.present = true;
1954
6a04002b 1955 /* LFP panel data */
41aa3448 1956 dev_priv->vbt.lvds_dither = 1;
6a04002b
SQ
1957
1958 /* SDVO panel data */
41aa3448 1959 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
6a04002b
SQ
1960
1961 /* general features */
41aa3448
RV
1962 dev_priv->vbt.int_tv_support = 1;
1963 dev_priv->vbt.int_crt_support = 1;
9a4114ff 1964
5255e2f8
VS
1965 /* driver features */
1966 dev_priv->vbt.int_lvds_support = 1;
1967
9a4114ff 1968 /* Default to using SSC */
41aa3448 1969 dev_priv->vbt.lvds_use_ssc = 1;
f69e5156
DL
1970 /*
1971 * Core/SandyBridge/IvyBridge use alternative (120MHz) reference
1972 * clock for LVDS.
1973 */
98f3a1dc
JN
1974 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv,
1975 !HAS_PCH_SPLIT(dev_priv));
e92cbf38
WK
1976 drm_dbg_kms(&dev_priv->drm, "Set default to SSC at %d kHz\n",
1977 dev_priv->vbt.lvds_ssc_freq);
bb1d1329
JN
1978}
1979
1980/* Defaults to initialize only if there is no VBT. */
1981static void
1982init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
1983{
1984 enum port port;
1985
c4a774c4 1986 for_each_port(port) {
bb1d1329
JN
1987 struct ddi_vbt_port_info *info =
1988 &dev_priv->vbt.ddi_port_info[port];
d8fe2ab6 1989 enum phy phy = intel_port_to_phy(dev_priv, port);
311a2094 1990
828ccb31
ID
1991 /*
1992 * VBT has the TypeC mode (native,TBT/USB) and we don't want
1993 * to detect it.
1994 */
d8fe2ab6 1995 if (intel_phy_is_tc(dev_priv, phy))
828ccb31
ID
1996 continue;
1997
311a2094
PZ
1998 info->supports_dvi = (port != PORT_A && port != PORT_E);
1999 info->supports_hdmi = info->supports_dvi;
2000 info->supports_dp = (port != PORT_E);
2131bc0c 2001 info->supports_edp = (port == PORT_A);
6acab15a 2002 }
6a04002b
SQ
2003}
2004
caf37fa4
JN
2005static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
2006{
2007 const void *_vbt = vbt;
2008
2009 return _vbt + vbt->bdb_offset;
2010}
2011
f0067a31
JN
2012/**
2013 * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT
2014 * @buf: pointer to a buffer to validate
2015 * @size: size of the buffer
2016 *
2017 * Returns true on valid VBT.
2018 */
2019bool intel_bios_is_valid_vbt(const void *buf, size_t size)
3dd4e846 2020{
f0067a31 2021 const struct vbt_header *vbt = buf;
dcb58a40 2022 const struct bdb_header *bdb;
3dd4e846 2023
caf37fa4 2024 if (!vbt)
f0067a31 2025 return false;
caf37fa4 2026
f0067a31 2027 if (sizeof(struct vbt_header) > size) {
3dd4e846 2028 DRM_DEBUG_DRIVER("VBT header incomplete\n");
f0067a31 2029 return false;
3dd4e846
CW
2030 }
2031
2032 if (memcmp(vbt->signature, "$VBT", 4)) {
2033 DRM_DEBUG_DRIVER("VBT invalid signature\n");
f0067a31 2034 return false;
3dd4e846
CW
2035 }
2036
ff00ff96
LDM
2037 if (vbt->vbt_size > size) {
2038 DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n");
2039 return false;
2040 }
2041
2042 size = vbt->vbt_size;
2043
e8f9ae9b
CW
2044 if (range_overflows_t(size_t,
2045 vbt->bdb_offset,
2046 sizeof(struct bdb_header),
2047 size)) {
3dd4e846 2048 DRM_DEBUG_DRIVER("BDB header incomplete\n");
f0067a31 2049 return false;
3dd4e846
CW
2050 }
2051
caf37fa4 2052 bdb = get_bdb_header(vbt);
e8f9ae9b 2053 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
3dd4e846 2054 DRM_DEBUG_DRIVER("BDB incomplete\n");
f0067a31 2055 return false;
3dd4e846
CW
2056 }
2057
caf37fa4 2058 return vbt;
3dd4e846
CW
2059}
2060
2cded152 2061static struct vbt_header *oprom_get_vbt(struct drm_i915_private *dev_priv)
b34a991a 2062{
2cded152
LDM
2063 struct pci_dev *pdev = dev_priv->drm.pdev;
2064 void __iomem *p = NULL, *oprom;
fd0186ce
LDM
2065 struct vbt_header *vbt;
2066 u16 vbt_size;
2cded152
LDM
2067 size_t i, size;
2068
2069 oprom = pci_map_rom(pdev, &size);
2070 if (!oprom)
2071 return NULL;
b34a991a
JN
2072
2073 /* Scour memory looking for the VBT signature. */
98cf5c9a 2074 for (i = 0; i + 4 < size; i += 4) {
496f50a6 2075 if (ioread32(oprom + i) != *((const u32 *)"$VBT"))
f0067a31
JN
2076 continue;
2077
fd0186ce
LDM
2078 p = oprom + i;
2079 size -= i;
f0067a31 2080 break;
b34a991a
JN
2081 }
2082
fd0186ce 2083 if (!p)
2cded152 2084 goto err_unmap_oprom;
fd0186ce
LDM
2085
2086 if (sizeof(struct vbt_header) > size) {
e92cbf38 2087 drm_dbg(&dev_priv->drm, "VBT header incomplete\n");
2cded152 2088 goto err_unmap_oprom;
fd0186ce
LDM
2089 }
2090
2091 vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size));
2092 if (vbt_size > size) {
e92cbf38
WK
2093 drm_dbg(&dev_priv->drm,
2094 "VBT incomplete (vbt_size overflows)\n");
2cded152 2095 goto err_unmap_oprom;
fd0186ce
LDM
2096 }
2097
2098 /* The rest will be validated by intel_bios_is_valid_vbt() */
2099 vbt = kmalloc(vbt_size, GFP_KERNEL);
2100 if (!vbt)
2cded152 2101 goto err_unmap_oprom;
fd0186ce
LDM
2102
2103 memcpy_fromio(vbt, p, vbt_size);
2104
2105 if (!intel_bios_is_valid_vbt(vbt, vbt_size))
2106 goto err_free_vbt;
2107
2cded152
LDM
2108 pci_unmap_rom(pdev, oprom);
2109
fd0186ce
LDM
2110 return vbt;
2111
2112err_free_vbt:
2113 kfree(vbt);
2cded152
LDM
2114err_unmap_oprom:
2115 pci_unmap_rom(pdev, oprom);
fd0186ce 2116
f0067a31 2117 return NULL;
b34a991a
JN
2118}
2119
79e53945 2120/**
8b8e1a89 2121 * intel_bios_init - find VBT and initialize settings from the BIOS
dd97950a 2122 * @dev_priv: i915 device instance
79e53945 2123 *
66578857
JN
2124 * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT
2125 * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also
2126 * initialize some defaults if the VBT is not present at all.
79e53945 2127 */
66578857 2128void intel_bios_init(struct drm_i915_private *dev_priv)
79e53945 2129{
f0067a31 2130 const struct vbt_header *vbt = dev_priv->opregion.vbt;
2cded152 2131 struct vbt_header *oprom_vbt = NULL;
caf37fa4 2132 const struct bdb_header *bdb;
44834a67 2133
0d9ef19b
JN
2134 INIT_LIST_HEAD(&dev_priv->vbt.display_devices);
2135
a2b69ea4 2136 if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) {
e92cbf38
WK
2137 drm_dbg_kms(&dev_priv->drm,
2138 "Skipping VBT init due to disabled display.\n");
66578857
JN
2139 return;
2140 }
ab5c608b 2141
6a04002b 2142 init_vbt_defaults(dev_priv);
f899fc64 2143
66578857 2144 /* If the OpRegion does not have VBT, look in PCI ROM. */
f0067a31 2145 if (!vbt) {
2cded152
LDM
2146 oprom_vbt = oprom_get_vbt(dev_priv);
2147 if (!oprom_vbt)
66578857 2148 goto out;
44834a67 2149
2cded152 2150 vbt = oprom_vbt;
e2051c44 2151
e92cbf38 2152 drm_dbg_kms(&dev_priv->drm, "Found valid VBT in PCI ROM\n");
44834a67 2153 }
79e53945 2154
caf37fa4
JN
2155 bdb = get_bdb_header(vbt);
2156
e92cbf38
WK
2157 drm_dbg_kms(&dev_priv->drm,
2158 "VBT signature \"%.*s\", BDB version %d\n",
2159 (int)sizeof(vbt->signature), vbt->signature, bdb->version);
e2051c44 2160
79e53945
JB
2161 /* Grab useful general definitions */
2162 parse_general_features(dev_priv, bdb);
db545019 2163 parse_general_definitions(dev_priv, bdb);
9e7ecedf 2164 parse_panel_options(dev_priv, bdb);
33ef6d4f 2165 parse_panel_dtd(dev_priv, bdb);
f00076d2 2166 parse_lfp_backlight(dev_priv, bdb);
88631706 2167 parse_sdvo_panel_data(dev_priv, bdb);
32f9d658 2168 parse_driver_features(dev_priv, bdb);
551fb93d 2169 parse_power_conservation_features(dev_priv, bdb);
500a8cc4 2170 parse_edp(dev_priv, bdb);
bfd7ebda 2171 parse_psr(dev_priv, bdb);
0f8689f5
JN
2172 parse_mipi_config(dev_priv, bdb);
2173 parse_mipi_sequence(dev_priv, bdb);
0ebdabe6 2174
6e0d46e9
JN
2175 /* Depends on child device list */
2176 parse_compression_parameters(dev_priv, bdb);
2177
0ebdabe6 2178 /* Further processing on pre-parsed data */
0ead5f81
JN
2179 parse_sdvo_device_mapping(dev_priv, bdb->version);
2180 parse_ddi_ports(dev_priv, bdb->version);
32f9d658 2181
66578857 2182out:
bb1d1329 2183 if (!vbt) {
e92cbf38
WK
2184 drm_info(&dev_priv->drm,
2185 "Failed to find VBIOS tables (VBT)\n");
bb1d1329
JN
2186 init_vbt_missing_defaults(dev_priv);
2187 }
66578857 2188
2cded152 2189 kfree(oprom_vbt);
79e53945 2190}
3bdd14d5 2191
785f076b 2192/**
78dae1ac 2193 * intel_bios_driver_remove - Free any resources allocated by intel_bios_init()
785f076b
HG
2194 * @dev_priv: i915 device instance
2195 */
78dae1ac 2196void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
785f076b 2197{
0d9ef19b
JN
2198 struct display_device_data *devdata, *n;
2199
2200 list_for_each_entry_safe(devdata, n, &dev_priv->vbt.display_devices, node) {
2201 list_del(&devdata->node);
6e0d46e9 2202 kfree(devdata->dsc);
0d9ef19b
JN
2203 kfree(devdata);
2204 }
2205
785f076b
HG
2206 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
2207 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
2208 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
2209 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
e1b86c85
HG
2210 kfree(dev_priv->vbt.dsi.data);
2211 dev_priv->vbt.dsi.data = NULL;
2212 kfree(dev_priv->vbt.dsi.pps);
2213 dev_priv->vbt.dsi.pps = NULL;
2214 kfree(dev_priv->vbt.dsi.config);
2215 dev_priv->vbt.dsi.config = NULL;
fb38e7ad
HG
2216 kfree(dev_priv->vbt.dsi.deassert_seq);
2217 dev_priv->vbt.dsi.deassert_seq = NULL;
785f076b
HG
2218}
2219
3bdd14d5
JN
2220/**
2221 * intel_bios_is_tv_present - is integrated TV present in VBT
2222 * @dev_priv: i915 device instance
2223 *
2224 * Return true if TV is present. If no child devices were parsed from VBT,
2225 * assume TV is present.
2226 */
2227bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
2228{
0d9ef19b 2229 const struct display_device_data *devdata;
cc998589 2230 const struct child_device_config *child;
3bdd14d5
JN
2231
2232 if (!dev_priv->vbt.int_tv_support)
2233 return false;
2234
0d9ef19b 2235 if (list_empty(&dev_priv->vbt.display_devices))
3bdd14d5
JN
2236 return true;
2237
0d9ef19b
JN
2238 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
2239 child = &devdata->child;
2240
3bdd14d5
JN
2241 /*
2242 * If the device type is not TV, continue.
2243 */
cc998589 2244 switch (child->device_type) {
3bdd14d5
JN
2245 case DEVICE_TYPE_INT_TV:
2246 case DEVICE_TYPE_TV:
2247 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
2248 break;
2249 default:
2250 continue;
2251 }
2252 /* Only when the addin_offset is non-zero, it is regarded
2253 * as present.
2254 */
cc998589 2255 if (child->addin_offset)
3bdd14d5
JN
2256 return true;
2257 }
2258
2259 return false;
2260}
5a69d13d
JN
2261
2262/**
2263 * intel_bios_is_lvds_present - is LVDS present in VBT
2264 * @dev_priv: i915 device instance
2265 * @i2c_pin: i2c pin for LVDS if present
2266 *
2267 * Return true if LVDS is present. If no child devices were parsed from VBT,
2268 * assume LVDS is present.
2269 */
2270bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
2271{
0d9ef19b 2272 const struct display_device_data *devdata;
cc998589 2273 const struct child_device_config *child;
5a69d13d 2274
0d9ef19b 2275 if (list_empty(&dev_priv->vbt.display_devices))
5a69d13d
JN
2276 return true;
2277
0d9ef19b
JN
2278 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
2279 child = &devdata->child;
5a69d13d
JN
2280
2281 /* If the device type is not LFP, continue.
2282 * We have to check both the new identifiers as well as the
2283 * old for compatibility with some BIOSes.
2284 */
2285 if (child->device_type != DEVICE_TYPE_INT_LFP &&
2286 child->device_type != DEVICE_TYPE_LFP)
2287 continue;
2288
2289 if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
2290 *i2c_pin = child->i2c_pin;
2291
2292 /* However, we cannot trust the BIOS writers to populate
2293 * the VBT correctly. Since LVDS requires additional
2294 * information from AIM blocks, a non-zero addin offset is
2295 * a good indicator that the LVDS is actually present.
2296 */
2297 if (child->addin_offset)
2298 return true;
2299
2300 /* But even then some BIOS writers perform some black magic
2301 * and instantiate the device without reference to any
2302 * additional data. Trust that if the VBT was written into
2303 * the OpRegion then they have validated the LVDS's existence.
2304 */
2305 if (dev_priv->opregion.vbt)
2306 return true;
2307 }
2308
2309 return false;
2310}
951d9efe 2311
22f35042
VS
2312/**
2313 * intel_bios_is_port_present - is the specified digital port present
2314 * @dev_priv: i915 device instance
2315 * @port: port to check
2316 *
2317 * Return true if the device in %port is present.
2318 */
2319bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port)
2320{
0d9ef19b 2321 const struct display_device_data *devdata;
cc998589 2322 const struct child_device_config *child;
22f35042
VS
2323 static const struct {
2324 u16 dp, hdmi;
2325 } port_mapping[] = {
2326 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
2327 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
2328 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
2329 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
841b5ed7 2330 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
22f35042 2331 };
22f35042 2332
e9d49bb7
ID
2333 if (HAS_DDI(dev_priv)) {
2334 const struct ddi_vbt_port_info *port_info =
2335 &dev_priv->vbt.ddi_port_info[port];
2336
85d8ec20 2337 return port_info->child;
e9d49bb7
ID
2338 }
2339
22f35042 2340 /* FIXME maybe deal with port A as well? */
f4224a4c
PB
2341 if (drm_WARN_ON(&dev_priv->drm,
2342 port == PORT_A) || port >= ARRAY_SIZE(port_mapping))
22f35042
VS
2343 return false;
2344
0d9ef19b
JN
2345 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
2346 child = &devdata->child;
cc998589
JN
2347
2348 if ((child->dvo_port == port_mapping[port].dp ||
2349 child->dvo_port == port_mapping[port].hdmi) &&
2350 (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
2351 DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
22f35042
VS
2352 return true;
2353 }
2354
2355 return false;
2356}
2357
951d9efe
JN
2358/**
2359 * intel_bios_is_port_edp - is the device in given port eDP
2360 * @dev_priv: i915 device instance
2361 * @port: port to check
2362 *
2363 * Return true if the device in %port is eDP.
2364 */
2365bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
2366{
0d9ef19b 2367 const struct display_device_data *devdata;
cc998589 2368 const struct child_device_config *child;
951d9efe
JN
2369 static const short port_mapping[] = {
2370 [PORT_B] = DVO_PORT_DPB,
2371 [PORT_C] = DVO_PORT_DPC,
2372 [PORT_D] = DVO_PORT_DPD,
2373 [PORT_E] = DVO_PORT_DPE,
841b5ed7 2374 [PORT_F] = DVO_PORT_DPF,
951d9efe 2375 };
951d9efe 2376
a98d9c1d
ID
2377 if (HAS_DDI(dev_priv))
2378 return dev_priv->vbt.ddi_port_info[port].supports_edp;
2379
0d9ef19b
JN
2380 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
2381 child = &devdata->child;
951d9efe 2382
cc998589
JN
2383 if (child->dvo_port == port_mapping[port] &&
2384 (child->device_type & DEVICE_TYPE_eDP_BITS) ==
951d9efe
JN
2385 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
2386 return true;
2387 }
2388
2389 return false;
2390}
7137aec1 2391
cc998589 2392static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
7a17995a 2393 enum port port)
d6199256
VS
2394{
2395 static const struct {
2396 u16 dp, hdmi;
2397 } port_mapping[] = {
2398 /*
2399 * Buggy VBTs may declare DP ports as having
2400 * HDMI type dvo_port :( So let's check both.
2401 */
2402 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
2403 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
2404 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
2405 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
841b5ed7 2406 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
d6199256 2407 };
d6199256
VS
2408
2409 if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
2410 return false;
2411
cc998589 2412 if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
7a17995a 2413 (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
d6199256
VS
2414 return false;
2415
cc998589 2416 if (child->dvo_port == port_mapping[port].dp)
7a17995a
VS
2417 return true;
2418
2419 /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */
cc998589
JN
2420 if (child->dvo_port == port_mapping[port].hdmi &&
2421 child->aux_channel != 0)
7a17995a
VS
2422 return true;
2423
2424 return false;
2425}
2426
2427bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
2428 enum port port)
2429{
0d9ef19b 2430 const struct display_device_data *devdata;
7a17995a 2431
0d9ef19b
JN
2432 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
2433 if (child_dev_is_dp_dual_mode(&devdata->child, port))
d6199256
VS
2434 return true;
2435 }
2436
2437 return false;
2438}
2439
7137aec1
JN
2440/**
2441 * intel_bios_is_dsi_present - is DSI present in VBT
2442 * @dev_priv: i915 device instance
2443 * @port: port for DSI if present
2444 *
2445 * Return true if DSI is present, and return the port in %port.
2446 */
2447bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
2448 enum port *port)
2449{
0d9ef19b 2450 const struct display_device_data *devdata;
cc998589 2451 const struct child_device_config *child;
7137aec1 2452 u8 dvo_port;
7137aec1 2453
0d9ef19b
JN
2454 list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) {
2455 child = &devdata->child;
7137aec1 2456
cc998589 2457 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
7137aec1
JN
2458 continue;
2459
cc998589 2460 dvo_port = child->dvo_port;
7137aec1 2461
bf4d57ff 2462 if (dvo_port == DVO_PORT_MIPIA ||
2dd24a9c
RV
2463 (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
2464 (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
7caaef33
JN
2465 if (port)
2466 *port = dvo_port - DVO_PORT_MIPIA;
7137aec1 2467 return true;
bf4d57ff
MC
2468 } else if (dvo_port == DVO_PORT_MIPIB ||
2469 dvo_port == DVO_PORT_MIPIC ||
2470 dvo_port == DVO_PORT_MIPID) {
e92cbf38
WK
2471 drm_dbg_kms(&dev_priv->drm,
2472 "VBT has unsupported DSI port %c\n",
2473 port_name(dvo_port - DVO_PORT_MIPIA));
7137aec1
JN
2474 }
2475 }
2476
2477 return false;
2478}
d252bf68 2479
1bf2f3bf
JN
2480static void fill_dsc(struct intel_crtc_state *crtc_state,
2481 struct dsc_compression_parameters_entry *dsc,
2482 int dsc_max_bpc)
2483{
2484 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2485 int bpc = 8;
2486
2487 vdsc_cfg->dsc_version_major = dsc->version_major;
2488 vdsc_cfg->dsc_version_minor = dsc->version_minor;
2489
2490 if (dsc->support_12bpc && dsc_max_bpc >= 12)
2491 bpc = 12;
2492 else if (dsc->support_10bpc && dsc_max_bpc >= 10)
2493 bpc = 10;
2494 else if (dsc->support_8bpc && dsc_max_bpc >= 8)
2495 bpc = 8;
2496 else
2497 DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
2498 dsc_max_bpc);
2499
2500 crtc_state->pipe_bpp = bpc * 3;
2501
2502 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
2503 VBT_DSC_MAX_BPP(dsc->max_bpp));
2504
2505 /*
2506 * FIXME: This is ugly, and slice count should take DSC engine
2507 * throughput etc. into account.
2508 *
2509 * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices.
2510 */
2511 if (dsc->slices_per_line & BIT(2)) {
2512 crtc_state->dsc.slice_count = 4;
2513 } else if (dsc->slices_per_line & BIT(1)) {
2514 crtc_state->dsc.slice_count = 2;
2515 } else {
2516 /* FIXME */
2517 if (!(dsc->slices_per_line & BIT(0)))
2518 DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n");
2519
2520 crtc_state->dsc.slice_count = 1;
2521 }
2522
2523 if (crtc_state->hw.adjusted_mode.crtc_hdisplay %
2524 crtc_state->dsc.slice_count != 0)
2525 DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n",
2526 crtc_state->hw.adjusted_mode.crtc_hdisplay,
2527 crtc_state->dsc.slice_count);
2528
2529 /*
2530 * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the
2531 * implementation specific physical rate buffer size. Currently we use
2532 * the required rate buffer model size calculated in
2533 * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E.
2534 *
2535 * The VBT rc_buffer_block_size and rc_buffer_size definitions
2536 * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC
2537 * implementation should also use the DPCD (or perhaps VBT for eDP)
2538 * provided value for the buffer size.
2539 */
2540
2541 /* FIXME: DSI spec says bpc + 1 for this one */
2542 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
2543
2544 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;
2545
2546 vdsc_cfg->slice_height = dsc->slice_height;
2547}
2548
2549/* FIXME: initially DSI specific */
2550bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
2551 struct intel_crtc_state *crtc_state,
2552 int dsc_max_bpc)
2553{
2554 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2555 const struct display_device_data *devdata;
2556 const struct child_device_config *child;
2557
2558 list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
2559 child = &devdata->child;
2560
2561 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
2562 continue;
2563
2564 if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {
2565 if (!devdata->dsc)
2566 return false;
2567
2568 if (crtc_state)
2569 fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);
2570
2571 return true;
2572 }
2573 }
2574
2575 return false;
2576}
2577
d252bf68
SS
2578/**
2579 * intel_bios_is_port_hpd_inverted - is HPD inverted for %port
c72deaa4 2580 * @i915: i915 device instance
d252bf68
SS
2581 * @port: port to check
2582 *
2583 * Return true if HPD should be inverted for %port.
2584 */
2585bool
c72deaa4 2586intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
d252bf68
SS
2587 enum port port)
2588{
c72deaa4
JN
2589 const struct child_device_config *child =
2590 i915->vbt.ddi_port_info[port].child;
d252bf68 2591
f4224a4c 2592 if (drm_WARN_ON_ONCE(&i915->drm, !IS_GEN9_LP(i915)))
d252bf68
SS
2593 return false;
2594
c72deaa4 2595 return child && child->hpd_invert;
d252bf68 2596}
6389dd83
SS
2597
2598/**
2599 * intel_bios_is_lspcon_present - if LSPCON is attached on %port
a7475e5d 2600 * @i915: i915 device instance
6389dd83
SS
2601 * @port: port to check
2602 *
2603 * Return true if LSPCON is present on this port
2604 */
2605bool
a7475e5d
JN
2606intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
2607 enum port port)
6389dd83 2608{
a7475e5d
JN
2609 const struct child_device_config *child =
2610 i915->vbt.ddi_port_info[port].child;
6389dd83 2611
a7475e5d 2612 return HAS_LSPCON(i915) && child && child->lspcon;
6389dd83 2613}
15d248ae 2614
39053089
JN
2615enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
2616 enum port port)
15d248ae
ID
2617{
2618 const struct ddi_vbt_port_info *info =
2619 &dev_priv->vbt.ddi_port_info[port];
2620 enum aux_ch aux_ch;
2621
2622 if (!info->alternate_aux_channel) {
2623 aux_ch = (enum aux_ch)port;
2624
e92cbf38
WK
2625 drm_dbg_kms(&dev_priv->drm,
2626 "using AUX %c for port %c (platform default)\n",
2627 aux_ch_name(aux_ch), port_name(port));
15d248ae
ID
2628 return aux_ch;
2629 }
2630
2631 switch (info->alternate_aux_channel) {
2632 case DP_AUX_A:
2633 aux_ch = AUX_CH_A;
2634 break;
2635 case DP_AUX_B:
2636 aux_ch = AUX_CH_B;
2637 break;
2638 case DP_AUX_C:
4628142a 2639 aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
15d248ae
ID
2640 break;
2641 case DP_AUX_D:
4628142a 2642 aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
15d248ae
ID
2643 break;
2644 case DP_AUX_E:
2645 aux_ch = AUX_CH_E;
2646 break;
2647 case DP_AUX_F:
2648 aux_ch = AUX_CH_F;
2649 break;
eb8de23c
KA
2650 case DP_AUX_G:
2651 aux_ch = AUX_CH_G;
2652 break;
15d248ae
ID
2653 default:
2654 MISSING_CASE(info->alternate_aux_channel);
2655 aux_ch = AUX_CH_A;
2656 break;
2657 }
2658
e92cbf38
WK
2659 drm_dbg_kms(&dev_priv->drm, "using AUX %c for port %c (VBT)\n",
2660 aux_ch_name(aux_ch), port_name(port));
15d248ae
ID
2661
2662 return aux_ch;
2663}
d9ee2111
JN
2664
2665int intel_bios_max_tmds_clock(struct intel_encoder *encoder)
2666{
2667 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2668
2669 return i915->vbt.ddi_port_info[encoder->port].max_tmds_clock;
2670}
0aed3bde
JN
2671
2672int intel_bios_hdmi_level_shift(struct intel_encoder *encoder)
2673{
2674 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2675 const struct ddi_vbt_port_info *info =
2676 &i915->vbt.ddi_port_info[encoder->port];
2677
2678 return info->hdmi_level_shift_set ? info->hdmi_level_shift : -1;
2679}
605a1872
JN
2680
2681int intel_bios_dp_boost_level(struct intel_encoder *encoder)
2682{
2683 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2684
2685 return i915->vbt.ddi_port_info[encoder->port].dp_boost_level;
2686}
01a60883
JN
2687
2688int intel_bios_hdmi_boost_level(struct intel_encoder *encoder)
2689{
2690 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2691
2692 return i915->vbt.ddi_port_info[encoder->port].hdmi_boost_level;
2693}
f83acdab
JN
2694
2695int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
2696{
2697 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2698
2699 return i915->vbt.ddi_port_info[encoder->port].dp_max_link_rate;
2700}
17004bfb
JN
2701
2702int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
2703{
2704 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2705
2706 return i915->vbt.ddi_port_info[encoder->port].alternate_ddc_pin;
2707}
c5faae5a
JN
2708
2709bool intel_bios_port_supports_dvi(struct drm_i915_private *i915, enum port port)
2710{
2711 return i915->vbt.ddi_port_info[port].supports_dvi;
2712}
2713
2714bool intel_bios_port_supports_hdmi(struct drm_i915_private *i915, enum port port)
2715{
2716 return i915->vbt.ddi_port_info[port].supports_hdmi;
2717}
2718
2719bool intel_bios_port_supports_dp(struct drm_i915_private *i915, enum port port)
2720{
2721 return i915->vbt.ddi_port_info[port].supports_dp;
2722}
2723
2724bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915,
2725 enum port port)
2726{
2727 return i915->vbt.ddi_port_info[port].supports_typec_usb;
2728}
2729
2730bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port)
2731{
2732 return i915->vbt.ddi_port_info[port].supports_tbt;
2733}