Commit | Line | Data |
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79e53945 | 1 | /* |
39507259 | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
b30581a4 | 27 | |
5b529e8d | 28 | #include <drm/dp/drm_dp_helper.h> |
3ce2ea65 | 29 | |
d8fe2ab6 | 30 | #include "display/intel_display.h" |
1bf2f3bf | 31 | #include "display/intel_display_types.h" |
379bc100 JN |
32 | #include "display/intel_gmbus.h" |
33 | ||
79e53945 | 34 | #include "i915_drv.h" |
ce2fce25 | 35 | #include "i915_reg.h" |
72341af4 JN |
36 | |
37 | #define _INTEL_BIOS_PRIVATE | |
38 | #include "intel_vbt_defs.h" | |
79e53945 | 39 | |
dd97950a JN |
40 | /** |
41 | * DOC: Video BIOS Table (VBT) | |
42 | * | |
43 | * The Video BIOS Table, or VBT, provides platform and board specific | |
44 | * configuration information to the driver that is not discoverable or available | |
45 | * through other means. The configuration is mostly related to display | |
46 | * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in | |
47 | * the PCI ROM. | |
48 | * | |
49 | * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB | |
50 | * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that | |
51 | * contain the actual configuration information. The VBT Header, and thus the | |
52 | * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the | |
53 | * BDB Header. The data blocks are concatenated after the BDB Header. The data | |
54 | * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of | |
55 | * data. (Block 53, the MIPI Sequence Block is an exception.) | |
56 | * | |
57 | * The driver parses the VBT during load. The relevant information is stored in | |
58 | * driver private data for ease of use, and the actual VBT is not read after | |
59 | * that. | |
60 | */ | |
61 | ||
0d9ef19b | 62 | /* Wrapper for VBT child device config */ |
3162d057 | 63 | struct intel_bios_encoder_data { |
7371fa34 JN |
64 | struct drm_i915_private *i915; |
65 | ||
0d9ef19b | 66 | struct child_device_config child; |
6e0d46e9 | 67 | struct dsc_compression_parameters_entry *dsc; |
0d9ef19b JN |
68 | struct list_head node; |
69 | }; | |
70 | ||
9b9d172d | 71 | #define SLAVE_ADDR1 0x70 |
72 | #define SLAVE_ADDR2 0x72 | |
79e53945 | 73 | |
08c0888b JN |
74 | /* Get BDB block size given a pointer to Block ID. */ |
75 | static u32 _get_blocksize(const u8 *block_base) | |
76 | { | |
77 | /* The MIPI Sequence Block v3+ has a separate size field. */ | |
78 | if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) | |
79 | return *((const u32 *)(block_base + 4)); | |
80 | else | |
81 | return *((const u16 *)(block_base + 1)); | |
82 | } | |
83 | ||
84 | /* Get BDB block size give a pointer to data after Block ID and Block Size. */ | |
85 | static u32 get_blocksize(const void *block_data) | |
86 | { | |
87 | return _get_blocksize(block_data - 3); | |
88 | } | |
89 | ||
e8ef3b4c | 90 | static const void * |
e163cfb4 | 91 | find_raw_section(const void *_bdb, enum bdb_block_id section_id) |
79e53945 | 92 | { |
e8ef3b4c JN |
93 | const struct bdb_header *bdb = _bdb; |
94 | const u8 *base = _bdb; | |
79e53945 | 95 | int index = 0; |
cd67d226 | 96 | u32 total, current_size; |
f41c6153 | 97 | enum bdb_block_id current_id; |
79e53945 JB |
98 | |
99 | /* skip to first section */ | |
100 | index += bdb->header_size; | |
101 | total = bdb->bdb_size; | |
102 | ||
103 | /* walk the sections looking for section_id */ | |
d1f13fd2 | 104 | while (index + 3 < total) { |
79e53945 | 105 | current_id = *(base + index); |
08c0888b JN |
106 | current_size = _get_blocksize(base + index); |
107 | index += 3; | |
cd67d226 | 108 | |
d1f13fd2 CW |
109 | if (index + current_size > total) |
110 | return NULL; | |
111 | ||
79e53945 JB |
112 | if (current_id == section_id) |
113 | return base + index; | |
d1f13fd2 | 114 | |
79e53945 JB |
115 | index += current_size; |
116 | } | |
117 | ||
118 | return NULL; | |
119 | } | |
120 | ||
e163cfb4 VS |
121 | /* |
122 | * Offset from the start of BDB to the start of the | |
123 | * block data (just past the block header). | |
124 | */ | |
125 | static u32 block_offset(const void *bdb, enum bdb_block_id section_id) | |
126 | { | |
127 | const void *block; | |
128 | ||
129 | block = find_raw_section(bdb, section_id); | |
130 | if (!block) | |
131 | return 0; | |
132 | ||
133 | return block - bdb; | |
134 | } | |
135 | ||
514003e1 VS |
136 | /* size of the block excluding the header */ |
137 | static u32 block_size(const void *bdb, enum bdb_block_id section_id) | |
138 | { | |
139 | const void *block; | |
140 | ||
141 | block = find_raw_section(bdb, section_id); | |
142 | if (!block) | |
143 | return 0; | |
144 | ||
145 | return get_blocksize(block); | |
146 | } | |
147 | ||
e163cfb4 VS |
148 | struct bdb_block_entry { |
149 | struct list_head node; | |
150 | enum bdb_block_id section_id; | |
151 | u8 data[]; | |
152 | }; | |
153 | ||
154 | static const void * | |
155 | find_section(struct drm_i915_private *i915, | |
156 | enum bdb_block_id section_id) | |
157 | { | |
158 | struct bdb_block_entry *entry; | |
159 | ||
160 | list_for_each_entry(entry, &i915->vbt.bdb_blocks, node) { | |
161 | if (entry->section_id == section_id) | |
162 | return entry->data + 3; | |
163 | } | |
164 | ||
165 | return NULL; | |
166 | } | |
167 | ||
168 | static const struct { | |
169 | enum bdb_block_id section_id; | |
170 | size_t min_size; | |
171 | } bdb_blocks[] = { | |
172 | { .section_id = BDB_GENERAL_FEATURES, | |
173 | .min_size = sizeof(struct bdb_general_features), }, | |
174 | { .section_id = BDB_GENERAL_DEFINITIONS, | |
175 | .min_size = sizeof(struct bdb_general_definitions), }, | |
176 | { .section_id = BDB_PSR, | |
177 | .min_size = sizeof(struct bdb_psr), }, | |
178 | { .section_id = BDB_DRIVER_FEATURES, | |
179 | .min_size = sizeof(struct bdb_driver_features), }, | |
180 | { .section_id = BDB_SDVO_LVDS_OPTIONS, | |
181 | .min_size = sizeof(struct bdb_sdvo_lvds_options), }, | |
182 | { .section_id = BDB_SDVO_PANEL_DTDS, | |
183 | .min_size = sizeof(struct bdb_sdvo_panel_dtds), }, | |
184 | { .section_id = BDB_EDP, | |
185 | .min_size = sizeof(struct bdb_edp), }, | |
186 | { .section_id = BDB_LVDS_OPTIONS, | |
187 | .min_size = sizeof(struct bdb_lvds_options), }, | |
901a0cad VS |
188 | /* |
189 | * BDB_LVDS_LFP_DATA depends on BDB_LVDS_LFP_DATA_PTRS, | |
190 | * so keep the two ordered. | |
191 | */ | |
e163cfb4 VS |
192 | { .section_id = BDB_LVDS_LFP_DATA_PTRS, |
193 | .min_size = sizeof(struct bdb_lvds_lfp_data_ptrs), }, | |
194 | { .section_id = BDB_LVDS_LFP_DATA, | |
901a0cad | 195 | .min_size = 0, /* special case */ }, |
e163cfb4 VS |
196 | { .section_id = BDB_LVDS_BACKLIGHT, |
197 | .min_size = sizeof(struct bdb_lfp_backlight_data), }, | |
198 | { .section_id = BDB_LFP_POWER, | |
199 | .min_size = sizeof(struct bdb_lfp_power), }, | |
200 | { .section_id = BDB_MIPI_CONFIG, | |
201 | .min_size = sizeof(struct bdb_mipi_config), }, | |
202 | { .section_id = BDB_MIPI_SEQUENCE, | |
203 | .min_size = sizeof(struct bdb_mipi_sequence) }, | |
204 | { .section_id = BDB_COMPRESSION_PARAMETERS, | |
205 | .min_size = sizeof(struct bdb_compression_parameters), }, | |
206 | { .section_id = BDB_GENERIC_DTD, | |
207 | .min_size = sizeof(struct bdb_generic_dtd), }, | |
208 | }; | |
209 | ||
901a0cad VS |
210 | static size_t lfp_data_min_size(struct drm_i915_private *i915) |
211 | { | |
212 | const struct bdb_lvds_lfp_data_ptrs *ptrs; | |
213 | size_t size; | |
214 | ||
215 | ptrs = find_section(i915, BDB_LVDS_LFP_DATA_PTRS); | |
216 | if (!ptrs) | |
217 | return 0; | |
218 | ||
219 | size = sizeof(struct bdb_lvds_lfp_data); | |
220 | if (ptrs->panel_name.table_size) | |
221 | size = max(size, ptrs->panel_name.offset + | |
222 | sizeof(struct bdb_lvds_lfp_data_tail)); | |
223 | ||
224 | return size; | |
225 | } | |
226 | ||
514003e1 VS |
227 | static bool validate_lfp_data_ptrs(const void *bdb, |
228 | const struct bdb_lvds_lfp_data_ptrs *ptrs) | |
229 | { | |
5ab58d69 | 230 | int fp_timing_size, dvo_timing_size, panel_pnp_id_size, panel_name_size; |
514003e1 VS |
231 | int data_block_size, lfp_data_size; |
232 | int i; | |
233 | ||
234 | data_block_size = block_size(bdb, BDB_LVDS_LFP_DATA); | |
235 | if (data_block_size == 0) | |
236 | return false; | |
237 | ||
238 | /* always 3 indicating the presence of fp_timing+dvo_timing+panel_pnp_id */ | |
239 | if (ptrs->lvds_entries != 3) | |
240 | return false; | |
241 | ||
242 | fp_timing_size = ptrs->ptr[0].fp_timing.table_size; | |
243 | dvo_timing_size = ptrs->ptr[0].dvo_timing.table_size; | |
244 | panel_pnp_id_size = ptrs->ptr[0].panel_pnp_id.table_size; | |
5ab58d69 | 245 | panel_name_size = ptrs->panel_name.table_size; |
514003e1 VS |
246 | |
247 | /* fp_timing has variable size */ | |
248 | if (fp_timing_size < 32 || | |
249 | dvo_timing_size != sizeof(struct lvds_dvo_timing) || | |
250 | panel_pnp_id_size != sizeof(struct lvds_pnp_id)) | |
251 | return false; | |
252 | ||
5ab58d69 VS |
253 | /* panel_name is not present in old VBTs */ |
254 | if (panel_name_size != 0 && | |
255 | panel_name_size != sizeof(struct lvds_lfp_panel_name)) | |
256 | return false; | |
257 | ||
514003e1 VS |
258 | lfp_data_size = ptrs->ptr[1].fp_timing.offset - ptrs->ptr[0].fp_timing.offset; |
259 | if (16 * lfp_data_size > data_block_size) | |
260 | return false; | |
261 | ||
262 | /* | |
263 | * Except for vlv/chv machines all real VBTs seem to have 6 | |
264 | * unaccounted bytes in the fp_timing table. And it doesn't | |
265 | * appear to be a really intentional hole as the fp_timing | |
266 | * 0xffff terminator is always within those 6 missing bytes. | |
267 | */ | |
268 | if (fp_timing_size + dvo_timing_size + panel_pnp_id_size != lfp_data_size && | |
269 | fp_timing_size + 6 + dvo_timing_size + panel_pnp_id_size != lfp_data_size) | |
270 | return false; | |
271 | ||
272 | if (ptrs->ptr[0].fp_timing.offset + fp_timing_size > ptrs->ptr[0].dvo_timing.offset || | |
273 | ptrs->ptr[0].dvo_timing.offset + dvo_timing_size != ptrs->ptr[0].panel_pnp_id.offset || | |
274 | ptrs->ptr[0].panel_pnp_id.offset + panel_pnp_id_size != lfp_data_size) | |
275 | return false; | |
276 | ||
277 | /* make sure the table entries have uniform size */ | |
278 | for (i = 1; i < 16; i++) { | |
279 | if (ptrs->ptr[i].fp_timing.table_size != fp_timing_size || | |
280 | ptrs->ptr[i].dvo_timing.table_size != dvo_timing_size || | |
281 | ptrs->ptr[i].panel_pnp_id.table_size != panel_pnp_id_size) | |
282 | return false; | |
283 | ||
284 | if (ptrs->ptr[i].fp_timing.offset - ptrs->ptr[i-1].fp_timing.offset != lfp_data_size || | |
285 | ptrs->ptr[i].dvo_timing.offset - ptrs->ptr[i-1].dvo_timing.offset != lfp_data_size || | |
286 | ptrs->ptr[i].panel_pnp_id.offset - ptrs->ptr[i-1].panel_pnp_id.offset != lfp_data_size) | |
287 | return false; | |
288 | } | |
289 | ||
290 | /* make sure the tables fit inside the data block */ | |
291 | for (i = 0; i < 16; i++) { | |
292 | if (ptrs->ptr[i].fp_timing.offset + fp_timing_size > data_block_size || | |
293 | ptrs->ptr[i].dvo_timing.offset + dvo_timing_size > data_block_size || | |
294 | ptrs->ptr[i].panel_pnp_id.offset + panel_pnp_id_size > data_block_size) | |
295 | return false; | |
296 | } | |
297 | ||
5ab58d69 VS |
298 | if (ptrs->panel_name.offset + 16 * panel_name_size > data_block_size) |
299 | return false; | |
300 | ||
514003e1 VS |
301 | return true; |
302 | } | |
303 | ||
918f3025 VS |
304 | /* make the data table offsets relative to the data block */ |
305 | static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block) | |
306 | { | |
307 | struct bdb_lvds_lfp_data_ptrs *ptrs = ptrs_block; | |
308 | u32 offset; | |
309 | int i; | |
310 | ||
311 | offset = block_offset(bdb, BDB_LVDS_LFP_DATA); | |
312 | ||
313 | for (i = 0; i < 16; i++) { | |
314 | if (ptrs->ptr[i].fp_timing.offset < offset || | |
315 | ptrs->ptr[i].dvo_timing.offset < offset || | |
316 | ptrs->ptr[i].panel_pnp_id.offset < offset) | |
317 | return false; | |
318 | ||
319 | ptrs->ptr[i].fp_timing.offset -= offset; | |
320 | ptrs->ptr[i].dvo_timing.offset -= offset; | |
321 | ptrs->ptr[i].panel_pnp_id.offset -= offset; | |
322 | } | |
323 | ||
5ab58d69 VS |
324 | if (ptrs->panel_name.table_size) { |
325 | if (ptrs->panel_name.offset < offset) | |
326 | return false; | |
327 | ||
328 | ptrs->panel_name.offset -= offset; | |
329 | } | |
330 | ||
514003e1 | 331 | return validate_lfp_data_ptrs(bdb, ptrs); |
918f3025 VS |
332 | } |
333 | ||
a87d0a84 VS |
334 | static const void *find_fp_timing_terminator(const u8 *data, int size) |
335 | { | |
336 | int i; | |
337 | ||
338 | for (i = 0; i < size - 1; i++) { | |
339 | if (data[i] == 0xff && data[i+1] == 0xff) | |
340 | return &data[i]; | |
341 | } | |
342 | ||
343 | return NULL; | |
344 | } | |
345 | ||
346 | static int make_lfp_data_ptr(struct lvds_lfp_data_ptr_table *table, | |
347 | int table_size, int total_size) | |
348 | { | |
349 | if (total_size < table_size) | |
350 | return total_size; | |
351 | ||
352 | table->table_size = table_size; | |
353 | table->offset = total_size - table_size; | |
354 | ||
355 | return total_size - table_size; | |
356 | } | |
357 | ||
358 | static void next_lfp_data_ptr(struct lvds_lfp_data_ptr_table *next, | |
359 | const struct lvds_lfp_data_ptr_table *prev, | |
360 | int size) | |
361 | { | |
362 | next->table_size = prev->table_size; | |
363 | next->offset = prev->offset + size; | |
364 | } | |
365 | ||
366 | static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, | |
367 | const void *bdb) | |
368 | { | |
369 | int i, size, table_size, block_size, offset; | |
370 | const void *t0, *t1, *block; | |
371 | struct bdb_lvds_lfp_data_ptrs *ptrs; | |
372 | void *ptrs_block; | |
373 | ||
374 | block = find_raw_section(bdb, BDB_LVDS_LFP_DATA); | |
375 | if (!block) | |
376 | return NULL; | |
377 | ||
378 | drm_dbg_kms(&i915->drm, "Generating LFP data table pointers\n"); | |
379 | ||
380 | block_size = get_blocksize(block); | |
381 | ||
382 | size = block_size; | |
383 | t0 = find_fp_timing_terminator(block, size); | |
384 | if (!t0) | |
385 | return NULL; | |
386 | ||
387 | size -= t0 - block - 2; | |
388 | t1 = find_fp_timing_terminator(t0 + 2, size); | |
389 | if (!t1) | |
390 | return NULL; | |
391 | ||
392 | size = t1 - t0; | |
393 | if (size * 16 > block_size) | |
394 | return NULL; | |
395 | ||
396 | ptrs_block = kzalloc(sizeof(*ptrs) + 3, GFP_KERNEL); | |
397 | if (!ptrs_block) | |
398 | return NULL; | |
399 | ||
400 | *(u8 *)(ptrs_block + 0) = BDB_LVDS_LFP_DATA_PTRS; | |
401 | *(u16 *)(ptrs_block + 1) = sizeof(*ptrs); | |
402 | ptrs = ptrs_block + 3; | |
403 | ||
404 | table_size = sizeof(struct lvds_pnp_id); | |
405 | size = make_lfp_data_ptr(&ptrs->ptr[0].panel_pnp_id, table_size, size); | |
406 | ||
407 | table_size = sizeof(struct lvds_dvo_timing); | |
408 | size = make_lfp_data_ptr(&ptrs->ptr[0].dvo_timing, table_size, size); | |
409 | ||
410 | table_size = t0 - block + 2; | |
411 | size = make_lfp_data_ptr(&ptrs->ptr[0].fp_timing, table_size, size); | |
412 | ||
413 | if (ptrs->ptr[0].fp_timing.table_size) | |
414 | ptrs->lvds_entries++; | |
415 | if (ptrs->ptr[0].dvo_timing.table_size) | |
416 | ptrs->lvds_entries++; | |
417 | if (ptrs->ptr[0].panel_pnp_id.table_size) | |
418 | ptrs->lvds_entries++; | |
419 | ||
420 | if (size != 0 || ptrs->lvds_entries != 3) { | |
421 | kfree(ptrs); | |
422 | return NULL; | |
423 | } | |
424 | ||
425 | size = t1 - t0; | |
426 | for (i = 1; i < 16; i++) { | |
427 | next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, &ptrs->ptr[i-1].fp_timing, size); | |
428 | next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, &ptrs->ptr[i-1].dvo_timing, size); | |
429 | next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, &ptrs->ptr[i-1].panel_pnp_id, size); | |
430 | } | |
431 | ||
432 | size = t1 - t0; | |
433 | table_size = sizeof(struct lvds_lfp_panel_name); | |
434 | ||
435 | if (16 * (size + table_size) <= block_size) { | |
436 | ptrs->panel_name.table_size = table_size; | |
437 | ptrs->panel_name.offset = size * 16; | |
438 | } | |
439 | ||
440 | offset = block - bdb; | |
441 | ||
442 | for (i = 0; i < 16; i++) { | |
443 | ptrs->ptr[i].fp_timing.offset += offset; | |
444 | ptrs->ptr[i].dvo_timing.offset += offset; | |
445 | ptrs->ptr[i].panel_pnp_id.offset += offset; | |
446 | } | |
447 | ||
448 | if (ptrs->panel_name.table_size) | |
449 | ptrs->panel_name.offset += offset; | |
450 | ||
451 | return ptrs_block; | |
452 | } | |
453 | ||
e163cfb4 VS |
454 | static void |
455 | init_bdb_block(struct drm_i915_private *i915, | |
456 | const void *bdb, enum bdb_block_id section_id, | |
457 | size_t min_size) | |
458 | { | |
459 | struct bdb_block_entry *entry; | |
a87d0a84 | 460 | void *temp_block = NULL; |
e163cfb4 VS |
461 | const void *block; |
462 | size_t block_size; | |
463 | ||
464 | block = find_raw_section(bdb, section_id); | |
a87d0a84 VS |
465 | |
466 | /* Modern VBTs lack the LFP data table pointers block, make one up */ | |
467 | if (!block && section_id == BDB_LVDS_LFP_DATA_PTRS) { | |
468 | temp_block = generate_lfp_data_ptrs(i915, bdb); | |
469 | if (temp_block) | |
470 | block = temp_block + 3; | |
471 | } | |
e163cfb4 VS |
472 | if (!block) |
473 | return; | |
474 | ||
475 | drm_WARN(&i915->drm, min_size == 0, | |
476 | "Block %d min_size is zero\n", section_id); | |
477 | ||
478 | block_size = get_blocksize(block); | |
479 | ||
480 | entry = kzalloc(struct_size(entry, data, max(min_size, block_size) + 3), | |
481 | GFP_KERNEL); | |
a87d0a84 VS |
482 | if (!entry) { |
483 | kfree(temp_block); | |
e163cfb4 | 484 | return; |
a87d0a84 | 485 | } |
e163cfb4 VS |
486 | |
487 | entry->section_id = section_id; | |
488 | memcpy(entry->data, block - 3, block_size + 3); | |
489 | ||
a87d0a84 VS |
490 | kfree(temp_block); |
491 | ||
e163cfb4 VS |
492 | drm_dbg_kms(&i915->drm, "Found BDB block %d (size %zu, min size %zu)\n", |
493 | section_id, block_size, min_size); | |
494 | ||
918f3025 VS |
495 | if (section_id == BDB_LVDS_LFP_DATA_PTRS && |
496 | !fixup_lfp_data_ptrs(bdb, entry->data + 3)) { | |
497 | drm_err(&i915->drm, "VBT has malformed LFP data table pointers\n"); | |
498 | kfree(entry); | |
499 | return; | |
500 | } | |
501 | ||
e163cfb4 VS |
502 | list_add_tail(&entry->node, &i915->vbt.bdb_blocks); |
503 | } | |
504 | ||
505 | static void init_bdb_blocks(struct drm_i915_private *i915, | |
506 | const void *bdb) | |
507 | { | |
508 | int i; | |
509 | ||
510 | for (i = 0; i < ARRAY_SIZE(bdb_blocks); i++) { | |
511 | enum bdb_block_id section_id = bdb_blocks[i].section_id; | |
512 | size_t min_size = bdb_blocks[i].min_size; | |
513 | ||
901a0cad VS |
514 | if (section_id == BDB_LVDS_LFP_DATA) |
515 | min_size = lfp_data_min_size(i915); | |
516 | ||
e163cfb4 VS |
517 | init_bdb_block(i915, bdb, section_id, min_size); |
518 | } | |
519 | } | |
520 | ||
79e53945 | 521 | static void |
88631706 | 522 | fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, |
99834ea4 | 523 | const struct lvds_dvo_timing *dvo_timing) |
88631706 ML |
524 | { |
525 | panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | | |
526 | dvo_timing->hactive_lo; | |
527 | panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + | |
528 | ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); | |
529 | panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + | |
ce2e87b4 VT |
530 | ((dvo_timing->hsync_pulse_width_hi << 8) | |
531 | dvo_timing->hsync_pulse_width_lo); | |
88631706 ML |
532 | panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + |
533 | ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); | |
534 | ||
535 | panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | | |
536 | dvo_timing->vactive_lo; | |
537 | panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + | |
ce2e87b4 | 538 | ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo); |
88631706 | 539 | panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + |
ce2e87b4 VT |
540 | ((dvo_timing->vsync_pulse_width_hi << 4) | |
541 | dvo_timing->vsync_pulse_width_lo); | |
88631706 ML |
542 | panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + |
543 | ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); | |
544 | panel_fixed_mode->clock = dvo_timing->clock * 10; | |
545 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
546 | ||
9bc35499 AJ |
547 | if (dvo_timing->hsync_positive) |
548 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
549 | else | |
550 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
551 | ||
552 | if (dvo_timing->vsync_positive) | |
553 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
554 | else | |
555 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
556 | ||
df457245 VS |
557 | panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) | |
558 | dvo_timing->himage_lo; | |
559 | panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) | | |
560 | dvo_timing->vimage_lo; | |
561 | ||
88631706 ML |
562 | /* Some VBTs have bogus h/vtotal values */ |
563 | if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) | |
564 | panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; | |
565 | if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) | |
566 | panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; | |
567 | ||
568 | drm_mode_set_name(panel_fixed_mode); | |
569 | } | |
570 | ||
99834ea4 | 571 | static const struct lvds_dvo_timing * |
58b2e382 VS |
572 | get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *data, |
573 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
99834ea4 CW |
574 | int index) |
575 | { | |
58b2e382 | 576 | return (const void *)data + ptrs->ptr[index].dvo_timing.offset; |
99834ea4 CW |
577 | } |
578 | ||
b0354385 | 579 | static const struct lvds_fp_timing * |
918f3025 | 580 | get_lvds_fp_timing(const struct bdb_lvds_lfp_data *data, |
b0354385 TI |
581 | const struct bdb_lvds_lfp_data_ptrs *ptrs, |
582 | int index) | |
583 | { | |
58b2e382 | 584 | return (const void *)data + ptrs->ptr[index].fp_timing.offset; |
b0354385 TI |
585 | } |
586 | ||
901a0cad VS |
587 | static const struct bdb_lvds_lfp_data_tail * |
588 | get_lfp_data_tail(const struct bdb_lvds_lfp_data *data, | |
589 | const struct bdb_lvds_lfp_data_ptrs *ptrs) | |
590 | { | |
591 | if (ptrs->panel_name.table_size) | |
592 | return (const void *)data + ptrs->panel_name.offset; | |
593 | else | |
594 | return NULL; | |
595 | } | |
596 | ||
9e7ecedf | 597 | /* Parse general panel options */ |
88631706 | 598 | static void |
e163cfb4 | 599 | parse_panel_options(struct drm_i915_private *i915) |
79e53945 | 600 | { |
99834ea4 | 601 | const struct bdb_lvds_options *lvds_options; |
3e845c7a | 602 | int panel_type; |
c329a4ec | 603 | int drrs_mode; |
a0562819 | 604 | int ret; |
79e53945 | 605 | |
e163cfb4 | 606 | lvds_options = find_section(i915, BDB_LVDS_OPTIONS); |
79e53945 JB |
607 | if (!lvds_options) |
608 | return; | |
609 | ||
dbd440d8 | 610 | i915->vbt.lvds_dither = lvds_options->pixel_dither; |
a0562819 | 611 | |
dbd440d8 | 612 | ret = intel_opregion_get_panel_type(i915); |
a0562819 | 613 | if (ret >= 0) { |
dbd440d8 | 614 | drm_WARN_ON(&i915->drm, ret > 0xf); |
a0562819 | 615 | panel_type = ret; |
dbd440d8 | 616 | drm_dbg_kms(&i915->drm, "Panel type: %d (OpRegion)\n", |
e92cbf38 | 617 | panel_type); |
a0562819 VS |
618 | } else { |
619 | if (lvds_options->panel_type > 0xf) { | |
dbd440d8 | 620 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
621 | "Invalid VBT panel type 0x%x\n", |
622 | lvds_options->panel_type); | |
a0562819 VS |
623 | return; |
624 | } | |
625 | panel_type = lvds_options->panel_type; | |
dbd440d8 | 626 | drm_dbg_kms(&i915->drm, "Panel type: %d (VBT)\n", |
e92cbf38 | 627 | panel_type); |
eeeebea6 | 628 | } |
6a04002b | 629 | |
dbd440d8 | 630 | i915->vbt.panel_type = panel_type; |
79e53945 | 631 | |
83a7280e PB |
632 | drrs_mode = (lvds_options->dps_panel_type_bits |
633 | >> (panel_type * 2)) & MODE_MASK; | |
634 | /* | |
635 | * VBT has static DRRS = 0 and seamless DRRS = 2. | |
636 | * The below piece of code is required to adjust vbt.drrs_type | |
637 | * to match the enum drrs_support_type. | |
638 | */ | |
639 | switch (drrs_mode) { | |
640 | case 0: | |
8e9c9848 | 641 | i915->vbt.drrs_type = DRRS_TYPE_STATIC; |
dbd440d8 | 642 | drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n"); |
83a7280e PB |
643 | break; |
644 | case 2: | |
8e9c9848 | 645 | i915->vbt.drrs_type = DRRS_TYPE_SEAMLESS; |
dbd440d8 | 646 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 647 | "DRRS supported mode is seamless\n"); |
83a7280e PB |
648 | break; |
649 | default: | |
8e9c9848 | 650 | i915->vbt.drrs_type = DRRS_TYPE_NONE; |
dbd440d8 | 651 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 652 | "DRRS not supported (VBT input)\n"); |
83a7280e PB |
653 | break; |
654 | } | |
9e7ecedf MR |
655 | } |
656 | ||
9e7ecedf | 657 | static void |
13367132 VS |
658 | parse_lfp_panel_dtd(struct drm_i915_private *i915, |
659 | const struct bdb_lvds_lfp_data *lvds_lfp_data, | |
660 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs) | |
9e7ecedf | 661 | { |
9e7ecedf MR |
662 | const struct lvds_dvo_timing *panel_dvo_timing; |
663 | const struct lvds_fp_timing *fp_timing; | |
664 | struct drm_display_mode *panel_fixed_mode; | |
dbd440d8 | 665 | int panel_type = i915->vbt.panel_type; |
83a7280e | 666 | |
99834ea4 CW |
667 | panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, |
668 | lvds_lfp_data_ptrs, | |
3e845c7a | 669 | panel_type); |
79e53945 | 670 | |
9a298b2a | 671 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
6edc3242 CW |
672 | if (!panel_fixed_mode) |
673 | return; | |
79e53945 | 674 | |
99834ea4 | 675 | fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); |
79e53945 | 676 | |
dbd440d8 | 677 | i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 678 | |
dbd440d8 | 679 | drm_dbg_kms(&i915->drm, |
f01bae2d VS |
680 | "Found panel mode in BIOS VBT legacy lfp table: " DRM_MODE_FMT "\n", |
681 | DRM_MODE_ARG(panel_fixed_mode)); | |
37df9673 | 682 | |
918f3025 | 683 | fp_timing = get_lvds_fp_timing(lvds_lfp_data, |
b0354385 | 684 | lvds_lfp_data_ptrs, |
3e845c7a | 685 | panel_type); |
58b2e382 VS |
686 | |
687 | /* check the resolution, just to be sure */ | |
688 | if (fp_timing->x_res == panel_fixed_mode->hdisplay && | |
689 | fp_timing->y_res == panel_fixed_mode->vdisplay) { | |
690 | i915->vbt.bios_lvds_val = fp_timing->lvds_reg_val; | |
691 | drm_dbg_kms(&i915->drm, | |
692 | "VBT initial LVDS value %x\n", | |
693 | i915->vbt.bios_lvds_val); | |
b0354385 | 694 | } |
88631706 ML |
695 | } |
696 | ||
13367132 VS |
697 | static void |
698 | parse_lfp_data(struct drm_i915_private *i915) | |
699 | { | |
700 | const struct bdb_lvds_lfp_data *data; | |
901a0cad | 701 | const struct bdb_lvds_lfp_data_tail *tail; |
13367132 VS |
702 | const struct bdb_lvds_lfp_data_ptrs *ptrs; |
703 | ||
704 | ptrs = find_section(i915, BDB_LVDS_LFP_DATA_PTRS); | |
705 | if (!ptrs) | |
706 | return; | |
707 | ||
708 | data = find_section(i915, BDB_LVDS_LFP_DATA); | |
709 | if (!data) | |
710 | return; | |
711 | ||
712 | if (!i915->vbt.lfp_lvds_vbt_mode) | |
713 | parse_lfp_panel_dtd(i915, data, ptrs); | |
901a0cad VS |
714 | |
715 | tail = get_lfp_data_tail(data, ptrs); | |
716 | if (!tail) | |
717 | return; | |
718 | ||
719 | (void)tail; | |
13367132 VS |
720 | } |
721 | ||
33ef6d4f | 722 | static void |
e163cfb4 | 723 | parse_generic_dtd(struct drm_i915_private *i915) |
33ef6d4f MR |
724 | { |
725 | const struct bdb_generic_dtd *generic_dtd; | |
726 | const struct generic_dtd_entry *dtd; | |
727 | struct drm_display_mode *panel_fixed_mode; | |
728 | int num_dtd; | |
729 | ||
13367132 VS |
730 | /* |
731 | * Older VBTs provided DTD information for internal displays through | |
732 | * the "LFP panel tables" block (42). As of VBT revision 229 the | |
733 | * DTD information should be provided via a newer "generic DTD" | |
734 | * block (58). Just to be safe, we'll try the new generic DTD block | |
735 | * first on VBT >= 229, but still fall back to trying the old LFP | |
736 | * block if that fails. | |
737 | */ | |
738 | if (i915->vbt.version < 229) | |
739 | return; | |
740 | ||
e163cfb4 | 741 | generic_dtd = find_section(i915, BDB_GENERIC_DTD); |
33ef6d4f MR |
742 | if (!generic_dtd) |
743 | return; | |
744 | ||
745 | if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) { | |
dbd440d8 | 746 | drm_err(&i915->drm, "GDTD size %u is too small.\n", |
e92cbf38 | 747 | generic_dtd->gdtd_size); |
33ef6d4f MR |
748 | return; |
749 | } else if (generic_dtd->gdtd_size != | |
750 | sizeof(struct generic_dtd_entry)) { | |
dbd440d8 | 751 | drm_err(&i915->drm, "Unexpected GDTD size %u\n", |
e92cbf38 | 752 | generic_dtd->gdtd_size); |
33ef6d4f MR |
753 | /* DTD has unknown fields, but keep going */ |
754 | } | |
755 | ||
756 | num_dtd = (get_blocksize(generic_dtd) - | |
757 | sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size; | |
dbd440d8 JN |
758 | if (i915->vbt.panel_type >= num_dtd) { |
759 | drm_err(&i915->drm, | |
e92cbf38 | 760 | "Panel type %d not found in table of %d DTD's\n", |
dbd440d8 | 761 | i915->vbt.panel_type, num_dtd); |
33ef6d4f MR |
762 | return; |
763 | } | |
764 | ||
dbd440d8 | 765 | dtd = &generic_dtd->dtd[i915->vbt.panel_type]; |
33ef6d4f MR |
766 | |
767 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); | |
768 | if (!panel_fixed_mode) | |
769 | return; | |
770 | ||
771 | panel_fixed_mode->hdisplay = dtd->hactive; | |
772 | panel_fixed_mode->hsync_start = | |
773 | panel_fixed_mode->hdisplay + dtd->hfront_porch; | |
774 | panel_fixed_mode->hsync_end = | |
775 | panel_fixed_mode->hsync_start + dtd->hsync; | |
ad278f35 VK |
776 | panel_fixed_mode->htotal = |
777 | panel_fixed_mode->hdisplay + dtd->hblank; | |
33ef6d4f MR |
778 | |
779 | panel_fixed_mode->vdisplay = dtd->vactive; | |
780 | panel_fixed_mode->vsync_start = | |
781 | panel_fixed_mode->vdisplay + dtd->vfront_porch; | |
782 | panel_fixed_mode->vsync_end = | |
783 | panel_fixed_mode->vsync_start + dtd->vsync; | |
ad278f35 VK |
784 | panel_fixed_mode->vtotal = |
785 | panel_fixed_mode->vdisplay + dtd->vblank; | |
33ef6d4f MR |
786 | |
787 | panel_fixed_mode->clock = dtd->pixel_clock; | |
788 | panel_fixed_mode->width_mm = dtd->width_mm; | |
789 | panel_fixed_mode->height_mm = dtd->height_mm; | |
790 | ||
791 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
792 | drm_mode_set_name(panel_fixed_mode); | |
793 | ||
794 | if (dtd->hsync_positive_polarity) | |
795 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
796 | else | |
797 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
798 | ||
799 | if (dtd->vsync_positive_polarity) | |
800 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
801 | else | |
802 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
803 | ||
dbd440d8 | 804 | drm_dbg_kms(&i915->drm, |
f01bae2d VS |
805 | "Found panel mode in BIOS VBT generic dtd table: " DRM_MODE_FMT "\n", |
806 | DRM_MODE_ARG(panel_fixed_mode)); | |
33ef6d4f | 807 | |
dbd440d8 | 808 | i915->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
33ef6d4f MR |
809 | } |
810 | ||
f00076d2 | 811 | static void |
e163cfb4 | 812 | parse_lfp_backlight(struct drm_i915_private *i915) |
f00076d2 JN |
813 | { |
814 | const struct bdb_lfp_backlight_data *backlight_data; | |
f87f6599 | 815 | const struct lfp_backlight_data_entry *entry; |
dbd440d8 | 816 | int panel_type = i915->vbt.panel_type; |
d381baad | 817 | u16 level; |
f00076d2 | 818 | |
e163cfb4 | 819 | backlight_data = find_section(i915, BDB_LVDS_BACKLIGHT); |
f00076d2 JN |
820 | if (!backlight_data) |
821 | return; | |
822 | ||
823 | if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { | |
dbd440d8 | 824 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
825 | "Unsupported backlight data entry size %u\n", |
826 | backlight_data->entry_size); | |
f00076d2 JN |
827 | return; |
828 | } | |
829 | ||
830 | entry = &backlight_data->data[panel_type]; | |
831 | ||
dbd440d8 JN |
832 | i915->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; |
833 | if (!i915->vbt.backlight.present) { | |
834 | drm_dbg_kms(&i915->drm, | |
e92cbf38 WK |
835 | "PWM backlight not present in VBT (type %u)\n", |
836 | entry->type); | |
39fbc9c8 JN |
837 | return; |
838 | } | |
839 | ||
dbd440d8 | 840 | i915->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; |
d58a3d69 | 841 | if (i915->vbt.version >= 191) { |
4378daf5 | 842 | size_t exp_size; |
9a41e17d | 843 | |
d58a3d69 | 844 | if (i915->vbt.version >= 236) |
4378daf5 | 845 | exp_size = sizeof(struct bdb_lfp_backlight_data); |
d58a3d69 | 846 | else if (i915->vbt.version >= 234) |
4378daf5 LM |
847 | exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234; |
848 | else | |
849 | exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191; | |
850 | ||
851 | if (get_blocksize(backlight_data) >= exp_size) { | |
852 | const struct lfp_backlight_control_method *method; | |
853 | ||
854 | method = &backlight_data->backlight_control[panel_type]; | |
855 | i915->vbt.backlight.type = method->type; | |
856 | i915->vbt.backlight.controller = method->controller; | |
857 | } | |
9a41e17d D |
858 | } |
859 | ||
dbd440d8 JN |
860 | i915->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; |
861 | i915->vbt.backlight.active_low_pwm = entry->active_low_pwm; | |
d381baad | 862 | |
d58a3d69 | 863 | if (i915->vbt.version >= 234) { |
d381baad JRS |
864 | u16 min_level; |
865 | bool scale; | |
866 | ||
867 | level = backlight_data->brightness_level[panel_type].level; | |
868 | min_level = backlight_data->brightness_min_level[panel_type].level; | |
869 | ||
d58a3d69 | 870 | if (i915->vbt.version >= 236) |
d381baad JRS |
871 | scale = backlight_data->brightness_precision_bits[panel_type] == 16; |
872 | else | |
873 | scale = level > 255; | |
874 | ||
875 | if (scale) | |
876 | min_level = min_level / 255; | |
877 | ||
878 | if (min_level > 255) { | |
dbd440d8 | 879 | drm_warn(&i915->drm, "Brightness min level > 255\n"); |
d381baad JRS |
880 | level = 255; |
881 | } | |
dbd440d8 | 882 | i915->vbt.backlight.min_brightness = min_level; |
84d3d71f LS |
883 | |
884 | i915->vbt.backlight.brightness_precision_bits = | |
885 | backlight_data->brightness_precision_bits[panel_type]; | |
d381baad JRS |
886 | } else { |
887 | level = backlight_data->level[panel_type]; | |
dbd440d8 | 888 | i915->vbt.backlight.min_brightness = entry->min_brightness; |
d381baad JRS |
889 | } |
890 | ||
dbd440d8 | 891 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
892 | "VBT backlight PWM modulation frequency %u Hz, " |
893 | "active %s, min brightness %u, level %u, controller %u\n", | |
dbd440d8 JN |
894 | i915->vbt.backlight.pwm_freq_hz, |
895 | i915->vbt.backlight.active_low_pwm ? "low" : "high", | |
896 | i915->vbt.backlight.min_brightness, | |
d381baad | 897 | level, |
dbd440d8 | 898 | i915->vbt.backlight.controller); |
f00076d2 JN |
899 | } |
900 | ||
88631706 ML |
901 | /* Try to find sdvo panel data */ |
902 | static void | |
e163cfb4 | 903 | parse_sdvo_panel_data(struct drm_i915_private *i915) |
88631706 | 904 | { |
f87f6599 | 905 | const struct bdb_sdvo_panel_dtds *dtds; |
88631706 | 906 | struct drm_display_mode *panel_fixed_mode; |
5a1e5b6c | 907 | int index; |
79e53945 | 908 | |
dbd440d8 | 909 | index = i915->params.vbt_sdvo_panel_type; |
c10e408a | 910 | if (index == -2) { |
dbd440d8 | 911 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 912 | "Ignore SDVO panel mode from BIOS VBT tables.\n"); |
c10e408a MF |
913 | return; |
914 | } | |
915 | ||
5a1e5b6c | 916 | if (index == -1) { |
e8ef3b4c | 917 | const struct bdb_sdvo_lvds_options *sdvo_lvds_options; |
5a1e5b6c | 918 | |
e163cfb4 | 919 | sdvo_lvds_options = find_section(i915, BDB_SDVO_LVDS_OPTIONS); |
5a1e5b6c CW |
920 | if (!sdvo_lvds_options) |
921 | return; | |
922 | ||
923 | index = sdvo_lvds_options->panel_type; | |
924 | } | |
88631706 | 925 | |
e163cfb4 | 926 | dtds = find_section(i915, BDB_SDVO_PANEL_DTDS); |
f87f6599 | 927 | if (!dtds) |
88631706 ML |
928 | return; |
929 | ||
9a298b2a | 930 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
88631706 ML |
931 | if (!panel_fixed_mode) |
932 | return; | |
933 | ||
f87f6599 | 934 | fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]); |
88631706 | 935 | |
dbd440d8 | 936 | i915->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 937 | |
dbd440d8 | 938 | drm_dbg_kms(&i915->drm, |
f01bae2d VS |
939 | "Found SDVO panel mode in BIOS VBT tables: " DRM_MODE_FMT "\n", |
940 | DRM_MODE_ARG(panel_fixed_mode)); | |
79e53945 JB |
941 | } |
942 | ||
dbd440d8 | 943 | static int intel_bios_ssc_frequency(struct drm_i915_private *i915, |
9a4114ff BF |
944 | bool alternate) |
945 | { | |
005e9537 | 946 | switch (DISPLAY_VER(i915)) { |
9a4114ff | 947 | case 2: |
e91e941b | 948 | return alternate ? 66667 : 48000; |
9a4114ff BF |
949 | case 3: |
950 | case 4: | |
e91e941b | 951 | return alternate ? 100000 : 96000; |
9a4114ff | 952 | default: |
e91e941b | 953 | return alternate ? 100000 : 120000; |
9a4114ff BF |
954 | } |
955 | } | |
956 | ||
79e53945 | 957 | static void |
e163cfb4 | 958 | parse_general_features(struct drm_i915_private *i915) |
79e53945 | 959 | { |
e8ef3b4c | 960 | const struct bdb_general_features *general; |
79e53945 | 961 | |
e163cfb4 | 962 | general = find_section(i915, BDB_GENERAL_FEATURES); |
34957e8c JN |
963 | if (!general) |
964 | return; | |
965 | ||
dbd440d8 | 966 | i915->vbt.int_tv_support = general->int_tv_support; |
34957e8c | 967 | /* int_crt_support can't be trusted on earlier platforms */ |
d58a3d69 | 968 | if (i915->vbt.version >= 155 && |
dbd440d8 JN |
969 | (HAS_DDI(i915) || IS_VALLEYVIEW(i915))) |
970 | i915->vbt.int_crt_support = general->int_crt_support; | |
971 | i915->vbt.lvds_use_ssc = general->enable_ssc; | |
972 | i915->vbt.lvds_ssc_freq = | |
973 | intel_bios_ssc_frequency(i915, general->ssc_freq); | |
974 | i915->vbt.display_clock_mode = general->display_clock_mode; | |
975 | i915->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; | |
d58a3d69 | 976 | if (i915->vbt.version >= 181) { |
dbd440d8 | 977 | i915->vbt.orientation = general->rotate_180 ? |
c1cd5b24 VS |
978 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP : |
979 | DRM_MODE_PANEL_ORIENTATION_NORMAL; | |
980 | } else { | |
dbd440d8 | 981 | i915->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; |
c1cd5b24 | 982 | } |
b70ad01a | 983 | |
d58a3d69 | 984 | if (i915->vbt.version >= 249 && general->afc_startup_config) { |
b70ad01a JRS |
985 | i915->vbt.override_afc_startup = true; |
986 | i915->vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7; | |
987 | } | |
988 | ||
dbd440d8 | 989 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 990 | "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", |
dbd440d8 JN |
991 | i915->vbt.int_tv_support, |
992 | i915->vbt.int_crt_support, | |
993 | i915->vbt.lvds_use_ssc, | |
994 | i915->vbt.lvds_ssc_freq, | |
995 | i915->vbt.display_clock_mode, | |
996 | i915->vbt.fdi_rx_polarity_inverted); | |
79e53945 JB |
997 | } |
998 | ||
cc998589 | 999 | static const struct child_device_config * |
e192839e | 1000 | child_device_ptr(const struct bdb_general_definitions *defs, int i) |
90e4f159 | 1001 | { |
e192839e | 1002 | return (const void *) &defs->devices[i * defs->child_dev_size]; |
90e4f159 VS |
1003 | } |
1004 | ||
9b9d172d | 1005 | static void |
ef0096e4 | 1006 | parse_sdvo_device_mapping(struct drm_i915_private *i915) |
9b9d172d | 1007 | { |
e192839e | 1008 | struct sdvo_device_mapping *mapping; |
3162d057 | 1009 | const struct intel_bios_encoder_data *devdata; |
cc998589 | 1010 | const struct child_device_config *child; |
0d9ef19b | 1011 | int count = 0; |
6cc38aca JN |
1012 | |
1013 | /* | |
0ebdabe6 JN |
1014 | * Only parse SDVO mappings on gens that could have SDVO. This isn't |
1015 | * accurate and doesn't have to be, as long as it's not too strict. | |
9b9d172d | 1016 | */ |
93e7e61e | 1017 | if (!IS_DISPLAY_VER(i915, 3, 7)) { |
dbd440d8 | 1018 | drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n"); |
9b9d172d | 1019 | return; |
1020 | } | |
0ebdabe6 | 1021 | |
dbd440d8 | 1022 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { |
0d9ef19b | 1023 | child = &devdata->child; |
0ebdabe6 | 1024 | |
6cc38aca JN |
1025 | if (child->slave_addr != SLAVE_ADDR1 && |
1026 | child->slave_addr != SLAVE_ADDR2) { | |
9b9d172d | 1027 | /* |
1028 | * If the slave address is neither 0x70 nor 0x72, | |
1029 | * it is not a SDVO device. Skip it. | |
1030 | */ | |
1031 | continue; | |
1032 | } | |
6cc38aca JN |
1033 | if (child->dvo_port != DEVICE_PORT_DVOB && |
1034 | child->dvo_port != DEVICE_PORT_DVOC) { | |
9b9d172d | 1035 | /* skip the incorrect SDVO port */ |
dbd440d8 | 1036 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1037 | "Incorrect SDVO port. Skip it\n"); |
9b9d172d | 1038 | continue; |
1039 | } | |
dbd440d8 | 1040 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1041 | "the SDVO device with slave addr %2x is found on" |
1042 | " %s port\n", | |
1043 | child->slave_addr, | |
1044 | (child->dvo_port == DEVICE_PORT_DVOB) ? | |
1045 | "SDVOB" : "SDVOC"); | |
dbd440d8 | 1046 | mapping = &i915->vbt.sdvo_mappings[child->dvo_port - 1]; |
e192839e JN |
1047 | if (!mapping->initialized) { |
1048 | mapping->dvo_port = child->dvo_port; | |
1049 | mapping->slave_addr = child->slave_addr; | |
1050 | mapping->dvo_wiring = child->dvo_wiring; | |
1051 | mapping->ddc_pin = child->ddc_pin; | |
1052 | mapping->i2c_pin = child->i2c_pin; | |
1053 | mapping->initialized = 1; | |
dbd440d8 | 1054 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1055 | "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", |
1056 | mapping->dvo_port, mapping->slave_addr, | |
1057 | mapping->dvo_wiring, mapping->ddc_pin, | |
1058 | mapping->i2c_pin); | |
9b9d172d | 1059 | } else { |
dbd440d8 | 1060 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1061 | "Maybe one SDVO port is shared by " |
1062 | "two SDVO device.\n"); | |
9b9d172d | 1063 | } |
6cc38aca | 1064 | if (child->slave2_addr) { |
9b9d172d | 1065 | /* Maybe this is a SDVO device with multiple inputs */ |
1066 | /* And the mapping info is not added */ | |
dbd440d8 | 1067 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1068 | "there exists the slave2_addr. Maybe this" |
1069 | " is a SDVO device with multiple inputs.\n"); | |
9b9d172d | 1070 | } |
1071 | count++; | |
1072 | } | |
1073 | ||
1074 | if (!count) { | |
1075 | /* No SDVO device info is found */ | |
dbd440d8 | 1076 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1077 | "No SDVO device info is found in VBT\n"); |
9b9d172d | 1078 | } |
9b9d172d | 1079 | } |
32f9d658 ZW |
1080 | |
1081 | static void | |
e163cfb4 | 1082 | parse_driver_features(struct drm_i915_private *i915) |
32f9d658 | 1083 | { |
e8ef3b4c | 1084 | const struct bdb_driver_features *driver; |
32f9d658 | 1085 | |
e163cfb4 | 1086 | driver = find_section(i915, BDB_DRIVER_FEATURES); |
652c393a JB |
1087 | if (!driver) |
1088 | return; | |
1089 | ||
005e9537 | 1090 | if (DISPLAY_VER(i915) >= 5) { |
ca3b3fa3 VS |
1091 | /* |
1092 | * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS | |
1093 | * to mean "eDP". The VBT spec doesn't agree with that | |
1094 | * interpretation, but real world VBTs seem to. | |
1095 | */ | |
1096 | if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) | |
dbd440d8 | 1097 | i915->vbt.int_lvds_support = 0; |
ca3b3fa3 VS |
1098 | } else { |
1099 | /* | |
1100 | * FIXME it's not clear which BDB version has the LVDS config | |
1101 | * bits defined. Revision history in the VBT spec says: | |
1102 | * "0.92 | Add two definitions for VBT value of LVDS Active | |
1103 | * Config (00b and 11b values defined) | 06/13/2005" | |
1104 | * but does not the specify the BDB version. | |
1105 | * | |
1106 | * So far version 134 (on i945gm) is the oldest VBT observed | |
1107 | * in the wild with the bits correctly populated. Version | |
1108 | * 108 (on i85x) does not have the bits correctly populated. | |
1109 | */ | |
d58a3d69 | 1110 | if (i915->vbt.version >= 134 && |
ca3b3fa3 VS |
1111 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && |
1112 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) | |
dbd440d8 | 1113 | i915->vbt.int_lvds_support = 0; |
ca3b3fa3 | 1114 | } |
652c393a | 1115 | |
d58a3d69 | 1116 | if (i915->vbt.version < 228) { |
dbd440d8 | 1117 | drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n", |
e92cbf38 | 1118 | driver->drrs_enabled); |
551fb93d JRS |
1119 | /* |
1120 | * If DRRS is not supported, drrs_type has to be set to 0. | |
1121 | * This is because, VBT is configured in such a way that | |
1122 | * static DRRS is 0 and DRRS not supported is represented by | |
1123 | * driver->drrs_enabled=false | |
1124 | */ | |
1125 | if (!driver->drrs_enabled) | |
8e9c9848 | 1126 | i915->vbt.drrs_type = DRRS_TYPE_NONE; |
551fb93d | 1127 | |
dbd440d8 | 1128 | i915->vbt.psr.enable = driver->psr_enabled; |
551fb93d JRS |
1129 | } |
1130 | } | |
1131 | ||
1132 | static void | |
e163cfb4 | 1133 | parse_power_conservation_features(struct drm_i915_private *i915) |
551fb93d JRS |
1134 | { |
1135 | const struct bdb_lfp_power *power; | |
dbd440d8 | 1136 | u8 panel_type = i915->vbt.panel_type; |
551fb93d | 1137 | |
d58a3d69 | 1138 | if (i915->vbt.version < 228) |
551fb93d JRS |
1139 | return; |
1140 | ||
e163cfb4 | 1141 | power = find_section(i915, BDB_LFP_POWER); |
551fb93d JRS |
1142 | if (!power) |
1143 | return; | |
1144 | ||
dbd440d8 | 1145 | i915->vbt.psr.enable = power->psr & BIT(panel_type); |
551fb93d | 1146 | |
83a7280e PB |
1147 | /* |
1148 | * If DRRS is not supported, drrs_type has to be set to 0. | |
1149 | * This is because, VBT is configured in such a way that | |
1150 | * static DRRS is 0 and DRRS not supported is represented by | |
551fb93d | 1151 | * power->drrs & BIT(panel_type)=false |
83a7280e | 1152 | */ |
551fb93d | 1153 | if (!(power->drrs & BIT(panel_type))) |
8e9c9848 | 1154 | i915->vbt.drrs_type = DRRS_TYPE_NONE; |
f615cb6a | 1155 | |
d58a3d69 | 1156 | if (i915->vbt.version >= 232) |
dbd440d8 | 1157 | i915->vbt.edp.hobl = power->hobl & BIT(panel_type); |
32f9d658 ZW |
1158 | } |
1159 | ||
500a8cc4 | 1160 | static void |
e163cfb4 | 1161 | parse_edp(struct drm_i915_private *i915) |
500a8cc4 | 1162 | { |
e8ef3b4c JN |
1163 | const struct bdb_edp *edp; |
1164 | const struct edp_power_seq *edp_pps; | |
058727ee | 1165 | const struct edp_fast_link_params *edp_link_params; |
dbd440d8 | 1166 | int panel_type = i915->vbt.panel_type; |
500a8cc4 | 1167 | |
e163cfb4 | 1168 | edp = find_section(i915, BDB_EDP); |
5255e2f8 | 1169 | if (!edp) |
500a8cc4 | 1170 | return; |
500a8cc4 ZW |
1171 | |
1172 | switch ((edp->color_depth >> (panel_type * 2)) & 3) { | |
1173 | case EDP_18BPP: | |
dbd440d8 | 1174 | i915->vbt.edp.bpp = 18; |
500a8cc4 ZW |
1175 | break; |
1176 | case EDP_24BPP: | |
dbd440d8 | 1177 | i915->vbt.edp.bpp = 24; |
500a8cc4 ZW |
1178 | break; |
1179 | case EDP_30BPP: | |
dbd440d8 | 1180 | i915->vbt.edp.bpp = 30; |
500a8cc4 ZW |
1181 | break; |
1182 | } | |
5ceb0f9b | 1183 | |
9f0e7ff4 JB |
1184 | /* Get the eDP sequencing and link info */ |
1185 | edp_pps = &edp->power_seqs[panel_type]; | |
058727ee | 1186 | edp_link_params = &edp->fast_link_params[panel_type]; |
5ceb0f9b | 1187 | |
dbd440d8 | 1188 | i915->vbt.edp.pps = *edp_pps; |
5ceb0f9b | 1189 | |
e13e2b2c JN |
1190 | switch (edp_link_params->rate) { |
1191 | case EDP_RATE_1_62: | |
dbd440d8 | 1192 | i915->vbt.edp.rate = DP_LINK_BW_1_62; |
e13e2b2c JN |
1193 | break; |
1194 | case EDP_RATE_2_7: | |
dbd440d8 | 1195 | i915->vbt.edp.rate = DP_LINK_BW_2_7; |
e13e2b2c JN |
1196 | break; |
1197 | default: | |
dbd440d8 | 1198 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1199 | "VBT has unknown eDP link rate value %u\n", |
1200 | edp_link_params->rate); | |
e13e2b2c JN |
1201 | break; |
1202 | } | |
1203 | ||
9f0e7ff4 | 1204 | switch (edp_link_params->lanes) { |
e13e2b2c | 1205 | case EDP_LANE_1: |
dbd440d8 | 1206 | i915->vbt.edp.lanes = 1; |
9f0e7ff4 | 1207 | break; |
e13e2b2c | 1208 | case EDP_LANE_2: |
dbd440d8 | 1209 | i915->vbt.edp.lanes = 2; |
9f0e7ff4 | 1210 | break; |
e13e2b2c | 1211 | case EDP_LANE_4: |
dbd440d8 | 1212 | i915->vbt.edp.lanes = 4; |
9f0e7ff4 | 1213 | break; |
e13e2b2c | 1214 | default: |
dbd440d8 | 1215 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1216 | "VBT has unknown eDP lane count value %u\n", |
1217 | edp_link_params->lanes); | |
e13e2b2c | 1218 | break; |
9f0e7ff4 | 1219 | } |
e13e2b2c | 1220 | |
9f0e7ff4 | 1221 | switch (edp_link_params->preemphasis) { |
e13e2b2c | 1222 | case EDP_PREEMPHASIS_NONE: |
dbd440d8 | 1223 | i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; |
9f0e7ff4 | 1224 | break; |
e13e2b2c | 1225 | case EDP_PREEMPHASIS_3_5dB: |
dbd440d8 | 1226 | i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; |
9f0e7ff4 | 1227 | break; |
e13e2b2c | 1228 | case EDP_PREEMPHASIS_6dB: |
dbd440d8 | 1229 | i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; |
9f0e7ff4 | 1230 | break; |
e13e2b2c | 1231 | case EDP_PREEMPHASIS_9_5dB: |
dbd440d8 | 1232 | i915->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; |
9f0e7ff4 | 1233 | break; |
e13e2b2c | 1234 | default: |
dbd440d8 | 1235 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1236 | "VBT has unknown eDP pre-emphasis value %u\n", |
1237 | edp_link_params->preemphasis); | |
e13e2b2c | 1238 | break; |
9f0e7ff4 | 1239 | } |
e13e2b2c | 1240 | |
9f0e7ff4 | 1241 | switch (edp_link_params->vswing) { |
e13e2b2c | 1242 | case EDP_VSWING_0_4V: |
dbd440d8 | 1243 | i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
9f0e7ff4 | 1244 | break; |
e13e2b2c | 1245 | case EDP_VSWING_0_6V: |
dbd440d8 | 1246 | i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; |
9f0e7ff4 | 1247 | break; |
e13e2b2c | 1248 | case EDP_VSWING_0_8V: |
dbd440d8 | 1249 | i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
9f0e7ff4 | 1250 | break; |
e13e2b2c | 1251 | case EDP_VSWING_1_2V: |
dbd440d8 | 1252 | i915->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
9f0e7ff4 | 1253 | break; |
e13e2b2c | 1254 | default: |
dbd440d8 | 1255 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1256 | "VBT has unknown eDP voltage swing value %u\n", |
1257 | edp_link_params->vswing); | |
e13e2b2c | 1258 | break; |
9f0e7ff4 | 1259 | } |
9a57f5bb | 1260 | |
d58a3d69 | 1261 | if (i915->vbt.version >= 173) { |
0ede0141 | 1262 | u8 vswing; |
9a57f5bb | 1263 | |
9e458034 | 1264 | /* Don't read from VBT if module parameter has valid value*/ |
dbd440d8 JN |
1265 | if (i915->params.edp_vswing) { |
1266 | i915->vbt.edp.low_vswing = | |
1267 | i915->params.edp_vswing == 1; | |
9e458034 SJ |
1268 | } else { |
1269 | vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; | |
dbd440d8 | 1270 | i915->vbt.edp.low_vswing = vswing == 0; |
9e458034 | 1271 | } |
9a57f5bb | 1272 | } |
b395c29a VS |
1273 | |
1274 | i915->vbt.edp.drrs_msa_timing_delay = | |
1275 | (edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3; | |
500a8cc4 ZW |
1276 | } |
1277 | ||
bfd7ebda | 1278 | static void |
e163cfb4 | 1279 | parse_psr(struct drm_i915_private *i915) |
bfd7ebda | 1280 | { |
e8ef3b4c JN |
1281 | const struct bdb_psr *psr; |
1282 | const struct psr_table *psr_table; | |
dbd440d8 | 1283 | int panel_type = i915->vbt.panel_type; |
bfd7ebda | 1284 | |
e163cfb4 | 1285 | psr = find_section(i915, BDB_PSR); |
bfd7ebda | 1286 | if (!psr) { |
dbd440d8 | 1287 | drm_dbg_kms(&i915->drm, "No PSR BDB found.\n"); |
bfd7ebda RV |
1288 | return; |
1289 | } | |
1290 | ||
1291 | psr_table = &psr->psr_table[panel_type]; | |
1292 | ||
dbd440d8 JN |
1293 | i915->vbt.psr.full_link = psr_table->full_link; |
1294 | i915->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; | |
bfd7ebda RV |
1295 | |
1296 | /* Allowed VBT values goes from 0 to 15 */ | |
dbd440d8 | 1297 | i915->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : |
bfd7ebda RV |
1298 | psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; |
1299 | ||
77312ae8 VN |
1300 | /* |
1301 | * New psr options 0=500us, 1=100us, 2=2500us, 3=0us | |
1302 | * Old decimal value is wake up time in multiples of 100 us. | |
1303 | */ | |
d58a3d69 | 1304 | if (i915->vbt.version >= 205 && |
2446e1d6 | 1305 | (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) { |
77312ae8 VN |
1306 | switch (psr_table->tp1_wakeup_time) { |
1307 | case 0: | |
dbd440d8 | 1308 | i915->vbt.psr.tp1_wakeup_time_us = 500; |
77312ae8 VN |
1309 | break; |
1310 | case 1: | |
dbd440d8 | 1311 | i915->vbt.psr.tp1_wakeup_time_us = 100; |
77312ae8 VN |
1312 | break; |
1313 | case 3: | |
dbd440d8 | 1314 | i915->vbt.psr.tp1_wakeup_time_us = 0; |
77312ae8 VN |
1315 | break; |
1316 | default: | |
dbd440d8 | 1317 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1318 | "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", |
1319 | psr_table->tp1_wakeup_time); | |
df561f66 | 1320 | fallthrough; |
77312ae8 | 1321 | case 2: |
dbd440d8 | 1322 | i915->vbt.psr.tp1_wakeup_time_us = 2500; |
77312ae8 VN |
1323 | break; |
1324 | } | |
1325 | ||
1326 | switch (psr_table->tp2_tp3_wakeup_time) { | |
1327 | case 0: | |
dbd440d8 | 1328 | i915->vbt.psr.tp2_tp3_wakeup_time_us = 500; |
77312ae8 VN |
1329 | break; |
1330 | case 1: | |
dbd440d8 | 1331 | i915->vbt.psr.tp2_tp3_wakeup_time_us = 100; |
77312ae8 VN |
1332 | break; |
1333 | case 3: | |
dbd440d8 | 1334 | i915->vbt.psr.tp2_tp3_wakeup_time_us = 0; |
77312ae8 VN |
1335 | break; |
1336 | default: | |
dbd440d8 | 1337 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1338 | "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", |
1339 | psr_table->tp2_tp3_wakeup_time); | |
df561f66 | 1340 | fallthrough; |
77312ae8 | 1341 | case 2: |
dbd440d8 | 1342 | i915->vbt.psr.tp2_tp3_wakeup_time_us = 2500; |
77312ae8 VN |
1343 | break; |
1344 | } | |
1345 | } else { | |
dbd440d8 JN |
1346 | i915->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; |
1347 | i915->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; | |
77312ae8 | 1348 | } |
88a0d960 | 1349 | |
d58a3d69 | 1350 | if (i915->vbt.version >= 226) { |
b5ea9c93 | 1351 | u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; |
88a0d960 JRS |
1352 | |
1353 | wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; | |
1354 | switch (wakeup_time) { | |
1355 | case 0: | |
1356 | wakeup_time = 500; | |
1357 | break; | |
1358 | case 1: | |
1359 | wakeup_time = 100; | |
1360 | break; | |
1361 | case 3: | |
1362 | wakeup_time = 50; | |
1363 | break; | |
1364 | default: | |
1365 | case 2: | |
1366 | wakeup_time = 2500; | |
1367 | break; | |
1368 | } | |
dbd440d8 | 1369 | i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time; |
88a0d960 JRS |
1370 | } else { |
1371 | /* Reusing PSR1 wakeup time for PSR2 in older VBTs */ | |
dbd440d8 | 1372 | i915->vbt.psr.psr2_tp2_tp3_wakeup_time_us = i915->vbt.psr.tp2_tp3_wakeup_time_us; |
88a0d960 | 1373 | } |
bfd7ebda RV |
1374 | } |
1375 | ||
dbd440d8 | 1376 | static void parse_dsi_backlight_ports(struct drm_i915_private *i915, |
46e58320 MC |
1377 | u16 version, enum port port) |
1378 | { | |
dbd440d8 JN |
1379 | if (!i915->vbt.dsi.config->dual_link || version < 197) { |
1380 | i915->vbt.dsi.bl_ports = BIT(port); | |
1381 | if (i915->vbt.dsi.config->cabc_supported) | |
1382 | i915->vbt.dsi.cabc_ports = BIT(port); | |
46e58320 | 1383 | |
46e58320 MC |
1384 | return; |
1385 | } | |
1386 | ||
dbd440d8 | 1387 | switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) { |
46e58320 | 1388 | case DL_DCS_PORT_A: |
dbd440d8 | 1389 | i915->vbt.dsi.bl_ports = BIT(PORT_A); |
46e58320 MC |
1390 | break; |
1391 | case DL_DCS_PORT_C: | |
dbd440d8 | 1392 | i915->vbt.dsi.bl_ports = BIT(PORT_C); |
46e58320 MC |
1393 | break; |
1394 | default: | |
1395 | case DL_DCS_PORT_A_AND_C: | |
dbd440d8 | 1396 | i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); |
46e58320 MC |
1397 | break; |
1398 | } | |
1399 | ||
dbd440d8 | 1400 | if (!i915->vbt.dsi.config->cabc_supported) |
46e58320 MC |
1401 | return; |
1402 | ||
dbd440d8 | 1403 | switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) { |
46e58320 | 1404 | case DL_DCS_PORT_A: |
dbd440d8 | 1405 | i915->vbt.dsi.cabc_ports = BIT(PORT_A); |
46e58320 MC |
1406 | break; |
1407 | case DL_DCS_PORT_C: | |
dbd440d8 | 1408 | i915->vbt.dsi.cabc_ports = BIT(PORT_C); |
46e58320 MC |
1409 | break; |
1410 | default: | |
1411 | case DL_DCS_PORT_A_AND_C: | |
dbd440d8 | 1412 | i915->vbt.dsi.cabc_ports = |
46e58320 MC |
1413 | BIT(PORT_A) | BIT(PORT_C); |
1414 | break; | |
1415 | } | |
1416 | } | |
1417 | ||
d17c5443 | 1418 | static void |
e163cfb4 | 1419 | parse_mipi_config(struct drm_i915_private *i915) |
d17c5443 | 1420 | { |
e8ef3b4c | 1421 | const struct bdb_mipi_config *start; |
e8ef3b4c JN |
1422 | const struct mipi_config *config; |
1423 | const struct mipi_pps_data *pps; | |
dbd440d8 | 1424 | int panel_type = i915->vbt.panel_type; |
46e58320 | 1425 | enum port port; |
d3b542fc | 1426 | |
3e6bd011 | 1427 | /* parse MIPI blocks only if LFP type is MIPI */ |
dbd440d8 | 1428 | if (!intel_bios_is_dsi_present(i915, &port)) |
3e6bd011 SK |
1429 | return; |
1430 | ||
d3b542fc | 1431 | /* Initialize this to undefined indicating no generic MIPI support */ |
dbd440d8 | 1432 | i915->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; |
d3b542fc SK |
1433 | |
1434 | /* Block #40 is already parsed and panel_fixed_mode is | |
dbd440d8 | 1435 | * stored in i915->lfp_lvds_vbt_mode |
d3b542fc SK |
1436 | * resuse this when needed |
1437 | */ | |
d17c5443 | 1438 | |
d3b542fc SK |
1439 | /* Parse #52 for panel index used from panel_type already |
1440 | * parsed | |
1441 | */ | |
e163cfb4 | 1442 | start = find_section(i915, BDB_MIPI_CONFIG); |
d3b542fc | 1443 | if (!start) { |
dbd440d8 | 1444 | drm_dbg_kms(&i915->drm, "No MIPI config BDB found"); |
d17c5443 SK |
1445 | return; |
1446 | } | |
1447 | ||
dbd440d8 | 1448 | drm_dbg(&i915->drm, "Found MIPI Config block, panel index = %d\n", |
e92cbf38 | 1449 | panel_type); |
d3b542fc SK |
1450 | |
1451 | /* | |
1452 | * get hold of the correct configuration block and pps data as per | |
1453 | * the panel_type as index | |
1454 | */ | |
1455 | config = &start->config[panel_type]; | |
1456 | pps = &start->pps[panel_type]; | |
1457 | ||
1458 | /* store as of now full data. Trim when we realise all is not needed */ | |
dbd440d8 JN |
1459 | i915->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); |
1460 | if (!i915->vbt.dsi.config) | |
d3b542fc SK |
1461 | return; |
1462 | ||
dbd440d8 JN |
1463 | i915->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); |
1464 | if (!i915->vbt.dsi.pps) { | |
1465 | kfree(i915->vbt.dsi.config); | |
d3b542fc SK |
1466 | return; |
1467 | } | |
1468 | ||
d58a3d69 | 1469 | parse_dsi_backlight_ports(i915, i915->vbt.version, port); |
9f7c5b17 | 1470 | |
c1cd5b24 VS |
1471 | /* FIXME is the 90 vs. 270 correct? */ |
1472 | switch (config->rotation) { | |
1473 | case ENABLE_ROTATION_0: | |
1474 | /* | |
1475 | * Most (all?) VBTs claim 0 degrees despite having | |
1476 | * an upside down panel, thus we do not trust this. | |
1477 | */ | |
dbd440d8 | 1478 | i915->vbt.dsi.orientation = |
c1cd5b24 VS |
1479 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN; |
1480 | break; | |
1481 | case ENABLE_ROTATION_90: | |
dbd440d8 | 1482 | i915->vbt.dsi.orientation = |
c1cd5b24 VS |
1483 | DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; |
1484 | break; | |
1485 | case ENABLE_ROTATION_180: | |
dbd440d8 | 1486 | i915->vbt.dsi.orientation = |
c1cd5b24 VS |
1487 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; |
1488 | break; | |
1489 | case ENABLE_ROTATION_270: | |
dbd440d8 | 1490 | i915->vbt.dsi.orientation = |
c1cd5b24 VS |
1491 | DRM_MODE_PANEL_ORIENTATION_LEFT_UP; |
1492 | break; | |
1493 | } | |
1494 | ||
d3b542fc | 1495 | /* We have mandatory mipi config blocks. Initialize as generic panel */ |
dbd440d8 | 1496 | i915->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; |
0f8689f5 JN |
1497 | } |
1498 | ||
5db72099 JN |
1499 | /* Find the sequence block and size for the given panel. */ |
1500 | static const u8 * | |
1501 | find_panel_sequence_block(const struct bdb_mipi_sequence *sequence, | |
2a33d934 | 1502 | u16 panel_id, u32 *seq_size) |
5db72099 JN |
1503 | { |
1504 | u32 total = get_blocksize(sequence); | |
1505 | const u8 *data = &sequence->data[0]; | |
1506 | u8 current_id; | |
2a33d934 JN |
1507 | u32 current_size; |
1508 | int header_size = sequence->version >= 3 ? 5 : 3; | |
5db72099 JN |
1509 | int index = 0; |
1510 | int i; | |
1511 | ||
2a33d934 JN |
1512 | /* skip new block size */ |
1513 | if (sequence->version >= 3) | |
1514 | data += 4; | |
1515 | ||
1516 | for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { | |
1517 | if (index + header_size > total) { | |
1518 | DRM_ERROR("Invalid sequence block (header)\n"); | |
1519 | return NULL; | |
1520 | } | |
1521 | ||
5db72099 | 1522 | current_id = *(data + index); |
2a33d934 JN |
1523 | if (sequence->version >= 3) |
1524 | current_size = *((const u32 *)(data + index + 1)); | |
1525 | else | |
1526 | current_size = *((const u16 *)(data + index + 1)); | |
5db72099 | 1527 | |
2a33d934 | 1528 | index += header_size; |
5db72099 JN |
1529 | |
1530 | if (index + current_size > total) { | |
1531 | DRM_ERROR("Invalid sequence block\n"); | |
1532 | return NULL; | |
1533 | } | |
1534 | ||
1535 | if (current_id == panel_id) { | |
1536 | *seq_size = current_size; | |
1537 | return data + index; | |
1538 | } | |
1539 | ||
1540 | index += current_size; | |
1541 | } | |
1542 | ||
1543 | DRM_ERROR("Sequence block detected but no valid configuration\n"); | |
1544 | ||
1545 | return NULL; | |
1546 | } | |
1547 | ||
8d3ed2f3 JN |
1548 | static int goto_next_sequence(const u8 *data, int index, int total) |
1549 | { | |
1550 | u16 len; | |
1551 | ||
1552 | /* Skip Sequence Byte. */ | |
1553 | for (index = index + 1; index < total; index += len) { | |
1554 | u8 operation_byte = *(data + index); | |
1555 | index++; | |
1556 | ||
1557 | switch (operation_byte) { | |
1558 | case MIPI_SEQ_ELEM_END: | |
1559 | return index; | |
1560 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1561 | if (index + 4 > total) | |
1562 | return 0; | |
1563 | ||
1564 | len = *((const u16 *)(data + index + 2)) + 4; | |
1565 | break; | |
1566 | case MIPI_SEQ_ELEM_DELAY: | |
1567 | len = 4; | |
1568 | break; | |
1569 | case MIPI_SEQ_ELEM_GPIO: | |
1570 | len = 2; | |
1571 | break; | |
f4d64936 JN |
1572 | case MIPI_SEQ_ELEM_I2C: |
1573 | if (index + 7 > total) | |
1574 | return 0; | |
1575 | len = *(data + index + 6) + 7; | |
1576 | break; | |
8d3ed2f3 JN |
1577 | default: |
1578 | DRM_ERROR("Unknown operation byte\n"); | |
1579 | return 0; | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
2a33d934 JN |
1586 | static int goto_next_sequence_v3(const u8 *data, int index, int total) |
1587 | { | |
1588 | int seq_end; | |
1589 | u16 len; | |
6765bd6d | 1590 | u32 size_of_sequence; |
2a33d934 JN |
1591 | |
1592 | /* | |
1593 | * Could skip sequence based on Size of Sequence alone, but also do some | |
1594 | * checking on the structure. | |
1595 | */ | |
1596 | if (total < 5) { | |
1597 | DRM_ERROR("Too small sequence size\n"); | |
1598 | return 0; | |
1599 | } | |
1600 | ||
6765bd6d JN |
1601 | /* Skip Sequence Byte. */ |
1602 | index++; | |
1603 | ||
1604 | /* | |
1605 | * Size of Sequence. Excludes the Sequence Byte and the size itself, | |
1606 | * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END | |
1607 | * byte. | |
1608 | */ | |
0ede0141 | 1609 | size_of_sequence = *((const u32 *)(data + index)); |
6765bd6d JN |
1610 | index += 4; |
1611 | ||
1612 | seq_end = index + size_of_sequence; | |
2a33d934 JN |
1613 | if (seq_end > total) { |
1614 | DRM_ERROR("Invalid sequence size\n"); | |
1615 | return 0; | |
1616 | } | |
1617 | ||
6765bd6d | 1618 | for (; index < total; index += len) { |
2a33d934 JN |
1619 | u8 operation_byte = *(data + index); |
1620 | index++; | |
1621 | ||
1622 | if (operation_byte == MIPI_SEQ_ELEM_END) { | |
1623 | if (index != seq_end) { | |
1624 | DRM_ERROR("Invalid element structure\n"); | |
1625 | return 0; | |
1626 | } | |
1627 | return index; | |
1628 | } | |
1629 | ||
1630 | len = *(data + index); | |
1631 | index++; | |
1632 | ||
1633 | /* | |
1634 | * FIXME: Would be nice to check elements like for v1/v2 in | |
1635 | * goto_next_sequence() above. | |
1636 | */ | |
1637 | switch (operation_byte) { | |
1638 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1639 | case MIPI_SEQ_ELEM_DELAY: | |
1640 | case MIPI_SEQ_ELEM_GPIO: | |
1641 | case MIPI_SEQ_ELEM_I2C: | |
1642 | case MIPI_SEQ_ELEM_SPI: | |
1643 | case MIPI_SEQ_ELEM_PMIC: | |
1644 | break; | |
1645 | default: | |
1646 | DRM_ERROR("Unknown operation byte %u\n", | |
1647 | operation_byte); | |
1648 | break; | |
1649 | } | |
1650 | } | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
fb38e7ad HG |
1655 | /* |
1656 | * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, | |
1657 | * skip all delay + gpio operands and stop at the first DSI packet op. | |
1658 | */ | |
dbd440d8 | 1659 | static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915) |
fb38e7ad | 1660 | { |
dbd440d8 | 1661 | const u8 *data = i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; |
fb38e7ad HG |
1662 | int index, len; |
1663 | ||
dbd440d8 JN |
1664 | if (drm_WARN_ON(&i915->drm, |
1665 | !data || i915->vbt.dsi.seq_version != 1)) | |
fb38e7ad HG |
1666 | return 0; |
1667 | ||
1668 | /* index = 1 to skip sequence byte */ | |
1669 | for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { | |
1670 | switch (data[index]) { | |
1671 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1672 | return index == 1 ? 0 : index; | |
1673 | case MIPI_SEQ_ELEM_DELAY: | |
1674 | len = 5; /* 1 byte for operand + uint32 */ | |
1675 | break; | |
1676 | case MIPI_SEQ_ELEM_GPIO: | |
1677 | len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ | |
1678 | break; | |
1679 | default: | |
1680 | return 0; | |
1681 | } | |
1682 | } | |
1683 | ||
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | /* | |
1688 | * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. | |
1689 | * The deassert must be done before calling intel_dsi_device_ready, so for | |
1690 | * these devices we split the init OTP sequence into a deassert sequence and | |
1691 | * the actual init OTP part. | |
1692 | */ | |
dbd440d8 | 1693 | static void fixup_mipi_sequences(struct drm_i915_private *i915) |
fb38e7ad HG |
1694 | { |
1695 | u8 *init_otp; | |
1696 | int len; | |
1697 | ||
1698 | /* Limit this to VLV for now. */ | |
dbd440d8 | 1699 | if (!IS_VALLEYVIEW(i915)) |
fb38e7ad HG |
1700 | return; |
1701 | ||
1702 | /* Limit this to v1 vid-mode sequences */ | |
dbd440d8 JN |
1703 | if (i915->vbt.dsi.config->is_cmd_mode || |
1704 | i915->vbt.dsi.seq_version != 1) | |
fb38e7ad HG |
1705 | return; |
1706 | ||
1707 | /* Only do this if there are otp and assert seqs and no deassert seq */ | |
dbd440d8 JN |
1708 | if (!i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || |
1709 | !i915->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || | |
1710 | i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) | |
fb38e7ad HG |
1711 | return; |
1712 | ||
1713 | /* The deassert-sequence ends at the first DSI packet */ | |
dbd440d8 | 1714 | len = get_init_otp_deassert_fragment_len(i915); |
fb38e7ad HG |
1715 | if (!len) |
1716 | return; | |
1717 | ||
dbd440d8 | 1718 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1719 | "Using init OTP fragment to deassert reset\n"); |
fb38e7ad HG |
1720 | |
1721 | /* Copy the fragment, update seq byte and terminate it */ | |
dbd440d8 JN |
1722 | init_otp = (u8 *)i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; |
1723 | i915->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); | |
1724 | if (!i915->vbt.dsi.deassert_seq) | |
fb38e7ad | 1725 | return; |
dbd440d8 JN |
1726 | i915->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; |
1727 | i915->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; | |
fb38e7ad | 1728 | /* Use the copy for deassert */ |
dbd440d8 JN |
1729 | i915->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = |
1730 | i915->vbt.dsi.deassert_seq; | |
fb38e7ad HG |
1731 | /* Replace the last byte of the fragment with init OTP seq byte */ |
1732 | init_otp[len - 1] = MIPI_SEQ_INIT_OTP; | |
1733 | /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ | |
dbd440d8 | 1734 | i915->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; |
fb38e7ad HG |
1735 | } |
1736 | ||
0f8689f5 | 1737 | static void |
e163cfb4 | 1738 | parse_mipi_sequence(struct drm_i915_private *i915) |
0f8689f5 | 1739 | { |
dbd440d8 | 1740 | int panel_type = i915->vbt.panel_type; |
0f8689f5 JN |
1741 | const struct bdb_mipi_sequence *sequence; |
1742 | const u8 *seq_data; | |
2a33d934 | 1743 | u32 seq_size; |
0f8689f5 | 1744 | u8 *data; |
8d3ed2f3 | 1745 | int index = 0; |
0f8689f5 JN |
1746 | |
1747 | /* Only our generic panel driver uses the sequence block. */ | |
dbd440d8 | 1748 | if (i915->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) |
0f8689f5 | 1749 | return; |
d3b542fc | 1750 | |
e163cfb4 | 1751 | sequence = find_section(i915, BDB_MIPI_SEQUENCE); |
d3b542fc | 1752 | if (!sequence) { |
dbd440d8 | 1753 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1754 | "No MIPI Sequence found, parsing complete\n"); |
d3b542fc SK |
1755 | return; |
1756 | } | |
1757 | ||
cd67d226 | 1758 | /* Fail gracefully for forward incompatible sequence block. */ |
2a33d934 | 1759 | if (sequence->version >= 4) { |
dbd440d8 | 1760 | drm_err(&i915->drm, |
e92cbf38 WK |
1761 | "Unable to parse MIPI Sequence Block v%u\n", |
1762 | sequence->version); | |
cd67d226 JN |
1763 | return; |
1764 | } | |
1765 | ||
dbd440d8 | 1766 | drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n", |
e92cbf38 | 1767 | sequence->version); |
d3b542fc | 1768 | |
5db72099 JN |
1769 | seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size); |
1770 | if (!seq_data) | |
d3b542fc | 1771 | return; |
d3b542fc | 1772 | |
8d3ed2f3 JN |
1773 | data = kmemdup(seq_data, seq_size, GFP_KERNEL); |
1774 | if (!data) | |
d3b542fc SK |
1775 | return; |
1776 | ||
8d3ed2f3 JN |
1777 | /* Parse the sequences, store pointers to each sequence. */ |
1778 | for (;;) { | |
1779 | u8 seq_id = *(data + index); | |
1780 | if (seq_id == MIPI_SEQ_END) | |
1781 | break; | |
d3b542fc | 1782 | |
8d3ed2f3 | 1783 | if (seq_id >= MIPI_SEQ_MAX) { |
dbd440d8 | 1784 | drm_err(&i915->drm, "Unknown sequence %u\n", |
e92cbf38 | 1785 | seq_id); |
d3b542fc SK |
1786 | goto err; |
1787 | } | |
1788 | ||
4b4f497e JN |
1789 | /* Log about presence of sequences we won't run. */ |
1790 | if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) | |
dbd440d8 | 1791 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1792 | "Unsupported sequence %u\n", seq_id); |
4b4f497e | 1793 | |
dbd440d8 | 1794 | i915->vbt.dsi.sequence[seq_id] = data + index; |
d3b542fc | 1795 | |
2a33d934 JN |
1796 | if (sequence->version >= 3) |
1797 | index = goto_next_sequence_v3(data, index, seq_size); | |
1798 | else | |
1799 | index = goto_next_sequence(data, index, seq_size); | |
8d3ed2f3 | 1800 | if (!index) { |
dbd440d8 | 1801 | drm_err(&i915->drm, "Invalid sequence %u\n", |
e92cbf38 | 1802 | seq_id); |
d3b542fc SK |
1803 | goto err; |
1804 | } | |
d3b542fc SK |
1805 | } |
1806 | ||
dbd440d8 JN |
1807 | i915->vbt.dsi.data = data; |
1808 | i915->vbt.dsi.size = seq_size; | |
1809 | i915->vbt.dsi.seq_version = sequence->version; | |
8d3ed2f3 | 1810 | |
dbd440d8 | 1811 | fixup_mipi_sequences(i915); |
fb38e7ad | 1812 | |
dbd440d8 | 1813 | drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n"); |
d3b542fc | 1814 | return; |
d3b542fc | 1815 | |
8d3ed2f3 JN |
1816 | err: |
1817 | kfree(data); | |
dbd440d8 | 1818 | memset(i915->vbt.dsi.sequence, 0, sizeof(i915->vbt.dsi.sequence)); |
d17c5443 SK |
1819 | } |
1820 | ||
6e0d46e9 | 1821 | static void |
e163cfb4 | 1822 | parse_compression_parameters(struct drm_i915_private *i915) |
6e0d46e9 JN |
1823 | { |
1824 | const struct bdb_compression_parameters *params; | |
3162d057 | 1825 | struct intel_bios_encoder_data *devdata; |
6e0d46e9 JN |
1826 | const struct child_device_config *child; |
1827 | u16 block_size; | |
1828 | int index; | |
1829 | ||
d58a3d69 | 1830 | if (i915->vbt.version < 198) |
6e0d46e9 JN |
1831 | return; |
1832 | ||
e163cfb4 | 1833 | params = find_section(i915, BDB_COMPRESSION_PARAMETERS); |
6e0d46e9 JN |
1834 | if (params) { |
1835 | /* Sanity checks */ | |
1836 | if (params->entry_size != sizeof(params->data[0])) { | |
e92cbf38 WK |
1837 | drm_dbg_kms(&i915->drm, |
1838 | "VBT: unsupported compression param entry size\n"); | |
6e0d46e9 JN |
1839 | return; |
1840 | } | |
1841 | ||
1842 | block_size = get_blocksize(params); | |
1843 | if (block_size < sizeof(*params)) { | |
e92cbf38 WK |
1844 | drm_dbg_kms(&i915->drm, |
1845 | "VBT: expected 16 compression param entries\n"); | |
6e0d46e9 JN |
1846 | return; |
1847 | } | |
1848 | } | |
1849 | ||
1850 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { | |
1851 | child = &devdata->child; | |
1852 | ||
1853 | if (!child->compression_enable) | |
1854 | continue; | |
1855 | ||
1856 | if (!params) { | |
e92cbf38 WK |
1857 | drm_dbg_kms(&i915->drm, |
1858 | "VBT: compression params not available\n"); | |
6e0d46e9 JN |
1859 | continue; |
1860 | } | |
1861 | ||
1862 | if (child->compression_method_cps) { | |
e92cbf38 WK |
1863 | drm_dbg_kms(&i915->drm, |
1864 | "VBT: CPS compression not supported\n"); | |
6e0d46e9 JN |
1865 | continue; |
1866 | } | |
1867 | ||
1868 | index = child->compression_structure_index; | |
1869 | ||
1870 | devdata->dsc = kmemdup(¶ms->data[index], | |
1871 | sizeof(*devdata->dsc), GFP_KERNEL); | |
1872 | } | |
1873 | } | |
1874 | ||
75067dde AK |
1875 | static u8 translate_iboost(u8 val) |
1876 | { | |
1877 | static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ | |
1878 | ||
1879 | if (val >= ARRAY_SIZE(mapping)) { | |
1880 | DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); | |
1881 | return 0; | |
1882 | } | |
1883 | return mapping[val]; | |
1884 | } | |
1885 | ||
9e1dbc1a JN |
1886 | static const u8 cnp_ddc_pin_map[] = { |
1887 | [0] = 0, /* N/A */ | |
1888 | [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT, | |
1889 | [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT, | |
1890 | [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */ | |
1891 | [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ | |
1892 | }; | |
1893 | ||
1894 | static const u8 icp_ddc_pin_map[] = { | |
1895 | [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, | |
1896 | [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, | |
1897 | [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT, | |
1898 | [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, | |
1899 | [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, | |
1900 | [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, | |
1901 | [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, | |
1902 | [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP, | |
1903 | [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, | |
1904 | }; | |
1905 | ||
1906 | static const u8 rkl_pch_tgp_ddc_pin_map[] = { | |
1907 | [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, | |
1908 | [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, | |
1909 | [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP, | |
1910 | [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, | |
1911 | }; | |
1912 | ||
1913 | static const u8 adls_ddc_pin_map[] = { | |
1914 | [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, | |
1915 | [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, | |
1916 | [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, | |
1917 | [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, | |
1918 | [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, | |
1919 | }; | |
1920 | ||
1921 | static const u8 gen9bc_tgp_ddc_pin_map[] = { | |
1922 | [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, | |
1923 | [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP, | |
1924 | [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP, | |
1925 | }; | |
1926 | ||
af10ec31 TU |
1927 | static const u8 adlp_ddc_pin_map[] = { |
1928 | [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, | |
1929 | [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, | |
1930 | [ADLP_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, | |
1931 | [ADLP_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, | |
1932 | [ADLP_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, | |
1933 | [ADLP_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, | |
1934 | }; | |
1935 | ||
9e1dbc1a JN |
1936 | static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) |
1937 | { | |
1938 | const u8 *ddc_pin_map; | |
1939 | int n_entries; | |
1940 | ||
af10ec31 TU |
1941 | if (IS_ALDERLAKE_P(i915)) { |
1942 | ddc_pin_map = adlp_ddc_pin_map; | |
1943 | n_entries = ARRAY_SIZE(adlp_ddc_pin_map); | |
1944 | } else if (IS_ALDERLAKE_S(i915)) { | |
9e1dbc1a JN |
1945 | ddc_pin_map = adls_ddc_pin_map; |
1946 | n_entries = ARRAY_SIZE(adls_ddc_pin_map); | |
1947 | } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { | |
1948 | return vbt_pin; | |
1949 | } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { | |
1950 | ddc_pin_map = rkl_pch_tgp_ddc_pin_map; | |
1951 | n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); | |
1952 | } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) { | |
1953 | ddc_pin_map = gen9bc_tgp_ddc_pin_map; | |
1954 | n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); | |
1955 | } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { | |
1956 | ddc_pin_map = icp_ddc_pin_map; | |
1957 | n_entries = ARRAY_SIZE(icp_ddc_pin_map); | |
1958 | } else if (HAS_PCH_CNP(i915)) { | |
1959 | ddc_pin_map = cnp_ddc_pin_map; | |
1960 | n_entries = ARRAY_SIZE(cnp_ddc_pin_map); | |
1961 | } else { | |
1962 | /* Assuming direct map */ | |
1963 | return vbt_pin; | |
1964 | } | |
1965 | ||
1966 | if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) | |
1967 | return ddc_pin_map[vbt_pin]; | |
1968 | ||
1969 | drm_dbg_kms(&i915->drm, | |
1970 | "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", | |
1971 | vbt_pin); | |
1972 | return 0; | |
1973 | } | |
1974 | ||
cc21f011 JN |
1975 | static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin) |
1976 | { | |
5a449e58 | 1977 | const struct intel_bios_encoder_data *devdata; |
cc21f011 JN |
1978 | enum port port; |
1979 | ||
95bbede5 JN |
1980 | if (!ddc_pin) |
1981 | return PORT_NONE; | |
1982 | ||
c4a774c4 | 1983 | for_each_port(port) { |
5a449e58 | 1984 | devdata = i915->vbt.ports[port]; |
cc21f011 | 1985 | |
5a449e58 | 1986 | if (devdata && ddc_pin == devdata->child.ddc_pin) |
cc21f011 JN |
1987 | return port; |
1988 | } | |
1989 | ||
1990 | return PORT_NONE; | |
1991 | } | |
1992 | ||
dab8477b | 1993 | static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata, |
9454fa87 VS |
1994 | enum port port) |
1995 | { | |
dab8477b | 1996 | struct drm_i915_private *i915 = devdata->i915; |
45c0673a | 1997 | struct child_device_config *child; |
dab8477b | 1998 | u8 mapped_ddc_pin; |
9454fa87 VS |
1999 | enum port p; |
2000 | ||
dab8477b JN |
2001 | if (!devdata->child.ddc_pin) |
2002 | return; | |
2003 | ||
2004 | mapped_ddc_pin = map_ddc_pin(i915, devdata->child.ddc_pin); | |
2005 | if (!intel_gmbus_is_valid_pin(i915, mapped_ddc_pin)) { | |
2006 | drm_dbg_kms(&i915->drm, | |
2007 | "Port %c has invalid DDC pin %d, " | |
2008 | "sticking to defaults\n", | |
2009 | port_name(port), mapped_ddc_pin); | |
2010 | devdata->child.ddc_pin = 0; | |
2011 | return; | |
2012 | } | |
2013 | ||
2014 | p = get_port_by_ddc_pin(i915, devdata->child.ddc_pin); | |
894d1739 JN |
2015 | if (p == PORT_NONE) |
2016 | return; | |
9454fa87 | 2017 | |
894d1739 JN |
2018 | drm_dbg_kms(&i915->drm, |
2019 | "port %c trying to use the same DDC pin (0x%x) as port %c, " | |
2020 | "disabling port %c DVI/HDMI support\n", | |
dab8477b | 2021 | port_name(port), mapped_ddc_pin, |
894d1739 | 2022 | port_name(p), port_name(p)); |
41e35ffb | 2023 | |
894d1739 JN |
2024 | /* |
2025 | * If we have multiple ports supposedly sharing the pin, then dvi/hdmi | |
2026 | * couldn't exist on the shared port. Otherwise they share the same ddc | |
2027 | * pin and system couldn't communicate with them separately. | |
2028 | * | |
2029 | * Give inverse child device order the priority, last one wins. Yes, | |
2030 | * there are real machines (eg. Asrock B250M-HDV) where VBT has both | |
2031 | * port A and port E with the same AUX ch and we must pick port E :( | |
2032 | */ | |
5a449e58 | 2033 | child = &i915->vbt.ports[p]->child; |
45c0673a JN |
2034 | |
2035 | child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; | |
2036 | child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT; | |
894d1739 | 2037 | |
dab8477b | 2038 | child->ddc_pin = 0; |
9454fa87 VS |
2039 | } |
2040 | ||
cc21f011 JN |
2041 | static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch) |
2042 | { | |
5a449e58 | 2043 | const struct intel_bios_encoder_data *devdata; |
cc21f011 JN |
2044 | enum port port; |
2045 | ||
95bbede5 JN |
2046 | if (!aux_ch) |
2047 | return PORT_NONE; | |
2048 | ||
c4a774c4 | 2049 | for_each_port(port) { |
5a449e58 | 2050 | devdata = i915->vbt.ports[port]; |
cc21f011 | 2051 | |
5a449e58 | 2052 | if (devdata && aux_ch == devdata->child.aux_channel) |
cc21f011 JN |
2053 | return port; |
2054 | } | |
2055 | ||
2056 | return PORT_NONE; | |
2057 | } | |
2058 | ||
11182986 | 2059 | static void sanitize_aux_ch(struct intel_bios_encoder_data *devdata, |
9454fa87 VS |
2060 | enum port port) |
2061 | { | |
11182986 | 2062 | struct drm_i915_private *i915 = devdata->i915; |
45c0673a | 2063 | struct child_device_config *child; |
9454fa87 VS |
2064 | enum port p; |
2065 | ||
11182986 | 2066 | p = get_port_by_aux_ch(i915, devdata->child.aux_channel); |
894d1739 JN |
2067 | if (p == PORT_NONE) |
2068 | return; | |
9454fa87 | 2069 | |
894d1739 JN |
2070 | drm_dbg_kms(&i915->drm, |
2071 | "port %c trying to use the same AUX CH (0x%x) as port %c, " | |
2072 | "disabling port %c DP support\n", | |
11182986 | 2073 | port_name(port), devdata->child.aux_channel, |
894d1739 | 2074 | port_name(p), port_name(p)); |
41e35ffb | 2075 | |
894d1739 JN |
2076 | /* |
2077 | * If we have multiple ports supposedly sharing the aux channel, then DP | |
2078 | * couldn't exist on the shared port. Otherwise they share the same aux | |
2079 | * channel and system couldn't communicate with them separately. | |
2080 | * | |
2081 | * Give inverse child device order the priority, last one wins. Yes, | |
2082 | * there are real machines (eg. Asrock B250M-HDV) where VBT has both | |
2083 | * port A and port E with the same AUX ch and we must pick port E :( | |
2084 | */ | |
5a449e58 | 2085 | child = &i915->vbt.ports[p]->child; |
894d1739 | 2086 | |
45c0673a | 2087 | child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT; |
11182986 | 2088 | child->aux_channel = 0; |
9c3b2689 RV |
2089 | } |
2090 | ||
32c2bc89 VS |
2091 | static u8 dvo_port_type(u8 dvo_port) |
2092 | { | |
2093 | switch (dvo_port) { | |
2094 | case DVO_PORT_HDMIA: | |
2095 | case DVO_PORT_HDMIB: | |
2096 | case DVO_PORT_HDMIC: | |
2097 | case DVO_PORT_HDMID: | |
2098 | case DVO_PORT_HDMIE: | |
2099 | case DVO_PORT_HDMIF: | |
2100 | case DVO_PORT_HDMIG: | |
2101 | case DVO_PORT_HDMIH: | |
2102 | case DVO_PORT_HDMII: | |
2103 | return DVO_PORT_HDMIA; | |
2104 | case DVO_PORT_DPA: | |
2105 | case DVO_PORT_DPB: | |
2106 | case DVO_PORT_DPC: | |
2107 | case DVO_PORT_DPD: | |
2108 | case DVO_PORT_DPE: | |
2109 | case DVO_PORT_DPF: | |
2110 | case DVO_PORT_DPG: | |
2111 | case DVO_PORT_DPH: | |
2112 | case DVO_PORT_DPI: | |
2113 | return DVO_PORT_DPA; | |
2114 | case DVO_PORT_MIPIA: | |
2115 | case DVO_PORT_MIPIB: | |
2116 | case DVO_PORT_MIPIC: | |
2117 | case DVO_PORT_MIPID: | |
2118 | return DVO_PORT_MIPIA; | |
2119 | default: | |
2120 | return dvo_port; | |
2121 | } | |
2122 | } | |
2123 | ||
4628142a LDM |
2124 | static enum port __dvo_port_to_port(int n_ports, int n_dvo, |
2125 | const int port_mapping[][3], u8 dvo_port) | |
6acab15a | 2126 | { |
b024ab9b JN |
2127 | enum port port; |
2128 | int i; | |
6acab15a | 2129 | |
4628142a LDM |
2130 | for (port = PORT_A; port < n_ports; port++) { |
2131 | for (i = 0; i < n_dvo; i++) { | |
2132 | if (port_mapping[port][i] == -1) | |
6acab15a PZ |
2133 | break; |
2134 | ||
4628142a | 2135 | if (dvo_port == port_mapping[port][i]) |
b024ab9b | 2136 | return port; |
6acab15a PZ |
2137 | } |
2138 | } | |
b024ab9b JN |
2139 | |
2140 | return PORT_NONE; | |
2141 | } | |
2142 | ||
dbd440d8 | 2143 | static enum port dvo_port_to_port(struct drm_i915_private *i915, |
4628142a LDM |
2144 | u8 dvo_port) |
2145 | { | |
2146 | /* | |
2147 | * Each DDI port can have more than one value on the "DVO Port" field, | |
2148 | * so look for all the possible values for each port. | |
2149 | */ | |
2150 | static const int port_mapping[][3] = { | |
2151 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2152 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2153 | [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, | |
2154 | [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
8c1a8f12 | 2155 | [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, |
4628142a LDM |
2156 | [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, |
2157 | [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, | |
176430cc VS |
2158 | [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, |
2159 | [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, | |
4628142a LDM |
2160 | }; |
2161 | /* | |
1d8ca002 VS |
2162 | * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D |
2163 | * map to DDI A,B,TC1,TC2 respectively. | |
4628142a LDM |
2164 | */ |
2165 | static const int rkl_port_mapping[][3] = { | |
2166 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2167 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2168 | [PORT_C] = { -1 }, | |
1d8ca002 VS |
2169 | [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, |
2170 | [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
4628142a | 2171 | }; |
18c283df AS |
2172 | /* |
2173 | * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E, | |
2174 | * PORT_F and PORT_G, we need to map that to correct VBT sections. | |
2175 | */ | |
2176 | static const int adls_port_mapping[][3] = { | |
2177 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2178 | [PORT_B] = { -1 }, | |
2179 | [PORT_C] = { -1 }, | |
2180 | [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2181 | [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, | |
2182 | [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
2183 | [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, | |
2184 | }; | |
eeb63c54 JRS |
2185 | static const int xelpd_port_mapping[][3] = { |
2186 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2187 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2188 | [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, | |
2189 | [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
2190 | [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, | |
2191 | [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, | |
2192 | [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, | |
2193 | [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, | |
2194 | [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, | |
2195 | }; | |
4628142a | 2196 | |
eeb63c54 JRS |
2197 | if (DISPLAY_VER(i915) == 13) |
2198 | return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping), | |
2199 | ARRAY_SIZE(xelpd_port_mapping[0]), | |
2200 | xelpd_port_mapping, | |
2201 | dvo_port); | |
2202 | else if (IS_ALDERLAKE_S(i915)) | |
18c283df AS |
2203 | return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping), |
2204 | ARRAY_SIZE(adls_port_mapping[0]), | |
2205 | adls_port_mapping, | |
2206 | dvo_port); | |
dbd440d8 | 2207 | else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) |
4628142a LDM |
2208 | return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), |
2209 | ARRAY_SIZE(rkl_port_mapping[0]), | |
2210 | rkl_port_mapping, | |
2211 | dvo_port); | |
2212 | else | |
2213 | return __dvo_port_to_port(ARRAY_SIZE(port_mapping), | |
2214 | ARRAY_SIZE(port_mapping[0]), | |
2215 | port_mapping, | |
2216 | dvo_port); | |
2217 | } | |
2218 | ||
b60e320b LS |
2219 | static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate) |
2220 | { | |
2221 | switch (vbt_max_link_rate) { | |
2222 | default: | |
2223 | case BDB_230_VBT_DP_MAX_LINK_RATE_DEF: | |
2224 | return 0; | |
2225 | case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20: | |
2226 | return 2000000; | |
2227 | case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5: | |
2228 | return 1350000; | |
2229 | case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10: | |
2230 | return 1000000; | |
2231 | case BDB_230_VBT_DP_MAX_LINK_RATE_HBR3: | |
2232 | return 810000; | |
2233 | case BDB_230_VBT_DP_MAX_LINK_RATE_HBR2: | |
2234 | return 540000; | |
2235 | case BDB_230_VBT_DP_MAX_LINK_RATE_HBR: | |
2236 | return 270000; | |
2237 | case BDB_230_VBT_DP_MAX_LINK_RATE_LBR: | |
2238 | return 162000; | |
2239 | } | |
2240 | } | |
2241 | ||
2242 | static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate) | |
2243 | { | |
2244 | switch (vbt_max_link_rate) { | |
2245 | default: | |
2246 | case BDB_216_VBT_DP_MAX_LINK_RATE_HBR3: | |
2247 | return 810000; | |
2248 | case BDB_216_VBT_DP_MAX_LINK_RATE_HBR2: | |
2249 | return 540000; | |
2250 | case BDB_216_VBT_DP_MAX_LINK_RATE_HBR: | |
2251 | return 270000; | |
2252 | case BDB_216_VBT_DP_MAX_LINK_RATE_LBR: | |
2253 | return 162000; | |
2254 | } | |
2255 | } | |
2256 | ||
72337aac JN |
2257 | static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata) |
2258 | { | |
2259 | if (!devdata || devdata->i915->vbt.version < 216) | |
2260 | return 0; | |
2261 | ||
2262 | if (devdata->i915->vbt.version >= 230) | |
2263 | return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate); | |
2264 | else | |
2265 | return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate); | |
2266 | } | |
2267 | ||
d0ab409d JN |
2268 | static void sanitize_device_type(struct intel_bios_encoder_data *devdata, |
2269 | enum port port) | |
2270 | { | |
2271 | struct drm_i915_private *i915 = devdata->i915; | |
2272 | bool is_hdmi; | |
2273 | ||
005e9537 | 2274 | if (port != PORT_A || DISPLAY_VER(i915) >= 12) |
d0ab409d JN |
2275 | return; |
2276 | ||
2277 | if (!(devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING)) | |
2278 | return; | |
2279 | ||
2280 | is_hdmi = !(devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT); | |
2281 | ||
2282 | drm_dbg_kms(&i915->drm, "VBT claims port A supports DVI%s, ignoring\n", | |
2283 | is_hdmi ? "/HDMI" : ""); | |
2284 | ||
2285 | devdata->child.device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; | |
2286 | devdata->child.device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT; | |
2287 | } | |
2288 | ||
2289 | static bool | |
2290 | intel_bios_encoder_supports_crt(const struct intel_bios_encoder_data *devdata) | |
2291 | { | |
2292 | return devdata->child.device_type & DEVICE_TYPE_ANALOG_OUTPUT; | |
2293 | } | |
2294 | ||
45c0673a | 2295 | bool |
d0ab409d JN |
2296 | intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata) |
2297 | { | |
2298 | return devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; | |
2299 | } | |
2300 | ||
45c0673a | 2301 | bool |
d0ab409d JN |
2302 | intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata) |
2303 | { | |
2304 | return intel_bios_encoder_supports_dvi(devdata) && | |
2305 | (devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; | |
2306 | } | |
2307 | ||
45c0673a | 2308 | bool |
d0ab409d JN |
2309 | intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata) |
2310 | { | |
2311 | return devdata->child.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
2312 | } | |
2313 | ||
2314 | static bool | |
2315 | intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata) | |
2316 | { | |
2317 | return intel_bios_encoder_supports_dp(devdata) && | |
2318 | devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR; | |
2319 | } | |
2320 | ||
a9a56e76 JN |
2321 | static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata) |
2322 | { | |
2323 | if (!devdata || devdata->i915->vbt.version < 158) | |
2324 | return -1; | |
2325 | ||
2326 | return devdata->child.hdmi_level_shifter_value; | |
2327 | } | |
2328 | ||
6ba69981 JN |
2329 | static int _intel_bios_max_tmds_clock(const struct intel_bios_encoder_data *devdata) |
2330 | { | |
2331 | if (!devdata || devdata->i915->vbt.version < 204) | |
2332 | return 0; | |
2333 | ||
2334 | switch (devdata->child.hdmi_max_data_rate) { | |
2335 | default: | |
2336 | MISSING_CASE(devdata->child.hdmi_max_data_rate); | |
2337 | fallthrough; | |
2338 | case HDMI_MAX_DATA_RATE_PLATFORM: | |
2339 | return 0; | |
5708fe0d LS |
2340 | case HDMI_MAX_DATA_RATE_594: |
2341 | return 594000; | |
2342 | case HDMI_MAX_DATA_RATE_340: | |
2343 | return 340000; | |
2344 | case HDMI_MAX_DATA_RATE_300: | |
2345 | return 300000; | |
6ba69981 JN |
2346 | case HDMI_MAX_DATA_RATE_297: |
2347 | return 297000; | |
2348 | case HDMI_MAX_DATA_RATE_165: | |
2349 | return 165000; | |
2350 | } | |
2351 | } | |
2352 | ||
5a9d38b2 LDM |
2353 | static bool is_port_valid(struct drm_i915_private *i915, enum port port) |
2354 | { | |
2355 | /* | |
cad83b40 | 2356 | * On some ICL SKUs port F is not present, but broken VBTs mark |
5a9d38b2 LDM |
2357 | * the port as present. Only try to initialize port F for the |
2358 | * SKUs that may actually have it. | |
2359 | */ | |
cad83b40 LDM |
2360 | if (port == PORT_F && IS_ICELAKE(i915)) |
2361 | return IS_ICL_WITH_PORT_F(i915); | |
5a9d38b2 LDM |
2362 | |
2363 | return true; | |
2364 | } | |
2365 | ||
dbd440d8 | 2366 | static void parse_ddi_port(struct drm_i915_private *i915, |
3162d057 | 2367 | struct intel_bios_encoder_data *devdata) |
b024ab9b | 2368 | { |
d1dad6f4 | 2369 | const struct child_device_config *child = &devdata->child; |
f08fbe6a | 2370 | bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, supports_tbt; |
72337aac | 2371 | int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock; |
b024ab9b JN |
2372 | enum port port; |
2373 | ||
dbd440d8 | 2374 | port = dvo_port_to_port(i915, child->dvo_port); |
b024ab9b JN |
2375 | if (port == PORT_NONE) |
2376 | return; | |
2377 | ||
5a9d38b2 LDM |
2378 | if (!is_port_valid(i915, port)) { |
2379 | drm_dbg_kms(&i915->drm, | |
2380 | "VBT reports port %c as supported, but that can't be true: skipping\n", | |
2381 | port_name(port)); | |
2382 | return; | |
2383 | } | |
2384 | ||
5a449e58 | 2385 | if (i915->vbt.ports[port]) { |
dbd440d8 | 2386 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2387 | "More than one child device for port %c in VBT, using the first.\n", |
2388 | port_name(port)); | |
6acab15a | 2389 | return; |
b024ab9b JN |
2390 | } |
2391 | ||
d0ab409d | 2392 | sanitize_device_type(devdata, port); |
554d6af5 | 2393 | |
d0ab409d JN |
2394 | is_dvi = intel_bios_encoder_supports_dvi(devdata); |
2395 | is_dp = intel_bios_encoder_supports_dp(devdata); | |
2396 | is_crt = intel_bios_encoder_supports_crt(devdata); | |
2397 | is_hdmi = intel_bios_encoder_supports_hdmi(devdata); | |
2398 | is_edp = intel_bios_encoder_supports_edp(devdata); | |
2ba7d7e0 | 2399 | |
f08fbe6a JN |
2400 | supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata); |
2401 | supports_tbt = intel_bios_encoder_supports_tbt(devdata); | |
38b3416f | 2402 | |
dbd440d8 | 2403 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2404 | "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", |
2405 | port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, | |
dbd440d8 | 2406 | HAS_LSPCON(i915) && child->lspcon, |
f08fbe6a | 2407 | supports_typec_usb, supports_tbt, |
e92cbf38 | 2408 | devdata->dsc != NULL); |
554d6af5 | 2409 | |
dab8477b JN |
2410 | if (is_dvi) |
2411 | sanitize_ddc_pin(devdata, port); | |
6bf19e7c | 2412 | |
11182986 JN |
2413 | if (is_dp) |
2414 | sanitize_aux_ch(devdata, port); | |
6bf19e7c | 2415 | |
a9a56e76 JN |
2416 | hdmi_level_shift = _intel_bios_hdmi_level_shift(devdata); |
2417 | if (hdmi_level_shift >= 0) { | |
dbd440d8 | 2418 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2419 | "Port %c VBT HDMI level shift: %d\n", |
a9a56e76 | 2420 | port_name(port), hdmi_level_shift); |
6acab15a | 2421 | } |
75067dde | 2422 | |
6ba69981 JN |
2423 | max_tmds_clock = _intel_bios_max_tmds_clock(devdata); |
2424 | if (max_tmds_clock) | |
2425 | drm_dbg_kms(&i915->drm, | |
2426 | "Port %c VBT HDMI max TMDS clock: %d kHz\n", | |
2427 | port_name(port), max_tmds_clock); | |
d6038611 | 2428 | |
c0a950d1 JN |
2429 | /* I_boost config for SKL and above */ |
2430 | dp_boost_level = intel_bios_encoder_dp_boost_level(devdata); | |
2431 | if (dp_boost_level) | |
dbd440d8 | 2432 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2433 | "Port %c VBT (e)DP boost level: %d\n", |
c0a950d1 JN |
2434 | port_name(port), dp_boost_level); |
2435 | ||
2436 | hdmi_boost_level = intel_bios_encoder_hdmi_boost_level(devdata); | |
2437 | if (hdmi_boost_level) | |
dbd440d8 | 2438 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2439 | "Port %c VBT HDMI boost level: %d\n", |
c0a950d1 | 2440 | port_name(port), hdmi_boost_level); |
99b91bda | 2441 | |
72337aac JN |
2442 | dp_max_link_rate = _intel_bios_dp_max_link_rate(devdata); |
2443 | if (dp_max_link_rate) | |
dbd440d8 | 2444 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2445 | "Port %c VBT DP max link rate: %d\n", |
72337aac | 2446 | port_name(port), dp_max_link_rate); |
7679f9b8 | 2447 | |
5a449e58 | 2448 | i915->vbt.ports[port] = devdata; |
6acab15a PZ |
2449 | } |
2450 | ||
b90b6e41 VS |
2451 | static bool has_ddi_port_info(struct drm_i915_private *i915) |
2452 | { | |
594c504d | 2453 | return DISPLAY_VER(i915) >= 5 || IS_G4X(i915); |
b90b6e41 VS |
2454 | } |
2455 | ||
ef0096e4 | 2456 | static void parse_ddi_ports(struct drm_i915_private *i915) |
6acab15a | 2457 | { |
3162d057 | 2458 | struct intel_bios_encoder_data *devdata; |
6acab15a | 2459 | |
eb9fcf63 | 2460 | if (!has_ddi_port_info(i915)) |
6acab15a PZ |
2461 | return; |
2462 | ||
dbd440d8 | 2463 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) |
ef0096e4 | 2464 | parse_ddi_port(i915, devdata); |
6acab15a PZ |
2465 | } |
2466 | ||
6363ee6f | 2467 | static void |
e163cfb4 | 2468 | parse_general_definitions(struct drm_i915_private *i915) |
6363ee6f | 2469 | { |
e192839e | 2470 | const struct bdb_general_definitions *defs; |
3162d057 | 2471 | struct intel_bios_encoder_data *devdata; |
e192839e | 2472 | const struct child_device_config *child; |
0d9ef19b | 2473 | int i, child_device_num; |
e2d6cf7f DW |
2474 | u8 expected_size; |
2475 | u16 block_size; | |
b3ca1f43 | 2476 | int bus_pin; |
6363ee6f | 2477 | |
e163cfb4 | 2478 | defs = find_section(i915, BDB_GENERAL_DEFINITIONS); |
e192839e | 2479 | if (!defs) { |
dbd440d8 | 2480 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 2481 | "No general definition block is found, no devices defined.\n"); |
6363ee6f ZY |
2482 | return; |
2483 | } | |
b3ca1f43 JN |
2484 | |
2485 | block_size = get_blocksize(defs); | |
2486 | if (block_size < sizeof(*defs)) { | |
dbd440d8 | 2487 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2488 | "General definitions block too small (%u)\n", |
2489 | block_size); | |
b3ca1f43 JN |
2490 | return; |
2491 | } | |
2492 | ||
2493 | bus_pin = defs->crt_ddc_gmbus_pin; | |
dbd440d8 JN |
2494 | drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin); |
2495 | if (intel_gmbus_is_valid_pin(i915, bus_pin)) | |
2496 | i915->vbt.crt_ddc_pin = bus_pin; | |
b3ca1f43 | 2497 | |
d58a3d69 | 2498 | if (i915->vbt.version < 106) { |
7244f309 | 2499 | expected_size = 22; |
d58a3d69 | 2500 | } else if (i915->vbt.version < 111) { |
52b69c84 | 2501 | expected_size = 27; |
d58a3d69 | 2502 | } else if (i915->vbt.version < 195) { |
21907e72 | 2503 | expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; |
d58a3d69 | 2504 | } else if (i915->vbt.version == 195) { |
e2d6cf7f | 2505 | expected_size = 37; |
d58a3d69 | 2506 | } else if (i915->vbt.version <= 215) { |
e2d6cf7f | 2507 | expected_size = 38; |
d58a3d69 | 2508 | } else if (i915->vbt.version <= 237) { |
c4fb60b9 | 2509 | expected_size = 39; |
e2d6cf7f | 2510 | } else { |
c4fb60b9 JN |
2511 | expected_size = sizeof(*child); |
2512 | BUILD_BUG_ON(sizeof(*child) < 39); | |
dbd440d8 | 2513 | drm_dbg(&i915->drm, |
e92cbf38 | 2514 | "Expected child device config size for VBT version %u not known; assuming %u\n", |
d58a3d69 | 2515 | i915->vbt.version, expected_size); |
e2d6cf7f DW |
2516 | } |
2517 | ||
e2d6cf7f | 2518 | /* Flag an error for unexpected size, but continue anyway. */ |
e192839e | 2519 | if (defs->child_dev_size != expected_size) |
dbd440d8 | 2520 | drm_err(&i915->drm, |
e92cbf38 | 2521 | "Unexpected child device config size %u (expected %u for VBT version %u)\n", |
d58a3d69 | 2522 | defs->child_dev_size, expected_size, i915->vbt.version); |
e2d6cf7f | 2523 | |
52b69c84 | 2524 | /* The legacy sized child device config is the minimum we need. */ |
e192839e | 2525 | if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { |
dbd440d8 | 2526 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2527 | "Child device config size %u is too small.\n", |
2528 | defs->child_dev_size); | |
52b69c84 VS |
2529 | return; |
2530 | } | |
2531 | ||
6363ee6f | 2532 | /* get the number of child device */ |
e192839e | 2533 | child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; |
6363ee6f | 2534 | |
6363ee6f | 2535 | for (i = 0; i < child_device_num; i++) { |
e192839e | 2536 | child = child_device_ptr(defs, i); |
53f6b243 | 2537 | if (!child->device_type) |
6363ee6f | 2538 | continue; |
3e6bd011 | 2539 | |
dbd440d8 | 2540 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2541 | "Found VBT child device with type 0x%x\n", |
2542 | child->device_type); | |
bdeb18db | 2543 | |
0d9ef19b JN |
2544 | devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); |
2545 | if (!devdata) | |
2546 | break; | |
2547 | ||
7371fa34 JN |
2548 | devdata->i915 = i915; |
2549 | ||
e2d6cf7f DW |
2550 | /* |
2551 | * Copy as much as we know (sizeof) and is available | |
0d9ef19b JN |
2552 | * (child_dev_size) of the child device config. Accessing the |
2553 | * data must depend on VBT version. | |
e2d6cf7f | 2554 | */ |
0d9ef19b | 2555 | memcpy(&devdata->child, child, |
e192839e | 2556 | min_t(size_t, defs->child_dev_size, sizeof(*child))); |
0d9ef19b | 2557 | |
dbd440d8 | 2558 | list_add_tail(&devdata->node, &i915->vbt.display_devices); |
6363ee6f | 2559 | } |
0d9ef19b | 2560 | |
dbd440d8 JN |
2561 | if (list_empty(&i915->vbt.display_devices)) |
2562 | drm_dbg_kms(&i915->drm, | |
e92cbf38 | 2563 | "no child dev is parsed from VBT\n"); |
6363ee6f | 2564 | } |
44834a67 | 2565 | |
bb1d1329 | 2566 | /* Common defaults which may be overridden by VBT. */ |
6a04002b | 2567 | static void |
dbd440d8 | 2568 | init_vbt_defaults(struct drm_i915_private *i915) |
6a04002b | 2569 | { |
dbd440d8 | 2570 | i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; |
6a04002b | 2571 | |
56c4b63a | 2572 | /* Default to having backlight */ |
dbd440d8 | 2573 | i915->vbt.backlight.present = true; |
56c4b63a | 2574 | |
6a04002b | 2575 | /* LFP panel data */ |
dbd440d8 | 2576 | i915->vbt.lvds_dither = 1; |
6a04002b SQ |
2577 | |
2578 | /* SDVO panel data */ | |
dbd440d8 | 2579 | i915->vbt.sdvo_lvds_vbt_mode = NULL; |
6a04002b SQ |
2580 | |
2581 | /* general features */ | |
dbd440d8 JN |
2582 | i915->vbt.int_tv_support = 1; |
2583 | i915->vbt.int_crt_support = 1; | |
9a4114ff | 2584 | |
5255e2f8 | 2585 | /* driver features */ |
dbd440d8 | 2586 | i915->vbt.int_lvds_support = 1; |
5255e2f8 | 2587 | |
9a4114ff | 2588 | /* Default to using SSC */ |
dbd440d8 | 2589 | i915->vbt.lvds_use_ssc = 1; |
f69e5156 DL |
2590 | /* |
2591 | * Core/SandyBridge/IvyBridge use alternative (120MHz) reference | |
2592 | * clock for LVDS. | |
2593 | */ | |
dbd440d8 JN |
2594 | i915->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915, |
2595 | !HAS_PCH_SPLIT(i915)); | |
2596 | drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n", | |
2597 | i915->vbt.lvds_ssc_freq); | |
bb1d1329 JN |
2598 | } |
2599 | ||
2600 | /* Defaults to initialize only if there is no VBT. */ | |
2601 | static void | |
dbd440d8 | 2602 | init_vbt_missing_defaults(struct drm_i915_private *i915) |
bb1d1329 JN |
2603 | { |
2604 | enum port port; | |
9b52aa72 RV |
2605 | int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | |
2606 | BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F); | |
bb1d1329 | 2607 | |
e20e4037 JN |
2608 | if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) |
2609 | return; | |
2610 | ||
3ae04c0c | 2611 | for_each_port_masked(port, ports) { |
3162d057 | 2612 | struct intel_bios_encoder_data *devdata; |
51f57481 | 2613 | struct child_device_config *child; |
dbd440d8 | 2614 | enum phy phy = intel_port_to_phy(i915, port); |
311a2094 | 2615 | |
828ccb31 ID |
2616 | /* |
2617 | * VBT has the TypeC mode (native,TBT/USB) and we don't want | |
2618 | * to detect it. | |
2619 | */ | |
dbd440d8 | 2620 | if (intel_phy_is_tc(i915, phy)) |
828ccb31 ID |
2621 | continue; |
2622 | ||
51f57481 JN |
2623 | /* Create fake child device config */ |
2624 | devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); | |
2625 | if (!devdata) | |
2626 | break; | |
2627 | ||
7371fa34 | 2628 | devdata->i915 = i915; |
51f57481 JN |
2629 | child = &devdata->child; |
2630 | ||
2631 | if (port == PORT_F) | |
2632 | child->dvo_port = DVO_PORT_HDMIF; | |
2633 | else if (port == PORT_E) | |
2634 | child->dvo_port = DVO_PORT_HDMIE; | |
2635 | else | |
2636 | child->dvo_port = DVO_PORT_HDMIA + port; | |
2637 | ||
2638 | if (port != PORT_A && port != PORT_E) | |
2639 | child->device_type |= DEVICE_TYPE_TMDS_DVI_SIGNALING; | |
2640 | ||
2641 | if (port != PORT_E) | |
2642 | child->device_type |= DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
2643 | ||
2644 | if (port == PORT_A) | |
2645 | child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR; | |
2646 | ||
2647 | list_add_tail(&devdata->node, &i915->vbt.display_devices); | |
2648 | ||
2649 | drm_dbg_kms(&i915->drm, | |
2650 | "Generating default VBT child device with type 0x04%x on port %c\n", | |
2651 | child->device_type, port_name(port)); | |
6acab15a | 2652 | } |
51f57481 JN |
2653 | |
2654 | /* Bypass some minimum baseline VBT version checks */ | |
2655 | i915->vbt.version = 155; | |
6a04002b SQ |
2656 | } |
2657 | ||
caf37fa4 JN |
2658 | static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) |
2659 | { | |
2660 | const void *_vbt = vbt; | |
2661 | ||
2662 | return _vbt + vbt->bdb_offset; | |
2663 | } | |
2664 | ||
f0067a31 JN |
2665 | /** |
2666 | * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT | |
2667 | * @buf: pointer to a buffer to validate | |
2668 | * @size: size of the buffer | |
2669 | * | |
2670 | * Returns true on valid VBT. | |
2671 | */ | |
2672 | bool intel_bios_is_valid_vbt(const void *buf, size_t size) | |
3dd4e846 | 2673 | { |
f0067a31 | 2674 | const struct vbt_header *vbt = buf; |
dcb58a40 | 2675 | const struct bdb_header *bdb; |
3dd4e846 | 2676 | |
caf37fa4 | 2677 | if (!vbt) |
f0067a31 | 2678 | return false; |
caf37fa4 | 2679 | |
f0067a31 | 2680 | if (sizeof(struct vbt_header) > size) { |
3dd4e846 | 2681 | DRM_DEBUG_DRIVER("VBT header incomplete\n"); |
f0067a31 | 2682 | return false; |
3dd4e846 CW |
2683 | } |
2684 | ||
2685 | if (memcmp(vbt->signature, "$VBT", 4)) { | |
2686 | DRM_DEBUG_DRIVER("VBT invalid signature\n"); | |
f0067a31 | 2687 | return false; |
3dd4e846 CW |
2688 | } |
2689 | ||
ff00ff96 LDM |
2690 | if (vbt->vbt_size > size) { |
2691 | DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n"); | |
2692 | return false; | |
2693 | } | |
2694 | ||
2695 | size = vbt->vbt_size; | |
2696 | ||
e8f9ae9b CW |
2697 | if (range_overflows_t(size_t, |
2698 | vbt->bdb_offset, | |
2699 | sizeof(struct bdb_header), | |
2700 | size)) { | |
3dd4e846 | 2701 | DRM_DEBUG_DRIVER("BDB header incomplete\n"); |
f0067a31 | 2702 | return false; |
3dd4e846 CW |
2703 | } |
2704 | ||
caf37fa4 | 2705 | bdb = get_bdb_header(vbt); |
e8f9ae9b | 2706 | if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { |
3dd4e846 | 2707 | DRM_DEBUG_DRIVER("BDB incomplete\n"); |
f0067a31 | 2708 | return false; |
3dd4e846 CW |
2709 | } |
2710 | ||
caf37fa4 | 2711 | return vbt; |
3dd4e846 CW |
2712 | } |
2713 | ||
a36e7dc0 CT |
2714 | static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915) |
2715 | { | |
2716 | u32 count, data, found, store = 0; | |
2717 | u32 static_region, oprom_offset; | |
2718 | u32 oprom_size = 0x200000; | |
2719 | u16 vbt_size; | |
2720 | u32 *vbt; | |
2721 | ||
2722 | static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS); | |
2723 | static_region &= OPTIONROM_SPI_REGIONID_MASK; | |
2724 | intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region); | |
2725 | ||
2726 | oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET); | |
2727 | oprom_offset &= OROM_OFFSET_MASK; | |
2728 | ||
2729 | for (count = 0; count < oprom_size; count += 4) { | |
2730 | intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, oprom_offset + count); | |
2731 | data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER); | |
2732 | ||
2733 | if (data == *((const u32 *)"$VBT")) { | |
2734 | found = oprom_offset + count; | |
2735 | break; | |
2736 | } | |
2737 | } | |
2738 | ||
2739 | if (count >= oprom_size) | |
2740 | goto err_not_found; | |
2741 | ||
2742 | /* Get VBT size and allocate space for the VBT */ | |
2743 | intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + | |
2744 | offsetof(struct vbt_header, vbt_size)); | |
2745 | vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER); | |
2746 | vbt_size &= 0xffff; | |
2747 | ||
980f42e7 | 2748 | vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL); |
a36e7dc0 CT |
2749 | if (!vbt) |
2750 | goto err_not_found; | |
2751 | ||
2752 | for (count = 0; count < vbt_size; count += 4) { | |
2753 | intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found + count); | |
2754 | data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER); | |
2755 | *(vbt + store++) = data; | |
2756 | } | |
2757 | ||
2758 | if (!intel_bios_is_valid_vbt(vbt, vbt_size)) | |
2759 | goto err_free_vbt; | |
2760 | ||
2761 | drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n"); | |
2762 | ||
2763 | return (struct vbt_header *)vbt; | |
2764 | ||
2765 | err_free_vbt: | |
2766 | kfree(vbt); | |
2767 | err_not_found: | |
2768 | return NULL; | |
2769 | } | |
2770 | ||
dbd440d8 | 2771 | static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915) |
b34a991a | 2772 | { |
dbd440d8 | 2773 | struct pci_dev *pdev = to_pci_dev(i915->drm.dev); |
2cded152 | 2774 | void __iomem *p = NULL, *oprom; |
fd0186ce LDM |
2775 | struct vbt_header *vbt; |
2776 | u16 vbt_size; | |
2cded152 LDM |
2777 | size_t i, size; |
2778 | ||
2779 | oprom = pci_map_rom(pdev, &size); | |
2780 | if (!oprom) | |
2781 | return NULL; | |
b34a991a JN |
2782 | |
2783 | /* Scour memory looking for the VBT signature. */ | |
98cf5c9a | 2784 | for (i = 0; i + 4 < size; i += 4) { |
496f50a6 | 2785 | if (ioread32(oprom + i) != *((const u32 *)"$VBT")) |
f0067a31 JN |
2786 | continue; |
2787 | ||
fd0186ce LDM |
2788 | p = oprom + i; |
2789 | size -= i; | |
f0067a31 | 2790 | break; |
b34a991a JN |
2791 | } |
2792 | ||
fd0186ce | 2793 | if (!p) |
2cded152 | 2794 | goto err_unmap_oprom; |
fd0186ce LDM |
2795 | |
2796 | if (sizeof(struct vbt_header) > size) { | |
dbd440d8 | 2797 | drm_dbg(&i915->drm, "VBT header incomplete\n"); |
2cded152 | 2798 | goto err_unmap_oprom; |
fd0186ce LDM |
2799 | } |
2800 | ||
2801 | vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); | |
2802 | if (vbt_size > size) { | |
dbd440d8 | 2803 | drm_dbg(&i915->drm, |
e92cbf38 | 2804 | "VBT incomplete (vbt_size overflows)\n"); |
2cded152 | 2805 | goto err_unmap_oprom; |
fd0186ce LDM |
2806 | } |
2807 | ||
2808 | /* The rest will be validated by intel_bios_is_valid_vbt() */ | |
2809 | vbt = kmalloc(vbt_size, GFP_KERNEL); | |
2810 | if (!vbt) | |
2cded152 | 2811 | goto err_unmap_oprom; |
fd0186ce LDM |
2812 | |
2813 | memcpy_fromio(vbt, p, vbt_size); | |
2814 | ||
2815 | if (!intel_bios_is_valid_vbt(vbt, vbt_size)) | |
2816 | goto err_free_vbt; | |
2817 | ||
2cded152 LDM |
2818 | pci_unmap_rom(pdev, oprom); |
2819 | ||
a36e7dc0 CT |
2820 | drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n"); |
2821 | ||
fd0186ce LDM |
2822 | return vbt; |
2823 | ||
2824 | err_free_vbt: | |
2825 | kfree(vbt); | |
2cded152 LDM |
2826 | err_unmap_oprom: |
2827 | pci_unmap_rom(pdev, oprom); | |
fd0186ce | 2828 | |
f0067a31 | 2829 | return NULL; |
b34a991a JN |
2830 | } |
2831 | ||
79e53945 | 2832 | /** |
8b8e1a89 | 2833 | * intel_bios_init - find VBT and initialize settings from the BIOS |
dbd440d8 | 2834 | * @i915: i915 device instance |
79e53945 | 2835 | * |
66578857 JN |
2836 | * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT |
2837 | * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also | |
2838 | * initialize some defaults if the VBT is not present at all. | |
79e53945 | 2839 | */ |
dbd440d8 | 2840 | void intel_bios_init(struct drm_i915_private *i915) |
79e53945 | 2841 | { |
dbd440d8 | 2842 | const struct vbt_header *vbt = i915->opregion.vbt; |
2cded152 | 2843 | struct vbt_header *oprom_vbt = NULL; |
caf37fa4 | 2844 | const struct bdb_header *bdb; |
44834a67 | 2845 | |
dbd440d8 | 2846 | INIT_LIST_HEAD(&i915->vbt.display_devices); |
e163cfb4 | 2847 | INIT_LIST_HEAD(&i915->vbt.bdb_blocks); |
0d9ef19b | 2848 | |
dbd440d8 JN |
2849 | if (!HAS_DISPLAY(i915)) { |
2850 | drm_dbg_kms(&i915->drm, | |
e92cbf38 | 2851 | "Skipping VBT init due to disabled display.\n"); |
66578857 JN |
2852 | return; |
2853 | } | |
ab5c608b | 2854 | |
dbd440d8 | 2855 | init_vbt_defaults(i915); |
f899fc64 | 2856 | |
a36e7dc0 CT |
2857 | /* |
2858 | * If the OpRegion does not have VBT, look in SPI flash through MMIO or | |
2859 | * PCI mapping | |
2860 | */ | |
2861 | if (!vbt && IS_DGFX(i915)) { | |
2862 | oprom_vbt = spi_oprom_get_vbt(i915); | |
2863 | vbt = oprom_vbt; | |
2864 | } | |
2865 | ||
f0067a31 | 2866 | if (!vbt) { |
dbd440d8 | 2867 | oprom_vbt = oprom_get_vbt(i915); |
2cded152 | 2868 | vbt = oprom_vbt; |
44834a67 | 2869 | } |
79e53945 | 2870 | |
a36e7dc0 CT |
2871 | if (!vbt) |
2872 | goto out; | |
2873 | ||
caf37fa4 | 2874 | bdb = get_bdb_header(vbt); |
ef0096e4 | 2875 | i915->vbt.version = bdb->version; |
caf37fa4 | 2876 | |
dbd440d8 | 2877 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 2878 | "VBT signature \"%.*s\", BDB version %d\n", |
d58a3d69 | 2879 | (int)sizeof(vbt->signature), vbt->signature, i915->vbt.version); |
e2051c44 | 2880 | |
e163cfb4 VS |
2881 | init_bdb_blocks(i915, bdb); |
2882 | ||
79e53945 | 2883 | /* Grab useful general definitions */ |
e163cfb4 VS |
2884 | parse_general_features(i915); |
2885 | parse_general_definitions(i915); | |
2886 | parse_panel_options(i915); | |
13367132 VS |
2887 | parse_generic_dtd(i915); |
2888 | parse_lfp_data(i915); | |
e163cfb4 VS |
2889 | parse_lfp_backlight(i915); |
2890 | parse_sdvo_panel_data(i915); | |
2891 | parse_driver_features(i915); | |
2892 | parse_power_conservation_features(i915); | |
2893 | parse_edp(i915); | |
2894 | parse_psr(i915); | |
2895 | parse_mipi_config(i915); | |
2896 | parse_mipi_sequence(i915); | |
0ebdabe6 | 2897 | |
6e0d46e9 | 2898 | /* Depends on child device list */ |
e163cfb4 | 2899 | parse_compression_parameters(i915); |
6e0d46e9 | 2900 | |
66578857 | 2901 | out: |
bb1d1329 | 2902 | if (!vbt) { |
dbd440d8 | 2903 | drm_info(&i915->drm, |
e92cbf38 | 2904 | "Failed to find VBIOS tables (VBT)\n"); |
dbd440d8 | 2905 | init_vbt_missing_defaults(i915); |
bb1d1329 | 2906 | } |
66578857 | 2907 | |
51f57481 JN |
2908 | /* Further processing on pre-parsed or generated child device data */ |
2909 | parse_sdvo_device_mapping(i915); | |
2910 | parse_ddi_ports(i915); | |
2911 | ||
2cded152 | 2912 | kfree(oprom_vbt); |
79e53945 | 2913 | } |
3bdd14d5 | 2914 | |
785f076b | 2915 | /** |
78dae1ac | 2916 | * intel_bios_driver_remove - Free any resources allocated by intel_bios_init() |
dbd440d8 | 2917 | * @i915: i915 device instance |
785f076b | 2918 | */ |
dbd440d8 | 2919 | void intel_bios_driver_remove(struct drm_i915_private *i915) |
785f076b | 2920 | { |
e163cfb4 VS |
2921 | struct intel_bios_encoder_data *devdata, *nd; |
2922 | struct bdb_block_entry *entry, *ne; | |
0d9ef19b | 2923 | |
e163cfb4 | 2924 | list_for_each_entry_safe(devdata, nd, &i915->vbt.display_devices, node) { |
0d9ef19b | 2925 | list_del(&devdata->node); |
6e0d46e9 | 2926 | kfree(devdata->dsc); |
0d9ef19b JN |
2927 | kfree(devdata); |
2928 | } | |
2929 | ||
e163cfb4 VS |
2930 | list_for_each_entry_safe(entry, ne, &i915->vbt.bdb_blocks, node) { |
2931 | list_del(&entry->node); | |
2932 | kfree(entry); | |
2933 | } | |
2934 | ||
dbd440d8 JN |
2935 | kfree(i915->vbt.sdvo_lvds_vbt_mode); |
2936 | i915->vbt.sdvo_lvds_vbt_mode = NULL; | |
2937 | kfree(i915->vbt.lfp_lvds_vbt_mode); | |
2938 | i915->vbt.lfp_lvds_vbt_mode = NULL; | |
2939 | kfree(i915->vbt.dsi.data); | |
2940 | i915->vbt.dsi.data = NULL; | |
2941 | kfree(i915->vbt.dsi.pps); | |
2942 | i915->vbt.dsi.pps = NULL; | |
2943 | kfree(i915->vbt.dsi.config); | |
2944 | i915->vbt.dsi.config = NULL; | |
2945 | kfree(i915->vbt.dsi.deassert_seq); | |
2946 | i915->vbt.dsi.deassert_seq = NULL; | |
785f076b HG |
2947 | } |
2948 | ||
3bdd14d5 JN |
2949 | /** |
2950 | * intel_bios_is_tv_present - is integrated TV present in VBT | |
dbd440d8 | 2951 | * @i915: i915 device instance |
3bdd14d5 JN |
2952 | * |
2953 | * Return true if TV is present. If no child devices were parsed from VBT, | |
2954 | * assume TV is present. | |
2955 | */ | |
dbd440d8 | 2956 | bool intel_bios_is_tv_present(struct drm_i915_private *i915) |
3bdd14d5 | 2957 | { |
3162d057 | 2958 | const struct intel_bios_encoder_data *devdata; |
cc998589 | 2959 | const struct child_device_config *child; |
3bdd14d5 | 2960 | |
dbd440d8 | 2961 | if (!i915->vbt.int_tv_support) |
3bdd14d5 JN |
2962 | return false; |
2963 | ||
dbd440d8 | 2964 | if (list_empty(&i915->vbt.display_devices)) |
3bdd14d5 JN |
2965 | return true; |
2966 | ||
dbd440d8 | 2967 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { |
0d9ef19b JN |
2968 | child = &devdata->child; |
2969 | ||
3bdd14d5 JN |
2970 | /* |
2971 | * If the device type is not TV, continue. | |
2972 | */ | |
cc998589 | 2973 | switch (child->device_type) { |
3bdd14d5 JN |
2974 | case DEVICE_TYPE_INT_TV: |
2975 | case DEVICE_TYPE_TV: | |
2976 | case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: | |
2977 | break; | |
2978 | default: | |
2979 | continue; | |
2980 | } | |
2981 | /* Only when the addin_offset is non-zero, it is regarded | |
2982 | * as present. | |
2983 | */ | |
cc998589 | 2984 | if (child->addin_offset) |
3bdd14d5 JN |
2985 | return true; |
2986 | } | |
2987 | ||
2988 | return false; | |
2989 | } | |
5a69d13d JN |
2990 | |
2991 | /** | |
2992 | * intel_bios_is_lvds_present - is LVDS present in VBT | |
dbd440d8 | 2993 | * @i915: i915 device instance |
5a69d13d JN |
2994 | * @i2c_pin: i2c pin for LVDS if present |
2995 | * | |
2996 | * Return true if LVDS is present. If no child devices were parsed from VBT, | |
2997 | * assume LVDS is present. | |
2998 | */ | |
dbd440d8 | 2999 | bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin) |
5a69d13d | 3000 | { |
3162d057 | 3001 | const struct intel_bios_encoder_data *devdata; |
cc998589 | 3002 | const struct child_device_config *child; |
5a69d13d | 3003 | |
dbd440d8 | 3004 | if (list_empty(&i915->vbt.display_devices)) |
5a69d13d JN |
3005 | return true; |
3006 | ||
dbd440d8 | 3007 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { |
0d9ef19b | 3008 | child = &devdata->child; |
5a69d13d JN |
3009 | |
3010 | /* If the device type is not LFP, continue. | |
3011 | * We have to check both the new identifiers as well as the | |
3012 | * old for compatibility with some BIOSes. | |
3013 | */ | |
3014 | if (child->device_type != DEVICE_TYPE_INT_LFP && | |
3015 | child->device_type != DEVICE_TYPE_LFP) | |
3016 | continue; | |
3017 | ||
dbd440d8 | 3018 | if (intel_gmbus_is_valid_pin(i915, child->i2c_pin)) |
5a69d13d JN |
3019 | *i2c_pin = child->i2c_pin; |
3020 | ||
3021 | /* However, we cannot trust the BIOS writers to populate | |
3022 | * the VBT correctly. Since LVDS requires additional | |
3023 | * information from AIM blocks, a non-zero addin offset is | |
3024 | * a good indicator that the LVDS is actually present. | |
3025 | */ | |
3026 | if (child->addin_offset) | |
3027 | return true; | |
3028 | ||
3029 | /* But even then some BIOS writers perform some black magic | |
3030 | * and instantiate the device without reference to any | |
3031 | * additional data. Trust that if the VBT was written into | |
3032 | * the OpRegion then they have validated the LVDS's existence. | |
3033 | */ | |
dbd440d8 | 3034 | if (i915->opregion.vbt) |
5a69d13d JN |
3035 | return true; |
3036 | } | |
3037 | ||
3038 | return false; | |
3039 | } | |
951d9efe | 3040 | |
22f35042 VS |
3041 | /** |
3042 | * intel_bios_is_port_present - is the specified digital port present | |
dbd440d8 | 3043 | * @i915: i915 device instance |
22f35042 VS |
3044 | * @port: port to check |
3045 | * | |
3046 | * Return true if the device in %port is present. | |
3047 | */ | |
dbd440d8 | 3048 | bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port) |
22f35042 | 3049 | { |
a868a1e5 VS |
3050 | if (WARN_ON(!has_ddi_port_info(i915))) |
3051 | return true; | |
22f35042 | 3052 | |
a868a1e5 | 3053 | return i915->vbt.ports[port]; |
22f35042 VS |
3054 | } |
3055 | ||
951d9efe JN |
3056 | /** |
3057 | * intel_bios_is_port_edp - is the device in given port eDP | |
dbd440d8 | 3058 | * @i915: i915 device instance |
951d9efe JN |
3059 | * @port: port to check |
3060 | * | |
3061 | * Return true if the device in %port is eDP. | |
3062 | */ | |
dbd440d8 | 3063 | bool intel_bios_is_port_edp(struct drm_i915_private *i915, enum port port) |
951d9efe | 3064 | { |
a868a1e5 VS |
3065 | const struct intel_bios_encoder_data *devdata = |
3066 | intel_bios_encoder_data_lookup(i915, port); | |
a98d9c1d | 3067 | |
a868a1e5 | 3068 | return devdata && intel_bios_encoder_supports_edp(devdata); |
951d9efe | 3069 | } |
7137aec1 | 3070 | |
044cbc7a | 3071 | static bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata) |
d6199256 | 3072 | { |
044cbc7a VS |
3073 | const struct child_device_config *child = &devdata->child; |
3074 | ||
3075 | if (!intel_bios_encoder_supports_dp(devdata) || | |
3076 | !intel_bios_encoder_supports_hdmi(devdata)) | |
d6199256 VS |
3077 | return false; |
3078 | ||
32c2bc89 | 3079 | if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA) |
7a17995a VS |
3080 | return true; |
3081 | ||
3082 | /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ | |
32c2bc89 | 3083 | if (dvo_port_type(child->dvo_port) == DVO_PORT_HDMIA && |
cc998589 | 3084 | child->aux_channel != 0) |
7a17995a VS |
3085 | return true; |
3086 | ||
3087 | return false; | |
3088 | } | |
3089 | ||
dbd440d8 | 3090 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *i915, |
7a17995a VS |
3091 | enum port port) |
3092 | { | |
a868a1e5 VS |
3093 | const struct intel_bios_encoder_data *devdata = |
3094 | intel_bios_encoder_data_lookup(i915, port); | |
7a17995a | 3095 | |
044cbc7a | 3096 | return devdata && intel_bios_encoder_supports_dp_dual_mode(devdata); |
d6199256 VS |
3097 | } |
3098 | ||
7137aec1 JN |
3099 | /** |
3100 | * intel_bios_is_dsi_present - is DSI present in VBT | |
dbd440d8 | 3101 | * @i915: i915 device instance |
7137aec1 JN |
3102 | * @port: port for DSI if present |
3103 | * | |
3104 | * Return true if DSI is present, and return the port in %port. | |
3105 | */ | |
dbd440d8 | 3106 | bool intel_bios_is_dsi_present(struct drm_i915_private *i915, |
7137aec1 JN |
3107 | enum port *port) |
3108 | { | |
3162d057 | 3109 | const struct intel_bios_encoder_data *devdata; |
cc998589 | 3110 | const struct child_device_config *child; |
7137aec1 | 3111 | u8 dvo_port; |
7137aec1 | 3112 | |
dbd440d8 | 3113 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { |
0d9ef19b | 3114 | child = &devdata->child; |
7137aec1 | 3115 | |
cc998589 | 3116 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) |
7137aec1 JN |
3117 | continue; |
3118 | ||
cc998589 | 3119 | dvo_port = child->dvo_port; |
7137aec1 | 3120 | |
bf4d57ff | 3121 | if (dvo_port == DVO_PORT_MIPIA || |
005e9537 MR |
3122 | (dvo_port == DVO_PORT_MIPIB && DISPLAY_VER(i915) >= 11) || |
3123 | (dvo_port == DVO_PORT_MIPIC && DISPLAY_VER(i915) < 11)) { | |
7caaef33 JN |
3124 | if (port) |
3125 | *port = dvo_port - DVO_PORT_MIPIA; | |
7137aec1 | 3126 | return true; |
bf4d57ff MC |
3127 | } else if (dvo_port == DVO_PORT_MIPIB || |
3128 | dvo_port == DVO_PORT_MIPIC || | |
3129 | dvo_port == DVO_PORT_MIPID) { | |
dbd440d8 | 3130 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
3131 | "VBT has unsupported DSI port %c\n", |
3132 | port_name(dvo_port - DVO_PORT_MIPIA)); | |
7137aec1 JN |
3133 | } |
3134 | } | |
3135 | ||
3136 | return false; | |
3137 | } | |
d252bf68 | 3138 | |
1bf2f3bf JN |
3139 | static void fill_dsc(struct intel_crtc_state *crtc_state, |
3140 | struct dsc_compression_parameters_entry *dsc, | |
3141 | int dsc_max_bpc) | |
3142 | { | |
3143 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; | |
3144 | int bpc = 8; | |
3145 | ||
3146 | vdsc_cfg->dsc_version_major = dsc->version_major; | |
3147 | vdsc_cfg->dsc_version_minor = dsc->version_minor; | |
3148 | ||
3149 | if (dsc->support_12bpc && dsc_max_bpc >= 12) | |
3150 | bpc = 12; | |
3151 | else if (dsc->support_10bpc && dsc_max_bpc >= 10) | |
3152 | bpc = 10; | |
3153 | else if (dsc->support_8bpc && dsc_max_bpc >= 8) | |
3154 | bpc = 8; | |
3155 | else | |
3156 | DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n", | |
3157 | dsc_max_bpc); | |
3158 | ||
3159 | crtc_state->pipe_bpp = bpc * 3; | |
3160 | ||
3161 | crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, | |
3162 | VBT_DSC_MAX_BPP(dsc->max_bpp)); | |
3163 | ||
3164 | /* | |
3165 | * FIXME: This is ugly, and slice count should take DSC engine | |
3166 | * throughput etc. into account. | |
3167 | * | |
3168 | * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices. | |
3169 | */ | |
3170 | if (dsc->slices_per_line & BIT(2)) { | |
3171 | crtc_state->dsc.slice_count = 4; | |
3172 | } else if (dsc->slices_per_line & BIT(1)) { | |
3173 | crtc_state->dsc.slice_count = 2; | |
3174 | } else { | |
3175 | /* FIXME */ | |
3176 | if (!(dsc->slices_per_line & BIT(0))) | |
3177 | DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n"); | |
3178 | ||
3179 | crtc_state->dsc.slice_count = 1; | |
3180 | } | |
3181 | ||
3182 | if (crtc_state->hw.adjusted_mode.crtc_hdisplay % | |
3183 | crtc_state->dsc.slice_count != 0) | |
3184 | DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n", | |
3185 | crtc_state->hw.adjusted_mode.crtc_hdisplay, | |
3186 | crtc_state->dsc.slice_count); | |
3187 | ||
3188 | /* | |
1bf2f3bf | 3189 | * The VBT rc_buffer_block_size and rc_buffer_size definitions |
fd8a5b27 | 3190 | * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. |
1bf2f3bf | 3191 | */ |
fd8a5b27 JN |
3192 | vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, |
3193 | dsc->rc_buffer_size); | |
1bf2f3bf JN |
3194 | |
3195 | /* FIXME: DSI spec says bpc + 1 for this one */ | |
3196 | vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); | |
3197 | ||
3198 | vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; | |
3199 | ||
3200 | vdsc_cfg->slice_height = dsc->slice_height; | |
3201 | } | |
3202 | ||
3203 | /* FIXME: initially DSI specific */ | |
3204 | bool intel_bios_get_dsc_params(struct intel_encoder *encoder, | |
3205 | struct intel_crtc_state *crtc_state, | |
3206 | int dsc_max_bpc) | |
3207 | { | |
3208 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
3162d057 | 3209 | const struct intel_bios_encoder_data *devdata; |
1bf2f3bf JN |
3210 | const struct child_device_config *child; |
3211 | ||
3212 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { | |
3213 | child = &devdata->child; | |
3214 | ||
3215 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) | |
3216 | continue; | |
3217 | ||
3218 | if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) { | |
3219 | if (!devdata->dsc) | |
3220 | return false; | |
3221 | ||
3222 | if (crtc_state) | |
3223 | fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc); | |
3224 | ||
3225 | return true; | |
3226 | } | |
3227 | } | |
3228 | ||
3229 | return false; | |
3230 | } | |
3231 | ||
d252bf68 SS |
3232 | /** |
3233 | * intel_bios_is_port_hpd_inverted - is HPD inverted for %port | |
c72deaa4 | 3234 | * @i915: i915 device instance |
d252bf68 SS |
3235 | * @port: port to check |
3236 | * | |
3237 | * Return true if HPD should be inverted for %port. | |
3238 | */ | |
3239 | bool | |
c72deaa4 | 3240 | intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, |
d252bf68 SS |
3241 | enum port port) |
3242 | { | |
5a449e58 | 3243 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; |
d252bf68 | 3244 | |
2446e1d6 MR |
3245 | if (drm_WARN_ON_ONCE(&i915->drm, |
3246 | !IS_GEMINILAKE(i915) && !IS_BROXTON(i915))) | |
d252bf68 SS |
3247 | return false; |
3248 | ||
dbc13742 | 3249 | return devdata && devdata->child.hpd_invert; |
d252bf68 | 3250 | } |
6389dd83 SS |
3251 | |
3252 | /** | |
3253 | * intel_bios_is_lspcon_present - if LSPCON is attached on %port | |
a7475e5d | 3254 | * @i915: i915 device instance |
6389dd83 SS |
3255 | * @port: port to check |
3256 | * | |
3257 | * Return true if LSPCON is present on this port | |
3258 | */ | |
3259 | bool | |
a7475e5d JN |
3260 | intel_bios_is_lspcon_present(const struct drm_i915_private *i915, |
3261 | enum port port) | |
6389dd83 | 3262 | { |
5a449e58 | 3263 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; |
6389dd83 | 3264 | |
dbc13742 | 3265 | return HAS_LSPCON(i915) && devdata && devdata->child.lspcon; |
6389dd83 | 3266 | } |
15d248ae | 3267 | |
aaab24bb US |
3268 | /** |
3269 | * intel_bios_is_lane_reversal_needed - if lane reversal needed on port | |
3270 | * @i915: i915 device instance | |
3271 | * @port: port to check | |
3272 | * | |
3273 | * Return true if port requires lane reversal | |
3274 | */ | |
3275 | bool | |
3276 | intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915, | |
3277 | enum port port) | |
3278 | { | |
5a449e58 | 3279 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; |
aaab24bb | 3280 | |
dbc13742 | 3281 | return devdata && devdata->child.lane_reversal; |
aaab24bb US |
3282 | } |
3283 | ||
dbd440d8 | 3284 | enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915, |
39053089 | 3285 | enum port port) |
15d248ae | 3286 | { |
5a449e58 | 3287 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port]; |
15d248ae ID |
3288 | enum aux_ch aux_ch; |
3289 | ||
5a449e58 | 3290 | if (!devdata || !devdata->child.aux_channel) { |
15d248ae ID |
3291 | aux_ch = (enum aux_ch)port; |
3292 | ||
dbd440d8 | 3293 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
3294 | "using AUX %c for port %c (platform default)\n", |
3295 | aux_ch_name(aux_ch), port_name(port)); | |
15d248ae ID |
3296 | return aux_ch; |
3297 | } | |
3298 | ||
18c283df AS |
3299 | /* |
3300 | * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D | |
3301 | * map to DDI A,B,TC1,TC2 respectively. | |
3302 | * | |
3303 | * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E | |
3304 | * map to DDI A,TC1,TC2,TC3,TC4 respectively. | |
3305 | */ | |
5a449e58 | 3306 | switch (devdata->child.aux_channel) { |
15d248ae ID |
3307 | case DP_AUX_A: |
3308 | aux_ch = AUX_CH_A; | |
3309 | break; | |
3310 | case DP_AUX_B: | |
dbd440d8 | 3311 | if (IS_ALDERLAKE_S(i915)) |
18c283df AS |
3312 | aux_ch = AUX_CH_USBC1; |
3313 | else | |
3314 | aux_ch = AUX_CH_B; | |
15d248ae ID |
3315 | break; |
3316 | case DP_AUX_C: | |
dbd440d8 | 3317 | if (IS_ALDERLAKE_S(i915)) |
18c283df | 3318 | aux_ch = AUX_CH_USBC2; |
dbd440d8 | 3319 | else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) |
18c283df AS |
3320 | aux_ch = AUX_CH_USBC1; |
3321 | else | |
3322 | aux_ch = AUX_CH_C; | |
15d248ae ID |
3323 | break; |
3324 | case DP_AUX_D: | |
ed2615a8 MR |
3325 | if (DISPLAY_VER(i915) == 13) |
3326 | aux_ch = AUX_CH_D_XELPD; | |
3327 | else if (IS_ALDERLAKE_S(i915)) | |
18c283df | 3328 | aux_ch = AUX_CH_USBC3; |
dbd440d8 | 3329 | else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) |
18c283df AS |
3330 | aux_ch = AUX_CH_USBC2; |
3331 | else | |
3332 | aux_ch = AUX_CH_D; | |
15d248ae ID |
3333 | break; |
3334 | case DP_AUX_E: | |
ed2615a8 MR |
3335 | if (DISPLAY_VER(i915) == 13) |
3336 | aux_ch = AUX_CH_E_XELPD; | |
3337 | else if (IS_ALDERLAKE_S(i915)) | |
18c283df AS |
3338 | aux_ch = AUX_CH_USBC4; |
3339 | else | |
3340 | aux_ch = AUX_CH_E; | |
15d248ae ID |
3341 | break; |
3342 | case DP_AUX_F: | |
ed2615a8 MR |
3343 | if (DISPLAY_VER(i915) == 13) |
3344 | aux_ch = AUX_CH_USBC1; | |
3345 | else | |
3346 | aux_ch = AUX_CH_F; | |
15d248ae | 3347 | break; |
eb8de23c | 3348 | case DP_AUX_G: |
ed2615a8 MR |
3349 | if (DISPLAY_VER(i915) == 13) |
3350 | aux_ch = AUX_CH_USBC2; | |
3351 | else | |
3352 | aux_ch = AUX_CH_G; | |
eb8de23c | 3353 | break; |
5bf22ee4 | 3354 | case DP_AUX_H: |
ed2615a8 MR |
3355 | if (DISPLAY_VER(i915) == 13) |
3356 | aux_ch = AUX_CH_USBC3; | |
3357 | else | |
3358 | aux_ch = AUX_CH_H; | |
5bf22ee4 VS |
3359 | break; |
3360 | case DP_AUX_I: | |
ed2615a8 MR |
3361 | if (DISPLAY_VER(i915) == 13) |
3362 | aux_ch = AUX_CH_USBC4; | |
3363 | else | |
3364 | aux_ch = AUX_CH_I; | |
5bf22ee4 | 3365 | break; |
15d248ae | 3366 | default: |
5a449e58 | 3367 | MISSING_CASE(devdata->child.aux_channel); |
15d248ae ID |
3368 | aux_ch = AUX_CH_A; |
3369 | break; | |
3370 | } | |
3371 | ||
dbd440d8 | 3372 | drm_dbg_kms(&i915->drm, "using AUX %c for port %c (VBT)\n", |
e92cbf38 | 3373 | aux_ch_name(aux_ch), port_name(port)); |
15d248ae ID |
3374 | |
3375 | return aux_ch; | |
3376 | } | |
d9ee2111 JN |
3377 | |
3378 | int intel_bios_max_tmds_clock(struct intel_encoder *encoder) | |
3379 | { | |
3380 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
5a449e58 | 3381 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; |
d9ee2111 | 3382 | |
6ba69981 | 3383 | return _intel_bios_max_tmds_clock(devdata); |
d9ee2111 | 3384 | } |
0aed3bde | 3385 | |
a9a56e76 | 3386 | /* This is an index in the HDMI/DVI DDI buffer translation table, or -1 */ |
0aed3bde JN |
3387 | int intel_bios_hdmi_level_shift(struct intel_encoder *encoder) |
3388 | { | |
3389 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
5a449e58 | 3390 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; |
0aed3bde | 3391 | |
a9a56e76 | 3392 | return _intel_bios_hdmi_level_shift(devdata); |
0aed3bde | 3393 | } |
605a1872 | 3394 | |
c0a950d1 | 3395 | int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata) |
605a1872 | 3396 | { |
c0a950d1 JN |
3397 | if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost) |
3398 | return 0; | |
605a1872 | 3399 | |
c0a950d1 | 3400 | return translate_iboost(devdata->child.dp_iboost_level); |
605a1872 | 3401 | } |
01a60883 | 3402 | |
c0a950d1 | 3403 | int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata) |
01a60883 | 3404 | { |
c0a950d1 JN |
3405 | if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost) |
3406 | return 0; | |
01a60883 | 3407 | |
c0a950d1 | 3408 | return translate_iboost(devdata->child.hdmi_iboost_level); |
01a60883 | 3409 | } |
f83acdab JN |
3410 | |
3411 | int intel_bios_dp_max_link_rate(struct intel_encoder *encoder) | |
3412 | { | |
3413 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
5a449e58 | 3414 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; |
f83acdab | 3415 | |
72337aac | 3416 | return _intel_bios_dp_max_link_rate(devdata); |
f83acdab | 3417 | } |
17004bfb JN |
3418 | |
3419 | int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder) | |
3420 | { | |
3421 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
5a449e58 | 3422 | const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port]; |
dab8477b JN |
3423 | |
3424 | if (!devdata || !devdata->child.ddc_pin) | |
3425 | return 0; | |
17004bfb | 3426 | |
dab8477b | 3427 | return map_ddc_pin(i915, devdata->child.ddc_pin); |
17004bfb | 3428 | } |
c5faae5a | 3429 | |
f08fbe6a | 3430 | bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata) |
c5faae5a | 3431 | { |
f08fbe6a | 3432 | return devdata->i915->vbt.version >= 195 && devdata->child.dp_usb_type_c; |
c5faae5a JN |
3433 | } |
3434 | ||
f08fbe6a | 3435 | bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata) |
c5faae5a | 3436 | { |
f08fbe6a | 3437 | return devdata->i915->vbt.version >= 209 && devdata->child.tbt; |
c5faae5a | 3438 | } |
45c0673a JN |
3439 | |
3440 | const struct intel_bios_encoder_data * | |
3441 | intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port) | |
3442 | { | |
5a449e58 | 3443 | return i915->vbt.ports[port]; |
45c0673a | 3444 | } |