Commit | Line | Data |
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79e53945 | 1 | /* |
39507259 | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
b30581a4 | 27 | |
9f0e7ff4 | 28 | #include <drm/drm_dp_helper.h> |
760285e7 | 29 | #include <drm/i915_drm.h> |
3ce2ea65 | 30 | |
d8fe2ab6 | 31 | #include "display/intel_display.h" |
1bf2f3bf | 32 | #include "display/intel_display_types.h" |
379bc100 JN |
33 | #include "display/intel_gmbus.h" |
34 | ||
79e53945 | 35 | #include "i915_drv.h" |
72341af4 JN |
36 | |
37 | #define _INTEL_BIOS_PRIVATE | |
38 | #include "intel_vbt_defs.h" | |
79e53945 | 39 | |
dd97950a JN |
40 | /** |
41 | * DOC: Video BIOS Table (VBT) | |
42 | * | |
43 | * The Video BIOS Table, or VBT, provides platform and board specific | |
44 | * configuration information to the driver that is not discoverable or available | |
45 | * through other means. The configuration is mostly related to display | |
46 | * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in | |
47 | * the PCI ROM. | |
48 | * | |
49 | * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB | |
50 | * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that | |
51 | * contain the actual configuration information. The VBT Header, and thus the | |
52 | * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the | |
53 | * BDB Header. The data blocks are concatenated after the BDB Header. The data | |
54 | * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of | |
55 | * data. (Block 53, the MIPI Sequence Block is an exception.) | |
56 | * | |
57 | * The driver parses the VBT during load. The relevant information is stored in | |
58 | * driver private data for ease of use, and the actual VBT is not read after | |
59 | * that. | |
60 | */ | |
61 | ||
0d9ef19b JN |
62 | /* Wrapper for VBT child device config */ |
63 | struct display_device_data { | |
64 | struct child_device_config child; | |
6e0d46e9 | 65 | struct dsc_compression_parameters_entry *dsc; |
0d9ef19b JN |
66 | struct list_head node; |
67 | }; | |
68 | ||
9b9d172d | 69 | #define SLAVE_ADDR1 0x70 |
70 | #define SLAVE_ADDR2 0x72 | |
79e53945 | 71 | |
08c0888b JN |
72 | /* Get BDB block size given a pointer to Block ID. */ |
73 | static u32 _get_blocksize(const u8 *block_base) | |
74 | { | |
75 | /* The MIPI Sequence Block v3+ has a separate size field. */ | |
76 | if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) | |
77 | return *((const u32 *)(block_base + 4)); | |
78 | else | |
79 | return *((const u16 *)(block_base + 1)); | |
80 | } | |
81 | ||
82 | /* Get BDB block size give a pointer to data after Block ID and Block Size. */ | |
83 | static u32 get_blocksize(const void *block_data) | |
84 | { | |
85 | return _get_blocksize(block_data - 3); | |
86 | } | |
87 | ||
e8ef3b4c | 88 | static const void * |
f41c6153 | 89 | find_section(const void *_bdb, enum bdb_block_id section_id) |
79e53945 | 90 | { |
e8ef3b4c JN |
91 | const struct bdb_header *bdb = _bdb; |
92 | const u8 *base = _bdb; | |
79e53945 | 93 | int index = 0; |
cd67d226 | 94 | u32 total, current_size; |
f41c6153 | 95 | enum bdb_block_id current_id; |
79e53945 JB |
96 | |
97 | /* skip to first section */ | |
98 | index += bdb->header_size; | |
99 | total = bdb->bdb_size; | |
100 | ||
101 | /* walk the sections looking for section_id */ | |
d1f13fd2 | 102 | while (index + 3 < total) { |
79e53945 | 103 | current_id = *(base + index); |
08c0888b JN |
104 | current_size = _get_blocksize(base + index); |
105 | index += 3; | |
cd67d226 | 106 | |
d1f13fd2 CW |
107 | if (index + current_size > total) |
108 | return NULL; | |
109 | ||
79e53945 JB |
110 | if (current_id == section_id) |
111 | return base + index; | |
d1f13fd2 | 112 | |
79e53945 JB |
113 | index += current_size; |
114 | } | |
115 | ||
116 | return NULL; | |
117 | } | |
118 | ||
79e53945 | 119 | static void |
88631706 | 120 | fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, |
99834ea4 | 121 | const struct lvds_dvo_timing *dvo_timing) |
88631706 ML |
122 | { |
123 | panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | | |
124 | dvo_timing->hactive_lo; | |
125 | panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + | |
126 | ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); | |
127 | panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + | |
ce2e87b4 VT |
128 | ((dvo_timing->hsync_pulse_width_hi << 8) | |
129 | dvo_timing->hsync_pulse_width_lo); | |
88631706 ML |
130 | panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + |
131 | ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); | |
132 | ||
133 | panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | | |
134 | dvo_timing->vactive_lo; | |
135 | panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + | |
ce2e87b4 | 136 | ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo); |
88631706 | 137 | panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + |
ce2e87b4 VT |
138 | ((dvo_timing->vsync_pulse_width_hi << 4) | |
139 | dvo_timing->vsync_pulse_width_lo); | |
88631706 ML |
140 | panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + |
141 | ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); | |
142 | panel_fixed_mode->clock = dvo_timing->clock * 10; | |
143 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
144 | ||
9bc35499 AJ |
145 | if (dvo_timing->hsync_positive) |
146 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
147 | else | |
148 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
149 | ||
150 | if (dvo_timing->vsync_positive) | |
151 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
152 | else | |
153 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
154 | ||
df457245 VS |
155 | panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) | |
156 | dvo_timing->himage_lo; | |
157 | panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) | | |
158 | dvo_timing->vimage_lo; | |
159 | ||
88631706 ML |
160 | /* Some VBTs have bogus h/vtotal values */ |
161 | if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) | |
162 | panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; | |
163 | if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) | |
164 | panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; | |
165 | ||
166 | drm_mode_set_name(panel_fixed_mode); | |
167 | } | |
168 | ||
99834ea4 CW |
169 | static const struct lvds_dvo_timing * |
170 | get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data, | |
171 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs, | |
172 | int index) | |
173 | { | |
174 | /* | |
175 | * the size of fp_timing varies on the different platform. | |
176 | * So calculate the DVO timing relative offset in LVDS data | |
177 | * entry to get the DVO timing entry | |
178 | */ | |
179 | ||
180 | int lfp_data_size = | |
181 | lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset - | |
182 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset; | |
183 | int dvo_timing_offset = | |
184 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset - | |
185 | lvds_lfp_data_ptrs->ptr[0].fp_timing_offset; | |
186 | char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index; | |
187 | ||
188 | return (struct lvds_dvo_timing *)(entry + dvo_timing_offset); | |
189 | } | |
190 | ||
b0354385 TI |
191 | /* get lvds_fp_timing entry |
192 | * this function may return NULL if the corresponding entry is invalid | |
193 | */ | |
194 | static const struct lvds_fp_timing * | |
195 | get_lvds_fp_timing(const struct bdb_header *bdb, | |
196 | const struct bdb_lvds_lfp_data *data, | |
197 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
198 | int index) | |
199 | { | |
200 | size_t data_ofs = (const u8 *)data - (const u8 *)bdb; | |
201 | u16 data_size = ((const u16 *)data)[-1]; /* stored in header */ | |
202 | size_t ofs; | |
203 | ||
204 | if (index >= ARRAY_SIZE(ptrs->ptr)) | |
205 | return NULL; | |
206 | ofs = ptrs->ptr[index].fp_timing_offset; | |
207 | if (ofs < data_ofs || | |
208 | ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size) | |
209 | return NULL; | |
210 | return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs); | |
211 | } | |
212 | ||
9e7ecedf | 213 | /* Parse general panel options */ |
88631706 | 214 | static void |
9e7ecedf MR |
215 | parse_panel_options(struct drm_i915_private *dev_priv, |
216 | const struct bdb_header *bdb) | |
79e53945 | 217 | { |
99834ea4 | 218 | const struct bdb_lvds_options *lvds_options; |
3e845c7a | 219 | int panel_type; |
c329a4ec | 220 | int drrs_mode; |
a0562819 | 221 | int ret; |
79e53945 | 222 | |
79e53945 JB |
223 | lvds_options = find_section(bdb, BDB_LVDS_OPTIONS); |
224 | if (!lvds_options) | |
225 | return; | |
226 | ||
41aa3448 | 227 | dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; |
a0562819 | 228 | |
6f9f4b7a | 229 | ret = intel_opregion_get_panel_type(dev_priv); |
a0562819 VS |
230 | if (ret >= 0) { |
231 | WARN_ON(ret > 0xf); | |
232 | panel_type = ret; | |
e92cbf38 WK |
233 | drm_dbg_kms(&dev_priv->drm, "Panel type: %d (OpRegion)\n", |
234 | panel_type); | |
a0562819 VS |
235 | } else { |
236 | if (lvds_options->panel_type > 0xf) { | |
e92cbf38 WK |
237 | drm_dbg_kms(&dev_priv->drm, |
238 | "Invalid VBT panel type 0x%x\n", | |
239 | lvds_options->panel_type); | |
a0562819 VS |
240 | return; |
241 | } | |
242 | panel_type = lvds_options->panel_type; | |
e92cbf38 WK |
243 | drm_dbg_kms(&dev_priv->drm, "Panel type: %d (VBT)\n", |
244 | panel_type); | |
eeeebea6 | 245 | } |
6a04002b | 246 | |
3e845c7a | 247 | dev_priv->vbt.panel_type = panel_type; |
79e53945 | 248 | |
83a7280e PB |
249 | drrs_mode = (lvds_options->dps_panel_type_bits |
250 | >> (panel_type * 2)) & MODE_MASK; | |
251 | /* | |
252 | * VBT has static DRRS = 0 and seamless DRRS = 2. | |
253 | * The below piece of code is required to adjust vbt.drrs_type | |
254 | * to match the enum drrs_support_type. | |
255 | */ | |
256 | switch (drrs_mode) { | |
257 | case 0: | |
258 | dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; | |
e92cbf38 | 259 | drm_dbg_kms(&dev_priv->drm, "DRRS supported mode is static\n"); |
83a7280e PB |
260 | break; |
261 | case 2: | |
262 | dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; | |
e92cbf38 WK |
263 | drm_dbg_kms(&dev_priv->drm, |
264 | "DRRS supported mode is seamless\n"); | |
83a7280e PB |
265 | break; |
266 | default: | |
267 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
e92cbf38 WK |
268 | drm_dbg_kms(&dev_priv->drm, |
269 | "DRRS not supported (VBT input)\n"); | |
83a7280e PB |
270 | break; |
271 | } | |
9e7ecedf MR |
272 | } |
273 | ||
274 | /* Try to find integrated panel timing data */ | |
275 | static void | |
276 | parse_lfp_panel_dtd(struct drm_i915_private *dev_priv, | |
277 | const struct bdb_header *bdb) | |
278 | { | |
279 | const struct bdb_lvds_lfp_data *lvds_lfp_data; | |
280 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; | |
281 | const struct lvds_dvo_timing *panel_dvo_timing; | |
282 | const struct lvds_fp_timing *fp_timing; | |
283 | struct drm_display_mode *panel_fixed_mode; | |
284 | int panel_type = dev_priv->vbt.panel_type; | |
83a7280e | 285 | |
79e53945 JB |
286 | lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); |
287 | if (!lvds_lfp_data) | |
288 | return; | |
289 | ||
1b16de0b JB |
290 | lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS); |
291 | if (!lvds_lfp_data_ptrs) | |
292 | return; | |
293 | ||
99834ea4 CW |
294 | panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, |
295 | lvds_lfp_data_ptrs, | |
3e845c7a | 296 | panel_type); |
79e53945 | 297 | |
9a298b2a | 298 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
6edc3242 CW |
299 | if (!panel_fixed_mode) |
300 | return; | |
79e53945 | 301 | |
99834ea4 | 302 | fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); |
79e53945 | 303 | |
41aa3448 | 304 | dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 305 | |
e92cbf38 WK |
306 | drm_dbg_kms(&dev_priv->drm, |
307 | "Found panel mode in BIOS VBT legacy lfp table:\n"); | |
88631706 | 308 | drm_mode_debug_printmodeline(panel_fixed_mode); |
37df9673 | 309 | |
b0354385 TI |
310 | fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, |
311 | lvds_lfp_data_ptrs, | |
3e845c7a | 312 | panel_type); |
b0354385 TI |
313 | if (fp_timing) { |
314 | /* check the resolution, just to be sure */ | |
315 | if (fp_timing->x_res == panel_fixed_mode->hdisplay && | |
316 | fp_timing->y_res == panel_fixed_mode->vdisplay) { | |
41aa3448 | 317 | dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; |
e92cbf38 WK |
318 | drm_dbg_kms(&dev_priv->drm, |
319 | "VBT initial LVDS value %x\n", | |
320 | dev_priv->vbt.bios_lvds_val); | |
b0354385 TI |
321 | } |
322 | } | |
88631706 ML |
323 | } |
324 | ||
33ef6d4f MR |
325 | static void |
326 | parse_generic_dtd(struct drm_i915_private *dev_priv, | |
327 | const struct bdb_header *bdb) | |
328 | { | |
329 | const struct bdb_generic_dtd *generic_dtd; | |
330 | const struct generic_dtd_entry *dtd; | |
331 | struct drm_display_mode *panel_fixed_mode; | |
332 | int num_dtd; | |
333 | ||
334 | generic_dtd = find_section(bdb, BDB_GENERIC_DTD); | |
335 | if (!generic_dtd) | |
336 | return; | |
337 | ||
338 | if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) { | |
e92cbf38 WK |
339 | drm_err(&dev_priv->drm, "GDTD size %u is too small.\n", |
340 | generic_dtd->gdtd_size); | |
33ef6d4f MR |
341 | return; |
342 | } else if (generic_dtd->gdtd_size != | |
343 | sizeof(struct generic_dtd_entry)) { | |
e92cbf38 WK |
344 | drm_err(&dev_priv->drm, "Unexpected GDTD size %u\n", |
345 | generic_dtd->gdtd_size); | |
33ef6d4f MR |
346 | /* DTD has unknown fields, but keep going */ |
347 | } | |
348 | ||
349 | num_dtd = (get_blocksize(generic_dtd) - | |
350 | sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size; | |
8c8a854d | 351 | if (dev_priv->vbt.panel_type >= num_dtd) { |
e92cbf38 WK |
352 | drm_err(&dev_priv->drm, |
353 | "Panel type %d not found in table of %d DTD's\n", | |
354 | dev_priv->vbt.panel_type, num_dtd); | |
33ef6d4f MR |
355 | return; |
356 | } | |
357 | ||
358 | dtd = &generic_dtd->dtd[dev_priv->vbt.panel_type]; | |
359 | ||
360 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); | |
361 | if (!panel_fixed_mode) | |
362 | return; | |
363 | ||
364 | panel_fixed_mode->hdisplay = dtd->hactive; | |
365 | panel_fixed_mode->hsync_start = | |
366 | panel_fixed_mode->hdisplay + dtd->hfront_porch; | |
367 | panel_fixed_mode->hsync_end = | |
368 | panel_fixed_mode->hsync_start + dtd->hsync; | |
ad278f35 VK |
369 | panel_fixed_mode->htotal = |
370 | panel_fixed_mode->hdisplay + dtd->hblank; | |
33ef6d4f MR |
371 | |
372 | panel_fixed_mode->vdisplay = dtd->vactive; | |
373 | panel_fixed_mode->vsync_start = | |
374 | panel_fixed_mode->vdisplay + dtd->vfront_porch; | |
375 | panel_fixed_mode->vsync_end = | |
376 | panel_fixed_mode->vsync_start + dtd->vsync; | |
ad278f35 VK |
377 | panel_fixed_mode->vtotal = |
378 | panel_fixed_mode->vdisplay + dtd->vblank; | |
33ef6d4f MR |
379 | |
380 | panel_fixed_mode->clock = dtd->pixel_clock; | |
381 | panel_fixed_mode->width_mm = dtd->width_mm; | |
382 | panel_fixed_mode->height_mm = dtd->height_mm; | |
383 | ||
384 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
385 | drm_mode_set_name(panel_fixed_mode); | |
386 | ||
387 | if (dtd->hsync_positive_polarity) | |
388 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
389 | else | |
390 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
391 | ||
392 | if (dtd->vsync_positive_polarity) | |
393 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
394 | else | |
395 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
396 | ||
e92cbf38 WK |
397 | drm_dbg_kms(&dev_priv->drm, |
398 | "Found panel mode in BIOS VBT generic dtd table:\n"); | |
33ef6d4f MR |
399 | drm_mode_debug_printmodeline(panel_fixed_mode); |
400 | ||
401 | dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; | |
402 | } | |
403 | ||
404 | static void | |
405 | parse_panel_dtd(struct drm_i915_private *dev_priv, | |
406 | const struct bdb_header *bdb) | |
407 | { | |
408 | /* | |
409 | * Older VBTs provided provided DTD information for internal displays | |
410 | * through the "LFP panel DTD" block (42). As of VBT revision 229, | |
411 | * that block is now deprecated and DTD information should be provided | |
412 | * via a newer "generic DTD" block (58). Just to be safe, we'll | |
413 | * try the new generic DTD block first on VBT >= 229, but still fall | |
414 | * back to trying the old LFP block if that fails. | |
415 | */ | |
416 | if (bdb->version >= 229) | |
417 | parse_generic_dtd(dev_priv, bdb); | |
418 | if (!dev_priv->vbt.lfp_lvds_vbt_mode) | |
419 | parse_lfp_panel_dtd(dev_priv, bdb); | |
420 | } | |
421 | ||
f00076d2 | 422 | static void |
dcb58a40 JN |
423 | parse_lfp_backlight(struct drm_i915_private *dev_priv, |
424 | const struct bdb_header *bdb) | |
f00076d2 JN |
425 | { |
426 | const struct bdb_lfp_backlight_data *backlight_data; | |
f87f6599 | 427 | const struct lfp_backlight_data_entry *entry; |
3e845c7a | 428 | int panel_type = dev_priv->vbt.panel_type; |
f00076d2 JN |
429 | |
430 | backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); | |
431 | if (!backlight_data) | |
432 | return; | |
433 | ||
434 | if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { | |
e92cbf38 WK |
435 | drm_dbg_kms(&dev_priv->drm, |
436 | "Unsupported backlight data entry size %u\n", | |
437 | backlight_data->entry_size); | |
f00076d2 JN |
438 | return; |
439 | } | |
440 | ||
441 | entry = &backlight_data->data[panel_type]; | |
442 | ||
39fbc9c8 JN |
443 | dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; |
444 | if (!dev_priv->vbt.backlight.present) { | |
e92cbf38 WK |
445 | drm_dbg_kms(&dev_priv->drm, |
446 | "PWM backlight not present in VBT (type %u)\n", | |
447 | entry->type); | |
39fbc9c8 JN |
448 | return; |
449 | } | |
450 | ||
9a41e17d D |
451 | dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; |
452 | if (bdb->version >= 191 && | |
453 | get_blocksize(backlight_data) >= sizeof(*backlight_data)) { | |
f87f6599 | 454 | const struct lfp_backlight_control_method *method; |
9a41e17d D |
455 | |
456 | method = &backlight_data->backlight_control[panel_type]; | |
457 | dev_priv->vbt.backlight.type = method->type; | |
add03379 | 458 | dev_priv->vbt.backlight.controller = method->controller; |
9a41e17d D |
459 | } |
460 | ||
f00076d2 JN |
461 | dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; |
462 | dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm; | |
1de6068e | 463 | dev_priv->vbt.backlight.min_brightness = entry->min_brightness; |
e92cbf38 WK |
464 | drm_dbg_kms(&dev_priv->drm, |
465 | "VBT backlight PWM modulation frequency %u Hz, " | |
466 | "active %s, min brightness %u, level %u, controller %u\n", | |
467 | dev_priv->vbt.backlight.pwm_freq_hz, | |
468 | dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", | |
469 | dev_priv->vbt.backlight.min_brightness, | |
470 | backlight_data->level[panel_type], | |
471 | dev_priv->vbt.backlight.controller); | |
f00076d2 JN |
472 | } |
473 | ||
88631706 ML |
474 | /* Try to find sdvo panel data */ |
475 | static void | |
476 | parse_sdvo_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 477 | const struct bdb_header *bdb) |
88631706 | 478 | { |
f87f6599 | 479 | const struct bdb_sdvo_panel_dtds *dtds; |
88631706 | 480 | struct drm_display_mode *panel_fixed_mode; |
5a1e5b6c | 481 | int index; |
79e53945 | 482 | |
4f044a88 | 483 | index = i915_modparams.vbt_sdvo_panel_type; |
c10e408a | 484 | if (index == -2) { |
e92cbf38 WK |
485 | drm_dbg_kms(&dev_priv->drm, |
486 | "Ignore SDVO panel mode from BIOS VBT tables.\n"); | |
c10e408a MF |
487 | return; |
488 | } | |
489 | ||
5a1e5b6c | 490 | if (index == -1) { |
e8ef3b4c | 491 | const struct bdb_sdvo_lvds_options *sdvo_lvds_options; |
5a1e5b6c CW |
492 | |
493 | sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); | |
494 | if (!sdvo_lvds_options) | |
495 | return; | |
496 | ||
497 | index = sdvo_lvds_options->panel_type; | |
498 | } | |
88631706 | 499 | |
f87f6599 JN |
500 | dtds = find_section(bdb, BDB_SDVO_PANEL_DTDS); |
501 | if (!dtds) | |
88631706 ML |
502 | return; |
503 | ||
9a298b2a | 504 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
88631706 ML |
505 | if (!panel_fixed_mode) |
506 | return; | |
507 | ||
f87f6599 | 508 | fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]); |
88631706 | 509 | |
41aa3448 | 510 | dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 511 | |
e92cbf38 WK |
512 | drm_dbg_kms(&dev_priv->drm, |
513 | "Found SDVO panel mode in BIOS VBT tables:\n"); | |
5a1e5b6c | 514 | drm_mode_debug_printmodeline(panel_fixed_mode); |
79e53945 JB |
515 | } |
516 | ||
98f3a1dc | 517 | static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, |
9a4114ff BF |
518 | bool alternate) |
519 | { | |
c56b89f1 | 520 | switch (INTEL_GEN(dev_priv)) { |
9a4114ff | 521 | case 2: |
e91e941b | 522 | return alternate ? 66667 : 48000; |
9a4114ff BF |
523 | case 3: |
524 | case 4: | |
e91e941b | 525 | return alternate ? 100000 : 96000; |
9a4114ff | 526 | default: |
e91e941b | 527 | return alternate ? 100000 : 120000; |
9a4114ff BF |
528 | } |
529 | } | |
530 | ||
79e53945 JB |
531 | static void |
532 | parse_general_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 533 | const struct bdb_header *bdb) |
79e53945 | 534 | { |
e8ef3b4c | 535 | const struct bdb_general_features *general; |
79e53945 | 536 | |
79e53945 | 537 | general = find_section(bdb, BDB_GENERAL_FEATURES); |
34957e8c JN |
538 | if (!general) |
539 | return; | |
540 | ||
541 | dev_priv->vbt.int_tv_support = general->int_tv_support; | |
542 | /* int_crt_support can't be trusted on earlier platforms */ | |
543 | if (bdb->version >= 155 && | |
544 | (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv))) | |
545 | dev_priv->vbt.int_crt_support = general->int_crt_support; | |
546 | dev_priv->vbt.lvds_use_ssc = general->enable_ssc; | |
547 | dev_priv->vbt.lvds_ssc_freq = | |
548 | intel_bios_ssc_frequency(dev_priv, general->ssc_freq); | |
549 | dev_priv->vbt.display_clock_mode = general->display_clock_mode; | |
550 | dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; | |
c1cd5b24 VS |
551 | if (bdb->version >= 181) { |
552 | dev_priv->vbt.orientation = general->rotate_180 ? | |
553 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP : | |
554 | DRM_MODE_PANEL_ORIENTATION_NORMAL; | |
555 | } else { | |
556 | dev_priv->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; | |
557 | } | |
e92cbf38 WK |
558 | drm_dbg_kms(&dev_priv->drm, |
559 | "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", | |
560 | dev_priv->vbt.int_tv_support, | |
561 | dev_priv->vbt.int_crt_support, | |
562 | dev_priv->vbt.lvds_use_ssc, | |
563 | dev_priv->vbt.lvds_ssc_freq, | |
564 | dev_priv->vbt.display_clock_mode, | |
565 | dev_priv->vbt.fdi_rx_polarity_inverted); | |
79e53945 JB |
566 | } |
567 | ||
cc998589 | 568 | static const struct child_device_config * |
e192839e | 569 | child_device_ptr(const struct bdb_general_definitions *defs, int i) |
90e4f159 | 570 | { |
e192839e | 571 | return (const void *) &defs->devices[i * defs->child_dev_size]; |
90e4f159 VS |
572 | } |
573 | ||
9b9d172d | 574 | static void |
0ead5f81 | 575 | parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) |
9b9d172d | 576 | { |
e192839e | 577 | struct sdvo_device_mapping *mapping; |
0d9ef19b | 578 | const struct display_device_data *devdata; |
cc998589 | 579 | const struct child_device_config *child; |
0d9ef19b | 580 | int count = 0; |
6cc38aca JN |
581 | |
582 | /* | |
0ebdabe6 JN |
583 | * Only parse SDVO mappings on gens that could have SDVO. This isn't |
584 | * accurate and doesn't have to be, as long as it's not too strict. | |
9b9d172d | 585 | */ |
00690008 | 586 | if (!IS_GEN_RANGE(dev_priv, 3, 7)) { |
e92cbf38 | 587 | drm_dbg_kms(&dev_priv->drm, "Skipping SDVO device mapping\n"); |
9b9d172d | 588 | return; |
589 | } | |
0ebdabe6 | 590 | |
0d9ef19b JN |
591 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { |
592 | child = &devdata->child; | |
0ebdabe6 | 593 | |
6cc38aca JN |
594 | if (child->slave_addr != SLAVE_ADDR1 && |
595 | child->slave_addr != SLAVE_ADDR2) { | |
9b9d172d | 596 | /* |
597 | * If the slave address is neither 0x70 nor 0x72, | |
598 | * it is not a SDVO device. Skip it. | |
599 | */ | |
600 | continue; | |
601 | } | |
6cc38aca JN |
602 | if (child->dvo_port != DEVICE_PORT_DVOB && |
603 | child->dvo_port != DEVICE_PORT_DVOC) { | |
9b9d172d | 604 | /* skip the incorrect SDVO port */ |
e92cbf38 WK |
605 | drm_dbg_kms(&dev_priv->drm, |
606 | "Incorrect SDVO port. Skip it\n"); | |
9b9d172d | 607 | continue; |
608 | } | |
e92cbf38 WK |
609 | drm_dbg_kms(&dev_priv->drm, |
610 | "the SDVO device with slave addr %2x is found on" | |
611 | " %s port\n", | |
612 | child->slave_addr, | |
613 | (child->dvo_port == DEVICE_PORT_DVOB) ? | |
614 | "SDVOB" : "SDVOC"); | |
e192839e JN |
615 | mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; |
616 | if (!mapping->initialized) { | |
617 | mapping->dvo_port = child->dvo_port; | |
618 | mapping->slave_addr = child->slave_addr; | |
619 | mapping->dvo_wiring = child->dvo_wiring; | |
620 | mapping->ddc_pin = child->ddc_pin; | |
621 | mapping->i2c_pin = child->i2c_pin; | |
622 | mapping->initialized = 1; | |
e92cbf38 WK |
623 | drm_dbg_kms(&dev_priv->drm, |
624 | "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", | |
625 | mapping->dvo_port, mapping->slave_addr, | |
626 | mapping->dvo_wiring, mapping->ddc_pin, | |
627 | mapping->i2c_pin); | |
9b9d172d | 628 | } else { |
e92cbf38 WK |
629 | drm_dbg_kms(&dev_priv->drm, |
630 | "Maybe one SDVO port is shared by " | |
631 | "two SDVO device.\n"); | |
9b9d172d | 632 | } |
6cc38aca | 633 | if (child->slave2_addr) { |
9b9d172d | 634 | /* Maybe this is a SDVO device with multiple inputs */ |
635 | /* And the mapping info is not added */ | |
e92cbf38 WK |
636 | drm_dbg_kms(&dev_priv->drm, |
637 | "there exists the slave2_addr. Maybe this" | |
638 | " is a SDVO device with multiple inputs.\n"); | |
9b9d172d | 639 | } |
640 | count++; | |
641 | } | |
642 | ||
643 | if (!count) { | |
644 | /* No SDVO device info is found */ | |
e92cbf38 WK |
645 | drm_dbg_kms(&dev_priv->drm, |
646 | "No SDVO device info is found in VBT\n"); | |
9b9d172d | 647 | } |
9b9d172d | 648 | } |
32f9d658 ZW |
649 | |
650 | static void | |
651 | parse_driver_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 652 | const struct bdb_header *bdb) |
32f9d658 | 653 | { |
e8ef3b4c | 654 | const struct bdb_driver_features *driver; |
32f9d658 | 655 | |
32f9d658 | 656 | driver = find_section(bdb, BDB_DRIVER_FEATURES); |
652c393a JB |
657 | if (!driver) |
658 | return; | |
659 | ||
ca3b3fa3 VS |
660 | if (INTEL_GEN(dev_priv) >= 5) { |
661 | /* | |
662 | * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS | |
663 | * to mean "eDP". The VBT spec doesn't agree with that | |
664 | * interpretation, but real world VBTs seem to. | |
665 | */ | |
666 | if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) | |
667 | dev_priv->vbt.int_lvds_support = 0; | |
668 | } else { | |
669 | /* | |
670 | * FIXME it's not clear which BDB version has the LVDS config | |
671 | * bits defined. Revision history in the VBT spec says: | |
672 | * "0.92 | Add two definitions for VBT value of LVDS Active | |
673 | * Config (00b and 11b values defined) | 06/13/2005" | |
674 | * but does not the specify the BDB version. | |
675 | * | |
676 | * So far version 134 (on i945gm) is the oldest VBT observed | |
677 | * in the wild with the bits correctly populated. Version | |
678 | * 108 (on i85x) does not have the bits correctly populated. | |
679 | */ | |
680 | if (bdb->version >= 134 && | |
681 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && | |
682 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) | |
683 | dev_priv->vbt.int_lvds_support = 0; | |
684 | } | |
652c393a | 685 | |
551fb93d | 686 | if (bdb->version < 228) { |
e92cbf38 WK |
687 | drm_dbg_kms(&dev_priv->drm, "DRRS State Enabled:%d\n", |
688 | driver->drrs_enabled); | |
551fb93d JRS |
689 | /* |
690 | * If DRRS is not supported, drrs_type has to be set to 0. | |
691 | * This is because, VBT is configured in such a way that | |
692 | * static DRRS is 0 and DRRS not supported is represented by | |
693 | * driver->drrs_enabled=false | |
694 | */ | |
695 | if (!driver->drrs_enabled) | |
696 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
697 | ||
698 | dev_priv->vbt.psr.enable = driver->psr_enabled; | |
699 | } | |
700 | } | |
701 | ||
702 | static void | |
703 | parse_power_conservation_features(struct drm_i915_private *dev_priv, | |
704 | const struct bdb_header *bdb) | |
705 | { | |
706 | const struct bdb_lfp_power *power; | |
707 | u8 panel_type = dev_priv->vbt.panel_type; | |
708 | ||
709 | if (bdb->version < 228) | |
710 | return; | |
711 | ||
4ec5abe9 | 712 | power = find_section(bdb, BDB_LFP_POWER); |
551fb93d JRS |
713 | if (!power) |
714 | return; | |
715 | ||
716 | dev_priv->vbt.psr.enable = power->psr & BIT(panel_type); | |
717 | ||
83a7280e PB |
718 | /* |
719 | * If DRRS is not supported, drrs_type has to be set to 0. | |
720 | * This is because, VBT is configured in such a way that | |
721 | * static DRRS is 0 and DRRS not supported is represented by | |
551fb93d | 722 | * power->drrs & BIT(panel_type)=false |
83a7280e | 723 | */ |
551fb93d | 724 | if (!(power->drrs & BIT(panel_type))) |
83a7280e | 725 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; |
32f9d658 ZW |
726 | } |
727 | ||
500a8cc4 | 728 | static void |
dcb58a40 | 729 | parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
500a8cc4 | 730 | { |
e8ef3b4c JN |
731 | const struct bdb_edp *edp; |
732 | const struct edp_power_seq *edp_pps; | |
058727ee | 733 | const struct edp_fast_link_params *edp_link_params; |
3e845c7a | 734 | int panel_type = dev_priv->vbt.panel_type; |
500a8cc4 ZW |
735 | |
736 | edp = find_section(bdb, BDB_EDP); | |
5255e2f8 | 737 | if (!edp) |
500a8cc4 | 738 | return; |
500a8cc4 ZW |
739 | |
740 | switch ((edp->color_depth >> (panel_type * 2)) & 3) { | |
741 | case EDP_18BPP: | |
6aa23e65 | 742 | dev_priv->vbt.edp.bpp = 18; |
500a8cc4 ZW |
743 | break; |
744 | case EDP_24BPP: | |
6aa23e65 | 745 | dev_priv->vbt.edp.bpp = 24; |
500a8cc4 ZW |
746 | break; |
747 | case EDP_30BPP: | |
6aa23e65 | 748 | dev_priv->vbt.edp.bpp = 30; |
500a8cc4 ZW |
749 | break; |
750 | } | |
5ceb0f9b | 751 | |
9f0e7ff4 JB |
752 | /* Get the eDP sequencing and link info */ |
753 | edp_pps = &edp->power_seqs[panel_type]; | |
058727ee | 754 | edp_link_params = &edp->fast_link_params[panel_type]; |
5ceb0f9b | 755 | |
6aa23e65 | 756 | dev_priv->vbt.edp.pps = *edp_pps; |
5ceb0f9b | 757 | |
e13e2b2c JN |
758 | switch (edp_link_params->rate) { |
759 | case EDP_RATE_1_62: | |
6aa23e65 | 760 | dev_priv->vbt.edp.rate = DP_LINK_BW_1_62; |
e13e2b2c JN |
761 | break; |
762 | case EDP_RATE_2_7: | |
6aa23e65 | 763 | dev_priv->vbt.edp.rate = DP_LINK_BW_2_7; |
e13e2b2c JN |
764 | break; |
765 | default: | |
e92cbf38 WK |
766 | drm_dbg_kms(&dev_priv->drm, |
767 | "VBT has unknown eDP link rate value %u\n", | |
768 | edp_link_params->rate); | |
e13e2b2c JN |
769 | break; |
770 | } | |
771 | ||
9f0e7ff4 | 772 | switch (edp_link_params->lanes) { |
e13e2b2c | 773 | case EDP_LANE_1: |
6aa23e65 | 774 | dev_priv->vbt.edp.lanes = 1; |
9f0e7ff4 | 775 | break; |
e13e2b2c | 776 | case EDP_LANE_2: |
6aa23e65 | 777 | dev_priv->vbt.edp.lanes = 2; |
9f0e7ff4 | 778 | break; |
e13e2b2c | 779 | case EDP_LANE_4: |
6aa23e65 | 780 | dev_priv->vbt.edp.lanes = 4; |
9f0e7ff4 | 781 | break; |
e13e2b2c | 782 | default: |
e92cbf38 WK |
783 | drm_dbg_kms(&dev_priv->drm, |
784 | "VBT has unknown eDP lane count value %u\n", | |
785 | edp_link_params->lanes); | |
e13e2b2c | 786 | break; |
9f0e7ff4 | 787 | } |
e13e2b2c | 788 | |
9f0e7ff4 | 789 | switch (edp_link_params->preemphasis) { |
e13e2b2c | 790 | case EDP_PREEMPHASIS_NONE: |
6aa23e65 | 791 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; |
9f0e7ff4 | 792 | break; |
e13e2b2c | 793 | case EDP_PREEMPHASIS_3_5dB: |
6aa23e65 | 794 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; |
9f0e7ff4 | 795 | break; |
e13e2b2c | 796 | case EDP_PREEMPHASIS_6dB: |
6aa23e65 | 797 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; |
9f0e7ff4 | 798 | break; |
e13e2b2c | 799 | case EDP_PREEMPHASIS_9_5dB: |
6aa23e65 | 800 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; |
9f0e7ff4 | 801 | break; |
e13e2b2c | 802 | default: |
e92cbf38 WK |
803 | drm_dbg_kms(&dev_priv->drm, |
804 | "VBT has unknown eDP pre-emphasis value %u\n", | |
805 | edp_link_params->preemphasis); | |
e13e2b2c | 806 | break; |
9f0e7ff4 | 807 | } |
e13e2b2c | 808 | |
9f0e7ff4 | 809 | switch (edp_link_params->vswing) { |
e13e2b2c | 810 | case EDP_VSWING_0_4V: |
6aa23e65 | 811 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
9f0e7ff4 | 812 | break; |
e13e2b2c | 813 | case EDP_VSWING_0_6V: |
6aa23e65 | 814 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; |
9f0e7ff4 | 815 | break; |
e13e2b2c | 816 | case EDP_VSWING_0_8V: |
6aa23e65 | 817 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
9f0e7ff4 | 818 | break; |
e13e2b2c | 819 | case EDP_VSWING_1_2V: |
6aa23e65 | 820 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
9f0e7ff4 | 821 | break; |
e13e2b2c | 822 | default: |
e92cbf38 WK |
823 | drm_dbg_kms(&dev_priv->drm, |
824 | "VBT has unknown eDP voltage swing value %u\n", | |
825 | edp_link_params->vswing); | |
e13e2b2c | 826 | break; |
9f0e7ff4 | 827 | } |
9a57f5bb SJ |
828 | |
829 | if (bdb->version >= 173) { | |
0ede0141 | 830 | u8 vswing; |
9a57f5bb | 831 | |
9e458034 | 832 | /* Don't read from VBT if module parameter has valid value*/ |
4f044a88 MW |
833 | if (i915_modparams.edp_vswing) { |
834 | dev_priv->vbt.edp.low_vswing = | |
835 | i915_modparams.edp_vswing == 1; | |
9e458034 SJ |
836 | } else { |
837 | vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; | |
06411f08 | 838 | dev_priv->vbt.edp.low_vswing = vswing == 0; |
9e458034 | 839 | } |
9a57f5bb | 840 | } |
500a8cc4 ZW |
841 | } |
842 | ||
bfd7ebda | 843 | static void |
dcb58a40 | 844 | parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
bfd7ebda | 845 | { |
e8ef3b4c JN |
846 | const struct bdb_psr *psr; |
847 | const struct psr_table *psr_table; | |
3e845c7a | 848 | int panel_type = dev_priv->vbt.panel_type; |
bfd7ebda RV |
849 | |
850 | psr = find_section(bdb, BDB_PSR); | |
851 | if (!psr) { | |
e92cbf38 | 852 | drm_dbg_kms(&dev_priv->drm, "No PSR BDB found.\n"); |
bfd7ebda RV |
853 | return; |
854 | } | |
855 | ||
856 | psr_table = &psr->psr_table[panel_type]; | |
857 | ||
858 | dev_priv->vbt.psr.full_link = psr_table->full_link; | |
859 | dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; | |
860 | ||
861 | /* Allowed VBT values goes from 0 to 15 */ | |
862 | dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : | |
863 | psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; | |
864 | ||
865 | switch (psr_table->lines_to_wait) { | |
866 | case 0: | |
867 | dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; | |
868 | break; | |
869 | case 1: | |
870 | dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; | |
871 | break; | |
872 | case 2: | |
873 | dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; | |
874 | break; | |
875 | case 3: | |
876 | dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; | |
877 | break; | |
878 | default: | |
e92cbf38 WK |
879 | drm_dbg_kms(&dev_priv->drm, |
880 | "VBT has unknown PSR lines to wait %u\n", | |
881 | psr_table->lines_to_wait); | |
bfd7ebda RV |
882 | break; |
883 | } | |
884 | ||
77312ae8 VN |
885 | /* |
886 | * New psr options 0=500us, 1=100us, 2=2500us, 3=0us | |
887 | * Old decimal value is wake up time in multiples of 100 us. | |
888 | */ | |
0fdb3f75 VN |
889 | if (bdb->version >= 205 && |
890 | (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || | |
891 | INTEL_GEN(dev_priv) >= 10)) { | |
77312ae8 VN |
892 | switch (psr_table->tp1_wakeup_time) { |
893 | case 0: | |
894 | dev_priv->vbt.psr.tp1_wakeup_time_us = 500; | |
895 | break; | |
896 | case 1: | |
897 | dev_priv->vbt.psr.tp1_wakeup_time_us = 100; | |
898 | break; | |
899 | case 3: | |
900 | dev_priv->vbt.psr.tp1_wakeup_time_us = 0; | |
901 | break; | |
902 | default: | |
e92cbf38 WK |
903 | drm_dbg_kms(&dev_priv->drm, |
904 | "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", | |
905 | psr_table->tp1_wakeup_time); | |
77312ae8 VN |
906 | /* fallthrough */ |
907 | case 2: | |
908 | dev_priv->vbt.psr.tp1_wakeup_time_us = 2500; | |
909 | break; | |
910 | } | |
911 | ||
912 | switch (psr_table->tp2_tp3_wakeup_time) { | |
913 | case 0: | |
914 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500; | |
915 | break; | |
916 | case 1: | |
917 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100; | |
918 | break; | |
919 | case 3: | |
c238ad62 | 920 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0; |
77312ae8 VN |
921 | break; |
922 | default: | |
e92cbf38 WK |
923 | drm_dbg_kms(&dev_priv->drm, |
924 | "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", | |
925 | psr_table->tp2_tp3_wakeup_time); | |
77312ae8 VN |
926 | /* fallthrough */ |
927 | case 2: | |
928 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500; | |
929 | break; | |
930 | } | |
931 | } else { | |
932 | dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; | |
933 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; | |
934 | } | |
88a0d960 JRS |
935 | |
936 | if (bdb->version >= 226) { | |
b5ea9c93 | 937 | u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; |
88a0d960 JRS |
938 | |
939 | wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; | |
940 | switch (wakeup_time) { | |
941 | case 0: | |
942 | wakeup_time = 500; | |
943 | break; | |
944 | case 1: | |
945 | wakeup_time = 100; | |
946 | break; | |
947 | case 3: | |
948 | wakeup_time = 50; | |
949 | break; | |
950 | default: | |
951 | case 2: | |
952 | wakeup_time = 2500; | |
953 | break; | |
954 | } | |
955 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time; | |
956 | } else { | |
957 | /* Reusing PSR1 wakeup time for PSR2 in older VBTs */ | |
958 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us; | |
959 | } | |
bfd7ebda RV |
960 | } |
961 | ||
46e58320 MC |
962 | static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, |
963 | u16 version, enum port port) | |
964 | { | |
965 | if (!dev_priv->vbt.dsi.config->dual_link || version < 197) { | |
966 | dev_priv->vbt.dsi.bl_ports = BIT(port); | |
967 | if (dev_priv->vbt.dsi.config->cabc_supported) | |
968 | dev_priv->vbt.dsi.cabc_ports = BIT(port); | |
969 | ||
46e58320 MC |
970 | return; |
971 | } | |
972 | ||
973 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
974 | case DL_DCS_PORT_A: | |
975 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_A); | |
976 | break; | |
977 | case DL_DCS_PORT_C: | |
978 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_C); | |
979 | break; | |
980 | default: | |
981 | case DL_DCS_PORT_A_AND_C: | |
982 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); | |
983 | break; | |
984 | } | |
985 | ||
986 | if (!dev_priv->vbt.dsi.config->cabc_supported) | |
987 | return; | |
988 | ||
989 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
990 | case DL_DCS_PORT_A: | |
991 | dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A); | |
992 | break; | |
993 | case DL_DCS_PORT_C: | |
994 | dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C); | |
995 | break; | |
996 | default: | |
997 | case DL_DCS_PORT_A_AND_C: | |
998 | dev_priv->vbt.dsi.cabc_ports = | |
999 | BIT(PORT_A) | BIT(PORT_C); | |
1000 | break; | |
1001 | } | |
1002 | } | |
1003 | ||
d17c5443 | 1004 | static void |
0f8689f5 JN |
1005 | parse_mipi_config(struct drm_i915_private *dev_priv, |
1006 | const struct bdb_header *bdb) | |
d17c5443 | 1007 | { |
e8ef3b4c | 1008 | const struct bdb_mipi_config *start; |
e8ef3b4c JN |
1009 | const struct mipi_config *config; |
1010 | const struct mipi_pps_data *pps; | |
3e845c7a | 1011 | int panel_type = dev_priv->vbt.panel_type; |
46e58320 | 1012 | enum port port; |
d3b542fc | 1013 | |
3e6bd011 | 1014 | /* parse MIPI blocks only if LFP type is MIPI */ |
46e58320 | 1015 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
3e6bd011 SK |
1016 | return; |
1017 | ||
d3b542fc SK |
1018 | /* Initialize this to undefined indicating no generic MIPI support */ |
1019 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; | |
1020 | ||
1021 | /* Block #40 is already parsed and panel_fixed_mode is | |
1022 | * stored in dev_priv->lfp_lvds_vbt_mode | |
1023 | * resuse this when needed | |
1024 | */ | |
d17c5443 | 1025 | |
d3b542fc SK |
1026 | /* Parse #52 for panel index used from panel_type already |
1027 | * parsed | |
1028 | */ | |
1029 | start = find_section(bdb, BDB_MIPI_CONFIG); | |
1030 | if (!start) { | |
e92cbf38 | 1031 | drm_dbg_kms(&dev_priv->drm, "No MIPI config BDB found"); |
d17c5443 SK |
1032 | return; |
1033 | } | |
1034 | ||
e92cbf38 WK |
1035 | drm_dbg(&dev_priv->drm, "Found MIPI Config block, panel index = %d\n", |
1036 | panel_type); | |
d3b542fc SK |
1037 | |
1038 | /* | |
1039 | * get hold of the correct configuration block and pps data as per | |
1040 | * the panel_type as index | |
1041 | */ | |
1042 | config = &start->config[panel_type]; | |
1043 | pps = &start->pps[panel_type]; | |
1044 | ||
1045 | /* store as of now full data. Trim when we realise all is not needed */ | |
1046 | dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); | |
1047 | if (!dev_priv->vbt.dsi.config) | |
1048 | return; | |
1049 | ||
1050 | dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); | |
1051 | if (!dev_priv->vbt.dsi.pps) { | |
1052 | kfree(dev_priv->vbt.dsi.config); | |
1053 | return; | |
1054 | } | |
1055 | ||
46e58320 | 1056 | parse_dsi_backlight_ports(dev_priv, bdb->version, port); |
9f7c5b17 | 1057 | |
c1cd5b24 VS |
1058 | /* FIXME is the 90 vs. 270 correct? */ |
1059 | switch (config->rotation) { | |
1060 | case ENABLE_ROTATION_0: | |
1061 | /* | |
1062 | * Most (all?) VBTs claim 0 degrees despite having | |
1063 | * an upside down panel, thus we do not trust this. | |
1064 | */ | |
1065 | dev_priv->vbt.dsi.orientation = | |
1066 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN; | |
1067 | break; | |
1068 | case ENABLE_ROTATION_90: | |
1069 | dev_priv->vbt.dsi.orientation = | |
1070 | DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; | |
1071 | break; | |
1072 | case ENABLE_ROTATION_180: | |
1073 | dev_priv->vbt.dsi.orientation = | |
1074 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; | |
1075 | break; | |
1076 | case ENABLE_ROTATION_270: | |
1077 | dev_priv->vbt.dsi.orientation = | |
1078 | DRM_MODE_PANEL_ORIENTATION_LEFT_UP; | |
1079 | break; | |
1080 | } | |
1081 | ||
d3b542fc | 1082 | /* We have mandatory mipi config blocks. Initialize as generic panel */ |
ea9a6baf | 1083 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; |
0f8689f5 JN |
1084 | } |
1085 | ||
5db72099 JN |
1086 | /* Find the sequence block and size for the given panel. */ |
1087 | static const u8 * | |
1088 | find_panel_sequence_block(const struct bdb_mipi_sequence *sequence, | |
2a33d934 | 1089 | u16 panel_id, u32 *seq_size) |
5db72099 JN |
1090 | { |
1091 | u32 total = get_blocksize(sequence); | |
1092 | const u8 *data = &sequence->data[0]; | |
1093 | u8 current_id; | |
2a33d934 JN |
1094 | u32 current_size; |
1095 | int header_size = sequence->version >= 3 ? 5 : 3; | |
5db72099 JN |
1096 | int index = 0; |
1097 | int i; | |
1098 | ||
2a33d934 JN |
1099 | /* skip new block size */ |
1100 | if (sequence->version >= 3) | |
1101 | data += 4; | |
1102 | ||
1103 | for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { | |
1104 | if (index + header_size > total) { | |
1105 | DRM_ERROR("Invalid sequence block (header)\n"); | |
1106 | return NULL; | |
1107 | } | |
1108 | ||
5db72099 | 1109 | current_id = *(data + index); |
2a33d934 JN |
1110 | if (sequence->version >= 3) |
1111 | current_size = *((const u32 *)(data + index + 1)); | |
1112 | else | |
1113 | current_size = *((const u16 *)(data + index + 1)); | |
5db72099 | 1114 | |
2a33d934 | 1115 | index += header_size; |
5db72099 JN |
1116 | |
1117 | if (index + current_size > total) { | |
1118 | DRM_ERROR("Invalid sequence block\n"); | |
1119 | return NULL; | |
1120 | } | |
1121 | ||
1122 | if (current_id == panel_id) { | |
1123 | *seq_size = current_size; | |
1124 | return data + index; | |
1125 | } | |
1126 | ||
1127 | index += current_size; | |
1128 | } | |
1129 | ||
1130 | DRM_ERROR("Sequence block detected but no valid configuration\n"); | |
1131 | ||
1132 | return NULL; | |
1133 | } | |
1134 | ||
8d3ed2f3 JN |
1135 | static int goto_next_sequence(const u8 *data, int index, int total) |
1136 | { | |
1137 | u16 len; | |
1138 | ||
1139 | /* Skip Sequence Byte. */ | |
1140 | for (index = index + 1; index < total; index += len) { | |
1141 | u8 operation_byte = *(data + index); | |
1142 | index++; | |
1143 | ||
1144 | switch (operation_byte) { | |
1145 | case MIPI_SEQ_ELEM_END: | |
1146 | return index; | |
1147 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1148 | if (index + 4 > total) | |
1149 | return 0; | |
1150 | ||
1151 | len = *((const u16 *)(data + index + 2)) + 4; | |
1152 | break; | |
1153 | case MIPI_SEQ_ELEM_DELAY: | |
1154 | len = 4; | |
1155 | break; | |
1156 | case MIPI_SEQ_ELEM_GPIO: | |
1157 | len = 2; | |
1158 | break; | |
f4d64936 JN |
1159 | case MIPI_SEQ_ELEM_I2C: |
1160 | if (index + 7 > total) | |
1161 | return 0; | |
1162 | len = *(data + index + 6) + 7; | |
1163 | break; | |
8d3ed2f3 JN |
1164 | default: |
1165 | DRM_ERROR("Unknown operation byte\n"); | |
1166 | return 0; | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
2a33d934 JN |
1173 | static int goto_next_sequence_v3(const u8 *data, int index, int total) |
1174 | { | |
1175 | int seq_end; | |
1176 | u16 len; | |
6765bd6d | 1177 | u32 size_of_sequence; |
2a33d934 JN |
1178 | |
1179 | /* | |
1180 | * Could skip sequence based on Size of Sequence alone, but also do some | |
1181 | * checking on the structure. | |
1182 | */ | |
1183 | if (total < 5) { | |
1184 | DRM_ERROR("Too small sequence size\n"); | |
1185 | return 0; | |
1186 | } | |
1187 | ||
6765bd6d JN |
1188 | /* Skip Sequence Byte. */ |
1189 | index++; | |
1190 | ||
1191 | /* | |
1192 | * Size of Sequence. Excludes the Sequence Byte and the size itself, | |
1193 | * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END | |
1194 | * byte. | |
1195 | */ | |
0ede0141 | 1196 | size_of_sequence = *((const u32 *)(data + index)); |
6765bd6d JN |
1197 | index += 4; |
1198 | ||
1199 | seq_end = index + size_of_sequence; | |
2a33d934 JN |
1200 | if (seq_end > total) { |
1201 | DRM_ERROR("Invalid sequence size\n"); | |
1202 | return 0; | |
1203 | } | |
1204 | ||
6765bd6d | 1205 | for (; index < total; index += len) { |
2a33d934 JN |
1206 | u8 operation_byte = *(data + index); |
1207 | index++; | |
1208 | ||
1209 | if (operation_byte == MIPI_SEQ_ELEM_END) { | |
1210 | if (index != seq_end) { | |
1211 | DRM_ERROR("Invalid element structure\n"); | |
1212 | return 0; | |
1213 | } | |
1214 | return index; | |
1215 | } | |
1216 | ||
1217 | len = *(data + index); | |
1218 | index++; | |
1219 | ||
1220 | /* | |
1221 | * FIXME: Would be nice to check elements like for v1/v2 in | |
1222 | * goto_next_sequence() above. | |
1223 | */ | |
1224 | switch (operation_byte) { | |
1225 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1226 | case MIPI_SEQ_ELEM_DELAY: | |
1227 | case MIPI_SEQ_ELEM_GPIO: | |
1228 | case MIPI_SEQ_ELEM_I2C: | |
1229 | case MIPI_SEQ_ELEM_SPI: | |
1230 | case MIPI_SEQ_ELEM_PMIC: | |
1231 | break; | |
1232 | default: | |
1233 | DRM_ERROR("Unknown operation byte %u\n", | |
1234 | operation_byte); | |
1235 | break; | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1241 | ||
fb38e7ad HG |
1242 | /* |
1243 | * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, | |
1244 | * skip all delay + gpio operands and stop at the first DSI packet op. | |
1245 | */ | |
1246 | static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv) | |
1247 | { | |
1248 | const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
1249 | int index, len; | |
1250 | ||
1251 | if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1)) | |
1252 | return 0; | |
1253 | ||
1254 | /* index = 1 to skip sequence byte */ | |
1255 | for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { | |
1256 | switch (data[index]) { | |
1257 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1258 | return index == 1 ? 0 : index; | |
1259 | case MIPI_SEQ_ELEM_DELAY: | |
1260 | len = 5; /* 1 byte for operand + uint32 */ | |
1261 | break; | |
1262 | case MIPI_SEQ_ELEM_GPIO: | |
1263 | len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ | |
1264 | break; | |
1265 | default: | |
1266 | return 0; | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | /* | |
1274 | * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. | |
1275 | * The deassert must be done before calling intel_dsi_device_ready, so for | |
1276 | * these devices we split the init OTP sequence into a deassert sequence and | |
1277 | * the actual init OTP part. | |
1278 | */ | |
1279 | static void fixup_mipi_sequences(struct drm_i915_private *dev_priv) | |
1280 | { | |
1281 | u8 *init_otp; | |
1282 | int len; | |
1283 | ||
1284 | /* Limit this to VLV for now. */ | |
1285 | if (!IS_VALLEYVIEW(dev_priv)) | |
1286 | return; | |
1287 | ||
1288 | /* Limit this to v1 vid-mode sequences */ | |
1289 | if (dev_priv->vbt.dsi.config->is_cmd_mode || | |
1290 | dev_priv->vbt.dsi.seq_version != 1) | |
1291 | return; | |
1292 | ||
1293 | /* Only do this if there are otp and assert seqs and no deassert seq */ | |
1294 | if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || | |
1295 | !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || | |
1296 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) | |
1297 | return; | |
1298 | ||
1299 | /* The deassert-sequence ends at the first DSI packet */ | |
1300 | len = get_init_otp_deassert_fragment_len(dev_priv); | |
1301 | if (!len) | |
1302 | return; | |
1303 | ||
e92cbf38 WK |
1304 | drm_dbg_kms(&dev_priv->drm, |
1305 | "Using init OTP fragment to deassert reset\n"); | |
fb38e7ad HG |
1306 | |
1307 | /* Copy the fragment, update seq byte and terminate it */ | |
1308 | init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
1309 | dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); | |
1310 | if (!dev_priv->vbt.dsi.deassert_seq) | |
1311 | return; | |
1312 | dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; | |
1313 | dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; | |
1314 | /* Use the copy for deassert */ | |
1315 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = | |
1316 | dev_priv->vbt.dsi.deassert_seq; | |
1317 | /* Replace the last byte of the fragment with init OTP seq byte */ | |
1318 | init_otp[len - 1] = MIPI_SEQ_INIT_OTP; | |
1319 | /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ | |
1320 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; | |
1321 | } | |
1322 | ||
0f8689f5 JN |
1323 | static void |
1324 | parse_mipi_sequence(struct drm_i915_private *dev_priv, | |
1325 | const struct bdb_header *bdb) | |
1326 | { | |
3e845c7a | 1327 | int panel_type = dev_priv->vbt.panel_type; |
0f8689f5 JN |
1328 | const struct bdb_mipi_sequence *sequence; |
1329 | const u8 *seq_data; | |
2a33d934 | 1330 | u32 seq_size; |
0f8689f5 | 1331 | u8 *data; |
8d3ed2f3 | 1332 | int index = 0; |
0f8689f5 JN |
1333 | |
1334 | /* Only our generic panel driver uses the sequence block. */ | |
1335 | if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) | |
1336 | return; | |
d3b542fc | 1337 | |
d3b542fc SK |
1338 | sequence = find_section(bdb, BDB_MIPI_SEQUENCE); |
1339 | if (!sequence) { | |
e92cbf38 WK |
1340 | drm_dbg_kms(&dev_priv->drm, |
1341 | "No MIPI Sequence found, parsing complete\n"); | |
d3b542fc SK |
1342 | return; |
1343 | } | |
1344 | ||
cd67d226 | 1345 | /* Fail gracefully for forward incompatible sequence block. */ |
2a33d934 | 1346 | if (sequence->version >= 4) { |
e92cbf38 WK |
1347 | drm_err(&dev_priv->drm, |
1348 | "Unable to parse MIPI Sequence Block v%u\n", | |
1349 | sequence->version); | |
cd67d226 JN |
1350 | return; |
1351 | } | |
1352 | ||
e92cbf38 WK |
1353 | drm_dbg(&dev_priv->drm, "Found MIPI sequence block v%u\n", |
1354 | sequence->version); | |
d3b542fc | 1355 | |
5db72099 JN |
1356 | seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size); |
1357 | if (!seq_data) | |
d3b542fc | 1358 | return; |
d3b542fc | 1359 | |
8d3ed2f3 JN |
1360 | data = kmemdup(seq_data, seq_size, GFP_KERNEL); |
1361 | if (!data) | |
d3b542fc SK |
1362 | return; |
1363 | ||
8d3ed2f3 JN |
1364 | /* Parse the sequences, store pointers to each sequence. */ |
1365 | for (;;) { | |
1366 | u8 seq_id = *(data + index); | |
1367 | if (seq_id == MIPI_SEQ_END) | |
1368 | break; | |
d3b542fc | 1369 | |
8d3ed2f3 | 1370 | if (seq_id >= MIPI_SEQ_MAX) { |
e92cbf38 WK |
1371 | drm_err(&dev_priv->drm, "Unknown sequence %u\n", |
1372 | seq_id); | |
d3b542fc SK |
1373 | goto err; |
1374 | } | |
1375 | ||
4b4f497e JN |
1376 | /* Log about presence of sequences we won't run. */ |
1377 | if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) | |
e92cbf38 WK |
1378 | drm_dbg_kms(&dev_priv->drm, |
1379 | "Unsupported sequence %u\n", seq_id); | |
4b4f497e | 1380 | |
8d3ed2f3 | 1381 | dev_priv->vbt.dsi.sequence[seq_id] = data + index; |
d3b542fc | 1382 | |
2a33d934 JN |
1383 | if (sequence->version >= 3) |
1384 | index = goto_next_sequence_v3(data, index, seq_size); | |
1385 | else | |
1386 | index = goto_next_sequence(data, index, seq_size); | |
8d3ed2f3 | 1387 | if (!index) { |
e92cbf38 WK |
1388 | drm_err(&dev_priv->drm, "Invalid sequence %u\n", |
1389 | seq_id); | |
d3b542fc SK |
1390 | goto err; |
1391 | } | |
d3b542fc SK |
1392 | } |
1393 | ||
8d3ed2f3 JN |
1394 | dev_priv->vbt.dsi.data = data; |
1395 | dev_priv->vbt.dsi.size = seq_size; | |
1396 | dev_priv->vbt.dsi.seq_version = sequence->version; | |
1397 | ||
fb38e7ad HG |
1398 | fixup_mipi_sequences(dev_priv); |
1399 | ||
e92cbf38 | 1400 | drm_dbg(&dev_priv->drm, "MIPI related VBT parsing complete\n"); |
d3b542fc | 1401 | return; |
d3b542fc | 1402 | |
8d3ed2f3 JN |
1403 | err: |
1404 | kfree(data); | |
ed3b6679 | 1405 | memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence)); |
d17c5443 SK |
1406 | } |
1407 | ||
6e0d46e9 JN |
1408 | static void |
1409 | parse_compression_parameters(struct drm_i915_private *i915, | |
1410 | const struct bdb_header *bdb) | |
1411 | { | |
1412 | const struct bdb_compression_parameters *params; | |
1413 | struct display_device_data *devdata; | |
1414 | const struct child_device_config *child; | |
1415 | u16 block_size; | |
1416 | int index; | |
1417 | ||
1418 | if (bdb->version < 198) | |
1419 | return; | |
1420 | ||
1421 | params = find_section(bdb, BDB_COMPRESSION_PARAMETERS); | |
1422 | if (params) { | |
1423 | /* Sanity checks */ | |
1424 | if (params->entry_size != sizeof(params->data[0])) { | |
e92cbf38 WK |
1425 | drm_dbg_kms(&i915->drm, |
1426 | "VBT: unsupported compression param entry size\n"); | |
6e0d46e9 JN |
1427 | return; |
1428 | } | |
1429 | ||
1430 | block_size = get_blocksize(params); | |
1431 | if (block_size < sizeof(*params)) { | |
e92cbf38 WK |
1432 | drm_dbg_kms(&i915->drm, |
1433 | "VBT: expected 16 compression param entries\n"); | |
6e0d46e9 JN |
1434 | return; |
1435 | } | |
1436 | } | |
1437 | ||
1438 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { | |
1439 | child = &devdata->child; | |
1440 | ||
1441 | if (!child->compression_enable) | |
1442 | continue; | |
1443 | ||
1444 | if (!params) { | |
e92cbf38 WK |
1445 | drm_dbg_kms(&i915->drm, |
1446 | "VBT: compression params not available\n"); | |
6e0d46e9 JN |
1447 | continue; |
1448 | } | |
1449 | ||
1450 | if (child->compression_method_cps) { | |
e92cbf38 WK |
1451 | drm_dbg_kms(&i915->drm, |
1452 | "VBT: CPS compression not supported\n"); | |
6e0d46e9 JN |
1453 | continue; |
1454 | } | |
1455 | ||
1456 | index = child->compression_structure_index; | |
1457 | ||
1458 | devdata->dsc = kmemdup(¶ms->data[index], | |
1459 | sizeof(*devdata->dsc), GFP_KERNEL); | |
1460 | } | |
1461 | } | |
1462 | ||
75067dde AK |
1463 | static u8 translate_iboost(u8 val) |
1464 | { | |
1465 | static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ | |
1466 | ||
1467 | if (val >= ARRAY_SIZE(mapping)) { | |
1468 | DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); | |
1469 | return 0; | |
1470 | } | |
1471 | return mapping[val]; | |
1472 | } | |
1473 | ||
cc21f011 JN |
1474 | static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin) |
1475 | { | |
1476 | const struct ddi_vbt_port_info *info; | |
1477 | enum port port; | |
1478 | ||
c4a774c4 | 1479 | for_each_port(port) { |
cc21f011 JN |
1480 | info = &i915->vbt.ddi_port_info[port]; |
1481 | ||
1482 | if (info->child && ddc_pin == info->alternate_ddc_pin) | |
1483 | return port; | |
1484 | } | |
1485 | ||
1486 | return PORT_NONE; | |
1487 | } | |
1488 | ||
9454fa87 VS |
1489 | static void sanitize_ddc_pin(struct drm_i915_private *dev_priv, |
1490 | enum port port) | |
1491 | { | |
36a0f920 | 1492 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
9454fa87 VS |
1493 | enum port p; |
1494 | ||
1495 | if (!info->alternate_ddc_pin) | |
1496 | return; | |
1497 | ||
cc21f011 JN |
1498 | p = get_port_by_ddc_pin(dev_priv, info->alternate_ddc_pin); |
1499 | if (p != PORT_NONE) { | |
e92cbf38 WK |
1500 | drm_dbg_kms(&dev_priv->drm, |
1501 | "port %c trying to use the same DDC pin (0x%x) as port %c, " | |
1502 | "disabling port %c DVI/HDMI support\n", | |
1503 | port_name(port), info->alternate_ddc_pin, | |
1504 | port_name(p), port_name(p)); | |
9454fa87 VS |
1505 | |
1506 | /* | |
1507 | * If we have multiple ports supposedly sharing the | |
1508 | * pin, then dvi/hdmi couldn't exist on the shared | |
1509 | * port. Otherwise they share the same ddc bin and | |
1510 | * system couldn't communicate with them separately. | |
1511 | * | |
41e35ffb VS |
1512 | * Give inverse child device order the priority, |
1513 | * last one wins. Yes, there are real machines | |
1514 | * (eg. Asrock B250M-HDV) where VBT has both | |
1515 | * port A and port E with the same AUX ch and | |
1516 | * we must pick port E :( | |
9454fa87 | 1517 | */ |
41e35ffb VS |
1518 | info = &dev_priv->vbt.ddi_port_info[p]; |
1519 | ||
36a0f920 JN |
1520 | info->supports_dvi = false; |
1521 | info->supports_hdmi = false; | |
1522 | info->alternate_ddc_pin = 0; | |
9454fa87 VS |
1523 | } |
1524 | } | |
1525 | ||
cc21f011 JN |
1526 | static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch) |
1527 | { | |
1528 | const struct ddi_vbt_port_info *info; | |
1529 | enum port port; | |
1530 | ||
c4a774c4 | 1531 | for_each_port(port) { |
cc21f011 JN |
1532 | info = &i915->vbt.ddi_port_info[port]; |
1533 | ||
1534 | if (info->child && aux_ch == info->alternate_aux_channel) | |
1535 | return port; | |
1536 | } | |
1537 | ||
1538 | return PORT_NONE; | |
1539 | } | |
1540 | ||
9454fa87 VS |
1541 | static void sanitize_aux_ch(struct drm_i915_private *dev_priv, |
1542 | enum port port) | |
1543 | { | |
36a0f920 | 1544 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
9454fa87 VS |
1545 | enum port p; |
1546 | ||
1547 | if (!info->alternate_aux_channel) | |
1548 | return; | |
1549 | ||
cc21f011 JN |
1550 | p = get_port_by_aux_ch(dev_priv, info->alternate_aux_channel); |
1551 | if (p != PORT_NONE) { | |
e92cbf38 WK |
1552 | drm_dbg_kms(&dev_priv->drm, |
1553 | "port %c trying to use the same AUX CH (0x%x) as port %c, " | |
1554 | "disabling port %c DP support\n", | |
1555 | port_name(port), info->alternate_aux_channel, | |
1556 | port_name(p), port_name(p)); | |
9454fa87 VS |
1557 | |
1558 | /* | |
1559 | * If we have multiple ports supposedlt sharing the | |
1560 | * aux channel, then DP couldn't exist on the shared | |
1561 | * port. Otherwise they share the same aux channel | |
1562 | * and system couldn't communicate with them separately. | |
1563 | * | |
41e35ffb VS |
1564 | * Give inverse child device order the priority, |
1565 | * last one wins. Yes, there are real machines | |
1566 | * (eg. Asrock B250M-HDV) where VBT has both | |
1567 | * port A and port E with the same AUX ch and | |
1568 | * we must pick port E :( | |
9454fa87 | 1569 | */ |
41e35ffb VS |
1570 | info = &dev_priv->vbt.ddi_port_info[p]; |
1571 | ||
36a0f920 JN |
1572 | info->supports_dp = false; |
1573 | info->alternate_aux_channel = 0; | |
9454fa87 VS |
1574 | } |
1575 | } | |
1576 | ||
9c3b2689 | 1577 | static const u8 cnp_ddc_pin_map[] = { |
3393ce1e | 1578 | [0] = 0, /* N/A */ |
9c3b2689 RV |
1579 | [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT, |
1580 | [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT, | |
1581 | [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */ | |
1582 | [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ | |
1583 | }; | |
1584 | ||
3937eb1a | 1585 | static const u8 icp_ddc_pin_map[] = { |
d757535e MK |
1586 | [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, |
1587 | [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, | |
1588 | [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT, | |
1589 | [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, | |
1590 | [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, | |
1591 | [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, | |
1592 | [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, | |
1593 | [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP, | |
1594 | [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, | |
1595 | }; | |
1596 | ||
9c3b2689 RV |
1597 | static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) |
1598 | { | |
3937eb1a RS |
1599 | const u8 *ddc_pin_map; |
1600 | int n_entries; | |
1601 | ||
5a6b7ef6 | 1602 | if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { |
3937eb1a RS |
1603 | ddc_pin_map = icp_ddc_pin_map; |
1604 | n_entries = ARRAY_SIZE(icp_ddc_pin_map); | |
1605 | } else if (HAS_PCH_CNP(dev_priv)) { | |
1606 | ddc_pin_map = cnp_ddc_pin_map; | |
1607 | n_entries = ARRAY_SIZE(cnp_ddc_pin_map); | |
1608 | } else { | |
1609 | /* Assuming direct map */ | |
1610 | return vbt_pin; | |
a8e6f388 | 1611 | } |
9c3b2689 | 1612 | |
3937eb1a RS |
1613 | if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) |
1614 | return ddc_pin_map[vbt_pin]; | |
1615 | ||
e92cbf38 WK |
1616 | drm_dbg_kms(&dev_priv->drm, |
1617 | "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", | |
1618 | vbt_pin); | |
3937eb1a | 1619 | return 0; |
9c3b2689 RV |
1620 | } |
1621 | ||
b024ab9b | 1622 | static enum port dvo_port_to_port(u8 dvo_port) |
6acab15a | 1623 | { |
b024ab9b JN |
1624 | /* |
1625 | * Each DDI port can have more than one value on the "DVO Port" field, | |
b5273d72 JN |
1626 | * so look for all the possible values for each port. |
1627 | */ | |
b024ab9b JN |
1628 | static const int dvo_ports[][3] = { |
1629 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, | |
1630 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, | |
1631 | [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1}, | |
1632 | [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1}, | |
1633 | [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, | |
1634 | [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1}, | |
eb8de23c | 1635 | [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1}, |
6acab15a | 1636 | }; |
b024ab9b JN |
1637 | enum port port; |
1638 | int i; | |
6acab15a | 1639 | |
b024ab9b JN |
1640 | for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) { |
1641 | for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) { | |
1642 | if (dvo_ports[port][i] == -1) | |
6acab15a PZ |
1643 | break; |
1644 | ||
b024ab9b JN |
1645 | if (dvo_port == dvo_ports[port][i]) |
1646 | return port; | |
6acab15a PZ |
1647 | } |
1648 | } | |
b024ab9b JN |
1649 | |
1650 | return PORT_NONE; | |
1651 | } | |
1652 | ||
1653 | static void parse_ddi_port(struct drm_i915_private *dev_priv, | |
d1dad6f4 | 1654 | struct display_device_data *devdata, |
b024ab9b JN |
1655 | u8 bdb_version) |
1656 | { | |
d1dad6f4 | 1657 | const struct child_device_config *child = &devdata->child; |
b024ab9b JN |
1658 | struct ddi_vbt_port_info *info; |
1659 | bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; | |
1660 | enum port port; | |
1661 | ||
1662 | port = dvo_port_to_port(child->dvo_port); | |
1663 | if (port == PORT_NONE) | |
1664 | return; | |
1665 | ||
1666 | info = &dev_priv->vbt.ddi_port_info[port]; | |
1667 | ||
7679f9b8 | 1668 | if (info->child) { |
e92cbf38 WK |
1669 | drm_dbg_kms(&dev_priv->drm, |
1670 | "More than one child device for port %c in VBT, using the first.\n", | |
1671 | port_name(port)); | |
6acab15a | 1672 | return; |
b024ab9b JN |
1673 | } |
1674 | ||
cc998589 JN |
1675 | is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; |
1676 | is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
1677 | is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT; | |
1678 | is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; | |
1679 | is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); | |
554d6af5 | 1680 | |
523e0cc8 | 1681 | if (port == PORT_A && is_dvi && INTEL_GEN(dev_priv) < 12) { |
e92cbf38 WK |
1682 | drm_dbg_kms(&dev_priv->drm, |
1683 | "VBT claims port A supports DVI%s, ignoring\n", | |
1684 | is_hdmi ? "/HDMI" : ""); | |
2ba7d7e0 JN |
1685 | is_dvi = false; |
1686 | is_hdmi = false; | |
1687 | } | |
1688 | ||
311a2094 PZ |
1689 | info->supports_dvi = is_dvi; |
1690 | info->supports_hdmi = is_hdmi; | |
1691 | info->supports_dp = is_dp; | |
a98d9c1d | 1692 | info->supports_edp = is_edp; |
311a2094 | 1693 | |
38b3416f ID |
1694 | if (bdb_version >= 195) |
1695 | info->supports_typec_usb = child->dp_usb_type_c; | |
1696 | ||
1697 | if (bdb_version >= 209) | |
1698 | info->supports_tbt = child->tbt; | |
1699 | ||
e92cbf38 WK |
1700 | drm_dbg_kms(&dev_priv->drm, |
1701 | "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", | |
1702 | port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, | |
1703 | HAS_LSPCON(dev_priv) && child->lspcon, | |
1704 | info->supports_typec_usb, info->supports_tbt, | |
1705 | devdata->dsc != NULL); | |
554d6af5 | 1706 | |
6bf19e7c | 1707 | if (is_dvi) { |
e53a1058 JN |
1708 | u8 ddc_pin; |
1709 | ||
f212bf9a JN |
1710 | ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin); |
1711 | if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) { | |
1712 | info->alternate_ddc_pin = ddc_pin; | |
1713 | sanitize_ddc_pin(dev_priv, port); | |
1714 | } else { | |
e92cbf38 WK |
1715 | drm_dbg_kms(&dev_priv->drm, |
1716 | "Port %c has invalid DDC pin %d, " | |
1717 | "sticking to defaults\n", | |
1718 | port_name(port), ddc_pin); | |
f212bf9a | 1719 | } |
6bf19e7c PZ |
1720 | } |
1721 | ||
1722 | if (is_dp) { | |
e53a1058 | 1723 | info->alternate_aux_channel = child->aux_channel; |
9454fa87 VS |
1724 | |
1725 | sanitize_aux_ch(dev_priv, port); | |
6bf19e7c PZ |
1726 | } |
1727 | ||
0ead5f81 | 1728 | if (bdb_version >= 158) { |
6acab15a | 1729 | /* The VBT HDMI level shift values match the table we have. */ |
e53a1058 | 1730 | u8 hdmi_level_shift = child->hdmi_level_shifter_value; |
e92cbf38 WK |
1731 | drm_dbg_kms(&dev_priv->drm, |
1732 | "VBT HDMI level shift for port %c: %d\n", | |
1733 | port_name(port), | |
1734 | hdmi_level_shift); | |
ce4dd49e | 1735 | info->hdmi_level_shift = hdmi_level_shift; |
7a0073d6 | 1736 | info->hdmi_level_shift_set = true; |
6acab15a | 1737 | } |
75067dde | 1738 | |
d6038611 VS |
1739 | if (bdb_version >= 204) { |
1740 | int max_tmds_clock; | |
1741 | ||
1742 | switch (child->hdmi_max_data_rate) { | |
1743 | default: | |
1744 | MISSING_CASE(child->hdmi_max_data_rate); | |
1745 | /* fall through */ | |
1746 | case HDMI_MAX_DATA_RATE_PLATFORM: | |
1747 | max_tmds_clock = 0; | |
1748 | break; | |
1749 | case HDMI_MAX_DATA_RATE_297: | |
1750 | max_tmds_clock = 297000; | |
1751 | break; | |
1752 | case HDMI_MAX_DATA_RATE_165: | |
1753 | max_tmds_clock = 165000; | |
1754 | break; | |
1755 | } | |
1756 | ||
1757 | if (max_tmds_clock) | |
e92cbf38 WK |
1758 | drm_dbg_kms(&dev_priv->drm, |
1759 | "VBT HDMI max TMDS clock for port %c: %d kHz\n", | |
1760 | port_name(port), max_tmds_clock); | |
d6038611 VS |
1761 | info->max_tmds_clock = max_tmds_clock; |
1762 | } | |
1763 | ||
75067dde | 1764 | /* Parse the I_boost config for SKL and above */ |
0ead5f81 | 1765 | if (bdb_version >= 196 && child->iboost) { |
f22bb358 | 1766 | info->dp_boost_level = translate_iboost(child->dp_iboost_level); |
e92cbf38 WK |
1767 | drm_dbg_kms(&dev_priv->drm, |
1768 | "VBT (e)DP boost level for port %c: %d\n", | |
1769 | port_name(port), info->dp_boost_level); | |
f22bb358 | 1770 | info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level); |
e92cbf38 WK |
1771 | drm_dbg_kms(&dev_priv->drm, |
1772 | "VBT HDMI boost level for port %c: %d\n", | |
1773 | port_name(port), info->hdmi_boost_level); | |
75067dde | 1774 | } |
99b91bda JN |
1775 | |
1776 | /* DP max link rate for CNL+ */ | |
1777 | if (bdb_version >= 216) { | |
1778 | switch (child->dp_max_link_rate) { | |
1779 | default: | |
1780 | case VBT_DP_MAX_LINK_RATE_HBR3: | |
1781 | info->dp_max_link_rate = 810000; | |
1782 | break; | |
1783 | case VBT_DP_MAX_LINK_RATE_HBR2: | |
1784 | info->dp_max_link_rate = 540000; | |
1785 | break; | |
1786 | case VBT_DP_MAX_LINK_RATE_HBR: | |
1787 | info->dp_max_link_rate = 270000; | |
1788 | break; | |
1789 | case VBT_DP_MAX_LINK_RATE_LBR: | |
1790 | info->dp_max_link_rate = 162000; | |
1791 | break; | |
1792 | } | |
e92cbf38 WK |
1793 | drm_dbg_kms(&dev_priv->drm, |
1794 | "VBT DP max link rate for port %c: %d\n", | |
1795 | port_name(port), info->dp_max_link_rate); | |
99b91bda | 1796 | } |
7679f9b8 JN |
1797 | |
1798 | info->child = child; | |
6acab15a PZ |
1799 | } |
1800 | ||
0ead5f81 | 1801 | static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version) |
6acab15a | 1802 | { |
d1dad6f4 | 1803 | struct display_device_data *devdata; |
6acab15a | 1804 | |
348e4058 | 1805 | if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6acab15a PZ |
1806 | return; |
1807 | ||
0ead5f81 | 1808 | if (bdb_version < 155) |
6acab15a PZ |
1809 | return; |
1810 | ||
0d9ef19b | 1811 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) |
d1dad6f4 | 1812 | parse_ddi_port(dev_priv, devdata, bdb_version); |
6acab15a PZ |
1813 | } |
1814 | ||
6363ee6f | 1815 | static void |
b3ca1f43 JN |
1816 | parse_general_definitions(struct drm_i915_private *dev_priv, |
1817 | const struct bdb_header *bdb) | |
6363ee6f | 1818 | { |
e192839e | 1819 | const struct bdb_general_definitions *defs; |
0d9ef19b | 1820 | struct display_device_data *devdata; |
e192839e | 1821 | const struct child_device_config *child; |
0d9ef19b | 1822 | int i, child_device_num; |
e2d6cf7f DW |
1823 | u8 expected_size; |
1824 | u16 block_size; | |
b3ca1f43 | 1825 | int bus_pin; |
6363ee6f | 1826 | |
e192839e JN |
1827 | defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); |
1828 | if (!defs) { | |
e92cbf38 WK |
1829 | drm_dbg_kms(&dev_priv->drm, |
1830 | "No general definition block is found, no devices defined.\n"); | |
6363ee6f ZY |
1831 | return; |
1832 | } | |
b3ca1f43 JN |
1833 | |
1834 | block_size = get_blocksize(defs); | |
1835 | if (block_size < sizeof(*defs)) { | |
e92cbf38 WK |
1836 | drm_dbg_kms(&dev_priv->drm, |
1837 | "General definitions block too small (%u)\n", | |
1838 | block_size); | |
b3ca1f43 JN |
1839 | return; |
1840 | } | |
1841 | ||
1842 | bus_pin = defs->crt_ddc_gmbus_pin; | |
e92cbf38 | 1843 | drm_dbg_kms(&dev_priv->drm, "crt_ddc_bus_pin: %d\n", bus_pin); |
b3ca1f43 JN |
1844 | if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) |
1845 | dev_priv->vbt.crt_ddc_pin = bus_pin; | |
1846 | ||
7244f309 VS |
1847 | if (bdb->version < 106) { |
1848 | expected_size = 22; | |
fa05178c | 1849 | } else if (bdb->version < 111) { |
52b69c84 VS |
1850 | expected_size = 27; |
1851 | } else if (bdb->version < 195) { | |
21907e72 | 1852 | expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; |
e2d6cf7f DW |
1853 | } else if (bdb->version == 195) { |
1854 | expected_size = 37; | |
c4fb60b9 | 1855 | } else if (bdb->version <= 215) { |
e2d6cf7f | 1856 | expected_size = 38; |
3aec2c6a | 1857 | } else if (bdb->version <= 229) { |
c4fb60b9 | 1858 | expected_size = 39; |
e2d6cf7f | 1859 | } else { |
c4fb60b9 JN |
1860 | expected_size = sizeof(*child); |
1861 | BUILD_BUG_ON(sizeof(*child) < 39); | |
e92cbf38 WK |
1862 | drm_dbg(&dev_priv->drm, |
1863 | "Expected child device config size for VBT version %u not known; assuming %u\n", | |
1864 | bdb->version, expected_size); | |
e2d6cf7f DW |
1865 | } |
1866 | ||
e2d6cf7f | 1867 | /* Flag an error for unexpected size, but continue anyway. */ |
e192839e | 1868 | if (defs->child_dev_size != expected_size) |
e92cbf38 WK |
1869 | drm_err(&dev_priv->drm, |
1870 | "Unexpected child device config size %u (expected %u for VBT version %u)\n", | |
1871 | defs->child_dev_size, expected_size, bdb->version); | |
e2d6cf7f | 1872 | |
52b69c84 | 1873 | /* The legacy sized child device config is the minimum we need. */ |
e192839e | 1874 | if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { |
e92cbf38 WK |
1875 | drm_dbg_kms(&dev_priv->drm, |
1876 | "Child device config size %u is too small.\n", | |
1877 | defs->child_dev_size); | |
52b69c84 VS |
1878 | return; |
1879 | } | |
1880 | ||
6363ee6f | 1881 | /* get the number of child device */ |
e192839e | 1882 | child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; |
6363ee6f | 1883 | |
6363ee6f | 1884 | for (i = 0; i < child_device_num; i++) { |
e192839e | 1885 | child = child_device_ptr(defs, i); |
53f6b243 | 1886 | if (!child->device_type) |
6363ee6f | 1887 | continue; |
3e6bd011 | 1888 | |
e92cbf38 WK |
1889 | drm_dbg_kms(&dev_priv->drm, |
1890 | "Found VBT child device with type 0x%x\n", | |
1891 | child->device_type); | |
bdeb18db | 1892 | |
0d9ef19b JN |
1893 | devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); |
1894 | if (!devdata) | |
1895 | break; | |
1896 | ||
e2d6cf7f DW |
1897 | /* |
1898 | * Copy as much as we know (sizeof) and is available | |
0d9ef19b JN |
1899 | * (child_dev_size) of the child device config. Accessing the |
1900 | * data must depend on VBT version. | |
e2d6cf7f | 1901 | */ |
0d9ef19b | 1902 | memcpy(&devdata->child, child, |
e192839e | 1903 | min_t(size_t, defs->child_dev_size, sizeof(*child))); |
0d9ef19b JN |
1904 | |
1905 | list_add_tail(&devdata->node, &dev_priv->vbt.display_devices); | |
6363ee6f | 1906 | } |
0d9ef19b JN |
1907 | |
1908 | if (list_empty(&dev_priv->vbt.display_devices)) | |
e92cbf38 WK |
1909 | drm_dbg_kms(&dev_priv->drm, |
1910 | "no child dev is parsed from VBT\n"); | |
6363ee6f | 1911 | } |
44834a67 | 1912 | |
bb1d1329 | 1913 | /* Common defaults which may be overridden by VBT. */ |
6a04002b SQ |
1914 | static void |
1915 | init_vbt_defaults(struct drm_i915_private *dev_priv) | |
1916 | { | |
988c7015 | 1917 | dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; |
6a04002b | 1918 | |
56c4b63a JN |
1919 | /* Default to having backlight */ |
1920 | dev_priv->vbt.backlight.present = true; | |
1921 | ||
6a04002b | 1922 | /* LFP panel data */ |
41aa3448 | 1923 | dev_priv->vbt.lvds_dither = 1; |
6a04002b SQ |
1924 | |
1925 | /* SDVO panel data */ | |
41aa3448 | 1926 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; |
6a04002b SQ |
1927 | |
1928 | /* general features */ | |
41aa3448 RV |
1929 | dev_priv->vbt.int_tv_support = 1; |
1930 | dev_priv->vbt.int_crt_support = 1; | |
9a4114ff | 1931 | |
5255e2f8 VS |
1932 | /* driver features */ |
1933 | dev_priv->vbt.int_lvds_support = 1; | |
1934 | ||
9a4114ff | 1935 | /* Default to using SSC */ |
41aa3448 | 1936 | dev_priv->vbt.lvds_use_ssc = 1; |
f69e5156 DL |
1937 | /* |
1938 | * Core/SandyBridge/IvyBridge use alternative (120MHz) reference | |
1939 | * clock for LVDS. | |
1940 | */ | |
98f3a1dc JN |
1941 | dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv, |
1942 | !HAS_PCH_SPLIT(dev_priv)); | |
e92cbf38 WK |
1943 | drm_dbg_kms(&dev_priv->drm, "Set default to SSC at %d kHz\n", |
1944 | dev_priv->vbt.lvds_ssc_freq); | |
bb1d1329 JN |
1945 | } |
1946 | ||
1947 | /* Defaults to initialize only if there is no VBT. */ | |
1948 | static void | |
1949 | init_vbt_missing_defaults(struct drm_i915_private *dev_priv) | |
1950 | { | |
1951 | enum port port; | |
1952 | ||
c4a774c4 | 1953 | for_each_port(port) { |
bb1d1329 JN |
1954 | struct ddi_vbt_port_info *info = |
1955 | &dev_priv->vbt.ddi_port_info[port]; | |
d8fe2ab6 | 1956 | enum phy phy = intel_port_to_phy(dev_priv, port); |
311a2094 | 1957 | |
828ccb31 ID |
1958 | /* |
1959 | * VBT has the TypeC mode (native,TBT/USB) and we don't want | |
1960 | * to detect it. | |
1961 | */ | |
d8fe2ab6 | 1962 | if (intel_phy_is_tc(dev_priv, phy)) |
828ccb31 ID |
1963 | continue; |
1964 | ||
311a2094 PZ |
1965 | info->supports_dvi = (port != PORT_A && port != PORT_E); |
1966 | info->supports_hdmi = info->supports_dvi; | |
1967 | info->supports_dp = (port != PORT_E); | |
2131bc0c | 1968 | info->supports_edp = (port == PORT_A); |
6acab15a | 1969 | } |
6a04002b SQ |
1970 | } |
1971 | ||
caf37fa4 JN |
1972 | static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) |
1973 | { | |
1974 | const void *_vbt = vbt; | |
1975 | ||
1976 | return _vbt + vbt->bdb_offset; | |
1977 | } | |
1978 | ||
f0067a31 JN |
1979 | /** |
1980 | * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT | |
1981 | * @buf: pointer to a buffer to validate | |
1982 | * @size: size of the buffer | |
1983 | * | |
1984 | * Returns true on valid VBT. | |
1985 | */ | |
1986 | bool intel_bios_is_valid_vbt(const void *buf, size_t size) | |
3dd4e846 | 1987 | { |
f0067a31 | 1988 | const struct vbt_header *vbt = buf; |
dcb58a40 | 1989 | const struct bdb_header *bdb; |
3dd4e846 | 1990 | |
caf37fa4 | 1991 | if (!vbt) |
f0067a31 | 1992 | return false; |
caf37fa4 | 1993 | |
f0067a31 | 1994 | if (sizeof(struct vbt_header) > size) { |
3dd4e846 | 1995 | DRM_DEBUG_DRIVER("VBT header incomplete\n"); |
f0067a31 | 1996 | return false; |
3dd4e846 CW |
1997 | } |
1998 | ||
1999 | if (memcmp(vbt->signature, "$VBT", 4)) { | |
2000 | DRM_DEBUG_DRIVER("VBT invalid signature\n"); | |
f0067a31 | 2001 | return false; |
3dd4e846 CW |
2002 | } |
2003 | ||
ff00ff96 LDM |
2004 | if (vbt->vbt_size > size) { |
2005 | DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n"); | |
2006 | return false; | |
2007 | } | |
2008 | ||
2009 | size = vbt->vbt_size; | |
2010 | ||
e8f9ae9b CW |
2011 | if (range_overflows_t(size_t, |
2012 | vbt->bdb_offset, | |
2013 | sizeof(struct bdb_header), | |
2014 | size)) { | |
3dd4e846 | 2015 | DRM_DEBUG_DRIVER("BDB header incomplete\n"); |
f0067a31 | 2016 | return false; |
3dd4e846 CW |
2017 | } |
2018 | ||
caf37fa4 | 2019 | bdb = get_bdb_header(vbt); |
e8f9ae9b | 2020 | if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { |
3dd4e846 | 2021 | DRM_DEBUG_DRIVER("BDB incomplete\n"); |
f0067a31 | 2022 | return false; |
3dd4e846 CW |
2023 | } |
2024 | ||
caf37fa4 | 2025 | return vbt; |
3dd4e846 CW |
2026 | } |
2027 | ||
2cded152 | 2028 | static struct vbt_header *oprom_get_vbt(struct drm_i915_private *dev_priv) |
b34a991a | 2029 | { |
2cded152 LDM |
2030 | struct pci_dev *pdev = dev_priv->drm.pdev; |
2031 | void __iomem *p = NULL, *oprom; | |
fd0186ce LDM |
2032 | struct vbt_header *vbt; |
2033 | u16 vbt_size; | |
2cded152 LDM |
2034 | size_t i, size; |
2035 | ||
2036 | oprom = pci_map_rom(pdev, &size); | |
2037 | if (!oprom) | |
2038 | return NULL; | |
b34a991a JN |
2039 | |
2040 | /* Scour memory looking for the VBT signature. */ | |
98cf5c9a | 2041 | for (i = 0; i + 4 < size; i += 4) { |
496f50a6 | 2042 | if (ioread32(oprom + i) != *((const u32 *)"$VBT")) |
f0067a31 JN |
2043 | continue; |
2044 | ||
fd0186ce LDM |
2045 | p = oprom + i; |
2046 | size -= i; | |
f0067a31 | 2047 | break; |
b34a991a JN |
2048 | } |
2049 | ||
fd0186ce | 2050 | if (!p) |
2cded152 | 2051 | goto err_unmap_oprom; |
fd0186ce LDM |
2052 | |
2053 | if (sizeof(struct vbt_header) > size) { | |
e92cbf38 | 2054 | drm_dbg(&dev_priv->drm, "VBT header incomplete\n"); |
2cded152 | 2055 | goto err_unmap_oprom; |
fd0186ce LDM |
2056 | } |
2057 | ||
2058 | vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); | |
2059 | if (vbt_size > size) { | |
e92cbf38 WK |
2060 | drm_dbg(&dev_priv->drm, |
2061 | "VBT incomplete (vbt_size overflows)\n"); | |
2cded152 | 2062 | goto err_unmap_oprom; |
fd0186ce LDM |
2063 | } |
2064 | ||
2065 | /* The rest will be validated by intel_bios_is_valid_vbt() */ | |
2066 | vbt = kmalloc(vbt_size, GFP_KERNEL); | |
2067 | if (!vbt) | |
2cded152 | 2068 | goto err_unmap_oprom; |
fd0186ce LDM |
2069 | |
2070 | memcpy_fromio(vbt, p, vbt_size); | |
2071 | ||
2072 | if (!intel_bios_is_valid_vbt(vbt, vbt_size)) | |
2073 | goto err_free_vbt; | |
2074 | ||
2cded152 LDM |
2075 | pci_unmap_rom(pdev, oprom); |
2076 | ||
fd0186ce LDM |
2077 | return vbt; |
2078 | ||
2079 | err_free_vbt: | |
2080 | kfree(vbt); | |
2cded152 LDM |
2081 | err_unmap_oprom: |
2082 | pci_unmap_rom(pdev, oprom); | |
fd0186ce | 2083 | |
f0067a31 | 2084 | return NULL; |
b34a991a JN |
2085 | } |
2086 | ||
79e53945 | 2087 | /** |
8b8e1a89 | 2088 | * intel_bios_init - find VBT and initialize settings from the BIOS |
dd97950a | 2089 | * @dev_priv: i915 device instance |
79e53945 | 2090 | * |
66578857 JN |
2091 | * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT |
2092 | * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also | |
2093 | * initialize some defaults if the VBT is not present at all. | |
79e53945 | 2094 | */ |
66578857 | 2095 | void intel_bios_init(struct drm_i915_private *dev_priv) |
79e53945 | 2096 | { |
f0067a31 | 2097 | const struct vbt_header *vbt = dev_priv->opregion.vbt; |
2cded152 | 2098 | struct vbt_header *oprom_vbt = NULL; |
caf37fa4 | 2099 | const struct bdb_header *bdb; |
44834a67 | 2100 | |
0d9ef19b JN |
2101 | INIT_LIST_HEAD(&dev_priv->vbt.display_devices); |
2102 | ||
a2b69ea4 | 2103 | if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) { |
e92cbf38 WK |
2104 | drm_dbg_kms(&dev_priv->drm, |
2105 | "Skipping VBT init due to disabled display.\n"); | |
66578857 JN |
2106 | return; |
2107 | } | |
ab5c608b | 2108 | |
6a04002b | 2109 | init_vbt_defaults(dev_priv); |
f899fc64 | 2110 | |
66578857 | 2111 | /* If the OpRegion does not have VBT, look in PCI ROM. */ |
f0067a31 | 2112 | if (!vbt) { |
2cded152 LDM |
2113 | oprom_vbt = oprom_get_vbt(dev_priv); |
2114 | if (!oprom_vbt) | |
66578857 | 2115 | goto out; |
44834a67 | 2116 | |
2cded152 | 2117 | vbt = oprom_vbt; |
e2051c44 | 2118 | |
e92cbf38 | 2119 | drm_dbg_kms(&dev_priv->drm, "Found valid VBT in PCI ROM\n"); |
44834a67 | 2120 | } |
79e53945 | 2121 | |
caf37fa4 JN |
2122 | bdb = get_bdb_header(vbt); |
2123 | ||
e92cbf38 WK |
2124 | drm_dbg_kms(&dev_priv->drm, |
2125 | "VBT signature \"%.*s\", BDB version %d\n", | |
2126 | (int)sizeof(vbt->signature), vbt->signature, bdb->version); | |
e2051c44 | 2127 | |
79e53945 JB |
2128 | /* Grab useful general definitions */ |
2129 | parse_general_features(dev_priv, bdb); | |
db545019 | 2130 | parse_general_definitions(dev_priv, bdb); |
9e7ecedf | 2131 | parse_panel_options(dev_priv, bdb); |
33ef6d4f | 2132 | parse_panel_dtd(dev_priv, bdb); |
f00076d2 | 2133 | parse_lfp_backlight(dev_priv, bdb); |
88631706 | 2134 | parse_sdvo_panel_data(dev_priv, bdb); |
32f9d658 | 2135 | parse_driver_features(dev_priv, bdb); |
551fb93d | 2136 | parse_power_conservation_features(dev_priv, bdb); |
500a8cc4 | 2137 | parse_edp(dev_priv, bdb); |
bfd7ebda | 2138 | parse_psr(dev_priv, bdb); |
0f8689f5 JN |
2139 | parse_mipi_config(dev_priv, bdb); |
2140 | parse_mipi_sequence(dev_priv, bdb); | |
0ebdabe6 | 2141 | |
6e0d46e9 JN |
2142 | /* Depends on child device list */ |
2143 | parse_compression_parameters(dev_priv, bdb); | |
2144 | ||
0ebdabe6 | 2145 | /* Further processing on pre-parsed data */ |
0ead5f81 JN |
2146 | parse_sdvo_device_mapping(dev_priv, bdb->version); |
2147 | parse_ddi_ports(dev_priv, bdb->version); | |
32f9d658 | 2148 | |
66578857 | 2149 | out: |
bb1d1329 | 2150 | if (!vbt) { |
e92cbf38 WK |
2151 | drm_info(&dev_priv->drm, |
2152 | "Failed to find VBIOS tables (VBT)\n"); | |
bb1d1329 JN |
2153 | init_vbt_missing_defaults(dev_priv); |
2154 | } | |
66578857 | 2155 | |
2cded152 | 2156 | kfree(oprom_vbt); |
79e53945 | 2157 | } |
3bdd14d5 | 2158 | |
785f076b | 2159 | /** |
78dae1ac | 2160 | * intel_bios_driver_remove - Free any resources allocated by intel_bios_init() |
785f076b HG |
2161 | * @dev_priv: i915 device instance |
2162 | */ | |
78dae1ac | 2163 | void intel_bios_driver_remove(struct drm_i915_private *dev_priv) |
785f076b | 2164 | { |
0d9ef19b JN |
2165 | struct display_device_data *devdata, *n; |
2166 | ||
2167 | list_for_each_entry_safe(devdata, n, &dev_priv->vbt.display_devices, node) { | |
2168 | list_del(&devdata->node); | |
6e0d46e9 | 2169 | kfree(devdata->dsc); |
0d9ef19b JN |
2170 | kfree(devdata); |
2171 | } | |
2172 | ||
785f076b HG |
2173 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); |
2174 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
2175 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
2176 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
e1b86c85 HG |
2177 | kfree(dev_priv->vbt.dsi.data); |
2178 | dev_priv->vbt.dsi.data = NULL; | |
2179 | kfree(dev_priv->vbt.dsi.pps); | |
2180 | dev_priv->vbt.dsi.pps = NULL; | |
2181 | kfree(dev_priv->vbt.dsi.config); | |
2182 | dev_priv->vbt.dsi.config = NULL; | |
fb38e7ad HG |
2183 | kfree(dev_priv->vbt.dsi.deassert_seq); |
2184 | dev_priv->vbt.dsi.deassert_seq = NULL; | |
785f076b HG |
2185 | } |
2186 | ||
3bdd14d5 JN |
2187 | /** |
2188 | * intel_bios_is_tv_present - is integrated TV present in VBT | |
2189 | * @dev_priv: i915 device instance | |
2190 | * | |
2191 | * Return true if TV is present. If no child devices were parsed from VBT, | |
2192 | * assume TV is present. | |
2193 | */ | |
2194 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) | |
2195 | { | |
0d9ef19b | 2196 | const struct display_device_data *devdata; |
cc998589 | 2197 | const struct child_device_config *child; |
3bdd14d5 JN |
2198 | |
2199 | if (!dev_priv->vbt.int_tv_support) | |
2200 | return false; | |
2201 | ||
0d9ef19b | 2202 | if (list_empty(&dev_priv->vbt.display_devices)) |
3bdd14d5 JN |
2203 | return true; |
2204 | ||
0d9ef19b JN |
2205 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { |
2206 | child = &devdata->child; | |
2207 | ||
3bdd14d5 JN |
2208 | /* |
2209 | * If the device type is not TV, continue. | |
2210 | */ | |
cc998589 | 2211 | switch (child->device_type) { |
3bdd14d5 JN |
2212 | case DEVICE_TYPE_INT_TV: |
2213 | case DEVICE_TYPE_TV: | |
2214 | case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: | |
2215 | break; | |
2216 | default: | |
2217 | continue; | |
2218 | } | |
2219 | /* Only when the addin_offset is non-zero, it is regarded | |
2220 | * as present. | |
2221 | */ | |
cc998589 | 2222 | if (child->addin_offset) |
3bdd14d5 JN |
2223 | return true; |
2224 | } | |
2225 | ||
2226 | return false; | |
2227 | } | |
5a69d13d JN |
2228 | |
2229 | /** | |
2230 | * intel_bios_is_lvds_present - is LVDS present in VBT | |
2231 | * @dev_priv: i915 device instance | |
2232 | * @i2c_pin: i2c pin for LVDS if present | |
2233 | * | |
2234 | * Return true if LVDS is present. If no child devices were parsed from VBT, | |
2235 | * assume LVDS is present. | |
2236 | */ | |
2237 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin) | |
2238 | { | |
0d9ef19b | 2239 | const struct display_device_data *devdata; |
cc998589 | 2240 | const struct child_device_config *child; |
5a69d13d | 2241 | |
0d9ef19b | 2242 | if (list_empty(&dev_priv->vbt.display_devices)) |
5a69d13d JN |
2243 | return true; |
2244 | ||
0d9ef19b JN |
2245 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { |
2246 | child = &devdata->child; | |
5a69d13d JN |
2247 | |
2248 | /* If the device type is not LFP, continue. | |
2249 | * We have to check both the new identifiers as well as the | |
2250 | * old for compatibility with some BIOSes. | |
2251 | */ | |
2252 | if (child->device_type != DEVICE_TYPE_INT_LFP && | |
2253 | child->device_type != DEVICE_TYPE_LFP) | |
2254 | continue; | |
2255 | ||
2256 | if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) | |
2257 | *i2c_pin = child->i2c_pin; | |
2258 | ||
2259 | /* However, we cannot trust the BIOS writers to populate | |
2260 | * the VBT correctly. Since LVDS requires additional | |
2261 | * information from AIM blocks, a non-zero addin offset is | |
2262 | * a good indicator that the LVDS is actually present. | |
2263 | */ | |
2264 | if (child->addin_offset) | |
2265 | return true; | |
2266 | ||
2267 | /* But even then some BIOS writers perform some black magic | |
2268 | * and instantiate the device without reference to any | |
2269 | * additional data. Trust that if the VBT was written into | |
2270 | * the OpRegion then they have validated the LVDS's existence. | |
2271 | */ | |
2272 | if (dev_priv->opregion.vbt) | |
2273 | return true; | |
2274 | } | |
2275 | ||
2276 | return false; | |
2277 | } | |
951d9efe | 2278 | |
22f35042 VS |
2279 | /** |
2280 | * intel_bios_is_port_present - is the specified digital port present | |
2281 | * @dev_priv: i915 device instance | |
2282 | * @port: port to check | |
2283 | * | |
2284 | * Return true if the device in %port is present. | |
2285 | */ | |
2286 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port) | |
2287 | { | |
0d9ef19b | 2288 | const struct display_device_data *devdata; |
cc998589 | 2289 | const struct child_device_config *child; |
22f35042 VS |
2290 | static const struct { |
2291 | u16 dp, hdmi; | |
2292 | } port_mapping[] = { | |
2293 | [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, | |
2294 | [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, | |
2295 | [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, | |
2296 | [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, | |
841b5ed7 | 2297 | [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, |
22f35042 | 2298 | }; |
22f35042 | 2299 | |
e9d49bb7 ID |
2300 | if (HAS_DDI(dev_priv)) { |
2301 | const struct ddi_vbt_port_info *port_info = | |
2302 | &dev_priv->vbt.ddi_port_info[port]; | |
2303 | ||
85d8ec20 | 2304 | return port_info->child; |
e9d49bb7 ID |
2305 | } |
2306 | ||
22f35042 VS |
2307 | /* FIXME maybe deal with port A as well? */ |
2308 | if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping)) | |
2309 | return false; | |
2310 | ||
0d9ef19b JN |
2311 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { |
2312 | child = &devdata->child; | |
cc998589 JN |
2313 | |
2314 | if ((child->dvo_port == port_mapping[port].dp || | |
2315 | child->dvo_port == port_mapping[port].hdmi) && | |
2316 | (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING | | |
2317 | DEVICE_TYPE_DISPLAYPORT_OUTPUT))) | |
22f35042 VS |
2318 | return true; |
2319 | } | |
2320 | ||
2321 | return false; | |
2322 | } | |
2323 | ||
951d9efe JN |
2324 | /** |
2325 | * intel_bios_is_port_edp - is the device in given port eDP | |
2326 | * @dev_priv: i915 device instance | |
2327 | * @port: port to check | |
2328 | * | |
2329 | * Return true if the device in %port is eDP. | |
2330 | */ | |
2331 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) | |
2332 | { | |
0d9ef19b | 2333 | const struct display_device_data *devdata; |
cc998589 | 2334 | const struct child_device_config *child; |
951d9efe JN |
2335 | static const short port_mapping[] = { |
2336 | [PORT_B] = DVO_PORT_DPB, | |
2337 | [PORT_C] = DVO_PORT_DPC, | |
2338 | [PORT_D] = DVO_PORT_DPD, | |
2339 | [PORT_E] = DVO_PORT_DPE, | |
841b5ed7 | 2340 | [PORT_F] = DVO_PORT_DPF, |
951d9efe | 2341 | }; |
951d9efe | 2342 | |
a98d9c1d ID |
2343 | if (HAS_DDI(dev_priv)) |
2344 | return dev_priv->vbt.ddi_port_info[port].supports_edp; | |
2345 | ||
0d9ef19b JN |
2346 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { |
2347 | child = &devdata->child; | |
951d9efe | 2348 | |
cc998589 JN |
2349 | if (child->dvo_port == port_mapping[port] && |
2350 | (child->device_type & DEVICE_TYPE_eDP_BITS) == | |
951d9efe JN |
2351 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
2352 | return true; | |
2353 | } | |
2354 | ||
2355 | return false; | |
2356 | } | |
7137aec1 | 2357 | |
cc998589 | 2358 | static bool child_dev_is_dp_dual_mode(const struct child_device_config *child, |
7a17995a | 2359 | enum port port) |
d6199256 VS |
2360 | { |
2361 | static const struct { | |
2362 | u16 dp, hdmi; | |
2363 | } port_mapping[] = { | |
2364 | /* | |
2365 | * Buggy VBTs may declare DP ports as having | |
2366 | * HDMI type dvo_port :( So let's check both. | |
2367 | */ | |
2368 | [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, | |
2369 | [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, | |
2370 | [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, | |
2371 | [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, | |
841b5ed7 | 2372 | [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, |
d6199256 | 2373 | }; |
d6199256 VS |
2374 | |
2375 | if (port == PORT_A || port >= ARRAY_SIZE(port_mapping)) | |
2376 | return false; | |
2377 | ||
cc998589 | 2378 | if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != |
7a17995a | 2379 | (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) |
d6199256 VS |
2380 | return false; |
2381 | ||
cc998589 | 2382 | if (child->dvo_port == port_mapping[port].dp) |
7a17995a VS |
2383 | return true; |
2384 | ||
2385 | /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ | |
cc998589 JN |
2386 | if (child->dvo_port == port_mapping[port].hdmi && |
2387 | child->aux_channel != 0) | |
7a17995a VS |
2388 | return true; |
2389 | ||
2390 | return false; | |
2391 | } | |
2392 | ||
2393 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, | |
2394 | enum port port) | |
2395 | { | |
0d9ef19b | 2396 | const struct display_device_data *devdata; |
7a17995a | 2397 | |
0d9ef19b JN |
2398 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { |
2399 | if (child_dev_is_dp_dual_mode(&devdata->child, port)) | |
d6199256 VS |
2400 | return true; |
2401 | } | |
2402 | ||
2403 | return false; | |
2404 | } | |
2405 | ||
7137aec1 JN |
2406 | /** |
2407 | * intel_bios_is_dsi_present - is DSI present in VBT | |
2408 | * @dev_priv: i915 device instance | |
2409 | * @port: port for DSI if present | |
2410 | * | |
2411 | * Return true if DSI is present, and return the port in %port. | |
2412 | */ | |
2413 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, | |
2414 | enum port *port) | |
2415 | { | |
0d9ef19b | 2416 | const struct display_device_data *devdata; |
cc998589 | 2417 | const struct child_device_config *child; |
7137aec1 | 2418 | u8 dvo_port; |
7137aec1 | 2419 | |
0d9ef19b JN |
2420 | list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { |
2421 | child = &devdata->child; | |
7137aec1 | 2422 | |
cc998589 | 2423 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) |
7137aec1 JN |
2424 | continue; |
2425 | ||
cc998589 | 2426 | dvo_port = child->dvo_port; |
7137aec1 | 2427 | |
bf4d57ff | 2428 | if (dvo_port == DVO_PORT_MIPIA || |
2dd24a9c RV |
2429 | (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) || |
2430 | (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) { | |
7caaef33 JN |
2431 | if (port) |
2432 | *port = dvo_port - DVO_PORT_MIPIA; | |
7137aec1 | 2433 | return true; |
bf4d57ff MC |
2434 | } else if (dvo_port == DVO_PORT_MIPIB || |
2435 | dvo_port == DVO_PORT_MIPIC || | |
2436 | dvo_port == DVO_PORT_MIPID) { | |
e92cbf38 WK |
2437 | drm_dbg_kms(&dev_priv->drm, |
2438 | "VBT has unsupported DSI port %c\n", | |
2439 | port_name(dvo_port - DVO_PORT_MIPIA)); | |
7137aec1 JN |
2440 | } |
2441 | } | |
2442 | ||
2443 | return false; | |
2444 | } | |
d252bf68 | 2445 | |
1bf2f3bf JN |
2446 | static void fill_dsc(struct intel_crtc_state *crtc_state, |
2447 | struct dsc_compression_parameters_entry *dsc, | |
2448 | int dsc_max_bpc) | |
2449 | { | |
2450 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; | |
2451 | int bpc = 8; | |
2452 | ||
2453 | vdsc_cfg->dsc_version_major = dsc->version_major; | |
2454 | vdsc_cfg->dsc_version_minor = dsc->version_minor; | |
2455 | ||
2456 | if (dsc->support_12bpc && dsc_max_bpc >= 12) | |
2457 | bpc = 12; | |
2458 | else if (dsc->support_10bpc && dsc_max_bpc >= 10) | |
2459 | bpc = 10; | |
2460 | else if (dsc->support_8bpc && dsc_max_bpc >= 8) | |
2461 | bpc = 8; | |
2462 | else | |
2463 | DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n", | |
2464 | dsc_max_bpc); | |
2465 | ||
2466 | crtc_state->pipe_bpp = bpc * 3; | |
2467 | ||
2468 | crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, | |
2469 | VBT_DSC_MAX_BPP(dsc->max_bpp)); | |
2470 | ||
2471 | /* | |
2472 | * FIXME: This is ugly, and slice count should take DSC engine | |
2473 | * throughput etc. into account. | |
2474 | * | |
2475 | * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices. | |
2476 | */ | |
2477 | if (dsc->slices_per_line & BIT(2)) { | |
2478 | crtc_state->dsc.slice_count = 4; | |
2479 | } else if (dsc->slices_per_line & BIT(1)) { | |
2480 | crtc_state->dsc.slice_count = 2; | |
2481 | } else { | |
2482 | /* FIXME */ | |
2483 | if (!(dsc->slices_per_line & BIT(0))) | |
2484 | DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n"); | |
2485 | ||
2486 | crtc_state->dsc.slice_count = 1; | |
2487 | } | |
2488 | ||
2489 | if (crtc_state->hw.adjusted_mode.crtc_hdisplay % | |
2490 | crtc_state->dsc.slice_count != 0) | |
2491 | DRM_DEBUG_KMS("VBT: DSC hdisplay %d not divisible by slice count %d\n", | |
2492 | crtc_state->hw.adjusted_mode.crtc_hdisplay, | |
2493 | crtc_state->dsc.slice_count); | |
2494 | ||
2495 | /* | |
2496 | * FIXME: Use VBT rc_buffer_block_size and rc_buffer_size for the | |
2497 | * implementation specific physical rate buffer size. Currently we use | |
2498 | * the required rate buffer model size calculated in | |
2499 | * drm_dsc_compute_rc_parameters() according to VESA DSC Annex E. | |
2500 | * | |
2501 | * The VBT rc_buffer_block_size and rc_buffer_size definitions | |
2502 | * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. The DP DSC | |
2503 | * implementation should also use the DPCD (or perhaps VBT for eDP) | |
2504 | * provided value for the buffer size. | |
2505 | */ | |
2506 | ||
2507 | /* FIXME: DSI spec says bpc + 1 for this one */ | |
2508 | vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); | |
2509 | ||
2510 | vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; | |
2511 | ||
2512 | vdsc_cfg->slice_height = dsc->slice_height; | |
2513 | } | |
2514 | ||
2515 | /* FIXME: initially DSI specific */ | |
2516 | bool intel_bios_get_dsc_params(struct intel_encoder *encoder, | |
2517 | struct intel_crtc_state *crtc_state, | |
2518 | int dsc_max_bpc) | |
2519 | { | |
2520 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2521 | const struct display_device_data *devdata; | |
2522 | const struct child_device_config *child; | |
2523 | ||
2524 | list_for_each_entry(devdata, &i915->vbt.display_devices, node) { | |
2525 | child = &devdata->child; | |
2526 | ||
2527 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) | |
2528 | continue; | |
2529 | ||
2530 | if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) { | |
2531 | if (!devdata->dsc) | |
2532 | return false; | |
2533 | ||
2534 | if (crtc_state) | |
2535 | fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc); | |
2536 | ||
2537 | return true; | |
2538 | } | |
2539 | } | |
2540 | ||
2541 | return false; | |
2542 | } | |
2543 | ||
d252bf68 SS |
2544 | /** |
2545 | * intel_bios_is_port_hpd_inverted - is HPD inverted for %port | |
c72deaa4 | 2546 | * @i915: i915 device instance |
d252bf68 SS |
2547 | * @port: port to check |
2548 | * | |
2549 | * Return true if HPD should be inverted for %port. | |
2550 | */ | |
2551 | bool | |
c72deaa4 | 2552 | intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, |
d252bf68 SS |
2553 | enum port port) |
2554 | { | |
c72deaa4 JN |
2555 | const struct child_device_config *child = |
2556 | i915->vbt.ddi_port_info[port].child; | |
d252bf68 | 2557 | |
c72deaa4 | 2558 | if (WARN_ON_ONCE(!IS_GEN9_LP(i915))) |
d252bf68 SS |
2559 | return false; |
2560 | ||
c72deaa4 | 2561 | return child && child->hpd_invert; |
d252bf68 | 2562 | } |
6389dd83 SS |
2563 | |
2564 | /** | |
2565 | * intel_bios_is_lspcon_present - if LSPCON is attached on %port | |
a7475e5d | 2566 | * @i915: i915 device instance |
6389dd83 SS |
2567 | * @port: port to check |
2568 | * | |
2569 | * Return true if LSPCON is present on this port | |
2570 | */ | |
2571 | bool | |
a7475e5d JN |
2572 | intel_bios_is_lspcon_present(const struct drm_i915_private *i915, |
2573 | enum port port) | |
6389dd83 | 2574 | { |
a7475e5d JN |
2575 | const struct child_device_config *child = |
2576 | i915->vbt.ddi_port_info[port].child; | |
6389dd83 | 2577 | |
a7475e5d | 2578 | return HAS_LSPCON(i915) && child && child->lspcon; |
6389dd83 | 2579 | } |
15d248ae | 2580 | |
39053089 JN |
2581 | enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, |
2582 | enum port port) | |
15d248ae ID |
2583 | { |
2584 | const struct ddi_vbt_port_info *info = | |
2585 | &dev_priv->vbt.ddi_port_info[port]; | |
2586 | enum aux_ch aux_ch; | |
2587 | ||
2588 | if (!info->alternate_aux_channel) { | |
2589 | aux_ch = (enum aux_ch)port; | |
2590 | ||
e92cbf38 WK |
2591 | drm_dbg_kms(&dev_priv->drm, |
2592 | "using AUX %c for port %c (platform default)\n", | |
2593 | aux_ch_name(aux_ch), port_name(port)); | |
15d248ae ID |
2594 | return aux_ch; |
2595 | } | |
2596 | ||
2597 | switch (info->alternate_aux_channel) { | |
2598 | case DP_AUX_A: | |
2599 | aux_ch = AUX_CH_A; | |
2600 | break; | |
2601 | case DP_AUX_B: | |
2602 | aux_ch = AUX_CH_B; | |
2603 | break; | |
2604 | case DP_AUX_C: | |
2605 | aux_ch = AUX_CH_C; | |
2606 | break; | |
2607 | case DP_AUX_D: | |
2608 | aux_ch = AUX_CH_D; | |
2609 | break; | |
2610 | case DP_AUX_E: | |
2611 | aux_ch = AUX_CH_E; | |
2612 | break; | |
2613 | case DP_AUX_F: | |
2614 | aux_ch = AUX_CH_F; | |
2615 | break; | |
eb8de23c KA |
2616 | case DP_AUX_G: |
2617 | aux_ch = AUX_CH_G; | |
2618 | break; | |
15d248ae ID |
2619 | default: |
2620 | MISSING_CASE(info->alternate_aux_channel); | |
2621 | aux_ch = AUX_CH_A; | |
2622 | break; | |
2623 | } | |
2624 | ||
e92cbf38 WK |
2625 | drm_dbg_kms(&dev_priv->drm, "using AUX %c for port %c (VBT)\n", |
2626 | aux_ch_name(aux_ch), port_name(port)); | |
15d248ae ID |
2627 | |
2628 | return aux_ch; | |
2629 | } | |
d9ee2111 JN |
2630 | |
2631 | int intel_bios_max_tmds_clock(struct intel_encoder *encoder) | |
2632 | { | |
2633 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2634 | ||
2635 | return i915->vbt.ddi_port_info[encoder->port].max_tmds_clock; | |
2636 | } | |
0aed3bde JN |
2637 | |
2638 | int intel_bios_hdmi_level_shift(struct intel_encoder *encoder) | |
2639 | { | |
2640 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2641 | const struct ddi_vbt_port_info *info = | |
2642 | &i915->vbt.ddi_port_info[encoder->port]; | |
2643 | ||
2644 | return info->hdmi_level_shift_set ? info->hdmi_level_shift : -1; | |
2645 | } | |
605a1872 JN |
2646 | |
2647 | int intel_bios_dp_boost_level(struct intel_encoder *encoder) | |
2648 | { | |
2649 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2650 | ||
2651 | return i915->vbt.ddi_port_info[encoder->port].dp_boost_level; | |
2652 | } | |
01a60883 JN |
2653 | |
2654 | int intel_bios_hdmi_boost_level(struct intel_encoder *encoder) | |
2655 | { | |
2656 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2657 | ||
2658 | return i915->vbt.ddi_port_info[encoder->port].hdmi_boost_level; | |
2659 | } | |
f83acdab JN |
2660 | |
2661 | int intel_bios_dp_max_link_rate(struct intel_encoder *encoder) | |
2662 | { | |
2663 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2664 | ||
2665 | return i915->vbt.ddi_port_info[encoder->port].dp_max_link_rate; | |
2666 | } | |
17004bfb JN |
2667 | |
2668 | int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder) | |
2669 | { | |
2670 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
2671 | ||
2672 | return i915->vbt.ddi_port_info[encoder->port].alternate_ddc_pin; | |
2673 | } | |
c5faae5a JN |
2674 | |
2675 | bool intel_bios_port_supports_dvi(struct drm_i915_private *i915, enum port port) | |
2676 | { | |
2677 | return i915->vbt.ddi_port_info[port].supports_dvi; | |
2678 | } | |
2679 | ||
2680 | bool intel_bios_port_supports_hdmi(struct drm_i915_private *i915, enum port port) | |
2681 | { | |
2682 | return i915->vbt.ddi_port_info[port].supports_hdmi; | |
2683 | } | |
2684 | ||
2685 | bool intel_bios_port_supports_dp(struct drm_i915_private *i915, enum port port) | |
2686 | { | |
2687 | return i915->vbt.ddi_port_info[port].supports_dp; | |
2688 | } | |
2689 | ||
2690 | bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, | |
2691 | enum port port) | |
2692 | { | |
2693 | return i915->vbt.ddi_port_info[port].supports_typec_usb; | |
2694 | } | |
2695 | ||
2696 | bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port) | |
2697 | { | |
2698 | return i915->vbt.ddi_port_info[port].supports_tbt; | |
2699 | } |