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79e53945 | 1 | /* |
39507259 | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
b30581a4 | 27 | |
9f0e7ff4 | 28 | #include <drm/drm_dp_helper.h> |
760285e7 | 29 | #include <drm/i915_drm.h> |
3ce2ea65 | 30 | |
d8fe2ab6 | 31 | #include "display/intel_display.h" |
379bc100 JN |
32 | #include "display/intel_gmbus.h" |
33 | ||
79e53945 | 34 | #include "i915_drv.h" |
72341af4 JN |
35 | |
36 | #define _INTEL_BIOS_PRIVATE | |
37 | #include "intel_vbt_defs.h" | |
79e53945 | 38 | |
dd97950a JN |
39 | /** |
40 | * DOC: Video BIOS Table (VBT) | |
41 | * | |
42 | * The Video BIOS Table, or VBT, provides platform and board specific | |
43 | * configuration information to the driver that is not discoverable or available | |
44 | * through other means. The configuration is mostly related to display | |
45 | * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in | |
46 | * the PCI ROM. | |
47 | * | |
48 | * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB | |
49 | * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that | |
50 | * contain the actual configuration information. The VBT Header, and thus the | |
51 | * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the | |
52 | * BDB Header. The data blocks are concatenated after the BDB Header. The data | |
53 | * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of | |
54 | * data. (Block 53, the MIPI Sequence Block is an exception.) | |
55 | * | |
56 | * The driver parses the VBT during load. The relevant information is stored in | |
57 | * driver private data for ease of use, and the actual VBT is not read after | |
58 | * that. | |
59 | */ | |
60 | ||
9b9d172d | 61 | #define SLAVE_ADDR1 0x70 |
62 | #define SLAVE_ADDR2 0x72 | |
79e53945 | 63 | |
08c0888b JN |
64 | /* Get BDB block size given a pointer to Block ID. */ |
65 | static u32 _get_blocksize(const u8 *block_base) | |
66 | { | |
67 | /* The MIPI Sequence Block v3+ has a separate size field. */ | |
68 | if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) | |
69 | return *((const u32 *)(block_base + 4)); | |
70 | else | |
71 | return *((const u16 *)(block_base + 1)); | |
72 | } | |
73 | ||
74 | /* Get BDB block size give a pointer to data after Block ID and Block Size. */ | |
75 | static u32 get_blocksize(const void *block_data) | |
76 | { | |
77 | return _get_blocksize(block_data - 3); | |
78 | } | |
79 | ||
e8ef3b4c | 80 | static const void * |
f41c6153 | 81 | find_section(const void *_bdb, enum bdb_block_id section_id) |
79e53945 | 82 | { |
e8ef3b4c JN |
83 | const struct bdb_header *bdb = _bdb; |
84 | const u8 *base = _bdb; | |
79e53945 | 85 | int index = 0; |
cd67d226 | 86 | u32 total, current_size; |
f41c6153 | 87 | enum bdb_block_id current_id; |
79e53945 JB |
88 | |
89 | /* skip to first section */ | |
90 | index += bdb->header_size; | |
91 | total = bdb->bdb_size; | |
92 | ||
93 | /* walk the sections looking for section_id */ | |
d1f13fd2 | 94 | while (index + 3 < total) { |
79e53945 | 95 | current_id = *(base + index); |
08c0888b JN |
96 | current_size = _get_blocksize(base + index); |
97 | index += 3; | |
cd67d226 | 98 | |
d1f13fd2 CW |
99 | if (index + current_size > total) |
100 | return NULL; | |
101 | ||
79e53945 JB |
102 | if (current_id == section_id) |
103 | return base + index; | |
d1f13fd2 | 104 | |
79e53945 JB |
105 | index += current_size; |
106 | } | |
107 | ||
108 | return NULL; | |
109 | } | |
110 | ||
79e53945 | 111 | static void |
88631706 | 112 | fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, |
99834ea4 | 113 | const struct lvds_dvo_timing *dvo_timing) |
88631706 ML |
114 | { |
115 | panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | | |
116 | dvo_timing->hactive_lo; | |
117 | panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + | |
118 | ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); | |
119 | panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + | |
ce2e87b4 VT |
120 | ((dvo_timing->hsync_pulse_width_hi << 8) | |
121 | dvo_timing->hsync_pulse_width_lo); | |
88631706 ML |
122 | panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + |
123 | ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); | |
124 | ||
125 | panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | | |
126 | dvo_timing->vactive_lo; | |
127 | panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + | |
ce2e87b4 | 128 | ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo); |
88631706 | 129 | panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + |
ce2e87b4 VT |
130 | ((dvo_timing->vsync_pulse_width_hi << 4) | |
131 | dvo_timing->vsync_pulse_width_lo); | |
88631706 ML |
132 | panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + |
133 | ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); | |
134 | panel_fixed_mode->clock = dvo_timing->clock * 10; | |
135 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
136 | ||
9bc35499 AJ |
137 | if (dvo_timing->hsync_positive) |
138 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
139 | else | |
140 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
141 | ||
142 | if (dvo_timing->vsync_positive) | |
143 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
144 | else | |
145 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
146 | ||
df457245 VS |
147 | panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) | |
148 | dvo_timing->himage_lo; | |
149 | panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) | | |
150 | dvo_timing->vimage_lo; | |
151 | ||
88631706 ML |
152 | /* Some VBTs have bogus h/vtotal values */ |
153 | if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) | |
154 | panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; | |
155 | if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) | |
156 | panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; | |
157 | ||
158 | drm_mode_set_name(panel_fixed_mode); | |
159 | } | |
160 | ||
99834ea4 CW |
161 | static const struct lvds_dvo_timing * |
162 | get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data, | |
163 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs, | |
164 | int index) | |
165 | { | |
166 | /* | |
167 | * the size of fp_timing varies on the different platform. | |
168 | * So calculate the DVO timing relative offset in LVDS data | |
169 | * entry to get the DVO timing entry | |
170 | */ | |
171 | ||
172 | int lfp_data_size = | |
173 | lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset - | |
174 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset; | |
175 | int dvo_timing_offset = | |
176 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset - | |
177 | lvds_lfp_data_ptrs->ptr[0].fp_timing_offset; | |
178 | char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index; | |
179 | ||
180 | return (struct lvds_dvo_timing *)(entry + dvo_timing_offset); | |
181 | } | |
182 | ||
b0354385 TI |
183 | /* get lvds_fp_timing entry |
184 | * this function may return NULL if the corresponding entry is invalid | |
185 | */ | |
186 | static const struct lvds_fp_timing * | |
187 | get_lvds_fp_timing(const struct bdb_header *bdb, | |
188 | const struct bdb_lvds_lfp_data *data, | |
189 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
190 | int index) | |
191 | { | |
192 | size_t data_ofs = (const u8 *)data - (const u8 *)bdb; | |
193 | u16 data_size = ((const u16 *)data)[-1]; /* stored in header */ | |
194 | size_t ofs; | |
195 | ||
196 | if (index >= ARRAY_SIZE(ptrs->ptr)) | |
197 | return NULL; | |
198 | ofs = ptrs->ptr[index].fp_timing_offset; | |
199 | if (ofs < data_ofs || | |
200 | ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size) | |
201 | return NULL; | |
202 | return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs); | |
203 | } | |
204 | ||
88631706 ML |
205 | /* Try to find integrated panel data */ |
206 | static void | |
207 | parse_lfp_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 208 | const struct bdb_header *bdb) |
79e53945 | 209 | { |
99834ea4 CW |
210 | const struct bdb_lvds_options *lvds_options; |
211 | const struct bdb_lvds_lfp_data *lvds_lfp_data; | |
212 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; | |
213 | const struct lvds_dvo_timing *panel_dvo_timing; | |
b0354385 | 214 | const struct lvds_fp_timing *fp_timing; |
79e53945 | 215 | struct drm_display_mode *panel_fixed_mode; |
3e845c7a | 216 | int panel_type; |
c329a4ec | 217 | int drrs_mode; |
a0562819 | 218 | int ret; |
79e53945 | 219 | |
79e53945 JB |
220 | lvds_options = find_section(bdb, BDB_LVDS_OPTIONS); |
221 | if (!lvds_options) | |
222 | return; | |
223 | ||
41aa3448 | 224 | dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; |
a0562819 | 225 | |
6f9f4b7a | 226 | ret = intel_opregion_get_panel_type(dev_priv); |
a0562819 VS |
227 | if (ret >= 0) { |
228 | WARN_ON(ret > 0xf); | |
229 | panel_type = ret; | |
230 | DRM_DEBUG_KMS("Panel type: %d (OpRegion)\n", panel_type); | |
231 | } else { | |
232 | if (lvds_options->panel_type > 0xf) { | |
233 | DRM_DEBUG_KMS("Invalid VBT panel type 0x%x\n", | |
234 | lvds_options->panel_type); | |
235 | return; | |
236 | } | |
237 | panel_type = lvds_options->panel_type; | |
238 | DRM_DEBUG_KMS("Panel type: %d (VBT)\n", panel_type); | |
eeeebea6 | 239 | } |
6a04002b | 240 | |
3e845c7a | 241 | dev_priv->vbt.panel_type = panel_type; |
79e53945 | 242 | |
83a7280e PB |
243 | drrs_mode = (lvds_options->dps_panel_type_bits |
244 | >> (panel_type * 2)) & MODE_MASK; | |
245 | /* | |
246 | * VBT has static DRRS = 0 and seamless DRRS = 2. | |
247 | * The below piece of code is required to adjust vbt.drrs_type | |
248 | * to match the enum drrs_support_type. | |
249 | */ | |
250 | switch (drrs_mode) { | |
251 | case 0: | |
252 | dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; | |
253 | DRM_DEBUG_KMS("DRRS supported mode is static\n"); | |
254 | break; | |
255 | case 2: | |
256 | dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; | |
257 | DRM_DEBUG_KMS("DRRS supported mode is seamless\n"); | |
258 | break; | |
259 | default: | |
260 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
261 | DRM_DEBUG_KMS("DRRS not supported (VBT input)\n"); | |
262 | break; | |
263 | } | |
264 | ||
79e53945 JB |
265 | lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); |
266 | if (!lvds_lfp_data) | |
267 | return; | |
268 | ||
1b16de0b JB |
269 | lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS); |
270 | if (!lvds_lfp_data_ptrs) | |
271 | return; | |
272 | ||
99834ea4 CW |
273 | panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, |
274 | lvds_lfp_data_ptrs, | |
3e845c7a | 275 | panel_type); |
79e53945 | 276 | |
9a298b2a | 277 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
6edc3242 CW |
278 | if (!panel_fixed_mode) |
279 | return; | |
79e53945 | 280 | |
99834ea4 | 281 | fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); |
79e53945 | 282 | |
41aa3448 | 283 | dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 284 | |
28c97730 | 285 | DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n"); |
88631706 | 286 | drm_mode_debug_printmodeline(panel_fixed_mode); |
37df9673 | 287 | |
b0354385 TI |
288 | fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, |
289 | lvds_lfp_data_ptrs, | |
3e845c7a | 290 | panel_type); |
b0354385 TI |
291 | if (fp_timing) { |
292 | /* check the resolution, just to be sure */ | |
293 | if (fp_timing->x_res == panel_fixed_mode->hdisplay && | |
294 | fp_timing->y_res == panel_fixed_mode->vdisplay) { | |
41aa3448 | 295 | dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; |
b0354385 | 296 | DRM_DEBUG_KMS("VBT initial LVDS value %x\n", |
41aa3448 | 297 | dev_priv->vbt.bios_lvds_val); |
b0354385 TI |
298 | } |
299 | } | |
88631706 ML |
300 | } |
301 | ||
f00076d2 | 302 | static void |
dcb58a40 JN |
303 | parse_lfp_backlight(struct drm_i915_private *dev_priv, |
304 | const struct bdb_header *bdb) | |
f00076d2 JN |
305 | { |
306 | const struct bdb_lfp_backlight_data *backlight_data; | |
f87f6599 | 307 | const struct lfp_backlight_data_entry *entry; |
3e845c7a | 308 | int panel_type = dev_priv->vbt.panel_type; |
f00076d2 JN |
309 | |
310 | backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); | |
311 | if (!backlight_data) | |
312 | return; | |
313 | ||
314 | if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { | |
315 | DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n", | |
316 | backlight_data->entry_size); | |
317 | return; | |
318 | } | |
319 | ||
320 | entry = &backlight_data->data[panel_type]; | |
321 | ||
39fbc9c8 JN |
322 | dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; |
323 | if (!dev_priv->vbt.backlight.present) { | |
324 | DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n", | |
325 | entry->type); | |
326 | return; | |
327 | } | |
328 | ||
9a41e17d D |
329 | dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; |
330 | if (bdb->version >= 191 && | |
331 | get_blocksize(backlight_data) >= sizeof(*backlight_data)) { | |
f87f6599 | 332 | const struct lfp_backlight_control_method *method; |
9a41e17d D |
333 | |
334 | method = &backlight_data->backlight_control[panel_type]; | |
335 | dev_priv->vbt.backlight.type = method->type; | |
add03379 | 336 | dev_priv->vbt.backlight.controller = method->controller; |
9a41e17d D |
337 | } |
338 | ||
f00076d2 JN |
339 | dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; |
340 | dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm; | |
1de6068e | 341 | dev_priv->vbt.backlight.min_brightness = entry->min_brightness; |
f00076d2 | 342 | DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, " |
add03379 | 343 | "active %s, min brightness %u, level %u, controller %u\n", |
f00076d2 JN |
344 | dev_priv->vbt.backlight.pwm_freq_hz, |
345 | dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", | |
1de6068e | 346 | dev_priv->vbt.backlight.min_brightness, |
add03379 VS |
347 | backlight_data->level[panel_type], |
348 | dev_priv->vbt.backlight.controller); | |
f00076d2 JN |
349 | } |
350 | ||
88631706 ML |
351 | /* Try to find sdvo panel data */ |
352 | static void | |
353 | parse_sdvo_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 354 | const struct bdb_header *bdb) |
88631706 | 355 | { |
f87f6599 | 356 | const struct bdb_sdvo_panel_dtds *dtds; |
88631706 | 357 | struct drm_display_mode *panel_fixed_mode; |
5a1e5b6c | 358 | int index; |
79e53945 | 359 | |
4f044a88 | 360 | index = i915_modparams.vbt_sdvo_panel_type; |
c10e408a MF |
361 | if (index == -2) { |
362 | DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n"); | |
363 | return; | |
364 | } | |
365 | ||
5a1e5b6c | 366 | if (index == -1) { |
e8ef3b4c | 367 | const struct bdb_sdvo_lvds_options *sdvo_lvds_options; |
5a1e5b6c CW |
368 | |
369 | sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); | |
370 | if (!sdvo_lvds_options) | |
371 | return; | |
372 | ||
373 | index = sdvo_lvds_options->panel_type; | |
374 | } | |
88631706 | 375 | |
f87f6599 JN |
376 | dtds = find_section(bdb, BDB_SDVO_PANEL_DTDS); |
377 | if (!dtds) | |
88631706 ML |
378 | return; |
379 | ||
9a298b2a | 380 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
88631706 ML |
381 | if (!panel_fixed_mode) |
382 | return; | |
383 | ||
f87f6599 | 384 | fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]); |
88631706 | 385 | |
41aa3448 | 386 | dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 387 | |
5a1e5b6c CW |
388 | DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n"); |
389 | drm_mode_debug_printmodeline(panel_fixed_mode); | |
79e53945 JB |
390 | } |
391 | ||
98f3a1dc | 392 | static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, |
9a4114ff BF |
393 | bool alternate) |
394 | { | |
c56b89f1 | 395 | switch (INTEL_GEN(dev_priv)) { |
9a4114ff | 396 | case 2: |
e91e941b | 397 | return alternate ? 66667 : 48000; |
9a4114ff BF |
398 | case 3: |
399 | case 4: | |
e91e941b | 400 | return alternate ? 100000 : 96000; |
9a4114ff | 401 | default: |
e91e941b | 402 | return alternate ? 100000 : 120000; |
9a4114ff BF |
403 | } |
404 | } | |
405 | ||
79e53945 JB |
406 | static void |
407 | parse_general_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 408 | const struct bdb_header *bdb) |
79e53945 | 409 | { |
e8ef3b4c | 410 | const struct bdb_general_features *general; |
79e53945 | 411 | |
79e53945 | 412 | general = find_section(bdb, BDB_GENERAL_FEATURES); |
34957e8c JN |
413 | if (!general) |
414 | return; | |
415 | ||
416 | dev_priv->vbt.int_tv_support = general->int_tv_support; | |
417 | /* int_crt_support can't be trusted on earlier platforms */ | |
418 | if (bdb->version >= 155 && | |
419 | (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv))) | |
420 | dev_priv->vbt.int_crt_support = general->int_crt_support; | |
421 | dev_priv->vbt.lvds_use_ssc = general->enable_ssc; | |
422 | dev_priv->vbt.lvds_ssc_freq = | |
423 | intel_bios_ssc_frequency(dev_priv, general->ssc_freq); | |
424 | dev_priv->vbt.display_clock_mode = general->display_clock_mode; | |
425 | dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; | |
c1cd5b24 VS |
426 | if (bdb->version >= 181) { |
427 | dev_priv->vbt.orientation = general->rotate_180 ? | |
428 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP : | |
429 | DRM_MODE_PANEL_ORIENTATION_NORMAL; | |
430 | } else { | |
431 | dev_priv->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; | |
432 | } | |
34957e8c JN |
433 | DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", |
434 | dev_priv->vbt.int_tv_support, | |
435 | dev_priv->vbt.int_crt_support, | |
436 | dev_priv->vbt.lvds_use_ssc, | |
437 | dev_priv->vbt.lvds_ssc_freq, | |
438 | dev_priv->vbt.display_clock_mode, | |
439 | dev_priv->vbt.fdi_rx_polarity_inverted); | |
79e53945 JB |
440 | } |
441 | ||
cc998589 | 442 | static const struct child_device_config * |
e192839e | 443 | child_device_ptr(const struct bdb_general_definitions *defs, int i) |
90e4f159 | 444 | { |
e192839e | 445 | return (const void *) &defs->devices[i * defs->child_dev_size]; |
90e4f159 VS |
446 | } |
447 | ||
9b9d172d | 448 | static void |
0ead5f81 | 449 | parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) |
9b9d172d | 450 | { |
e192839e | 451 | struct sdvo_device_mapping *mapping; |
cc998589 | 452 | const struct child_device_config *child; |
0ebdabe6 | 453 | int i, count = 0; |
6cc38aca JN |
454 | |
455 | /* | |
0ebdabe6 JN |
456 | * Only parse SDVO mappings on gens that could have SDVO. This isn't |
457 | * accurate and doesn't have to be, as long as it's not too strict. | |
9b9d172d | 458 | */ |
00690008 | 459 | if (!IS_GEN_RANGE(dev_priv, 3, 7)) { |
0ebdabe6 | 460 | DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); |
9b9d172d | 461 | return; |
462 | } | |
0ebdabe6 JN |
463 | |
464 | for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
465 | child = dev_priv->vbt.child_dev + i; | |
466 | ||
6cc38aca JN |
467 | if (child->slave_addr != SLAVE_ADDR1 && |
468 | child->slave_addr != SLAVE_ADDR2) { | |
9b9d172d | 469 | /* |
470 | * If the slave address is neither 0x70 nor 0x72, | |
471 | * it is not a SDVO device. Skip it. | |
472 | */ | |
473 | continue; | |
474 | } | |
6cc38aca JN |
475 | if (child->dvo_port != DEVICE_PORT_DVOB && |
476 | child->dvo_port != DEVICE_PORT_DVOC) { | |
9b9d172d | 477 | /* skip the incorrect SDVO port */ |
0206e353 | 478 | DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n"); |
9b9d172d | 479 | continue; |
480 | } | |
28c97730 | 481 | DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on" |
6cc38aca JN |
482 | " %s port\n", |
483 | child->slave_addr, | |
484 | (child->dvo_port == DEVICE_PORT_DVOB) ? | |
485 | "SDVOB" : "SDVOC"); | |
e192839e JN |
486 | mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; |
487 | if (!mapping->initialized) { | |
488 | mapping->dvo_port = child->dvo_port; | |
489 | mapping->slave_addr = child->slave_addr; | |
490 | mapping->dvo_wiring = child->dvo_wiring; | |
491 | mapping->ddc_pin = child->ddc_pin; | |
492 | mapping->i2c_pin = child->i2c_pin; | |
493 | mapping->initialized = 1; | |
46eb3036 | 494 | DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", |
e192839e JN |
495 | mapping->dvo_port, |
496 | mapping->slave_addr, | |
497 | mapping->dvo_wiring, | |
498 | mapping->ddc_pin, | |
499 | mapping->i2c_pin); | |
9b9d172d | 500 | } else { |
28c97730 | 501 | DRM_DEBUG_KMS("Maybe one SDVO port is shared by " |
9b9d172d | 502 | "two SDVO device.\n"); |
503 | } | |
6cc38aca | 504 | if (child->slave2_addr) { |
9b9d172d | 505 | /* Maybe this is a SDVO device with multiple inputs */ |
506 | /* And the mapping info is not added */ | |
28c97730 ZY |
507 | DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this" |
508 | " is a SDVO device with multiple inputs.\n"); | |
9b9d172d | 509 | } |
510 | count++; | |
511 | } | |
512 | ||
513 | if (!count) { | |
514 | /* No SDVO device info is found */ | |
28c97730 | 515 | DRM_DEBUG_KMS("No SDVO device info is found in VBT\n"); |
9b9d172d | 516 | } |
9b9d172d | 517 | } |
32f9d658 ZW |
518 | |
519 | static void | |
520 | parse_driver_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 521 | const struct bdb_header *bdb) |
32f9d658 | 522 | { |
e8ef3b4c | 523 | const struct bdb_driver_features *driver; |
32f9d658 | 524 | |
32f9d658 | 525 | driver = find_section(bdb, BDB_DRIVER_FEATURES); |
652c393a JB |
526 | if (!driver) |
527 | return; | |
528 | ||
ca3b3fa3 VS |
529 | if (INTEL_GEN(dev_priv) >= 5) { |
530 | /* | |
531 | * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS | |
532 | * to mean "eDP". The VBT spec doesn't agree with that | |
533 | * interpretation, but real world VBTs seem to. | |
534 | */ | |
535 | if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) | |
536 | dev_priv->vbt.int_lvds_support = 0; | |
537 | } else { | |
538 | /* | |
539 | * FIXME it's not clear which BDB version has the LVDS config | |
540 | * bits defined. Revision history in the VBT spec says: | |
541 | * "0.92 | Add two definitions for VBT value of LVDS Active | |
542 | * Config (00b and 11b values defined) | 06/13/2005" | |
543 | * but does not the specify the BDB version. | |
544 | * | |
545 | * So far version 134 (on i945gm) is the oldest VBT observed | |
546 | * in the wild with the bits correctly populated. Version | |
547 | * 108 (on i85x) does not have the bits correctly populated. | |
548 | */ | |
549 | if (bdb->version >= 134 && | |
550 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && | |
551 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) | |
552 | dev_priv->vbt.int_lvds_support = 0; | |
553 | } | |
652c393a | 554 | |
83a7280e PB |
555 | DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled); |
556 | /* | |
557 | * If DRRS is not supported, drrs_type has to be set to 0. | |
558 | * This is because, VBT is configured in such a way that | |
559 | * static DRRS is 0 and DRRS not supported is represented by | |
560 | * driver->drrs_enabled=false | |
561 | */ | |
562 | if (!driver->drrs_enabled) | |
563 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
2bdd045e | 564 | dev_priv->vbt.psr.enable = driver->psr_enabled; |
32f9d658 ZW |
565 | } |
566 | ||
500a8cc4 | 567 | static void |
dcb58a40 | 568 | parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
500a8cc4 | 569 | { |
e8ef3b4c JN |
570 | const struct bdb_edp *edp; |
571 | const struct edp_power_seq *edp_pps; | |
058727ee | 572 | const struct edp_fast_link_params *edp_link_params; |
3e845c7a | 573 | int panel_type = dev_priv->vbt.panel_type; |
500a8cc4 ZW |
574 | |
575 | edp = find_section(bdb, BDB_EDP); | |
5255e2f8 | 576 | if (!edp) |
500a8cc4 | 577 | return; |
500a8cc4 ZW |
578 | |
579 | switch ((edp->color_depth >> (panel_type * 2)) & 3) { | |
580 | case EDP_18BPP: | |
6aa23e65 | 581 | dev_priv->vbt.edp.bpp = 18; |
500a8cc4 ZW |
582 | break; |
583 | case EDP_24BPP: | |
6aa23e65 | 584 | dev_priv->vbt.edp.bpp = 24; |
500a8cc4 ZW |
585 | break; |
586 | case EDP_30BPP: | |
6aa23e65 | 587 | dev_priv->vbt.edp.bpp = 30; |
500a8cc4 ZW |
588 | break; |
589 | } | |
5ceb0f9b | 590 | |
9f0e7ff4 JB |
591 | /* Get the eDP sequencing and link info */ |
592 | edp_pps = &edp->power_seqs[panel_type]; | |
058727ee | 593 | edp_link_params = &edp->fast_link_params[panel_type]; |
5ceb0f9b | 594 | |
6aa23e65 | 595 | dev_priv->vbt.edp.pps = *edp_pps; |
5ceb0f9b | 596 | |
e13e2b2c JN |
597 | switch (edp_link_params->rate) { |
598 | case EDP_RATE_1_62: | |
6aa23e65 | 599 | dev_priv->vbt.edp.rate = DP_LINK_BW_1_62; |
e13e2b2c JN |
600 | break; |
601 | case EDP_RATE_2_7: | |
6aa23e65 | 602 | dev_priv->vbt.edp.rate = DP_LINK_BW_2_7; |
e13e2b2c JN |
603 | break; |
604 | default: | |
605 | DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n", | |
606 | edp_link_params->rate); | |
607 | break; | |
608 | } | |
609 | ||
9f0e7ff4 | 610 | switch (edp_link_params->lanes) { |
e13e2b2c | 611 | case EDP_LANE_1: |
6aa23e65 | 612 | dev_priv->vbt.edp.lanes = 1; |
9f0e7ff4 | 613 | break; |
e13e2b2c | 614 | case EDP_LANE_2: |
6aa23e65 | 615 | dev_priv->vbt.edp.lanes = 2; |
9f0e7ff4 | 616 | break; |
e13e2b2c | 617 | case EDP_LANE_4: |
6aa23e65 | 618 | dev_priv->vbt.edp.lanes = 4; |
9f0e7ff4 | 619 | break; |
e13e2b2c JN |
620 | default: |
621 | DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n", | |
622 | edp_link_params->lanes); | |
623 | break; | |
9f0e7ff4 | 624 | } |
e13e2b2c | 625 | |
9f0e7ff4 | 626 | switch (edp_link_params->preemphasis) { |
e13e2b2c | 627 | case EDP_PREEMPHASIS_NONE: |
6aa23e65 | 628 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; |
9f0e7ff4 | 629 | break; |
e13e2b2c | 630 | case EDP_PREEMPHASIS_3_5dB: |
6aa23e65 | 631 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; |
9f0e7ff4 | 632 | break; |
e13e2b2c | 633 | case EDP_PREEMPHASIS_6dB: |
6aa23e65 | 634 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; |
9f0e7ff4 | 635 | break; |
e13e2b2c | 636 | case EDP_PREEMPHASIS_9_5dB: |
6aa23e65 | 637 | dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; |
9f0e7ff4 | 638 | break; |
e13e2b2c JN |
639 | default: |
640 | DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", | |
641 | edp_link_params->preemphasis); | |
642 | break; | |
9f0e7ff4 | 643 | } |
e13e2b2c | 644 | |
9f0e7ff4 | 645 | switch (edp_link_params->vswing) { |
e13e2b2c | 646 | case EDP_VSWING_0_4V: |
6aa23e65 | 647 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
9f0e7ff4 | 648 | break; |
e13e2b2c | 649 | case EDP_VSWING_0_6V: |
6aa23e65 | 650 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; |
9f0e7ff4 | 651 | break; |
e13e2b2c | 652 | case EDP_VSWING_0_8V: |
6aa23e65 | 653 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
9f0e7ff4 | 654 | break; |
e13e2b2c | 655 | case EDP_VSWING_1_2V: |
6aa23e65 | 656 | dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
9f0e7ff4 | 657 | break; |
e13e2b2c JN |
658 | default: |
659 | DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", | |
660 | edp_link_params->vswing); | |
661 | break; | |
9f0e7ff4 | 662 | } |
9a57f5bb SJ |
663 | |
664 | if (bdb->version >= 173) { | |
0ede0141 | 665 | u8 vswing; |
9a57f5bb | 666 | |
9e458034 | 667 | /* Don't read from VBT if module parameter has valid value*/ |
4f044a88 MW |
668 | if (i915_modparams.edp_vswing) { |
669 | dev_priv->vbt.edp.low_vswing = | |
670 | i915_modparams.edp_vswing == 1; | |
9e458034 SJ |
671 | } else { |
672 | vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; | |
06411f08 | 673 | dev_priv->vbt.edp.low_vswing = vswing == 0; |
9e458034 | 674 | } |
9a57f5bb | 675 | } |
500a8cc4 ZW |
676 | } |
677 | ||
bfd7ebda | 678 | static void |
dcb58a40 | 679 | parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
bfd7ebda | 680 | { |
e8ef3b4c JN |
681 | const struct bdb_psr *psr; |
682 | const struct psr_table *psr_table; | |
3e845c7a | 683 | int panel_type = dev_priv->vbt.panel_type; |
bfd7ebda RV |
684 | |
685 | psr = find_section(bdb, BDB_PSR); | |
686 | if (!psr) { | |
687 | DRM_DEBUG_KMS("No PSR BDB found.\n"); | |
688 | return; | |
689 | } | |
690 | ||
691 | psr_table = &psr->psr_table[panel_type]; | |
692 | ||
693 | dev_priv->vbt.psr.full_link = psr_table->full_link; | |
694 | dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; | |
695 | ||
696 | /* Allowed VBT values goes from 0 to 15 */ | |
697 | dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : | |
698 | psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; | |
699 | ||
700 | switch (psr_table->lines_to_wait) { | |
701 | case 0: | |
702 | dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; | |
703 | break; | |
704 | case 1: | |
705 | dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; | |
706 | break; | |
707 | case 2: | |
708 | dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; | |
709 | break; | |
710 | case 3: | |
711 | dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; | |
712 | break; | |
713 | default: | |
714 | DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n", | |
715 | psr_table->lines_to_wait); | |
716 | break; | |
717 | } | |
718 | ||
77312ae8 VN |
719 | /* |
720 | * New psr options 0=500us, 1=100us, 2=2500us, 3=0us | |
721 | * Old decimal value is wake up time in multiples of 100 us. | |
722 | */ | |
0fdb3f75 VN |
723 | if (bdb->version >= 205 && |
724 | (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || | |
725 | INTEL_GEN(dev_priv) >= 10)) { | |
77312ae8 VN |
726 | switch (psr_table->tp1_wakeup_time) { |
727 | case 0: | |
728 | dev_priv->vbt.psr.tp1_wakeup_time_us = 500; | |
729 | break; | |
730 | case 1: | |
731 | dev_priv->vbt.psr.tp1_wakeup_time_us = 100; | |
732 | break; | |
733 | case 3: | |
734 | dev_priv->vbt.psr.tp1_wakeup_time_us = 0; | |
735 | break; | |
736 | default: | |
737 | DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", | |
738 | psr_table->tp1_wakeup_time); | |
739 | /* fallthrough */ | |
740 | case 2: | |
741 | dev_priv->vbt.psr.tp1_wakeup_time_us = 2500; | |
742 | break; | |
743 | } | |
744 | ||
745 | switch (psr_table->tp2_tp3_wakeup_time) { | |
746 | case 0: | |
747 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500; | |
748 | break; | |
749 | case 1: | |
750 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100; | |
751 | break; | |
752 | case 3: | |
c238ad62 | 753 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0; |
77312ae8 VN |
754 | break; |
755 | default: | |
756 | DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", | |
757 | psr_table->tp2_tp3_wakeup_time); | |
758 | /* fallthrough */ | |
759 | case 2: | |
760 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500; | |
761 | break; | |
762 | } | |
763 | } else { | |
764 | dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; | |
765 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; | |
766 | } | |
88a0d960 JRS |
767 | |
768 | if (bdb->version >= 226) { | |
b5ea9c93 | 769 | u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; |
88a0d960 JRS |
770 | |
771 | wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; | |
772 | switch (wakeup_time) { | |
773 | case 0: | |
774 | wakeup_time = 500; | |
775 | break; | |
776 | case 1: | |
777 | wakeup_time = 100; | |
778 | break; | |
779 | case 3: | |
780 | wakeup_time = 50; | |
781 | break; | |
782 | default: | |
783 | case 2: | |
784 | wakeup_time = 2500; | |
785 | break; | |
786 | } | |
787 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time; | |
788 | } else { | |
789 | /* Reusing PSR1 wakeup time for PSR2 in older VBTs */ | |
790 | dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us; | |
791 | } | |
bfd7ebda RV |
792 | } |
793 | ||
46e58320 MC |
794 | static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, |
795 | u16 version, enum port port) | |
796 | { | |
797 | if (!dev_priv->vbt.dsi.config->dual_link || version < 197) { | |
798 | dev_priv->vbt.dsi.bl_ports = BIT(port); | |
799 | if (dev_priv->vbt.dsi.config->cabc_supported) | |
800 | dev_priv->vbt.dsi.cabc_ports = BIT(port); | |
801 | ||
46e58320 MC |
802 | return; |
803 | } | |
804 | ||
805 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
806 | case DL_DCS_PORT_A: | |
807 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_A); | |
808 | break; | |
809 | case DL_DCS_PORT_C: | |
810 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_C); | |
811 | break; | |
812 | default: | |
813 | case DL_DCS_PORT_A_AND_C: | |
814 | dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C); | |
815 | break; | |
816 | } | |
817 | ||
818 | if (!dev_priv->vbt.dsi.config->cabc_supported) | |
819 | return; | |
820 | ||
821 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
822 | case DL_DCS_PORT_A: | |
823 | dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A); | |
824 | break; | |
825 | case DL_DCS_PORT_C: | |
826 | dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C); | |
827 | break; | |
828 | default: | |
829 | case DL_DCS_PORT_A_AND_C: | |
830 | dev_priv->vbt.dsi.cabc_ports = | |
831 | BIT(PORT_A) | BIT(PORT_C); | |
832 | break; | |
833 | } | |
834 | } | |
835 | ||
d17c5443 | 836 | static void |
0f8689f5 JN |
837 | parse_mipi_config(struct drm_i915_private *dev_priv, |
838 | const struct bdb_header *bdb) | |
d17c5443 | 839 | { |
e8ef3b4c | 840 | const struct bdb_mipi_config *start; |
e8ef3b4c JN |
841 | const struct mipi_config *config; |
842 | const struct mipi_pps_data *pps; | |
3e845c7a | 843 | int panel_type = dev_priv->vbt.panel_type; |
46e58320 | 844 | enum port port; |
d3b542fc | 845 | |
3e6bd011 | 846 | /* parse MIPI blocks only if LFP type is MIPI */ |
46e58320 | 847 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
3e6bd011 SK |
848 | return; |
849 | ||
d3b542fc SK |
850 | /* Initialize this to undefined indicating no generic MIPI support */ |
851 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; | |
852 | ||
853 | /* Block #40 is already parsed and panel_fixed_mode is | |
854 | * stored in dev_priv->lfp_lvds_vbt_mode | |
855 | * resuse this when needed | |
856 | */ | |
d17c5443 | 857 | |
d3b542fc SK |
858 | /* Parse #52 for panel index used from panel_type already |
859 | * parsed | |
860 | */ | |
861 | start = find_section(bdb, BDB_MIPI_CONFIG); | |
862 | if (!start) { | |
863 | DRM_DEBUG_KMS("No MIPI config BDB found"); | |
d17c5443 SK |
864 | return; |
865 | } | |
866 | ||
d3b542fc SK |
867 | DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n", |
868 | panel_type); | |
869 | ||
870 | /* | |
871 | * get hold of the correct configuration block and pps data as per | |
872 | * the panel_type as index | |
873 | */ | |
874 | config = &start->config[panel_type]; | |
875 | pps = &start->pps[panel_type]; | |
876 | ||
877 | /* store as of now full data. Trim when we realise all is not needed */ | |
878 | dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); | |
879 | if (!dev_priv->vbt.dsi.config) | |
880 | return; | |
881 | ||
882 | dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); | |
883 | if (!dev_priv->vbt.dsi.pps) { | |
884 | kfree(dev_priv->vbt.dsi.config); | |
885 | return; | |
886 | } | |
887 | ||
46e58320 | 888 | parse_dsi_backlight_ports(dev_priv, bdb->version, port); |
9f7c5b17 | 889 | |
c1cd5b24 VS |
890 | /* FIXME is the 90 vs. 270 correct? */ |
891 | switch (config->rotation) { | |
892 | case ENABLE_ROTATION_0: | |
893 | /* | |
894 | * Most (all?) VBTs claim 0 degrees despite having | |
895 | * an upside down panel, thus we do not trust this. | |
896 | */ | |
897 | dev_priv->vbt.dsi.orientation = | |
898 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN; | |
899 | break; | |
900 | case ENABLE_ROTATION_90: | |
901 | dev_priv->vbt.dsi.orientation = | |
902 | DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; | |
903 | break; | |
904 | case ENABLE_ROTATION_180: | |
905 | dev_priv->vbt.dsi.orientation = | |
906 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; | |
907 | break; | |
908 | case ENABLE_ROTATION_270: | |
909 | dev_priv->vbt.dsi.orientation = | |
910 | DRM_MODE_PANEL_ORIENTATION_LEFT_UP; | |
911 | break; | |
912 | } | |
913 | ||
d3b542fc | 914 | /* We have mandatory mipi config blocks. Initialize as generic panel */ |
ea9a6baf | 915 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; |
0f8689f5 JN |
916 | } |
917 | ||
5db72099 JN |
918 | /* Find the sequence block and size for the given panel. */ |
919 | static const u8 * | |
920 | find_panel_sequence_block(const struct bdb_mipi_sequence *sequence, | |
2a33d934 | 921 | u16 panel_id, u32 *seq_size) |
5db72099 JN |
922 | { |
923 | u32 total = get_blocksize(sequence); | |
924 | const u8 *data = &sequence->data[0]; | |
925 | u8 current_id; | |
2a33d934 JN |
926 | u32 current_size; |
927 | int header_size = sequence->version >= 3 ? 5 : 3; | |
5db72099 JN |
928 | int index = 0; |
929 | int i; | |
930 | ||
2a33d934 JN |
931 | /* skip new block size */ |
932 | if (sequence->version >= 3) | |
933 | data += 4; | |
934 | ||
935 | for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { | |
936 | if (index + header_size > total) { | |
937 | DRM_ERROR("Invalid sequence block (header)\n"); | |
938 | return NULL; | |
939 | } | |
940 | ||
5db72099 | 941 | current_id = *(data + index); |
2a33d934 JN |
942 | if (sequence->version >= 3) |
943 | current_size = *((const u32 *)(data + index + 1)); | |
944 | else | |
945 | current_size = *((const u16 *)(data + index + 1)); | |
5db72099 | 946 | |
2a33d934 | 947 | index += header_size; |
5db72099 JN |
948 | |
949 | if (index + current_size > total) { | |
950 | DRM_ERROR("Invalid sequence block\n"); | |
951 | return NULL; | |
952 | } | |
953 | ||
954 | if (current_id == panel_id) { | |
955 | *seq_size = current_size; | |
956 | return data + index; | |
957 | } | |
958 | ||
959 | index += current_size; | |
960 | } | |
961 | ||
962 | DRM_ERROR("Sequence block detected but no valid configuration\n"); | |
963 | ||
964 | return NULL; | |
965 | } | |
966 | ||
8d3ed2f3 JN |
967 | static int goto_next_sequence(const u8 *data, int index, int total) |
968 | { | |
969 | u16 len; | |
970 | ||
971 | /* Skip Sequence Byte. */ | |
972 | for (index = index + 1; index < total; index += len) { | |
973 | u8 operation_byte = *(data + index); | |
974 | index++; | |
975 | ||
976 | switch (operation_byte) { | |
977 | case MIPI_SEQ_ELEM_END: | |
978 | return index; | |
979 | case MIPI_SEQ_ELEM_SEND_PKT: | |
980 | if (index + 4 > total) | |
981 | return 0; | |
982 | ||
983 | len = *((const u16 *)(data + index + 2)) + 4; | |
984 | break; | |
985 | case MIPI_SEQ_ELEM_DELAY: | |
986 | len = 4; | |
987 | break; | |
988 | case MIPI_SEQ_ELEM_GPIO: | |
989 | len = 2; | |
990 | break; | |
f4d64936 JN |
991 | case MIPI_SEQ_ELEM_I2C: |
992 | if (index + 7 > total) | |
993 | return 0; | |
994 | len = *(data + index + 6) + 7; | |
995 | break; | |
8d3ed2f3 JN |
996 | default: |
997 | DRM_ERROR("Unknown operation byte\n"); | |
998 | return 0; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
2a33d934 JN |
1005 | static int goto_next_sequence_v3(const u8 *data, int index, int total) |
1006 | { | |
1007 | int seq_end; | |
1008 | u16 len; | |
6765bd6d | 1009 | u32 size_of_sequence; |
2a33d934 JN |
1010 | |
1011 | /* | |
1012 | * Could skip sequence based on Size of Sequence alone, but also do some | |
1013 | * checking on the structure. | |
1014 | */ | |
1015 | if (total < 5) { | |
1016 | DRM_ERROR("Too small sequence size\n"); | |
1017 | return 0; | |
1018 | } | |
1019 | ||
6765bd6d JN |
1020 | /* Skip Sequence Byte. */ |
1021 | index++; | |
1022 | ||
1023 | /* | |
1024 | * Size of Sequence. Excludes the Sequence Byte and the size itself, | |
1025 | * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END | |
1026 | * byte. | |
1027 | */ | |
0ede0141 | 1028 | size_of_sequence = *((const u32 *)(data + index)); |
6765bd6d JN |
1029 | index += 4; |
1030 | ||
1031 | seq_end = index + size_of_sequence; | |
2a33d934 JN |
1032 | if (seq_end > total) { |
1033 | DRM_ERROR("Invalid sequence size\n"); | |
1034 | return 0; | |
1035 | } | |
1036 | ||
6765bd6d | 1037 | for (; index < total; index += len) { |
2a33d934 JN |
1038 | u8 operation_byte = *(data + index); |
1039 | index++; | |
1040 | ||
1041 | if (operation_byte == MIPI_SEQ_ELEM_END) { | |
1042 | if (index != seq_end) { | |
1043 | DRM_ERROR("Invalid element structure\n"); | |
1044 | return 0; | |
1045 | } | |
1046 | return index; | |
1047 | } | |
1048 | ||
1049 | len = *(data + index); | |
1050 | index++; | |
1051 | ||
1052 | /* | |
1053 | * FIXME: Would be nice to check elements like for v1/v2 in | |
1054 | * goto_next_sequence() above. | |
1055 | */ | |
1056 | switch (operation_byte) { | |
1057 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1058 | case MIPI_SEQ_ELEM_DELAY: | |
1059 | case MIPI_SEQ_ELEM_GPIO: | |
1060 | case MIPI_SEQ_ELEM_I2C: | |
1061 | case MIPI_SEQ_ELEM_SPI: | |
1062 | case MIPI_SEQ_ELEM_PMIC: | |
1063 | break; | |
1064 | default: | |
1065 | DRM_ERROR("Unknown operation byte %u\n", | |
1066 | operation_byte); | |
1067 | break; | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
fb38e7ad HG |
1074 | /* |
1075 | * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, | |
1076 | * skip all delay + gpio operands and stop at the first DSI packet op. | |
1077 | */ | |
1078 | static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv) | |
1079 | { | |
1080 | const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
1081 | int index, len; | |
1082 | ||
1083 | if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1)) | |
1084 | return 0; | |
1085 | ||
1086 | /* index = 1 to skip sequence byte */ | |
1087 | for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { | |
1088 | switch (data[index]) { | |
1089 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1090 | return index == 1 ? 0 : index; | |
1091 | case MIPI_SEQ_ELEM_DELAY: | |
1092 | len = 5; /* 1 byte for operand + uint32 */ | |
1093 | break; | |
1094 | case MIPI_SEQ_ELEM_GPIO: | |
1095 | len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ | |
1096 | break; | |
1097 | default: | |
1098 | return 0; | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
1105 | /* | |
1106 | * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. | |
1107 | * The deassert must be done before calling intel_dsi_device_ready, so for | |
1108 | * these devices we split the init OTP sequence into a deassert sequence and | |
1109 | * the actual init OTP part. | |
1110 | */ | |
1111 | static void fixup_mipi_sequences(struct drm_i915_private *dev_priv) | |
1112 | { | |
1113 | u8 *init_otp; | |
1114 | int len; | |
1115 | ||
1116 | /* Limit this to VLV for now. */ | |
1117 | if (!IS_VALLEYVIEW(dev_priv)) | |
1118 | return; | |
1119 | ||
1120 | /* Limit this to v1 vid-mode sequences */ | |
1121 | if (dev_priv->vbt.dsi.config->is_cmd_mode || | |
1122 | dev_priv->vbt.dsi.seq_version != 1) | |
1123 | return; | |
1124 | ||
1125 | /* Only do this if there are otp and assert seqs and no deassert seq */ | |
1126 | if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || | |
1127 | !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || | |
1128 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) | |
1129 | return; | |
1130 | ||
1131 | /* The deassert-sequence ends at the first DSI packet */ | |
1132 | len = get_init_otp_deassert_fragment_len(dev_priv); | |
1133 | if (!len) | |
1134 | return; | |
1135 | ||
1136 | DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n"); | |
1137 | ||
1138 | /* Copy the fragment, update seq byte and terminate it */ | |
1139 | init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
1140 | dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); | |
1141 | if (!dev_priv->vbt.dsi.deassert_seq) | |
1142 | return; | |
1143 | dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; | |
1144 | dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; | |
1145 | /* Use the copy for deassert */ | |
1146 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = | |
1147 | dev_priv->vbt.dsi.deassert_seq; | |
1148 | /* Replace the last byte of the fragment with init OTP seq byte */ | |
1149 | init_otp[len - 1] = MIPI_SEQ_INIT_OTP; | |
1150 | /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ | |
1151 | dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; | |
1152 | } | |
1153 | ||
0f8689f5 JN |
1154 | static void |
1155 | parse_mipi_sequence(struct drm_i915_private *dev_priv, | |
1156 | const struct bdb_header *bdb) | |
1157 | { | |
3e845c7a | 1158 | int panel_type = dev_priv->vbt.panel_type; |
0f8689f5 JN |
1159 | const struct bdb_mipi_sequence *sequence; |
1160 | const u8 *seq_data; | |
2a33d934 | 1161 | u32 seq_size; |
0f8689f5 | 1162 | u8 *data; |
8d3ed2f3 | 1163 | int index = 0; |
0f8689f5 JN |
1164 | |
1165 | /* Only our generic panel driver uses the sequence block. */ | |
1166 | if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) | |
1167 | return; | |
d3b542fc | 1168 | |
d3b542fc SK |
1169 | sequence = find_section(bdb, BDB_MIPI_SEQUENCE); |
1170 | if (!sequence) { | |
1171 | DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n"); | |
1172 | return; | |
1173 | } | |
1174 | ||
cd67d226 | 1175 | /* Fail gracefully for forward incompatible sequence block. */ |
2a33d934 JN |
1176 | if (sequence->version >= 4) { |
1177 | DRM_ERROR("Unable to parse MIPI Sequence Block v%u\n", | |
1178 | sequence->version); | |
cd67d226 JN |
1179 | return; |
1180 | } | |
1181 | ||
2a33d934 | 1182 | DRM_DEBUG_DRIVER("Found MIPI sequence block v%u\n", sequence->version); |
d3b542fc | 1183 | |
5db72099 JN |
1184 | seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size); |
1185 | if (!seq_data) | |
d3b542fc | 1186 | return; |
d3b542fc | 1187 | |
8d3ed2f3 JN |
1188 | data = kmemdup(seq_data, seq_size, GFP_KERNEL); |
1189 | if (!data) | |
d3b542fc SK |
1190 | return; |
1191 | ||
8d3ed2f3 JN |
1192 | /* Parse the sequences, store pointers to each sequence. */ |
1193 | for (;;) { | |
1194 | u8 seq_id = *(data + index); | |
1195 | if (seq_id == MIPI_SEQ_END) | |
1196 | break; | |
d3b542fc | 1197 | |
8d3ed2f3 JN |
1198 | if (seq_id >= MIPI_SEQ_MAX) { |
1199 | DRM_ERROR("Unknown sequence %u\n", seq_id); | |
d3b542fc SK |
1200 | goto err; |
1201 | } | |
1202 | ||
4b4f497e JN |
1203 | /* Log about presence of sequences we won't run. */ |
1204 | if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) | |
1205 | DRM_DEBUG_KMS("Unsupported sequence %u\n", seq_id); | |
1206 | ||
8d3ed2f3 | 1207 | dev_priv->vbt.dsi.sequence[seq_id] = data + index; |
d3b542fc | 1208 | |
2a33d934 JN |
1209 | if (sequence->version >= 3) |
1210 | index = goto_next_sequence_v3(data, index, seq_size); | |
1211 | else | |
1212 | index = goto_next_sequence(data, index, seq_size); | |
8d3ed2f3 JN |
1213 | if (!index) { |
1214 | DRM_ERROR("Invalid sequence %u\n", seq_id); | |
d3b542fc SK |
1215 | goto err; |
1216 | } | |
d3b542fc SK |
1217 | } |
1218 | ||
8d3ed2f3 JN |
1219 | dev_priv->vbt.dsi.data = data; |
1220 | dev_priv->vbt.dsi.size = seq_size; | |
1221 | dev_priv->vbt.dsi.seq_version = sequence->version; | |
1222 | ||
fb38e7ad HG |
1223 | fixup_mipi_sequences(dev_priv); |
1224 | ||
8d3ed2f3 | 1225 | DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n"); |
d3b542fc | 1226 | return; |
d3b542fc | 1227 | |
8d3ed2f3 JN |
1228 | err: |
1229 | kfree(data); | |
ed3b6679 | 1230 | memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence)); |
d17c5443 SK |
1231 | } |
1232 | ||
75067dde AK |
1233 | static u8 translate_iboost(u8 val) |
1234 | { | |
1235 | static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ | |
1236 | ||
1237 | if (val >= ARRAY_SIZE(mapping)) { | |
1238 | DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); | |
1239 | return 0; | |
1240 | } | |
1241 | return mapping[val]; | |
1242 | } | |
1243 | ||
cc21f011 JN |
1244 | static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin) |
1245 | { | |
1246 | const struct ddi_vbt_port_info *info; | |
1247 | enum port port; | |
1248 | ||
1249 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
1250 | info = &i915->vbt.ddi_port_info[port]; | |
1251 | ||
1252 | if (info->child && ddc_pin == info->alternate_ddc_pin) | |
1253 | return port; | |
1254 | } | |
1255 | ||
1256 | return PORT_NONE; | |
1257 | } | |
1258 | ||
9454fa87 VS |
1259 | static void sanitize_ddc_pin(struct drm_i915_private *dev_priv, |
1260 | enum port port) | |
1261 | { | |
36a0f920 | 1262 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
9454fa87 VS |
1263 | enum port p; |
1264 | ||
1265 | if (!info->alternate_ddc_pin) | |
1266 | return; | |
1267 | ||
cc21f011 JN |
1268 | p = get_port_by_ddc_pin(dev_priv, info->alternate_ddc_pin); |
1269 | if (p != PORT_NONE) { | |
9454fa87 VS |
1270 | DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, " |
1271 | "disabling port %c DVI/HDMI support\n", | |
36a0f920 JN |
1272 | port_name(port), info->alternate_ddc_pin, |
1273 | port_name(p), port_name(port)); | |
9454fa87 VS |
1274 | |
1275 | /* | |
1276 | * If we have multiple ports supposedly sharing the | |
1277 | * pin, then dvi/hdmi couldn't exist on the shared | |
1278 | * port. Otherwise they share the same ddc bin and | |
1279 | * system couldn't communicate with them separately. | |
1280 | * | |
36a0f920 JN |
1281 | * Give child device order the priority, first come first |
1282 | * served. | |
9454fa87 | 1283 | */ |
36a0f920 JN |
1284 | info->supports_dvi = false; |
1285 | info->supports_hdmi = false; | |
1286 | info->alternate_ddc_pin = 0; | |
9454fa87 VS |
1287 | } |
1288 | } | |
1289 | ||
cc21f011 JN |
1290 | static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch) |
1291 | { | |
1292 | const struct ddi_vbt_port_info *info; | |
1293 | enum port port; | |
1294 | ||
1295 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
1296 | info = &i915->vbt.ddi_port_info[port]; | |
1297 | ||
1298 | if (info->child && aux_ch == info->alternate_aux_channel) | |
1299 | return port; | |
1300 | } | |
1301 | ||
1302 | return PORT_NONE; | |
1303 | } | |
1304 | ||
9454fa87 VS |
1305 | static void sanitize_aux_ch(struct drm_i915_private *dev_priv, |
1306 | enum port port) | |
1307 | { | |
36a0f920 | 1308 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; |
9454fa87 VS |
1309 | enum port p; |
1310 | ||
1311 | if (!info->alternate_aux_channel) | |
1312 | return; | |
1313 | ||
cc21f011 JN |
1314 | p = get_port_by_aux_ch(dev_priv, info->alternate_aux_channel); |
1315 | if (p != PORT_NONE) { | |
9454fa87 VS |
1316 | DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, " |
1317 | "disabling port %c DP support\n", | |
36a0f920 JN |
1318 | port_name(port), info->alternate_aux_channel, |
1319 | port_name(p), port_name(port)); | |
9454fa87 VS |
1320 | |
1321 | /* | |
1322 | * If we have multiple ports supposedlt sharing the | |
1323 | * aux channel, then DP couldn't exist on the shared | |
1324 | * port. Otherwise they share the same aux channel | |
1325 | * and system couldn't communicate with them separately. | |
1326 | * | |
36a0f920 JN |
1327 | * Give child device order the priority, first come first |
1328 | * served. | |
9454fa87 | 1329 | */ |
36a0f920 JN |
1330 | info->supports_dp = false; |
1331 | info->alternate_aux_channel = 0; | |
9454fa87 VS |
1332 | } |
1333 | } | |
1334 | ||
9c3b2689 | 1335 | static const u8 cnp_ddc_pin_map[] = { |
3393ce1e | 1336 | [0] = 0, /* N/A */ |
9c3b2689 RV |
1337 | [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT, |
1338 | [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT, | |
1339 | [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */ | |
1340 | [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */ | |
1341 | }; | |
1342 | ||
3937eb1a | 1343 | static const u8 icp_ddc_pin_map[] = { |
d757535e MK |
1344 | [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, |
1345 | [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT, | |
1346 | [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT, | |
1347 | [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP, | |
1348 | [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP, | |
1349 | [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP, | |
1350 | [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP, | |
1351 | [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP, | |
1352 | [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP, | |
1353 | }; | |
1354 | ||
9c3b2689 RV |
1355 | static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) |
1356 | { | |
3937eb1a RS |
1357 | const u8 *ddc_pin_map; |
1358 | int n_entries; | |
1359 | ||
5a6b7ef6 | 1360 | if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { |
3937eb1a RS |
1361 | ddc_pin_map = icp_ddc_pin_map; |
1362 | n_entries = ARRAY_SIZE(icp_ddc_pin_map); | |
1363 | } else if (HAS_PCH_CNP(dev_priv)) { | |
1364 | ddc_pin_map = cnp_ddc_pin_map; | |
1365 | n_entries = ARRAY_SIZE(cnp_ddc_pin_map); | |
1366 | } else { | |
1367 | /* Assuming direct map */ | |
1368 | return vbt_pin; | |
a8e6f388 | 1369 | } |
9c3b2689 | 1370 | |
3937eb1a RS |
1371 | if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) |
1372 | return ddc_pin_map[vbt_pin]; | |
1373 | ||
1374 | DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", | |
1375 | vbt_pin); | |
1376 | return 0; | |
9c3b2689 RV |
1377 | } |
1378 | ||
b024ab9b | 1379 | static enum port dvo_port_to_port(u8 dvo_port) |
6acab15a | 1380 | { |
b024ab9b JN |
1381 | /* |
1382 | * Each DDI port can have more than one value on the "DVO Port" field, | |
b5273d72 JN |
1383 | * so look for all the possible values for each port. |
1384 | */ | |
b024ab9b JN |
1385 | static const int dvo_ports[][3] = { |
1386 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, | |
1387 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, | |
1388 | [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1}, | |
1389 | [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1}, | |
1390 | [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, | |
1391 | [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1}, | |
6acab15a | 1392 | }; |
b024ab9b JN |
1393 | enum port port; |
1394 | int i; | |
6acab15a | 1395 | |
b024ab9b JN |
1396 | for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) { |
1397 | for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) { | |
1398 | if (dvo_ports[port][i] == -1) | |
6acab15a PZ |
1399 | break; |
1400 | ||
b024ab9b JN |
1401 | if (dvo_port == dvo_ports[port][i]) |
1402 | return port; | |
6acab15a PZ |
1403 | } |
1404 | } | |
b024ab9b JN |
1405 | |
1406 | return PORT_NONE; | |
1407 | } | |
1408 | ||
1409 | static void parse_ddi_port(struct drm_i915_private *dev_priv, | |
1410 | const struct child_device_config *child, | |
1411 | u8 bdb_version) | |
1412 | { | |
1413 | struct ddi_vbt_port_info *info; | |
1414 | bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; | |
1415 | enum port port; | |
1416 | ||
1417 | port = dvo_port_to_port(child->dvo_port); | |
1418 | if (port == PORT_NONE) | |
1419 | return; | |
1420 | ||
1421 | info = &dev_priv->vbt.ddi_port_info[port]; | |
1422 | ||
7679f9b8 | 1423 | if (info->child) { |
b024ab9b JN |
1424 | DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n", |
1425 | port_name(port)); | |
6acab15a | 1426 | return; |
b024ab9b JN |
1427 | } |
1428 | ||
cc998589 JN |
1429 | is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; |
1430 | is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
1431 | is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT; | |
1432 | is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; | |
1433 | is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); | |
554d6af5 | 1434 | |
2ba7d7e0 JN |
1435 | if (port == PORT_A && is_dvi) { |
1436 | DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n", | |
1437 | is_hdmi ? "/HDMI" : ""); | |
1438 | is_dvi = false; | |
1439 | is_hdmi = false; | |
1440 | } | |
1441 | ||
311a2094 PZ |
1442 | info->supports_dvi = is_dvi; |
1443 | info->supports_hdmi = is_hdmi; | |
1444 | info->supports_dp = is_dp; | |
a98d9c1d | 1445 | info->supports_edp = is_edp; |
311a2094 | 1446 | |
38b3416f ID |
1447 | if (bdb_version >= 195) |
1448 | info->supports_typec_usb = child->dp_usb_type_c; | |
1449 | ||
1450 | if (bdb_version >= 209) | |
1451 | info->supports_tbt = child->tbt; | |
1452 | ||
932cd154 JN |
1453 | DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d\n", |
1454 | port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, | |
1455 | HAS_LSPCON(dev_priv) && child->lspcon, | |
38b3416f | 1456 | info->supports_typec_usb, info->supports_tbt); |
554d6af5 PZ |
1457 | |
1458 | if (is_edp && is_dvi) | |
1459 | DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n", | |
1460 | port_name(port)); | |
1461 | if (is_crt && port != PORT_E) | |
1462 | DRM_DEBUG_KMS("Port %c is analog\n", port_name(port)); | |
1463 | if (is_crt && (is_dvi || is_dp)) | |
1464 | DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n", | |
1465 | port_name(port)); | |
1466 | if (is_dvi && (port == PORT_A || port == PORT_E)) | |
9b13494c | 1467 | DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port)); |
554d6af5 PZ |
1468 | if (!is_dvi && !is_dp && !is_crt) |
1469 | DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n", | |
1470 | port_name(port)); | |
1471 | if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E)) | |
1472 | DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); | |
6bf19e7c PZ |
1473 | |
1474 | if (is_dvi) { | |
e53a1058 JN |
1475 | u8 ddc_pin; |
1476 | ||
f212bf9a JN |
1477 | ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin); |
1478 | if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) { | |
1479 | info->alternate_ddc_pin = ddc_pin; | |
1480 | sanitize_ddc_pin(dev_priv, port); | |
1481 | } else { | |
1482 | DRM_DEBUG_KMS("Port %c has invalid DDC pin %d, " | |
1483 | "sticking to defaults\n", | |
1484 | port_name(port), ddc_pin); | |
1485 | } | |
6bf19e7c PZ |
1486 | } |
1487 | ||
1488 | if (is_dp) { | |
e53a1058 | 1489 | info->alternate_aux_channel = child->aux_channel; |
9454fa87 VS |
1490 | |
1491 | sanitize_aux_ch(dev_priv, port); | |
6bf19e7c PZ |
1492 | } |
1493 | ||
0ead5f81 | 1494 | if (bdb_version >= 158) { |
6acab15a | 1495 | /* The VBT HDMI level shift values match the table we have. */ |
e53a1058 | 1496 | u8 hdmi_level_shift = child->hdmi_level_shifter_value; |
ce4dd49e DL |
1497 | DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", |
1498 | port_name(port), | |
1499 | hdmi_level_shift); | |
1500 | info->hdmi_level_shift = hdmi_level_shift; | |
6acab15a | 1501 | } |
75067dde | 1502 | |
d6038611 VS |
1503 | if (bdb_version >= 204) { |
1504 | int max_tmds_clock; | |
1505 | ||
1506 | switch (child->hdmi_max_data_rate) { | |
1507 | default: | |
1508 | MISSING_CASE(child->hdmi_max_data_rate); | |
1509 | /* fall through */ | |
1510 | case HDMI_MAX_DATA_RATE_PLATFORM: | |
1511 | max_tmds_clock = 0; | |
1512 | break; | |
1513 | case HDMI_MAX_DATA_RATE_297: | |
1514 | max_tmds_clock = 297000; | |
1515 | break; | |
1516 | case HDMI_MAX_DATA_RATE_165: | |
1517 | max_tmds_clock = 165000; | |
1518 | break; | |
1519 | } | |
1520 | ||
1521 | if (max_tmds_clock) | |
1522 | DRM_DEBUG_KMS("VBT HDMI max TMDS clock for port %c: %d kHz\n", | |
1523 | port_name(port), max_tmds_clock); | |
1524 | info->max_tmds_clock = max_tmds_clock; | |
1525 | } | |
1526 | ||
75067dde | 1527 | /* Parse the I_boost config for SKL and above */ |
0ead5f81 | 1528 | if (bdb_version >= 196 && child->iboost) { |
f22bb358 | 1529 | info->dp_boost_level = translate_iboost(child->dp_iboost_level); |
75067dde AK |
1530 | DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n", |
1531 | port_name(port), info->dp_boost_level); | |
f22bb358 | 1532 | info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level); |
75067dde AK |
1533 | DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n", |
1534 | port_name(port), info->hdmi_boost_level); | |
1535 | } | |
99b91bda JN |
1536 | |
1537 | /* DP max link rate for CNL+ */ | |
1538 | if (bdb_version >= 216) { | |
1539 | switch (child->dp_max_link_rate) { | |
1540 | default: | |
1541 | case VBT_DP_MAX_LINK_RATE_HBR3: | |
1542 | info->dp_max_link_rate = 810000; | |
1543 | break; | |
1544 | case VBT_DP_MAX_LINK_RATE_HBR2: | |
1545 | info->dp_max_link_rate = 540000; | |
1546 | break; | |
1547 | case VBT_DP_MAX_LINK_RATE_HBR: | |
1548 | info->dp_max_link_rate = 270000; | |
1549 | break; | |
1550 | case VBT_DP_MAX_LINK_RATE_LBR: | |
1551 | info->dp_max_link_rate = 162000; | |
1552 | break; | |
1553 | } | |
1554 | DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n", | |
1555 | port_name(port), info->dp_max_link_rate); | |
1556 | } | |
7679f9b8 JN |
1557 | |
1558 | info->child = child; | |
6acab15a PZ |
1559 | } |
1560 | ||
0ead5f81 | 1561 | static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version) |
6acab15a | 1562 | { |
b024ab9b JN |
1563 | const struct child_device_config *child; |
1564 | int i; | |
6acab15a | 1565 | |
348e4058 | 1566 | if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6acab15a PZ |
1567 | return; |
1568 | ||
0ead5f81 | 1569 | if (bdb_version < 155) |
6acab15a PZ |
1570 | return; |
1571 | ||
b024ab9b JN |
1572 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
1573 | child = dev_priv->vbt.child_dev + i; | |
1574 | ||
1575 | parse_ddi_port(dev_priv, child, bdb_version); | |
1576 | } | |
6acab15a PZ |
1577 | } |
1578 | ||
6363ee6f | 1579 | static void |
b3ca1f43 JN |
1580 | parse_general_definitions(struct drm_i915_private *dev_priv, |
1581 | const struct bdb_header *bdb) | |
6363ee6f | 1582 | { |
e192839e JN |
1583 | const struct bdb_general_definitions *defs; |
1584 | const struct child_device_config *child; | |
6363ee6f | 1585 | int i, child_device_num, count; |
e2d6cf7f DW |
1586 | u8 expected_size; |
1587 | u16 block_size; | |
b3ca1f43 | 1588 | int bus_pin; |
6363ee6f | 1589 | |
e192839e JN |
1590 | defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); |
1591 | if (!defs) { | |
44834a67 | 1592 | DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); |
6363ee6f ZY |
1593 | return; |
1594 | } | |
b3ca1f43 JN |
1595 | |
1596 | block_size = get_blocksize(defs); | |
1597 | if (block_size < sizeof(*defs)) { | |
1598 | DRM_DEBUG_KMS("General definitions block too small (%u)\n", | |
1599 | block_size); | |
1600 | return; | |
1601 | } | |
1602 | ||
1603 | bus_pin = defs->crt_ddc_gmbus_pin; | |
1604 | DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin); | |
1605 | if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) | |
1606 | dev_priv->vbt.crt_ddc_pin = bus_pin; | |
1607 | ||
7244f309 VS |
1608 | if (bdb->version < 106) { |
1609 | expected_size = 22; | |
fa05178c | 1610 | } else if (bdb->version < 111) { |
52b69c84 VS |
1611 | expected_size = 27; |
1612 | } else if (bdb->version < 195) { | |
21907e72 | 1613 | expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; |
e2d6cf7f DW |
1614 | } else if (bdb->version == 195) { |
1615 | expected_size = 37; | |
c4fb60b9 | 1616 | } else if (bdb->version <= 215) { |
e2d6cf7f | 1617 | expected_size = 38; |
c4fb60b9 JN |
1618 | } else if (bdb->version <= 216) { |
1619 | expected_size = 39; | |
e2d6cf7f | 1620 | } else { |
c4fb60b9 JN |
1621 | expected_size = sizeof(*child); |
1622 | BUILD_BUG_ON(sizeof(*child) < 39); | |
e2d6cf7f DW |
1623 | DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n", |
1624 | bdb->version, expected_size); | |
1625 | } | |
1626 | ||
e2d6cf7f | 1627 | /* Flag an error for unexpected size, but continue anyway. */ |
e192839e | 1628 | if (defs->child_dev_size != expected_size) |
e2d6cf7f | 1629 | DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n", |
e192839e | 1630 | defs->child_dev_size, expected_size, bdb->version); |
e2d6cf7f | 1631 | |
52b69c84 | 1632 | /* The legacy sized child device config is the minimum we need. */ |
e192839e | 1633 | if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { |
52b69c84 | 1634 | DRM_DEBUG_KMS("Child device config size %u is too small.\n", |
e192839e | 1635 | defs->child_dev_size); |
52b69c84 VS |
1636 | return; |
1637 | } | |
1638 | ||
6363ee6f | 1639 | /* get the number of child device */ |
e192839e | 1640 | child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; |
6363ee6f ZY |
1641 | count = 0; |
1642 | /* get the number of child device that is present */ | |
1643 | for (i = 0; i < child_device_num; i++) { | |
e192839e | 1644 | child = child_device_ptr(defs, i); |
53f6b243 | 1645 | if (!child->device_type) |
6363ee6f | 1646 | continue; |
6363ee6f ZY |
1647 | count++; |
1648 | } | |
1649 | if (!count) { | |
0206e353 | 1650 | DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); |
6363ee6f ZY |
1651 | return; |
1652 | } | |
e192839e | 1653 | dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL); |
41aa3448 | 1654 | if (!dev_priv->vbt.child_dev) { |
6363ee6f ZY |
1655 | DRM_DEBUG_KMS("No memory space for child device\n"); |
1656 | return; | |
1657 | } | |
1658 | ||
41aa3448 | 1659 | dev_priv->vbt.child_dev_num = count; |
6363ee6f ZY |
1660 | count = 0; |
1661 | for (i = 0; i < child_device_num; i++) { | |
e192839e | 1662 | child = child_device_ptr(defs, i); |
53f6b243 | 1663 | if (!child->device_type) |
6363ee6f | 1664 | continue; |
3e6bd011 | 1665 | |
bdeb18db MR |
1666 | DRM_DEBUG_KMS("Found VBT child device with type 0x%x\n", |
1667 | child->device_type); | |
1668 | ||
e2d6cf7f DW |
1669 | /* |
1670 | * Copy as much as we know (sizeof) and is available | |
1671 | * (child_dev_size) of the child device. Accessing the data must | |
1672 | * depend on VBT version. | |
1673 | */ | |
127704f5 | 1674 | memcpy(dev_priv->vbt.child_dev + count, child, |
e192839e | 1675 | min_t(size_t, defs->child_dev_size, sizeof(*child))); |
127704f5 | 1676 | count++; |
6363ee6f | 1677 | } |
6363ee6f | 1678 | } |
44834a67 | 1679 | |
bb1d1329 | 1680 | /* Common defaults which may be overridden by VBT. */ |
6a04002b SQ |
1681 | static void |
1682 | init_vbt_defaults(struct drm_i915_private *dev_priv) | |
1683 | { | |
6acab15a | 1684 | enum port port; |
9a4114ff | 1685 | |
988c7015 | 1686 | dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; |
6a04002b | 1687 | |
56c4b63a JN |
1688 | /* Default to having backlight */ |
1689 | dev_priv->vbt.backlight.present = true; | |
1690 | ||
6a04002b | 1691 | /* LFP panel data */ |
41aa3448 | 1692 | dev_priv->vbt.lvds_dither = 1; |
6a04002b SQ |
1693 | |
1694 | /* SDVO panel data */ | |
41aa3448 | 1695 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; |
6a04002b SQ |
1696 | |
1697 | /* general features */ | |
41aa3448 RV |
1698 | dev_priv->vbt.int_tv_support = 1; |
1699 | dev_priv->vbt.int_crt_support = 1; | |
9a4114ff | 1700 | |
5255e2f8 VS |
1701 | /* driver features */ |
1702 | dev_priv->vbt.int_lvds_support = 1; | |
1703 | ||
9a4114ff | 1704 | /* Default to using SSC */ |
41aa3448 | 1705 | dev_priv->vbt.lvds_use_ssc = 1; |
f69e5156 DL |
1706 | /* |
1707 | * Core/SandyBridge/IvyBridge use alternative (120MHz) reference | |
1708 | * clock for LVDS. | |
1709 | */ | |
98f3a1dc JN |
1710 | dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv, |
1711 | !HAS_PCH_SPLIT(dev_priv)); | |
e91e941b | 1712 | DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq); |
6acab15a PZ |
1713 | |
1714 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
311a2094 PZ |
1715 | struct ddi_vbt_port_info *info = |
1716 | &dev_priv->vbt.ddi_port_info[port]; | |
1717 | ||
ce4dd49e | 1718 | info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN; |
bb1d1329 JN |
1719 | } |
1720 | } | |
1721 | ||
1722 | /* Defaults to initialize only if there is no VBT. */ | |
1723 | static void | |
1724 | init_vbt_missing_defaults(struct drm_i915_private *dev_priv) | |
1725 | { | |
1726 | enum port port; | |
1727 | ||
1728 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
1729 | struct ddi_vbt_port_info *info = | |
1730 | &dev_priv->vbt.ddi_port_info[port]; | |
d8fe2ab6 | 1731 | enum phy phy = intel_port_to_phy(dev_priv, port); |
311a2094 | 1732 | |
828ccb31 ID |
1733 | /* |
1734 | * VBT has the TypeC mode (native,TBT/USB) and we don't want | |
1735 | * to detect it. | |
1736 | */ | |
d8fe2ab6 | 1737 | if (intel_phy_is_tc(dev_priv, phy)) |
828ccb31 ID |
1738 | continue; |
1739 | ||
311a2094 PZ |
1740 | info->supports_dvi = (port != PORT_A && port != PORT_E); |
1741 | info->supports_hdmi = info->supports_dvi; | |
1742 | info->supports_dp = (port != PORT_E); | |
2131bc0c | 1743 | info->supports_edp = (port == PORT_A); |
6acab15a | 1744 | } |
6a04002b SQ |
1745 | } |
1746 | ||
caf37fa4 JN |
1747 | static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) |
1748 | { | |
1749 | const void *_vbt = vbt; | |
1750 | ||
1751 | return _vbt + vbt->bdb_offset; | |
1752 | } | |
1753 | ||
f0067a31 JN |
1754 | /** |
1755 | * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT | |
1756 | * @buf: pointer to a buffer to validate | |
1757 | * @size: size of the buffer | |
1758 | * | |
1759 | * Returns true on valid VBT. | |
1760 | */ | |
1761 | bool intel_bios_is_valid_vbt(const void *buf, size_t size) | |
3dd4e846 | 1762 | { |
f0067a31 | 1763 | const struct vbt_header *vbt = buf; |
dcb58a40 | 1764 | const struct bdb_header *bdb; |
3dd4e846 | 1765 | |
caf37fa4 | 1766 | if (!vbt) |
f0067a31 | 1767 | return false; |
caf37fa4 | 1768 | |
f0067a31 | 1769 | if (sizeof(struct vbt_header) > size) { |
3dd4e846 | 1770 | DRM_DEBUG_DRIVER("VBT header incomplete\n"); |
f0067a31 | 1771 | return false; |
3dd4e846 CW |
1772 | } |
1773 | ||
1774 | if (memcmp(vbt->signature, "$VBT", 4)) { | |
1775 | DRM_DEBUG_DRIVER("VBT invalid signature\n"); | |
f0067a31 | 1776 | return false; |
3dd4e846 CW |
1777 | } |
1778 | ||
e8f9ae9b CW |
1779 | if (range_overflows_t(size_t, |
1780 | vbt->bdb_offset, | |
1781 | sizeof(struct bdb_header), | |
1782 | size)) { | |
3dd4e846 | 1783 | DRM_DEBUG_DRIVER("BDB header incomplete\n"); |
f0067a31 | 1784 | return false; |
3dd4e846 CW |
1785 | } |
1786 | ||
caf37fa4 | 1787 | bdb = get_bdb_header(vbt); |
e8f9ae9b | 1788 | if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { |
3dd4e846 | 1789 | DRM_DEBUG_DRIVER("BDB incomplete\n"); |
f0067a31 | 1790 | return false; |
3dd4e846 CW |
1791 | } |
1792 | ||
caf37fa4 | 1793 | return vbt; |
3dd4e846 CW |
1794 | } |
1795 | ||
caf37fa4 | 1796 | static const struct vbt_header *find_vbt(void __iomem *bios, size_t size) |
b34a991a | 1797 | { |
b34a991a JN |
1798 | size_t i; |
1799 | ||
1800 | /* Scour memory looking for the VBT signature. */ | |
1801 | for (i = 0; i + 4 < size; i++) { | |
f0067a31 | 1802 | void *vbt; |
115719fc | 1803 | |
f0067a31 JN |
1804 | if (ioread32(bios + i) != *((const u32 *) "$VBT")) |
1805 | continue; | |
1806 | ||
1807 | /* | |
1808 | * This is the one place where we explicitly discard the address | |
1809 | * space (__iomem) of the BIOS/VBT. | |
1810 | */ | |
1811 | vbt = (void __force *) bios + i; | |
1812 | if (intel_bios_is_valid_vbt(vbt, size - i)) | |
1813 | return vbt; | |
1814 | ||
1815 | break; | |
b34a991a JN |
1816 | } |
1817 | ||
f0067a31 | 1818 | return NULL; |
b34a991a JN |
1819 | } |
1820 | ||
79e53945 | 1821 | /** |
8b8e1a89 | 1822 | * intel_bios_init - find VBT and initialize settings from the BIOS |
dd97950a | 1823 | * @dev_priv: i915 device instance |
79e53945 | 1824 | * |
66578857 JN |
1825 | * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT |
1826 | * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also | |
1827 | * initialize some defaults if the VBT is not present at all. | |
79e53945 | 1828 | */ |
66578857 | 1829 | void intel_bios_init(struct drm_i915_private *dev_priv) |
79e53945 | 1830 | { |
91c8a326 | 1831 | struct pci_dev *pdev = dev_priv->drm.pdev; |
f0067a31 | 1832 | const struct vbt_header *vbt = dev_priv->opregion.vbt; |
caf37fa4 | 1833 | const struct bdb_header *bdb; |
44834a67 CW |
1834 | u8 __iomem *bios = NULL; |
1835 | ||
a2b69ea4 | 1836 | if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) { |
66578857 JN |
1837 | DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n"); |
1838 | return; | |
1839 | } | |
ab5c608b | 1840 | |
6a04002b | 1841 | init_vbt_defaults(dev_priv); |
f899fc64 | 1842 | |
66578857 | 1843 | /* If the OpRegion does not have VBT, look in PCI ROM. */ |
f0067a31 | 1844 | if (!vbt) { |
b34a991a | 1845 | size_t size; |
79e53945 | 1846 | |
44834a67 CW |
1847 | bios = pci_map_rom(pdev, &size); |
1848 | if (!bios) | |
66578857 | 1849 | goto out; |
44834a67 | 1850 | |
caf37fa4 | 1851 | vbt = find_vbt(bios, size); |
66578857 JN |
1852 | if (!vbt) |
1853 | goto out; | |
e2051c44 JN |
1854 | |
1855 | DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n"); | |
44834a67 | 1856 | } |
79e53945 | 1857 | |
caf37fa4 JN |
1858 | bdb = get_bdb_header(vbt); |
1859 | ||
3556dd40 JN |
1860 | DRM_DEBUG_KMS("VBT signature \"%.*s\", BDB version %d\n", |
1861 | (int)sizeof(vbt->signature), vbt->signature, bdb->version); | |
e2051c44 | 1862 | |
79e53945 JB |
1863 | /* Grab useful general definitions */ |
1864 | parse_general_features(dev_priv, bdb); | |
db545019 | 1865 | parse_general_definitions(dev_priv, bdb); |
88631706 | 1866 | parse_lfp_panel_data(dev_priv, bdb); |
f00076d2 | 1867 | parse_lfp_backlight(dev_priv, bdb); |
88631706 | 1868 | parse_sdvo_panel_data(dev_priv, bdb); |
32f9d658 | 1869 | parse_driver_features(dev_priv, bdb); |
500a8cc4 | 1870 | parse_edp(dev_priv, bdb); |
bfd7ebda | 1871 | parse_psr(dev_priv, bdb); |
0f8689f5 JN |
1872 | parse_mipi_config(dev_priv, bdb); |
1873 | parse_mipi_sequence(dev_priv, bdb); | |
0ebdabe6 JN |
1874 | |
1875 | /* Further processing on pre-parsed data */ | |
0ead5f81 JN |
1876 | parse_sdvo_device_mapping(dev_priv, bdb->version); |
1877 | parse_ddi_ports(dev_priv, bdb->version); | |
32f9d658 | 1878 | |
66578857 | 1879 | out: |
bb1d1329 | 1880 | if (!vbt) { |
66578857 | 1881 | DRM_INFO("Failed to find VBIOS tables (VBT)\n"); |
bb1d1329 JN |
1882 | init_vbt_missing_defaults(dev_priv); |
1883 | } | |
66578857 | 1884 | |
44834a67 CW |
1885 | if (bios) |
1886 | pci_unmap_rom(pdev, bios); | |
79e53945 | 1887 | } |
3bdd14d5 | 1888 | |
785f076b | 1889 | /** |
78dae1ac | 1890 | * intel_bios_driver_remove - Free any resources allocated by intel_bios_init() |
785f076b HG |
1891 | * @dev_priv: i915 device instance |
1892 | */ | |
78dae1ac | 1893 | void intel_bios_driver_remove(struct drm_i915_private *dev_priv) |
785f076b HG |
1894 | { |
1895 | kfree(dev_priv->vbt.child_dev); | |
1896 | dev_priv->vbt.child_dev = NULL; | |
1897 | dev_priv->vbt.child_dev_num = 0; | |
1898 | kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); | |
1899 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; | |
1900 | kfree(dev_priv->vbt.lfp_lvds_vbt_mode); | |
1901 | dev_priv->vbt.lfp_lvds_vbt_mode = NULL; | |
e1b86c85 HG |
1902 | kfree(dev_priv->vbt.dsi.data); |
1903 | dev_priv->vbt.dsi.data = NULL; | |
1904 | kfree(dev_priv->vbt.dsi.pps); | |
1905 | dev_priv->vbt.dsi.pps = NULL; | |
1906 | kfree(dev_priv->vbt.dsi.config); | |
1907 | dev_priv->vbt.dsi.config = NULL; | |
fb38e7ad HG |
1908 | kfree(dev_priv->vbt.dsi.deassert_seq); |
1909 | dev_priv->vbt.dsi.deassert_seq = NULL; | |
785f076b HG |
1910 | } |
1911 | ||
3bdd14d5 JN |
1912 | /** |
1913 | * intel_bios_is_tv_present - is integrated TV present in VBT | |
1914 | * @dev_priv: i915 device instance | |
1915 | * | |
1916 | * Return true if TV is present. If no child devices were parsed from VBT, | |
1917 | * assume TV is present. | |
1918 | */ | |
1919 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv) | |
1920 | { | |
cc998589 | 1921 | const struct child_device_config *child; |
3bdd14d5 JN |
1922 | int i; |
1923 | ||
1924 | if (!dev_priv->vbt.int_tv_support) | |
1925 | return false; | |
1926 | ||
1927 | if (!dev_priv->vbt.child_dev_num) | |
1928 | return true; | |
1929 | ||
1930 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 1931 | child = dev_priv->vbt.child_dev + i; |
3bdd14d5 JN |
1932 | /* |
1933 | * If the device type is not TV, continue. | |
1934 | */ | |
cc998589 | 1935 | switch (child->device_type) { |
3bdd14d5 JN |
1936 | case DEVICE_TYPE_INT_TV: |
1937 | case DEVICE_TYPE_TV: | |
1938 | case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: | |
1939 | break; | |
1940 | default: | |
1941 | continue; | |
1942 | } | |
1943 | /* Only when the addin_offset is non-zero, it is regarded | |
1944 | * as present. | |
1945 | */ | |
cc998589 | 1946 | if (child->addin_offset) |
3bdd14d5 JN |
1947 | return true; |
1948 | } | |
1949 | ||
1950 | return false; | |
1951 | } | |
5a69d13d JN |
1952 | |
1953 | /** | |
1954 | * intel_bios_is_lvds_present - is LVDS present in VBT | |
1955 | * @dev_priv: i915 device instance | |
1956 | * @i2c_pin: i2c pin for LVDS if present | |
1957 | * | |
1958 | * Return true if LVDS is present. If no child devices were parsed from VBT, | |
1959 | * assume LVDS is present. | |
1960 | */ | |
1961 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin) | |
1962 | { | |
cc998589 | 1963 | const struct child_device_config *child; |
5a69d13d JN |
1964 | int i; |
1965 | ||
1966 | if (!dev_priv->vbt.child_dev_num) | |
1967 | return true; | |
1968 | ||
1969 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 1970 | child = dev_priv->vbt.child_dev + i; |
5a69d13d JN |
1971 | |
1972 | /* If the device type is not LFP, continue. | |
1973 | * We have to check both the new identifiers as well as the | |
1974 | * old for compatibility with some BIOSes. | |
1975 | */ | |
1976 | if (child->device_type != DEVICE_TYPE_INT_LFP && | |
1977 | child->device_type != DEVICE_TYPE_LFP) | |
1978 | continue; | |
1979 | ||
1980 | if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) | |
1981 | *i2c_pin = child->i2c_pin; | |
1982 | ||
1983 | /* However, we cannot trust the BIOS writers to populate | |
1984 | * the VBT correctly. Since LVDS requires additional | |
1985 | * information from AIM blocks, a non-zero addin offset is | |
1986 | * a good indicator that the LVDS is actually present. | |
1987 | */ | |
1988 | if (child->addin_offset) | |
1989 | return true; | |
1990 | ||
1991 | /* But even then some BIOS writers perform some black magic | |
1992 | * and instantiate the device without reference to any | |
1993 | * additional data. Trust that if the VBT was written into | |
1994 | * the OpRegion then they have validated the LVDS's existence. | |
1995 | */ | |
1996 | if (dev_priv->opregion.vbt) | |
1997 | return true; | |
1998 | } | |
1999 | ||
2000 | return false; | |
2001 | } | |
951d9efe | 2002 | |
22f35042 VS |
2003 | /** |
2004 | * intel_bios_is_port_present - is the specified digital port present | |
2005 | * @dev_priv: i915 device instance | |
2006 | * @port: port to check | |
2007 | * | |
2008 | * Return true if the device in %port is present. | |
2009 | */ | |
2010 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port) | |
2011 | { | |
cc998589 | 2012 | const struct child_device_config *child; |
22f35042 VS |
2013 | static const struct { |
2014 | u16 dp, hdmi; | |
2015 | } port_mapping[] = { | |
2016 | [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, | |
2017 | [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, | |
2018 | [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, | |
2019 | [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, | |
841b5ed7 | 2020 | [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, |
22f35042 VS |
2021 | }; |
2022 | int i; | |
2023 | ||
e9d49bb7 ID |
2024 | if (HAS_DDI(dev_priv)) { |
2025 | const struct ddi_vbt_port_info *port_info = | |
2026 | &dev_priv->vbt.ddi_port_info[port]; | |
2027 | ||
2028 | return port_info->supports_dp || | |
2029 | port_info->supports_dvi || | |
2030 | port_info->supports_hdmi; | |
2031 | } | |
2032 | ||
22f35042 VS |
2033 | /* FIXME maybe deal with port A as well? */ |
2034 | if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping)) | |
2035 | return false; | |
2036 | ||
2037 | if (!dev_priv->vbt.child_dev_num) | |
2038 | return false; | |
2039 | ||
2040 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 JN |
2041 | child = dev_priv->vbt.child_dev + i; |
2042 | ||
2043 | if ((child->dvo_port == port_mapping[port].dp || | |
2044 | child->dvo_port == port_mapping[port].hdmi) && | |
2045 | (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING | | |
2046 | DEVICE_TYPE_DISPLAYPORT_OUTPUT))) | |
22f35042 VS |
2047 | return true; |
2048 | } | |
2049 | ||
2050 | return false; | |
2051 | } | |
2052 | ||
951d9efe JN |
2053 | /** |
2054 | * intel_bios_is_port_edp - is the device in given port eDP | |
2055 | * @dev_priv: i915 device instance | |
2056 | * @port: port to check | |
2057 | * | |
2058 | * Return true if the device in %port is eDP. | |
2059 | */ | |
2060 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port) | |
2061 | { | |
cc998589 | 2062 | const struct child_device_config *child; |
951d9efe JN |
2063 | static const short port_mapping[] = { |
2064 | [PORT_B] = DVO_PORT_DPB, | |
2065 | [PORT_C] = DVO_PORT_DPC, | |
2066 | [PORT_D] = DVO_PORT_DPD, | |
2067 | [PORT_E] = DVO_PORT_DPE, | |
841b5ed7 | 2068 | [PORT_F] = DVO_PORT_DPF, |
951d9efe JN |
2069 | }; |
2070 | int i; | |
2071 | ||
a98d9c1d ID |
2072 | if (HAS_DDI(dev_priv)) |
2073 | return dev_priv->vbt.ddi_port_info[port].supports_edp; | |
2074 | ||
951d9efe JN |
2075 | if (!dev_priv->vbt.child_dev_num) |
2076 | return false; | |
2077 | ||
2078 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 2079 | child = dev_priv->vbt.child_dev + i; |
951d9efe | 2080 | |
cc998589 JN |
2081 | if (child->dvo_port == port_mapping[port] && |
2082 | (child->device_type & DEVICE_TYPE_eDP_BITS) == | |
951d9efe JN |
2083 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
2084 | return true; | |
2085 | } | |
2086 | ||
2087 | return false; | |
2088 | } | |
7137aec1 | 2089 | |
cc998589 | 2090 | static bool child_dev_is_dp_dual_mode(const struct child_device_config *child, |
7a17995a | 2091 | enum port port) |
d6199256 VS |
2092 | { |
2093 | static const struct { | |
2094 | u16 dp, hdmi; | |
2095 | } port_mapping[] = { | |
2096 | /* | |
2097 | * Buggy VBTs may declare DP ports as having | |
2098 | * HDMI type dvo_port :( So let's check both. | |
2099 | */ | |
2100 | [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, }, | |
2101 | [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, }, | |
2102 | [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, }, | |
2103 | [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, }, | |
841b5ed7 | 2104 | [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, }, |
d6199256 | 2105 | }; |
d6199256 VS |
2106 | |
2107 | if (port == PORT_A || port >= ARRAY_SIZE(port_mapping)) | |
2108 | return false; | |
2109 | ||
cc998589 | 2110 | if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) != |
7a17995a | 2111 | (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS)) |
d6199256 VS |
2112 | return false; |
2113 | ||
cc998589 | 2114 | if (child->dvo_port == port_mapping[port].dp) |
7a17995a VS |
2115 | return true; |
2116 | ||
2117 | /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ | |
cc998589 JN |
2118 | if (child->dvo_port == port_mapping[port].hdmi && |
2119 | child->aux_channel != 0) | |
7a17995a VS |
2120 | return true; |
2121 | ||
2122 | return false; | |
2123 | } | |
2124 | ||
2125 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, | |
2126 | enum port port) | |
2127 | { | |
cc998589 | 2128 | const struct child_device_config *child; |
7a17995a VS |
2129 | int i; |
2130 | ||
d6199256 | 2131 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
cc998589 | 2132 | child = dev_priv->vbt.child_dev + i; |
d6199256 | 2133 | |
cc998589 | 2134 | if (child_dev_is_dp_dual_mode(child, port)) |
d6199256 VS |
2135 | return true; |
2136 | } | |
2137 | ||
2138 | return false; | |
2139 | } | |
2140 | ||
7137aec1 JN |
2141 | /** |
2142 | * intel_bios_is_dsi_present - is DSI present in VBT | |
2143 | * @dev_priv: i915 device instance | |
2144 | * @port: port for DSI if present | |
2145 | * | |
2146 | * Return true if DSI is present, and return the port in %port. | |
2147 | */ | |
2148 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, | |
2149 | enum port *port) | |
2150 | { | |
cc998589 | 2151 | const struct child_device_config *child; |
7137aec1 JN |
2152 | u8 dvo_port; |
2153 | int i; | |
2154 | ||
2155 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
cc998589 | 2156 | child = dev_priv->vbt.child_dev + i; |
7137aec1 | 2157 | |
cc998589 | 2158 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) |
7137aec1 JN |
2159 | continue; |
2160 | ||
cc998589 | 2161 | dvo_port = child->dvo_port; |
7137aec1 | 2162 | |
bf4d57ff | 2163 | if (dvo_port == DVO_PORT_MIPIA || |
2dd24a9c RV |
2164 | (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) || |
2165 | (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) { | |
7caaef33 JN |
2166 | if (port) |
2167 | *port = dvo_port - DVO_PORT_MIPIA; | |
7137aec1 | 2168 | return true; |
bf4d57ff MC |
2169 | } else if (dvo_port == DVO_PORT_MIPIB || |
2170 | dvo_port == DVO_PORT_MIPIC || | |
2171 | dvo_port == DVO_PORT_MIPID) { | |
7137aec1 JN |
2172 | DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n", |
2173 | port_name(dvo_port - DVO_PORT_MIPIA)); | |
7137aec1 JN |
2174 | } |
2175 | } | |
2176 | ||
2177 | return false; | |
2178 | } | |
d252bf68 SS |
2179 | |
2180 | /** | |
2181 | * intel_bios_is_port_hpd_inverted - is HPD inverted for %port | |
c72deaa4 | 2182 | * @i915: i915 device instance |
d252bf68 SS |
2183 | * @port: port to check |
2184 | * | |
2185 | * Return true if HPD should be inverted for %port. | |
2186 | */ | |
2187 | bool | |
c72deaa4 | 2188 | intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, |
d252bf68 SS |
2189 | enum port port) |
2190 | { | |
c72deaa4 JN |
2191 | const struct child_device_config *child = |
2192 | i915->vbt.ddi_port_info[port].child; | |
d252bf68 | 2193 | |
c72deaa4 | 2194 | if (WARN_ON_ONCE(!IS_GEN9_LP(i915))) |
d252bf68 SS |
2195 | return false; |
2196 | ||
c72deaa4 | 2197 | return child && child->hpd_invert; |
d252bf68 | 2198 | } |
6389dd83 SS |
2199 | |
2200 | /** | |
2201 | * intel_bios_is_lspcon_present - if LSPCON is attached on %port | |
a7475e5d | 2202 | * @i915: i915 device instance |
6389dd83 SS |
2203 | * @port: port to check |
2204 | * | |
2205 | * Return true if LSPCON is present on this port | |
2206 | */ | |
2207 | bool | |
a7475e5d JN |
2208 | intel_bios_is_lspcon_present(const struct drm_i915_private *i915, |
2209 | enum port port) | |
6389dd83 | 2210 | { |
a7475e5d JN |
2211 | const struct child_device_config *child = |
2212 | i915->vbt.ddi_port_info[port].child; | |
6389dd83 | 2213 | |
a7475e5d | 2214 | return HAS_LSPCON(i915) && child && child->lspcon; |
6389dd83 | 2215 | } |
15d248ae | 2216 | |
39053089 JN |
2217 | enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, |
2218 | enum port port) | |
15d248ae ID |
2219 | { |
2220 | const struct ddi_vbt_port_info *info = | |
2221 | &dev_priv->vbt.ddi_port_info[port]; | |
2222 | enum aux_ch aux_ch; | |
2223 | ||
2224 | if (!info->alternate_aux_channel) { | |
2225 | aux_ch = (enum aux_ch)port; | |
2226 | ||
2227 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", | |
2228 | aux_ch_name(aux_ch), port_name(port)); | |
2229 | return aux_ch; | |
2230 | } | |
2231 | ||
2232 | switch (info->alternate_aux_channel) { | |
2233 | case DP_AUX_A: | |
2234 | aux_ch = AUX_CH_A; | |
2235 | break; | |
2236 | case DP_AUX_B: | |
2237 | aux_ch = AUX_CH_B; | |
2238 | break; | |
2239 | case DP_AUX_C: | |
2240 | aux_ch = AUX_CH_C; | |
2241 | break; | |
2242 | case DP_AUX_D: | |
2243 | aux_ch = AUX_CH_D; | |
2244 | break; | |
2245 | case DP_AUX_E: | |
2246 | aux_ch = AUX_CH_E; | |
2247 | break; | |
2248 | case DP_AUX_F: | |
2249 | aux_ch = AUX_CH_F; | |
2250 | break; | |
2251 | default: | |
2252 | MISSING_CASE(info->alternate_aux_channel); | |
2253 | aux_ch = AUX_CH_A; | |
2254 | break; | |
2255 | } | |
2256 | ||
2257 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
2258 | aux_ch_name(aux_ch), port_name(port)); | |
2259 | ||
2260 | return aux_ch; | |
2261 | } |