Commit | Line | Data |
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fcfe0bdc MC |
1 | /* |
2 | * Copyright © 2018 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Madhav Chauhan <madhav.chauhan@intel.com> | |
25 | * Jani Nikula <jani.nikula@intel.com> | |
26 | */ | |
27 | ||
2a64b147 | 28 | #include <drm/display/drm_dsc_helper.h> |
e2758048 | 29 | #include <drm/drm_atomic_helper.h> |
fdc24cf3 JN |
30 | #include <drm/drm_mipi_dsi.h> |
31 | ||
801543b2 | 32 | #include "i915_reg.h" |
617ed6c2 | 33 | #include "icl_dsi.h" |
3c0deb14 | 34 | #include "icl_dsi_regs.h" |
12392a74 | 35 | #include "intel_atomic.h" |
6cc42fbe | 36 | #include "intel_backlight.h" |
a9b4c16d | 37 | #include "intel_backlight_regs.h" |
bd60a562 | 38 | #include "intel_combo_phy.h" |
d0864ee4 | 39 | #include "intel_combo_phy_regs.h" |
ec7f29ff | 40 | #include "intel_connector.h" |
7c53e628 | 41 | #include "intel_crtc.h" |
fdc24cf3 | 42 | #include "intel_ddi.h" |
7785ae0b | 43 | #include "intel_de.h" |
fcfe0bdc | 44 | #include "intel_dsi.h" |
aebdd742 | 45 | #include "intel_dsi_vbt.h" |
44c1220a | 46 | #include "intel_panel.h" |
2b68392e | 47 | #include "intel_vdsc.h" |
c3f05948 | 48 | #include "intel_vdsc_regs.h" |
714b1cdb | 49 | #include "skl_scaler.h" |
46d12f91 | 50 | #include "skl_universal_plane.h" |
fcfe0bdc | 51 | |
81b55ef1 JN |
52 | static int header_credits_available(struct drm_i915_private *dev_priv, |
53 | enum transcoder dsi_trans) | |
32bbc3d4 | 54 | { |
1c63f6df | 55 | return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) |
32bbc3d4 MC |
56 | >> FREE_HEADER_CREDIT_SHIFT; |
57 | } | |
58 | ||
81b55ef1 JN |
59 | static int payload_credits_available(struct drm_i915_private *dev_priv, |
60 | enum transcoder dsi_trans) | |
32bbc3d4 | 61 | { |
1c63f6df | 62 | return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) |
32bbc3d4 MC |
63 | >> FREE_PLOAD_CREDIT_SHIFT; |
64 | } | |
65 | ||
43315f86 LS |
66 | static bool wait_for_header_credits(struct drm_i915_private *dev_priv, |
67 | enum transcoder dsi_trans, int hdr_credit) | |
32bbc3d4 MC |
68 | { |
69 | if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= | |
43315f86 | 70 | hdr_credit, 100)) { |
b5280cd0 | 71 | drm_err(&dev_priv->drm, "DSI header credits not released\n"); |
43315f86 LS |
72 | return false; |
73 | } | |
74 | ||
75 | return true; | |
32bbc3d4 MC |
76 | } |
77 | ||
43315f86 LS |
78 | static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, |
79 | enum transcoder dsi_trans, int payld_credit) | |
32bbc3d4 MC |
80 | { |
81 | if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= | |
43315f86 | 82 | payld_credit, 100)) { |
b5280cd0 | 83 | drm_err(&dev_priv->drm, "DSI payload credits not released\n"); |
43315f86 LS |
84 | return false; |
85 | } | |
86 | ||
87 | return true; | |
32bbc3d4 MC |
88 | } |
89 | ||
d364dc66 | 90 | static enum transcoder dsi_port_to_transcoder(enum port port) |
ca8fc99f MC |
91 | { |
92 | if (port == PORT_A) | |
93 | return TRANSCODER_DSI_0; | |
94 | else | |
95 | return TRANSCODER_DSI_1; | |
96 | } | |
97 | ||
32bbc3d4 MC |
98 | static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) |
99 | { | |
100 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 101 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
32bbc3d4 MC |
102 | struct mipi_dsi_device *dsi; |
103 | enum port port; | |
104 | enum transcoder dsi_trans; | |
105 | int ret; | |
106 | ||
107 | /* wait for header/payload credits to be released */ | |
108 | for_each_dsi_port(port, intel_dsi->ports) { | |
109 | dsi_trans = dsi_port_to_transcoder(port); | |
43315f86 LS |
110 | wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); |
111 | wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); | |
32bbc3d4 MC |
112 | } |
113 | ||
114 | /* send nop DCS command */ | |
115 | for_each_dsi_port(port, intel_dsi->ports) { | |
116 | dsi = intel_dsi->dsi_hosts[port]->device; | |
117 | dsi->mode_flags |= MIPI_DSI_MODE_LPM; | |
118 | dsi->channel = 0; | |
119 | ret = mipi_dsi_dcs_nop(dsi); | |
120 | if (ret < 0) | |
b5280cd0 WK |
121 | drm_err(&dev_priv->drm, |
122 | "error sending DCS NOP command\n"); | |
32bbc3d4 MC |
123 | } |
124 | ||
125 | /* wait for header credits to be released */ | |
126 | for_each_dsi_port(port, intel_dsi->ports) { | |
127 | dsi_trans = dsi_port_to_transcoder(port); | |
43315f86 | 128 | wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); |
32bbc3d4 MC |
129 | } |
130 | ||
131 | /* wait for LP TX in progress bit to be cleared */ | |
132 | for_each_dsi_port(port, intel_dsi->ports) { | |
133 | dsi_trans = dsi_port_to_transcoder(port); | |
1c63f6df | 134 | if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & |
32bbc3d4 | 135 | LPTX_IN_PROGRESS), 20)) |
b5280cd0 | 136 | drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); |
32bbc3d4 MC |
137 | } |
138 | } | |
139 | ||
207ea507 JN |
140 | static int dsi_send_pkt_payld(struct intel_dsi_host *host, |
141 | const struct mipi_dsi_packet *packet) | |
c5f9c934 MC |
142 | { |
143 | struct intel_dsi *intel_dsi = host->intel_dsi; | |
207ea507 | 144 | struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); |
c5f9c934 | 145 | enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); |
207ea507 JN |
146 | const u8 *data = packet->payload; |
147 | u32 len = packet->payload_length; | |
c5f9c934 MC |
148 | int i, j; |
149 | ||
207ea507 JN |
150 | /* payload queue can accept *256 bytes*, check limit */ |
151 | if (len > MAX_PLOAD_CREDIT * 4) { | |
152 | drm_err(&i915->drm, "payload size exceeds max queue limit\n"); | |
153 | return -EINVAL; | |
154 | } | |
155 | ||
c5f9c934 MC |
156 | for (i = 0; i < len; i += 4) { |
157 | u32 tmp = 0; | |
158 | ||
207ea507 JN |
159 | if (!wait_for_payload_credits(i915, dsi_trans, 1)) |
160 | return -EBUSY; | |
c5f9c934 MC |
161 | |
162 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
163 | tmp |= *data++ << 8 * j; | |
164 | ||
207ea507 | 165 | intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp); |
c5f9c934 MC |
166 | } |
167 | ||
207ea507 | 168 | return 0; |
c5f9c934 MC |
169 | } |
170 | ||
171 | static int dsi_send_pkt_hdr(struct intel_dsi_host *host, | |
3e2947cd JN |
172 | const struct mipi_dsi_packet *packet, |
173 | bool enable_lpdt) | |
c5f9c934 MC |
174 | { |
175 | struct intel_dsi *intel_dsi = host->intel_dsi; | |
176 | struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); | |
177 | enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); | |
178 | u32 tmp; | |
c5f9c934 | 179 | |
43315f86 | 180 | if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) |
b90acd09 | 181 | return -EBUSY; |
c5f9c934 | 182 | |
1c63f6df | 183 | tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); |
c5f9c934 | 184 | |
3e2947cd | 185 | if (packet->payload) |
c5f9c934 MC |
186 | tmp |= PAYLOAD_PRESENT; |
187 | else | |
188 | tmp &= ~PAYLOAD_PRESENT; | |
189 | ||
190 | tmp &= ~VBLANK_FENCE; | |
191 | ||
192 | if (enable_lpdt) | |
193 | tmp |= LP_DATA_TRANSFER; | |
38a1b50c WT |
194 | else |
195 | tmp &= ~LP_DATA_TRANSFER; | |
c5f9c934 MC |
196 | |
197 | tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); | |
3e2947cd JN |
198 | tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); |
199 | tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); | |
200 | tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); | |
201 | tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); | |
1c63f6df | 202 | intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); |
c5f9c934 MC |
203 | |
204 | return 0; | |
205 | } | |
206 | ||
26fb0d55 VK |
207 | void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) |
208 | { | |
209 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
210 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1a45d681 | 211 | u32 mode_flags; |
26fb0d55 VK |
212 | enum port port; |
213 | ||
214 | mode_flags = crtc_state->mode_flags; | |
215 | ||
216 | /* | |
217 | * case 1 also covers dual link | |
218 | * In case of dual link, frame update should be set on | |
219 | * DSI_0 | |
220 | */ | |
221 | if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) | |
222 | port = PORT_A; | |
223 | else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) | |
224 | port = PORT_B; | |
225 | else | |
226 | return; | |
227 | ||
1a45d681 | 228 | intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST); |
26fb0d55 VK |
229 | } |
230 | ||
3f4b9d9d MC |
231 | static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) |
232 | { | |
233 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 234 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
dc867bc7 | 235 | enum phy phy; |
1a45d681 | 236 | u32 tmp, mask, val; |
3f4b9d9d MC |
237 | int lane; |
238 | ||
dc867bc7 | 239 | for_each_dsi_phy(phy, intel_dsi->phys) { |
3f4b9d9d MC |
240 | /* |
241 | * Program voltage swing and pre-emphasis level values as per | |
242 | * table in BSPEC under DDI buffer programing | |
243 | */ | |
1a45d681 AH |
244 | mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; |
245 | val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | | |
246 | RTERM_SELECT(0x6); | |
e6908588 | 247 | tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); |
1a45d681 AH |
248 | tmp &= ~mask; |
249 | tmp |= val; | |
1c63f6df | 250 | intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); |
1a45d681 | 251 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val); |
3f4b9d9d | 252 | |
1a45d681 AH |
253 | mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | |
254 | RCOMP_SCALAR_MASK; | |
255 | val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | | |
256 | RCOMP_SCALAR(0x98); | |
e6908588 | 257 | tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); |
1a45d681 AH |
258 | tmp &= ~mask; |
259 | tmp |= val; | |
1c63f6df | 260 | intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); |
1a45d681 AH |
261 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val); |
262 | ||
263 | mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | | |
264 | CURSOR_COEFF_MASK; | |
265 | val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | | |
266 | CURSOR_COEFF(0x3f); | |
267 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val); | |
268 | ||
269 | /* Bspec: must not use GRP register for write */ | |
270 | for (lane = 0; lane <= 3; lane++) | |
271 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), | |
272 | mask, val); | |
3f4b9d9d MC |
273 | } |
274 | } | |
275 | ||
5a8507b5 MC |
276 | static void configure_dual_link_mode(struct intel_encoder *encoder, |
277 | const struct intel_crtc_state *pipe_config) | |
278 | { | |
279 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 280 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
1a62dd98 | 281 | i915_reg_t dss_ctl1_reg, dss_ctl2_reg; |
5a8507b5 MC |
282 | u32 dss_ctl1; |
283 | ||
1a62dd98 JN |
284 | /* FIXME: Move all DSS handling to intel_vdsc.c */ |
285 | if (DISPLAY_VER(dev_priv) >= 12) { | |
286 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); | |
287 | ||
288 | dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); | |
289 | dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); | |
290 | } else { | |
291 | dss_ctl1_reg = DSS_CTL1; | |
292 | dss_ctl2_reg = DSS_CTL2; | |
293 | } | |
294 | ||
295 | dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); | |
5a8507b5 MC |
296 | dss_ctl1 |= SPLITTER_ENABLE; |
297 | dss_ctl1 &= ~OVERLAP_PIXELS_MASK; | |
298 | dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); | |
299 | ||
300 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
301 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 302 | &pipe_config->hw.adjusted_mode; |
5a8507b5 MC |
303 | u16 hactive = adjusted_mode->crtc_hdisplay; |
304 | u16 dl_buffer_depth; | |
305 | ||
306 | dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; | |
307 | dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; | |
308 | ||
309 | if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) | |
b5280cd0 WK |
310 | drm_err(&dev_priv->drm, |
311 | "DL buffer depth exceed max value\n"); | |
5a8507b5 MC |
312 | |
313 | dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; | |
314 | dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); | |
1a62dd98 | 315 | intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, |
1a45d681 | 316 | RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); |
5a8507b5 MC |
317 | } else { |
318 | /* Interleave */ | |
319 | dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; | |
320 | } | |
321 | ||
1a62dd98 | 322 | intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); |
5a8507b5 MC |
323 | } |
324 | ||
54ed6902 | 325 | /* aka DSI 8X clock */ |
04865139 JN |
326 | static int afe_clk(struct intel_encoder *encoder, |
327 | const struct intel_crtc_state *crtc_state) | |
54ed6902 | 328 | { |
b7d02c3a | 329 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
54ed6902 JN |
330 | int bpp; |
331 | ||
04865139 | 332 | if (crtc_state->dsc.compression_enable) |
59a266f0 | 333 | bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); |
04865139 JN |
334 | else |
335 | bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); | |
54ed6902 JN |
336 | |
337 | return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); | |
338 | } | |
339 | ||
04865139 JN |
340 | static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, |
341 | const struct intel_crtc_state *crtc_state) | |
fcfe0bdc MC |
342 | { |
343 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 344 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
fcfe0bdc | 345 | enum port port; |
54ed6902 | 346 | int afe_clk_khz; |
510b2814 MK |
347 | int theo_word_clk, act_word_clk; |
348 | u32 esc_clk_div_m, esc_clk_div_m_phy; | |
fcfe0bdc | 349 | |
04865139 | 350 | afe_clk_khz = afe_clk(encoder, crtc_state); |
510b2814 MK |
351 | |
352 | if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { | |
353 | theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); | |
354 | act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); | |
355 | esc_clk_div_m = act_word_clk * 8; | |
356 | esc_clk_div_m_phy = (act_word_clk - 1) / 2; | |
357 | } else { | |
358 | esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); | |
359 | } | |
fcfe0bdc MC |
360 | |
361 | for_each_dsi_port(port, intel_dsi->ports) { | |
1c63f6df JN |
362 | intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), |
363 | esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); | |
364 | intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); | |
fcfe0bdc MC |
365 | } |
366 | ||
367 | for_each_dsi_port(port, intel_dsi->ports) { | |
1c63f6df JN |
368 | intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), |
369 | esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); | |
370 | intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); | |
fcfe0bdc | 371 | } |
510b2814 MK |
372 | |
373 | if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { | |
374 | for_each_dsi_port(port, intel_dsi->ports) { | |
375 | intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8), | |
376 | esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); | |
377 | intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); | |
378 | } | |
379 | } | |
fcfe0bdc MC |
380 | } |
381 | ||
3a52fb7e ID |
382 | static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, |
383 | struct intel_dsi *intel_dsi) | |
384 | { | |
385 | enum port port; | |
386 | ||
387 | for_each_dsi_port(port, intel_dsi->ports) { | |
3dbe5e11 | 388 | drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); |
3a52fb7e ID |
389 | intel_dsi->io_wakeref[port] = |
390 | intel_display_power_get(dev_priv, | |
391 | port == PORT_A ? | |
0ba2661d ID |
392 | POWER_DOMAIN_PORT_DDI_IO_A : |
393 | POWER_DOMAIN_PORT_DDI_IO_B); | |
3a52fb7e ID |
394 | } |
395 | } | |
396 | ||
b1cb21a5 MC |
397 | static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) |
398 | { | |
399 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 400 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
b1cb21a5 | 401 | enum port port; |
b1cb21a5 | 402 | |
1a45d681 AH |
403 | for_each_dsi_port(port, intel_dsi->ports) |
404 | intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), | |
405 | 0, COMBO_PHY_MODE_DSI); | |
b1cb21a5 | 406 | |
3a52fb7e | 407 | get_dsi_io_power_domains(dev_priv, intel_dsi); |
b1cb21a5 MC |
408 | } |
409 | ||
45f09f7a MC |
410 | static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) |
411 | { | |
412 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 413 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
dc867bc7 | 414 | enum phy phy; |
45f09f7a | 415 | |
dc867bc7 MR |
416 | for_each_dsi_phy(phy, intel_dsi->phys) |
417 | intel_combo_phy_power_up_lanes(dev_priv, phy, true, | |
bd60a562 | 418 | intel_dsi->lane_count, false); |
45f09f7a MC |
419 | } |
420 | ||
fc41001d MC |
421 | static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) |
422 | { | |
423 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 424 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
dc867bc7 | 425 | enum phy phy; |
fc41001d MC |
426 | u32 tmp; |
427 | int lane; | |
428 | ||
429 | /* Step 4b(i) set loadgen select for transmit and aux lanes */ | |
dc867bc7 | 430 | for_each_dsi_phy(phy, intel_dsi->phys) { |
1a45d681 AH |
431 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0); |
432 | for (lane = 0; lane <= 3; lane++) | |
433 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), | |
434 | LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); | |
fc41001d MC |
435 | } |
436 | ||
437 | /* Step 4b(ii) set latency optimization for transmit and aux lanes */ | |
dc867bc7 | 438 | for_each_dsi_phy(phy, intel_dsi->phys) { |
1a45d681 AH |
439 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), |
440 | FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); | |
e6908588 | 441 | tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); |
fc41001d MC |
442 | tmp &= ~FRC_LATENCY_OPTIM_MASK; |
443 | tmp |= FRC_LATENCY_OPTIM_VAL(0x5); | |
1c63f6df | 444 | intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); |
6a7bafe8 | 445 | |
960e9836 | 446 | /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ |
0c65dc06 DB |
447 | if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) || |
448 | (DISPLAY_VER(dev_priv) >= 12)) { | |
1a45d681 AH |
449 | intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), |
450 | LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); | |
6a7bafe8 | 451 | |
1c63f6df | 452 | tmp = intel_de_read(dev_priv, |
e6908588 | 453 | ICL_PORT_PCS_DW1_LN(0, phy)); |
6a7bafe8 VK |
454 | tmp &= ~LATENCY_OPTIM_MASK; |
455 | tmp |= LATENCY_OPTIM_VAL(0x1); | |
1c63f6df JN |
456 | intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), |
457 | tmp); | |
6a7bafe8 | 458 | } |
fc41001d MC |
459 | } |
460 | ||
461 | } | |
462 | ||
3f4b9d9d MC |
463 | static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) |
464 | { | |
465 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 466 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
3f4b9d9d | 467 | u32 tmp; |
dc867bc7 | 468 | enum phy phy; |
3f4b9d9d MC |
469 | |
470 | /* clear common keeper enable bit */ | |
dc867bc7 | 471 | for_each_dsi_phy(phy, intel_dsi->phys) { |
e6908588 | 472 | tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); |
3f4b9d9d | 473 | tmp &= ~COMMON_KEEPER_EN; |
1c63f6df | 474 | intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); |
1a45d681 | 475 | intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); |
3f4b9d9d MC |
476 | } |
477 | ||
478 | /* | |
479 | * Set SUS Clock Config bitfield to 11b | |
480 | * Note: loadgen select program is done | |
481 | * as part of lane phy sequence configuration | |
482 | */ | |
1a45d681 AH |
483 | for_each_dsi_phy(phy, intel_dsi->phys) |
484 | intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG); | |
3f4b9d9d MC |
485 | |
486 | /* Clear training enable to change swing values */ | |
dc867bc7 | 487 | for_each_dsi_phy(phy, intel_dsi->phys) { |
e6908588 | 488 | tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); |
3f4b9d9d | 489 | tmp &= ~TX_TRAINING_EN; |
1c63f6df | 490 | intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); |
1a45d681 | 491 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); |
3f4b9d9d MC |
492 | } |
493 | ||
494 | /* Program swing and de-emphasis */ | |
495 | dsi_program_swing_and_deemphasis(encoder); | |
496 | ||
497 | /* Set training enable to trigger update */ | |
dc867bc7 | 498 | for_each_dsi_phy(phy, intel_dsi->phys) { |
e6908588 | 499 | tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); |
3f4b9d9d | 500 | tmp |= TX_TRAINING_EN; |
1c63f6df | 501 | intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); |
1a45d681 | 502 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); |
3f4b9d9d MC |
503 | } |
504 | } | |
505 | ||
ba3df888 MC |
506 | static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) |
507 | { | |
508 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 509 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
ba3df888 MC |
510 | enum port port; |
511 | ||
512 | for_each_dsi_port(port, intel_dsi->ports) { | |
1a45d681 | 513 | intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); |
ba3df888 | 514 | |
1c63f6df | 515 | if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & |
ba3df888 MC |
516 | DDI_BUF_IS_IDLE), |
517 | 500)) | |
b5280cd0 WK |
518 | drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", |
519 | port_name(port)); | |
ba3df888 MC |
520 | } |
521 | } | |
522 | ||
04865139 JN |
523 | static void |
524 | gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, | |
525 | const struct intel_crtc_state *crtc_state) | |
70a7b836 MC |
526 | { |
527 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 528 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
70a7b836 | 529 | enum port port; |
dc867bc7 | 530 | enum phy phy; |
70a7b836 | 531 | |
e72cce53 | 532 | /* Program DPHY clock lanes timings */ |
d4121327 | 533 | for_each_dsi_port(port, intel_dsi->ports) |
1c63f6df JN |
534 | intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), |
535 | intel_dsi->dphy_reg); | |
e72cce53 | 536 | |
e72cce53 | 537 | /* Program DPHY data lanes timings */ |
d4121327 | 538 | for_each_dsi_port(port, intel_dsi->ports) |
1c63f6df JN |
539 | intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), |
540 | intel_dsi->dphy_data_lane_reg); | |
e72cce53 | 541 | |
5fea8645 MC |
542 | /* |
543 | * If DSI link operating at or below an 800 MHz, | |
544 | * TA_SURE should be override and programmed to | |
545 | * a value '0' inside TA_PARAM_REGISTERS otherwise | |
546 | * leave all fields at HW default values. | |
547 | */ | |
93e7e61e | 548 | if (DISPLAY_VER(dev_priv) == 11) { |
04865139 | 549 | if (afe_clk(encoder, crtc_state) <= 800000) { |
d4121327 | 550 | for_each_dsi_port(port, intel_dsi->ports) |
1a45d681 AH |
551 | intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port), |
552 | TA_SURE_MASK, | |
553 | TA_SURE_OVERRIDE | TA_SURE(0)); | |
5fea8645 MC |
554 | } |
555 | } | |
683d672c | 556 | |
0c65dc06 | 557 | if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { |
1a45d681 AH |
558 | for_each_dsi_phy(phy, intel_dsi->phys) |
559 | intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy), | |
560 | 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); | |
683d672c | 561 | } |
70a7b836 MC |
562 | } |
563 | ||
d4121327 VS |
564 | static void |
565 | gen11_dsi_setup_timings(struct intel_encoder *encoder, | |
566 | const struct intel_crtc_state *crtc_state) | |
567 | { | |
568 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
569 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
570 | enum port port; | |
571 | ||
572 | /* Program T-INIT master registers */ | |
573 | for_each_dsi_port(port, intel_dsi->ports) | |
574 | intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port), | |
575 | DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); | |
576 | ||
577 | /* shadow register inside display core */ | |
578 | for_each_dsi_port(port, intel_dsi->ports) | |
579 | intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), | |
580 | intel_dsi->dphy_reg); | |
581 | ||
582 | /* shadow register inside display core */ | |
583 | for_each_dsi_port(port, intel_dsi->ports) | |
584 | intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), | |
585 | intel_dsi->dphy_data_lane_reg); | |
586 | ||
587 | /* shadow register inside display core */ | |
588 | if (DISPLAY_VER(dev_priv) == 11) { | |
589 | if (afe_clk(encoder, crtc_state) <= 800000) { | |
590 | for_each_dsi_port(port, intel_dsi->ports) { | |
591 | intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port), | |
592 | TA_SURE_MASK, | |
593 | TA_SURE_OVERRIDE | TA_SURE(0)); | |
594 | } | |
595 | } | |
596 | } | |
597 | } | |
598 | ||
32250c8e MC |
599 | static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) |
600 | { | |
601 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 602 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
32250c8e | 603 | u32 tmp; |
befa372b | 604 | enum phy phy; |
32250c8e | 605 | |
36d225f3 | 606 | mutex_lock(&dev_priv->display.dpll.lock); |
1c63f6df | 607 | tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); |
dc867bc7 | 608 | for_each_dsi_phy(phy, intel_dsi->phys) |
befa372b | 609 | tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); |
32250c8e | 610 | |
1c63f6df | 611 | intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); |
36d225f3 | 612 | mutex_unlock(&dev_priv->display.dpll.lock); |
32250c8e MC |
613 | } |
614 | ||
1026bea0 MC |
615 | static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) |
616 | { | |
617 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 618 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
1026bea0 | 619 | u32 tmp; |
befa372b | 620 | enum phy phy; |
1026bea0 | 621 | |
36d225f3 | 622 | mutex_lock(&dev_priv->display.dpll.lock); |
1c63f6df | 623 | tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); |
dc867bc7 | 624 | for_each_dsi_phy(phy, intel_dsi->phys) |
befa372b | 625 | tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); |
1026bea0 | 626 | |
1c63f6df | 627 | intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); |
36d225f3 | 628 | mutex_unlock(&dev_priv->display.dpll.lock); |
1026bea0 MC |
629 | } |
630 | ||
0fbd8694 VS |
631 | static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) |
632 | { | |
633 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
634 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
635 | bool clock_enabled = false; | |
636 | enum phy phy; | |
637 | u32 tmp; | |
638 | ||
639 | tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); | |
640 | ||
641 | for_each_dsi_phy(phy, intel_dsi->phys) { | |
642 | if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) | |
643 | clock_enabled = true; | |
644 | } | |
645 | ||
646 | return clock_enabled; | |
647 | } | |
648 | ||
949fc52a JN |
649 | static void gen11_dsi_map_pll(struct intel_encoder *encoder, |
650 | const struct intel_crtc_state *crtc_state) | |
651 | { | |
652 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 653 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
949fc52a | 654 | struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
befa372b | 655 | enum phy phy; |
949fc52a JN |
656 | u32 val; |
657 | ||
36d225f3 | 658 | mutex_lock(&dev_priv->display.dpll.lock); |
949fc52a | 659 | |
1c63f6df | 660 | val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); |
dc867bc7 | 661 | for_each_dsi_phy(phy, intel_dsi->phys) { |
befa372b MR |
662 | val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); |
663 | val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); | |
949fc52a | 664 | } |
1c63f6df | 665 | intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); |
c5b81a32 | 666 | |
dc867bc7 | 667 | for_each_dsi_phy(phy, intel_dsi->phys) { |
4579509e | 668 | val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); |
c5b81a32 | 669 | } |
1c63f6df | 670 | intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); |
c5b81a32 | 671 | |
1c63f6df | 672 | intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); |
949fc52a | 673 | |
36d225f3 | 674 | mutex_unlock(&dev_priv->display.dpll.lock); |
949fc52a JN |
675 | } |
676 | ||
70f4f502 MC |
677 | static void |
678 | gen11_dsi_configure_transcoder(struct intel_encoder *encoder, | |
679 | const struct intel_crtc_state *pipe_config) | |
d364dc66 MC |
680 | { |
681 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 682 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
f15f01a7 VS |
683 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
684 | enum pipe pipe = crtc->pipe; | |
d364dc66 MC |
685 | u32 tmp; |
686 | enum port port; | |
687 | enum transcoder dsi_trans; | |
688 | ||
689 | for_each_dsi_port(port, intel_dsi->ports) { | |
690 | dsi_trans = dsi_port_to_transcoder(port); | |
1c63f6df | 691 | tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); |
d364dc66 MC |
692 | |
693 | if (intel_dsi->eotp_pkt) | |
694 | tmp &= ~EOTP_DISABLED; | |
695 | else | |
696 | tmp |= EOTP_DISABLED; | |
697 | ||
698 | /* enable link calibration if freq > 1.5Gbps */ | |
04865139 | 699 | if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { |
d364dc66 MC |
700 | tmp &= ~LINK_CALIBRATION_MASK; |
701 | tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; | |
702 | } | |
703 | ||
704 | /* configure continuous clock */ | |
705 | tmp &= ~CONTINUOUS_CLK_MASK; | |
706 | if (intel_dsi->clock_stop) | |
707 | tmp |= CLK_ENTER_LP_AFTER_DATA; | |
708 | else | |
709 | tmp |= CLK_HS_CONTINUOUS; | |
710 | ||
711 | /* configure buffer threshold limit to minimum */ | |
712 | tmp &= ~PIX_BUF_THRESHOLD_MASK; | |
713 | tmp |= PIX_BUF_THRESHOLD_1_4; | |
714 | ||
715 | /* set virtual channel to '0' */ | |
716 | tmp &= ~PIX_VIRT_CHAN_MASK; | |
717 | tmp |= PIX_VIRT_CHAN(0); | |
718 | ||
719 | /* program BGR transmission */ | |
720 | if (intel_dsi->bgr_enabled) | |
721 | tmp |= BGR_TRANSMISSION; | |
722 | ||
723 | /* select pixel format */ | |
724 | tmp &= ~PIX_FMT_MASK; | |
38b89881 JN |
725 | if (pipe_config->dsc.compression_enable) { |
726 | tmp |= PIX_FMT_COMPRESSED; | |
727 | } else { | |
728 | switch (intel_dsi->pixel_format) { | |
729 | default: | |
730 | MISSING_CASE(intel_dsi->pixel_format); | |
df561f66 | 731 | fallthrough; |
38b89881 JN |
732 | case MIPI_DSI_FMT_RGB565: |
733 | tmp |= PIX_FMT_RGB565; | |
734 | break; | |
735 | case MIPI_DSI_FMT_RGB666_PACKED: | |
736 | tmp |= PIX_FMT_RGB666_PACKED; | |
737 | break; | |
738 | case MIPI_DSI_FMT_RGB666: | |
739 | tmp |= PIX_FMT_RGB666_LOOSE; | |
740 | break; | |
741 | case MIPI_DSI_FMT_RGB888: | |
742 | tmp |= PIX_FMT_RGB888; | |
743 | break; | |
744 | } | |
d364dc66 MC |
745 | } |
746 | ||
005e9537 | 747 | if (DISPLAY_VER(dev_priv) >= 12) { |
32d38e6c VK |
748 | if (is_vid_mode(intel_dsi)) |
749 | tmp |= BLANKING_PACKET_ENABLE; | |
750 | } | |
751 | ||
d364dc66 MC |
752 | /* program DSI operation mode */ |
753 | if (is_vid_mode(intel_dsi)) { | |
754 | tmp &= ~OP_MODE_MASK; | |
8f0991cc | 755 | switch (intel_dsi->video_mode) { |
d364dc66 | 756 | default: |
8f0991cc | 757 | MISSING_CASE(intel_dsi->video_mode); |
df561f66 | 758 | fallthrough; |
8f0991cc | 759 | case NON_BURST_SYNC_EVENTS: |
d364dc66 MC |
760 | tmp |= VIDEO_MODE_SYNC_EVENT; |
761 | break; | |
8f0991cc | 762 | case NON_BURST_SYNC_PULSE: |
d364dc66 MC |
763 | tmp |= VIDEO_MODE_SYNC_PULSE; |
764 | break; | |
765 | } | |
b4b95b05 VK |
766 | } else { |
767 | /* | |
768 | * FIXME: Retrieve this info from VBT. | |
769 | * As per the spec when dsi transcoder is operating | |
770 | * in TE GATE mode, TE comes from GPIO | |
771 | * which is UTIL PIN for DSI 0. | |
772 | * Also this GPIO would not be used for other | |
773 | * purposes is an assumption. | |
774 | */ | |
775 | tmp &= ~OP_MODE_MASK; | |
776 | tmp |= CMD_MODE_TE_GATE; | |
777 | tmp |= TE_SOURCE_GPIO; | |
d364dc66 MC |
778 | } |
779 | ||
1c63f6df | 780 | intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); |
d364dc66 | 781 | } |
70f4f502 MC |
782 | |
783 | /* enable port sync mode if dual link */ | |
784 | if (intel_dsi->dual_link) { | |
785 | for_each_dsi_port(port, intel_dsi->ports) { | |
786 | dsi_trans = dsi_port_to_transcoder(port); | |
1a45d681 AH |
787 | intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), |
788 | 0, PORT_SYNC_MODE_ENABLE); | |
70f4f502 MC |
789 | } |
790 | ||
5a8507b5 MC |
791 | /* configure stream splitting */ |
792 | configure_dual_link_mode(encoder, pipe_config); | |
70f4f502 MC |
793 | } |
794 | ||
795 | for_each_dsi_port(port, intel_dsi->ports) { | |
796 | dsi_trans = dsi_port_to_transcoder(port); | |
797 | ||
798 | /* select data lane width */ | |
1c63f6df | 799 | tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); |
70f4f502 MC |
800 | tmp &= ~DDI_PORT_WIDTH_MASK; |
801 | tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); | |
802 | ||
803 | /* select input pipe */ | |
804 | tmp &= ~TRANS_DDI_EDP_INPUT_MASK; | |
805 | switch (pipe) { | |
806 | default: | |
807 | MISSING_CASE(pipe); | |
df561f66 | 808 | fallthrough; |
70f4f502 MC |
809 | case PIPE_A: |
810 | tmp |= TRANS_DDI_EDP_INPUT_A_ON; | |
811 | break; | |
812 | case PIPE_B: | |
813 | tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
814 | break; | |
815 | case PIPE_C: | |
816 | tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
817 | break; | |
4d89adc7 JRS |
818 | case PIPE_D: |
819 | tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; | |
820 | break; | |
70f4f502 MC |
821 | } |
822 | ||
823 | /* enable DDI buffer */ | |
824 | tmp |= TRANS_DDI_FUNC_ENABLE; | |
1c63f6df | 825 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); |
70f4f502 MC |
826 | } |
827 | ||
828 | /* wait for link ready */ | |
829 | for_each_dsi_port(port, intel_dsi->ports) { | |
830 | dsi_trans = dsi_port_to_transcoder(port); | |
1c63f6df JN |
831 | if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & |
832 | LINK_READY), 2500)) | |
b5280cd0 | 833 | drm_err(&dev_priv->drm, "DSI link not ready\n"); |
70f4f502 | 834 | } |
d364dc66 MC |
835 | } |
836 | ||
d1aeb5f3 MC |
837 | static void |
838 | gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, | |
53693f02 | 839 | const struct intel_crtc_state *crtc_state) |
d1aeb5f3 MC |
840 | { |
841 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 842 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
d1aeb5f3 | 843 | const struct drm_display_mode *adjusted_mode = |
53693f02 | 844 | &crtc_state->hw.adjusted_mode; |
d1aeb5f3 MC |
845 | enum port port; |
846 | enum transcoder dsi_trans; | |
847 | /* horizontal timings */ | |
848 | u16 htotal, hactive, hsync_start, hsync_end, hsync_size; | |
0cc35a9c | 849 | u16 hback_porch; |
d1aeb5f3 MC |
850 | /* vertical timings */ |
851 | u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; | |
53693f02 JN |
852 | int mul = 1, div = 1; |
853 | ||
854 | /* | |
855 | * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account | |
856 | * for slower link speed if DSC is enabled. | |
857 | * | |
858 | * The compression frequency ratio is the ratio between compressed and | |
859 | * non-compressed link speeds, and simplifies down to the ratio between | |
860 | * compressed and non-compressed bpp. | |
861 | */ | |
862 | if (crtc_state->dsc.compression_enable) { | |
59a266f0 | 863 | mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); |
53693f02 JN |
864 | div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
865 | } | |
d1aeb5f3 MC |
866 | |
867 | hactive = adjusted_mode->crtc_hdisplay; | |
b9277832 VK |
868 | |
869 | if (is_vid_mode(intel_dsi)) | |
870 | htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); | |
871 | else | |
872 | htotal = DIV_ROUND_UP((hactive + 160) * mul, div); | |
873 | ||
53693f02 JN |
874 | hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); |
875 | hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); | |
d1aeb5f3 | 876 | hsync_size = hsync_end - hsync_start; |
d1aeb5f3 MC |
877 | hback_porch = (adjusted_mode->crtc_htotal - |
878 | adjusted_mode->crtc_hsync_end); | |
879 | vactive = adjusted_mode->crtc_vdisplay; | |
b9277832 VK |
880 | |
881 | if (is_vid_mode(intel_dsi)) { | |
882 | vtotal = adjusted_mode->crtc_vtotal; | |
883 | } else { | |
884 | int bpp, line_time_us, byte_clk_period_ns; | |
885 | ||
886 | if (crtc_state->dsc.compression_enable) | |
59a266f0 | 887 | bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16); |
b9277832 VK |
888 | else |
889 | bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); | |
890 | ||
891 | byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); | |
892 | line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); | |
893 | vtotal = vactive + DIV_ROUND_UP(400, line_time_us); | |
894 | } | |
d1aeb5f3 MC |
895 | vsync_start = adjusted_mode->crtc_vsync_start; |
896 | vsync_end = adjusted_mode->crtc_vsync_end; | |
897 | vsync_shift = hsync_start - htotal / 2; | |
898 | ||
899 | if (intel_dsi->dual_link) { | |
900 | hactive /= 2; | |
901 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
902 | hactive += intel_dsi->pixel_overlap; | |
903 | htotal /= 2; | |
904 | } | |
905 | ||
906 | /* minimum hactive as per bspec: 256 pixels */ | |
907 | if (adjusted_mode->crtc_hdisplay < 256) | |
b5280cd0 | 908 | drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); |
d1aeb5f3 MC |
909 | |
910 | /* if RGB666 format, then hactive must be multiple of 4 pixels */ | |
911 | if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) | |
b5280cd0 WK |
912 | drm_err(&dev_priv->drm, |
913 | "hactive pixels are not multiple of 4\n"); | |
d1aeb5f3 MC |
914 | |
915 | /* program TRANS_HTOTAL register */ | |
916 | for_each_dsi_port(port, intel_dsi->ports) { | |
917 | dsi_trans = dsi_port_to_transcoder(port); | |
5ac421a9 | 918 | intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans), |
050db7d7 | 919 | HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); |
d1aeb5f3 MC |
920 | } |
921 | ||
922 | /* TRANS_HSYNC register to be programmed only for video mode */ | |
b9277832 | 923 | if (is_vid_mode(intel_dsi)) { |
8f0991cc | 924 | if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { |
d1aeb5f3 MC |
925 | /* BSPEC: hsync size should be atleast 16 pixels */ |
926 | if (hsync_size < 16) | |
b5280cd0 WK |
927 | drm_err(&dev_priv->drm, |
928 | "hsync size < 16 pixels\n"); | |
d1aeb5f3 MC |
929 | } |
930 | ||
931 | if (hback_porch < 16) | |
b5280cd0 | 932 | drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); |
d1aeb5f3 MC |
933 | |
934 | if (intel_dsi->dual_link) { | |
935 | hsync_start /= 2; | |
936 | hsync_end /= 2; | |
937 | } | |
938 | ||
939 | for_each_dsi_port(port, intel_dsi->ports) { | |
940 | dsi_trans = dsi_port_to_transcoder(port); | |
5ac421a9 | 941 | intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans), |
050db7d7 | 942 | HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); |
d1aeb5f3 MC |
943 | } |
944 | } | |
945 | ||
946 | /* program TRANS_VTOTAL register */ | |
947 | for_each_dsi_port(port, intel_dsi->ports) { | |
948 | dsi_trans = dsi_port_to_transcoder(port); | |
949 | /* | |
950 | * FIXME: Programing this by assuming progressive mode, since | |
951 | * non-interlaced info from VBT is not saved inside | |
952 | * struct drm_display_mode. | |
953 | * For interlace mode: program required pixel minus 2 | |
954 | */ | |
5ac421a9 | 955 | intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans), |
050db7d7 | 956 | VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); |
d1aeb5f3 MC |
957 | } |
958 | ||
959 | if (vsync_end < vsync_start || vsync_end > vtotal) | |
b5280cd0 | 960 | drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); |
d1aeb5f3 MC |
961 | |
962 | if (vsync_start < vactive) | |
b5280cd0 | 963 | drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); |
d1aeb5f3 | 964 | |
b9277832 VK |
965 | /* program TRANS_VSYNC register for video mode only */ |
966 | if (is_vid_mode(intel_dsi)) { | |
967 | for_each_dsi_port(port, intel_dsi->ports) { | |
968 | dsi_trans = dsi_port_to_transcoder(port); | |
5ac421a9 | 969 | intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans), |
050db7d7 | 970 | VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); |
b9277832 | 971 | } |
d1aeb5f3 MC |
972 | } |
973 | ||
974 | /* | |
b9277832 | 975 | * FIXME: It has to be programmed only for video modes and interlaced |
d1aeb5f3 MC |
976 | * modes. Put the check condition here once interlaced |
977 | * info available as described above. | |
978 | * program TRANS_VSYNCSHIFT register | |
979 | */ | |
b9277832 VK |
980 | if (is_vid_mode(intel_dsi)) { |
981 | for_each_dsi_port(port, intel_dsi->ports) { | |
982 | dsi_trans = dsi_port_to_transcoder(port); | |
5ac421a9 | 983 | intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans), |
b9277832 VK |
984 | vsync_shift); |
985 | } | |
d1aeb5f3 | 986 | } |
3522a33a | 987 | |
1552dd6e VS |
988 | /* |
989 | * program TRANS_VBLANK register, should be same as vtotal programmed | |
990 | * | |
991 | * FIXME get rid of these local hacks and do it right, | |
992 | * this will not handle eg. delayed vblank correctly. | |
993 | */ | |
005e9537 | 994 | if (DISPLAY_VER(dev_priv) >= 12) { |
3522a33a VK |
995 | for_each_dsi_port(port, intel_dsi->ports) { |
996 | dsi_trans = dsi_port_to_transcoder(port); | |
5ac421a9 | 997 | intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans), |
050db7d7 | 998 | VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); |
3522a33a VK |
999 | } |
1000 | } | |
d1aeb5f3 MC |
1001 | } |
1002 | ||
303e347c MC |
1003 | static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) |
1004 | { | |
1005 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1006 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
303e347c MC |
1007 | enum port port; |
1008 | enum transcoder dsi_trans; | |
303e347c MC |
1009 | |
1010 | for_each_dsi_port(port, intel_dsi->ports) { | |
1011 | dsi_trans = dsi_port_to_transcoder(port); | |
3eb08ea5 | 1012 | intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE); |
303e347c MC |
1013 | |
1014 | /* wait for transcoder to be enabled */ | |
3eb08ea5 VS |
1015 | if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans), |
1016 | TRANSCONF_STATE_ENABLE, 10)) | |
b5280cd0 WK |
1017 | drm_err(&dev_priv->drm, |
1018 | "DSI transcoder not enabled\n"); | |
303e347c MC |
1019 | } |
1020 | } | |
1021 | ||
04865139 JN |
1022 | static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, |
1023 | const struct intel_crtc_state *crtc_state) | |
5a4712f4 MC |
1024 | { |
1025 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1026 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
5a4712f4 MC |
1027 | enum port port; |
1028 | enum transcoder dsi_trans; | |
1a45d681 | 1029 | u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; |
5a4712f4 MC |
1030 | |
1031 | /* | |
1032 | * escape clock count calculation: | |
1033 | * BYTE_CLK_COUNT = TIME_NS/(8 * UI) | |
1034 | * UI (nsec) = (10^6)/Bitrate | |
1035 | * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate | |
1036 | * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS | |
1037 | */ | |
04865139 | 1038 | divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; |
5a4712f4 MC |
1039 | mul = 8 * 1000000; |
1040 | hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, | |
1041 | divisor); | |
1042 | lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); | |
1043 | ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); | |
1044 | ||
1045 | for_each_dsi_port(port, intel_dsi->ports) { | |
1046 | dsi_trans = dsi_port_to_transcoder(port); | |
1047 | ||
1048 | /* program hst_tx_timeout */ | |
1a45d681 AH |
1049 | intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans), |
1050 | HSTX_TIMEOUT_VALUE_MASK, | |
1051 | HSTX_TIMEOUT_VALUE(hs_tx_timeout)); | |
5a4712f4 MC |
1052 | |
1053 | /* FIXME: DSI_CALIB_TO */ | |
1054 | ||
1055 | /* program lp_rx_host timeout */ | |
1a45d681 AH |
1056 | intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), |
1057 | LPRX_TIMEOUT_VALUE_MASK, | |
1058 | LPRX_TIMEOUT_VALUE(lp_rx_timeout)); | |
5a4712f4 MC |
1059 | |
1060 | /* FIXME: DSI_PWAIT_TO */ | |
1061 | ||
1062 | /* program turn around timeout */ | |
1a45d681 AH |
1063 | intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans), |
1064 | TA_TIMEOUT_VALUE_MASK, | |
1065 | TA_TIMEOUT_VALUE(ta_timeout)); | |
5a4712f4 MC |
1066 | } |
1067 | } | |
1068 | ||
b4b95b05 VK |
1069 | static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, |
1070 | bool enable) | |
1071 | { | |
1072 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1073 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1074 | u32 tmp; | |
1075 | ||
1076 | /* | |
1077 | * used as TE i/p for DSI0, | |
1078 | * for dual link/DSI1 TE is from slave DSI1 | |
1079 | * through GPIO. | |
1080 | */ | |
1081 | if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) | |
1082 | return; | |
1083 | ||
1084 | tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); | |
1085 | ||
1086 | if (enable) { | |
1087 | tmp |= UTIL_PIN_DIRECTION_INPUT; | |
1088 | tmp |= UTIL_PIN_ENABLE; | |
1089 | } else { | |
1090 | tmp &= ~UTIL_PIN_ENABLE; | |
1091 | } | |
1092 | intel_de_write(dev_priv, UTIL_PIN_CTL, tmp); | |
1093 | } | |
1094 | ||
70f4f502 MC |
1095 | static void |
1096 | gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, | |
04865139 | 1097 | const struct intel_crtc_state *crtc_state) |
45f09f7a MC |
1098 | { |
1099 | /* step 4a: power up all lanes of the DDI used by DSI */ | |
1100 | gen11_dsi_power_up_lanes(encoder); | |
fc41001d MC |
1101 | |
1102 | /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ | |
1103 | gen11_dsi_config_phy_lanes_sequence(encoder); | |
3f4b9d9d MC |
1104 | |
1105 | /* step 4c: configure voltage swing and skew */ | |
1106 | gen11_dsi_voltage_swing_program_seq(encoder); | |
ba3df888 | 1107 | |
d4121327 VS |
1108 | /* setup D-PHY timings */ |
1109 | gen11_dsi_setup_dphy_timings(encoder, crtc_state); | |
1110 | ||
ba3df888 MC |
1111 | /* enable DDI buffer */ |
1112 | gen11_dsi_enable_ddi_buffer(encoder); | |
70a7b836 | 1113 | |
a43d9281 VS |
1114 | gen11_dsi_gate_clocks(encoder); |
1115 | ||
d4121327 | 1116 | gen11_dsi_setup_timings(encoder, crtc_state); |
d364dc66 | 1117 | |
b4b95b05 VK |
1118 | /* Since transcoder is configured to take events from GPIO */ |
1119 | gen11_dsi_config_util_pin(encoder, true); | |
1120 | ||
5a4712f4 | 1121 | /* step 4h: setup DSI protocol timeouts */ |
04865139 | 1122 | gen11_dsi_setup_timeouts(encoder, crtc_state); |
5a4712f4 | 1123 | |
d364dc66 | 1124 | /* Step (4h, 4i, 4j, 4k): Configure transcoder */ |
04865139 | 1125 | gen11_dsi_configure_transcoder(encoder, crtc_state); |
45f09f7a MC |
1126 | } |
1127 | ||
bfee32bf MC |
1128 | static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) |
1129 | { | |
1130 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1131 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
bfee32bf MC |
1132 | struct mipi_dsi_device *dsi; |
1133 | enum port port; | |
1134 | enum transcoder dsi_trans; | |
1135 | u32 tmp; | |
1136 | int ret; | |
1137 | ||
1138 | /* set maximum return packet size */ | |
1139 | for_each_dsi_port(port, intel_dsi->ports) { | |
1140 | dsi_trans = dsi_port_to_transcoder(port); | |
1141 | ||
1142 | /* | |
1143 | * FIXME: This uses the number of DW's currently in the payload | |
1144 | * receive queue. This is probably not what we want here. | |
1145 | */ | |
1c63f6df | 1146 | tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); |
bfee32bf MC |
1147 | tmp &= NUMBER_RX_PLOAD_DW_MASK; |
1148 | /* multiply "Number Rx Payload DW" by 4 to get max value */ | |
1149 | tmp = tmp * 4; | |
1150 | dsi = intel_dsi->dsi_hosts[port]->device; | |
1151 | ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); | |
1152 | if (ret < 0) | |
b5280cd0 WK |
1153 | drm_err(&dev_priv->drm, |
1154 | "error setting max return pkt size%d\n", tmp); | |
bfee32bf | 1155 | } |
c2661638 | 1156 | |
c2661638 | 1157 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); |
6992eb81 | 1158 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); |
32bbc3d4 MC |
1159 | |
1160 | /* ensure all panel commands dispatched before enabling transcoder */ | |
1161 | wait_for_cmds_dispatched_to_panel(encoder); | |
bfee32bf MC |
1162 | } |
1163 | ||
ede9771d VS |
1164 | static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, |
1165 | struct intel_encoder *encoder, | |
04865139 | 1166 | const struct intel_crtc_state *crtc_state, |
95f2f4db | 1167 | const struct drm_connector_state *conn_state) |
fcfe0bdc | 1168 | { |
86ecd3b3 VS |
1169 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
1170 | ||
201963a8 VS |
1171 | intel_dsi_wait_panel_power_cycle(intel_dsi); |
1172 | ||
86ecd3b3 VS |
1173 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); |
1174 | msleep(intel_dsi->panel_on_delay); | |
1175 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); | |
1176 | ||
b1cb21a5 MC |
1177 | /* step2: enable IO power */ |
1178 | gen11_dsi_enable_io_power(encoder); | |
1179 | ||
fcfe0bdc | 1180 | /* step3: enable DSI PLL */ |
04865139 | 1181 | gen11_dsi_program_esc_clk_div(encoder, crtc_state); |
95f2f4db VK |
1182 | } |
1183 | ||
ede9771d VS |
1184 | static void gen11_dsi_pre_enable(struct intel_atomic_state *state, |
1185 | struct intel_encoder *encoder, | |
95f2f4db VK |
1186 | const struct intel_crtc_state *pipe_config, |
1187 | const struct drm_connector_state *conn_state) | |
1188 | { | |
949fc52a JN |
1189 | /* step3b */ |
1190 | gen11_dsi_map_pll(encoder, pipe_config); | |
1191 | ||
45f09f7a | 1192 | /* step4: enable DSI port and DPHY */ |
70f4f502 | 1193 | gen11_dsi_enable_port_and_phy(encoder, pipe_config); |
d1aeb5f3 | 1194 | |
bfee32bf MC |
1195 | /* step5: program and powerup panel */ |
1196 | gen11_dsi_powerup_panel(encoder); | |
1197 | ||
3126977d VS |
1198 | intel_dsc_dsi_pps_write(encoder, pipe_config); |
1199 | ||
d1aeb5f3 MC |
1200 | /* step6c: configure transcoder timings */ |
1201 | gen11_dsi_set_transcoder_timings(encoder, pipe_config); | |
fcfe0bdc | 1202 | } |
d9d996b6 | 1203 | |
544021e3 TU |
1204 | /* |
1205 | * Wa_1409054076:icl,jsl,ehl | |
1206 | * When pipe A is disabled and MIPI DSI is enabled on pipe B, | |
1207 | * the AMT KVMR feature will incorrectly see pipe A as enabled. | |
1208 | * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave | |
1209 | * it set while DSI is enabled on pipe B | |
1210 | */ | |
1211 | static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, | |
1212 | enum pipe pipe, bool enable) | |
1213 | { | |
1214 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1215 | ||
1216 | if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) | |
1217 | intel_de_rmw(dev_priv, CHICKEN_PAR1_1, | |
1218 | IGNORE_KVMR_PIPE_A, | |
1219 | enable ? IGNORE_KVMR_PIPE_A : 0); | |
1220 | } | |
f87c46c4 VK |
1221 | |
1222 | /* | |
1223 | * Wa_16012360555:adl-p | |
1224 | * SW will have to program the "LP to HS Wakeup Guardband" | |
1225 | * to account for the repeaters on the HS Request/Ready | |
1226 | * PPI signaling between the Display engine and the DPHY. | |
1227 | */ | |
1228 | static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) | |
1229 | { | |
1230 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
1231 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1232 | enum port port; | |
1233 | ||
1234 | if (DISPLAY_VER(i915) == 13) { | |
1235 | for_each_dsi_port(port, intel_dsi->ports) | |
1236 | intel_de_rmw(i915, TGL_DSI_CHKN_REG(port), | |
6f07707f VK |
1237 | TGL_DSI_CHKN_LSHS_GB_MASK, |
1238 | TGL_DSI_CHKN_LSHS_GB(4)); | |
f87c46c4 VK |
1239 | } |
1240 | } | |
1241 | ||
ede9771d VS |
1242 | static void gen11_dsi_enable(struct intel_atomic_state *state, |
1243 | struct intel_encoder *encoder, | |
21fd23ac JN |
1244 | const struct intel_crtc_state *crtc_state, |
1245 | const struct drm_connector_state *conn_state) | |
1246 | { | |
87e9bb49 | 1247 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
3d41ec41 | 1248 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
87e9bb49 | 1249 | |
544021e3 TU |
1250 | /* Wa_1409054076:icl,jsl,ehl */ |
1251 | icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); | |
1252 | ||
f87c46c4 VK |
1253 | /* Wa_16012360555:adl-p */ |
1254 | adlp_set_lp_hs_wakeup_gb(encoder); | |
1255 | ||
87e9bb49 VK |
1256 | /* step6d: enable dsi transcoder */ |
1257 | gen11_dsi_enable_transcoder(encoder); | |
1258 | ||
1259 | /* step7: enable backlight */ | |
c0a52f8b | 1260 | intel_backlight_enable(crtc_state, conn_state); |
87e9bb49 VK |
1261 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); |
1262 | ||
21fd23ac JN |
1263 | intel_crtc_vblank_on(crtc_state); |
1264 | } | |
1265 | ||
4e123bd3 MC |
1266 | static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) |
1267 | { | |
1268 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1269 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
4e123bd3 MC |
1270 | enum port port; |
1271 | enum transcoder dsi_trans; | |
4e123bd3 MC |
1272 | |
1273 | for_each_dsi_port(port, intel_dsi->ports) { | |
1274 | dsi_trans = dsi_port_to_transcoder(port); | |
1275 | ||
1276 | /* disable transcoder */ | |
3eb08ea5 | 1277 | intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0); |
4e123bd3 MC |
1278 | |
1279 | /* wait for transcoder to be disabled */ | |
3eb08ea5 VS |
1280 | if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans), |
1281 | TRANSCONF_STATE_ENABLE, 50)) | |
b5280cd0 WK |
1282 | drm_err(&dev_priv->drm, |
1283 | "DSI trancoder not disabled\n"); | |
4e123bd3 MC |
1284 | } |
1285 | } | |
1286 | ||
522cc3f7 MC |
1287 | static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) |
1288 | { | |
b7d02c3a | 1289 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
522cc3f7 MC |
1290 | |
1291 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); | |
201963a8 | 1292 | |
522cc3f7 MC |
1293 | /* ensure cmds dispatched to panel */ |
1294 | wait_for_cmds_dispatched_to_panel(encoder); | |
1295 | } | |
1296 | ||
4769b598 MC |
1297 | static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) |
1298 | { | |
1299 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1300 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
4769b598 MC |
1301 | enum port port; |
1302 | enum transcoder dsi_trans; | |
1303 | u32 tmp; | |
1304 | ||
b4b95b05 VK |
1305 | /* disable periodic update mode */ |
1306 | if (is_cmd_mode(intel_dsi)) { | |
1a45d681 AH |
1307 | for_each_dsi_port(port, intel_dsi->ports) |
1308 | intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), | |
1309 | DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); | |
b4b95b05 VK |
1310 | } |
1311 | ||
4769b598 MC |
1312 | /* put dsi link in ULPS */ |
1313 | for_each_dsi_port(port, intel_dsi->ports) { | |
1314 | dsi_trans = dsi_port_to_transcoder(port); | |
1c63f6df | 1315 | tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); |
4769b598 MC |
1316 | tmp |= LINK_ENTER_ULPS; |
1317 | tmp &= ~LINK_ULPS_TYPE_LP11; | |
1c63f6df | 1318 | intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); |
4769b598 | 1319 | |
1c63f6df JN |
1320 | if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & |
1321 | LINK_IN_ULPS), | |
4769b598 | 1322 | 10)) |
b5280cd0 | 1323 | drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); |
4769b598 | 1324 | } |
7aa32f7c MC |
1325 | |
1326 | /* disable ddi function */ | |
1327 | for_each_dsi_port(port, intel_dsi->ports) { | |
1328 | dsi_trans = dsi_port_to_transcoder(port); | |
1a45d681 AH |
1329 | intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), |
1330 | TRANS_DDI_FUNC_ENABLE, 0); | |
7aa32f7c | 1331 | } |
9c83ab1b MC |
1332 | |
1333 | /* disable port sync mode if dual link */ | |
1334 | if (intel_dsi->dual_link) { | |
1335 | for_each_dsi_port(port, intel_dsi->ports) { | |
1336 | dsi_trans = dsi_port_to_transcoder(port); | |
1a45d681 AH |
1337 | intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), |
1338 | PORT_SYNC_MODE_ENABLE, 0); | |
9c83ab1b MC |
1339 | } |
1340 | } | |
4769b598 MC |
1341 | } |
1342 | ||
019cec36 MC |
1343 | static void gen11_dsi_disable_port(struct intel_encoder *encoder) |
1344 | { | |
1345 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1346 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
019cec36 MC |
1347 | enum port port; |
1348 | ||
1026bea0 | 1349 | gen11_dsi_ungate_clocks(encoder); |
019cec36 | 1350 | for_each_dsi_port(port, intel_dsi->ports) { |
1a45d681 | 1351 | intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); |
019cec36 | 1352 | |
1c63f6df | 1353 | if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & |
019cec36 MC |
1354 | DDI_BUF_IS_IDLE), |
1355 | 8)) | |
b5280cd0 WK |
1356 | drm_err(&dev_priv->drm, |
1357 | "DDI port:%c buffer not idle\n", | |
1358 | port_name(port)); | |
019cec36 | 1359 | } |
942d1cf4 | 1360 | gen11_dsi_gate_clocks(encoder); |
019cec36 MC |
1361 | } |
1362 | ||
0f0fe849 MC |
1363 | static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) |
1364 | { | |
1365 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1366 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
0f0fe849 | 1367 | enum port port; |
0f0fe849 | 1368 | |
0e6e0be4 CW |
1369 | for_each_dsi_port(port, intel_dsi->ports) { |
1370 | intel_wakeref_t wakeref; | |
1371 | ||
1372 | wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); | |
99fa4bc2 ID |
1373 | intel_display_power_put(dev_priv, |
1374 | port == PORT_A ? | |
0ba2661d ID |
1375 | POWER_DOMAIN_PORT_DDI_IO_A : |
1376 | POWER_DOMAIN_PORT_DDI_IO_B, | |
99fa4bc2 | 1377 | wakeref); |
0e6e0be4 | 1378 | } |
0f0fe849 MC |
1379 | |
1380 | /* set mode to DDI */ | |
1a45d681 AH |
1381 | for_each_dsi_port(port, intel_dsi->ports) |
1382 | intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), | |
1383 | COMBO_PHY_MODE_DSI, 0); | |
0f0fe849 MC |
1384 | } |
1385 | ||
ede9771d VS |
1386 | static void gen11_dsi_disable(struct intel_atomic_state *state, |
1387 | struct intel_encoder *encoder, | |
e2758048 MC |
1388 | const struct intel_crtc_state *old_crtc_state, |
1389 | const struct drm_connector_state *old_conn_state) | |
d9d996b6 | 1390 | { |
b7d02c3a | 1391 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
d9d996b6 MC |
1392 | |
1393 | /* step1: turn off backlight */ | |
1394 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); | |
c0a52f8b | 1395 | intel_backlight_disable(old_conn_state); |
a57aa1e3 VS |
1396 | } |
1397 | ||
1398 | static void gen11_dsi_post_disable(struct intel_atomic_state *state, | |
1399 | struct intel_encoder *encoder, | |
1400 | const struct intel_crtc_state *old_crtc_state, | |
1401 | const struct drm_connector_state *old_conn_state) | |
1402 | { | |
5263a63c | 1403 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
3d41ec41 | 1404 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
a57aa1e3 VS |
1405 | |
1406 | intel_crtc_vblank_off(old_crtc_state); | |
4e123bd3 MC |
1407 | |
1408 | /* step2d,e: disable transcoder and wait */ | |
1409 | gen11_dsi_disable_transcoder(encoder); | |
522cc3f7 | 1410 | |
544021e3 TU |
1411 | /* Wa_1409054076:icl,jsl,ehl */ |
1412 | icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); | |
1413 | ||
522cc3f7 MC |
1414 | /* step2f,g: powerdown panel */ |
1415 | gen11_dsi_powerdown_panel(encoder); | |
4769b598 MC |
1416 | |
1417 | /* step2h,i,j: deconfig trancoder */ | |
1418 | gen11_dsi_deconfigure_trancoder(encoder); | |
019cec36 | 1419 | |
29428c85 VS |
1420 | intel_dsc_disable(old_crtc_state); |
1421 | skl_scaler_disable(old_crtc_state); | |
1422 | ||
019cec36 MC |
1423 | /* step3: disable port */ |
1424 | gen11_dsi_disable_port(encoder); | |
0f0fe849 | 1425 | |
b4b95b05 VK |
1426 | gen11_dsi_config_util_pin(encoder, false); |
1427 | ||
0f0fe849 MC |
1428 | /* step4: disable IO power */ |
1429 | gen11_dsi_disable_io_power(encoder); | |
5263a63c VS |
1430 | |
1431 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); | |
1432 | ||
1433 | msleep(intel_dsi->panel_off_delay); | |
1434 | intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); | |
1435 | ||
1436 | intel_dsi->panel_power_off_time = ktime_get_boottime(); | |
773b4b54 VS |
1437 | } |
1438 | ||
2b68392e JN |
1439 | static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, |
1440 | struct drm_display_mode *mode) | |
1441 | { | |
e0ef2daa VS |
1442 | struct drm_i915_private *i915 = to_i915(connector->dev); |
1443 | enum drm_mode_status status; | |
1444 | ||
1445 | status = intel_cpu_transcoder_mode_valid(i915, mode); | |
1446 | if (status != MODE_OK) | |
1447 | return status; | |
1448 | ||
2b68392e JN |
1449 | /* FIXME: DSC? */ |
1450 | return intel_dsi_mode_valid(connector, mode); | |
1451 | } | |
1452 | ||
3c23ed13 VK |
1453 | static void gen11_dsi_get_timings(struct intel_encoder *encoder, |
1454 | struct intel_crtc_state *pipe_config) | |
1455 | { | |
b7d02c3a | 1456 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
3c23ed13 | 1457 | struct drm_display_mode *adjusted_mode = |
1326a92c | 1458 | &pipe_config->hw.adjusted_mode; |
3c23ed13 | 1459 | |
59a266f0 AN |
1460 | if (pipe_config->dsc.compressed_bpp_x16) { |
1461 | int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16); | |
c2bb35e9 VK |
1462 | int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
1463 | ||
1464 | adjusted_mode->crtc_htotal = | |
1465 | DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); | |
1466 | adjusted_mode->crtc_hsync_start = | |
1467 | DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); | |
1468 | adjusted_mode->crtc_hsync_end = | |
1469 | DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); | |
1470 | } | |
1471 | ||
3c23ed13 VK |
1472 | if (intel_dsi->dual_link) { |
1473 | adjusted_mode->crtc_hdisplay *= 2; | |
1474 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1475 | adjusted_mode->crtc_hdisplay -= | |
1476 | intel_dsi->pixel_overlap; | |
1477 | adjusted_mode->crtc_htotal *= 2; | |
1478 | } | |
1479 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; | |
1480 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; | |
1481 | ||
1482 | if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { | |
1483 | if (intel_dsi->dual_link) { | |
1484 | adjusted_mode->crtc_hsync_start *= 2; | |
1485 | adjusted_mode->crtc_hsync_end *= 2; | |
1486 | } | |
1487 | } | |
1488 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; | |
1489 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
1490 | } | |
1491 | ||
cebb28ac VK |
1492 | static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) |
1493 | { | |
1494 | struct drm_device *dev = intel_dsi->base.base.dev; | |
1495 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1496 | enum transcoder dsi_trans; | |
1497 | u32 val; | |
1498 | ||
1499 | if (intel_dsi->ports == BIT(PORT_B)) | |
1500 | dsi_trans = TRANSCODER_DSI_1; | |
1501 | else | |
1502 | dsi_trans = TRANSCODER_DSI_0; | |
1503 | ||
1504 | val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); | |
1505 | return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); | |
1506 | } | |
1507 | ||
5682a41f VK |
1508 | static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, |
1509 | struct intel_crtc_state *pipe_config) | |
1510 | { | |
1511 | if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) | |
1512 | pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | | |
1513 | I915_MODE_FLAG_DSI_USE_TE0; | |
1514 | else if (intel_dsi->ports == BIT(PORT_B)) | |
1515 | pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; | |
1516 | else | |
1517 | pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; | |
1518 | } | |
1519 | ||
8327af28 VK |
1520 | static void gen11_dsi_get_config(struct intel_encoder *encoder, |
1521 | struct intel_crtc_state *pipe_config) | |
1522 | { | |
2225f3c6 | 1523 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
b7d02c3a | 1524 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
8327af28 | 1525 | |
351221ff | 1526 | intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); |
e3c54da0 | 1527 | |
1326a92c | 1528 | pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; |
e3c54da0 | 1529 | if (intel_dsi->dual_link) |
1326a92c | 1530 | pipe_config->hw.adjusted_mode.crtc_clock *= 2; |
e3c54da0 | 1531 | |
3c23ed13 | 1532 | gen11_dsi_get_timings(encoder, pipe_config); |
8327af28 | 1533 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); |
c640f6c5 | 1534 | pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); |
cebb28ac | 1535 | |
5682a41f VK |
1536 | /* Get the details on which TE should be enabled */ |
1537 | if (is_cmd_mode(intel_dsi)) | |
1538 | gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); | |
1539 | ||
cebb28ac | 1540 | if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) |
af157b76 | 1541 | pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; |
8327af28 VK |
1542 | } |
1543 | ||
544021e3 TU |
1544 | static void gen11_dsi_sync_state(struct intel_encoder *encoder, |
1545 | const struct intel_crtc_state *crtc_state) | |
1546 | { | |
1547 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
7194dc99 ID |
1548 | struct intel_crtc *intel_crtc; |
1549 | enum pipe pipe; | |
1550 | ||
1551 | if (!crtc_state) | |
1552 | return; | |
1553 | ||
1554 | intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); | |
1555 | pipe = intel_crtc->pipe; | |
544021e3 TU |
1556 | |
1557 | /* wa verify 1409054076:icl,jsl,ehl */ | |
1558 | if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && | |
1559 | !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) | |
1560 | drm_dbg_kms(&dev_priv->drm, | |
1561 | "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", | |
1562 | encoder->base.base.id, | |
1563 | encoder->base.name); | |
1564 | } | |
1565 | ||
2b68392e JN |
1566 | static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, |
1567 | struct intel_crtc_state *crtc_state) | |
1568 | { | |
1569 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1570 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; | |
005e9537 | 1571 | int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; |
2b68392e JN |
1572 | bool use_dsc; |
1573 | int ret; | |
1574 | ||
1575 | use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); | |
1576 | if (!use_dsc) | |
1577 | return 0; | |
1578 | ||
1579 | if (crtc_state->pipe_bpp < 8 * 3) | |
1580 | return -EINVAL; | |
1581 | ||
1582 | /* FIXME: split only when necessary */ | |
1583 | if (crtc_state->dsc.slice_count > 1) | |
1584 | crtc_state->dsc.dsc_split = true; | |
1585 | ||
420798a0 JN |
1586 | /* FIXME: initialize from VBT */ |
1587 | vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; | |
1588 | ||
e72df53d AN |
1589 | vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; |
1590 | ||
3126977d | 1591 | ret = intel_dsc_compute_params(crtc_state); |
2b68392e JN |
1592 | if (ret) |
1593 | return ret; | |
1594 | ||
1595 | /* DSI specific sanity checks on the common code */ | |
3dbe5e11 PB |
1596 | drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); |
1597 | drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); | |
1598 | drm_WARN_ON(&dev_priv->drm, | |
1599 | vdsc_cfg->pic_width % vdsc_cfg->slice_width); | |
1600 | drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); | |
1601 | drm_WARN_ON(&dev_priv->drm, | |
1602 | vdsc_cfg->pic_height % vdsc_cfg->slice_height); | |
2b68392e JN |
1603 | |
1604 | ret = drm_dsc_compute_rc_parameters(vdsc_cfg); | |
1605 | if (ret) | |
1606 | return ret; | |
1607 | ||
1608 | crtc_state->dsc.compression_enable = true; | |
1609 | ||
1610 | return 0; | |
1611 | } | |
1612 | ||
204474a6 LP |
1613 | static int gen11_dsi_compute_config(struct intel_encoder *encoder, |
1614 | struct intel_crtc_state *pipe_config, | |
1615 | struct drm_connector_state *conn_state) | |
d04afb15 | 1616 | { |
dd10a80f | 1617 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
d04afb15 MC |
1618 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
1619 | base); | |
1620 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
d04afb15 | 1621 | struct drm_display_mode *adjusted_mode = |
d7ff281c VS |
1622 | &pipe_config->hw.adjusted_mode; |
1623 | int ret; | |
d04afb15 | 1624 | |
a04d27cd | 1625 | pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; |
30bd7efd | 1626 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
cff4c2c6 VS |
1627 | |
1628 | ret = intel_panel_compute_config(intel_connector, adjusted_mode); | |
1629 | if (ret) | |
1630 | return ret; | |
d7ff281c | 1631 | |
4b93f49d | 1632 | ret = intel_panel_fitting(pipe_config, conn_state); |
d7ff281c VS |
1633 | if (ret) |
1634 | return ret; | |
d04afb15 MC |
1635 | |
1636 | adjusted_mode->flags = 0; | |
1637 | ||
1638 | /* Dual link goes to trancoder DSI'0' */ | |
1639 | if (intel_dsi->ports == BIT(PORT_B)) | |
1640 | pipe_config->cpu_transcoder = TRANSCODER_DSI_1; | |
1641 | else | |
1642 | pipe_config->cpu_transcoder = TRANSCODER_DSI_0; | |
1643 | ||
50003bf5 JN |
1644 | if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) |
1645 | pipe_config->pipe_bpp = 24; | |
1646 | else | |
1647 | pipe_config->pipe_bpp = 18; | |
1648 | ||
d04afb15 | 1649 | pipe_config->clock_set = true; |
2b68392e JN |
1650 | |
1651 | if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) | |
dd10a80f | 1652 | drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); |
2b68392e | 1653 | |
04865139 | 1654 | pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; |
d04afb15 | 1655 | |
f78a862d VK |
1656 | /* |
1657 | * In case of TE GATE cmd mode, we | |
1658 | * receive TE from the slave if | |
1659 | * dual link is enabled | |
1660 | */ | |
5682a41f VK |
1661 | if (is_cmd_mode(intel_dsi)) |
1662 | gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); | |
f78a862d | 1663 | |
204474a6 | 1664 | return 0; |
d04afb15 MC |
1665 | } |
1666 | ||
3a52fb7e ID |
1667 | static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, |
1668 | struct intel_crtc_state *crtc_state) | |
ab841148 | 1669 | { |
2b68392e JN |
1670 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
1671 | ||
b7d02c3a VS |
1672 | get_dsi_io_power_domains(i915, |
1673 | enc_to_intel_dsi(encoder)); | |
ab841148 MC |
1674 | } |
1675 | ||
1676 | static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, | |
1677 | enum pipe *pipe) | |
1678 | { | |
1679 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 1680 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
ab841148 | 1681 | enum transcoder dsi_trans; |
0e6e0be4 CW |
1682 | intel_wakeref_t wakeref; |
1683 | enum port port; | |
ab841148 | 1684 | bool ret = false; |
0e6e0be4 | 1685 | u32 tmp; |
ab841148 | 1686 | |
0e6e0be4 CW |
1687 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1688 | encoder->power_domain); | |
1689 | if (!wakeref) | |
ab841148 MC |
1690 | return false; |
1691 | ||
1692 | for_each_dsi_port(port, intel_dsi->ports) { | |
1693 | dsi_trans = dsi_port_to_transcoder(port); | |
1c63f6df | 1694 | tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); |
ab841148 MC |
1695 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1696 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1697 | *pipe = PIPE_A; | |
1698 | break; | |
1699 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1700 | *pipe = PIPE_B; | |
1701 | break; | |
1702 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1703 | *pipe = PIPE_C; | |
1704 | break; | |
4d89adc7 JRS |
1705 | case TRANS_DDI_EDP_INPUT_D_ONOFF: |
1706 | *pipe = PIPE_D; | |
1707 | break; | |
ab841148 | 1708 | default: |
b5280cd0 | 1709 | drm_err(&dev_priv->drm, "Invalid PIPE input\n"); |
ab841148 MC |
1710 | goto out; |
1711 | } | |
1712 | ||
3eb08ea5 VS |
1713 | tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans)); |
1714 | ret = tmp & TRANSCONF_ENABLE; | |
ab841148 MC |
1715 | } |
1716 | out: | |
0e6e0be4 | 1717 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
ab841148 MC |
1718 | return ret; |
1719 | } | |
1720 | ||
b671d6ef ID |
1721 | static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, |
1722 | struct intel_crtc_state *crtc_state) | |
1723 | { | |
1724 | if (crtc_state->dsc.compression_enable) { | |
1725 | drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); | |
1726 | crtc_state->uapi.mode_changed = true; | |
1727 | ||
1728 | return false; | |
1729 | } | |
1730 | ||
1731 | return true; | |
1732 | } | |
1733 | ||
e2758048 MC |
1734 | static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) |
1735 | { | |
1736 | intel_encoder_destroy(encoder); | |
1737 | } | |
1738 | ||
1739 | static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { | |
1740 | .destroy = gen11_dsi_encoder_destroy, | |
1741 | }; | |
1742 | ||
1743 | static const struct drm_connector_funcs gen11_dsi_connector_funcs = { | |
b81dddb9 | 1744 | .detect = intel_panel_detect, |
e2758048 MC |
1745 | .late_register = intel_connector_register, |
1746 | .early_unregister = intel_connector_unregister, | |
1747 | .destroy = intel_connector_destroy, | |
1748 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1749 | .atomic_get_property = intel_digital_connector_atomic_get_property, | |
1750 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
1751 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
1752 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, | |
1753 | }; | |
1754 | ||
1755 | static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { | |
1756 | .get_modes = intel_dsi_get_modes, | |
2b68392e | 1757 | .mode_valid = gen11_dsi_mode_valid, |
e2758048 MC |
1758 | .atomic_check = intel_digital_connector_atomic_check, |
1759 | }; | |
1760 | ||
c5f9c934 MC |
1761 | static int gen11_dsi_host_attach(struct mipi_dsi_host *host, |
1762 | struct mipi_dsi_device *dsi) | |
1763 | { | |
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | static int gen11_dsi_host_detach(struct mipi_dsi_host *host, | |
1768 | struct mipi_dsi_device *dsi) | |
1769 | { | |
1770 | return 0; | |
1771 | } | |
1772 | ||
1773 | static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, | |
1774 | const struct mipi_dsi_msg *msg) | |
1775 | { | |
1776 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
1777 | struct mipi_dsi_packet dsi_pkt; | |
1778 | ssize_t ret; | |
1779 | bool enable_lpdt = false; | |
1780 | ||
1781 | ret = mipi_dsi_create_packet(&dsi_pkt, msg); | |
1782 | if (ret < 0) | |
1783 | return ret; | |
1784 | ||
1785 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) | |
1786 | enable_lpdt = true; | |
1787 | ||
c5f9c934 MC |
1788 | /* only long packet contains payload */ |
1789 | if (mipi_dsi_packet_format_is_long(msg->type)) { | |
3e2947cd | 1790 | ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); |
c5f9c934 MC |
1791 | if (ret < 0) |
1792 | return ret; | |
1793 | } | |
1794 | ||
5ebd50d3 | 1795 | /* send packet header */ |
3e2947cd | 1796 | ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); |
5ebd50d3 LS |
1797 | if (ret < 0) |
1798 | return ret; | |
1799 | ||
c5f9c934 MC |
1800 | //TODO: add payload receive code if needed |
1801 | ||
1802 | ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; | |
1803 | ||
1804 | return ret; | |
1805 | } | |
1806 | ||
1807 | static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { | |
1808 | .attach = gen11_dsi_host_attach, | |
1809 | .detach = gen11_dsi_host_detach, | |
1810 | .transfer = gen11_dsi_host_transfer, | |
1811 | }; | |
1812 | ||
2def5ae7 HG |
1813 | #define ICL_PREPARE_CNT_MAX 0x7 |
1814 | #define ICL_CLK_ZERO_CNT_MAX 0xf | |
1815 | #define ICL_TRAIL_CNT_MAX 0x7 | |
1816 | #define ICL_TCLK_PRE_CNT_MAX 0x3 | |
1817 | #define ICL_TCLK_POST_CNT_MAX 0x7 | |
1818 | #define ICL_HS_ZERO_CNT_MAX 0xf | |
1819 | #define ICL_EXIT_ZERO_CNT_MAX 0x7 | |
1820 | ||
1821 | static void icl_dphy_param_init(struct intel_dsi *intel_dsi) | |
1822 | { | |
1823 | struct drm_device *dev = intel_dsi->base.base.dev; | |
1824 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3cf05076 VS |
1825 | struct intel_connector *connector = intel_dsi->attached_connector; |
1826 | struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; | |
2def5ae7 HG |
1827 | u32 tlpx_ns; |
1828 | u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; | |
1829 | u32 ths_prepare_ns, tclk_trail_ns; | |
1830 | u32 hs_zero_cnt; | |
fc3bbd57 | 1831 | u32 tclk_pre_cnt; |
2def5ae7 HG |
1832 | |
1833 | tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); | |
1834 | ||
1835 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); | |
1836 | ths_prepare_ns = max(mipi_config->ths_prepare, | |
1837 | mipi_config->tclk_prepare); | |
1838 | ||
1839 | /* | |
1840 | * prepare cnt in escape clocks | |
1841 | * this field represents a hexadecimal value with a precision | |
1842 | * of 1.2 – i.e. the most significant bit is the integer | |
1843 | * and the least significant 2 bits are fraction bits. | |
1844 | * so, the field can represent a range of 0.25 to 1.75 | |
1845 | */ | |
1846 | prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); | |
1847 | if (prepare_cnt > ICL_PREPARE_CNT_MAX) { | |
b5280cd0 WK |
1848 | drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", |
1849 | prepare_cnt); | |
2def5ae7 HG |
1850 | prepare_cnt = ICL_PREPARE_CNT_MAX; |
1851 | } | |
1852 | ||
1853 | /* clk zero count in escape clocks */ | |
1854 | clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - | |
1855 | ths_prepare_ns, tlpx_ns); | |
1856 | if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { | |
b5280cd0 WK |
1857 | drm_dbg_kms(&dev_priv->drm, |
1858 | "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); | |
2def5ae7 HG |
1859 | clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; |
1860 | } | |
1861 | ||
1862 | /* trail cnt in escape clocks*/ | |
1863 | trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); | |
1864 | if (trail_cnt > ICL_TRAIL_CNT_MAX) { | |
b5280cd0 WK |
1865 | drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", |
1866 | trail_cnt); | |
2def5ae7 HG |
1867 | trail_cnt = ICL_TRAIL_CNT_MAX; |
1868 | } | |
1869 | ||
1870 | /* tclk pre count in escape clocks */ | |
1871 | tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); | |
1872 | if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { | |
b5280cd0 WK |
1873 | drm_dbg_kms(&dev_priv->drm, |
1874 | "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); | |
2def5ae7 HG |
1875 | tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; |
1876 | } | |
1877 | ||
2def5ae7 HG |
1878 | /* hs zero cnt in escape clocks */ |
1879 | hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - | |
1880 | ths_prepare_ns, tlpx_ns); | |
1881 | if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { | |
b5280cd0 WK |
1882 | drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", |
1883 | hs_zero_cnt); | |
2def5ae7 HG |
1884 | hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; |
1885 | } | |
1886 | ||
1887 | /* hs exit zero cnt in escape clocks */ | |
1888 | exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); | |
1889 | if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { | |
b5280cd0 WK |
1890 | drm_dbg_kms(&dev_priv->drm, |
1891 | "exit_zero_cnt out of range (%d)\n", | |
1892 | exit_zero_cnt); | |
2def5ae7 HG |
1893 | exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; |
1894 | } | |
1895 | ||
1896 | /* clock lane dphy timings */ | |
1897 | intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | | |
1898 | CLK_PREPARE(prepare_cnt) | | |
1899 | CLK_ZERO_OVERRIDE | | |
1900 | CLK_ZERO(clk_zero_cnt) | | |
1901 | CLK_PRE_OVERRIDE | | |
1902 | CLK_PRE(tclk_pre_cnt) | | |
2def5ae7 HG |
1903 | CLK_TRAIL_OVERRIDE | |
1904 | CLK_TRAIL(trail_cnt)); | |
1905 | ||
1906 | /* data lanes dphy timings */ | |
1907 | intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | | |
1908 | HS_PREPARE(prepare_cnt) | | |
1909 | HS_ZERO_OVERRIDE | | |
1910 | HS_ZERO(hs_zero_cnt) | | |
1911 | HS_TRAIL_OVERRIDE | | |
1912 | HS_TRAIL(trail_cnt) | | |
1913 | HS_EXIT_OVERRIDE | | |
1914 | HS_EXIT(exit_zero_cnt)); | |
1915 | ||
1916 | intel_dsi_log_params(intel_dsi); | |
1917 | } | |
1918 | ||
f6d39f56 | 1919 | static void icl_dsi_add_properties(struct intel_connector *connector) |
f384e48d | 1920 | { |
f6d39f56 VS |
1921 | const struct drm_display_mode *fixed_mode = |
1922 | intel_panel_preferred_fixed_mode(connector); | |
f384e48d | 1923 | |
6ac2f04b | 1924 | intel_attach_scaling_mode_property(&connector->base); |
f384e48d | 1925 | |
69654c63 | 1926 | drm_connector_set_panel_orientation_with_quirk(&connector->base, |
dee54887 VS |
1927 | intel_dsi_get_panel_orientation(connector), |
1928 | fixed_mode->hdisplay, | |
1929 | fixed_mode->vdisplay); | |
f384e48d VK |
1930 | } |
1931 | ||
021a62a5 VS |
1932 | void icl_dsi_init(struct drm_i915_private *dev_priv, |
1933 | const struct intel_bios_encoder_data *devdata) | |
bf4d57ff | 1934 | { |
e2758048 MC |
1935 | struct intel_dsi *intel_dsi; |
1936 | struct intel_encoder *encoder; | |
1937 | struct intel_connector *intel_connector; | |
1938 | struct drm_connector *connector; | |
bf4d57ff MC |
1939 | enum port port; |
1940 | ||
021a62a5 VS |
1941 | port = intel_bios_encoder_port(devdata); |
1942 | if (port == PORT_NONE) | |
bf4d57ff | 1943 | return; |
e2758048 MC |
1944 | |
1945 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); | |
1946 | if (!intel_dsi) | |
1947 | return; | |
1948 | ||
1949 | intel_connector = intel_connector_alloc(); | |
1950 | if (!intel_connector) { | |
1951 | kfree(intel_dsi); | |
1952 | return; | |
1953 | } | |
1954 | ||
1955 | encoder = &intel_dsi->base; | |
1956 | intel_dsi->attached_connector = intel_connector; | |
1957 | connector = &intel_connector->base; | |
1958 | ||
021a62a5 VS |
1959 | encoder->devdata = devdata; |
1960 | ||
e2758048 | 1961 | /* register DSI encoder with DRM subsystem */ |
3703060d | 1962 | drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs, |
e2758048 MC |
1963 | DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); |
1964 | ||
95f2f4db | 1965 | encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; |
e2758048 | 1966 | encoder->pre_enable = gen11_dsi_pre_enable; |
21fd23ac | 1967 | encoder->enable = gen11_dsi_enable; |
e2758048 | 1968 | encoder->disable = gen11_dsi_disable; |
773b4b54 | 1969 | encoder->post_disable = gen11_dsi_post_disable; |
e2758048 | 1970 | encoder->port = port; |
8327af28 | 1971 | encoder->get_config = gen11_dsi_get_config; |
544021e3 | 1972 | encoder->sync_state = gen11_dsi_sync_state; |
c0a52f8b | 1973 | encoder->update_pipe = intel_backlight_update; |
d04afb15 | 1974 | encoder->compute_config = gen11_dsi_compute_config; |
ab841148 | 1975 | encoder->get_hw_state = gen11_dsi_get_hw_state; |
b671d6ef | 1976 | encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; |
e2758048 MC |
1977 | encoder->type = INTEL_OUTPUT_DSI; |
1978 | encoder->cloneable = 0; | |
34053ee1 | 1979 | encoder->pipe_mask = ~0; |
e2758048 | 1980 | encoder->power_domain = POWER_DOMAIN_PORT_DSI; |
ab841148 | 1981 | encoder->get_power_domains = gen11_dsi_get_power_domains; |
87bd8498 | 1982 | encoder->disable_clock = gen11_dsi_gate_clocks; |
0fbd8694 | 1983 | encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; |
e3972476 | 1984 | encoder->shutdown = intel_dsi_shutdown; |
e2758048 MC |
1985 | |
1986 | /* register DSI connector with DRM subsystem */ | |
3703060d | 1987 | drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs, |
e2758048 MC |
1988 | DRM_MODE_CONNECTOR_DSI); |
1989 | drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); | |
1990 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
ab841148 | 1991 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
e2758048 MC |
1992 | |
1993 | /* attach connector to encoder */ | |
1994 | intel_connector_attach_encoder(intel_connector, encoder); | |
1995 | ||
201963a8 VS |
1996 | intel_dsi->panel_power_off_time = ktime_get_boottime(); |
1997 | ||
ba00eb6a | 1998 | intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL); |
3cf05076 | 1999 | |
3703060d | 2000 | mutex_lock(&dev_priv->drm.mode_config.mutex); |
db10c14a | 2001 | intel_panel_add_vbt_lfp_fixed_mode(intel_connector); |
3703060d | 2002 | mutex_unlock(&dev_priv->drm.mode_config.mutex); |
e2758048 | 2003 | |
db10c14a | 2004 | if (!intel_panel_preferred_fixed_mode(intel_connector)) { |
b5280cd0 | 2005 | drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); |
e2758048 MC |
2006 | goto err; |
2007 | } | |
2008 | ||
15d045fd | 2009 | intel_panel_init(intel_connector, NULL); |
db10c14a | 2010 | |
c0a52f8b | 2011 | intel_backlight_setup(intel_connector, INVALID_PIPE); |
e2758048 | 2012 | |
3cf05076 | 2013 | if (intel_connector->panel.vbt.dsi.config->dual_link) |
972d607c MC |
2014 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); |
2015 | else | |
2016 | intel_dsi->ports = BIT(port); | |
2017 | ||
f4a6c7a4 JN |
2018 | if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) |
2019 | intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; | |
2020 | ||
f4a6c7a4 JN |
2021 | if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) |
2022 | intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; | |
2023 | ||
c5f9c934 MC |
2024 | for_each_dsi_port(port, intel_dsi->ports) { |
2025 | struct intel_dsi_host *host; | |
2026 | ||
2027 | host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); | |
2028 | if (!host) | |
2029 | goto err; | |
2030 | ||
2031 | intel_dsi->dsi_hosts[port] = host; | |
2032 | } | |
2033 | ||
e2758048 | 2034 | if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { |
b5280cd0 | 2035 | drm_dbg_kms(&dev_priv->drm, "no device found\n"); |
e2758048 MC |
2036 | goto err; |
2037 | } | |
2038 | ||
2def5ae7 | 2039 | icl_dphy_param_init(intel_dsi); |
f384e48d | 2040 | |
f6d39f56 | 2041 | icl_dsi_add_properties(intel_connector); |
e2758048 MC |
2042 | return; |
2043 | ||
2044 | err: | |
d1613061 | 2045 | drm_connector_cleanup(connector); |
e2758048 MC |
2046 | drm_encoder_cleanup(&encoder->base); |
2047 | kfree(intel_dsi); | |
2048 | kfree(intel_connector); | |
bf4d57ff | 2049 | } |