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[linux-2.6-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
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e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
7e567624 23#include <sound/hdmi-codec.h>
e7792ce2
RC		 24
25#include <drm/drmP.h>
9736e988 26#include <drm/drm_atomic_helper.h>
e7792ce2 27#include <drm/drm_crtc_helper.h>
e7792ce2 28#include <drm/drm_edid.h>
5dbcf319 29#include <drm/drm_of.h>
c4c11dd1 30#include <drm/i2c/tda998x.h>
e7792ce2
RC		 31
32#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
33
7e567624
JS		 34struct tda998x_audio_port {
35 u8 format; /* AFMT_xxx */
36 u8 config; /* AP value */
37};
38
e7792ce2
RC		 39struct tda998x_priv {
40 struct i2c_client *cec;
2f7f730a 41 struct i2c_client *hdmi;
ed9a8426 42 struct mutex mutex;
e66e03ab 43 u16 rev;
14e5b588 44 u8 cec_addr;
e66e03ab 45 u8 current_page;
3cb43378 46 bool is_on;
896a4130 47 bool supports_infoframes;
8f3f21f6 48 bool sink_has_audio;
5e74c22c
RK		 49 u8 vip_cntrl_0;
50 u8 vip_cntrl_1;
51 u8 vip_cntrl_2;
319e658c 52 unsigned long tmds_clock;
95db3b25 53 struct tda998x_audio_params audio_params;
12473b7d 54
7e567624
JS		 55 struct platform_device *audio_pdev;
56 struct mutex audio_mutex;
57
12473b7d
JFM		 58 wait_queue_head_t wq_edid;
59 volatile int wq_edid_wait;
0fc6f44d
RK		 60
61 struct work_struct detect_work;
62 struct timer_list edid_delay_timer;
63 wait_queue_head_t edid_delay_waitq;
64 bool edid_delay_active;
78e401f9
RK		 65
66 struct drm_encoder encoder;
eed64b59 67 struct drm_connector connector;
7e567624
JS		 68
69 struct tda998x_audio_port audio_port[2];
e7792ce2
RC		 70};
71
9525c4dd
RK		 72#define conn_to_tda998x_priv(x) \
73 container_of(x, struct tda998x_priv, connector)
74
75#define enc_to_tda998x_priv(x) \
76 container_of(x, struct tda998x_priv, encoder)
77
e7792ce2
RC		 78/* The TDA9988 series of devices use a paged register scheme.. to simplify
79 * things we encode the page # in upper bits of the register #. To read/
80 * write a given register, we need to make sure CURPAGE register is set
81 * appropriately. Which implies reads/writes are not atomic. Fun!
82 */
83
84#define REG(page, addr) (((page) << 8) | (addr))
85#define REG2ADDR(reg) ((reg) & 0xff)
86#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
87
88#define REG_CURPAGE 0xff /* write */
89
90
91/* Page 00h: General Control */
92#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
93#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
94# define MAIN_CNTRL0_SR (1 << 0)
95# define MAIN_CNTRL0_DECS (1 << 1)
96# define MAIN_CNTRL0_DEHS (1 << 2)
97# define MAIN_CNTRL0_CECS (1 << 3)
98# define MAIN_CNTRL0_CEHS (1 << 4)
99# define MAIN_CNTRL0_SCALER (1 << 7)
100#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
101#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
102# define SOFTRESET_AUDIO (1 << 0)
103# define SOFTRESET_I2C_MASTER (1 << 1)
104#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
105#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
106#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
107# define I2C_MASTER_DIS_MM (1 << 0)
108# define I2C_MASTER_DIS_FILT (1 << 1)
109# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1 110#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
9476ed2e
RK		 111# define FEAT_POWERDOWN_PREFILT BIT(0)
112# define FEAT_POWERDOWN_CSC BIT(1)
c4c11dd1 113# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 114#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
115#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
116#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
117# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 118#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 119#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
120#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
121#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
122#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
123#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
124# define VIP_CNTRL_0_MIRR_A (1 << 7)
125# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
126# define VIP_CNTRL_0_MIRR_B (1 << 3)
127# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
128#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
129# define VIP_CNTRL_1_MIRR_C (1 << 7)
130# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
131# define VIP_CNTRL_1_MIRR_D (1 << 3)
132# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
133#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
134# define VIP_CNTRL_2_MIRR_E (1 << 7)
135# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
136# define VIP_CNTRL_2_MIRR_F (1 << 3)
137# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
138#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
139# define VIP_CNTRL_3_X_TGL (1 << 0)
140# define VIP_CNTRL_3_H_TGL (1 << 1)
141# define VIP_CNTRL_3_V_TGL (1 << 2)
142# define VIP_CNTRL_3_EMB (1 << 3)
143# define VIP_CNTRL_3_SYNC_DE (1 << 4)
144# define VIP_CNTRL_3_SYNC_HS (1 << 5)
145# define VIP_CNTRL_3_DE_INT (1 << 6)
146# define VIP_CNTRL_3_EDGE (1 << 7)
147#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
148# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
149# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
150# define VIP_CNTRL_4_CCIR656 (1 << 4)
151# define VIP_CNTRL_4_656_ALT (1 << 5)
152# define VIP_CNTRL_4_TST_656 (1 << 6)
153# define VIP_CNTRL_4_TST_PAT (1 << 7)
154#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
155# define VIP_CNTRL_5_CKCASE (1 << 0)
156# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 157#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 158# define MUX_AP_SELECT_I2S 0x64
159# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 160#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 161#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
162# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
163# define MAT_CONTRL_MAT_BP (1 << 2)
164#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
165#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
166#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
167#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
168#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
169#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
170#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
171#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
172#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
173#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
174#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
175#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
176#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
177#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
178#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
179#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
180#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 181#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
182#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 183#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
184#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 185#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
186#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 187#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
188#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
189#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
190#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
191#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
192#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
193#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
194#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
195#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
196#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 197#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
198#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
199#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
200#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 201#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
202#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
203#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
204#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
205#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 206# define TBG_CNTRL_0_TOP_TGL (1 << 0)
207# define TBG_CNTRL_0_TOP_SEL (1 << 1)
208# define TBG_CNTRL_0_DE_EXT (1 << 2)
209# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 210# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
211# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
212# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
213#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 214# define TBG_CNTRL_1_H_TGL (1 << 0)
215# define TBG_CNTRL_1_V_TGL (1 << 1)
216# define TBG_CNTRL_1_TGL_EN (1 << 2)
217# define TBG_CNTRL_1_X_EXT (1 << 3)
218# define TBG_CNTRL_1_H_EXT (1 << 4)
219# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 220# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
221#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
222#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
223# define HVF_CNTRL_0_SM (1 << 7)
224# define HVF_CNTRL_0_RWB (1 << 6)
225# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
226# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
227#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
228# define HVF_CNTRL_1_FOR (1 << 0)
229# define HVF_CNTRL_1_YUVBLK (1 << 1)
230# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
231# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
232# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
233#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 234#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
235# define I2S_FORMAT(x) (((x) & 3) << 0)
236#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 237# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
238# define AIP_CLKSEL_AIP_I2S (1 << 3)
239# define AIP_CLKSEL_FS_ACLK (0 << 0)
240# define AIP_CLKSEL_FS_MCLK (1 << 0)
241# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 242
243/* Page 02h: PLL settings */
244#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
245# define PLL_SERIAL_1_SRL_FDN (1 << 0)
246# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
247# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
248#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 249# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 250# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
251#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
252# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
253# define PLL_SERIAL_3_SRL_DE (1 << 2)
254# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
255#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
256#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
257#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
258#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
259#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
260#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
261#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
262#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
263#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 264# define AUDIO_DIV_SERCLK_1 0
265# define AUDIO_DIV_SERCLK_2 1
266# define AUDIO_DIV_SERCLK_4 2
267# define AUDIO_DIV_SERCLK_8 3
268# define AUDIO_DIV_SERCLK_16 4
269# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 270#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
271# define SEL_CLK_SEL_CLK1 (1 << 0)
272# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
273# define SEL_CLK_ENA_SC_CLK (1 << 3)
274#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
275
276
277/* Page 09h: EDID Control */
278#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
279/* next 127 successive registers are the EDID block */
280#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
281#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
282#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
283#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
284#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
285
286
287/* Page 10h: information frames and packets */
c4c11dd1
RK		 288#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
289#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
290#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
291#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
292#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 293
294
295/* Page 11h: audio settings and content info packets */
296#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
297# define AIP_CNTRL_0_RST_FIFO (1 << 0)
298# define AIP_CNTRL_0_SWAP (1 << 1)
299# define AIP_CNTRL_0_LAYOUT (1 << 2)
300# define AIP_CNTRL_0_ACR_MAN (1 << 5)
301# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 302#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
303# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
304# define CA_I2S_HBR_CHSTAT (1 << 6)
305#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
306#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
307#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
308#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
309#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
310#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
311#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
312#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
313# define CTS_N_K(x) (((x) & 7) << 0)
314# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 315#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
316# define ENC_CNTRL_RST_ENC (1 << 0)
317# define ENC_CNTRL_RST_SEL (1 << 1)
318# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 319#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
320# define DIP_FLAGS_ACR (1 << 0)
321# define DIP_FLAGS_GC (1 << 1)
322#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
323# define DIP_IF_FLAGS_IF1 (1 << 1)
324# define DIP_IF_FLAGS_IF2 (1 << 2)
325# define DIP_IF_FLAGS_IF3 (1 << 3)
326# define DIP_IF_FLAGS_IF4 (1 << 4)
327# define DIP_IF_FLAGS_IF5 (1 << 5)
328#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 329
330
331/* Page 12h: HDCP and OTP */
332#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 333#define REG_TX4 REG(0x12, 0x9b) /* read/write */
334# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 335#define REG_TX33 REG(0x12, 0xb8) /* read/write */
336# define TX33_HDMI (1 << 1)
337
338
339/* Page 13h: Gamut related metadata packets */
340
341
342
343/* CEC registers: (not paged)
344 */
12473b7d
JFM		 345#define REG_CEC_INTSTATUS 0xee /* read */
346# define CEC_INTSTATUS_CEC (1 << 0)
347# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 348#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
349# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
350# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
351# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
352# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 353#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
354#define REG_CEC_RXSHPDINT 0xfd /* read */
ec5d3e83
RK		 355# define CEC_RXSHPDINT_RXSENS BIT(0)
356# define CEC_RXSHPDINT_HPD BIT(1)
e7792ce2
RC		 357#define REG_CEC_RXSHPDLEV 0xfe /* read */
358# define CEC_RXSHPDLEV_RXSENS (1 << 0)
359# define CEC_RXSHPDLEV_HPD (1 << 1)
360
361#define REG_CEC_ENAMODS 0xff /* read/write */
362# define CEC_ENAMODS_DIS_FRO (1 << 6)
363# define CEC_ENAMODS_DIS_CCLK (1 << 5)
364# define CEC_ENAMODS_EN_RXSENS (1 << 2)
365# define CEC_ENAMODS_EN_HDMI (1 << 1)
366# define CEC_ENAMODS_EN_CEC (1 << 0)
367
368
369/* Device versions: */
370#define TDA9989N2 0x0101
371#define TDA19989 0x0201
372#define TDA19989N2 0x0202
373#define TDA19988 0x0301
374
375static void
e66e03ab 376cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
e7792ce2 377{
e66e03ab 378 u8 buf[] = {addr, val};
14e5b588
RK		 379 struct i2c_msg msg = {
380 .addr = priv->cec_addr,
381 .len = 2,
382 .buf = buf,
383 };
e7792ce2
RC		 384 int ret;
385
14e5b588 386 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
e7792ce2 387 if (ret < 0)
14e5b588
RK		 388 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
389 ret, addr);
e7792ce2
RC		 390}
391
e66e03ab
RK		 392static u8
393cec_read(struct tda998x_priv *priv, u8 addr)
e7792ce2 394{
e66e03ab 395 u8 val;
14e5b588
RK		 396 struct i2c_msg msg[2] = {
397 {
398 .addr = priv->cec_addr,
399 .len = 1,
400 .buf = &addr,
401 }, {
402 .addr = priv->cec_addr,
403 .flags = I2C_M_RD,
404 .len = 1,
405 .buf = &val,
406 },
407 };
e7792ce2
RC		 408 int ret;
409
14e5b588
RK		 410 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
411 if (ret < 0) {
412 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
413 ret, addr);
414 val = 0;
415 }
e7792ce2
RC		 416
417 return val;
e7792ce2
RC		 418}
419
7d2eadc9 420static int
e66e03ab 421set_page(struct tda998x_priv *priv, u16 reg)
e7792ce2 422{
e7792ce2 423 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 424 struct i2c_client *client = priv->hdmi;
e66e03ab 425 u8 buf[] = {
e7792ce2
RC		 426 REG_CURPAGE, REG2PAGE(reg)
427 };
428 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 429 if (ret < 0) {
288ffc73 430 dev_err(&client->dev, "%s %04x err %d\n", __func__,
704d63f5 431 reg, ret);
7d2eadc9
JFM		 432 return ret;
433 }
e7792ce2
RC		 434
435 priv->current_page = REG2PAGE(reg);
436 }
7d2eadc9 437 return 0;
e7792ce2
RC		 438}
439
440static int
e66e03ab 441reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
e7792ce2 442{
2f7f730a 443 struct i2c_client *client = priv->hdmi;
e66e03ab 444 u8 addr = REG2ADDR(reg);
e7792ce2
RC		 445 int ret;
446
ed9a8426 447 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 448 ret = set_page(priv, reg);
449 if (ret < 0)
ed9a8426 450 goto out;
e7792ce2
RC		 451
452 ret = i2c_master_send(client, &addr, sizeof(addr));
453 if (ret < 0)
454 goto fail;
455
456 ret = i2c_master_recv(client, buf, cnt);
457 if (ret < 0)
458 goto fail;
459
ed9a8426 460 goto out;
e7792ce2
RC		 461
462fail:
463 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
ed9a8426
JFM		 464out:
465 mutex_unlock(&priv->mutex);
e7792ce2
RC		 466 return ret;
467}
468
c4c11dd1 469static void
e66e03ab 470reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
c4c11dd1 471{
2f7f730a 472 struct i2c_client *client = priv->hdmi;
e66e03ab 473 u8 buf[cnt+1];
c4c11dd1
RK		 474 int ret;
475
476 buf[0] = REG2ADDR(reg);
477 memcpy(&buf[1], p, cnt);
478
ed9a8426 479 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 480 ret = set_page(priv, reg);
481 if (ret < 0)
ed9a8426 482 goto out;
c4c11dd1
RK		 483
484 ret = i2c_master_send(client, buf, cnt + 1);
485 if (ret < 0)
486 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 487out:
488 mutex_unlock(&priv->mutex);
c4c11dd1
RK		 489}
490
7d2eadc9 491static int
e66e03ab 492reg_read(struct tda998x_priv *priv, u16 reg)
e7792ce2 493{
e66e03ab 494 u8 val = 0;
7d2eadc9
JFM		 495 int ret;
496
497 ret = reg_read_range(priv, reg, &val, sizeof(val));
498 if (ret < 0)
499 return ret;
e7792ce2
RC		 500 return val;
501}
502
503static void
e66e03ab 504reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 505{
2f7f730a 506 struct i2c_client *client = priv->hdmi;
e66e03ab 507 u8 buf[] = {REG2ADDR(reg), val};
e7792ce2
RC		 508 int ret;
509
ed9a8426 510 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 511 ret = set_page(priv, reg);
512 if (ret < 0)
ed9a8426 513 goto out;
e7792ce2 514
704d63f5 515 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 516 if (ret < 0)
517 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 518out:
519 mutex_unlock(&priv->mutex);
e7792ce2
RC		 520}
521
522static void
e66e03ab 523reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
e7792ce2 524{
2f7f730a 525 struct i2c_client *client = priv->hdmi;
e66e03ab 526 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
e7792ce2
RC		 527 int ret;
528
ed9a8426 529 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 530 ret = set_page(priv, reg);
531 if (ret < 0)
ed9a8426 532 goto out;
e7792ce2 533
704d63f5 534 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 535 if (ret < 0)
536 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 537out:
538 mutex_unlock(&priv->mutex);
e7792ce2
RC		 539}
540
541static void
e66e03ab 542reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 543{
7d2eadc9
JFM		 544 int old_val;
545
546 old_val = reg_read(priv, reg);
547 if (old_val >= 0)
548 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 549}
550
551static void
e66e03ab 552reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 553{
7d2eadc9
JFM		 554 int old_val;
555
556 old_val = reg_read(priv, reg);
557 if (old_val >= 0)
558 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 559}
560
561static void
2f7f730a 562tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 563{
564 /* reset audio and i2c master: */
81b53a16 565 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 566 msleep(50);
81b53a16 567 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 568 msleep(50);
569
570 /* reset transmitter: */
2f7f730a
JFM		 571 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
572 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 573
574 /* PLL registers common configuration */
2f7f730a
JFM		 575 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
576 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
577 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
578 reg_write(priv, REG_SERIALIZER, 0x00);
579 reg_write(priv, REG_BUFFER_OUT, 0x00);
580 reg_write(priv, REG_PLL_SCG1, 0x00);
581 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
582 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
583 reg_write(priv, REG_PLL_SCGN1, 0xfa);
584 reg_write(priv, REG_PLL_SCGN2, 0x00);
585 reg_write(priv, REG_PLL_SCGR1, 0x5b);
586 reg_write(priv, REG_PLL_SCGR2, 0x00);
587 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 588
589 /* Write the default value MUX register */
2f7f730a 590 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 591}
592
0fc6f44d
RK		 593/*
594 * The TDA998x has a problem when trying to read the EDID close to a
595 * HPD assertion: it needs a delay of 100ms to avoid timing out while
596 * trying to read EDID data.
597 *
95a9b686 598 * However, tda998x_connector_get_modes() may be called at any moment
9525c4dd 599 * after tda998x_connector_detect() indicates that we are connected, so
95a9b686 600 * we need to delay probing modes in tda998x_connector_get_modes() after
0fc6f44d
RK		 601 * we have seen a HPD inactive->active transition. This code implements
602 * that delay.
603 */
e99e88a9 604static void tda998x_edid_delay_done(struct timer_list *t)
0fc6f44d 605{
e99e88a9 606 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
0fc6f44d
RK		 607
608 priv->edid_delay_active = false;
609 wake_up(&priv->edid_delay_waitq);
610 schedule_work(&priv->detect_work);
611}
612
613static void tda998x_edid_delay_start(struct tda998x_priv *priv)
614{
615 priv->edid_delay_active = true;
616 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
617}
618
619static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
620{
621 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
622}
623
624/*
625 * We need to run the KMS hotplug event helper outside of our threaded
626 * interrupt routine as this can call back into our get_modes method,
627 * which will want to make use of interrupts.
628 */
629static void tda998x_detect_work(struct work_struct *work)
6833d26e 630{
6833d26e 631 struct tda998x_priv *priv =
0fc6f44d 632 container_of(work, struct tda998x_priv, detect_work);
78e401f9 633 struct drm_device *dev = priv->encoder.dev;
6833d26e 634
0fc6f44d
RK		 635 if (dev)
636 drm_kms_helper_hotplug_event(dev);
6833d26e
JFM		 637}
638
12473b7d
JFM		 639/*
640 * only 2 interrupts may occur: screen plug/unplug and EDID read
641 */
642static irqreturn_t tda998x_irq_thread(int irq, void *data)
643{
644 struct tda998x_priv *priv = data;
645 u8 sta, cec, lvl, flag0, flag1, flag2;
f84a97d4 646 bool handled = false;
12473b7d 647
12473b7d 648 sta = cec_read(priv, REG_CEC_INTSTATUS);
ae81553c
RK		 649 if (sta & CEC_INTSTATUS_HDMI) {
650 cec = cec_read(priv, REG_CEC_RXSHPDINT);
651 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
652 flag0 = reg_read(priv, REG_INT_FLAGS_0);
653 flag1 = reg_read(priv, REG_INT_FLAGS_1);
654 flag2 = reg_read(priv, REG_INT_FLAGS_2);
655 DRM_DEBUG_DRIVER(
656 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
657 sta, cec, lvl, flag0, flag1, flag2);
658
659 if (cec & CEC_RXSHPDINT_HPD) {
660 if (lvl & CEC_RXSHPDLEV_HPD)
661 tda998x_edid_delay_start(priv);
662 else
663 schedule_work(&priv->detect_work);
664
665 handled = true;
666 }
ec5d3e83 667
ae81553c
RK		 668 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
669 priv->wq_edid_wait = 0;
670 wake_up(&priv->wq_edid);
671 handled = true;
672 }
ec5d3e83
RK		 673 }
674
f84a97d4 675 return IRQ_RETVAL(handled);
12473b7d
JFM		 676}
677
c4c11dd1 678static void
e66e03ab 679tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
96795df1 680 union hdmi_infoframe *frame)
c4c11dd1 681{
96795df1
RK		 682 u8 buf[32];
683 ssize_t len;
684
685 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
686 if (len < 0) {
687 dev_err(&priv->hdmi->dev,
688 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
689 frame->any.type, len);
690 return;
691 }
692
2f7f730a 693 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
96795df1 694 reg_write_range(priv, addr, buf, len);
2f7f730a 695 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 696}
697
95db3b25
JS		 698static int tda998x_write_aif(struct tda998x_priv *priv,
699 struct hdmi_audio_infoframe *cea)
c4c11dd1 700{
96795df1
RK		 701 union hdmi_infoframe frame;
702
95db3b25 703 frame.audio = *cea;
4a6ca1a2 704
96795df1 705 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
95db3b25
JS		 706
707 return 0;
c4c11dd1
RK		 708}
709
710static void
2f7f730a 711tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 712{
96795df1 713 union hdmi_infoframe frame;
8c7a075d 714
0c1f528c 715 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
96795df1 716 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
8c7a075d 717
96795df1 718 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
c4c11dd1
RK		 719}
720
ad975f93
RK		 721/* Audio support */
722
2f7f730a 723static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 724{
725 if (on) {
2f7f730a
JFM		 726 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
727 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
728 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 729 } else {
2f7f730a 730 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 731 }
732}
733
95db3b25 734static int
2f7f730a 735tda998x_configure_audio(struct tda998x_priv *priv,
319e658c 736 struct tda998x_audio_params *params)
c4c11dd1 737{
e66e03ab
RK		 738 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
739 u32 n;
c4c11dd1
RK		 740
741 /* Enable audio ports */
95db3b25 742 reg_write(priv, REG_ENA_AP, params->config);
c4c11dd1
RK		 743
744 /* Set audio input source */
95db3b25 745 switch (params->format) {
c4c11dd1 746 case AFMT_SPDIF:
95db3b25 747 reg_write(priv, REG_ENA_ACLK, 0);
10df1a95
JFM		 748 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
749 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
750 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 751 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 752 break;
753
754 case AFMT_I2S:
95db3b25 755 reg_write(priv, REG_ENA_ACLK, 1);
10df1a95
JFM		 756 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
757 clksel_aip = AIP_CLKSEL_AIP_I2S;
758 clksel_fs = AIP_CLKSEL_FS_ACLK;
95db3b25
JS		 759 switch (params->sample_width) {
760 case 16:
761 cts_n = CTS_N_M(3) | CTS_N_K(1);
762 break;
763 case 18:
764 case 20:
765 case 24:
766 cts_n = CTS_N_M(3) | CTS_N_K(2);
767 break;
768 default:
769 case 32:
770 cts_n = CTS_N_M(3) | CTS_N_K(3);
771 break;
772 }
c4c11dd1 773 break;
3b28802e
DH		 774
775 default:
7e567624 776 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
95db3b25 777 return -EINVAL;
c4c11dd1
RK		 778 }
779
2f7f730a 780 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 781 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
782 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 783 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 784
785 /*
786 * Audio input somehow depends on HDMI line rate which is
787 * related to pixclk. Testing showed that modes with pixclk
788 * >100MHz need a larger divider while <40MHz need the default.
789 * There is no detailed info in the datasheet, so we just
790 * assume 100MHz requires larger divider.
791 */
2470fecc 792 adiv = AUDIO_DIV_SERCLK_8;
319e658c 793 if (priv->tmds_clock > 100000)
2470fecc
JFM		 794 adiv++; /* AUDIO_DIV_SERCLK_16 */
795
796 /* S/PDIF asks for a larger divider */
95db3b25 797 if (params->format == AFMT_SPDIF)
2470fecc
JFM		 798 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
799
2f7f730a 800 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 801
802 /*
803 * This is the approximate value of N, which happens to be
804 * the recommended values for non-coherent clocks.
805 */
95db3b25 806 n = 128 * params->sample_rate / 1000;
c4c11dd1
RK		 807
808 /* Write the CTS and N values */
809 buf[0] = 0x44;
810 buf[1] = 0x42;
811 buf[2] = 0x01;
812 buf[3] = n;
813 buf[4] = n >> 8;
814 buf[5] = n >> 16;
2f7f730a 815 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 816
817 /* Set CTS clock reference */
2f7f730a 818 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 819
820 /* Reset CTS generator */
2f7f730a
JFM		 821 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
822 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1 823
95db3b25
JS		 824 /* Write the channel status
825 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
826 * there is a separate register for each I2S wire.
827 */
828 buf[0] = params->status[0];
829 buf[1] = params->status[1];
830 buf[2] = params->status[3];
831 buf[3] = params->status[4];
2f7f730a 832 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 833
2f7f730a 834 tda998x_audio_mute(priv, true);
73d5e253 835 msleep(20);
2f7f730a 836 tda998x_audio_mute(priv, false);
c4c11dd1 837
95db3b25 838 return tda998x_write_aif(priv, &params->cea);
c4c11dd1
RK		 839}
840
ad975f93
RK		 841static int tda998x_audio_hw_params(struct device *dev, void *data,
842 struct hdmi_codec_daifmt *daifmt,
843 struct hdmi_codec_params *params)
844{
845 struct tda998x_priv *priv = dev_get_drvdata(dev);
846 int i, ret;
847 struct tda998x_audio_params audio = {
848 .sample_width = params->sample_width,
849 .sample_rate = params->sample_rate,
850 .cea = params->cea,
851 };
852
853 memcpy(audio.status, params->iec.status,
854 min(sizeof(audio.status), sizeof(params->iec.status)));
855
856 switch (daifmt->fmt) {
857 case HDMI_I2S:
858 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
859 daifmt->bit_clk_master || daifmt->frame_clk_master) {
860 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
861 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
862 daifmt->bit_clk_master,
863 daifmt->frame_clk_master);
864 return -EINVAL;
865 }
866 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
867 if (priv->audio_port[i].format == AFMT_I2S)
868 audio.config = priv->audio_port[i].config;
869 audio.format = AFMT_I2S;
870 break;
871 case HDMI_SPDIF:
872 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
873 if (priv->audio_port[i].format == AFMT_SPDIF)
874 audio.config = priv->audio_port[i].config;
875 audio.format = AFMT_SPDIF;
876 break;
877 default:
878 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
879 return -EINVAL;
880 }
881
882 if (audio.config == 0) {
9b2502b6 883 dev_err(dev, "%s: No audio configuration found\n", __func__);
ad975f93
RK		 884 return -EINVAL;
885 }
886
887 mutex_lock(&priv->audio_mutex);
888 if (priv->supports_infoframes && priv->sink_has_audio)
889 ret = tda998x_configure_audio(priv, &audio);
890 else
891 ret = 0;
892
893 if (ret == 0)
894 priv->audio_params = audio;
895 mutex_unlock(&priv->audio_mutex);
896
897 return ret;
898}
899
900static void tda998x_audio_shutdown(struct device *dev, void *data)
901{
902 struct tda998x_priv *priv = dev_get_drvdata(dev);
903
904 mutex_lock(&priv->audio_mutex);
905
906 reg_write(priv, REG_ENA_AP, 0);
907
908 priv->audio_params.format = AFMT_UNUSED;
909
910 mutex_unlock(&priv->audio_mutex);
911}
912
913int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
914{
915 struct tda998x_priv *priv = dev_get_drvdata(dev);
916
917 mutex_lock(&priv->audio_mutex);
918
919 tda998x_audio_mute(priv, enable);
920
921 mutex_unlock(&priv->audio_mutex);
922 return 0;
923}
924
925static int tda998x_audio_get_eld(struct device *dev, void *data,
926 uint8_t *buf, size_t len)
927{
928 struct tda998x_priv *priv = dev_get_drvdata(dev);
ad975f93 929
02efac0f
RK		 930 mutex_lock(&priv->audio_mutex);
931 memcpy(buf, priv->connector.eld,
932 min(sizeof(priv->connector.eld), len));
933 mutex_unlock(&priv->audio_mutex);
934
935 return 0;
ad975f93
RK		 936}
937
938static const struct hdmi_codec_ops audio_codec_ops = {
939 .hw_params = tda998x_audio_hw_params,
940 .audio_shutdown = tda998x_audio_shutdown,
941 .digital_mute = tda998x_audio_digital_mute,
942 .get_eld = tda998x_audio_get_eld,
943};
944
945static int tda998x_audio_codec_init(struct tda998x_priv *priv,
946 struct device *dev)
947{
948 struct hdmi_codec_pdata codec_data = {
949 .ops = &audio_codec_ops,
950 .max_i2s_channels = 2,
951 };
952 int i;
953
954 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
955 if (priv->audio_port[i].format == AFMT_I2S &&
956 priv->audio_port[i].config != 0)
957 codec_data.i2s = 1;
958 if (priv->audio_port[i].format == AFMT_SPDIF &&
959 priv->audio_port[i].config != 0)
960 codec_data.spdif = 1;
961 }
962
963 priv->audio_pdev = platform_device_register_data(
964 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
965 &codec_data, sizeof(codec_data));
966
967 return PTR_ERR_OR_ZERO(priv->audio_pdev);
968}
969
25576733
RK		 970/* DRM connector functions */
971
25576733
RK		 972static int tda998x_connector_fill_modes(struct drm_connector *connector,
973 uint32_t maxX, uint32_t maxY)
974{
975 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
976 int ret;
977
02efac0f 978 mutex_lock(&priv->audio_mutex);
25576733
RK		 979 ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
980
981 if (connector->edid_blob_ptr) {
982 struct edid *edid = (void *)connector->edid_blob_ptr->data;
983
984 priv->sink_has_audio = drm_detect_monitor_audio(edid);
985 } else {
986 priv->sink_has_audio = false;
987 }
02efac0f 988 mutex_unlock(&priv->audio_mutex);
25576733
RK		 989
990 return ret;
991}
992
993static enum drm_connector_status
994tda998x_connector_detect(struct drm_connector *connector, bool force)
995{
996 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
997 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
998
999 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1000 connector_status_disconnected;
1001}
1002
1003static void tda998x_connector_destroy(struct drm_connector *connector)
1004{
1005 drm_connector_cleanup(connector);
1006}
1007
1008static const struct drm_connector_funcs tda998x_connector_funcs = {
7d902c05 1009 .dpms = drm_helper_connector_dpms,
25576733
RK		 1010 .reset = drm_atomic_helper_connector_reset,
1011 .fill_modes = tda998x_connector_fill_modes,
1012 .detect = tda998x_connector_detect,
1013 .destroy = tda998x_connector_destroy,
1014 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1015 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1016};
1017
1018static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1019{
1020 struct tda998x_priv *priv = data;
1021 u8 offset, segptr;
1022 int ret, i;
1023
1024 offset = (blk & 1) ? 128 : 0;
1025 segptr = blk / 2;
1026
1027 reg_write(priv, REG_DDC_ADDR, 0xa0);
1028 reg_write(priv, REG_DDC_OFFS, offset);
1029 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1030 reg_write(priv, REG_DDC_SEGM, segptr);
1031
1032 /* enable reading EDID: */
1033 priv->wq_edid_wait = 1;
1034 reg_write(priv, REG_EDID_CTRL, 0x1);
1035
1036 /* flag must be cleared by sw: */
1037 reg_write(priv, REG_EDID_CTRL, 0x0);
1038
1039 /* wait for block read to complete: */
1040 if (priv->hdmi->irq) {
1041 i = wait_event_timeout(priv->wq_edid,
1042 !priv->wq_edid_wait,
1043 msecs_to_jiffies(100));
1044 if (i < 0) {
1045 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1046 return i;
1047 }
1048 } else {
1049 for (i = 100; i > 0; i--) {
1050 msleep(1);
1051 ret = reg_read(priv, REG_INT_FLAGS_2);
1052 if (ret < 0)
1053 return ret;
1054 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1055 break;
1056 }
1057 }
1058
1059 if (i == 0) {
1060 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1061 return -ETIMEDOUT;
1062 }
1063
1064 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1065 if (ret != length) {
1066 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1067 blk, ret);
1068 return ret;
1069 }
1070
1071 return 0;
1072}
1073
1074static int tda998x_connector_get_modes(struct drm_connector *connector)
1075{
1076 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1077 struct edid *edid;
1078 int n;
1079
1080 /*
1081 * If we get killed while waiting for the HPD timeout, return
1082 * no modes found: we are not in a restartable path, so we
1083 * can't handle signals gracefully.
1084 */
1085 if (tda998x_edid_delay_wait(priv))
1086 return 0;
1087
1088 if (priv->rev == TDA19988)
1089 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1090
1091 edid = drm_do_get_edid(connector, read_edid_block, priv);
1092
1093 if (priv->rev == TDA19988)
1094 reg_set(priv, REG_TX4, TX4_PD_RAM);
1095
1096 if (!edid) {
1097 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1098 return 0;
1099 }
1100
1101 drm_mode_connector_update_edid_property(connector, edid);
1102 n = drm_add_edid_modes(connector, edid);
1103 drm_edid_to_eld(connector, edid);
1104
1105 kfree(edid);
1106
1107 return n;
1108}
1109
1110static int tda998x_connector_mode_valid(struct drm_connector *connector,
1111 struct drm_display_mode *mode)
1112{
1113 /* TDA19988 dotclock can go up to 165MHz */
1114 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1115
1116 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1117 return MODE_CLOCK_HIGH;
1118 if (mode->htotal >= BIT(13))
1119 return MODE_BAD_HVALUE;
1120 if (mode->vtotal >= BIT(11))
1121 return MODE_BAD_VVALUE;
1122 return MODE_OK;
1123}
1124
1125static struct drm_encoder *
1126tda998x_connector_best_encoder(struct drm_connector *connector)
1127{
1128 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1129
1130 return &priv->encoder;
1131}
1132
1133static
1134const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1135 .get_modes = tda998x_connector_get_modes,
1136 .mode_valid = tda998x_connector_mode_valid,
1137 .best_encoder = tda998x_connector_best_encoder,
1138};
1139
a2f75662
RK		 1140static int tda998x_connector_init(struct tda998x_priv *priv,
1141 struct drm_device *drm)
1142{
1143 struct drm_connector *connector = &priv->connector;
1144 int ret;
1145
1146 connector->interlace_allowed = 1;
1147
1148 if (priv->hdmi->irq)
1149 connector->polled = DRM_CONNECTOR_POLL_HPD;
1150 else
1151 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1152 DRM_CONNECTOR_POLL_DISCONNECT;
1153
1154 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1155 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1156 DRM_MODE_CONNECTOR_HDMIA);
1157 if (ret)
1158 return ret;
1159
1160 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1161
1162 return 0;
1163}
1164
e7792ce2
RC		 1165/* DRM encoder functions */
1166
9525c4dd 1167static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
e7792ce2 1168{
9525c4dd 1169 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
3cb43378 1170 bool on;
9525c4dd 1171
e7792ce2 1172 /* we only care about on or off: */
3cb43378 1173 on = mode == DRM_MODE_DPMS_ON;
e7792ce2 1174
3cb43378 1175 if (on == priv->is_on)
e7792ce2
RC		 1176 return;
1177
3cb43378 1178 if (on) {
c4c11dd1 1179 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 1180 reg_write(priv, REG_ENA_VP_0, 0xff);
1181 reg_write(priv, REG_ENA_VP_1, 0xff);
1182 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 1183 /* set muxing after enabling ports: */
2f7f730a
JFM		 1184 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1185 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1186 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
3cb43378
RK		 1187
1188 priv->is_on = true;
1189 } else {
db6aaf4d 1190 /* disable video ports */
2f7f730a
JFM		 1191 reg_write(priv, REG_ENA_VP_0, 0x00);
1192 reg_write(priv, REG_ENA_VP_1, 0x00);
1193 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2 1194
3cb43378
RK		 1195 priv->is_on = false;
1196 }
e7792ce2
RC		 1197}
1198
e7792ce2 1199static void
9525c4dd 1200tda998x_encoder_mode_set(struct drm_encoder *encoder,
a8f4d4d6
RK		 1201 struct drm_display_mode *mode,
1202 struct drm_display_mode *adjusted_mode)
e7792ce2 1203{
9525c4dd 1204 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
e66e03ab
RK		 1205 u16 ref_pix, ref_line, n_pix, n_line;
1206 u16 hs_pix_s, hs_pix_e;
1207 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1208 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1209 u16 vwin1_line_s, vwin1_line_e;
1210 u16 vwin2_line_s, vwin2_line_e;
1211 u16 de_pix_s, de_pix_e;
1212 u8 reg, div, rep;
e7792ce2 1213
088d61d1
SH		 1214 /*
1215 * Internally TDA998x is using ITU-R BT.656 style sync but
1216 * we get VESA style sync. TDA998x is using a reference pixel
1217 * relative to ITU to sync to the input frame and for output
1218 * sync generation. Currently, we are using reference detection
1219 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1220 * which is position of rising VS with coincident rising HS.
1221 *
1222 * Now there is some issues to take care of:
1223 * - HDMI data islands require sync-before-active
1224 * - TDA998x register values must be > 0 to be enabled
1225 * - REFLINE needs an additional offset of +1
1226 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1227 *
1228 * So we add +1 to all horizontal and vertical register values,
1229 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 1230 */
088d61d1
SH		 1231 n_pix = mode->htotal;
1232 n_line = mode->vtotal;
1233
1234 hs_pix_e = mode->hsync_end - mode->hdisplay;
1235 hs_pix_s = mode->hsync_start - mode->hdisplay;
1236 de_pix_e = mode->htotal;
1237 de_pix_s = mode->htotal - mode->hdisplay;
1238 ref_pix = 3 + hs_pix_s;
1239
179f1aa4
SH		 1240 /*
1241 * Attached LCD controllers may generate broken sync. Allow
1242 * those to adjust the position of the rising VS edge by adding
1243 * HSKEW to ref_pix.
1244 */
1245 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1246 ref_pix += adjusted_mode->hskew;
1247
088d61d1
SH		 1248 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1249 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1250 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1251 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1252 vs1_pix_s = vs1_pix_e = hs_pix_s;
1253 vs1_line_s = mode->vsync_start - mode->vdisplay;
1254 vs1_line_e = vs1_line_s +
1255 mode->vsync_end - mode->vsync_start;
1256 vwin2_line_s = vwin2_line_e = 0;
1257 vs2_pix_s = vs2_pix_e = 0;
1258 vs2_line_s = vs2_line_e = 0;
1259 } else {
1260 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1261 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1262 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1263 vs1_pix_s = vs1_pix_e = hs_pix_s;
1264 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1265 vs1_line_e = vs1_line_s +
1266 (mode->vsync_end - mode->vsync_start)/2;
1267 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1268 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1269 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1270 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1271 vs2_line_e = vs2_line_s +
1272 (mode->vsync_end - mode->vsync_start)/2;
1273 }
e7792ce2
RC		 1274
1275 div = 148500 / mode->clock;
3ae471f7
JFM		 1276 if (div != 0) {
1277 div--;
1278 if (div > 3)
1279 div = 3;
1280 }
e7792ce2 1281
2cae8e02
RK		 1282 mutex_lock(&priv->audio_mutex);
1283
e7792ce2 1284 /* mute the audio FIFO: */
2f7f730a 1285 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 1286
1287 /* set HDMI HDCP mode off: */
81b53a16 1288 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 1289 reg_clear(priv, REG_TX33, TX33_HDMI);
1290 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 1291
e7792ce2 1292 /* no pre-filter or interpolator: */
2f7f730a 1293 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 1294 HVF_CNTRL_0_INTPOL(0));
9476ed2e 1295 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
2f7f730a
JFM		 1296 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1297 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 1298 VIP_CNTRL_4_BLC(0));
e7792ce2 1299
2f7f730a 1300 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 1301 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1302 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 1303 reg_write(priv, REG_SERIALIZER, 0);
1304 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 1305
1306 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1307 rep = 0;
2f7f730a
JFM		 1308 reg_write(priv, REG_RPT_CNTRL, 0);
1309 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 1310 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1311
2f7f730a 1312 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 1313 PLL_SERIAL_2_SRL_PR(rep));
1314
e7792ce2 1315 /* set color matrix bypass flag: */
81b53a16
JFM		 1316 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1317 MAT_CONTRL_MAT_SC(1));
9476ed2e 1318 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
e7792ce2
RC		 1319
1320 /* set BIAS tmds value: */
2f7f730a 1321 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 1322
088d61d1
SH		 1323 /*
1324 * Sync on rising HSYNC/VSYNC
1325 */
81b53a16 1326 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 1327
1328 /*
1329 * TDA19988 requires high-active sync at input stage,
1330 * so invert low-active sync provided by master encoder here
1331 */
1332 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 1333 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 1334 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 1335 reg |= VIP_CNTRL_3_V_TGL;
1336 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 1337
1338 reg_write(priv, REG_VIDFORMAT, 0x00);
1339 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1340 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1341 reg_write16(priv, REG_NPIX_MSB, n_pix);
1342 reg_write16(priv, REG_NLINE_MSB, n_line);
1343 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1344 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1345 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1346 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1347 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1348 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1349 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1350 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1351 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1352 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1353 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1354 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1355 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1356 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1357 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1358 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 1359
1360 if (priv->rev == TDA19988) {
1361 /* let incoming pixels fill the active space (if any) */
2f7f730a 1362 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 1363 }
1364
81b53a16
JFM		 1365 /*
1366 * Always generate sync polarity relative to input sync and
1367 * revert input stage toggled sync at output stage
1368 */
1369 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1370 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1371 reg |= TBG_CNTRL_1_H_TGL;
1372 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1373 reg |= TBG_CNTRL_1_V_TGL;
1374 reg_write(priv, REG_TBG_CNTRL_1, reg);
1375
e7792ce2 1376 /* must be last register set: */
81b53a16 1377 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1 1378
319e658c
RK		 1379 priv->tmds_clock = adjusted_mode->clock;
1380
896a4130
RK		 1381 /* CEA-861B section 6 says that:
1382 * CEA version 1 (CEA-861) has no support for infoframes.
1383 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1384 * and optional basic audio.
1385 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1386 * and optional digital audio, with audio infoframes.
1387 *
1388 * Since we only support generation of version 2 AVI infoframes,
1389 * ignore CEA version 2 and below (iow, behave as if we're a
1390 * CEA-861 source.)
1391 */
1392 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1393
1394 if (priv->supports_infoframes) {
c4c11dd1 1395 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1396 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1397 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1398 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1399 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1400
2f7f730a 1401 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1 1402
8f3f21f6
RK		 1403 if (priv->audio_params.format != AFMT_UNUSED &&
1404 priv->sink_has_audio)
319e658c 1405 tda998x_configure_audio(priv, &priv->audio_params);
c4c11dd1 1406 }
319e658c
RK		 1407
1408 mutex_unlock(&priv->audio_mutex);
e7792ce2
RC		 1409}
1410
a8f4d4d6 1411static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1412{
12473b7d
JFM		 1413 /* disable all IRQs and free the IRQ handler */
1414 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1415 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
0fc6f44d 1416
7e567624
JS		 1417 if (priv->audio_pdev)
1418 platform_device_unregister(priv->audio_pdev);
1419
0fc6f44d 1420 if (priv->hdmi->irq)
12473b7d 1421 free_irq(priv->hdmi->irq, priv);
0fc6f44d
RK		 1422
1423 del_timer_sync(&priv->edid_delay_timer);
1424 cancel_work_sync(&priv->detect_work);
12473b7d 1425
89fc8686 1426 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1427}
1428
e7792ce2
RC		 1429/* I2C driver functions */
1430
7e567624
JS		 1431static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1432 struct device_node *np)
1433{
1434 const u32 *port_data;
1435 u32 size;
1436 int i;
1437
1438 port_data = of_get_property(np, "audio-ports", &size);
1439 if (!port_data)
1440 return 0;
1441
1442 size /= sizeof(u32);
1443 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1444 dev_err(&priv->hdmi->dev,
1445 "Bad number of elements in audio-ports dt-property\n");
1446 return -EINVAL;
1447 }
1448
1449 size /= 2;
1450
1451 for (i = 0; i < size; i++) {
1452 u8 afmt = be32_to_cpup(&port_data[2*i]);
1453 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1454
1455 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1456 dev_err(&priv->hdmi->dev,
1457 "Bad audio format %u\n", afmt);
1458 return -EINVAL;
1459 }
1460
1461 priv->audio_port[i].format = afmt;
1462 priv->audio_port[i].config = ena_ap;
1463 }
1464
1465 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1466 dev_err(&priv->hdmi->dev,
1467 "There can only be on I2S port and one SPDIF port\n");
1468 return -EINVAL;
1469 }
1470 return 0;
1471}
1472
a8f4d4d6 1473static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1474{
0d44ea19
JFM		 1475 struct device_node *np = client->dev.of_node;
1476 u32 video;
fb7544d7 1477 int rev_lo, rev_hi, ret;
e7792ce2 1478
ba300c17
RK		 1479 mutex_init(&priv->audio_mutex); /* Protect access from audio thread */
1480
5e74c22c
RK		 1481 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1482 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1483 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1484
14e5b588
RK		 1485 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1486 priv->cec_addr = 0x34 + (client->addr & 0x03);
2eb4c7b1 1487 priv->current_page = 0xff;
2f7f730a 1488 priv->hdmi = client;
14e5b588 1489 priv->cec = i2c_new_dummy(client->adapter, priv->cec_addr);
a8f4d4d6 1490 if (!priv->cec)
6ae668cc 1491 return -ENODEV;
12473b7d 1492
ed9a8426 1493 mutex_init(&priv->mutex); /* protect the page access */
0fc6f44d 1494 init_waitqueue_head(&priv->edid_delay_waitq);
e99e88a9 1495 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
0fc6f44d 1496 INIT_WORK(&priv->detect_work, tda998x_detect_work);
ed9a8426 1497
e7792ce2 1498 /* wake up the device: */
2f7f730a 1499 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1500 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1501
2f7f730a 1502 tda998x_reset(priv);
e7792ce2
RC		 1503
1504 /* read version: */
fb7544d7
RK		 1505 rev_lo = reg_read(priv, REG_VERSION_LSB);
1506 rev_hi = reg_read(priv, REG_VERSION_MSB);
1507 if (rev_lo < 0 || rev_hi < 0) {
1508 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1509 goto fail;
fb7544d7
RK		 1510 }
1511
1512 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1513
1514 /* mask off feature bits: */
1515 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1516
1517 switch (priv->rev) {
b728fab7
JFM		 1518 case TDA9989N2:
1519 dev_info(&client->dev, "found TDA9989 n2");
1520 break;
1521 case TDA19989:
1522 dev_info(&client->dev, "found TDA19989");
1523 break;
1524 case TDA19989N2:
1525 dev_info(&client->dev, "found TDA19989 n2");
1526 break;
1527 case TDA19988:
1528 dev_info(&client->dev, "found TDA19988");
1529 break;
e7792ce2 1530 default:
b728fab7
JFM		 1531 dev_err(&client->dev, "found unsupported device: %04x\n",
1532 priv->rev);
e7792ce2
RC		 1533 goto fail;
1534 }
1535
1536 /* after reset, enable DDC: */
2f7f730a 1537 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1538
1539 /* set clock on DDC channel: */
2f7f730a 1540 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1541
1542 /* if necessary, disable multi-master: */
1543 if (priv->rev == TDA19989)
2f7f730a 1544 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1545
2f7f730a 1546 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1547 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1548
12473b7d
JFM		 1549 /* initialize the optional IRQ */
1550 if (client->irq) {
ae81553c 1551 unsigned long irq_flags;
12473b7d 1552
6833d26e 1553 /* init read EDID waitqueue and HDP work */
12473b7d
JFM		 1554 init_waitqueue_head(&priv->wq_edid);
1555
1556 /* clear pending interrupts */
1557 reg_read(priv, REG_INT_FLAGS_0);
1558 reg_read(priv, REG_INT_FLAGS_1);
1559 reg_read(priv, REG_INT_FLAGS_2);
1560
ae81553c 1561 irq_flags =
12473b7d 1562 irqd_get_trigger_type(irq_get_irq_data(client->irq));
ae81553c 1563 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
12473b7d 1564 ret = request_threaded_irq(client->irq, NULL,
ae81553c 1565 tda998x_irq_thread, irq_flags,
12473b7d
JFM		 1566 "tda998x", priv);
1567 if (ret) {
1568 dev_err(&client->dev,
1569 "failed to request IRQ#%u: %d\n",
1570 client->irq, ret);
1571 goto fail;
1572 }
1573
1574 /* enable HPD irq */
1575 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1576 }
1577
e4782627
JFM		 1578 /* enable EDID read irq: */
1579 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1580
0d44ea19
JFM		 1581 if (!np)
1582 return 0; /* non-DT */
1583
7e567624 1584 /* get the device tree parameters */
0d44ea19
JFM		 1585 ret = of_property_read_u32(np, "video-ports", &video);
1586 if (ret == 0) {
1587 priv->vip_cntrl_0 = video >> 16;
1588 priv->vip_cntrl_1 = video >> 8;
1589 priv->vip_cntrl_2 = video;
1590 }
1591
7e567624
JS		 1592 ret = tda998x_get_audio_ports(priv, np);
1593 if (ret)
1594 goto fail;
1595
1596 if (priv->audio_port[0].format != AFMT_UNUSED)
1597 tda998x_audio_codec_init(priv, &client->dev);
1598
1599 return 0;
e7792ce2
RC		 1600fail:
1601 /* if encoder_init fails, the encoder slave is never registered,
1602 * so cleanup here:
1603 */
1604 if (priv->cec)
1605 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1606 return -ENXIO;
1607}
1608
c707c361
RK		 1609static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1610{
9525c4dd 1611 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
c707c361
RK		 1612}
1613
1614static void tda998x_encoder_commit(struct drm_encoder *encoder)
1615{
9525c4dd 1616 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
c707c361
RK		 1617}
1618
1619static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
9525c4dd 1620 .dpms = tda998x_encoder_dpms,
c707c361
RK		 1621 .prepare = tda998x_encoder_prepare,
1622 .commit = tda998x_encoder_commit,
9525c4dd 1623 .mode_set = tda998x_encoder_mode_set,
c707c361
RK		 1624};
1625
1626static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1627{
a3584f60 1628 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
c707c361 1629
a3584f60 1630 tda998x_destroy(priv);
c707c361
RK		 1631 drm_encoder_cleanup(encoder);
1632}
1633
1634static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1635 .destroy = tda998x_encoder_destroy,
1636};
1637
94579273
RK		 1638static void tda998x_set_config(struct tda998x_priv *priv,
1639 const struct tda998x_encoder_params *p)
1640{
1641 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1642 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1643 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1644 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1645 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1646 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1647 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1648 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1649 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1650 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1651 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1652 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1653
1654 priv->audio_params = p->audio_params;
1655}
1656
c707c361
RK		 1657static int tda998x_bind(struct device *dev, struct device *master, void *data)
1658{
1659 struct tda998x_encoder_params *params = dev->platform_data;
1660 struct i2c_client *client = to_i2c_client(dev);
1661 struct drm_device *drm = data;
a3584f60 1662 struct tda998x_priv *priv;
e66e03ab 1663 u32 crtcs = 0;
c707c361
RK		 1664 int ret;
1665
1666 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1667 if (!priv)
1668 return -ENOMEM;
1669
1670 dev_set_drvdata(dev, priv);
1671
5dbcf319
RK		 1672 if (dev->of_node)
1673 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1674
1675 /* If no CRTCs were found, fall back to our old behaviour */
1676 if (crtcs == 0) {
1677 dev_warn(dev, "Falling back to first CRTC\n");
1678 crtcs = 1 << 0;
1679 }
1680
a3584f60 1681 priv->encoder.possible_crtcs = crtcs;
c707c361 1682
a3584f60 1683 ret = tda998x_create(client, priv);
c707c361
RK		 1684 if (ret)
1685 return ret;
1686
1687 if (!dev->of_node && params)
94579273 1688 tda998x_set_config(priv, params);
c707c361 1689
a3584f60
RK		 1690 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1691 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
13a3d91f 1692 DRM_MODE_ENCODER_TMDS, NULL);
c707c361
RK		 1693 if (ret)
1694 goto err_encoder;
1695
a2f75662 1696 ret = tda998x_connector_init(priv, drm);
c707c361
RK		 1697 if (ret)
1698 goto err_connector;
1699
c707c361
RK		 1700 return 0;
1701
c707c361 1702err_connector:
a3584f60 1703 drm_encoder_cleanup(&priv->encoder);
c707c361 1704err_encoder:
a3584f60 1705 tda998x_destroy(priv);
c707c361
RK		 1706 return ret;
1707}
1708
1709static void tda998x_unbind(struct device *dev, struct device *master,
1710 void *data)
1711{
a3584f60 1712 struct tda998x_priv *priv = dev_get_drvdata(dev);
c707c361 1713
a3584f60
RK		 1714 drm_connector_cleanup(&priv->connector);
1715 drm_encoder_cleanup(&priv->encoder);
1716 tda998x_destroy(priv);
c707c361
RK		 1717}
1718
1719static const struct component_ops tda998x_ops = {
1720 .bind = tda998x_bind,
1721 .unbind = tda998x_unbind,
1722};
1723
1724static int
1725tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1726{
14e5b588
RK		 1727 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1728 dev_warn(&client->dev, "adapter does not support I2C\n");
1729 return -EIO;
1730 }
c707c361
RK		 1731 return component_add(&client->dev, &tda998x_ops);
1732}
1733
1734static int tda998x_remove(struct i2c_client *client)
1735{
1736 component_del(&client->dev, &tda998x_ops);
1737 return 0;
1738}
1739
0d44ea19
JFM		 1740#ifdef CONFIG_OF
1741static const struct of_device_id tda998x_dt_ids[] = {
1742 { .compatible = "nxp,tda998x", },
1743 { }
1744};
1745MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1746#endif
1747
b7f08c89 1748static const struct i2c_device_id tda998x_ids[] = {
e7792ce2
RC		 1749 { "tda998x", 0 },
1750 { }
1751};
1752MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1753
3d58e318
RK		 1754static struct i2c_driver tda998x_driver = {
1755 .probe = tda998x_probe,
1756 .remove = tda998x_remove,
1757 .driver = {
1758 .name = "tda998x",
1759 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2 1760 },
3d58e318 1761 .id_table = tda998x_ids,
e7792ce2
RC		 1762};
1763
3d58e318 1764module_i2c_driver(tda998x_driver);
e7792ce2
RC		 1765
1766MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1767MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1768MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)