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drm/i2c: tda998x: Remove VLA usage
[linux-2.6-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
CommitLineData
e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
7e567624 23#include <sound/hdmi-codec.h>
e7792ce2
RC		 24
25#include <drm/drmP.h>
9736e988 26#include <drm/drm_atomic_helper.h>
e7792ce2 27#include <drm/drm_crtc_helper.h>
e7792ce2 28#include <drm/drm_edid.h>
5dbcf319 29#include <drm/drm_of.h>
c4c11dd1 30#include <drm/i2c/tda998x.h>
e7792ce2
RC		 31
32#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
33
7e567624
JS		 34struct tda998x_audio_port {
35 u8 format; /* AFMT_xxx */
36 u8 config; /* AP value */
37};
38
e7792ce2
RC		 39struct tda998x_priv {
40 struct i2c_client *cec;
2f7f730a 41 struct i2c_client *hdmi;
ed9a8426 42 struct mutex mutex;
e66e03ab 43 u16 rev;
14e5b588 44 u8 cec_addr;
e66e03ab 45 u8 current_page;
3cb43378 46 bool is_on;
896a4130 47 bool supports_infoframes;
8f3f21f6 48 bool sink_has_audio;
5e74c22c
RK		 49 u8 vip_cntrl_0;
50 u8 vip_cntrl_1;
51 u8 vip_cntrl_2;
319e658c 52 unsigned long tmds_clock;
95db3b25 53 struct tda998x_audio_params audio_params;
12473b7d 54
7e567624
JS		 55 struct platform_device *audio_pdev;
56 struct mutex audio_mutex;
57
12473b7d
JFM		 58 wait_queue_head_t wq_edid;
59 volatile int wq_edid_wait;
0fc6f44d
RK		 60
61 struct work_struct detect_work;
62 struct timer_list edid_delay_timer;
63 wait_queue_head_t edid_delay_waitq;
64 bool edid_delay_active;
78e401f9
RK		 65
66 struct drm_encoder encoder;
eed64b59 67 struct drm_connector connector;
7e567624
JS		 68
69 struct tda998x_audio_port audio_port[2];
e7792ce2
RC		 70};
71
9525c4dd
RK		 72#define conn_to_tda998x_priv(x) \
73 container_of(x, struct tda998x_priv, connector)
74
75#define enc_to_tda998x_priv(x) \
76 container_of(x, struct tda998x_priv, encoder)
77
e7792ce2
RC		 78/* The TDA9988 series of devices use a paged register scheme.. to simplify
79 * things we encode the page # in upper bits of the register #. To read/
80 * write a given register, we need to make sure CURPAGE register is set
81 * appropriately. Which implies reads/writes are not atomic. Fun!
82 */
83
84#define REG(page, addr) (((page) << 8) | (addr))
85#define REG2ADDR(reg) ((reg) & 0xff)
86#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
87
88#define REG_CURPAGE 0xff /* write */
89
90
91/* Page 00h: General Control */
92#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
93#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
94# define MAIN_CNTRL0_SR (1 << 0)
95# define MAIN_CNTRL0_DECS (1 << 1)
96# define MAIN_CNTRL0_DEHS (1 << 2)
97# define MAIN_CNTRL0_CECS (1 << 3)
98# define MAIN_CNTRL0_CEHS (1 << 4)
99# define MAIN_CNTRL0_SCALER (1 << 7)
100#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
101#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
102# define SOFTRESET_AUDIO (1 << 0)
103# define SOFTRESET_I2C_MASTER (1 << 1)
104#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
105#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
106#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
107# define I2C_MASTER_DIS_MM (1 << 0)
108# define I2C_MASTER_DIS_FILT (1 << 1)
109# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1 110#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
9476ed2e
RK		 111# define FEAT_POWERDOWN_PREFILT BIT(0)
112# define FEAT_POWERDOWN_CSC BIT(1)
c4c11dd1 113# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 114#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
115#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
116#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
117# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 118#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 119#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
120#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
121#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
122#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
123#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
124# define VIP_CNTRL_0_MIRR_A (1 << 7)
125# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
126# define VIP_CNTRL_0_MIRR_B (1 << 3)
127# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
128#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
129# define VIP_CNTRL_1_MIRR_C (1 << 7)
130# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
131# define VIP_CNTRL_1_MIRR_D (1 << 3)
132# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
133#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
134# define VIP_CNTRL_2_MIRR_E (1 << 7)
135# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
136# define VIP_CNTRL_2_MIRR_F (1 << 3)
137# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
138#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
139# define VIP_CNTRL_3_X_TGL (1 << 0)
140# define VIP_CNTRL_3_H_TGL (1 << 1)
141# define VIP_CNTRL_3_V_TGL (1 << 2)
142# define VIP_CNTRL_3_EMB (1 << 3)
143# define VIP_CNTRL_3_SYNC_DE (1 << 4)
144# define VIP_CNTRL_3_SYNC_HS (1 << 5)
145# define VIP_CNTRL_3_DE_INT (1 << 6)
146# define VIP_CNTRL_3_EDGE (1 << 7)
147#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
148# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
149# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
150# define VIP_CNTRL_4_CCIR656 (1 << 4)
151# define VIP_CNTRL_4_656_ALT (1 << 5)
152# define VIP_CNTRL_4_TST_656 (1 << 6)
153# define VIP_CNTRL_4_TST_PAT (1 << 7)
154#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
155# define VIP_CNTRL_5_CKCASE (1 << 0)
156# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 157#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 158# define MUX_AP_SELECT_I2S 0x64
159# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 160#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 161#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
162# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
163# define MAT_CONTRL_MAT_BP (1 << 2)
164#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
165#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
166#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
167#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
168#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
169#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
170#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
171#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
172#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
173#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
174#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
175#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
176#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
177#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
178#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
179#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
180#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 181#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
182#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 183#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
184#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 185#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
186#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 187#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
188#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
189#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
190#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
191#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
192#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
193#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
194#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
195#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
196#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 197#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
198#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
199#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
200#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 201#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
202#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
203#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
204#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
205#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 206# define TBG_CNTRL_0_TOP_TGL (1 << 0)
207# define TBG_CNTRL_0_TOP_SEL (1 << 1)
208# define TBG_CNTRL_0_DE_EXT (1 << 2)
209# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 210# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
211# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
212# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
213#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 214# define TBG_CNTRL_1_H_TGL (1 << 0)
215# define TBG_CNTRL_1_V_TGL (1 << 1)
216# define TBG_CNTRL_1_TGL_EN (1 << 2)
217# define TBG_CNTRL_1_X_EXT (1 << 3)
218# define TBG_CNTRL_1_H_EXT (1 << 4)
219# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 220# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
221#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
222#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
223# define HVF_CNTRL_0_SM (1 << 7)
224# define HVF_CNTRL_0_RWB (1 << 6)
225# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
226# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
227#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
228# define HVF_CNTRL_1_FOR (1 << 0)
229# define HVF_CNTRL_1_YUVBLK (1 << 1)
230# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
231# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
232# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
233#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 234#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
235# define I2S_FORMAT(x) (((x) & 3) << 0)
236#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 237# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
238# define AIP_CLKSEL_AIP_I2S (1 << 3)
239# define AIP_CLKSEL_FS_ACLK (0 << 0)
240# define AIP_CLKSEL_FS_MCLK (1 << 0)
241# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 242
243/* Page 02h: PLL settings */
244#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
245# define PLL_SERIAL_1_SRL_FDN (1 << 0)
246# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
247# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
248#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 249# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 250# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
251#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
252# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
253# define PLL_SERIAL_3_SRL_DE (1 << 2)
254# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
255#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
256#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
257#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
258#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
259#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
260#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
261#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
262#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
263#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 264# define AUDIO_DIV_SERCLK_1 0
265# define AUDIO_DIV_SERCLK_2 1
266# define AUDIO_DIV_SERCLK_4 2
267# define AUDIO_DIV_SERCLK_8 3
268# define AUDIO_DIV_SERCLK_16 4
269# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 270#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
271# define SEL_CLK_SEL_CLK1 (1 << 0)
272# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
273# define SEL_CLK_ENA_SC_CLK (1 << 3)
274#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
275
276
277/* Page 09h: EDID Control */
278#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
279/* next 127 successive registers are the EDID block */
280#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
281#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
282#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
283#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
284#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
285
286
287/* Page 10h: information frames and packets */
c4c11dd1
RK		 288#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
289#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
290#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
291#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
292#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 293
294
295/* Page 11h: audio settings and content info packets */
296#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
297# define AIP_CNTRL_0_RST_FIFO (1 << 0)
298# define AIP_CNTRL_0_SWAP (1 << 1)
299# define AIP_CNTRL_0_LAYOUT (1 << 2)
300# define AIP_CNTRL_0_ACR_MAN (1 << 5)
301# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 302#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
303# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
304# define CA_I2S_HBR_CHSTAT (1 << 6)
305#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
306#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
307#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
308#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
309#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
310#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
311#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
312#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
313# define CTS_N_K(x) (((x) & 7) << 0)
314# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 315#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
316# define ENC_CNTRL_RST_ENC (1 << 0)
317# define ENC_CNTRL_RST_SEL (1 << 1)
318# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 319#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
320# define DIP_FLAGS_ACR (1 << 0)
321# define DIP_FLAGS_GC (1 << 1)
322#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
323# define DIP_IF_FLAGS_IF1 (1 << 1)
324# define DIP_IF_FLAGS_IF2 (1 << 2)
325# define DIP_IF_FLAGS_IF3 (1 << 3)
326# define DIP_IF_FLAGS_IF4 (1 << 4)
327# define DIP_IF_FLAGS_IF5 (1 << 5)
328#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 329
330
331/* Page 12h: HDCP and OTP */
332#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 333#define REG_TX4 REG(0x12, 0x9b) /* read/write */
334# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 335#define REG_TX33 REG(0x12, 0xb8) /* read/write */
336# define TX33_HDMI (1 << 1)
337
338
339/* Page 13h: Gamut related metadata packets */
340
341
342
343/* CEC registers: (not paged)
344 */
12473b7d
JFM		 345#define REG_CEC_INTSTATUS 0xee /* read */
346# define CEC_INTSTATUS_CEC (1 << 0)
347# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 348#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
349# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
350# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
351# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
352# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 353#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
354#define REG_CEC_RXSHPDINT 0xfd /* read */
ec5d3e83
RK		 355# define CEC_RXSHPDINT_RXSENS BIT(0)
356# define CEC_RXSHPDINT_HPD BIT(1)
e7792ce2
RC		 357#define REG_CEC_RXSHPDLEV 0xfe /* read */
358# define CEC_RXSHPDLEV_RXSENS (1 << 0)
359# define CEC_RXSHPDLEV_HPD (1 << 1)
360
361#define REG_CEC_ENAMODS 0xff /* read/write */
362# define CEC_ENAMODS_DIS_FRO (1 << 6)
363# define CEC_ENAMODS_DIS_CCLK (1 << 5)
364# define CEC_ENAMODS_EN_RXSENS (1 << 2)
365# define CEC_ENAMODS_EN_HDMI (1 << 1)
366# define CEC_ENAMODS_EN_CEC (1 << 0)
367
368
369/* Device versions: */
370#define TDA9989N2 0x0101
371#define TDA19989 0x0201
372#define TDA19989N2 0x0202
373#define TDA19988 0x0301
374
375static void
e66e03ab 376cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
e7792ce2 377{
e66e03ab 378 u8 buf[] = {addr, val};
14e5b588
RK		 379 struct i2c_msg msg = {
380 .addr = priv->cec_addr,
381 .len = 2,
382 .buf = buf,
383 };
e7792ce2
RC		 384 int ret;
385
14e5b588 386 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
e7792ce2 387 if (ret < 0)
14e5b588
RK		 388 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
389 ret, addr);
e7792ce2
RC		 390}
391
e66e03ab
RK		 392static u8
393cec_read(struct tda998x_priv *priv, u8 addr)
e7792ce2 394{
e66e03ab 395 u8 val;
14e5b588
RK		 396 struct i2c_msg msg[2] = {
397 {
398 .addr = priv->cec_addr,
399 .len = 1,
400 .buf = &addr,
401 }, {
402 .addr = priv->cec_addr,
403 .flags = I2C_M_RD,
404 .len = 1,
405 .buf = &val,
406 },
407 };
e7792ce2
RC		 408 int ret;
409
14e5b588
RK		 410 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
411 if (ret < 0) {
412 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
413 ret, addr);
414 val = 0;
415 }
e7792ce2
RC		 416
417 return val;
e7792ce2
RC		 418}
419
7d2eadc9 420static int
e66e03ab 421set_page(struct tda998x_priv *priv, u16 reg)
e7792ce2 422{
e7792ce2 423 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 424 struct i2c_client *client = priv->hdmi;
e66e03ab 425 u8 buf[] = {
e7792ce2
RC		 426 REG_CURPAGE, REG2PAGE(reg)
427 };
428 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 429 if (ret < 0) {
288ffc73 430 dev_err(&client->dev, "%s %04x err %d\n", __func__,
704d63f5 431 reg, ret);
7d2eadc9
JFM		 432 return ret;
433 }
e7792ce2
RC		 434
435 priv->current_page = REG2PAGE(reg);
436 }
7d2eadc9 437 return 0;
e7792ce2
RC		 438}
439
440static int
e66e03ab 441reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
e7792ce2 442{
2f7f730a 443 struct i2c_client *client = priv->hdmi;
e66e03ab 444 u8 addr = REG2ADDR(reg);
e7792ce2
RC		 445 int ret;
446
ed9a8426 447 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 448 ret = set_page(priv, reg);
449 if (ret < 0)
ed9a8426 450 goto out;
e7792ce2
RC		 451
452 ret = i2c_master_send(client, &addr, sizeof(addr));
453 if (ret < 0)
454 goto fail;
455
456 ret = i2c_master_recv(client, buf, cnt);
457 if (ret < 0)
458 goto fail;
459
ed9a8426 460 goto out;
e7792ce2
RC		 461
462fail:
463 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
ed9a8426
JFM		 464out:
465 mutex_unlock(&priv->mutex);
e7792ce2
RC		 466 return ret;
467}
468
ca510ead
LA		 469#define MAX_WRITE_RANGE_BUF 32
470
c4c11dd1 471static void
e66e03ab 472reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
c4c11dd1 473{
2f7f730a 474 struct i2c_client *client = priv->hdmi;
ca510ead
LA		 475 /* This is the maximum size of the buffer passed in */
476 u8 buf[MAX_WRITE_RANGE_BUF + 1];
c4c11dd1
RK		 477 int ret;
478
ca510ead
LA		 479 if (cnt > MAX_WRITE_RANGE_BUF) {
480 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
481 MAX_WRITE_RANGE_BUF);
482 return;
483 }
484
c4c11dd1
RK		 485 buf[0] = REG2ADDR(reg);
486 memcpy(&buf[1], p, cnt);
487
ed9a8426 488 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 489 ret = set_page(priv, reg);
490 if (ret < 0)
ed9a8426 491 goto out;
c4c11dd1
RK		 492
493 ret = i2c_master_send(client, buf, cnt + 1);
494 if (ret < 0)
495 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 496out:
497 mutex_unlock(&priv->mutex);
c4c11dd1
RK		 498}
499
7d2eadc9 500static int
e66e03ab 501reg_read(struct tda998x_priv *priv, u16 reg)
e7792ce2 502{
e66e03ab 503 u8 val = 0;
7d2eadc9
JFM		 504 int ret;
505
506 ret = reg_read_range(priv, reg, &val, sizeof(val));
507 if (ret < 0)
508 return ret;
e7792ce2
RC		 509 return val;
510}
511
512static void
e66e03ab 513reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 514{
2f7f730a 515 struct i2c_client *client = priv->hdmi;
e66e03ab 516 u8 buf[] = {REG2ADDR(reg), val};
e7792ce2
RC		 517 int ret;
518
ed9a8426 519 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 520 ret = set_page(priv, reg);
521 if (ret < 0)
ed9a8426 522 goto out;
e7792ce2 523
704d63f5 524 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 525 if (ret < 0)
526 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 527out:
528 mutex_unlock(&priv->mutex);
e7792ce2
RC		 529}
530
531static void
e66e03ab 532reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
e7792ce2 533{
2f7f730a 534 struct i2c_client *client = priv->hdmi;
e66e03ab 535 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
e7792ce2
RC		 536 int ret;
537
ed9a8426 538 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 539 ret = set_page(priv, reg);
540 if (ret < 0)
ed9a8426 541 goto out;
e7792ce2 542
704d63f5 543 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 544 if (ret < 0)
545 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 546out:
547 mutex_unlock(&priv->mutex);
e7792ce2
RC		 548}
549
550static void
e66e03ab 551reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 552{
7d2eadc9
JFM		 553 int old_val;
554
555 old_val = reg_read(priv, reg);
556 if (old_val >= 0)
557 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 558}
559
560static void
e66e03ab 561reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 562{
7d2eadc9
JFM		 563 int old_val;
564
565 old_val = reg_read(priv, reg);
566 if (old_val >= 0)
567 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 568}
569
570static void
2f7f730a 571tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 572{
573 /* reset audio and i2c master: */
81b53a16 574 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 575 msleep(50);
81b53a16 576 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 577 msleep(50);
578
579 /* reset transmitter: */
2f7f730a
JFM		 580 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
581 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 582
583 /* PLL registers common configuration */
2f7f730a
JFM		 584 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
585 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
586 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
587 reg_write(priv, REG_SERIALIZER, 0x00);
588 reg_write(priv, REG_BUFFER_OUT, 0x00);
589 reg_write(priv, REG_PLL_SCG1, 0x00);
590 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
591 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
592 reg_write(priv, REG_PLL_SCGN1, 0xfa);
593 reg_write(priv, REG_PLL_SCGN2, 0x00);
594 reg_write(priv, REG_PLL_SCGR1, 0x5b);
595 reg_write(priv, REG_PLL_SCGR2, 0x00);
596 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 597
598 /* Write the default value MUX register */
2f7f730a 599 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 600}
601
0fc6f44d
RK		 602/*
603 * The TDA998x has a problem when trying to read the EDID close to a
604 * HPD assertion: it needs a delay of 100ms to avoid timing out while
605 * trying to read EDID data.
606 *
95a9b686 607 * However, tda998x_connector_get_modes() may be called at any moment
9525c4dd 608 * after tda998x_connector_detect() indicates that we are connected, so
95a9b686 609 * we need to delay probing modes in tda998x_connector_get_modes() after
0fc6f44d
RK		 610 * we have seen a HPD inactive->active transition. This code implements
611 * that delay.
612 */
e99e88a9 613static void tda998x_edid_delay_done(struct timer_list *t)
0fc6f44d 614{
e99e88a9 615 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
0fc6f44d
RK		 616
617 priv->edid_delay_active = false;
618 wake_up(&priv->edid_delay_waitq);
619 schedule_work(&priv->detect_work);
620}
621
622static void tda998x_edid_delay_start(struct tda998x_priv *priv)
623{
624 priv->edid_delay_active = true;
625 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
626}
627
628static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
629{
630 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
631}
632
633/*
634 * We need to run the KMS hotplug event helper outside of our threaded
635 * interrupt routine as this can call back into our get_modes method,
636 * which will want to make use of interrupts.
637 */
638static void tda998x_detect_work(struct work_struct *work)
6833d26e 639{
6833d26e 640 struct tda998x_priv *priv =
0fc6f44d 641 container_of(work, struct tda998x_priv, detect_work);
78e401f9 642 struct drm_device *dev = priv->encoder.dev;
6833d26e 643
0fc6f44d
RK		 644 if (dev)
645 drm_kms_helper_hotplug_event(dev);
6833d26e
JFM		 646}
647
12473b7d
JFM		 648/*
649 * only 2 interrupts may occur: screen plug/unplug and EDID read
650 */
651static irqreturn_t tda998x_irq_thread(int irq, void *data)
652{
653 struct tda998x_priv *priv = data;
654 u8 sta, cec, lvl, flag0, flag1, flag2;
f84a97d4 655 bool handled = false;
12473b7d 656
12473b7d 657 sta = cec_read(priv, REG_CEC_INTSTATUS);
ae81553c
RK		 658 if (sta & CEC_INTSTATUS_HDMI) {
659 cec = cec_read(priv, REG_CEC_RXSHPDINT);
660 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
661 flag0 = reg_read(priv, REG_INT_FLAGS_0);
662 flag1 = reg_read(priv, REG_INT_FLAGS_1);
663 flag2 = reg_read(priv, REG_INT_FLAGS_2);
664 DRM_DEBUG_DRIVER(
665 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
666 sta, cec, lvl, flag0, flag1, flag2);
667
668 if (cec & CEC_RXSHPDINT_HPD) {
669 if (lvl & CEC_RXSHPDLEV_HPD)
670 tda998x_edid_delay_start(priv);
671 else
672 schedule_work(&priv->detect_work);
673
674 handled = true;
675 }
ec5d3e83 676
ae81553c
RK		 677 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
678 priv->wq_edid_wait = 0;
679 wake_up(&priv->wq_edid);
680 handled = true;
681 }
ec5d3e83
RK		 682 }
683
f84a97d4 684 return IRQ_RETVAL(handled);
12473b7d
JFM		 685}
686
c4c11dd1 687static void
e66e03ab 688tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
96795df1 689 union hdmi_infoframe *frame)
c4c11dd1 690{
ca510ead 691 u8 buf[MAX_WRITE_RANGE_BUF];
96795df1
RK		 692 ssize_t len;
693
694 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
695 if (len < 0) {
696 dev_err(&priv->hdmi->dev,
697 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
698 frame->any.type, len);
699 return;
700 }
701
2f7f730a 702 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
96795df1 703 reg_write_range(priv, addr, buf, len);
2f7f730a 704 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 705}
706
95db3b25
JS		 707static int tda998x_write_aif(struct tda998x_priv *priv,
708 struct hdmi_audio_infoframe *cea)
c4c11dd1 709{
96795df1
RK		 710 union hdmi_infoframe frame;
711
95db3b25 712 frame.audio = *cea;
4a6ca1a2 713
96795df1 714 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
95db3b25
JS		 715
716 return 0;
c4c11dd1
RK		 717}
718
719static void
2f7f730a 720tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 721{
96795df1 722 union hdmi_infoframe frame;
8c7a075d 723
0c1f528c 724 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
96795df1 725 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
8c7a075d 726
96795df1 727 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
c4c11dd1
RK		 728}
729
ad975f93
RK		 730/* Audio support */
731
2f7f730a 732static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 733{
734 if (on) {
2f7f730a
JFM		 735 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
736 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
737 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 738 } else {
2f7f730a 739 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 740 }
741}
742
95db3b25 743static int
2f7f730a 744tda998x_configure_audio(struct tda998x_priv *priv,
319e658c 745 struct tda998x_audio_params *params)
c4c11dd1 746{
e66e03ab
RK		 747 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
748 u32 n;
c4c11dd1
RK		 749
750 /* Enable audio ports */
95db3b25 751 reg_write(priv, REG_ENA_AP, params->config);
c4c11dd1
RK		 752
753 /* Set audio input source */
95db3b25 754 switch (params->format) {
c4c11dd1 755 case AFMT_SPDIF:
95db3b25 756 reg_write(priv, REG_ENA_ACLK, 0);
10df1a95
JFM		 757 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
758 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
759 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 760 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 761 break;
762
763 case AFMT_I2S:
95db3b25 764 reg_write(priv, REG_ENA_ACLK, 1);
10df1a95
JFM		 765 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
766 clksel_aip = AIP_CLKSEL_AIP_I2S;
767 clksel_fs = AIP_CLKSEL_FS_ACLK;
95db3b25
JS		 768 switch (params->sample_width) {
769 case 16:
770 cts_n = CTS_N_M(3) | CTS_N_K(1);
771 break;
772 case 18:
773 case 20:
774 case 24:
775 cts_n = CTS_N_M(3) | CTS_N_K(2);
776 break;
777 default:
778 case 32:
779 cts_n = CTS_N_M(3) | CTS_N_K(3);
780 break;
781 }
c4c11dd1 782 break;
3b28802e
DH		 783
784 default:
7e567624 785 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
95db3b25 786 return -EINVAL;
c4c11dd1
RK		 787 }
788
2f7f730a 789 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 790 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
791 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 792 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 793
794 /*
795 * Audio input somehow depends on HDMI line rate which is
796 * related to pixclk. Testing showed that modes with pixclk
797 * >100MHz need a larger divider while <40MHz need the default.
798 * There is no detailed info in the datasheet, so we just
799 * assume 100MHz requires larger divider.
800 */
2470fecc 801 adiv = AUDIO_DIV_SERCLK_8;
319e658c 802 if (priv->tmds_clock > 100000)
2470fecc
JFM		 803 adiv++; /* AUDIO_DIV_SERCLK_16 */
804
805 /* S/PDIF asks for a larger divider */
95db3b25 806 if (params->format == AFMT_SPDIF)
2470fecc
JFM		 807 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
808
2f7f730a 809 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 810
811 /*
812 * This is the approximate value of N, which happens to be
813 * the recommended values for non-coherent clocks.
814 */
95db3b25 815 n = 128 * params->sample_rate / 1000;
c4c11dd1
RK		 816
817 /* Write the CTS and N values */
818 buf[0] = 0x44;
819 buf[1] = 0x42;
820 buf[2] = 0x01;
821 buf[3] = n;
822 buf[4] = n >> 8;
823 buf[5] = n >> 16;
2f7f730a 824 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 825
826 /* Set CTS clock reference */
2f7f730a 827 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 828
829 /* Reset CTS generator */
2f7f730a
JFM		 830 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
831 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1 832
95db3b25
JS		 833 /* Write the channel status
834 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
835 * there is a separate register for each I2S wire.
836 */
837 buf[0] = params->status[0];
838 buf[1] = params->status[1];
839 buf[2] = params->status[3];
840 buf[3] = params->status[4];
2f7f730a 841 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 842
2f7f730a 843 tda998x_audio_mute(priv, true);
73d5e253 844 msleep(20);
2f7f730a 845 tda998x_audio_mute(priv, false);
c4c11dd1 846
95db3b25 847 return tda998x_write_aif(priv, &params->cea);
c4c11dd1
RK		 848}
849
ad975f93
RK		 850static int tda998x_audio_hw_params(struct device *dev, void *data,
851 struct hdmi_codec_daifmt *daifmt,
852 struct hdmi_codec_params *params)
853{
854 struct tda998x_priv *priv = dev_get_drvdata(dev);
855 int i, ret;
856 struct tda998x_audio_params audio = {
857 .sample_width = params->sample_width,
858 .sample_rate = params->sample_rate,
859 .cea = params->cea,
860 };
861
862 memcpy(audio.status, params->iec.status,
863 min(sizeof(audio.status), sizeof(params->iec.status)));
864
865 switch (daifmt->fmt) {
866 case HDMI_I2S:
867 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
868 daifmt->bit_clk_master || daifmt->frame_clk_master) {
869 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
870 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
871 daifmt->bit_clk_master,
872 daifmt->frame_clk_master);
873 return -EINVAL;
874 }
875 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
876 if (priv->audio_port[i].format == AFMT_I2S)
877 audio.config = priv->audio_port[i].config;
878 audio.format = AFMT_I2S;
879 break;
880 case HDMI_SPDIF:
881 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
882 if (priv->audio_port[i].format == AFMT_SPDIF)
883 audio.config = priv->audio_port[i].config;
884 audio.format = AFMT_SPDIF;
885 break;
886 default:
887 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
888 return -EINVAL;
889 }
890
891 if (audio.config == 0) {
9b2502b6 892 dev_err(dev, "%s: No audio configuration found\n", __func__);
ad975f93
RK		 893 return -EINVAL;
894 }
895
896 mutex_lock(&priv->audio_mutex);
897 if (priv->supports_infoframes && priv->sink_has_audio)
898 ret = tda998x_configure_audio(priv, &audio);
899 else
900 ret = 0;
901
902 if (ret == 0)
903 priv->audio_params = audio;
904 mutex_unlock(&priv->audio_mutex);
905
906 return ret;
907}
908
909static void tda998x_audio_shutdown(struct device *dev, void *data)
910{
911 struct tda998x_priv *priv = dev_get_drvdata(dev);
912
913 mutex_lock(&priv->audio_mutex);
914
915 reg_write(priv, REG_ENA_AP, 0);
916
917 priv->audio_params.format = AFMT_UNUSED;
918
919 mutex_unlock(&priv->audio_mutex);
920}
921
922int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
923{
924 struct tda998x_priv *priv = dev_get_drvdata(dev);
925
926 mutex_lock(&priv->audio_mutex);
927
928 tda998x_audio_mute(priv, enable);
929
930 mutex_unlock(&priv->audio_mutex);
931 return 0;
932}
933
934static int tda998x_audio_get_eld(struct device *dev, void *data,
935 uint8_t *buf, size_t len)
936{
937 struct tda998x_priv *priv = dev_get_drvdata(dev);
ad975f93 938
02efac0f
RK		 939 mutex_lock(&priv->audio_mutex);
940 memcpy(buf, priv->connector.eld,
941 min(sizeof(priv->connector.eld), len));
942 mutex_unlock(&priv->audio_mutex);
943
944 return 0;
ad975f93
RK		 945}
946
947static const struct hdmi_codec_ops audio_codec_ops = {
948 .hw_params = tda998x_audio_hw_params,
949 .audio_shutdown = tda998x_audio_shutdown,
950 .digital_mute = tda998x_audio_digital_mute,
951 .get_eld = tda998x_audio_get_eld,
952};
953
954static int tda998x_audio_codec_init(struct tda998x_priv *priv,
955 struct device *dev)
956{
957 struct hdmi_codec_pdata codec_data = {
958 .ops = &audio_codec_ops,
959 .max_i2s_channels = 2,
960 };
961 int i;
962
963 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
964 if (priv->audio_port[i].format == AFMT_I2S &&
965 priv->audio_port[i].config != 0)
966 codec_data.i2s = 1;
967 if (priv->audio_port[i].format == AFMT_SPDIF &&
968 priv->audio_port[i].config != 0)
969 codec_data.spdif = 1;
970 }
971
972 priv->audio_pdev = platform_device_register_data(
973 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
974 &codec_data, sizeof(codec_data));
975
976 return PTR_ERR_OR_ZERO(priv->audio_pdev);
977}
978
25576733
RK		 979/* DRM connector functions */
980
25576733
RK		 981static int tda998x_connector_fill_modes(struct drm_connector *connector,
982 uint32_t maxX, uint32_t maxY)
983{
984 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
985 int ret;
986
02efac0f 987 mutex_lock(&priv->audio_mutex);
25576733
RK		 988 ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
989
990 if (connector->edid_blob_ptr) {
991 struct edid *edid = (void *)connector->edid_blob_ptr->data;
992
993 priv->sink_has_audio = drm_detect_monitor_audio(edid);
994 } else {
995 priv->sink_has_audio = false;
996 }
02efac0f 997 mutex_unlock(&priv->audio_mutex);
25576733
RK		 998
999 return ret;
1000}
1001
1002static enum drm_connector_status
1003tda998x_connector_detect(struct drm_connector *connector, bool force)
1004{
1005 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1006 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1007
1008 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1009 connector_status_disconnected;
1010}
1011
1012static void tda998x_connector_destroy(struct drm_connector *connector)
1013{
1014 drm_connector_cleanup(connector);
1015}
1016
1017static const struct drm_connector_funcs tda998x_connector_funcs = {
7d902c05 1018 .dpms = drm_helper_connector_dpms,
25576733
RK		 1019 .reset = drm_atomic_helper_connector_reset,
1020 .fill_modes = tda998x_connector_fill_modes,
1021 .detect = tda998x_connector_detect,
1022 .destroy = tda998x_connector_destroy,
1023 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1024 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1025};
1026
1027static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1028{
1029 struct tda998x_priv *priv = data;
1030 u8 offset, segptr;
1031 int ret, i;
1032
1033 offset = (blk & 1) ? 128 : 0;
1034 segptr = blk / 2;
1035
1036 reg_write(priv, REG_DDC_ADDR, 0xa0);
1037 reg_write(priv, REG_DDC_OFFS, offset);
1038 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1039 reg_write(priv, REG_DDC_SEGM, segptr);
1040
1041 /* enable reading EDID: */
1042 priv->wq_edid_wait = 1;
1043 reg_write(priv, REG_EDID_CTRL, 0x1);
1044
1045 /* flag must be cleared by sw: */
1046 reg_write(priv, REG_EDID_CTRL, 0x0);
1047
1048 /* wait for block read to complete: */
1049 if (priv->hdmi->irq) {
1050 i = wait_event_timeout(priv->wq_edid,
1051 !priv->wq_edid_wait,
1052 msecs_to_jiffies(100));
1053 if (i < 0) {
1054 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1055 return i;
1056 }
1057 } else {
1058 for (i = 100; i > 0; i--) {
1059 msleep(1);
1060 ret = reg_read(priv, REG_INT_FLAGS_2);
1061 if (ret < 0)
1062 return ret;
1063 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1064 break;
1065 }
1066 }
1067
1068 if (i == 0) {
1069 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1070 return -ETIMEDOUT;
1071 }
1072
1073 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1074 if (ret != length) {
1075 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1076 blk, ret);
1077 return ret;
1078 }
1079
1080 return 0;
1081}
1082
1083static int tda998x_connector_get_modes(struct drm_connector *connector)
1084{
1085 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1086 struct edid *edid;
1087 int n;
1088
1089 /*
1090 * If we get killed while waiting for the HPD timeout, return
1091 * no modes found: we are not in a restartable path, so we
1092 * can't handle signals gracefully.
1093 */
1094 if (tda998x_edid_delay_wait(priv))
1095 return 0;
1096
1097 if (priv->rev == TDA19988)
1098 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1099
1100 edid = drm_do_get_edid(connector, read_edid_block, priv);
1101
1102 if (priv->rev == TDA19988)
1103 reg_set(priv, REG_TX4, TX4_PD_RAM);
1104
1105 if (!edid) {
1106 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1107 return 0;
1108 }
1109
1110 drm_mode_connector_update_edid_property(connector, edid);
1111 n = drm_add_edid_modes(connector, edid);
25576733
RK		 1112
1113 kfree(edid);
1114
1115 return n;
1116}
1117
f555828e 1118static enum drm_mode_status tda998x_connector_mode_valid(struct drm_connector *connector,
25576733
RK		 1119 struct drm_display_mode *mode)
1120{
1121 /* TDA19988 dotclock can go up to 165MHz */
1122 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1123
1124 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1125 return MODE_CLOCK_HIGH;
1126 if (mode->htotal >= BIT(13))
1127 return MODE_BAD_HVALUE;
1128 if (mode->vtotal >= BIT(11))
1129 return MODE_BAD_VVALUE;
1130 return MODE_OK;
1131}
1132
1133static struct drm_encoder *
1134tda998x_connector_best_encoder(struct drm_connector *connector)
1135{
1136 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1137
1138 return &priv->encoder;
1139}
1140
1141static
1142const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1143 .get_modes = tda998x_connector_get_modes,
1144 .mode_valid = tda998x_connector_mode_valid,
1145 .best_encoder = tda998x_connector_best_encoder,
1146};
1147
a2f75662
RK		 1148static int tda998x_connector_init(struct tda998x_priv *priv,
1149 struct drm_device *drm)
1150{
1151 struct drm_connector *connector = &priv->connector;
1152 int ret;
1153
1154 connector->interlace_allowed = 1;
1155
1156 if (priv->hdmi->irq)
1157 connector->polled = DRM_CONNECTOR_POLL_HPD;
1158 else
1159 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1160 DRM_CONNECTOR_POLL_DISCONNECT;
1161
1162 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1163 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1164 DRM_MODE_CONNECTOR_HDMIA);
1165 if (ret)
1166 return ret;
1167
1168 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1169
1170 return 0;
1171}
1172
e7792ce2
RC		 1173/* DRM encoder functions */
1174
9525c4dd 1175static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
e7792ce2 1176{
9525c4dd 1177 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
3cb43378 1178 bool on;
9525c4dd 1179
e7792ce2 1180 /* we only care about on or off: */
3cb43378 1181 on = mode == DRM_MODE_DPMS_ON;
e7792ce2 1182
3cb43378 1183 if (on == priv->is_on)
e7792ce2
RC		 1184 return;
1185
3cb43378 1186 if (on) {
c4c11dd1 1187 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 1188 reg_write(priv, REG_ENA_VP_0, 0xff);
1189 reg_write(priv, REG_ENA_VP_1, 0xff);
1190 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 1191 /* set muxing after enabling ports: */
2f7f730a
JFM		 1192 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1193 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1194 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
3cb43378
RK		 1195
1196 priv->is_on = true;
1197 } else {
db6aaf4d 1198 /* disable video ports */
2f7f730a
JFM		 1199 reg_write(priv, REG_ENA_VP_0, 0x00);
1200 reg_write(priv, REG_ENA_VP_1, 0x00);
1201 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2 1202
3cb43378
RK		 1203 priv->is_on = false;
1204 }
e7792ce2
RC		 1205}
1206
e7792ce2 1207static void
9525c4dd 1208tda998x_encoder_mode_set(struct drm_encoder *encoder,
a8f4d4d6
RK		 1209 struct drm_display_mode *mode,
1210 struct drm_display_mode *adjusted_mode)
e7792ce2 1211{
9525c4dd 1212 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
e66e03ab
RK		 1213 u16 ref_pix, ref_line, n_pix, n_line;
1214 u16 hs_pix_s, hs_pix_e;
1215 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1216 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1217 u16 vwin1_line_s, vwin1_line_e;
1218 u16 vwin2_line_s, vwin2_line_e;
1219 u16 de_pix_s, de_pix_e;
1220 u8 reg, div, rep;
e7792ce2 1221
088d61d1
SH		 1222 /*
1223 * Internally TDA998x is using ITU-R BT.656 style sync but
1224 * we get VESA style sync. TDA998x is using a reference pixel
1225 * relative to ITU to sync to the input frame and for output
1226 * sync generation. Currently, we are using reference detection
1227 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1228 * which is position of rising VS with coincident rising HS.
1229 *
1230 * Now there is some issues to take care of:
1231 * - HDMI data islands require sync-before-active
1232 * - TDA998x register values must be > 0 to be enabled
1233 * - REFLINE needs an additional offset of +1
1234 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1235 *
1236 * So we add +1 to all horizontal and vertical register values,
1237 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 1238 */
088d61d1
SH		 1239 n_pix = mode->htotal;
1240 n_line = mode->vtotal;
1241
1242 hs_pix_e = mode->hsync_end - mode->hdisplay;
1243 hs_pix_s = mode->hsync_start - mode->hdisplay;
1244 de_pix_e = mode->htotal;
1245 de_pix_s = mode->htotal - mode->hdisplay;
1246 ref_pix = 3 + hs_pix_s;
1247
179f1aa4
SH		 1248 /*
1249 * Attached LCD controllers may generate broken sync. Allow
1250 * those to adjust the position of the rising VS edge by adding
1251 * HSKEW to ref_pix.
1252 */
1253 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1254 ref_pix += adjusted_mode->hskew;
1255
088d61d1
SH		 1256 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1257 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1258 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1259 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1260 vs1_pix_s = vs1_pix_e = hs_pix_s;
1261 vs1_line_s = mode->vsync_start - mode->vdisplay;
1262 vs1_line_e = vs1_line_s +
1263 mode->vsync_end - mode->vsync_start;
1264 vwin2_line_s = vwin2_line_e = 0;
1265 vs2_pix_s = vs2_pix_e = 0;
1266 vs2_line_s = vs2_line_e = 0;
1267 } else {
1268 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1269 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1270 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1271 vs1_pix_s = vs1_pix_e = hs_pix_s;
1272 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1273 vs1_line_e = vs1_line_s +
1274 (mode->vsync_end - mode->vsync_start)/2;
1275 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1276 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1277 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1278 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1279 vs2_line_e = vs2_line_s +
1280 (mode->vsync_end - mode->vsync_start)/2;
1281 }
e7792ce2
RC		 1282
1283 div = 148500 / mode->clock;
3ae471f7
JFM		 1284 if (div != 0) {
1285 div--;
1286 if (div > 3)
1287 div = 3;
1288 }
e7792ce2 1289
2cae8e02
RK		 1290 mutex_lock(&priv->audio_mutex);
1291
e7792ce2 1292 /* mute the audio FIFO: */
2f7f730a 1293 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 1294
1295 /* set HDMI HDCP mode off: */
81b53a16 1296 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 1297 reg_clear(priv, REG_TX33, TX33_HDMI);
1298 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 1299
e7792ce2 1300 /* no pre-filter or interpolator: */
2f7f730a 1301 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 1302 HVF_CNTRL_0_INTPOL(0));
9476ed2e 1303 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
2f7f730a
JFM		 1304 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1305 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 1306 VIP_CNTRL_4_BLC(0));
e7792ce2 1307
2f7f730a 1308 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 1309 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1310 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 1311 reg_write(priv, REG_SERIALIZER, 0);
1312 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 1313
1314 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1315 rep = 0;
2f7f730a
JFM		 1316 reg_write(priv, REG_RPT_CNTRL, 0);
1317 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 1318 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1319
2f7f730a 1320 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 1321 PLL_SERIAL_2_SRL_PR(rep));
1322
e7792ce2 1323 /* set color matrix bypass flag: */
81b53a16
JFM		 1324 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1325 MAT_CONTRL_MAT_SC(1));
9476ed2e 1326 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
e7792ce2
RC		 1327
1328 /* set BIAS tmds value: */
2f7f730a 1329 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 1330
088d61d1
SH		 1331 /*
1332 * Sync on rising HSYNC/VSYNC
1333 */
81b53a16 1334 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 1335
1336 /*
1337 * TDA19988 requires high-active sync at input stage,
1338 * so invert low-active sync provided by master encoder here
1339 */
1340 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 1341 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 1342 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 1343 reg |= VIP_CNTRL_3_V_TGL;
1344 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 1345
1346 reg_write(priv, REG_VIDFORMAT, 0x00);
1347 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1348 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1349 reg_write16(priv, REG_NPIX_MSB, n_pix);
1350 reg_write16(priv, REG_NLINE_MSB, n_line);
1351 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1352 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1353 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1354 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1355 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1356 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1357 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1358 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1359 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1360 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1361 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1362 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1363 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1364 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1365 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1366 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 1367
1368 if (priv->rev == TDA19988) {
1369 /* let incoming pixels fill the active space (if any) */
2f7f730a 1370 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 1371 }
1372
81b53a16
JFM		 1373 /*
1374 * Always generate sync polarity relative to input sync and
1375 * revert input stage toggled sync at output stage
1376 */
1377 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1378 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1379 reg |= TBG_CNTRL_1_H_TGL;
1380 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1381 reg |= TBG_CNTRL_1_V_TGL;
1382 reg_write(priv, REG_TBG_CNTRL_1, reg);
1383
e7792ce2 1384 /* must be last register set: */
81b53a16 1385 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1 1386
319e658c
RK		 1387 priv->tmds_clock = adjusted_mode->clock;
1388
896a4130
RK		 1389 /* CEA-861B section 6 says that:
1390 * CEA version 1 (CEA-861) has no support for infoframes.
1391 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1392 * and optional basic audio.
1393 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1394 * and optional digital audio, with audio infoframes.
1395 *
1396 * Since we only support generation of version 2 AVI infoframes,
1397 * ignore CEA version 2 and below (iow, behave as if we're a
1398 * CEA-861 source.)
1399 */
1400 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1401
1402 if (priv->supports_infoframes) {
c4c11dd1 1403 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1404 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1405 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1406 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1407 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1408
2f7f730a 1409 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1 1410
8f3f21f6
RK		 1411 if (priv->audio_params.format != AFMT_UNUSED &&
1412 priv->sink_has_audio)
319e658c 1413 tda998x_configure_audio(priv, &priv->audio_params);
c4c11dd1 1414 }
319e658c
RK		 1415
1416 mutex_unlock(&priv->audio_mutex);
e7792ce2
RC		 1417}
1418
a8f4d4d6 1419static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1420{
12473b7d
JFM		 1421 /* disable all IRQs and free the IRQ handler */
1422 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1423 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
0fc6f44d 1424
7e567624
JS		 1425 if (priv->audio_pdev)
1426 platform_device_unregister(priv->audio_pdev);
1427
0fc6f44d 1428 if (priv->hdmi->irq)
12473b7d 1429 free_irq(priv->hdmi->irq, priv);
0fc6f44d
RK		 1430
1431 del_timer_sync(&priv->edid_delay_timer);
1432 cancel_work_sync(&priv->detect_work);
12473b7d 1433
89fc8686 1434 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1435}
1436
e7792ce2
RC		 1437/* I2C driver functions */
1438
7e567624
JS		 1439static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1440 struct device_node *np)
1441{
1442 const u32 *port_data;
1443 u32 size;
1444 int i;
1445
1446 port_data = of_get_property(np, "audio-ports", &size);
1447 if (!port_data)
1448 return 0;
1449
1450 size /= sizeof(u32);
1451 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1452 dev_err(&priv->hdmi->dev,
1453 "Bad number of elements in audio-ports dt-property\n");
1454 return -EINVAL;
1455 }
1456
1457 size /= 2;
1458
1459 for (i = 0; i < size; i++) {
1460 u8 afmt = be32_to_cpup(&port_data[2*i]);
1461 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1462
1463 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1464 dev_err(&priv->hdmi->dev,
1465 "Bad audio format %u\n", afmt);
1466 return -EINVAL;
1467 }
1468
1469 priv->audio_port[i].format = afmt;
1470 priv->audio_port[i].config = ena_ap;
1471 }
1472
1473 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1474 dev_err(&priv->hdmi->dev,
1475 "There can only be on I2S port and one SPDIF port\n");
1476 return -EINVAL;
1477 }
1478 return 0;
1479}
1480
a8f4d4d6 1481static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1482{
0d44ea19
JFM		 1483 struct device_node *np = client->dev.of_node;
1484 u32 video;
fb7544d7 1485 int rev_lo, rev_hi, ret;
e7792ce2 1486
ba300c17
RK		 1487 mutex_init(&priv->audio_mutex); /* Protect access from audio thread */
1488
5e74c22c
RK		 1489 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1490 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1491 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1492
14e5b588
RK		 1493 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1494 priv->cec_addr = 0x34 + (client->addr & 0x03);
2eb4c7b1 1495 priv->current_page = 0xff;
2f7f730a 1496 priv->hdmi = client;
14e5b588 1497 priv->cec = i2c_new_dummy(client->adapter, priv->cec_addr);
a8f4d4d6 1498 if (!priv->cec)
6ae668cc 1499 return -ENODEV;
12473b7d 1500
ed9a8426 1501 mutex_init(&priv->mutex); /* protect the page access */
0fc6f44d 1502 init_waitqueue_head(&priv->edid_delay_waitq);
e99e88a9 1503 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
0fc6f44d 1504 INIT_WORK(&priv->detect_work, tda998x_detect_work);
ed9a8426 1505
e7792ce2 1506 /* wake up the device: */
2f7f730a 1507 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1508 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1509
2f7f730a 1510 tda998x_reset(priv);
e7792ce2
RC		 1511
1512 /* read version: */
fb7544d7
RK		 1513 rev_lo = reg_read(priv, REG_VERSION_LSB);
1514 rev_hi = reg_read(priv, REG_VERSION_MSB);
1515 if (rev_lo < 0 || rev_hi < 0) {
1516 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1517 goto fail;
fb7544d7
RK		 1518 }
1519
1520 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1521
1522 /* mask off feature bits: */
1523 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1524
1525 switch (priv->rev) {
b728fab7
JFM		 1526 case TDA9989N2:
1527 dev_info(&client->dev, "found TDA9989 n2");
1528 break;
1529 case TDA19989:
1530 dev_info(&client->dev, "found TDA19989");
1531 break;
1532 case TDA19989N2:
1533 dev_info(&client->dev, "found TDA19989 n2");
1534 break;
1535 case TDA19988:
1536 dev_info(&client->dev, "found TDA19988");
1537 break;
e7792ce2 1538 default:
b728fab7
JFM		 1539 dev_err(&client->dev, "found unsupported device: %04x\n",
1540 priv->rev);
e7792ce2
RC		 1541 goto fail;
1542 }
1543
1544 /* after reset, enable DDC: */
2f7f730a 1545 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1546
1547 /* set clock on DDC channel: */
2f7f730a 1548 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1549
1550 /* if necessary, disable multi-master: */
1551 if (priv->rev == TDA19989)
2f7f730a 1552 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1553
2f7f730a 1554 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1555 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1556
12473b7d
JFM		 1557 /* initialize the optional IRQ */
1558 if (client->irq) {
ae81553c 1559 unsigned long irq_flags;
12473b7d 1560
6833d26e 1561 /* init read EDID waitqueue and HDP work */
12473b7d
JFM		 1562 init_waitqueue_head(&priv->wq_edid);
1563
1564 /* clear pending interrupts */
1565 reg_read(priv, REG_INT_FLAGS_0);
1566 reg_read(priv, REG_INT_FLAGS_1);
1567 reg_read(priv, REG_INT_FLAGS_2);
1568
ae81553c 1569 irq_flags =
12473b7d 1570 irqd_get_trigger_type(irq_get_irq_data(client->irq));
ae81553c 1571 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
12473b7d 1572 ret = request_threaded_irq(client->irq, NULL,
ae81553c 1573 tda998x_irq_thread, irq_flags,
12473b7d
JFM		 1574 "tda998x", priv);
1575 if (ret) {
1576 dev_err(&client->dev,
1577 "failed to request IRQ#%u: %d\n",
1578 client->irq, ret);
1579 goto fail;
1580 }
1581
1582 /* enable HPD irq */
1583 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1584 }
1585
e4782627
JFM		 1586 /* enable EDID read irq: */
1587 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1588
0d44ea19
JFM		 1589 if (!np)
1590 return 0; /* non-DT */
1591
7e567624 1592 /* get the device tree parameters */
0d44ea19
JFM		 1593 ret = of_property_read_u32(np, "video-ports", &video);
1594 if (ret == 0) {
1595 priv->vip_cntrl_0 = video >> 16;
1596 priv->vip_cntrl_1 = video >> 8;
1597 priv->vip_cntrl_2 = video;
1598 }
1599
7e567624
JS		 1600 ret = tda998x_get_audio_ports(priv, np);
1601 if (ret)
1602 goto fail;
1603
1604 if (priv->audio_port[0].format != AFMT_UNUSED)
1605 tda998x_audio_codec_init(priv, &client->dev);
1606
1607 return 0;
e7792ce2
RC		 1608fail:
1609 /* if encoder_init fails, the encoder slave is never registered,
1610 * so cleanup here:
1611 */
e1ca774b 1612 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1613 return -ENXIO;
1614}
1615
c707c361
RK		 1616static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1617{
9525c4dd 1618 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
c707c361
RK		 1619}
1620
1621static void tda998x_encoder_commit(struct drm_encoder *encoder)
1622{
9525c4dd 1623 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
c707c361
RK		 1624}
1625
1626static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
9525c4dd 1627 .dpms = tda998x_encoder_dpms,
c707c361
RK		 1628 .prepare = tda998x_encoder_prepare,
1629 .commit = tda998x_encoder_commit,
9525c4dd 1630 .mode_set = tda998x_encoder_mode_set,
c707c361
RK		 1631};
1632
1633static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1634{
a3584f60 1635 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
c707c361 1636
a3584f60 1637 tda998x_destroy(priv);
c707c361
RK		 1638 drm_encoder_cleanup(encoder);
1639}
1640
1641static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1642 .destroy = tda998x_encoder_destroy,
1643};
1644
94579273
RK		 1645static void tda998x_set_config(struct tda998x_priv *priv,
1646 const struct tda998x_encoder_params *p)
1647{
1648 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1649 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1650 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1651 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1652 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1653 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1654 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1655 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1656 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1657 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1658 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1659 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1660
1661 priv->audio_params = p->audio_params;
1662}
1663
c707c361
RK		 1664static int tda998x_bind(struct device *dev, struct device *master, void *data)
1665{
1666 struct tda998x_encoder_params *params = dev->platform_data;
1667 struct i2c_client *client = to_i2c_client(dev);
1668 struct drm_device *drm = data;
a3584f60 1669 struct tda998x_priv *priv;
e66e03ab 1670 u32 crtcs = 0;
c707c361
RK		 1671 int ret;
1672
1673 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1674 if (!priv)
1675 return -ENOMEM;
1676
1677 dev_set_drvdata(dev, priv);
1678
5dbcf319
RK		 1679 if (dev->of_node)
1680 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1681
1682 /* If no CRTCs were found, fall back to our old behaviour */
1683 if (crtcs == 0) {
1684 dev_warn(dev, "Falling back to first CRTC\n");
1685 crtcs = 1 << 0;
1686 }
1687
a3584f60 1688 priv->encoder.possible_crtcs = crtcs;
c707c361 1689
a3584f60 1690 ret = tda998x_create(client, priv);
c707c361
RK		 1691 if (ret)
1692 return ret;
1693
1694 if (!dev->of_node && params)
94579273 1695 tda998x_set_config(priv, params);
c707c361 1696
a3584f60
RK		 1697 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1698 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
13a3d91f 1699 DRM_MODE_ENCODER_TMDS, NULL);
c707c361
RK		 1700 if (ret)
1701 goto err_encoder;
1702
a2f75662 1703 ret = tda998x_connector_init(priv, drm);
c707c361
RK		 1704 if (ret)
1705 goto err_connector;
1706
c707c361
RK		 1707 return 0;
1708
c707c361 1709err_connector:
a3584f60 1710 drm_encoder_cleanup(&priv->encoder);
c707c361 1711err_encoder:
a3584f60 1712 tda998x_destroy(priv);
c707c361
RK		 1713 return ret;
1714}
1715
1716static void tda998x_unbind(struct device *dev, struct device *master,
1717 void *data)
1718{
a3584f60 1719 struct tda998x_priv *priv = dev_get_drvdata(dev);
c707c361 1720
a3584f60
RK		 1721 drm_connector_cleanup(&priv->connector);
1722 drm_encoder_cleanup(&priv->encoder);
1723 tda998x_destroy(priv);
c707c361
RK		 1724}
1725
1726static const struct component_ops tda998x_ops = {
1727 .bind = tda998x_bind,
1728 .unbind = tda998x_unbind,
1729};
1730
1731static int
1732tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1733{
14e5b588
RK		 1734 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1735 dev_warn(&client->dev, "adapter does not support I2C\n");
1736 return -EIO;
1737 }
c707c361
RK		 1738 return component_add(&client->dev, &tda998x_ops);
1739}
1740
1741static int tda998x_remove(struct i2c_client *client)
1742{
1743 component_del(&client->dev, &tda998x_ops);
1744 return 0;
1745}
1746
0d44ea19
JFM		 1747#ifdef CONFIG_OF
1748static const struct of_device_id tda998x_dt_ids[] = {
1749 { .compatible = "nxp,tda998x", },
1750 { }
1751};
1752MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1753#endif
1754
b7f08c89 1755static const struct i2c_device_id tda998x_ids[] = {
e7792ce2
RC		 1756 { "tda998x", 0 },
1757 { }
1758};
1759MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1760
3d58e318
RK		 1761static struct i2c_driver tda998x_driver = {
1762 .probe = tda998x_probe,
1763 .remove = tda998x_remove,
1764 .driver = {
1765 .name = "tda998x",
1766 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2 1767 },
3d58e318 1768 .id_table = tda998x_ids,
e7792ce2
RC		 1769};
1770
3d58e318 1771module_i2c_driver(tda998x_driver);
e7792ce2
RC		 1772
1773MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1774MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1775MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)