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drm/i2c: tda998x: add OF support for finding attached CRTCs
[linux-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
CommitLineData
e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
e7792ce2
RC		 23
24#include <drm/drmP.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_encoder_slave.h>
27#include <drm/drm_edid.h>
5dbcf319 28#include <drm/drm_of.h>
c4c11dd1 29#include <drm/i2c/tda998x.h>
e7792ce2
RC		 30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
2f7f730a 35 struct i2c_client *hdmi;
e7792ce2
RC		 36 uint16_t rev;
37 uint8_t current_page;
38 int dpms;
c4c11dd1 39 bool is_hdmi_sink;
5e74c22c
RK		 40 u8 vip_cntrl_0;
41 u8 vip_cntrl_1;
42 u8 vip_cntrl_2;
c4c11dd1 43 struct tda998x_encoder_params params;
12473b7d
JFM		 44
45 wait_queue_head_t wq_edid;
46 volatile int wq_edid_wait;
47 struct drm_encoder *encoder;
e7792ce2
RC		 48};
49
50#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
51
52/* The TDA9988 series of devices use a paged register scheme.. to simplify
53 * things we encode the page # in upper bits of the register #. To read/
54 * write a given register, we need to make sure CURPAGE register is set
55 * appropriately. Which implies reads/writes are not atomic. Fun!
56 */
57
58#define REG(page, addr) (((page) << 8) | (addr))
59#define REG2ADDR(reg) ((reg) & 0xff)
60#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
61
62#define REG_CURPAGE 0xff /* write */
63
64
65/* Page 00h: General Control */
66#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
67#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
68# define MAIN_CNTRL0_SR (1 << 0)
69# define MAIN_CNTRL0_DECS (1 << 1)
70# define MAIN_CNTRL0_DEHS (1 << 2)
71# define MAIN_CNTRL0_CECS (1 << 3)
72# define MAIN_CNTRL0_CEHS (1 << 4)
73# define MAIN_CNTRL0_SCALER (1 << 7)
74#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
75#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
76# define SOFTRESET_AUDIO (1 << 0)
77# define SOFTRESET_I2C_MASTER (1 << 1)
78#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
79#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
80#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
81# define I2C_MASTER_DIS_MM (1 << 0)
82# define I2C_MASTER_DIS_FILT (1 << 1)
83# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 84#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
85# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 86#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
87#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
88#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
89# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 90#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 91#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
92#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
93#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
94#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
95#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
96# define VIP_CNTRL_0_MIRR_A (1 << 7)
97# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
98# define VIP_CNTRL_0_MIRR_B (1 << 3)
99# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
100#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
101# define VIP_CNTRL_1_MIRR_C (1 << 7)
102# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
103# define VIP_CNTRL_1_MIRR_D (1 << 3)
104# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
105#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
106# define VIP_CNTRL_2_MIRR_E (1 << 7)
107# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
108# define VIP_CNTRL_2_MIRR_F (1 << 3)
109# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
110#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
111# define VIP_CNTRL_3_X_TGL (1 << 0)
112# define VIP_CNTRL_3_H_TGL (1 << 1)
113# define VIP_CNTRL_3_V_TGL (1 << 2)
114# define VIP_CNTRL_3_EMB (1 << 3)
115# define VIP_CNTRL_3_SYNC_DE (1 << 4)
116# define VIP_CNTRL_3_SYNC_HS (1 << 5)
117# define VIP_CNTRL_3_DE_INT (1 << 6)
118# define VIP_CNTRL_3_EDGE (1 << 7)
119#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
120# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
121# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
122# define VIP_CNTRL_4_CCIR656 (1 << 4)
123# define VIP_CNTRL_4_656_ALT (1 << 5)
124# define VIP_CNTRL_4_TST_656 (1 << 6)
125# define VIP_CNTRL_4_TST_PAT (1 << 7)
126#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
127# define VIP_CNTRL_5_CKCASE (1 << 0)
128# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 129#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 130# define MUX_AP_SELECT_I2S 0x64
131# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 132#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 133#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
134# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
135# define MAT_CONTRL_MAT_BP (1 << 2)
136#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
137#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
138#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
139#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
140#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
141#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
142#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
143#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
144#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
145#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
146#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
147#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
148#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
149#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
150#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
151#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
152#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 153#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
154#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 155#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
156#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 157#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
158#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 159#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
160#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
161#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
162#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
163#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
164#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
165#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
166#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
167#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
168#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 169#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
170#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
171#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
172#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 173#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
174#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
175#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
176#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
177#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 178# define TBG_CNTRL_0_TOP_TGL (1 << 0)
179# define TBG_CNTRL_0_TOP_SEL (1 << 1)
180# define TBG_CNTRL_0_DE_EXT (1 << 2)
181# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 182# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
183# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
184# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
185#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 186# define TBG_CNTRL_1_H_TGL (1 << 0)
187# define TBG_CNTRL_1_V_TGL (1 << 1)
188# define TBG_CNTRL_1_TGL_EN (1 << 2)
189# define TBG_CNTRL_1_X_EXT (1 << 3)
190# define TBG_CNTRL_1_H_EXT (1 << 4)
191# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 192# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
193#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
194#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
195# define HVF_CNTRL_0_SM (1 << 7)
196# define HVF_CNTRL_0_RWB (1 << 6)
197# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
198# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
199#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
200# define HVF_CNTRL_1_FOR (1 << 0)
201# define HVF_CNTRL_1_YUVBLK (1 << 1)
202# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
203# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
204# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
205#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 206#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
207# define I2S_FORMAT(x) (((x) & 3) << 0)
208#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 209# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
210# define AIP_CLKSEL_AIP_I2S (1 << 3)
211# define AIP_CLKSEL_FS_ACLK (0 << 0)
212# define AIP_CLKSEL_FS_MCLK (1 << 0)
213# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 214
215/* Page 02h: PLL settings */
216#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
217# define PLL_SERIAL_1_SRL_FDN (1 << 0)
218# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
219# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
220#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 221# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 222# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
223#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
224# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
225# define PLL_SERIAL_3_SRL_DE (1 << 2)
226# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
227#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
228#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
229#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
230#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
231#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
232#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
233#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
234#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
235#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 236# define AUDIO_DIV_SERCLK_1 0
237# define AUDIO_DIV_SERCLK_2 1
238# define AUDIO_DIV_SERCLK_4 2
239# define AUDIO_DIV_SERCLK_8 3
240# define AUDIO_DIV_SERCLK_16 4
241# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 242#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
243# define SEL_CLK_SEL_CLK1 (1 << 0)
244# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
245# define SEL_CLK_ENA_SC_CLK (1 << 3)
246#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
247
248
249/* Page 09h: EDID Control */
250#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
251/* next 127 successive registers are the EDID block */
252#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
253#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
254#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
255#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
256#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
257
258
259/* Page 10h: information frames and packets */
c4c11dd1
RK		 260#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
261#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
262#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
263#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
264#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 265
266
267/* Page 11h: audio settings and content info packets */
268#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
269# define AIP_CNTRL_0_RST_FIFO (1 << 0)
270# define AIP_CNTRL_0_SWAP (1 << 1)
271# define AIP_CNTRL_0_LAYOUT (1 << 2)
272# define AIP_CNTRL_0_ACR_MAN (1 << 5)
273# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 274#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
275# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
276# define CA_I2S_HBR_CHSTAT (1 << 6)
277#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
278#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
279#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
280#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
281#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
282#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
283#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
284#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
285# define CTS_N_K(x) (((x) & 7) << 0)
286# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 287#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
288# define ENC_CNTRL_RST_ENC (1 << 0)
289# define ENC_CNTRL_RST_SEL (1 << 1)
290# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 291#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
292# define DIP_FLAGS_ACR (1 << 0)
293# define DIP_FLAGS_GC (1 << 1)
294#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
295# define DIP_IF_FLAGS_IF1 (1 << 1)
296# define DIP_IF_FLAGS_IF2 (1 << 2)
297# define DIP_IF_FLAGS_IF3 (1 << 3)
298# define DIP_IF_FLAGS_IF4 (1 << 4)
299# define DIP_IF_FLAGS_IF5 (1 << 5)
300#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 301
302
303/* Page 12h: HDCP and OTP */
304#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 305#define REG_TX4 REG(0x12, 0x9b) /* read/write */
306# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 307#define REG_TX33 REG(0x12, 0xb8) /* read/write */
308# define TX33_HDMI (1 << 1)
309
310
311/* Page 13h: Gamut related metadata packets */
312
313
314
315/* CEC registers: (not paged)
316 */
12473b7d
JFM		 317#define REG_CEC_INTSTATUS 0xee /* read */
318# define CEC_INTSTATUS_CEC (1 << 0)
319# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 320#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
321# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
322# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
323# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
324# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 325#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
326#define REG_CEC_RXSHPDINT 0xfd /* read */
e7792ce2
RC		 327#define REG_CEC_RXSHPDLEV 0xfe /* read */
328# define CEC_RXSHPDLEV_RXSENS (1 << 0)
329# define CEC_RXSHPDLEV_HPD (1 << 1)
330
331#define REG_CEC_ENAMODS 0xff /* read/write */
332# define CEC_ENAMODS_DIS_FRO (1 << 6)
333# define CEC_ENAMODS_DIS_CCLK (1 << 5)
334# define CEC_ENAMODS_EN_RXSENS (1 << 2)
335# define CEC_ENAMODS_EN_HDMI (1 << 1)
336# define CEC_ENAMODS_EN_CEC (1 << 0)
337
338
339/* Device versions: */
340#define TDA9989N2 0x0101
341#define TDA19989 0x0201
342#define TDA19989N2 0x0202
343#define TDA19988 0x0301
344
345static void
2f7f730a 346cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
e7792ce2 347{
2f7f730a 348 struct i2c_client *client = priv->cec;
e7792ce2
RC		 349 uint8_t buf[] = {addr, val};
350 int ret;
351
704d63f5 352 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 353 if (ret < 0)
354 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
355}
356
357static uint8_t
2f7f730a 358cec_read(struct tda998x_priv *priv, uint8_t addr)
e7792ce2 359{
2f7f730a 360 struct i2c_client *client = priv->cec;
e7792ce2
RC		 361 uint8_t val;
362 int ret;
363
364 ret = i2c_master_send(client, &addr, sizeof(addr));
365 if (ret < 0)
366 goto fail;
367
368 ret = i2c_master_recv(client, &val, sizeof(val));
369 if (ret < 0)
370 goto fail;
371
372 return val;
373
374fail:
375 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
376 return 0;
377}
378
7d2eadc9 379static int
2f7f730a 380set_page(struct tda998x_priv *priv, uint16_t reg)
e7792ce2 381{
e7792ce2 382 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 383 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 384 uint8_t buf[] = {
385 REG_CURPAGE, REG2PAGE(reg)
386 };
387 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 388 if (ret < 0) {
704d63f5
JFM		 389 dev_err(&client->dev, "setpage %04x err %d\n",
390 reg, ret);
7d2eadc9
JFM		 391 return ret;
392 }
e7792ce2
RC		 393
394 priv->current_page = REG2PAGE(reg);
395 }
7d2eadc9 396 return 0;
e7792ce2
RC		 397}
398
399static int
2f7f730a 400reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
e7792ce2 401{
2f7f730a 402 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 403 uint8_t addr = REG2ADDR(reg);
404 int ret;
405
7d2eadc9
JFM		 406 ret = set_page(priv, reg);
407 if (ret < 0)
408 return ret;
e7792ce2
RC		 409
410 ret = i2c_master_send(client, &addr, sizeof(addr));
411 if (ret < 0)
412 goto fail;
413
414 ret = i2c_master_recv(client, buf, cnt);
415 if (ret < 0)
416 goto fail;
417
418 return ret;
419
420fail:
421 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
422 return ret;
423}
424
c4c11dd1 425static void
2f7f730a 426reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
c4c11dd1 427{
2f7f730a 428 struct i2c_client *client = priv->hdmi;
c4c11dd1
RK		 429 uint8_t buf[cnt+1];
430 int ret;
431
432 buf[0] = REG2ADDR(reg);
433 memcpy(&buf[1], p, cnt);
434
7d2eadc9
JFM		 435 ret = set_page(priv, reg);
436 if (ret < 0)
437 return;
c4c11dd1
RK		 438
439 ret = i2c_master_send(client, buf, cnt + 1);
440 if (ret < 0)
441 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
442}
443
7d2eadc9 444static int
2f7f730a 445reg_read(struct tda998x_priv *priv, uint16_t reg)
e7792ce2
RC		 446{
447 uint8_t val = 0;
7d2eadc9
JFM		 448 int ret;
449
450 ret = reg_read_range(priv, reg, &val, sizeof(val));
451 if (ret < 0)
452 return ret;
e7792ce2
RC		 453 return val;
454}
455
456static void
2f7f730a 457reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 458{
2f7f730a 459 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 460 uint8_t buf[] = {REG2ADDR(reg), val};
461 int ret;
462
7d2eadc9
JFM		 463 ret = set_page(priv, reg);
464 if (ret < 0)
465 return;
e7792ce2 466
704d63f5 467 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 468 if (ret < 0)
469 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
470}
471
472static void
2f7f730a 473reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
e7792ce2 474{
2f7f730a 475 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 476 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
477 int ret;
478
7d2eadc9
JFM		 479 ret = set_page(priv, reg);
480 if (ret < 0)
481 return;
e7792ce2 482
704d63f5 483 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 484 if (ret < 0)
485 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
486}
487
488static void
2f7f730a 489reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 490{
7d2eadc9
JFM		 491 int old_val;
492
493 old_val = reg_read(priv, reg);
494 if (old_val >= 0)
495 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 496}
497
498static void
2f7f730a 499reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 500{
7d2eadc9
JFM		 501 int old_val;
502
503 old_val = reg_read(priv, reg);
504 if (old_val >= 0)
505 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 506}
507
508static void
2f7f730a 509tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 510{
511 /* reset audio and i2c master: */
81b53a16 512 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 513 msleep(50);
81b53a16 514 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 515 msleep(50);
516
517 /* reset transmitter: */
2f7f730a
JFM		 518 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
519 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 520
521 /* PLL registers common configuration */
2f7f730a
JFM		 522 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
523 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
524 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
525 reg_write(priv, REG_SERIALIZER, 0x00);
526 reg_write(priv, REG_BUFFER_OUT, 0x00);
527 reg_write(priv, REG_PLL_SCG1, 0x00);
528 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
529 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
530 reg_write(priv, REG_PLL_SCGN1, 0xfa);
531 reg_write(priv, REG_PLL_SCGN2, 0x00);
532 reg_write(priv, REG_PLL_SCGR1, 0x5b);
533 reg_write(priv, REG_PLL_SCGR2, 0x00);
534 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 535
536 /* Write the default value MUX register */
2f7f730a 537 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 538}
539
12473b7d
JFM		 540/*
541 * only 2 interrupts may occur: screen plug/unplug and EDID read
542 */
543static irqreturn_t tda998x_irq_thread(int irq, void *data)
544{
545 struct tda998x_priv *priv = data;
546 u8 sta, cec, lvl, flag0, flag1, flag2;
547
548 if (!priv)
549 return IRQ_HANDLED;
550 sta = cec_read(priv, REG_CEC_INTSTATUS);
551 cec = cec_read(priv, REG_CEC_RXSHPDINT);
552 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
553 flag0 = reg_read(priv, REG_INT_FLAGS_0);
554 flag1 = reg_read(priv, REG_INT_FLAGS_1);
555 flag2 = reg_read(priv, REG_INT_FLAGS_2);
556 DRM_DEBUG_DRIVER(
557 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
558 sta, cec, lvl, flag0, flag1, flag2);
559 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
560 priv->wq_edid_wait = 0;
561 wake_up(&priv->wq_edid);
562 } else if (cec != 0) { /* HPD change */
563 if (priv->encoder && priv->encoder->dev)
564 drm_helper_hpd_irq_event(priv->encoder->dev);
565 }
566 return IRQ_HANDLED;
567}
568
c4c11dd1
RK		 569static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
570{
8268bd48 571 int sum = 0;
c4c11dd1
RK		 572
573 while (bytes--)
8268bd48
DV		 574 sum -= *buf++;
575 return sum;
c4c11dd1
RK		 576}
577
578#define HB(x) (x)
579#define PB(x) (HB(2) + 1 + (x))
580
581static void
2f7f730a 582tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
c4c11dd1
RK		 583 uint8_t *buf, size_t size)
584{
585 buf[PB(0)] = tda998x_cksum(buf, size);
586
2f7f730a
JFM		 587 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
588 reg_write_range(priv, addr, buf, size);
589 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 590}
591
592static void
2f7f730a 593tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
c4c11dd1 594{
9e541466 595 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
c4c11dd1 596
7288ca07 597 memset(buf, 0, sizeof(buf));
9e541466 598 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
c4c11dd1 599 buf[HB(1)] = 0x01;
9e541466 600 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
c4c11dd1
RK		 601 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
602 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
603 buf[PB(4)] = p->audio_frame[4];
604 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
605
2f7f730a 606 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
c4c11dd1
RK		 607 sizeof(buf));
608}
609
610static void
2f7f730a 611tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 612{
9e541466 613 u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1];
c4c11dd1
RK		 614
615 memset(buf, 0, sizeof(buf));
9e541466 616 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI;
c4c11dd1 617 buf[HB(1)] = 0x02;
9e541466 618 buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE;
893c3e53 619 buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN;
bdf6345b 620 buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE;
893c3e53 621 buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2;
c4c11dd1
RK		 622 buf[PB(4)] = drm_match_cea_mode(mode);
623
2f7f730a 624 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf,
c4c11dd1
RK		 625 sizeof(buf));
626}
627
2f7f730a 628static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 629{
630 if (on) {
2f7f730a
JFM		 631 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
632 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
633 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 634 } else {
2f7f730a 635 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 636 }
637}
638
639static void
2f7f730a 640tda998x_configure_audio(struct tda998x_priv *priv,
c4c11dd1
RK		 641 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
642{
85c988bb 643 uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv;
c4c11dd1
RK		 644 uint32_t n;
645
646 /* Enable audio ports */
2f7f730a
JFM		 647 reg_write(priv, REG_ENA_AP, p->audio_cfg);
648 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
c4c11dd1
RK		 649
650 /* Set audio input source */
651 switch (p->audio_format) {
652 case AFMT_SPDIF:
10df1a95
JFM		 653 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
654 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
655 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 656 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 657 break;
658
659 case AFMT_I2S:
10df1a95
JFM		 660 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
661 clksel_aip = AIP_CLKSEL_AIP_I2S;
662 clksel_fs = AIP_CLKSEL_FS_ACLK;
c4c11dd1 663 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1 664 break;
3b28802e
DH		 665
666 default:
667 BUG();
668 return;
c4c11dd1
RK		 669 }
670
2f7f730a 671 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 672 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
673 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 674 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 675
676 /*
677 * Audio input somehow depends on HDMI line rate which is
678 * related to pixclk. Testing showed that modes with pixclk
679 * >100MHz need a larger divider while <40MHz need the default.
680 * There is no detailed info in the datasheet, so we just
681 * assume 100MHz requires larger divider.
682 */
2470fecc 683 adiv = AUDIO_DIV_SERCLK_8;
c4c11dd1 684 if (mode->clock > 100000)
2470fecc
JFM		 685 adiv++; /* AUDIO_DIV_SERCLK_16 */
686
687 /* S/PDIF asks for a larger divider */
688 if (p->audio_format == AFMT_SPDIF)
689 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
690
2f7f730a 691 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 692
693 /*
694 * This is the approximate value of N, which happens to be
695 * the recommended values for non-coherent clocks.
696 */
697 n = 128 * p->audio_sample_rate / 1000;
698
699 /* Write the CTS and N values */
700 buf[0] = 0x44;
701 buf[1] = 0x42;
702 buf[2] = 0x01;
703 buf[3] = n;
704 buf[4] = n >> 8;
705 buf[5] = n >> 16;
2f7f730a 706 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 707
708 /* Set CTS clock reference */
2f7f730a 709 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 710
711 /* Reset CTS generator */
2f7f730a
JFM		 712 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
713 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1
RK		 714
715 /* Write the channel status */
f0b33b28 716 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
c4c11dd1 717 buf[1] = 0x00;
f0b33b28
JFM		 718 buf[2] = IEC958_AES3_CON_FS_NOTID;
719 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
720 IEC958_AES4_CON_MAX_WORDLEN_24;
2f7f730a 721 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 722
2f7f730a 723 tda998x_audio_mute(priv, true);
73d5e253 724 msleep(20);
2f7f730a 725 tda998x_audio_mute(priv, false);
c4c11dd1
RK		 726
727 /* Write the audio information packet */
2f7f730a 728 tda998x_write_aif(priv, p);
c4c11dd1
RK		 729}
730
e7792ce2
RC		 731/* DRM encoder functions */
732
a8f4d4d6
RK		 733static void tda998x_encoder_set_config(struct tda998x_priv *priv,
734 const struct tda998x_encoder_params *p)
e7792ce2 735{
c4c11dd1
RK		 736 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
737 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
738 VIP_CNTRL_0_SWAP_B(p->swap_b) |
739 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
740 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
741 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
742 VIP_CNTRL_1_SWAP_D(p->swap_d) |
743 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
744 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
745 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
746 VIP_CNTRL_2_SWAP_F(p->swap_f) |
747 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
748
749 priv->params = *p;
e7792ce2
RC		 750}
751
a8f4d4d6 752static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
e7792ce2 753{
e7792ce2
RC		 754 /* we only care about on or off: */
755 if (mode != DRM_MODE_DPMS_ON)
756 mode = DRM_MODE_DPMS_OFF;
757
758 if (mode == priv->dpms)
759 return;
760
761 switch (mode) {
762 case DRM_MODE_DPMS_ON:
c4c11dd1 763 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 764 reg_write(priv, REG_ENA_VP_0, 0xff);
765 reg_write(priv, REG_ENA_VP_1, 0xff);
766 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 767 /* set muxing after enabling ports: */
2f7f730a
JFM		 768 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
769 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
770 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 771 break;
772 case DRM_MODE_DPMS_OFF:
db6aaf4d 773 /* disable video ports */
2f7f730a
JFM		 774 reg_write(priv, REG_ENA_VP_0, 0x00);
775 reg_write(priv, REG_ENA_VP_1, 0x00);
776 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 777 break;
778 }
779
780 priv->dpms = mode;
781}
782
783static void
784tda998x_encoder_save(struct drm_encoder *encoder)
785{
786 DBG("");
787}
788
789static void
790tda998x_encoder_restore(struct drm_encoder *encoder)
791{
792 DBG("");
793}
794
795static bool
796tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
797 const struct drm_display_mode *mode,
798 struct drm_display_mode *adjusted_mode)
799{
800 return true;
801}
802
a8f4d4d6
RK		 803static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
804 struct drm_display_mode *mode)
e7792ce2 805{
92fbdfcd
RK		 806 if (mode->clock > 150000)
807 return MODE_CLOCK_HIGH;
808 if (mode->htotal >= BIT(13))
809 return MODE_BAD_HVALUE;
810 if (mode->vtotal >= BIT(11))
811 return MODE_BAD_VVALUE;
e7792ce2
RC		 812 return MODE_OK;
813}
814
815static void
a8f4d4d6
RK		 816tda998x_encoder_mode_set(struct tda998x_priv *priv,
817 struct drm_display_mode *mode,
818 struct drm_display_mode *adjusted_mode)
e7792ce2 819{
088d61d1
SH		 820 uint16_t ref_pix, ref_line, n_pix, n_line;
821 uint16_t hs_pix_s, hs_pix_e;
822 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
823 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
824 uint16_t vwin1_line_s, vwin1_line_e;
825 uint16_t vwin2_line_s, vwin2_line_e;
826 uint16_t de_pix_s, de_pix_e;
e7792ce2
RC		 827 uint8_t reg, div, rep;
828
088d61d1
SH		 829 /*
830 * Internally TDA998x is using ITU-R BT.656 style sync but
831 * we get VESA style sync. TDA998x is using a reference pixel
832 * relative to ITU to sync to the input frame and for output
833 * sync generation. Currently, we are using reference detection
834 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
835 * which is position of rising VS with coincident rising HS.
836 *
837 * Now there is some issues to take care of:
838 * - HDMI data islands require sync-before-active
839 * - TDA998x register values must be > 0 to be enabled
840 * - REFLINE needs an additional offset of +1
841 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
842 *
843 * So we add +1 to all horizontal and vertical register values,
844 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 845 */
088d61d1
SH		 846 n_pix = mode->htotal;
847 n_line = mode->vtotal;
848
849 hs_pix_e = mode->hsync_end - mode->hdisplay;
850 hs_pix_s = mode->hsync_start - mode->hdisplay;
851 de_pix_e = mode->htotal;
852 de_pix_s = mode->htotal - mode->hdisplay;
853 ref_pix = 3 + hs_pix_s;
854
179f1aa4
SH		 855 /*
856 * Attached LCD controllers may generate broken sync. Allow
857 * those to adjust the position of the rising VS edge by adding
858 * HSKEW to ref_pix.
859 */
860 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
861 ref_pix += adjusted_mode->hskew;
862
088d61d1
SH		 863 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
864 ref_line = 1 + mode->vsync_start - mode->vdisplay;
865 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
866 vwin1_line_e = vwin1_line_s + mode->vdisplay;
867 vs1_pix_s = vs1_pix_e = hs_pix_s;
868 vs1_line_s = mode->vsync_start - mode->vdisplay;
869 vs1_line_e = vs1_line_s +
870 mode->vsync_end - mode->vsync_start;
871 vwin2_line_s = vwin2_line_e = 0;
872 vs2_pix_s = vs2_pix_e = 0;
873 vs2_line_s = vs2_line_e = 0;
874 } else {
875 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
876 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
877 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
878 vs1_pix_s = vs1_pix_e = hs_pix_s;
879 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
880 vs1_line_e = vs1_line_s +
881 (mode->vsync_end - mode->vsync_start)/2;
882 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
883 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
884 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
885 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
886 vs2_line_e = vs2_line_s +
887 (mode->vsync_end - mode->vsync_start)/2;
888 }
e7792ce2
RC		 889
890 div = 148500 / mode->clock;
3ae471f7
JFM		 891 if (div != 0) {
892 div--;
893 if (div > 3)
894 div = 3;
895 }
e7792ce2 896
e7792ce2 897 /* mute the audio FIFO: */
2f7f730a 898 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 899
900 /* set HDMI HDCP mode off: */
81b53a16 901 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 902 reg_clear(priv, REG_TX33, TX33_HDMI);
903 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 904
e7792ce2 905 /* no pre-filter or interpolator: */
2f7f730a 906 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 907 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 908 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
909 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 910 VIP_CNTRL_4_BLC(0));
e7792ce2 911
2f7f730a 912 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 913 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
914 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 915 reg_write(priv, REG_SERIALIZER, 0);
916 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 917
918 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
919 rep = 0;
2f7f730a
JFM		 920 reg_write(priv, REG_RPT_CNTRL, 0);
921 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 922 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
923
2f7f730a 924 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 925 PLL_SERIAL_2_SRL_PR(rep));
926
e7792ce2 927 /* set color matrix bypass flag: */
81b53a16
JFM		 928 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
929 MAT_CONTRL_MAT_SC(1));
e7792ce2
RC		 930
931 /* set BIAS tmds value: */
2f7f730a 932 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 933
088d61d1
SH		 934 /*
935 * Sync on rising HSYNC/VSYNC
936 */
81b53a16 937 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 938
939 /*
940 * TDA19988 requires high-active sync at input stage,
941 * so invert low-active sync provided by master encoder here
942 */
943 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 944 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 945 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 946 reg |= VIP_CNTRL_3_V_TGL;
947 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 948
949 reg_write(priv, REG_VIDFORMAT, 0x00);
950 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
951 reg_write16(priv, REG_REFLINE_MSB, ref_line);
952 reg_write16(priv, REG_NPIX_MSB, n_pix);
953 reg_write16(priv, REG_NLINE_MSB, n_line);
954 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
955 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
956 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
957 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
958 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
959 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
960 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
961 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
962 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
963 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
964 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
965 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
966 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
967 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
968 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
969 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 970
971 if (priv->rev == TDA19988) {
972 /* let incoming pixels fill the active space (if any) */
2f7f730a 973 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 974 }
975
81b53a16
JFM		 976 /*
977 * Always generate sync polarity relative to input sync and
978 * revert input stage toggled sync at output stage
979 */
980 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
981 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
982 reg |= TBG_CNTRL_1_H_TGL;
983 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
984 reg |= TBG_CNTRL_1_V_TGL;
985 reg_write(priv, REG_TBG_CNTRL_1, reg);
986
e7792ce2 987 /* must be last register set: */
81b53a16 988 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1
RK		 989
990 /* Only setup the info frames if the sink is HDMI */
991 if (priv->is_hdmi_sink) {
992 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 993 reg &= ~TBG_CNTRL_1_DWIN_DIS;
994 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 995 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
996 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 997
2f7f730a 998 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1
RK		 999
1000 if (priv->params.audio_cfg)
2f7f730a 1001 tda998x_configure_audio(priv, adjusted_mode,
c4c11dd1
RK		 1002 &priv->params);
1003 }
e7792ce2
RC		 1004}
1005
1006static enum drm_connector_status
a8f4d4d6 1007tda998x_encoder_detect(struct tda998x_priv *priv)
e7792ce2 1008{
2f7f730a
JFM		 1009 uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
1010
e7792ce2
RC		 1011 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1012 connector_status_disconnected;
1013}
1014
a8f4d4d6 1015static int read_edid_block(struct tda998x_priv *priv, uint8_t *buf, int blk)
e7792ce2
RC		 1016{
1017 uint8_t offset, segptr;
1018 int ret, i;
1019
e7792ce2
RC		 1020 offset = (blk & 1) ? 128 : 0;
1021 segptr = blk / 2;
1022
2f7f730a
JFM		 1023 reg_write(priv, REG_DDC_ADDR, 0xa0);
1024 reg_write(priv, REG_DDC_OFFS, offset);
1025 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1026 reg_write(priv, REG_DDC_SEGM, segptr);
e7792ce2
RC		 1027
1028 /* enable reading EDID: */
12473b7d 1029 priv->wq_edid_wait = 1;
2f7f730a 1030 reg_write(priv, REG_EDID_CTRL, 0x1);
e7792ce2
RC		 1031
1032 /* flag must be cleared by sw: */
2f7f730a 1033 reg_write(priv, REG_EDID_CTRL, 0x0);
e7792ce2
RC		 1034
1035 /* wait for block read to complete: */
12473b7d
JFM		 1036 if (priv->hdmi->irq) {
1037 i = wait_event_timeout(priv->wq_edid,
1038 !priv->wq_edid_wait,
1039 msecs_to_jiffies(100));
1040 if (i < 0) {
5e7fe2fe 1041 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
12473b7d
JFM		 1042 return i;
1043 }
1044 } else {
713456db
RK		 1045 for (i = 100; i > 0; i--) {
1046 msleep(1);
12473b7d
JFM		 1047 ret = reg_read(priv, REG_INT_FLAGS_2);
1048 if (ret < 0)
1049 return ret;
1050 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1051 break;
1052 }
e7792ce2
RC		 1053 }
1054
12473b7d 1055 if (i == 0) {
5e7fe2fe 1056 dev_err(&priv->hdmi->dev, "read edid timeout\n");
e7792ce2 1057 return -ETIMEDOUT;
12473b7d 1058 }
e7792ce2 1059
2f7f730a 1060 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH);
e7792ce2 1061 if (ret != EDID_LENGTH) {
5e7fe2fe
RK		 1062 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1063 blk, ret);
e7792ce2
RC		 1064 return ret;
1065 }
1066
e7792ce2
RC		 1067 return 0;
1068}
1069
a8f4d4d6 1070static uint8_t *do_get_edid(struct tda998x_priv *priv)
e7792ce2 1071{
704d63f5 1072 int j, valid_extensions = 0;
e7792ce2
RC		 1073 uint8_t *block, *new;
1074 bool print_bad_edid = drm_debug & DRM_UT_KMS;
1075
1076 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1077 return NULL;
1078
063b472f 1079 if (priv->rev == TDA19988)
2f7f730a 1080 reg_clear(priv, REG_TX4, TX4_PD_RAM);
063b472f 1081
e7792ce2 1082 /* base block fetch */
a8f4d4d6 1083 if (read_edid_block(priv, block, 0))
e7792ce2
RC		 1084 goto fail;
1085
1086 if (!drm_edid_block_valid(block, 0, print_bad_edid))
1087 goto fail;
1088
1089 /* if there's no extensions, we're done */
1090 if (block[0x7e] == 0)
063b472f 1091 goto done;
e7792ce2
RC		 1092
1093 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1094 if (!new)
1095 goto fail;
1096 block = new;
1097
1098 for (j = 1; j <= block[0x7e]; j++) {
1099 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
a8f4d4d6 1100 if (read_edid_block(priv, ext_block, j))
e7792ce2
RC		 1101 goto fail;
1102
1103 if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
1104 goto fail;
1105
1106 valid_extensions++;
1107 }
1108
1109 if (valid_extensions != block[0x7e]) {
1110 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1111 block[0x7e] = valid_extensions;
1112 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1113 if (!new)
1114 goto fail;
1115 block = new;
1116 }
1117
063b472f
RK		 1118done:
1119 if (priv->rev == TDA19988)
2f7f730a 1120 reg_set(priv, REG_TX4, TX4_PD_RAM);
063b472f 1121
e7792ce2
RC		 1122 return block;
1123
1124fail:
063b472f 1125 if (priv->rev == TDA19988)
2f7f730a 1126 reg_set(priv, REG_TX4, TX4_PD_RAM);
5e7fe2fe 1127 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
e7792ce2
RC		 1128 kfree(block);
1129 return NULL;
1130}
1131
1132static int
a8f4d4d6
RK		 1133tda998x_encoder_get_modes(struct tda998x_priv *priv,
1134 struct drm_connector *connector)
e7792ce2 1135{
a8f4d4d6 1136 struct edid *edid = (struct edid *)do_get_edid(priv);
e7792ce2
RC		 1137 int n = 0;
1138
1139 if (edid) {
1140 drm_mode_connector_update_edid_property(connector, edid);
1141 n = drm_add_edid_modes(connector, edid);
c4c11dd1 1142 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
e7792ce2
RC		 1143 kfree(edid);
1144 }
1145
1146 return n;
1147}
1148
a8f4d4d6
RK		 1149static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1150 struct drm_connector *connector)
e7792ce2 1151{
12473b7d
JFM		 1152 if (priv->hdmi->irq)
1153 connector->polled = DRM_CONNECTOR_POLL_HPD;
1154 else
1155 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1156 DRM_CONNECTOR_POLL_DISCONNECT;
e7792ce2
RC		 1157}
1158
1159static int
1160tda998x_encoder_set_property(struct drm_encoder *encoder,
1161 struct drm_connector *connector,
1162 struct drm_property *property,
1163 uint64_t val)
1164{
1165 DBG("");
1166 return 0;
1167}
1168
a8f4d4d6 1169static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1170{
12473b7d
JFM		 1171 /* disable all IRQs and free the IRQ handler */
1172 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1173 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1174 if (priv->hdmi->irq)
1175 free_irq(priv->hdmi->irq, priv);
1176
89fc8686 1177 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1178}
1179
1180/* Slave encoder support */
1181
1182static void
1183tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params)
1184{
1185 tda998x_encoder_set_config(to_tda998x_priv(encoder), params);
1186}
1187
1188static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder)
1189{
1190 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1191
1192 tda998x_destroy(priv);
2e48cecb 1193 drm_i2c_encoder_destroy(encoder);
e7792ce2
RC		 1194 kfree(priv);
1195}
1196
a8f4d4d6
RK		 1197static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode)
1198{
1199 tda998x_encoder_dpms(to_tda998x_priv(encoder), mode);
1200}
e7792ce2 1201
a8f4d4d6
RK		 1202static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder,
1203 struct drm_display_mode *mode)
1204{
1205 return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode);
1206}
e7792ce2 1207
a8f4d4d6
RK		 1208static void
1209tda998x_encoder_slave_mode_set(struct drm_encoder *encoder,
1210 struct drm_display_mode *mode,
1211 struct drm_display_mode *adjusted_mode)
e7792ce2 1212{
a8f4d4d6
RK		 1213 tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode);
1214}
1215
1216static enum drm_connector_status
1217tda998x_encoder_slave_detect(struct drm_encoder *encoder,
1218 struct drm_connector *connector)
1219{
1220 return tda998x_encoder_detect(to_tda998x_priv(encoder));
1221}
1222
1223static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder,
1224 struct drm_connector *connector)
1225{
1226 return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector);
e7792ce2
RC		 1227}
1228
1229static int
a8f4d4d6
RK		 1230tda998x_encoder_slave_create_resources(struct drm_encoder *encoder,
1231 struct drm_connector *connector)
e7792ce2 1232{
a8f4d4d6 1233 tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector);
e7792ce2
RC		 1234 return 0;
1235}
1236
a8f4d4d6
RK		 1237static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = {
1238 .set_config = tda998x_encoder_slave_set_config,
1239 .destroy = tda998x_encoder_slave_destroy,
1240 .dpms = tda998x_encoder_slave_dpms,
e7792ce2
RC		 1241 .save = tda998x_encoder_save,
1242 .restore = tda998x_encoder_restore,
1243 .mode_fixup = tda998x_encoder_mode_fixup,
a8f4d4d6
RK		 1244 .mode_valid = tda998x_encoder_slave_mode_valid,
1245 .mode_set = tda998x_encoder_slave_mode_set,
1246 .detect = tda998x_encoder_slave_detect,
1247 .get_modes = tda998x_encoder_slave_get_modes,
1248 .create_resources = tda998x_encoder_slave_create_resources,
e7792ce2
RC		 1249 .set_property = tda998x_encoder_set_property,
1250};
1251
1252/* I2C driver functions */
1253
a8f4d4d6 1254static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1255{
0d44ea19
JFM		 1256 struct device_node *np = client->dev.of_node;
1257 u32 video;
fb7544d7 1258 int rev_lo, rev_hi, ret;
e7792ce2 1259
5e74c22c
RK		 1260 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1261 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1262 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1263
2eb4c7b1 1264 priv->current_page = 0xff;
2f7f730a 1265 priv->hdmi = client;
e7792ce2 1266 priv->cec = i2c_new_dummy(client->adapter, 0x34);
a8f4d4d6 1267 if (!priv->cec)
6ae668cc 1268 return -ENODEV;
12473b7d 1269
e7792ce2
RC		 1270 priv->dpms = DRM_MODE_DPMS_OFF;
1271
e7792ce2 1272 /* wake up the device: */
2f7f730a 1273 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1274 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1275
2f7f730a 1276 tda998x_reset(priv);
e7792ce2
RC		 1277
1278 /* read version: */
fb7544d7
RK		 1279 rev_lo = reg_read(priv, REG_VERSION_LSB);
1280 rev_hi = reg_read(priv, REG_VERSION_MSB);
1281 if (rev_lo < 0 || rev_hi < 0) {
1282 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1283 goto fail;
fb7544d7
RK		 1284 }
1285
1286 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1287
1288 /* mask off feature bits: */
1289 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1290
1291 switch (priv->rev) {
b728fab7
JFM		 1292 case TDA9989N2:
1293 dev_info(&client->dev, "found TDA9989 n2");
1294 break;
1295 case TDA19989:
1296 dev_info(&client->dev, "found TDA19989");
1297 break;
1298 case TDA19989N2:
1299 dev_info(&client->dev, "found TDA19989 n2");
1300 break;
1301 case TDA19988:
1302 dev_info(&client->dev, "found TDA19988");
1303 break;
e7792ce2 1304 default:
b728fab7
JFM		 1305 dev_err(&client->dev, "found unsupported device: %04x\n",
1306 priv->rev);
e7792ce2
RC		 1307 goto fail;
1308 }
1309
1310 /* after reset, enable DDC: */
2f7f730a 1311 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1312
1313 /* set clock on DDC channel: */
2f7f730a 1314 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1315
1316 /* if necessary, disable multi-master: */
1317 if (priv->rev == TDA19989)
2f7f730a 1318 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1319
2f7f730a 1320 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1321 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1322
12473b7d
JFM		 1323 /* initialize the optional IRQ */
1324 if (client->irq) {
1325 int irqf_trigger;
1326
1327 /* init read EDID waitqueue */
1328 init_waitqueue_head(&priv->wq_edid);
1329
1330 /* clear pending interrupts */
1331 reg_read(priv, REG_INT_FLAGS_0);
1332 reg_read(priv, REG_INT_FLAGS_1);
1333 reg_read(priv, REG_INT_FLAGS_2);
1334
1335 irqf_trigger =
1336 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1337 ret = request_threaded_irq(client->irq, NULL,
1338 tda998x_irq_thread,
1339 irqf_trigger | IRQF_ONESHOT,
1340 "tda998x", priv);
1341 if (ret) {
1342 dev_err(&client->dev,
1343 "failed to request IRQ#%u: %d\n",
1344 client->irq, ret);
1345 goto fail;
1346 }
1347
1348 /* enable HPD irq */
1349 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1350 }
1351
e4782627
JFM		 1352 /* enable EDID read irq: */
1353 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1354
0d44ea19
JFM		 1355 if (!np)
1356 return 0; /* non-DT */
1357
1358 /* get the optional video properties */
1359 ret = of_property_read_u32(np, "video-ports", &video);
1360 if (ret == 0) {
1361 priv->vip_cntrl_0 = video >> 16;
1362 priv->vip_cntrl_1 = video >> 8;
1363 priv->vip_cntrl_2 = video;
1364 }
1365
e7792ce2
RC		 1366 return 0;
1367
1368fail:
1369 /* if encoder_init fails, the encoder slave is never registered,
1370 * so cleanup here:
1371 */
1372 if (priv->cec)
1373 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1374 return -ENXIO;
1375}
1376
a8f4d4d6
RK		 1377static int tda998x_encoder_init(struct i2c_client *client,
1378 struct drm_device *dev,
1379 struct drm_encoder_slave *encoder_slave)
1380{
1381 struct tda998x_priv *priv;
1382 int ret;
1383
1384 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1385 if (!priv)
1386 return -ENOMEM;
1387
1388 priv->encoder = &encoder_slave->base;
1389
1390 ret = tda998x_create(client, priv);
1391 if (ret) {
1392 kfree(priv);
1393 return ret;
1394 }
1395
1396 encoder_slave->slave_priv = priv;
1397 encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs;
1398
1399 return 0;
1400}
1401
c707c361
RK		 1402struct tda998x_priv2 {
1403 struct tda998x_priv base;
1404 struct drm_encoder encoder;
1405 struct drm_connector connector;
1406};
1407
1408#define conn_to_tda998x_priv2(x) \
1409 container_of(x, struct tda998x_priv2, connector);
1410
1411#define enc_to_tda998x_priv2(x) \
1412 container_of(x, struct tda998x_priv2, encoder);
1413
1414static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1415{
1416 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1417
1418 tda998x_encoder_dpms(&priv->base, mode);
1419}
1420
1421static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1422{
1423 tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1424}
1425
1426static void tda998x_encoder_commit(struct drm_encoder *encoder)
1427{
1428 tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1429}
1430
1431static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1432 struct drm_display_mode *mode,
1433 struct drm_display_mode *adjusted_mode)
1434{
1435 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1436
1437 tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1438}
1439
1440static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1441 .dpms = tda998x_encoder2_dpms,
1442 .save = tda998x_encoder_save,
1443 .restore = tda998x_encoder_restore,
1444 .mode_fixup = tda998x_encoder_mode_fixup,
1445 .prepare = tda998x_encoder_prepare,
1446 .commit = tda998x_encoder_commit,
1447 .mode_set = tda998x_encoder2_mode_set,
1448};
1449
1450static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1451{
1452 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1453
1454 tda998x_destroy(&priv->base);
1455 drm_encoder_cleanup(encoder);
1456}
1457
1458static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1459 .destroy = tda998x_encoder_destroy,
1460};
1461
1462static int tda998x_connector_get_modes(struct drm_connector *connector)
1463{
1464 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1465
1466 return tda998x_encoder_get_modes(&priv->base, connector);
1467}
1468
1469static int tda998x_connector_mode_valid(struct drm_connector *connector,
1470 struct drm_display_mode *mode)
1471{
1472 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1473
1474 return tda998x_encoder_mode_valid(&priv->base, mode);
1475}
1476
1477static struct drm_encoder *
1478tda998x_connector_best_encoder(struct drm_connector *connector)
1479{
1480 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1481
1482 return &priv->encoder;
1483}
1484
1485static
1486const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1487 .get_modes = tda998x_connector_get_modes,
1488 .mode_valid = tda998x_connector_mode_valid,
1489 .best_encoder = tda998x_connector_best_encoder,
1490};
1491
1492static enum drm_connector_status
1493tda998x_connector_detect(struct drm_connector *connector, bool force)
1494{
1495 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1496
1497 return tda998x_encoder_detect(&priv->base);
1498}
1499
1500static void tda998x_connector_destroy(struct drm_connector *connector)
1501{
74cd62ea 1502 drm_connector_unregister(connector);
c707c361
RK		 1503 drm_connector_cleanup(connector);
1504}
1505
1506static const struct drm_connector_funcs tda998x_connector_funcs = {
1507 .dpms = drm_helper_connector_dpms,
1508 .fill_modes = drm_helper_probe_single_connector_modes,
1509 .detect = tda998x_connector_detect,
1510 .destroy = tda998x_connector_destroy,
1511};
1512
1513static int tda998x_bind(struct device *dev, struct device *master, void *data)
1514{
1515 struct tda998x_encoder_params *params = dev->platform_data;
1516 struct i2c_client *client = to_i2c_client(dev);
1517 struct drm_device *drm = data;
1518 struct tda998x_priv2 *priv;
5dbcf319 1519 uint32_t crtcs = 0;
c707c361
RK		 1520 int ret;
1521
1522 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1523 if (!priv)
1524 return -ENOMEM;
1525
1526 dev_set_drvdata(dev, priv);
1527
5dbcf319
RK		 1528 if (dev->of_node)
1529 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1530
1531 /* If no CRTCs were found, fall back to our old behaviour */
1532 if (crtcs == 0) {
1533 dev_warn(dev, "Falling back to first CRTC\n");
1534 crtcs = 1 << 0;
1535 }
1536
c707c361
RK		 1537 priv->base.encoder = &priv->encoder;
1538 priv->connector.interlace_allowed = 1;
5dbcf319 1539 priv->encoder.possible_crtcs = crtcs;
c707c361
RK		 1540
1541 ret = tda998x_create(client, &priv->base);
1542 if (ret)
1543 return ret;
1544
1545 if (!dev->of_node && params)
1546 tda998x_encoder_set_config(&priv->base, params);
1547
1548 tda998x_encoder_set_polling(&priv->base, &priv->connector);
1549
1550 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1551 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1552 DRM_MODE_ENCODER_TMDS);
1553 if (ret)
1554 goto err_encoder;
1555
1556 drm_connector_helper_add(&priv->connector,
1557 &tda998x_connector_helper_funcs);
1558 ret = drm_connector_init(drm, &priv->connector,
1559 &tda998x_connector_funcs,
1560 DRM_MODE_CONNECTOR_HDMIA);
1561 if (ret)
1562 goto err_connector;
1563
74cd62ea 1564 ret = drm_connector_register(&priv->connector);
c707c361
RK		 1565 if (ret)
1566 goto err_sysfs;
1567
1568 priv->connector.encoder = &priv->encoder;
1569 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1570
1571 return 0;
1572
1573err_sysfs:
1574 drm_connector_cleanup(&priv->connector);
1575err_connector:
1576 drm_encoder_cleanup(&priv->encoder);
1577err_encoder:
1578 tda998x_destroy(&priv->base);
1579 return ret;
1580}
1581
1582static void tda998x_unbind(struct device *dev, struct device *master,
1583 void *data)
1584{
1585 struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1586
1587 drm_connector_cleanup(&priv->connector);
1588 drm_encoder_cleanup(&priv->encoder);
1589 tda998x_destroy(&priv->base);
1590}
1591
1592static const struct component_ops tda998x_ops = {
1593 .bind = tda998x_bind,
1594 .unbind = tda998x_unbind,
1595};
1596
1597static int
1598tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1599{
1600 return component_add(&client->dev, &tda998x_ops);
1601}
1602
1603static int tda998x_remove(struct i2c_client *client)
1604{
1605 component_del(&client->dev, &tda998x_ops);
1606 return 0;
1607}
1608
0d44ea19
JFM		 1609#ifdef CONFIG_OF
1610static const struct of_device_id tda998x_dt_ids[] = {
1611 { .compatible = "nxp,tda998x", },
1612 { }
1613};
1614MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1615#endif
1616
e7792ce2
RC		 1617static struct i2c_device_id tda998x_ids[] = {
1618 { "tda998x", 0 },
1619 { }
1620};
1621MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1622
1623static struct drm_i2c_encoder_driver tda998x_driver = {
1624 .i2c_driver = {
1625 .probe = tda998x_probe,
1626 .remove = tda998x_remove,
1627 .driver = {
1628 .name = "tda998x",
0d44ea19 1629 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2
RC		 1630 },
1631 .id_table = tda998x_ids,
1632 },
1633 .encoder_init = tda998x_encoder_init,
1634};
1635
1636/* Module initialization */
1637
1638static int __init
1639tda998x_init(void)
1640{
1641 DBG("");
1642 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1643}
1644
1645static void __exit
1646tda998x_exit(void)
1647{
1648 DBG("");
1649 drm_i2c_encoder_unregister(&tda998x_driver);
1650}
1651
1652MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1653MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1654MODULE_LICENSE("GPL");
1655
1656module_init(tda998x_init);
1657module_exit(tda998x_exit);
Linux 6.x block layer and io_uring tree(s)