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drm/i2c: tda998x: remove complexity from tda998x_audio_get_eld()
[linux-2.6-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
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e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
7e567624 23#include <sound/hdmi-codec.h>
e7792ce2
RC		 24
25#include <drm/drmP.h>
9736e988 26#include <drm/drm_atomic_helper.h>
e7792ce2 27#include <drm/drm_crtc_helper.h>
e7792ce2 28#include <drm/drm_edid.h>
5dbcf319 29#include <drm/drm_of.h>
c4c11dd1 30#include <drm/i2c/tda998x.h>
e7792ce2
RC		 31
32#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
33
7e567624
JS		 34struct tda998x_audio_port {
35 u8 format; /* AFMT_xxx */
36 u8 config; /* AP value */
37};
38
e7792ce2
RC		 39struct tda998x_priv {
40 struct i2c_client *cec;
2f7f730a 41 struct i2c_client *hdmi;
ed9a8426 42 struct mutex mutex;
e66e03ab
RK		 43 u16 rev;
44 u8 current_page;
e7792ce2 45 int dpms;
896a4130 46 bool supports_infoframes;
8f3f21f6 47 bool sink_has_audio;
5e74c22c
RK		 48 u8 vip_cntrl_0;
49 u8 vip_cntrl_1;
50 u8 vip_cntrl_2;
319e658c 51 unsigned long tmds_clock;
95db3b25 52 struct tda998x_audio_params audio_params;
12473b7d 53
7e567624
JS		 54 struct platform_device *audio_pdev;
55 struct mutex audio_mutex;
56
12473b7d
JFM		 57 wait_queue_head_t wq_edid;
58 volatile int wq_edid_wait;
0fc6f44d
RK		 59
60 struct work_struct detect_work;
61 struct timer_list edid_delay_timer;
62 wait_queue_head_t edid_delay_waitq;
63 bool edid_delay_active;
78e401f9
RK		 64
65 struct drm_encoder encoder;
eed64b59 66 struct drm_connector connector;
7e567624
JS		 67
68 struct tda998x_audio_port audio_port[2];
e7792ce2
RC		 69};
70
9525c4dd
RK		 71#define conn_to_tda998x_priv(x) \
72 container_of(x, struct tda998x_priv, connector)
73
74#define enc_to_tda998x_priv(x) \
75 container_of(x, struct tda998x_priv, encoder)
76
e7792ce2
RC		 77/* The TDA9988 series of devices use a paged register scheme.. to simplify
78 * things we encode the page # in upper bits of the register #. To read/
79 * write a given register, we need to make sure CURPAGE register is set
80 * appropriately. Which implies reads/writes are not atomic. Fun!
81 */
82
83#define REG(page, addr) (((page) << 8) | (addr))
84#define REG2ADDR(reg) ((reg) & 0xff)
85#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
86
87#define REG_CURPAGE 0xff /* write */
88
89
90/* Page 00h: General Control */
91#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
92#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
93# define MAIN_CNTRL0_SR (1 << 0)
94# define MAIN_CNTRL0_DECS (1 << 1)
95# define MAIN_CNTRL0_DEHS (1 << 2)
96# define MAIN_CNTRL0_CECS (1 << 3)
97# define MAIN_CNTRL0_CEHS (1 << 4)
98# define MAIN_CNTRL0_SCALER (1 << 7)
99#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
100#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
101# define SOFTRESET_AUDIO (1 << 0)
102# define SOFTRESET_I2C_MASTER (1 << 1)
103#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
104#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
105#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
106# define I2C_MASTER_DIS_MM (1 << 0)
107# define I2C_MASTER_DIS_FILT (1 << 1)
108# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 109#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
110# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 111#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
112#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
113#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
114# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 115#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 116#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
117#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
118#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
119#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
120#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
121# define VIP_CNTRL_0_MIRR_A (1 << 7)
122# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
123# define VIP_CNTRL_0_MIRR_B (1 << 3)
124# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
125#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
126# define VIP_CNTRL_1_MIRR_C (1 << 7)
127# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
128# define VIP_CNTRL_1_MIRR_D (1 << 3)
129# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
130#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
131# define VIP_CNTRL_2_MIRR_E (1 << 7)
132# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
133# define VIP_CNTRL_2_MIRR_F (1 << 3)
134# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
135#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
136# define VIP_CNTRL_3_X_TGL (1 << 0)
137# define VIP_CNTRL_3_H_TGL (1 << 1)
138# define VIP_CNTRL_3_V_TGL (1 << 2)
139# define VIP_CNTRL_3_EMB (1 << 3)
140# define VIP_CNTRL_3_SYNC_DE (1 << 4)
141# define VIP_CNTRL_3_SYNC_HS (1 << 5)
142# define VIP_CNTRL_3_DE_INT (1 << 6)
143# define VIP_CNTRL_3_EDGE (1 << 7)
144#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
145# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
146# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
147# define VIP_CNTRL_4_CCIR656 (1 << 4)
148# define VIP_CNTRL_4_656_ALT (1 << 5)
149# define VIP_CNTRL_4_TST_656 (1 << 6)
150# define VIP_CNTRL_4_TST_PAT (1 << 7)
151#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
152# define VIP_CNTRL_5_CKCASE (1 << 0)
153# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 154#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 155# define MUX_AP_SELECT_I2S 0x64
156# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 157#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 158#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
159# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
160# define MAT_CONTRL_MAT_BP (1 << 2)
161#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
162#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
163#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
164#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
165#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
166#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
167#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
168#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
169#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
170#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
171#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
172#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
173#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
174#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
175#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
176#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
177#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 178#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
179#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 180#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
181#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 182#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
183#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 184#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
185#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
186#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
187#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
188#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
189#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
190#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
191#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
192#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
193#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 194#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
195#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
196#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
197#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 198#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
199#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
200#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
201#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
202#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 203# define TBG_CNTRL_0_TOP_TGL (1 << 0)
204# define TBG_CNTRL_0_TOP_SEL (1 << 1)
205# define TBG_CNTRL_0_DE_EXT (1 << 2)
206# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 207# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
208# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
209# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
210#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 211# define TBG_CNTRL_1_H_TGL (1 << 0)
212# define TBG_CNTRL_1_V_TGL (1 << 1)
213# define TBG_CNTRL_1_TGL_EN (1 << 2)
214# define TBG_CNTRL_1_X_EXT (1 << 3)
215# define TBG_CNTRL_1_H_EXT (1 << 4)
216# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 217# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
218#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
219#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
220# define HVF_CNTRL_0_SM (1 << 7)
221# define HVF_CNTRL_0_RWB (1 << 6)
222# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
223# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
224#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
225# define HVF_CNTRL_1_FOR (1 << 0)
226# define HVF_CNTRL_1_YUVBLK (1 << 1)
227# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
228# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
229# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
230#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 231#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
232# define I2S_FORMAT(x) (((x) & 3) << 0)
233#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 234# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
235# define AIP_CLKSEL_AIP_I2S (1 << 3)
236# define AIP_CLKSEL_FS_ACLK (0 << 0)
237# define AIP_CLKSEL_FS_MCLK (1 << 0)
238# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 239
240/* Page 02h: PLL settings */
241#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
242# define PLL_SERIAL_1_SRL_FDN (1 << 0)
243# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
244# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
245#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 246# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 247# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
248#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
249# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
250# define PLL_SERIAL_3_SRL_DE (1 << 2)
251# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
252#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
253#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
254#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
255#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
256#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
257#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
258#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
259#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
260#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 261# define AUDIO_DIV_SERCLK_1 0
262# define AUDIO_DIV_SERCLK_2 1
263# define AUDIO_DIV_SERCLK_4 2
264# define AUDIO_DIV_SERCLK_8 3
265# define AUDIO_DIV_SERCLK_16 4
266# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 267#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
268# define SEL_CLK_SEL_CLK1 (1 << 0)
269# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
270# define SEL_CLK_ENA_SC_CLK (1 << 3)
271#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
272
273
274/* Page 09h: EDID Control */
275#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
276/* next 127 successive registers are the EDID block */
277#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
278#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
279#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
280#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
281#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
282
283
284/* Page 10h: information frames and packets */
c4c11dd1
RK		 285#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
286#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
287#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
288#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
289#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 290
291
292/* Page 11h: audio settings and content info packets */
293#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
294# define AIP_CNTRL_0_RST_FIFO (1 << 0)
295# define AIP_CNTRL_0_SWAP (1 << 1)
296# define AIP_CNTRL_0_LAYOUT (1 << 2)
297# define AIP_CNTRL_0_ACR_MAN (1 << 5)
298# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 299#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
300# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
301# define CA_I2S_HBR_CHSTAT (1 << 6)
302#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
303#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
304#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
305#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
306#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
307#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
308#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
309#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
310# define CTS_N_K(x) (((x) & 7) << 0)
311# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 312#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
313# define ENC_CNTRL_RST_ENC (1 << 0)
314# define ENC_CNTRL_RST_SEL (1 << 1)
315# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 316#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
317# define DIP_FLAGS_ACR (1 << 0)
318# define DIP_FLAGS_GC (1 << 1)
319#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
320# define DIP_IF_FLAGS_IF1 (1 << 1)
321# define DIP_IF_FLAGS_IF2 (1 << 2)
322# define DIP_IF_FLAGS_IF3 (1 << 3)
323# define DIP_IF_FLAGS_IF4 (1 << 4)
324# define DIP_IF_FLAGS_IF5 (1 << 5)
325#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 326
327
328/* Page 12h: HDCP and OTP */
329#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 330#define REG_TX4 REG(0x12, 0x9b) /* read/write */
331# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 332#define REG_TX33 REG(0x12, 0xb8) /* read/write */
333# define TX33_HDMI (1 << 1)
334
335
336/* Page 13h: Gamut related metadata packets */
337
338
339
340/* CEC registers: (not paged)
341 */
12473b7d
JFM		 342#define REG_CEC_INTSTATUS 0xee /* read */
343# define CEC_INTSTATUS_CEC (1 << 0)
344# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 345#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
346# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
347# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
348# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
349# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 350#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
351#define REG_CEC_RXSHPDINT 0xfd /* read */
ec5d3e83
RK		 352# define CEC_RXSHPDINT_RXSENS BIT(0)
353# define CEC_RXSHPDINT_HPD BIT(1)
e7792ce2
RC		 354#define REG_CEC_RXSHPDLEV 0xfe /* read */
355# define CEC_RXSHPDLEV_RXSENS (1 << 0)
356# define CEC_RXSHPDLEV_HPD (1 << 1)
357
358#define REG_CEC_ENAMODS 0xff /* read/write */
359# define CEC_ENAMODS_DIS_FRO (1 << 6)
360# define CEC_ENAMODS_DIS_CCLK (1 << 5)
361# define CEC_ENAMODS_EN_RXSENS (1 << 2)
362# define CEC_ENAMODS_EN_HDMI (1 << 1)
363# define CEC_ENAMODS_EN_CEC (1 << 0)
364
365
366/* Device versions: */
367#define TDA9989N2 0x0101
368#define TDA19989 0x0201
369#define TDA19989N2 0x0202
370#define TDA19988 0x0301
371
372static void
e66e03ab 373cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
e7792ce2 374{
2f7f730a 375 struct i2c_client *client = priv->cec;
e66e03ab 376 u8 buf[] = {addr, val};
e7792ce2
RC		 377 int ret;
378
704d63f5 379 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 380 if (ret < 0)
381 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
382}
383
e66e03ab
RK		 384static u8
385cec_read(struct tda998x_priv *priv, u8 addr)
e7792ce2 386{
2f7f730a 387 struct i2c_client *client = priv->cec;
e66e03ab 388 u8 val;
e7792ce2
RC		 389 int ret;
390
391 ret = i2c_master_send(client, &addr, sizeof(addr));
392 if (ret < 0)
393 goto fail;
394
395 ret = i2c_master_recv(client, &val, sizeof(val));
396 if (ret < 0)
397 goto fail;
398
399 return val;
400
401fail:
402 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
403 return 0;
404}
405
7d2eadc9 406static int
e66e03ab 407set_page(struct tda998x_priv *priv, u16 reg)
e7792ce2 408{
e7792ce2 409 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 410 struct i2c_client *client = priv->hdmi;
e66e03ab 411 u8 buf[] = {
e7792ce2
RC		 412 REG_CURPAGE, REG2PAGE(reg)
413 };
414 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 415 if (ret < 0) {
288ffc73 416 dev_err(&client->dev, "%s %04x err %d\n", __func__,
704d63f5 417 reg, ret);
7d2eadc9
JFM		 418 return ret;
419 }
e7792ce2
RC		 420
421 priv->current_page = REG2PAGE(reg);
422 }
7d2eadc9 423 return 0;
e7792ce2
RC		 424}
425
426static int
e66e03ab 427reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
e7792ce2 428{
2f7f730a 429 struct i2c_client *client = priv->hdmi;
e66e03ab 430 u8 addr = REG2ADDR(reg);
e7792ce2
RC		 431 int ret;
432
ed9a8426 433 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 434 ret = set_page(priv, reg);
435 if (ret < 0)
ed9a8426 436 goto out;
e7792ce2
RC		 437
438 ret = i2c_master_send(client, &addr, sizeof(addr));
439 if (ret < 0)
440 goto fail;
441
442 ret = i2c_master_recv(client, buf, cnt);
443 if (ret < 0)
444 goto fail;
445
ed9a8426 446 goto out;
e7792ce2
RC		 447
448fail:
449 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
ed9a8426
JFM		 450out:
451 mutex_unlock(&priv->mutex);
e7792ce2
RC		 452 return ret;
453}
454
c4c11dd1 455static void
e66e03ab 456reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
c4c11dd1 457{
2f7f730a 458 struct i2c_client *client = priv->hdmi;
e66e03ab 459 u8 buf[cnt+1];
c4c11dd1
RK		 460 int ret;
461
462 buf[0] = REG2ADDR(reg);
463 memcpy(&buf[1], p, cnt);
464
ed9a8426 465 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 466 ret = set_page(priv, reg);
467 if (ret < 0)
ed9a8426 468 goto out;
c4c11dd1
RK		 469
470 ret = i2c_master_send(client, buf, cnt + 1);
471 if (ret < 0)
472 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 473out:
474 mutex_unlock(&priv->mutex);
c4c11dd1
RK		 475}
476
7d2eadc9 477static int
e66e03ab 478reg_read(struct tda998x_priv *priv, u16 reg)
e7792ce2 479{
e66e03ab 480 u8 val = 0;
7d2eadc9
JFM		 481 int ret;
482
483 ret = reg_read_range(priv, reg, &val, sizeof(val));
484 if (ret < 0)
485 return ret;
e7792ce2
RC		 486 return val;
487}
488
489static void
e66e03ab 490reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 491{
2f7f730a 492 struct i2c_client *client = priv->hdmi;
e66e03ab 493 u8 buf[] = {REG2ADDR(reg), val};
e7792ce2
RC		 494 int ret;
495
ed9a8426 496 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 497 ret = set_page(priv, reg);
498 if (ret < 0)
ed9a8426 499 goto out;
e7792ce2 500
704d63f5 501 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 502 if (ret < 0)
503 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 504out:
505 mutex_unlock(&priv->mutex);
e7792ce2
RC		 506}
507
508static void
e66e03ab 509reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
e7792ce2 510{
2f7f730a 511 struct i2c_client *client = priv->hdmi;
e66e03ab 512 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
e7792ce2
RC		 513 int ret;
514
ed9a8426 515 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 516 ret = set_page(priv, reg);
517 if (ret < 0)
ed9a8426 518 goto out;
e7792ce2 519
704d63f5 520 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 521 if (ret < 0)
522 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 523out:
524 mutex_unlock(&priv->mutex);
e7792ce2
RC		 525}
526
527static void
e66e03ab 528reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 529{
7d2eadc9
JFM		 530 int old_val;
531
532 old_val = reg_read(priv, reg);
533 if (old_val >= 0)
534 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 535}
536
537static void
e66e03ab 538reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 539{
7d2eadc9
JFM		 540 int old_val;
541
542 old_val = reg_read(priv, reg);
543 if (old_val >= 0)
544 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 545}
546
547static void
2f7f730a 548tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 549{
550 /* reset audio and i2c master: */
81b53a16 551 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 552 msleep(50);
81b53a16 553 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 554 msleep(50);
555
556 /* reset transmitter: */
2f7f730a
JFM		 557 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
558 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 559
560 /* PLL registers common configuration */
2f7f730a
JFM		 561 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
562 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
563 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
564 reg_write(priv, REG_SERIALIZER, 0x00);
565 reg_write(priv, REG_BUFFER_OUT, 0x00);
566 reg_write(priv, REG_PLL_SCG1, 0x00);
567 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
568 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
569 reg_write(priv, REG_PLL_SCGN1, 0xfa);
570 reg_write(priv, REG_PLL_SCGN2, 0x00);
571 reg_write(priv, REG_PLL_SCGR1, 0x5b);
572 reg_write(priv, REG_PLL_SCGR2, 0x00);
573 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 574
575 /* Write the default value MUX register */
2f7f730a 576 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 577}
578
0fc6f44d
RK		 579/*
580 * The TDA998x has a problem when trying to read the EDID close to a
581 * HPD assertion: it needs a delay of 100ms to avoid timing out while
582 * trying to read EDID data.
583 *
95a9b686 584 * However, tda998x_connector_get_modes() may be called at any moment
9525c4dd 585 * after tda998x_connector_detect() indicates that we are connected, so
95a9b686 586 * we need to delay probing modes in tda998x_connector_get_modes() after
0fc6f44d
RK		 587 * we have seen a HPD inactive->active transition. This code implements
588 * that delay.
589 */
590static void tda998x_edid_delay_done(unsigned long data)
591{
592 struct tda998x_priv *priv = (struct tda998x_priv *)data;
593
594 priv->edid_delay_active = false;
595 wake_up(&priv->edid_delay_waitq);
596 schedule_work(&priv->detect_work);
597}
598
599static void tda998x_edid_delay_start(struct tda998x_priv *priv)
600{
601 priv->edid_delay_active = true;
602 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
603}
604
605static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
606{
607 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
608}
609
610/*
611 * We need to run the KMS hotplug event helper outside of our threaded
612 * interrupt routine as this can call back into our get_modes method,
613 * which will want to make use of interrupts.
614 */
615static void tda998x_detect_work(struct work_struct *work)
6833d26e 616{
6833d26e 617 struct tda998x_priv *priv =
0fc6f44d 618 container_of(work, struct tda998x_priv, detect_work);
78e401f9 619 struct drm_device *dev = priv->encoder.dev;
6833d26e 620
0fc6f44d
RK		 621 if (dev)
622 drm_kms_helper_hotplug_event(dev);
6833d26e
JFM		 623}
624
12473b7d
JFM		 625/*
626 * only 2 interrupts may occur: screen plug/unplug and EDID read
627 */
628static irqreturn_t tda998x_irq_thread(int irq, void *data)
629{
630 struct tda998x_priv *priv = data;
631 u8 sta, cec, lvl, flag0, flag1, flag2;
f84a97d4 632 bool handled = false;
12473b7d 633
12473b7d
JFM		 634 sta = cec_read(priv, REG_CEC_INTSTATUS);
635 cec = cec_read(priv, REG_CEC_RXSHPDINT);
636 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
637 flag0 = reg_read(priv, REG_INT_FLAGS_0);
638 flag1 = reg_read(priv, REG_INT_FLAGS_1);
639 flag2 = reg_read(priv, REG_INT_FLAGS_2);
640 DRM_DEBUG_DRIVER(
641 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
642 sta, cec, lvl, flag0, flag1, flag2);
ec5d3e83
RK		 643
644 if (cec & CEC_RXSHPDINT_HPD) {
0fc6f44d
RK		 645 if (lvl & CEC_RXSHPDLEV_HPD)
646 tda998x_edid_delay_start(priv);
647 else
648 schedule_work(&priv->detect_work);
649
f84a97d4 650 handled = true;
12473b7d 651 }
ec5d3e83
RK		 652
653 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
654 priv->wq_edid_wait = 0;
655 wake_up(&priv->wq_edid);
656 handled = true;
657 }
658
f84a97d4 659 return IRQ_RETVAL(handled);
12473b7d
JFM		 660}
661
c4c11dd1 662static void
e66e03ab 663tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
96795df1 664 union hdmi_infoframe *frame)
c4c11dd1 665{
96795df1
RK		 666 u8 buf[32];
667 ssize_t len;
668
669 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
670 if (len < 0) {
671 dev_err(&priv->hdmi->dev,
672 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
673 frame->any.type, len);
674 return;
675 }
676
2f7f730a 677 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
96795df1 678 reg_write_range(priv, addr, buf, len);
2f7f730a 679 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 680}
681
95db3b25
JS		 682static int tda998x_write_aif(struct tda998x_priv *priv,
683 struct hdmi_audio_infoframe *cea)
c4c11dd1 684{
96795df1
RK		 685 union hdmi_infoframe frame;
686
95db3b25 687 frame.audio = *cea;
4a6ca1a2 688
96795df1 689 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
95db3b25
JS		 690
691 return 0;
c4c11dd1
RK		 692}
693
694static void
2f7f730a 695tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 696{
96795df1 697 union hdmi_infoframe frame;
8c7a075d 698
96795df1
RK		 699 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
700 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
8c7a075d 701
96795df1 702 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
c4c11dd1
RK		 703}
704
ad975f93
RK		 705/* Audio support */
706
2f7f730a 707static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 708{
709 if (on) {
2f7f730a
JFM		 710 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
711 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
712 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 713 } else {
2f7f730a 714 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 715 }
716}
717
95db3b25 718static int
2f7f730a 719tda998x_configure_audio(struct tda998x_priv *priv,
319e658c 720 struct tda998x_audio_params *params)
c4c11dd1 721{
e66e03ab
RK		 722 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
723 u32 n;
c4c11dd1
RK		 724
725 /* Enable audio ports */
95db3b25 726 reg_write(priv, REG_ENA_AP, params->config);
c4c11dd1
RK		 727
728 /* Set audio input source */
95db3b25 729 switch (params->format) {
c4c11dd1 730 case AFMT_SPDIF:
95db3b25 731 reg_write(priv, REG_ENA_ACLK, 0);
10df1a95
JFM		 732 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
733 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
734 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 735 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 736 break;
737
738 case AFMT_I2S:
95db3b25 739 reg_write(priv, REG_ENA_ACLK, 1);
10df1a95
JFM		 740 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
741 clksel_aip = AIP_CLKSEL_AIP_I2S;
742 clksel_fs = AIP_CLKSEL_FS_ACLK;
95db3b25
JS		 743 switch (params->sample_width) {
744 case 16:
745 cts_n = CTS_N_M(3) | CTS_N_K(1);
746 break;
747 case 18:
748 case 20:
749 case 24:
750 cts_n = CTS_N_M(3) | CTS_N_K(2);
751 break;
752 default:
753 case 32:
754 cts_n = CTS_N_M(3) | CTS_N_K(3);
755 break;
756 }
c4c11dd1 757 break;
3b28802e
DH		 758
759 default:
7e567624 760 dev_err(&priv->hdmi->dev, "Unsupported I2S format\n");
95db3b25 761 return -EINVAL;
c4c11dd1
RK		 762 }
763
2f7f730a 764 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 765 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
766 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 767 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 768
769 /*
770 * Audio input somehow depends on HDMI line rate which is
771 * related to pixclk. Testing showed that modes with pixclk
772 * >100MHz need a larger divider while <40MHz need the default.
773 * There is no detailed info in the datasheet, so we just
774 * assume 100MHz requires larger divider.
775 */
2470fecc 776 adiv = AUDIO_DIV_SERCLK_8;
319e658c 777 if (priv->tmds_clock > 100000)
2470fecc
JFM		 778 adiv++; /* AUDIO_DIV_SERCLK_16 */
779
780 /* S/PDIF asks for a larger divider */
95db3b25 781 if (params->format == AFMT_SPDIF)
2470fecc
JFM		 782 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
783
2f7f730a 784 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 785
786 /*
787 * This is the approximate value of N, which happens to be
788 * the recommended values for non-coherent clocks.
789 */
95db3b25 790 n = 128 * params->sample_rate / 1000;
c4c11dd1
RK		 791
792 /* Write the CTS and N values */
793 buf[0] = 0x44;
794 buf[1] = 0x42;
795 buf[2] = 0x01;
796 buf[3] = n;
797 buf[4] = n >> 8;
798 buf[5] = n >> 16;
2f7f730a 799 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 800
801 /* Set CTS clock reference */
2f7f730a 802 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 803
804 /* Reset CTS generator */
2f7f730a
JFM		 805 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
806 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1 807
95db3b25
JS		 808 /* Write the channel status
809 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
810 * there is a separate register for each I2S wire.
811 */
812 buf[0] = params->status[0];
813 buf[1] = params->status[1];
814 buf[2] = params->status[3];
815 buf[3] = params->status[4];
2f7f730a 816 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 817
2f7f730a 818 tda998x_audio_mute(priv, true);
73d5e253 819 msleep(20);
2f7f730a 820 tda998x_audio_mute(priv, false);
c4c11dd1 821
95db3b25 822 return tda998x_write_aif(priv, &params->cea);
c4c11dd1
RK		 823}
824
ad975f93
RK		 825static int tda998x_audio_hw_params(struct device *dev, void *data,
826 struct hdmi_codec_daifmt *daifmt,
827 struct hdmi_codec_params *params)
828{
829 struct tda998x_priv *priv = dev_get_drvdata(dev);
830 int i, ret;
831 struct tda998x_audio_params audio = {
832 .sample_width = params->sample_width,
833 .sample_rate = params->sample_rate,
834 .cea = params->cea,
835 };
836
837 memcpy(audio.status, params->iec.status,
838 min(sizeof(audio.status), sizeof(params->iec.status)));
839
840 switch (daifmt->fmt) {
841 case HDMI_I2S:
842 if (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
843 daifmt->bit_clk_master || daifmt->frame_clk_master) {
844 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
845 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
846 daifmt->bit_clk_master,
847 daifmt->frame_clk_master);
848 return -EINVAL;
849 }
850 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
851 if (priv->audio_port[i].format == AFMT_I2S)
852 audio.config = priv->audio_port[i].config;
853 audio.format = AFMT_I2S;
854 break;
855 case HDMI_SPDIF:
856 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++)
857 if (priv->audio_port[i].format == AFMT_SPDIF)
858 audio.config = priv->audio_port[i].config;
859 audio.format = AFMT_SPDIF;
860 break;
861 default:
862 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
863 return -EINVAL;
864 }
865
866 if (audio.config == 0) {
867 dev_err(dev, "%s: No audio configutation found\n", __func__);
868 return -EINVAL;
869 }
870
871 mutex_lock(&priv->audio_mutex);
872 if (priv->supports_infoframes && priv->sink_has_audio)
873 ret = tda998x_configure_audio(priv, &audio);
874 else
875 ret = 0;
876
877 if (ret == 0)
878 priv->audio_params = audio;
879 mutex_unlock(&priv->audio_mutex);
880
881 return ret;
882}
883
884static void tda998x_audio_shutdown(struct device *dev, void *data)
885{
886 struct tda998x_priv *priv = dev_get_drvdata(dev);
887
888 mutex_lock(&priv->audio_mutex);
889
890 reg_write(priv, REG_ENA_AP, 0);
891
892 priv->audio_params.format = AFMT_UNUSED;
893
894 mutex_unlock(&priv->audio_mutex);
895}
896
897int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable)
898{
899 struct tda998x_priv *priv = dev_get_drvdata(dev);
900
901 mutex_lock(&priv->audio_mutex);
902
903 tda998x_audio_mute(priv, enable);
904
905 mutex_unlock(&priv->audio_mutex);
906 return 0;
907}
908
909static int tda998x_audio_get_eld(struct device *dev, void *data,
910 uint8_t *buf, size_t len)
911{
912 struct tda998x_priv *priv = dev_get_drvdata(dev);
ad975f93 913
02efac0f
RK		 914 mutex_lock(&priv->audio_mutex);
915 memcpy(buf, priv->connector.eld,
916 min(sizeof(priv->connector.eld), len));
917 mutex_unlock(&priv->audio_mutex);
918
919 return 0;
ad975f93
RK		 920}
921
922static const struct hdmi_codec_ops audio_codec_ops = {
923 .hw_params = tda998x_audio_hw_params,
924 .audio_shutdown = tda998x_audio_shutdown,
925 .digital_mute = tda998x_audio_digital_mute,
926 .get_eld = tda998x_audio_get_eld,
927};
928
929static int tda998x_audio_codec_init(struct tda998x_priv *priv,
930 struct device *dev)
931{
932 struct hdmi_codec_pdata codec_data = {
933 .ops = &audio_codec_ops,
934 .max_i2s_channels = 2,
935 };
936 int i;
937
938 for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) {
939 if (priv->audio_port[i].format == AFMT_I2S &&
940 priv->audio_port[i].config != 0)
941 codec_data.i2s = 1;
942 if (priv->audio_port[i].format == AFMT_SPDIF &&
943 priv->audio_port[i].config != 0)
944 codec_data.spdif = 1;
945 }
946
947 priv->audio_pdev = platform_device_register_data(
948 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
949 &codec_data, sizeof(codec_data));
950
951 return PTR_ERR_OR_ZERO(priv->audio_pdev);
952}
953
25576733
RK		 954/* DRM connector functions */
955
956static int tda998x_connector_dpms(struct drm_connector *connector, int mode)
957{
958 if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC))
959 return drm_atomic_helper_connector_dpms(connector, mode);
960 else
961 return drm_helper_connector_dpms(connector, mode);
962}
963
964static int tda998x_connector_fill_modes(struct drm_connector *connector,
965 uint32_t maxX, uint32_t maxY)
966{
967 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
968 int ret;
969
02efac0f 970 mutex_lock(&priv->audio_mutex);
25576733
RK		 971 ret = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
972
973 if (connector->edid_blob_ptr) {
974 struct edid *edid = (void *)connector->edid_blob_ptr->data;
975
976 priv->sink_has_audio = drm_detect_monitor_audio(edid);
977 } else {
978 priv->sink_has_audio = false;
979 }
02efac0f 980 mutex_unlock(&priv->audio_mutex);
25576733
RK		 981
982 return ret;
983}
984
985static enum drm_connector_status
986tda998x_connector_detect(struct drm_connector *connector, bool force)
987{
988 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
989 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
990
991 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
992 connector_status_disconnected;
993}
994
995static void tda998x_connector_destroy(struct drm_connector *connector)
996{
997 drm_connector_cleanup(connector);
998}
999
1000static const struct drm_connector_funcs tda998x_connector_funcs = {
1001 .dpms = tda998x_connector_dpms,
1002 .reset = drm_atomic_helper_connector_reset,
1003 .fill_modes = tda998x_connector_fill_modes,
1004 .detect = tda998x_connector_detect,
1005 .destroy = tda998x_connector_destroy,
1006 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1007 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1008};
1009
1010static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1011{
1012 struct tda998x_priv *priv = data;
1013 u8 offset, segptr;
1014 int ret, i;
1015
1016 offset = (blk & 1) ? 128 : 0;
1017 segptr = blk / 2;
1018
1019 reg_write(priv, REG_DDC_ADDR, 0xa0);
1020 reg_write(priv, REG_DDC_OFFS, offset);
1021 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1022 reg_write(priv, REG_DDC_SEGM, segptr);
1023
1024 /* enable reading EDID: */
1025 priv->wq_edid_wait = 1;
1026 reg_write(priv, REG_EDID_CTRL, 0x1);
1027
1028 /* flag must be cleared by sw: */
1029 reg_write(priv, REG_EDID_CTRL, 0x0);
1030
1031 /* wait for block read to complete: */
1032 if (priv->hdmi->irq) {
1033 i = wait_event_timeout(priv->wq_edid,
1034 !priv->wq_edid_wait,
1035 msecs_to_jiffies(100));
1036 if (i < 0) {
1037 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1038 return i;
1039 }
1040 } else {
1041 for (i = 100; i > 0; i--) {
1042 msleep(1);
1043 ret = reg_read(priv, REG_INT_FLAGS_2);
1044 if (ret < 0)
1045 return ret;
1046 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1047 break;
1048 }
1049 }
1050
1051 if (i == 0) {
1052 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1053 return -ETIMEDOUT;
1054 }
1055
1056 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1057 if (ret != length) {
1058 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1059 blk, ret);
1060 return ret;
1061 }
1062
1063 return 0;
1064}
1065
1066static int tda998x_connector_get_modes(struct drm_connector *connector)
1067{
1068 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1069 struct edid *edid;
1070 int n;
1071
1072 /*
1073 * If we get killed while waiting for the HPD timeout, return
1074 * no modes found: we are not in a restartable path, so we
1075 * can't handle signals gracefully.
1076 */
1077 if (tda998x_edid_delay_wait(priv))
1078 return 0;
1079
1080 if (priv->rev == TDA19988)
1081 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1082
1083 edid = drm_do_get_edid(connector, read_edid_block, priv);
1084
1085 if (priv->rev == TDA19988)
1086 reg_set(priv, REG_TX4, TX4_PD_RAM);
1087
1088 if (!edid) {
1089 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1090 return 0;
1091 }
1092
1093 drm_mode_connector_update_edid_property(connector, edid);
1094 n = drm_add_edid_modes(connector, edid);
1095 drm_edid_to_eld(connector, edid);
1096
1097 kfree(edid);
1098
1099 return n;
1100}
1101
1102static int tda998x_connector_mode_valid(struct drm_connector *connector,
1103 struct drm_display_mode *mode)
1104{
1105 /* TDA19988 dotclock can go up to 165MHz */
1106 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1107
1108 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1109 return MODE_CLOCK_HIGH;
1110 if (mode->htotal >= BIT(13))
1111 return MODE_BAD_HVALUE;
1112 if (mode->vtotal >= BIT(11))
1113 return MODE_BAD_VVALUE;
1114 return MODE_OK;
1115}
1116
1117static struct drm_encoder *
1118tda998x_connector_best_encoder(struct drm_connector *connector)
1119{
1120 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1121
1122 return &priv->encoder;
1123}
1124
1125static
1126const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1127 .get_modes = tda998x_connector_get_modes,
1128 .mode_valid = tda998x_connector_mode_valid,
1129 .best_encoder = tda998x_connector_best_encoder,
1130};
1131
a2f75662
RK		 1132static int tda998x_connector_init(struct tda998x_priv *priv,
1133 struct drm_device *drm)
1134{
1135 struct drm_connector *connector = &priv->connector;
1136 int ret;
1137
1138 connector->interlace_allowed = 1;
1139
1140 if (priv->hdmi->irq)
1141 connector->polled = DRM_CONNECTOR_POLL_HPD;
1142 else
1143 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1144 DRM_CONNECTOR_POLL_DISCONNECT;
1145
1146 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1147 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1148 DRM_MODE_CONNECTOR_HDMIA);
1149 if (ret)
1150 return ret;
1151
1152 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1153
1154 return 0;
1155}
1156
e7792ce2
RC		 1157/* DRM encoder functions */
1158
9525c4dd 1159static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
e7792ce2 1160{
9525c4dd
RK		 1161 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1162
e7792ce2
RC		 1163 /* we only care about on or off: */
1164 if (mode != DRM_MODE_DPMS_ON)
1165 mode = DRM_MODE_DPMS_OFF;
1166
1167 if (mode == priv->dpms)
1168 return;
1169
1170 switch (mode) {
1171 case DRM_MODE_DPMS_ON:
c4c11dd1 1172 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 1173 reg_write(priv, REG_ENA_VP_0, 0xff);
1174 reg_write(priv, REG_ENA_VP_1, 0xff);
1175 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 1176 /* set muxing after enabling ports: */
2f7f730a
JFM		 1177 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1178 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1179 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 1180 break;
1181 case DRM_MODE_DPMS_OFF:
db6aaf4d 1182 /* disable video ports */
2f7f730a
JFM		 1183 reg_write(priv, REG_ENA_VP_0, 0x00);
1184 reg_write(priv, REG_ENA_VP_1, 0x00);
1185 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 1186 break;
1187 }
1188
1189 priv->dpms = mode;
1190}
1191
e7792ce2 1192static void
9525c4dd 1193tda998x_encoder_mode_set(struct drm_encoder *encoder,
a8f4d4d6
RK		 1194 struct drm_display_mode *mode,
1195 struct drm_display_mode *adjusted_mode)
e7792ce2 1196{
9525c4dd 1197 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
e66e03ab
RK		 1198 u16 ref_pix, ref_line, n_pix, n_line;
1199 u16 hs_pix_s, hs_pix_e;
1200 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1201 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1202 u16 vwin1_line_s, vwin1_line_e;
1203 u16 vwin2_line_s, vwin2_line_e;
1204 u16 de_pix_s, de_pix_e;
1205 u8 reg, div, rep;
e7792ce2 1206
088d61d1
SH		 1207 /*
1208 * Internally TDA998x is using ITU-R BT.656 style sync but
1209 * we get VESA style sync. TDA998x is using a reference pixel
1210 * relative to ITU to sync to the input frame and for output
1211 * sync generation. Currently, we are using reference detection
1212 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1213 * which is position of rising VS with coincident rising HS.
1214 *
1215 * Now there is some issues to take care of:
1216 * - HDMI data islands require sync-before-active
1217 * - TDA998x register values must be > 0 to be enabled
1218 * - REFLINE needs an additional offset of +1
1219 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1220 *
1221 * So we add +1 to all horizontal and vertical register values,
1222 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 1223 */
088d61d1
SH		 1224 n_pix = mode->htotal;
1225 n_line = mode->vtotal;
1226
1227 hs_pix_e = mode->hsync_end - mode->hdisplay;
1228 hs_pix_s = mode->hsync_start - mode->hdisplay;
1229 de_pix_e = mode->htotal;
1230 de_pix_s = mode->htotal - mode->hdisplay;
1231 ref_pix = 3 + hs_pix_s;
1232
179f1aa4
SH		 1233 /*
1234 * Attached LCD controllers may generate broken sync. Allow
1235 * those to adjust the position of the rising VS edge by adding
1236 * HSKEW to ref_pix.
1237 */
1238 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1239 ref_pix += adjusted_mode->hskew;
1240
088d61d1
SH		 1241 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1242 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1243 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1244 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1245 vs1_pix_s = vs1_pix_e = hs_pix_s;
1246 vs1_line_s = mode->vsync_start - mode->vdisplay;
1247 vs1_line_e = vs1_line_s +
1248 mode->vsync_end - mode->vsync_start;
1249 vwin2_line_s = vwin2_line_e = 0;
1250 vs2_pix_s = vs2_pix_e = 0;
1251 vs2_line_s = vs2_line_e = 0;
1252 } else {
1253 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1254 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1255 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1256 vs1_pix_s = vs1_pix_e = hs_pix_s;
1257 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1258 vs1_line_e = vs1_line_s +
1259 (mode->vsync_end - mode->vsync_start)/2;
1260 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1261 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1262 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1263 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1264 vs2_line_e = vs2_line_s +
1265 (mode->vsync_end - mode->vsync_start)/2;
1266 }
e7792ce2
RC		 1267
1268 div = 148500 / mode->clock;
3ae471f7
JFM		 1269 if (div != 0) {
1270 div--;
1271 if (div > 3)
1272 div = 3;
1273 }
e7792ce2 1274
2cae8e02
RK		 1275 mutex_lock(&priv->audio_mutex);
1276
e7792ce2 1277 /* mute the audio FIFO: */
2f7f730a 1278 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 1279
1280 /* set HDMI HDCP mode off: */
81b53a16 1281 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 1282 reg_clear(priv, REG_TX33, TX33_HDMI);
1283 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 1284
e7792ce2 1285 /* no pre-filter or interpolator: */
2f7f730a 1286 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 1287 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 1288 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1289 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 1290 VIP_CNTRL_4_BLC(0));
e7792ce2 1291
2f7f730a 1292 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 1293 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1294 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 1295 reg_write(priv, REG_SERIALIZER, 0);
1296 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 1297
1298 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
1299 rep = 0;
2f7f730a
JFM		 1300 reg_write(priv, REG_RPT_CNTRL, 0);
1301 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 1302 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
1303
2f7f730a 1304 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 1305 PLL_SERIAL_2_SRL_PR(rep));
1306
e7792ce2 1307 /* set color matrix bypass flag: */
81b53a16
JFM		 1308 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1309 MAT_CONTRL_MAT_SC(1));
e7792ce2
RC		 1310
1311 /* set BIAS tmds value: */
2f7f730a 1312 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 1313
088d61d1
SH		 1314 /*
1315 * Sync on rising HSYNC/VSYNC
1316 */
81b53a16 1317 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 1318
1319 /*
1320 * TDA19988 requires high-active sync at input stage,
1321 * so invert low-active sync provided by master encoder here
1322 */
1323 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 1324 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 1325 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 1326 reg |= VIP_CNTRL_3_V_TGL;
1327 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 1328
1329 reg_write(priv, REG_VIDFORMAT, 0x00);
1330 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1331 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1332 reg_write16(priv, REG_NPIX_MSB, n_pix);
1333 reg_write16(priv, REG_NLINE_MSB, n_line);
1334 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1335 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1336 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1337 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1338 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1339 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1340 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1341 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1342 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1343 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1344 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1345 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1346 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1347 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1348 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1349 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 1350
1351 if (priv->rev == TDA19988) {
1352 /* let incoming pixels fill the active space (if any) */
2f7f730a 1353 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 1354 }
1355
81b53a16
JFM		 1356 /*
1357 * Always generate sync polarity relative to input sync and
1358 * revert input stage toggled sync at output stage
1359 */
1360 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1361 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1362 reg |= TBG_CNTRL_1_H_TGL;
1363 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1364 reg |= TBG_CNTRL_1_V_TGL;
1365 reg_write(priv, REG_TBG_CNTRL_1, reg);
1366
e7792ce2 1367 /* must be last register set: */
81b53a16 1368 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1 1369
319e658c
RK		 1370 priv->tmds_clock = adjusted_mode->clock;
1371
896a4130
RK		 1372 /* CEA-861B section 6 says that:
1373 * CEA version 1 (CEA-861) has no support for infoframes.
1374 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1375 * and optional basic audio.
1376 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1377 * and optional digital audio, with audio infoframes.
1378 *
1379 * Since we only support generation of version 2 AVI infoframes,
1380 * ignore CEA version 2 and below (iow, behave as if we're a
1381 * CEA-861 source.)
1382 */
1383 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1384
1385 if (priv->supports_infoframes) {
c4c11dd1 1386 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1387 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1388 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1389 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1390 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1391
2f7f730a 1392 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1 1393
8f3f21f6
RK		 1394 if (priv->audio_params.format != AFMT_UNUSED &&
1395 priv->sink_has_audio)
319e658c 1396 tda998x_configure_audio(priv, &priv->audio_params);
c4c11dd1 1397 }
319e658c
RK		 1398
1399 mutex_unlock(&priv->audio_mutex);
e7792ce2
RC		 1400}
1401
a8f4d4d6 1402static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1403{
12473b7d
JFM		 1404 /* disable all IRQs and free the IRQ handler */
1405 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1406 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
0fc6f44d 1407
7e567624
JS		 1408 if (priv->audio_pdev)
1409 platform_device_unregister(priv->audio_pdev);
1410
0fc6f44d 1411 if (priv->hdmi->irq)
12473b7d 1412 free_irq(priv->hdmi->irq, priv);
0fc6f44d
RK		 1413
1414 del_timer_sync(&priv->edid_delay_timer);
1415 cancel_work_sync(&priv->detect_work);
12473b7d 1416
89fc8686 1417 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1418}
1419
e7792ce2
RC		 1420/* I2C driver functions */
1421
7e567624
JS		 1422static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1423 struct device_node *np)
1424{
1425 const u32 *port_data;
1426 u32 size;
1427 int i;
1428
1429 port_data = of_get_property(np, "audio-ports", &size);
1430 if (!port_data)
1431 return 0;
1432
1433 size /= sizeof(u32);
1434 if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) {
1435 dev_err(&priv->hdmi->dev,
1436 "Bad number of elements in audio-ports dt-property\n");
1437 return -EINVAL;
1438 }
1439
1440 size /= 2;
1441
1442 for (i = 0; i < size; i++) {
1443 u8 afmt = be32_to_cpup(&port_data[2*i]);
1444 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1445
1446 if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) {
1447 dev_err(&priv->hdmi->dev,
1448 "Bad audio format %u\n", afmt);
1449 return -EINVAL;
1450 }
1451
1452 priv->audio_port[i].format = afmt;
1453 priv->audio_port[i].config = ena_ap;
1454 }
1455
1456 if (priv->audio_port[0].format == priv->audio_port[1].format) {
1457 dev_err(&priv->hdmi->dev,
1458 "There can only be on I2S port and one SPDIF port\n");
1459 return -EINVAL;
1460 }
1461 return 0;
1462}
1463
a8f4d4d6 1464static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1465{
0d44ea19
JFM		 1466 struct device_node *np = client->dev.of_node;
1467 u32 video;
fb7544d7 1468 int rev_lo, rev_hi, ret;
cfe38757 1469 unsigned short cec_addr;
e7792ce2 1470
ba300c17
RK		 1471 mutex_init(&priv->audio_mutex); /* Protect access from audio thread */
1472
5e74c22c
RK		 1473 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1474 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1475 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1476
2eb4c7b1 1477 priv->current_page = 0xff;
2f7f730a 1478 priv->hdmi = client;
cfe38757
AJ		 1479 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1480 cec_addr = 0x34 + (client->addr & 0x03);
1481 priv->cec = i2c_new_dummy(client->adapter, cec_addr);
a8f4d4d6 1482 if (!priv->cec)
6ae668cc 1483 return -ENODEV;
12473b7d 1484
e7792ce2
RC		 1485 priv->dpms = DRM_MODE_DPMS_OFF;
1486
ed9a8426 1487 mutex_init(&priv->mutex); /* protect the page access */
0fc6f44d
RK		 1488 init_waitqueue_head(&priv->edid_delay_waitq);
1489 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1490 (unsigned long)priv);
1491 INIT_WORK(&priv->detect_work, tda998x_detect_work);
ed9a8426 1492
e7792ce2 1493 /* wake up the device: */
2f7f730a 1494 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1495 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1496
2f7f730a 1497 tda998x_reset(priv);
e7792ce2
RC		 1498
1499 /* read version: */
fb7544d7
RK		 1500 rev_lo = reg_read(priv, REG_VERSION_LSB);
1501 rev_hi = reg_read(priv, REG_VERSION_MSB);
1502 if (rev_lo < 0 || rev_hi < 0) {
1503 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1504 goto fail;
fb7544d7
RK		 1505 }
1506
1507 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1508
1509 /* mask off feature bits: */
1510 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1511
1512 switch (priv->rev) {
b728fab7
JFM		 1513 case TDA9989N2:
1514 dev_info(&client->dev, "found TDA9989 n2");
1515 break;
1516 case TDA19989:
1517 dev_info(&client->dev, "found TDA19989");
1518 break;
1519 case TDA19989N2:
1520 dev_info(&client->dev, "found TDA19989 n2");
1521 break;
1522 case TDA19988:
1523 dev_info(&client->dev, "found TDA19988");
1524 break;
e7792ce2 1525 default:
b728fab7
JFM		 1526 dev_err(&client->dev, "found unsupported device: %04x\n",
1527 priv->rev);
e7792ce2
RC		 1528 goto fail;
1529 }
1530
1531 /* after reset, enable DDC: */
2f7f730a 1532 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1533
1534 /* set clock on DDC channel: */
2f7f730a 1535 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1536
1537 /* if necessary, disable multi-master: */
1538 if (priv->rev == TDA19989)
2f7f730a 1539 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1540
2f7f730a 1541 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1542 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1543
12473b7d
JFM		 1544 /* initialize the optional IRQ */
1545 if (client->irq) {
1546 int irqf_trigger;
1547
6833d26e 1548 /* init read EDID waitqueue and HDP work */
12473b7d
JFM		 1549 init_waitqueue_head(&priv->wq_edid);
1550
1551 /* clear pending interrupts */
1552 reg_read(priv, REG_INT_FLAGS_0);
1553 reg_read(priv, REG_INT_FLAGS_1);
1554 reg_read(priv, REG_INT_FLAGS_2);
1555
1556 irqf_trigger =
1557 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1558 ret = request_threaded_irq(client->irq, NULL,
1559 tda998x_irq_thread,
1560 irqf_trigger | IRQF_ONESHOT,
1561 "tda998x", priv);
1562 if (ret) {
1563 dev_err(&client->dev,
1564 "failed to request IRQ#%u: %d\n",
1565 client->irq, ret);
1566 goto fail;
1567 }
1568
1569 /* enable HPD irq */
1570 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1571 }
1572
e4782627
JFM		 1573 /* enable EDID read irq: */
1574 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1575
0d44ea19
JFM		 1576 if (!np)
1577 return 0; /* non-DT */
1578
7e567624 1579 /* get the device tree parameters */
0d44ea19
JFM		 1580 ret = of_property_read_u32(np, "video-ports", &video);
1581 if (ret == 0) {
1582 priv->vip_cntrl_0 = video >> 16;
1583 priv->vip_cntrl_1 = video >> 8;
1584 priv->vip_cntrl_2 = video;
1585 }
1586
7e567624
JS		 1587 ret = tda998x_get_audio_ports(priv, np);
1588 if (ret)
1589 goto fail;
1590
1591 if (priv->audio_port[0].format != AFMT_UNUSED)
1592 tda998x_audio_codec_init(priv, &client->dev);
1593
1594 return 0;
e7792ce2
RC		 1595fail:
1596 /* if encoder_init fails, the encoder slave is never registered,
1597 * so cleanup here:
1598 */
1599 if (priv->cec)
1600 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1601 return -ENXIO;
1602}
1603
c707c361
RK		 1604static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1605{
9525c4dd 1606 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
c707c361
RK		 1607}
1608
1609static void tda998x_encoder_commit(struct drm_encoder *encoder)
1610{
9525c4dd 1611 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
c707c361
RK		 1612}
1613
1614static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
9525c4dd 1615 .dpms = tda998x_encoder_dpms,
c707c361
RK		 1616 .prepare = tda998x_encoder_prepare,
1617 .commit = tda998x_encoder_commit,
9525c4dd 1618 .mode_set = tda998x_encoder_mode_set,
c707c361
RK		 1619};
1620
1621static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1622{
a3584f60 1623 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
c707c361 1624
a3584f60 1625 tda998x_destroy(priv);
c707c361
RK		 1626 drm_encoder_cleanup(encoder);
1627}
1628
1629static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1630 .destroy = tda998x_encoder_destroy,
1631};
1632
94579273
RK		 1633static void tda998x_set_config(struct tda998x_priv *priv,
1634 const struct tda998x_encoder_params *p)
1635{
1636 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1637 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1638 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1639 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1640 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1641 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1642 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1643 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1644 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1645 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1646 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1647 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1648
1649 priv->audio_params = p->audio_params;
1650}
1651
c707c361
RK		 1652static int tda998x_bind(struct device *dev, struct device *master, void *data)
1653{
1654 struct tda998x_encoder_params *params = dev->platform_data;
1655 struct i2c_client *client = to_i2c_client(dev);
1656 struct drm_device *drm = data;
a3584f60 1657 struct tda998x_priv *priv;
e66e03ab 1658 u32 crtcs = 0;
c707c361
RK		 1659 int ret;
1660
1661 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1662 if (!priv)
1663 return -ENOMEM;
1664
1665 dev_set_drvdata(dev, priv);
1666
5dbcf319
RK		 1667 if (dev->of_node)
1668 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1669
1670 /* If no CRTCs were found, fall back to our old behaviour */
1671 if (crtcs == 0) {
1672 dev_warn(dev, "Falling back to first CRTC\n");
1673 crtcs = 1 << 0;
1674 }
1675
a3584f60 1676 priv->encoder.possible_crtcs = crtcs;
c707c361 1677
a3584f60 1678 ret = tda998x_create(client, priv);
c707c361
RK		 1679 if (ret)
1680 return ret;
1681
1682 if (!dev->of_node && params)
94579273 1683 tda998x_set_config(priv, params);
c707c361 1684
a3584f60
RK		 1685 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1686 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
13a3d91f 1687 DRM_MODE_ENCODER_TMDS, NULL);
c707c361
RK		 1688 if (ret)
1689 goto err_encoder;
1690
a2f75662 1691 ret = tda998x_connector_init(priv, drm);
c707c361
RK		 1692 if (ret)
1693 goto err_connector;
1694
c707c361
RK		 1695 return 0;
1696
c707c361 1697err_connector:
a3584f60 1698 drm_encoder_cleanup(&priv->encoder);
c707c361 1699err_encoder:
a3584f60 1700 tda998x_destroy(priv);
c707c361
RK		 1701 return ret;
1702}
1703
1704static void tda998x_unbind(struct device *dev, struct device *master,
1705 void *data)
1706{
a3584f60 1707 struct tda998x_priv *priv = dev_get_drvdata(dev);
c707c361 1708
a3584f60
RK		 1709 drm_connector_cleanup(&priv->connector);
1710 drm_encoder_cleanup(&priv->encoder);
1711 tda998x_destroy(priv);
c707c361
RK		 1712}
1713
1714static const struct component_ops tda998x_ops = {
1715 .bind = tda998x_bind,
1716 .unbind = tda998x_unbind,
1717};
1718
1719static int
1720tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1721{
1722 return component_add(&client->dev, &tda998x_ops);
1723}
1724
1725static int tda998x_remove(struct i2c_client *client)
1726{
1727 component_del(&client->dev, &tda998x_ops);
1728 return 0;
1729}
1730
0d44ea19
JFM		 1731#ifdef CONFIG_OF
1732static const struct of_device_id tda998x_dt_ids[] = {
1733 { .compatible = "nxp,tda998x", },
1734 { }
1735};
1736MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1737#endif
1738
e7792ce2
RC		 1739static struct i2c_device_id tda998x_ids[] = {
1740 { "tda998x", 0 },
1741 { }
1742};
1743MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1744
3d58e318
RK		 1745static struct i2c_driver tda998x_driver = {
1746 .probe = tda998x_probe,
1747 .remove = tda998x_remove,
1748 .driver = {
1749 .name = "tda998x",
1750 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2 1751 },
3d58e318 1752 .id_table = tda998x_ids,
e7792ce2
RC		 1753};
1754
3d58e318 1755module_i2c_driver(tda998x_driver);
e7792ce2
RC		 1756
1757MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1758MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1759MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)